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Diffstat (limited to 'drivers/staging/octeon/cvmx-wqe.h')
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1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | /** | ||
29 | * | ||
30 | * This header file defines the work queue entry (wqe) data structure. | ||
31 | * Since this is a commonly used structure that depends on structures | ||
32 | * from several hardware blocks, those definitions have been placed | ||
33 | * in this file to create a single point of definition of the wqe | ||
34 | * format. | ||
35 | * Data structures are still named according to the block that they | ||
36 | * relate to. | ||
37 | * | ||
38 | */ | ||
39 | |||
40 | #ifndef __CVMX_WQE_H__ | ||
41 | #define __CVMX_WQE_H__ | ||
42 | |||
43 | #include "cvmx-packet.h" | ||
44 | |||
45 | |||
46 | #define OCT_TAG_TYPE_STRING(x) \ | ||
47 | (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \ | ||
48 | (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \ | ||
49 | (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \ | ||
50 | "NULL_NULL"))) | ||
51 | |||
52 | /** | ||
53 | * HW decode / err_code in work queue entry | ||
54 | */ | ||
55 | typedef union { | ||
56 | uint64_t u64; | ||
57 | |||
58 | /* Use this struct if the hardware determines that the packet is IP */ | ||
59 | struct { | ||
60 | /* HW sets this to the number of buffers used by this packet */ | ||
61 | uint64_t bufs:8; | ||
62 | /* HW sets to the number of L2 bytes prior to the IP */ | ||
63 | uint64_t ip_offset:8; | ||
64 | /* set to 1 if we found DSA/VLAN in the L2 */ | ||
65 | uint64_t vlan_valid:1; | ||
66 | /* Set to 1 if the DSA/VLAN tag is stacked */ | ||
67 | uint64_t vlan_stacked:1; | ||
68 | uint64_t unassigned:1; | ||
69 | /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */ | ||
70 | uint64_t vlan_cfi:1; | ||
71 | /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */ | ||
72 | uint64_t vlan_id:12; | ||
73 | /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */ | ||
74 | uint64_t pr:4; | ||
75 | uint64_t unassigned2:8; | ||
76 | /* the packet needs to be decompressed */ | ||
77 | uint64_t dec_ipcomp:1; | ||
78 | /* the packet is either TCP or UDP */ | ||
79 | uint64_t tcp_or_udp:1; | ||
80 | /* the packet needs to be decrypted (ESP or AH) */ | ||
81 | uint64_t dec_ipsec:1; | ||
82 | /* the packet is IPv6 */ | ||
83 | uint64_t is_v6:1; | ||
84 | |||
85 | /* | ||
86 | * (rcv_error, not_IP, IP_exc, is_frag, L4_error, | ||
87 | * software, etc.). | ||
88 | */ | ||
89 | |||
90 | /* | ||
91 | * reserved for software use, hardware will clear on | ||
92 | * packet creation. | ||
93 | */ | ||
94 | uint64_t software:1; | ||
95 | /* exceptional conditions below */ | ||
96 | /* the receive interface hardware detected an L4 error | ||
97 | * (only applies if !is_frag) (only applies if | ||
98 | * !rcv_error && !not_IP && !IP_exc && !is_frag) | ||
99 | * failure indicated in err_code below, decode: | ||
100 | * | ||
101 | * - 1 = Malformed L4 | ||
102 | * - 2 = L4 Checksum Error: the L4 checksum value is | ||
103 | * - 3 = UDP Length Error: The UDP length field would | ||
104 | * make the UDP data longer than what remains in | ||
105 | * the IP packet (as defined by the IP header | ||
106 | * length field). | ||
107 | * - 4 = Bad L4 Port: either the source or destination | ||
108 | * TCP/UDP port is 0. | ||
109 | * - 8 = TCP FIN Only: the packet is TCP and only the | ||
110 | * FIN flag set. | ||
111 | * - 9 = TCP No Flags: the packet is TCP and no flags | ||
112 | * are set. | ||
113 | * - 10 = TCP FIN RST: the packet is TCP and both FIN | ||
114 | * and RST are set. | ||
115 | * - 11 = TCP SYN URG: the packet is TCP and both SYN | ||
116 | * and URG are set. | ||
117 | * - 12 = TCP SYN RST: the packet is TCP and both SYN | ||
118 | * and RST are set. | ||
119 | * - 13 = TCP SYN FIN: the packet is TCP and both SYN | ||
120 | * and FIN are set. | ||
121 | */ | ||
122 | uint64_t L4_error:1; | ||
123 | /* set if the packet is a fragment */ | ||
124 | uint64_t is_frag:1; | ||
125 | /* the receive interface hardware detected an IP error | ||
126 | * / exception (only applies if !rcv_error && !not_IP) | ||
127 | * failure indicated in err_code below, decode: | ||
128 | * | ||
129 | * - 1 = Not IP: the IP version field is neither 4 nor | ||
130 | * 6. | ||
131 | * - 2 = IPv4 Header Checksum Error: the IPv4 header | ||
132 | * has a checksum violation. | ||
133 | * - 3 = IP Malformed Header: the packet is not long | ||
134 | * enough to contain the IP header. | ||
135 | * - 4 = IP Malformed: the packet is not long enough | ||
136 | * to contain the bytes indicated by the IP | ||
137 | * header. Pad is allowed. | ||
138 | * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 | ||
139 | * Hop Count field are zero. | ||
140 | * - 6 = IP Options | ||
141 | */ | ||
142 | uint64_t IP_exc:1; | ||
143 | /* | ||
144 | * Set if the hardware determined that the packet is a | ||
145 | * broadcast. | ||
146 | */ | ||
147 | uint64_t is_bcast:1; | ||
148 | /* | ||
149 | * St if the hardware determined that the packet is a | ||
150 | * multi-cast. | ||
151 | */ | ||
152 | uint64_t is_mcast:1; | ||
153 | /* | ||
154 | * Set if the packet may not be IP (must be zero in | ||
155 | * this case). | ||
156 | */ | ||
157 | uint64_t not_IP:1; | ||
158 | /* | ||
159 | * The receive interface hardware detected a receive | ||
160 | * error (must be zero in this case). | ||
161 | */ | ||
162 | uint64_t rcv_error:1; | ||
163 | /* lower err_code = first-level descriptor of the | ||
164 | * work */ | ||
165 | /* zero for packet submitted by hardware that isn't on | ||
166 | * the slow path */ | ||
167 | /* type is cvmx_pip_err_t */ | ||
168 | uint64_t err_code:8; | ||
169 | } s; | ||
170 | |||
171 | /* use this to get at the 16 vlan bits */ | ||
172 | struct { | ||
173 | uint64_t unused1:16; | ||
174 | uint64_t vlan:16; | ||
175 | uint64_t unused2:32; | ||
176 | } svlan; | ||
177 | |||
178 | /* | ||
179 | * use this struct if the hardware could not determine that | ||
180 | * the packet is ip. | ||
181 | */ | ||
182 | struct { | ||
183 | /* | ||
184 | * HW sets this to the number of buffers used by this | ||
185 | * packet. | ||
186 | */ | ||
187 | uint64_t bufs:8; | ||
188 | uint64_t unused:8; | ||
189 | /* set to 1 if we found DSA/VLAN in the L2 */ | ||
190 | uint64_t vlan_valid:1; | ||
191 | /* Set to 1 if the DSA/VLAN tag is stacked */ | ||
192 | uint64_t vlan_stacked:1; | ||
193 | uint64_t unassigned:1; | ||
194 | /* | ||
195 | * HW sets to the DSA/VLAN CFI flag (valid when | ||
196 | * vlan_valid) | ||
197 | */ | ||
198 | uint64_t vlan_cfi:1; | ||
199 | /* | ||
200 | * HW sets to the DSA/VLAN_ID field (valid when | ||
201 | * vlan_valid). | ||
202 | */ | ||
203 | uint64_t vlan_id:12; | ||
204 | /* | ||
205 | * Ring Identifier (if PCIe). Requires | ||
206 | * PIP_GBL_CTL[RING_EN]=1 | ||
207 | */ | ||
208 | uint64_t pr:4; | ||
209 | uint64_t unassigned2:12; | ||
210 | /* | ||
211 | * reserved for software use, hardware will clear on | ||
212 | * packet creation. | ||
213 | */ | ||
214 | uint64_t software:1; | ||
215 | uint64_t unassigned3:1; | ||
216 | /* | ||
217 | * set if the hardware determined that the packet is | ||
218 | * rarp. | ||
219 | */ | ||
220 | uint64_t is_rarp:1; | ||
221 | /* | ||
222 | * set if the hardware determined that the packet is | ||
223 | * arp | ||
224 | */ | ||
225 | uint64_t is_arp:1; | ||
226 | /* | ||
227 | * set if the hardware determined that the packet is a | ||
228 | * broadcast. | ||
229 | */ | ||
230 | uint64_t is_bcast:1; | ||
231 | /* | ||
232 | * set if the hardware determined that the packet is a | ||
233 | * multi-cast | ||
234 | */ | ||
235 | uint64_t is_mcast:1; | ||
236 | /* | ||
237 | * set if the packet may not be IP (must be one in | ||
238 | * this case) | ||
239 | */ | ||
240 | uint64_t not_IP:1; | ||
241 | /* The receive interface hardware detected a receive | ||
242 | * error. Failure indicated in err_code below, | ||
243 | * decode: | ||
244 | * | ||
245 | * - 1 = partial error: a packet was partially | ||
246 | * received, but internal buffering / bandwidth | ||
247 | * was not adequate to receive the entire | ||
248 | * packet. | ||
249 | * - 2 = jabber error: the RGMII packet was too large | ||
250 | * and is truncated. | ||
251 | * - 3 = overrun error: the RGMII packet is longer | ||
252 | * than allowed and had an FCS error. | ||
253 | * - 4 = oversize error: the RGMII packet is longer | ||
254 | * than allowed. | ||
255 | * - 5 = alignment error: the RGMII packet is not an | ||
256 | * integer number of bytes | ||
257 | * and had an FCS error (100M and 10M only). | ||
258 | * - 6 = fragment error: the RGMII packet is shorter | ||
259 | * than allowed and had an FCS error. | ||
260 | * - 7 = GMX FCS error: the RGMII packet had an FCS | ||
261 | * error. | ||
262 | * - 8 = undersize error: the RGMII packet is shorter | ||
263 | * than allowed. | ||
264 | * - 9 = extend error: the RGMII packet had an extend | ||
265 | * error. | ||
266 | * - 10 = length mismatch error: the RGMII packet had | ||
267 | * a length that did not match the length field | ||
268 | * in the L2 HDR. | ||
269 | * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII | ||
270 | * packet had one or more data reception errors | ||
271 | * (RXERR) or the SPI4 packet had one or more | ||
272 | * DIP4 errors. | ||
273 | * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII | ||
274 | * packet was not large enough to cover the | ||
275 | * skipped bytes or the SPI4 packet was | ||
276 | * terminated with an About EOPS. | ||
277 | * - 13 = RGMII nibble error/SPI4 Port NXA Error: the | ||
278 | * RGMII packet had a studder error (data not | ||
279 | * repeated - 10/100M only) or the SPI4 packet | ||
280 | * was sent to an NXA. | ||
281 | * - 16 = FCS error: a SPI4.2 packet had an FCS error. | ||
282 | * - 17 = Skip error: a packet was not large enough to | ||
283 | * cover the skipped bytes. | ||
284 | * - 18 = L2 header malformed: the packet is not long | ||
285 | * enough to contain the L2. | ||
286 | */ | ||
287 | |||
288 | uint64_t rcv_error:1; | ||
289 | /* | ||
290 | * lower err_code = first-level descriptor of the | ||
291 | * work | ||
292 | */ | ||
293 | /* | ||
294 | * zero for packet submitted by hardware that isn't on | ||
295 | * the slow path | ||
296 | */ | ||
297 | /* type is cvmx_pip_err_t (union, so can't use directly */ | ||
298 | uint64_t err_code:8; | ||
299 | } snoip; | ||
300 | |||
301 | } cvmx_pip_wqe_word2; | ||
302 | |||
303 | /** | ||
304 | * Work queue entry format | ||
305 | * | ||
306 | * must be 8-byte aligned | ||
307 | */ | ||
308 | typedef struct { | ||
309 | |||
310 | /***************************************************************** | ||
311 | * WORD 0 | ||
312 | * HW WRITE: the following 64 bits are filled by HW when a packet arrives | ||
313 | */ | ||
314 | |||
315 | /** | ||
316 | * raw chksum result generated by the HW | ||
317 | */ | ||
318 | uint16_t hw_chksum; | ||
319 | /** | ||
320 | * Field unused by hardware - available for software | ||
321 | */ | ||
322 | uint8_t unused; | ||
323 | /** | ||
324 | * Next pointer used by hardware for list maintenance. | ||
325 | * May be written/read by HW before the work queue | ||
326 | * entry is scheduled to a PP | ||
327 | * (Only 36 bits used in Octeon 1) | ||
328 | */ | ||
329 | uint64_t next_ptr:40; | ||
330 | |||
331 | /***************************************************************** | ||
332 | * WORD 1 | ||
333 | * HW WRITE: the following 64 bits are filled by HW when a packet arrives | ||
334 | */ | ||
335 | |||
336 | /** | ||
337 | * HW sets to the total number of bytes in the packet | ||
338 | */ | ||
339 | uint64_t len:16; | ||
340 | /** | ||
341 | * HW sets this to input physical port | ||
342 | */ | ||
343 | uint64_t ipprt:6; | ||
344 | |||
345 | /** | ||
346 | * HW sets this to what it thought the priority of the input packet was | ||
347 | */ | ||
348 | uint64_t qos:3; | ||
349 | |||
350 | /** | ||
351 | * the group that the work queue entry will be scheduled to | ||
352 | */ | ||
353 | uint64_t grp:4; | ||
354 | /** | ||
355 | * the type of the tag (ORDERED, ATOMIC, NULL) | ||
356 | */ | ||
357 | uint64_t tag_type:3; | ||
358 | /** | ||
359 | * the synchronization/ordering tag | ||
360 | */ | ||
361 | uint64_t tag:32; | ||
362 | |||
363 | /** | ||
364 | * WORD 2 HW WRITE: the following 64-bits are filled in by | ||
365 | * hardware when a packet arrives This indicates a variety of | ||
366 | * status and error conditions. | ||
367 | */ | ||
368 | cvmx_pip_wqe_word2 word2; | ||
369 | |||
370 | /** | ||
371 | * Pointer to the first segment of the packet. | ||
372 | */ | ||
373 | union cvmx_buf_ptr packet_ptr; | ||
374 | |||
375 | /** | ||
376 | * HW WRITE: octeon will fill in a programmable amount from the | ||
377 | * packet, up to (at most, but perhaps less) the amount | ||
378 | * needed to fill the work queue entry to 128 bytes | ||
379 | * | ||
380 | * If the packet is recognized to be IP, the hardware starts | ||
381 | * (except that the IPv4 header is padded for appropriate | ||
382 | * alignment) writing here where the IP header starts. If the | ||
383 | * packet is not recognized to be IP, the hardware starts | ||
384 | * writing the beginning of the packet here. | ||
385 | */ | ||
386 | uint8_t packet_data[96]; | ||
387 | |||
388 | /** | ||
389 | * If desired, SW can make the work Q entry any length. For the | ||
390 | * purposes of discussion here, Assume 128B always, as this is all that | ||
391 | * the hardware deals with. | ||
392 | * | ||
393 | */ | ||
394 | |||
395 | } CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t; | ||
396 | |||
397 | #endif /* __CVMX_WQE_H__ */ | ||