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-rw-r--r--drivers/staging/gma500/psb_irq.c627
1 files changed, 0 insertions, 627 deletions
diff --git a/drivers/staging/gma500/psb_irq.c b/drivers/staging/gma500/psb_irq.c
deleted file mode 100644
index 36dd63044b0..00000000000
--- a/drivers/staging/gma500/psb_irq.c
+++ /dev/null
@@ -1,627 +0,0 @@
1/**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
20 *
21 **************************************************************************/
22/*
23 */
24
25#include <drm/drmP.h>
26#include "psb_drv.h"
27#include "psb_reg.h"
28#include "psb_intel_reg.h"
29#include "power.h"
30#include "mdfld_output.h"
31
32/*
33 * inline functions
34 */
35
36static inline u32
37psb_pipestat(int pipe)
38{
39 if (pipe == 0)
40 return PIPEASTAT;
41 if (pipe == 1)
42 return PIPEBSTAT;
43 if (pipe == 2)
44 return PIPECSTAT;
45 BUG();
46}
47
48static inline u32
49mid_pipe_event(int pipe)
50{
51 if (pipe == 0)
52 return _PSB_PIPEA_EVENT_FLAG;
53 if (pipe == 1)
54 return _MDFLD_PIPEB_EVENT_FLAG;
55 if (pipe == 2)
56 return _MDFLD_PIPEC_EVENT_FLAG;
57 BUG();
58}
59
60static inline u32
61mid_pipe_vsync(int pipe)
62{
63 if (pipe == 0)
64 return _PSB_VSYNC_PIPEA_FLAG;
65 if (pipe == 1)
66 return _PSB_VSYNC_PIPEB_FLAG;
67 if (pipe == 2)
68 return _MDFLD_PIPEC_VBLANK_FLAG;
69 BUG();
70}
71
72static inline u32
73mid_pipeconf(int pipe)
74{
75 if (pipe == 0)
76 return PIPEACONF;
77 if (pipe == 1)
78 return PIPEBCONF;
79 if (pipe == 2)
80 return PIPECCONF;
81 BUG();
82}
83
84void
85psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
86{
87 if ((dev_priv->pipestat[pipe] & mask) != mask) {
88 u32 reg = psb_pipestat(pipe);
89 dev_priv->pipestat[pipe] |= mask;
90 /* Enable the interrupt, clear any pending status */
91 if (gma_power_begin(dev_priv->dev, false)) {
92 u32 writeVal = PSB_RVDC32(reg);
93 writeVal |= (mask | (mask >> 16));
94 PSB_WVDC32(writeVal, reg);
95 (void) PSB_RVDC32(reg);
96 gma_power_end(dev_priv->dev);
97 }
98 }
99}
100
101void
102psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
103{
104 if ((dev_priv->pipestat[pipe] & mask) != 0) {
105 u32 reg = psb_pipestat(pipe);
106 dev_priv->pipestat[pipe] &= ~mask;
107 if (gma_power_begin(dev_priv->dev, false)) {
108 u32 writeVal = PSB_RVDC32(reg);
109 writeVal &= ~mask;
110 PSB_WVDC32(writeVal, reg);
111 (void) PSB_RVDC32(reg);
112 gma_power_end(dev_priv->dev);
113 }
114 }
115}
116
117void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
118{
119 if (gma_power_begin(dev_priv->dev, false)) {
120 u32 pipe_event = mid_pipe_event(pipe);
121 dev_priv->vdc_irq_mask |= pipe_event;
122 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
123 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
124 gma_power_end(dev_priv->dev);
125 }
126}
127
128void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
129{
130 if (dev_priv->pipestat[pipe] == 0) {
131 if (gma_power_begin(dev_priv->dev, false)) {
132 u32 pipe_event = mid_pipe_event(pipe);
133 dev_priv->vdc_irq_mask &= ~pipe_event;
134 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
135 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
136 gma_power_end(dev_priv->dev);
137 }
138 }
139}
140
141/**
142 * Display controller interrupt handler for pipe event.
143 *
144 */
145static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
146{
147 struct drm_psb_private *dev_priv =
148 (struct drm_psb_private *) dev->dev_private;
149
150 uint32_t pipe_stat_val = 0;
151 uint32_t pipe_stat_reg = psb_pipestat(pipe);
152 uint32_t pipe_enable = dev_priv->pipestat[pipe];
153 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
154 uint32_t pipe_clear;
155 uint32_t i = 0;
156
157 spin_lock(&dev_priv->irqmask_lock);
158
159 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
160 pipe_stat_val &= pipe_enable | pipe_status;
161 pipe_stat_val &= pipe_stat_val >> 16;
162
163 spin_unlock(&dev_priv->irqmask_lock);
164
165 /* Clear the 2nd level interrupt status bits
166 * Sometimes the bits are very sticky so we repeat until they unstick */
167 for (i = 0; i < 0xffff; i++) {
168 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
169 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
170
171 if (pipe_clear == 0)
172 break;
173 }
174
175 if (pipe_clear)
176 dev_err(dev->dev,
177 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
178 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
179
180 if (pipe_stat_val & PIPE_VBLANK_STATUS)
181 drm_handle_vblank(dev, pipe);
182
183 if (pipe_stat_val & PIPE_TE_STATUS)
184 drm_handle_vblank(dev, pipe);
185}
186
187/*
188 * Display controller interrupt handler.
189 */
190static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
191{
192 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
193 mid_pipe_event_handler(dev, 0);
194
195 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
196 mid_pipe_event_handler(dev, 1);
197}
198
199irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
200{
201 struct drm_device *dev = (struct drm_device *) arg;
202 struct drm_psb_private *dev_priv =
203 (struct drm_psb_private *) dev->dev_private;
204
205 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
206 int handled = 0;
207
208 spin_lock(&dev_priv->irqmask_lock);
209
210 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
211
212 if (vdc_stat & _PSB_PIPE_EVENT_FLAG)
213 dsp_int = 1;
214
215 /* FIXME: Handle Medfield
216 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
217 dsp_int = 1;
218 */
219
220 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
221 sgx_int = 1;
222
223 vdc_stat &= dev_priv->vdc_irq_mask;
224 spin_unlock(&dev_priv->irqmask_lock);
225
226 if (dsp_int && gma_power_is_on(dev)) {
227 psb_vdc_interrupt(dev, vdc_stat);
228 handled = 1;
229 }
230
231 if (sgx_int) {
232 /* Not expected - we have it masked, shut it up */
233 u32 s, s2;
234 s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
235 s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
236 PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
237 PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
238 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
239 we may as well poll even if we add that ! */
240 handled = 1;
241 }
242
243 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
244 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
245 DRM_READMEMORYBARRIER();
246
247 if (!handled)
248 return IRQ_NONE;
249
250 return IRQ_HANDLED;
251}
252
253void psb_irq_preinstall(struct drm_device *dev)
254{
255 struct drm_psb_private *dev_priv =
256 (struct drm_psb_private *) dev->dev_private;
257 unsigned long irqflags;
258
259 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
260
261 if (gma_power_is_on(dev))
262 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
263 if (dev->vblank_enabled[0])
264 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
265 if (dev->vblank_enabled[1])
266 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
267
268 /* FIXME: Handle Medfield irq mask
269 if (dev->vblank_enabled[1])
270 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
271 if (dev->vblank_enabled[2])
272 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
273 */
274
275 /* This register is safe even if display island is off */
276 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
277 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
278}
279
280int psb_irq_postinstall(struct drm_device *dev)
281{
282 struct drm_psb_private *dev_priv =
283 (struct drm_psb_private *) dev->dev_private;
284 unsigned long irqflags;
285
286 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
287
288 /* This register is safe even if display island is off */
289 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
290 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
291
292 if (dev->vblank_enabled[0])
293 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
294 else
295 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
296
297 if (dev->vblank_enabled[1])
298 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
299 else
300 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
301
302 if (dev->vblank_enabled[2])
303 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
304 else
305 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
306
307 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
308 return 0;
309}
310
311void psb_irq_uninstall(struct drm_device *dev)
312{
313 struct drm_psb_private *dev_priv =
314 (struct drm_psb_private *) dev->dev_private;
315 unsigned long irqflags;
316
317 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
318
319 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
320
321 if (dev->vblank_enabled[0])
322 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
323
324 if (dev->vblank_enabled[1])
325 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
326
327 if (dev->vblank_enabled[2])
328 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
329
330 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
331 _PSB_IRQ_MSVDX_FLAG |
332 _LNC_IRQ_TOPAZ_FLAG;
333
334 /* These two registers are safe even if display island is off */
335 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
336 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
337
338 wmb();
339
340 /* This register is safe even if display island is off */
341 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
342 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
343}
344
345void psb_irq_turn_on_dpst(struct drm_device *dev)
346{
347 struct drm_psb_private *dev_priv =
348 (struct drm_psb_private *) dev->dev_private;
349 u32 hist_reg;
350 u32 pwm_reg;
351
352 if (gma_power_begin(dev, false)) {
353 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
354 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
355 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
356 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
357
358 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
359 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
360 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
361 | PWM_PHASEIN_INT_ENABLE,
362 PWM_CONTROL_LOGIC);
363 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
364
365 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
366
367 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
368 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
369 HISTOGRAM_INT_CONTROL);
370 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
371 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
372 PWM_CONTROL_LOGIC);
373
374 gma_power_end(dev);
375 }
376}
377
378int psb_irq_enable_dpst(struct drm_device *dev)
379{
380 struct drm_psb_private *dev_priv =
381 (struct drm_psb_private *) dev->dev_private;
382 unsigned long irqflags;
383
384 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
385
386 /* enable DPST */
387 mid_enable_pipe_event(dev_priv, 0);
388 psb_irq_turn_on_dpst(dev);
389
390 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
391 return 0;
392}
393
394void psb_irq_turn_off_dpst(struct drm_device *dev)
395{
396 struct drm_psb_private *dev_priv =
397 (struct drm_psb_private *) dev->dev_private;
398 u32 hist_reg;
399 u32 pwm_reg;
400
401 if (gma_power_begin(dev, false)) {
402 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
403 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
404
405 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
406
407 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
408 PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
409 PWM_CONTROL_LOGIC);
410 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
411
412 gma_power_end(dev);
413 }
414}
415
416int psb_irq_disable_dpst(struct drm_device *dev)
417{
418 struct drm_psb_private *dev_priv =
419 (struct drm_psb_private *) dev->dev_private;
420 unsigned long irqflags;
421
422 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
423
424 mid_disable_pipe_event(dev_priv, 0);
425 psb_irq_turn_off_dpst(dev);
426
427 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
428
429 return 0;
430}
431
432#ifdef PSB_FIXME
433static int psb_vblank_do_wait(struct drm_device *dev,
434 unsigned int *sequence, atomic_t *counter)
435{
436 unsigned int cur_vblank;
437 int ret = 0;
438 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
439 (((cur_vblank = atomic_read(counter))
440 - *sequence) <= (1 << 23)));
441 *sequence = cur_vblank;
442
443 return ret;
444}
445#endif
446
447/*
448 * It is used to enable VBLANK interrupt
449 */
450int psb_enable_vblank(struct drm_device *dev, int pipe)
451{
452 struct drm_psb_private *dev_priv = dev->dev_private;
453 unsigned long irqflags;
454 uint32_t reg_val = 0;
455 uint32_t pipeconf_reg = mid_pipeconf(pipe);
456
457#if defined(CONFIG_DRM_PSB_MFLD)
458 /* Medfield is different - we should perhaps extract out vblank
459 and blacklight etc ops */
460 if (IS_MFLD(dev) && !mdfld_panel_dpi(dev))
461 return mdfld_enable_te(dev, pipe);
462#endif
463 if (gma_power_begin(dev, false)) {
464 reg_val = REG_READ(pipeconf_reg);
465 gma_power_end(dev);
466 }
467
468 if (!(reg_val & PIPEACONF_ENABLE))
469 return -EINVAL;
470
471 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
472
473 if (pipe == 0)
474 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
475 else if (pipe == 1)
476 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
477
478 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
479 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
480 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
481
482 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
483
484 return 0;
485}
486
487/*
488 * It is used to disable VBLANK interrupt
489 */
490void psb_disable_vblank(struct drm_device *dev, int pipe)
491{
492 struct drm_psb_private *dev_priv = dev->dev_private;
493 unsigned long irqflags;
494
495#if defined(CONFIG_DRM_PSB_MFLD)
496 if (IS_MFLD(dev) && !mdfld_panel_dpi(dev))
497 mdfld_disable_te(dev, pipe);
498#endif
499 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
500
501 if (pipe == 0)
502 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
503 else if (pipe == 1)
504 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
505
506 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
507 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
508 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
509
510 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
511}
512
513/**
514 * mdfld_enable_te - enable TE events
515 * @dev: our DRM device
516 * @pipe: which pipe to work on
517 *
518 * Enable TE events on a Medfield display pipe. Medfield specific.
519 */
520int mdfld_enable_te(struct drm_device *dev, int pipe)
521{
522 struct drm_psb_private *dev_priv = dev->dev_private;
523 unsigned long flags;
524 uint32_t reg_val = 0;
525 uint32_t pipeconf_reg = mid_pipeconf(pipe);
526
527 if (gma_power_begin(dev, false)) {
528 reg_val = REG_READ(pipeconf_reg);
529 gma_power_end(dev);
530 }
531
532 if (!(reg_val & PIPEACONF_ENABLE))
533 return -EINVAL;
534
535 spin_lock_irqsave(&dev_priv->irqmask_lock, flags);
536
537 mid_enable_pipe_event(dev_priv, pipe);
538 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
539
540 spin_unlock_irqrestore(&dev_priv->irqmask_lock, flags);
541
542 return 0;
543}
544
545/**
546 * mdfld_disable_te - disable TE events
547 * @dev: our DRM device
548 * @pipe: which pipe to work on
549 *
550 * Disable TE events on a Medfield display pipe. Medfield specific.
551 */
552void mdfld_disable_te(struct drm_device *dev, int pipe)
553{
554 struct drm_psb_private *dev_priv = dev->dev_private;
555 unsigned long flags;
556
557 spin_lock_irqsave(&dev_priv->irqmask_lock, flags);
558
559 mid_disable_pipe_event(dev_priv, pipe);
560 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
561
562 spin_unlock_irqrestore(&dev_priv->irqmask_lock, flags);
563}
564
565/* Called from drm generic code, passed a 'crtc', which
566 * we use as a pipe index
567 */
568u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
569{
570 uint32_t high_frame = PIPEAFRAMEHIGH;
571 uint32_t low_frame = PIPEAFRAMEPIXEL;
572 uint32_t pipeconf_reg = PIPEACONF;
573 uint32_t reg_val = 0;
574 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
575
576 switch (pipe) {
577 case 0:
578 break;
579 case 1:
580 high_frame = PIPEBFRAMEHIGH;
581 low_frame = PIPEBFRAMEPIXEL;
582 pipeconf_reg = PIPEBCONF;
583 break;
584 case 2:
585 high_frame = PIPECFRAMEHIGH;
586 low_frame = PIPECFRAMEPIXEL;
587 pipeconf_reg = PIPECCONF;
588 break;
589 default:
590 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
591 return 0;
592 }
593
594 if (!gma_power_begin(dev, false))
595 return 0;
596
597 reg_val = REG_READ(pipeconf_reg);
598
599 if (!(reg_val & PIPEACONF_ENABLE)) {
600 dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
601 pipe);
602 goto psb_get_vblank_counter_exit;
603 }
604
605 /*
606 * High & low register fields aren't synchronized, so make sure
607 * we get a low value that's stable across two reads of the high
608 * register.
609 */
610 do {
611 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
612 PIPE_FRAME_HIGH_SHIFT);
613 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
614 PIPE_FRAME_LOW_SHIFT);
615 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
616 PIPE_FRAME_HIGH_SHIFT);
617 } while (high1 != high2);
618
619 count = (high1 << 8) | low;
620
621psb_get_vblank_counter_exit:
622
623 gma_power_end(dev);
624
625 return count;
626}
627
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 02:46:34 -0400