aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/staging/et131x/et1310_address_map.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/staging/et131x/et1310_address_map.h')
-rw-r--r--drivers/staging/et131x/et1310_address_map.h82
1 files changed, 19 insertions, 63 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h
index d599f312963..67aef73b3ce 100644
--- a/drivers/staging/et131x/et1310_address_map.h
+++ b/drivers/staging/et131x/et1310_address_map.h
@@ -684,77 +684,33 @@ typedef union _RXMAC_CTRL_t {
684/* 684/*
685 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map 685 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
686 * located at address 0x4004 686 * located at address 0x4004
687 * 31-16: crc
688 * 15-12: reserved
689 * 11: ignore_pp
690 * 10: ignore_mp
691 * 9: clr_intr
692 * 8: ignore_link_chg
693 * 7: ignore_uni
694 * 6: ignore_multi
695 * 5: ignore_broad
696 * 4-0: valid_crc 4-0
687 */ 697 */
688typedef union _RXMAC_WOL_CTL_CRC0_t {
689 u32 value;
690 struct {
691#ifdef _BIT_FIELDS_HTOL
692 u32 crc0:16; /* bits 16-31 */
693 u32 reserve:4; /* bits 12-15 */
694 u32 ignore_pp:1; /* bit 11 */
695 u32 ignore_mp:1; /* bit 10 */
696 u32 clr_intr:1; /* bit 9 */
697 u32 ignore_link_chg:1; /* bit 8 */
698 u32 ignore_uni:1; /* bit 7 */
699 u32 ignore_multi:1; /* bit 6 */
700 u32 ignore_broad:1; /* bit 5 */
701 u32 valid_crc4:1; /* bit 4 */
702 u32 valid_crc3:1; /* bit 3 */
703 u32 valid_crc2:1; /* bit 2 */
704 u32 valid_crc1:1; /* bit 1 */
705 u32 valid_crc0:1; /* bit 0 */
706#else
707 u32 valid_crc0:1; /* bit 0 */
708 u32 valid_crc1:1; /* bit 1 */
709 u32 valid_crc2:1; /* bit 2 */
710 u32 valid_crc3:1; /* bit 3 */
711 u32 valid_crc4:1; /* bit 4 */
712 u32 ignore_broad:1; /* bit 5 */
713 u32 ignore_multi:1; /* bit 6 */
714 u32 ignore_uni:1; /* bit 7 */
715 u32 ignore_link_chg:1; /* bit 8 */
716 u32 clr_intr:1; /* bit 9 */
717 u32 ignore_mp:1; /* bit 10 */
718 u32 ignore_pp:1; /* bit 11 */
719 u32 reserve:4; /* bits 12-15 */
720 u32 crc0:16; /* bits 16-31 */
721#endif
722 } bits;
723} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
724 698
725/* 699/*
726 * structure for CRC 1 and CRC 2 reg in rxmac address map 700 * structure for CRC 1 and CRC 2 reg in rxmac address map
727 * located at address 0x4008 701 * located at address 0x4008
702 *
703 * 31-16: crc2
704 * 15-0: crc1
728 */ 705 */
729typedef union _RXMAC_WOL_CRC12_t {
730 u32 value;
731 struct {
732#ifdef _BIT_FIELDS_HTOL
733 u32 crc2:16; /* bits 16-31 */
734 u32 crc1:16; /* bits 0-15 */
735#else
736 u32 crc1:16; /* bits 0-15 */
737 u32 crc2:16; /* bits 16-31 */
738#endif
739 } bits;
740} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
741 706
742/* 707/*
743 * structure for CRC 3 and CRC 4 reg in rxmac address map 708 * structure for CRC 3 and CRC 4 reg in rxmac address map
744 * located at address 0x400C 709 * located at address 0x400C
710 *
711 * 31-16: crc4
712 * 15-0: crc3
745 */ 713 */
746typedef union _RXMAC_WOL_CRC34_t {
747 u32 value;
748 struct {
749#ifdef _BIT_FIELDS_HTOL
750 u32 crc4:16; /* bits 16-31 */
751 u32 crc3:16; /* bits 0-15 */
752#else
753 u32 crc3:16; /* bits 0-15 */
754 u32 crc4:16; /* bits 16-31 */
755#endif
756 } bits;
757} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
758 714
759/* 715/*
760 * structure for Wake On Lan Source Address Lo reg in rxmac address map 716 * structure for Wake On Lan Source Address Lo reg in rxmac address map
@@ -1029,9 +985,9 @@ typedef union _RXMAC_ERROR_REG_t {
1029 */ 985 */
1030typedef struct _RXMAC_t { /* Location: */ 986typedef struct _RXMAC_t { /* Location: */
1031 RXMAC_CTRL_t ctrl; /* 0x4000 */ 987 RXMAC_CTRL_t ctrl; /* 0x4000 */
1032 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */ 988 u32 crc0; /* 0x4004 */
1033 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */ 989 u32 crc12; /* 0x4008 */
1034 RXMAC_WOL_CRC34_t crc34; /* 0x400C */ 990 u32 crc34; /* 0x400C */
1035 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */ 991 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1036 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */ 992 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1037 u32 mask0_word0; /* 0x4018 */ 993 u32 mask0_word0; /* 0x4018 */