16 files changed, 8911 insertions, 0 deletions

diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h
new file mode 100644
index 00000000000..410677ee22b
--- /dev/null
+++ b/drivers/staging/et131x/et1310_address_map.h
@@ -0,0 +1,1434 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_address_map.h - Contains the register mapping for the ET1310
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef _ET1310_ADDRESS_MAP_H_
+#define _ET1310_ADDRESS_MAP_H_
+
+
+/* START OF GLOBAL REGISTER ADDRESS MAP */
+
+/*
+ * 10bit registers
+ *
+ * Tx queue start address reg in global address map at address 0x0000
+ * tx queue end address reg in global address map at address 0x0004
+ * rx queue start address reg in global address map at address 0x0008
+ * rx queue end address reg in global address map at address 0x000C
+ */
+
+/*
+ * structure for power management control status reg in global address map
+ * located at address 0x0010
+ *      jagcore_rx_rdy  bit 9
+ *      jagcore_tx_rdy  bit 8
+ *      phy_lped_en     bit 7
+ *      phy_sw_coma     bit 6
+ *      rxclk_gate      bit 5
+ *      txclk_gate      bit 4
+ *      sysclk_gate     bit 3
+ *      jagcore_rx_en   bit 2
+ *      jagcore_tx_en   bit 1
+ *      gigephy_en      bit 0
+ */
+
+#define ET_PM_PHY_SW_COMA               0x40
+#define ET_PMCSR_INIT                   0x38
+
+/*
+ * Interrupt status reg at address 0x0018
+ */
+
+#define ET_INTR_TXDMA_ISR       0x00000008
+#define ET_INTR_TXDMA_ERR       0x00000010
+#define ET_INTR_RXDMA_XFR_DONE  0x00000020
+#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
+#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
+#define ET_INTR_RXDMA_STAT_LOW  0x00000100
+#define ET_INTR_RXDMA_ERR       0x00000200
+#define ET_INTR_WATCHDOG        0x00004000
+#define ET_INTR_WOL             0x00008000
+#define ET_INTR_PHY             0x00010000
+#define ET_INTR_TXMAC           0x00020000
+#define ET_INTR_RXMAC           0x00040000
+#define ET_INTR_MAC_STAT        0x00080000
+#define ET_INTR_SLV_TIMEOUT     0x00100000
+
+/*
+ * Interrupt mask register at address 0x001C
+ * Interrupt alias clear mask reg at address 0x0020
+ * Interrupt status alias reg at address 0x0024
+ *
+ * Same masks as above
+ */
+
+/*
+ * Software reset reg at address 0x0028
+ * 0:   txdma_sw_reset
+ * 1:   rxdma_sw_reset
+ * 2:   txmac_sw_reset
+ * 3:   rxmac_sw_reset
+ * 4:   mac_sw_reset
+ * 5:   mac_stat_sw_reset
+ * 6:   mmc_sw_reset
+ *31:   selfclr_disable
+ */
+
+/*
+ * SLV Timer reg at address 0x002C (low 24 bits)
+ */
+
+/*
+ * MSI Configuration reg at address 0x0030
+ */
+
+#define ET_MSI_VECTOR   0x0000001F
+#define ET_MSI_TC       0x00070000
+
+/*
+ * Loopback reg located at address 0x0034
+ */
+
+#define ET_LOOP_MAC     0x00000001
+#define ET_LOOP_DMA     0x00000002
+
+/*
+ * GLOBAL Module of JAGCore Address Mapping
+ * Located at address 0x0000
+ */
+struct global_regs {                    /* Location: */
+        u32 txq_start_addr;                     /*  0x0000 */
+        u32 txq_end_addr;                       /*  0x0004 */
+        u32 rxq_start_addr;                     /*  0x0008 */
+        u32 rxq_end_addr;                       /*  0x000C */
+        u32 pm_csr;                             /*  0x0010 */
+        u32 unused;                             /*  0x0014 */
+        u32 int_status;                         /*  0x0018 */
+        u32 int_mask;                           /*  0x001C */
+        u32 int_alias_clr_en;                   /*  0x0020 */
+        u32 int_status_alias;                   /*  0x0024 */
+        u32 sw_reset;                           /*  0x0028 */
+        u32 slv_timer;                          /*  0x002C */
+        u32 msi_config;                         /*  0x0030 */
+        u32 loopback;                   /*  0x0034 */
+        u32 watchdog_timer;                     /*  0x0038 */
+};
+
+
+/* START OF TXDMA REGISTER ADDRESS MAP */
+
+/*
+ * txdma control status reg at address 0x1000
+ */
+
+#define ET_TXDMA_CSR_HALT       0x00000001
+#define ET_TXDMA_DROP_TLP       0x00000002
+#define ET_TXDMA_CACHE_THRS     0x000000F0
+#define ET_TXDMA_CACHE_SHIFT    4
+#define ET_TXDMA_SNGL_EPKT      0x00000100
+#define ET_TXDMA_CLASS          0x00001E00
+
+/*
+ * structure for txdma packet ring base address hi reg in txdma address map
+ * located at address 0x1004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring base address low reg in txdma address map
+ * located at address 0x1008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring number of descriptor reg in txdma address
+ * map.  Located at address 0x100C
+ *
+ * 31-10: unused
+ * 9-0: pr ndes
+ */
+
+#define ET_DMA12_MASK           0x0FFF  /* 12 bit mask for DMA12W types */
+#define ET_DMA12_WRAP           0x1000
+#define ET_DMA10_MASK           0x03FF  /* 10 bit mask for DMA10W types */
+#define ET_DMA10_WRAP           0x0400
+#define ET_DMA4_MASK            0x000F  /* 4 bit mask for DMA4W types */
+#define ET_DMA4_WRAP            0x0010
+
+#define INDEX12(x)      ((x) & ET_DMA12_MASK)
+#define INDEX10(x)      ((x) & ET_DMA10_MASK)
+#define INDEX4(x)       ((x) & ET_DMA4_MASK)
+
+extern inline void add_10bit(u32 *v, int n)
+{
+        *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
+}
+
+extern inline void add_12bit(u32 *v, int n)
+{
+        *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
+}
+
+/*
+ * 10bit DMA with wrap
+ * txdma tx queue write address reg in txdma address map at 0x1010
+ * txdma tx queue write address external reg in txdma address map at 0x1014
+ * txdma tx queue read address reg in txdma address map at 0x1018
+ *
+ * u32
+ * txdma status writeback address hi reg in txdma address map at0x101C
+ * txdma status writeback address lo reg in txdma address map at 0x1020
+ *
+ * 10bit DMA with wrap
+ * txdma service request reg in txdma address map at 0x1024
+ * structure for txdma service complete reg in txdma address map at 0x1028
+ *
+ * 4bit DMA with wrap
+ * txdma tx descriptor cache read index reg in txdma address map at 0x102C
+ * txdma tx descriptor cache write index reg in txdma address map at 0x1030
+ *
+ * txdma error reg in txdma address map at address 0x1034
+ * 0: PyldResend
+ * 1: PyldRewind
+ * 4: DescrResend
+ * 5: DescrRewind
+ * 8: WrbkResend
+ * 9: WrbkRewind
+ */
+
+/*
+ * Tx DMA Module of JAGCore Address Mapping
+ * Located at address 0x1000
+ */
+struct txdma_regs {                     /* Location: */
+        u32 csr;                        /*  0x1000 */
+        u32 pr_base_hi;                 /*  0x1004 */
+        u32 pr_base_lo;                 /*  0x1008 */
+        u32 pr_num_des;                 /*  0x100C */
+        u32 txq_wr_addr;                /*  0x1010 */
+        u32 txq_wr_addr_ext;            /*  0x1014 */
+        u32 txq_rd_addr;                /*  0x1018 */
+        u32 dma_wb_base_hi;             /*  0x101C */
+        u32 dma_wb_base_lo;             /*  0x1020 */
+        u32 service_request;            /*  0x1024 */
+        u32 service_complete;           /*  0x1028 */
+        u32 cache_rd_index;             /*  0x102C */
+        u32 cache_wr_index;             /*  0x1030 */
+        u32 tx_dma_error;               /*  0x1034 */
+        u32 desc_abort_cnt;             /*  0x1038 */
+        u32 payload_abort_cnt;          /*  0x103c */
+        u32 writeback_abort_cnt;        /*  0x1040 */
+        u32 desc_timeout_cnt;           /*  0x1044 */
+        u32 payload_timeout_cnt;        /*  0x1048 */
+        u32 writeback_timeout_cnt;      /*  0x104c */
+        u32 desc_error_cnt;             /*  0x1050 */
+        u32 payload_error_cnt;          /*  0x1054 */
+        u32 writeback_error_cnt;        /*  0x1058 */
+        u32 dropped_tlp_cnt;            /*  0x105c */
+        u32 new_service_complete;       /*  0x1060 */
+        u32 ethernet_packet_cnt;        /*  0x1064 */
+};
+
+/* END OF TXDMA REGISTER ADDRESS MAP */
+
+
+/* START OF RXDMA REGISTER ADDRESS MAP */
+
+/*
+ * structure for control status reg in rxdma address map
+ * Located at address 0x2000
+ *
+ * CSR
+ * 0: halt
+ * 1-3: tc
+ * 4: fbr_big_endian
+ * 5: psr_big_endian
+ * 6: pkt_big_endian
+ * 7: dma_big_endian
+ * 8-9: fbr0_size
+ * 10: fbr0_enable
+ * 11-12: fbr1_size
+ * 13: fbr1_enable
+ * 14: unused
+ * 15: pkt_drop_disable
+ * 16: pkt_done_flush
+ * 17: halt_status
+ * 18-31: unused
+ */
+
+
+/*
+ * structure for dma writeback lo reg in rxdma address map
+ * located at address 0x2004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for dma writeback hi reg in rxdma address map
+ * located at address 0x2008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for number of packets done reg in rxdma address map
+ * located at address 0x200C
+ *
+ * 31-8: unused
+ * 7-0: num done
+ */
+
+/*
+ * structure for max packet time reg in rxdma address map
+ * located at address 0x2010
+ *
+ * 31-18: unused
+ * 17-0: time done
+ */
+
+/*
+ * structure for rx queue read address reg in rxdma address map
+ * located at address 0x2014
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for rx queue read address external reg in rxdma address map
+ * located at address 0x2018
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for rx queue write address reg in rxdma address map
+ * located at address 0x201C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring base address lo reg in rxdma address map
+ * located at address 0x2020
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring base address hi reg in rxdma address map
+ * located at address 0x2024
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring number of descriptors reg in rxdma address
+ * map.  Located at address 0x2028
+ *
+ * 31-12: unused
+ * 11-0: psr ndes
+ */
+
+/*
+ * structure for packet status ring available offset reg in rxdma address map
+ * located at address 0x202C
+ *
+ * 31-13: unused
+ * 12: psr avail wrap
+ * 11-0: psr avail
+ */
+
+/*
+ * structure for packet status ring full offset reg in rxdma address map
+ * located at address 0x2030
+ *
+ * 31-13: unused
+ * 12: psr full wrap
+ * 11-0: psr full
+ */
+
+/*
+ * structure for packet status ring access index reg in rxdma address map
+ * located at address 0x2034
+ *
+ * 31-5: unused
+ * 4-0: psr_ai
+ */
+
+/*
+ * structure for packet status ring minimum descriptors reg in rxdma address
+ * map.  Located at address 0x2038
+ *
+ * 31-12: unused
+ * 11-0: psr_min
+ */
+
+/*
+ * structure for free buffer ring base lo address reg in rxdma address map
+ * located at address 0x203C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring base hi address reg in rxdma address map
+ * located at address 0x2040
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring number of descriptors reg in rxdma address
+ * map.  Located at address 0x2044
+ *
+ * 31-10: unused
+ * 9-0: fbr ndesc
+ */
+
+/*
+ * structure for free buffer ring 0 available offset reg in rxdma address map
+ * located at address 0x2048
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring 0 full offset reg in rxdma address map
+ * located at address 0x204C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer cache 0 full offset reg in rxdma address map
+ * located at address 0x2050
+ *
+ * 31-5: unused
+ * 4-0: fbc rdi
+ */
+
+/*
+ * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
+ * located at address 0x2054
+ *
+ * 31-10: unused
+ * 9-0: fbr min
+ */
+
+/*
+ * structure for free buffer ring 1 base address lo reg in rxdma address map
+ * located at address 0x2058 - 0x205C
+ * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
+ */
+
+/*
+ * structure for free buffer ring 1 number of descriptors reg in rxdma address
+ * map.  Located at address 0x2060
+ * Defined earlier (RXDMA_FBR_NUM_DES_t)
+ */
+
+/*
+ * structure for free buffer ring 1 available offset reg in rxdma address map
+ * located at address 0x2064
+ * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer ring 1 full offset reg in rxdma address map
+ * located at address 0x2068
+ * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer cache 1 read index reg in rxdma address map
+ * located at address 0x206C
+ * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
+ */
+
+/*
+ * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
+ * located at address 0x2070
+ * Defined Earlier (RXDMA_FBR_MIN_DES_t)
+ */
+
+/*
+ * Rx DMA Module of JAGCore Address Mapping
+ * Located at address 0x2000
+ */
+struct rxdma_regs {                                     /* Location: */
+        u32 csr;                                        /*  0x2000 */
+        u32 dma_wb_base_lo;                             /*  0x2004 */
+        u32 dma_wb_base_hi;                             /*  0x2008 */
+        u32 num_pkt_done;                               /*  0x200C */
+        u32 max_pkt_time;                               /*  0x2010 */
+        u32 rxq_rd_addr;                                /*  0x2014 */
+        u32 rxq_rd_addr_ext;                            /*  0x2018 */
+        u32 rxq_wr_addr;                                /*  0x201C */
+        u32 psr_base_lo;                                /*  0x2020 */
+        u32 psr_base_hi;                                /*  0x2024 */
+        u32 psr_num_des;                                /*  0x2028 */
+        u32 psr_avail_offset;                           /*  0x202C */
+        u32 psr_full_offset;                            /*  0x2030 */
+        u32 psr_access_index;                           /*  0x2034 */
+        u32 psr_min_des;                                /*  0x2038 */
+        u32 fbr0_base_lo;                               /*  0x203C */
+        u32 fbr0_base_hi;                               /*  0x2040 */
+        u32 fbr0_num_des;                               /*  0x2044 */
+        u32 fbr0_avail_offset;                          /*  0x2048 */
+        u32 fbr0_full_offset;                           /*  0x204C */
+        u32 fbr0_rd_index;                              /*  0x2050 */
+        u32 fbr0_min_des;                               /*  0x2054 */
+        u32 fbr1_base_lo;                               /*  0x2058 */
+        u32 fbr1_base_hi;                               /*  0x205C */
+        u32 fbr1_num_des;                               /*  0x2060 */
+        u32 fbr1_avail_offset;                          /*  0x2064 */
+        u32 fbr1_full_offset;                           /*  0x2068 */
+        u32 fbr1_rd_index;                              /*  0x206C */
+        u32 fbr1_min_des;                               /*  0x2070 */
+};
+
+/* END OF RXDMA REGISTER ADDRESS MAP */
+
+
+/* START OF TXMAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for control reg in txmac address map
+ * located at address 0x3000
+ *
+ * bits
+ * 31-8: unused
+ * 7: cklseg_disable
+ * 6: ckbcnt_disable
+ * 5: cksegnum
+ * 4: async_disable
+ * 3: fc_disable
+ * 2: mcif_disable
+ * 1: mif_disable
+ * 0: txmac_en
+ */
+
+/*
+ * structure for shadow pointer reg in txmac address map
+ * located at address 0x3004
+ * 31-27: reserved
+ * 26-16: txq rd ptr
+ * 15-11: reserved
+ * 10-0: txq wr ptr
+ */
+
+/*
+ * structure for error count reg in txmac address map
+ * located at address 0x3008
+ *
+ * 31-12: unused
+ * 11-8: reserved
+ * 7-4: txq_underrun
+ * 3-0: fifo_underrun
+ */
+
+/*
+ * structure for max fill reg in txmac address map
+ * located at address 0x300C
+ * 31-12: unused
+ * 11-0: max fill
+ */
+
+/*
+ * structure for cf parameter reg in txmac address map
+ * located at address 0x3010
+ * 31-16: cfep
+ * 15-0: cfpt
+ */
+
+/*
+ * structure for tx test reg in txmac address map
+ * located at address 0x3014
+ * 31-17: unused
+ * 16: reserved1
+ * 15: txtest_en
+ * 14-11: unused
+ * 10-0: txq test pointer
+ */
+
+/*
+ * structure for error reg in txmac address map
+ * located at address 0x3018
+ *
+ * 31-9: unused
+ * 8: fifo_underrun
+ * 7-6: unused
+ * 5: ctrl2_err
+ * 4: txq_underrun
+ * 3: bcnt_err
+ * 2: lseg_err
+ * 1: segnum_err
+ * 0: seg0_err
+ */
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x301C
+ *
+ * 31-9: unused
+ * 8: fifo_underrun
+ * 7-6: unused
+ * 5: ctrl2_err
+ * 4: txq_underrun
+ * 3: bcnt_err
+ * 2: lseg_err
+ * 1: segnum_err
+ * 0: seg0_err
+ */
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x3020
+ *
+ * 31-2: unused
+ * 1: bp_req
+ * 0: bp_xonxoff
+ */
+
+/*
+ * Tx MAC Module of JAGCore Address Mapping
+ */
+struct txmac_regs {                     /* Location: */
+        u32 ctl;                        /*  0x3000 */
+        u32 shadow_ptr;                 /*  0x3004 */
+        u32 err_cnt;                    /*  0x3008 */
+        u32 max_fill;                   /*  0x300C */
+        u32 cf_param;                   /*  0x3010 */
+        u32 tx_test;                    /*  0x3014 */
+        u32 err;                        /*  0x3018 */
+        u32 err_int;                    /*  0x301C */
+        u32 bp_ctrl;                    /*  0x3020 */
+};
+
+/* END OF TXMAC REGISTER ADDRESS MAP */
+
+/* START OF RXMAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for rxmac control reg in rxmac address map
+ * located at address 0x4000
+ *
+ * 31-7: reserved
+ * 6: rxmac_int_disable
+ * 5: async_disable
+ * 4: mif_disable
+ * 3: wol_disable
+ * 2: pkt_filter_disable
+ * 1: mcif_disable
+ * 0: rxmac_en
+ */
+
+/*
+ * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
+ * located at address 0x4004
+ * 31-16: crc
+ * 15-12: reserved
+ * 11: ignore_pp
+ * 10: ignore_mp
+ * 9: clr_intr
+ * 8: ignore_link_chg
+ * 7: ignore_uni
+ * 6: ignore_multi
+ * 5: ignore_broad
+ * 4-0: valid_crc 4-0
+ */
+
+/*
+ * structure for CRC 1 and CRC 2 reg in rxmac address map
+ * located at address 0x4008
+ *
+ * 31-16: crc2
+ * 15-0: crc1
+ */
+
+/*
+ * structure for CRC 3 and CRC 4 reg in rxmac address map
+ * located at address 0x400C
+ *
+ * 31-16: crc4
+ * 15-0: crc3
+ */
+
+/*
+ * structure for Wake On Lan Source Address Lo reg in rxmac address map
+ * located at address 0x4010
+ *
+ * 31-24: sa3
+ * 23-16: sa4
+ * 15-8: sa5
+ * 7-0: sa6
+ */
+
+#define ET_WOL_LO_SA3_SHIFT 24
+#define ET_WOL_LO_SA4_SHIFT 16
+#define ET_WOL_LO_SA5_SHIFT 8
+
+/*
+ * structure for Wake On Lan Source Address Hi reg in rxmac address map
+ * located at address 0x4014
+ *
+ * 31-16: reserved
+ * 15-8: sa1
+ * 7-0: sa2
+ */
+
+#define ET_WOL_HI_SA1_SHIFT 8
+
+/*
+ * structure for Wake On Lan mask reg in rxmac address map
+ * located at address 0x4018 - 0x4064
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Unicast Paket Filter Address 1 reg in rxmac address map
+ * located at address 0x4068
+ *
+ * 31-24: addr1_3
+ * 23-16: addr1_4
+ * 15-8: addr1_5
+ * 7-0: addr1_6
+ */
+
+#define ET_UNI_PF_ADDR1_3_SHIFT 24
+#define ET_UNI_PF_ADDR1_4_SHIFT 16
+#define ET_UNI_PF_ADDR1_5_SHIFT 8
+
+/*
+ * structure for Unicast Paket Filter Address 2 reg in rxmac address map
+ * located at address 0x406C
+ *
+ * 31-24: addr2_3
+ * 23-16: addr2_4
+ * 15-8: addr2_5
+ * 7-0: addr2_6
+ */
+
+#define ET_UNI_PF_ADDR2_3_SHIFT 24
+#define ET_UNI_PF_ADDR2_4_SHIFT 16
+#define ET_UNI_PF_ADDR2_5_SHIFT 8
+
+/*
+ * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
+ * located at address 0x4070
+ *
+ * 31-24: addr2_1
+ * 23-16: addr2_2
+ * 15-8: addr1_1
+ * 7-0: addr1_2
+ */
+
+#define ET_UNI_PF_ADDR2_1_SHIFT 24
+#define ET_UNI_PF_ADDR2_2_SHIFT 16
+#define ET_UNI_PF_ADDR1_1_SHIFT 8
+
+
+/*
+ * structure for Multicast Hash reg in rxmac address map
+ * located at address 0x4074 - 0x4080
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Packet Filter Control reg in rxmac address map
+ * located at address 0x4084
+ *
+ * 31-23: unused
+ * 22-16: min_pkt_size
+ * 15-4: unused
+ * 3: filter_frag_en
+ * 2: filter_uni_en
+ * 1: filter_multi_en
+ * 0: filter_broad_en
+ */
+
+/*
+ * structure for Memory Controller Interface Control Max Segment reg in rxmac
+ * address map.  Located at address 0x4088
+ *
+ * 31-10: reserved
+ * 9-2: max_size
+ * 1: fc_en
+ * 0: seg_en
+ */
+
+/*
+ * structure for Memory Controller Interface Water Mark reg in rxmac address
+ * map.  Located at address 0x408C
+ *
+ * 31-26: unused
+ * 25-16: mark_hi
+ * 15-10: unused
+ * 9-0: mark_lo
+ */
+
+/*
+ * structure for Rx Queue Dialog reg in rxmac address map.
+ * located at address 0x4090
+ *
+ * 31-26: reserved
+ * 25-16: rd_ptr
+ * 15-10: reserved
+ * 9-0: wr_ptr
+ */
+
+/*
+ * structure for space available reg in rxmac address map.
+ * located at address 0x4094
+ *
+ * 31-17: reserved
+ * 16: space_avail_en
+ * 15-10: reserved
+ * 9-0: space_avail
+ */
+
+/*
+ * structure for management interface reg in rxmac address map.
+ * located at address 0x4098
+ *
+ * 31-18: reserved
+ * 17: drop_pkt_en
+ * 16-0: drop_pkt_mask
+ */
+
+/*
+ * structure for Error reg in rxmac address map.
+ * located at address 0x409C
+ *
+ * 31-4: unused
+ * 3: mif
+ * 2: async
+ * 1: pkt_filter
+ * 0: mcif
+ */
+
+/*
+ * Rx MAC Module of JAGCore Address Mapping
+ */
+struct rxmac_regs {                                     /* Location: */
+        u32 ctrl;                                       /*  0x4000 */
+        u32 crc0;                                       /*  0x4004 */
+        u32 crc12;                                      /*  0x4008 */
+        u32 crc34;                                      /*  0x400C */
+        u32 sa_lo;                                      /*  0x4010 */
+        u32 sa_hi;                                      /*  0x4014 */
+        u32 mask0_word0;                                /*  0x4018 */
+        u32 mask0_word1;                                /*  0x401C */
+        u32 mask0_word2;                                /*  0x4020 */
+        u32 mask0_word3;                                /*  0x4024 */
+        u32 mask1_word0;                                /*  0x4028 */
+        u32 mask1_word1;                                /*  0x402C */
+        u32 mask1_word2;                                /*  0x4030 */
+        u32 mask1_word3;                                /*  0x4034 */
+        u32 mask2_word0;                                /*  0x4038 */
+        u32 mask2_word1;                                /*  0x403C */
+        u32 mask2_word2;                                /*  0x4040 */
+        u32 mask2_word3;                                /*  0x4044 */
+        u32 mask3_word0;                                /*  0x4048 */
+        u32 mask3_word1;                                /*  0x404C */
+        u32 mask3_word2;                                /*  0x4050 */
+        u32 mask3_word3;                                /*  0x4054 */
+        u32 mask4_word0;                                /*  0x4058 */
+        u32 mask4_word1;                                /*  0x405C */
+        u32 mask4_word2;                                /*  0x4060 */
+        u32 mask4_word3;                                /*  0x4064 */
+        u32 uni_pf_addr1;                               /*  0x4068 */
+        u32 uni_pf_addr2;                               /*  0x406C */
+        u32 uni_pf_addr3;                               /*  0x4070 */
+        u32 multi_hash1;                                /*  0x4074 */
+        u32 multi_hash2;                                /*  0x4078 */
+        u32 multi_hash3;                                /*  0x407C */
+        u32 multi_hash4;                                /*  0x4080 */
+        u32 pf_ctrl;                                    /*  0x4084 */
+        u32 mcif_ctrl_max_seg;                          /*  0x4088 */
+        u32 mcif_water_mark;                            /*  0x408C */
+        u32 rxq_diag;                                   /*  0x4090 */
+        u32 space_avail;                                /*  0x4094 */
+
+        u32 mif_ctrl;                                   /*  0x4098 */
+        u32 err_reg;                                    /*  0x409C */
+};
+
+/* END OF RXMAC REGISTER ADDRESS MAP */
+
+
+/* START OF MAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for configuration #1 reg in mac address map.
+ * located at address 0x5000
+ *
+ * 31: soft reset
+ * 30: sim reset
+ * 29-20: reserved
+ * 19: reset rx mc
+ * 18: reset tx mc
+ * 17: reset rx func
+ * 16: reset tx fnc
+ * 15-9: reserved
+ * 8: loopback
+ * 7-6: reserved
+ * 5: rx flow
+ * 4: tx flow
+ * 3: syncd rx en
+ * 2: rx enable
+ * 1: syncd tx en
+ * 0: tx enable
+ */
+
+#define CFG1_LOOPBACK   0x00000100
+#define CFG1_RX_FLOW    0x00000020
+#define CFG1_TX_FLOW    0x00000010
+#define CFG1_RX_ENABLE  0x00000004
+#define CFG1_TX_ENABLE  0x00000001
+#define CFG1_WAIT       0x0000000A      /* RX & TX syncd */
+
+/*
+ * structure for configuration #2 reg in mac address map.
+ * located at address 0x5004
+ * 31-16: reserved
+ * 15-12: preamble
+ * 11-10: reserved
+ * 9-8: if mode
+ * 7-6: reserved
+ * 5: huge frame
+ * 4: length check
+ * 3: undefined
+ * 2: pad crc
+ * 1: crc enable
+ * 0: full duplex
+ */
+
+
+/*
+ * structure for Interpacket gap reg in mac address map.
+ * located at address 0x5008
+ *
+ * 31: reserved
+ * 30-24: non B2B ipg 1
+ * 23: undefined
+ * 22-16: non B2B ipg 2
+ * 15-8: Min ifg enforce
+ * 7-0: B2B ipg
+ *
+ * structure for half duplex reg in mac address map.
+ * located at address 0x500C
+ * 31-24: reserved
+ * 23-20: Alt BEB trunc
+ * 19: Alt BEB enable
+ * 18: BP no backoff
+ * 17: no backoff
+ * 16: excess defer
+ * 15-12: re-xmit max
+ * 11-10: reserved
+ * 9-0: collision window
+ */
+
+/*
+ * structure for Maximum Frame Length reg in mac address map.
+ * located at address 0x5010: bits 0-15 hold the length.
+ */
+
+/*
+ * structure for Reserve 1 reg in mac address map.
+ * located at address 0x5014 - 0x5018
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Test reg in mac address map.
+ * located at address 0x501C
+ * test: bits 0-2, rest unused
+ */
+
+/*
+ * structure for MII Management Configuration reg in mac address map.
+ * located at address 0x5020
+ *
+ * 31: reset MII mgmt
+ * 30-6: unused
+ * 5: scan auto increment
+ * 4: preamble suppress
+ * 3: undefined
+ * 2-0: mgmt clock reset
+ */
+
+/*
+ * structure for MII Management Command reg in mac address map.
+ * located at address 0x5024
+ * bit 1: scan cycle
+ * bit 0: read cycle
+ */
+
+/*
+ * structure for MII Management Address reg in mac address map.
+ * located at address 0x5028
+ * 31-13: reserved
+ * 12-8: phy addr
+ * 7-5: reserved
+ * 4-0: register
+ */
+
+#define MII_ADDR(phy, reg)      ((phy) << 8 | (reg))
+
+/*
+ * structure for MII Management Control reg in mac address map.
+ * located at address 0x502C
+ * 31-16: reserved
+ * 15-0: phy control
+ */
+
+/*
+ * structure for MII Management Status reg in mac address map.
+ * located at address 0x5030
+ * 31-16: reserved
+ * 15-0: phy control
+ */
+
+/*
+ * structure for MII Management Indicators reg in mac address map.
+ * located at address 0x5034
+ * 31-3: reserved
+ * 2: not valid
+ * 1: scanning
+ * 0: busy
+ */
+
+#define MGMT_BUSY       0x00000001      /* busy */
+#define MGMT_WAIT       0x00000005      /* busy | not valid */
+
+/*
+ * structure for Interface Control reg in mac address map.
+ * located at address 0x5038
+ *
+ * 31: reset if module
+ * 30-28: reserved
+ * 27: tbi mode
+ * 26: ghd mode
+ * 25: lhd mode
+ * 24: phy mode
+ * 23: reset per mii
+ * 22-17: reserved
+ * 16: speed
+ * 15: reset pe100x
+ * 14-11: reserved
+ * 10: force quiet
+ * 9: no cipher
+ * 8: disable link fail
+ * 7: reset gpsi
+ * 6-1: reserved
+ * 0: enable jabber protection
+ */
+
+/*
+ * structure for Interface Status reg in mac address map.
+ * located at address 0x503C
+ *
+ * 31-10: reserved
+ * 9: excess_defer
+ * 8: clash
+ * 7: phy_jabber
+ * 6: phy_link_ok
+ * 5: phy_full_duplex
+ * 4: phy_speed
+ * 3: pe100x_link_fail
+ * 2: pe10t_loss_carrier
+ * 1: pe10t_sqe_error
+ * 0: pe10t_jabber
+ */
+
+/*
+ * structure for Mac Station Address, Part 1 reg in mac address map.
+ * located at address 0x5040
+ *
+ * 31-24: Octet6
+ * 23-16: Octet5
+ * 15-8: Octet4
+ * 7-0: Octet3
+ */
+
+#define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
+#define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
+#define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
+
+/*
+ * structure for Mac Station Address, Part 2 reg in mac address map.
+ * located at address 0x5044
+ *
+ * 31-24: Octet2
+ * 23-16: Octet1
+ * 15-0: reserved
+ */
+
+#define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
+#define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
+
+/*
+ * MAC Module of JAGCore Address Mapping
+ */
+struct mac_regs {                                       /* Location: */
+        u32 cfg1;                                       /*  0x5000 */
+        u32 cfg2;                                       /*  0x5004 */
+        u32 ipg;                                        /*  0x5008 */
+        u32 hfdp;                                       /*  0x500C */
+        u32 max_fm_len;                                 /*  0x5010 */
+        u32 rsv1;                                       /*  0x5014 */
+        u32 rsv2;                                       /*  0x5018 */
+        u32 mac_test;                                   /*  0x501C */
+        u32 mii_mgmt_cfg;                               /*  0x5020 */
+        u32 mii_mgmt_cmd;                               /*  0x5024 */
+        u32 mii_mgmt_addr;                              /*  0x5028 */
+        u32 mii_mgmt_ctrl;                              /*  0x502C */
+        u32 mii_mgmt_stat;                              /*  0x5030 */
+        u32 mii_mgmt_indicator;                         /*  0x5034 */
+        u32 if_ctrl;                                    /*  0x5038 */
+        u32 if_stat;                                    /*  0x503C */
+        u32 station_addr_1;                             /*  0x5040 */
+        u32 station_addr_2;                             /*  0x5044 */
+};
+
+/* END OF MAC REGISTER ADDRESS MAP */
+
+/* START OF MAC STAT REGISTER ADDRESS MAP */
+
+/*
+ * structure for Carry Register One and it's Mask Register reg located in mac
+ * stat address map address 0x6130 and 0x6138.
+ *
+ * 31: tr64
+ * 30: tr127
+ * 29: tr255
+ * 28: tr511
+ * 27: tr1k
+ * 26: trmax
+ * 25: trmgv
+ * 24-17: unused
+ * 16: rbyt
+ * 15: rpkt
+ * 14: rfcs
+ * 13: rmca
+ * 12: rbca
+ * 11: rxcf
+ * 10: rxpf
+ * 9: rxuo
+ * 8: raln
+ * 7: rflr
+ * 6: rcde
+ * 5: rcse
+ * 4: rund
+ * 3: rovr
+ * 2: rfrg
+ * 1: rjbr
+ * 0: rdrp
+ */
+
+/*
+ * structure for Carry Register Two Mask Register reg in mac stat address map.
+ * located at address 0x613C
+ *
+ * 31-20: unused
+ * 19: tjbr
+ * 18: tfcs
+ * 17: txcf
+ * 16: tovr
+ * 15: tund
+ * 14: trfg
+ * 13: tbyt
+ * 12: tpkt
+ * 11: tmca
+ * 10: tbca
+ * 9: txpf
+ * 8: tdfr
+ * 7: tedf
+ * 6: tscl
+ * 5: tmcl
+ * 4: tlcl
+ * 3: txcl
+ * 2: tncl
+ * 1: tpfh
+ * 0: tdrp
+ */
+
+/*
+ * MAC STATS Module of JAGCore Address Mapping
+ */
+struct macstat_regs {                   /* Location: */
+        u32 pad[32];                    /*  0x6000 - 607C */
+
+        /* Tx/Rx 0-64 Byte Frame Counter */
+        u32 txrx_0_64_byte_frames;      /*  0x6080 */
+
+        /* Tx/Rx 65-127 Byte Frame Counter */
+        u32 txrx_65_127_byte_frames;    /*  0x6084 */
+
+        /* Tx/Rx 128-255 Byte Frame Counter */
+        u32 txrx_128_255_byte_frames;   /*  0x6088 */
+
+        /* Tx/Rx 256-511 Byte Frame Counter */
+        u32 txrx_256_511_byte_frames;   /*  0x608C */
+
+        /* Tx/Rx 512-1023 Byte Frame Counter */
+        u32 txrx_512_1023_byte_frames;  /*  0x6090 */
+
+        /* Tx/Rx 1024-1518 Byte Frame Counter */
+        u32 txrx_1024_1518_byte_frames; /*  0x6094 */
+
+        /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
+        u32 txrx_1519_1522_gvln_frames; /*  0x6098 */
+
+        /* Rx Byte Counter */
+        u32 rx_bytes;                   /*  0x609C */
+
+        /* Rx Packet Counter */
+        u32 rx_packets;                 /*  0x60A0 */
+
+        /* Rx FCS Error Counter */
+        u32 rx_fcs_errs;                /*  0x60A4 */
+
+        /* Rx Multicast Packet Counter */
+        u32 rx_multicast_packets;       /*  0x60A8 */
+
+        /* Rx Broadcast Packet Counter */
+        u32 rx_broadcast_packets;       /*  0x60AC */
+
+        /* Rx Control Frame Packet Counter */
+        u32 rx_control_frames;          /*  0x60B0 */
+
+        /* Rx Pause Frame Packet Counter */
+        u32 rx_pause_frames;            /*  0x60B4 */
+
+        /* Rx Unknown OP Code Counter */
+        u32 rx_unknown_opcodes;         /*  0x60B8 */
+
+        /* Rx Alignment Error Counter */
+        u32 rx_align_errs;              /*  0x60BC */
+
+        /* Rx Frame Length Error Counter */
+        u32 rx_frame_len_errs;          /*  0x60C0 */
+
+        /* Rx Code Error Counter */
+        u32 rx_code_errs;               /*  0x60C4 */
+
+        /* Rx Carrier Sense Error Counter */
+        u32 rx_carrier_sense_errs;      /*  0x60C8 */
+
+        /* Rx Undersize Packet Counter */
+        u32 rx_undersize_packets;       /*  0x60CC */
+
+        /* Rx Oversize Packet Counter */
+        u32 rx_oversize_packets;        /*  0x60D0 */
+
+        /* Rx Fragment Counter */
+        u32 rx_fragment_packets;        /*  0x60D4 */
+
+        /* Rx Jabber Counter */
+        u32 rx_jabbers;                 /*  0x60D8 */
+
+        /* Rx Drop */
+        u32 rx_drops;                   /*  0x60DC */
+
+        /* Tx Byte Counter */
+        u32 tx_bytes;                   /*  0x60E0 */
+
+        /* Tx Packet Counter */
+        u32 tx_packets;                 /*  0x60E4 */
+
+        /* Tx Multicast Packet Counter */
+        u32 tx_multicast_packets;       /*  0x60E8 */
+
+        /* Tx Broadcast Packet Counter */
+        u32 tx_broadcast_packets;       /*  0x60EC */
+
+        /* Tx Pause Control Frame Counter */
+        u32 tx_pause_frames;            /*  0x60F0 */
+
+        /* Tx Deferral Packet Counter */
+        u32 tx_deferred;                /*  0x60F4 */
+
+        /* Tx Excessive Deferral Packet Counter */
+        u32 tx_excessive_deferred;      /*  0x60F8 */
+
+        /* Tx Single Collision Packet Counter */
+        u32 tx_single_collisions;       /*  0x60FC */
+
+        /* Tx Multiple Collision Packet Counter */
+        u32 tx_multiple_collisions;     /*  0x6100 */
+
+        /* Tx Late Collision Packet Counter */
+        u32 tx_late_collisions;         /*  0x6104 */
+
+        /* Tx Excessive Collision Packet Counter */
+        u32 tx_excessive_collisions;    /*  0x6108 */
+
+        /* Tx Total Collision Packet Counter */
+        u32 tx_total_collisions;        /*  0x610C */
+
+        /* Tx Pause Frame Honored Counter */
+        u32 tx_pause_honored_frames;    /*  0x6110 */
+
+        /* Tx Drop Frame Counter */
+        u32 tx_drops;                   /*  0x6114 */
+
+        /* Tx Jabber Frame Counter */
+        u32 tx_jabbers;                 /*  0x6118 */
+
+        /* Tx FCS Error Counter */
+        u32 tx_fcs_errs;                /*  0x611C */
+
+        /* Tx Control Frame Counter */
+        u32 tx_control_frames;          /*  0x6120 */
+
+        /* Tx Oversize Frame Counter */
+        u32 tx_oversize_frames;         /*  0x6124 */
+
+        /* Tx Undersize Frame Counter */
+        u32 tx_undersize_frames;        /*  0x6128 */
+
+        /* Tx Fragments Frame Counter */
+        u32 tx_fragments;               /*  0x612C */
+
+        /* Carry Register One Register */
+        u32 carry_reg1;                 /*  0x6130 */
+
+        /* Carry Register Two Register */
+        u32 carry_reg2;                 /*  0x6134 */
+
+        /* Carry Register One Mask Register */
+        u32 carry_reg1_mask;            /*  0x6138 */
+
+        /* Carry Register Two Mask Register */
+        u32 carry_reg2_mask;            /*  0x613C */
+};
+
+/* END OF MAC STAT REGISTER ADDRESS MAP */
+
+
+/* START OF MMC REGISTER ADDRESS MAP */
+
+/*
+ * Main Memory Controller Control reg in mmc address map.
+ * located at address 0x7000
+ */
+
+#define ET_MMC_ENABLE           1
+#define ET_MMC_ARB_DISABLE      2
+#define ET_MMC_RXMAC_DISABLE    4
+#define ET_MMC_TXMAC_DISABLE    8
+#define ET_MMC_TXDMA_DISABLE    16
+#define ET_MMC_RXDMA_DISABLE    32
+#define ET_MMC_FORCE_CE         64
+
+/*
+ * Main Memory Controller Host Memory Access Address reg in mmc
+ * address map.  Located at address 0x7004. Top 16 bits hold the address bits
+ */
+
+#define ET_SRAM_REQ_ACCESS      1
+#define ET_SRAM_WR_ACCESS       2
+#define ET_SRAM_IS_CTRL         4
+
+/*
+ * structure for Main Memory Controller Host Memory Access Data reg in mmc
+ * address map.  Located at address 0x7008 - 0x7014
+ * Defined earlier (u32)
+ */
+
+/*
+ * Memory Control Module of JAGCore Address Mapping
+ */
+struct mmc_regs {               /* Location: */
+        u32 mmc_ctrl;           /*  0x7000 */
+        u32 sram_access;        /*  0x7004 */
+        u32 sram_word1;         /*  0x7008 */
+        u32 sram_word2;         /*  0x700C */
+        u32 sram_word3;         /*  0x7010 */
+        u32 sram_word4;         /*  0x7014 */
+};
+
+/* END OF MMC REGISTER ADDRESS MAP */
+
+
+/*
+ * JAGCore Address Mapping
+ */
+struct address_map {
+        struct global_regs global;
+        /* unused section of global address map */
+        u8 unused_global[4096 - sizeof(struct global_regs)];
+        struct txdma_regs txdma;
+        /* unused section of txdma address map */
+        u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
+        struct rxdma_regs rxdma;
+        /* unused section of rxdma address map */
+        u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
+        struct txmac_regs txmac;
+        /* unused section of txmac address map */
+        u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
+        struct rxmac_regs rxmac;
+        /* unused section of rxmac address map */
+        u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
+        struct mac_regs mac;
+        /* unused section of mac address map */
+        u8 unused_mac[4096 - sizeof(struct mac_regs)];
+        struct macstat_regs macstat;
+        /* unused section of mac stat address map */
+        u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
+        struct mmc_regs mmc;
+        /* unused section of mmc address map */
+        u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
+        /* unused section of address map */
+        u8 unused_[1015808];
+
+        u8 unused_exp_rom[4096];        /* MGS-size TBD */
+        u8 unused__[524288];    /* unused section of address map */
+};
+
+#endif /* _ET1310_ADDRESS_MAP_H_ */
diff --git a/drivers/staging/et131x/et1310_eeprom.c b/drivers/staging/et131x/et1310_eeprom.c
new file mode 100644
index 00000000000..237584001a8
--- /dev/null
+++ b/drivers/staging/et131x/et1310_eeprom.c
@@ -0,0 +1,407 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_eeprom.c - Code used to access the device's EEPROM
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et131x_adapter.h"
+#include "et131x.h"
+
+/*
+ * EEPROM Defines
+ */
+
+/* LBCIF Register Groups (addressed via 32-bit offsets) */
+#define LBCIF_DWORD0_GROUP       0xAC
+#define LBCIF_DWORD1_GROUP       0xB0
+
+/* LBCIF Registers (addressed via 8-bit offsets) */
+#define LBCIF_ADDRESS_REGISTER   0xAC
+#define LBCIF_DATA_REGISTER      0xB0
+#define LBCIF_CONTROL_REGISTER   0xB1
+#define LBCIF_STATUS_REGISTER    0xB2
+
+/* LBCIF Control Register Bits */
+#define LBCIF_CONTROL_SEQUENTIAL_READ   0x01
+#define LBCIF_CONTROL_PAGE_WRITE        0x02
+#define LBCIF_CONTROL_EEPROM_RELOAD     0x08
+#define LBCIF_CONTROL_TWO_BYTE_ADDR     0x20
+#define LBCIF_CONTROL_I2C_WRITE         0x40
+#define LBCIF_CONTROL_LBCIF_ENABLE      0x80
+
+/* LBCIF Status Register Bits */
+#define LBCIF_STATUS_PHY_QUEUE_AVAIL    0x01
+#define LBCIF_STATUS_I2C_IDLE           0x02
+#define LBCIF_STATUS_ACK_ERROR          0x04
+#define LBCIF_STATUS_GENERAL_ERROR      0x08
+#define LBCIF_STATUS_CHECKSUM_ERROR     0x40
+#define LBCIF_STATUS_EEPROM_PRESENT     0x80
+
+/* Miscellaneous Constraints */
+#define MAX_NUM_REGISTER_POLLS          1000
+#define MAX_NUM_WRITE_RETRIES           2
+
+static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
+{
+        u32 reg;
+        int i;
+
+        /*
+         * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
+         *    bits 7,1:0 both equal to 1, at least once after reset.
+         *    Subsequent operations need only to check that bits 1:0 are equal
+         *    to 1 prior to starting a single byte read/write
+         */
+
+        for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
+                /* Read registers grouped in DWORD1 */
+                if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
+                        return -EIO;
+
+                /* I2C idle and Phy Queue Avail both true */
+                if ((reg & 0x3000) == 0x3000) {
+                        if (status)
+                                *status = reg;
+                        return reg & 0xFF;
+                }
+        }
+        return -ETIMEDOUT;
+}
+
+
+/**
+ * eeprom_write - Write a byte to the ET1310's EEPROM
+ * @etdev: pointer to our private adapter structure
+ * @addr: the address to write
+ * @data: the value to write
+ *
+ * Returns 1 for a successful write.
+ */
+static int eeprom_write(struct et131x_adapter *etdev, u32 addr, u8 data)
+{
+        struct pci_dev *pdev = etdev->pdev;
+        int index = 0;
+        int retries;
+        int err = 0;
+        int i2c_wack = 0;
+        int writeok = 0;
+        u32 status;
+        u32 val = 0;
+
+        /*
+         * For an EEPROM, an I2C single byte write is defined as a START
+         * condition followed by the device address, EEPROM address, one byte
+         * of data and a STOP condition.  The STOP condition will trigger the
+         * EEPROM's internally timed write cycle to the nonvolatile memory.
+         * All inputs are disabled during this write cycle and the EEPROM will
+         * not respond to any access until the internal write is complete.
+         */
+
+        err = eeprom_wait_ready(pdev, NULL);
+        if (err)
+                return err;
+
+         /*
+         * 2. Write to the LBCIF Control Register:  bit 7=1, bit 6=1, bit 3=0,
+         *    and bits 1:0 both =0.  Bit 5 should be set according to the
+         *    type of EEPROM being accessed (1=two byte addressing, 0=one
+         *    byte addressing).
+         */
+        if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
+                        LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
+                return -EIO;
+
+        i2c_wack = 1;
+
+        /* Prepare EEPROM address for Step 3 */
+
+        for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
+                /* Write the address to the LBCIF Address Register */
+                if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
+                        break;
+                /*
+                 * Write the data to the LBCIF Data Register (the I2C write
+                 * will begin).
+                 */
+                if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
+                        break;
+                /*
+                 * Monitor bit 1:0 of the LBCIF Status Register.  When bits
+                 * 1:0 are both equal to 1, the I2C write has completed and the
+                 * internal write cycle of the EEPROM is about to start.
+                 * (bits 1:0 = 01 is a legal state while waiting from both
+                 * equal to 1, but bits 1:0 = 10 is invalid and implies that
+                 * something is broken).
+                 */
+                err = eeprom_wait_ready(pdev, &status);
+                if (err < 0)
+                        return 0;
+
+                /*
+                 * Check bit 3 of the LBCIF Status Register.  If  equal to 1,
+                 * an error has occurred.Don't break here if we are revision
+                 * 1, this is so we do a blind write for load bug.
+                 */
+                if ((status & LBCIF_STATUS_GENERAL_ERROR)
+                        && etdev->pdev->revision == 0)
+                        break;
+
+                /*
+                 * Check bit 2 of the LBCIF Status Register.  If equal to 1 an
+                 * ACK error has occurred on the address phase of the write.
+                 * This could be due to an actual hardware failure or the
+                 * EEPROM may still be in its internal write cycle from a
+                 * previous write. This write operation was ignored and must be
+                  *repeated later.
+                 */
+                if (status & LBCIF_STATUS_ACK_ERROR) {
+                        /*
+                         * This could be due to an actual hardware failure
+                         * or the EEPROM may still be in its internal write
+                         * cycle from a previous write. This write operation
+                         * was ignored and must be repeated later.
+                         */
+                        udelay(10);
+                        continue;
+                }
+
+                writeok = 1;
+                break;
+        }
+
+        /*
+         * Set bit 6 of the LBCIF Control Register = 0.
+         */
+        udelay(10);
+
+        while (i2c_wack) {
+                if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
+                        LBCIF_CONTROL_LBCIF_ENABLE))
+                        writeok = 0;
+
+                /* Do read until internal ACK_ERROR goes away meaning write
+                 * completed
+                 */
+                do {
+                        pci_write_config_dword(pdev,
+                                               LBCIF_ADDRESS_REGISTER,
+                                               addr);
+                        do {
+                                pci_read_config_dword(pdev,
+                                        LBCIF_DATA_REGISTER, &val);
+                        } while ((val & 0x00010000) == 0);
+                } while (val & 0x00040000);
+
+                if ((val & 0xFF00) != 0xC000 || index == 10000)
+                        break;
+                index++;
+        }
+        return writeok ? 0 : -EIO;
+}
+
+/**
+ * eeprom_read - Read a byte from the ET1310's EEPROM
+ * @etdev: pointer to our private adapter structure
+ * @addr: the address from which to read
+ * @pdata: a pointer to a byte in which to store the value of the read
+ * @eeprom_id: the ID of the EEPROM
+ * @addrmode: how the EEPROM is to be accessed
+ *
+ * Returns 1 for a successful read
+ */
+static int eeprom_read(struct et131x_adapter *etdev, u32 addr, u8 *pdata)
+{
+        struct pci_dev *pdev = etdev->pdev;
+        int err;
+        u32 status;
+
+        /*
+         * A single byte read is similar to the single byte write, with the
+         * exception of the data flow:
+         */
+
+        err = eeprom_wait_ready(pdev, NULL);
+        if (err)
+                return err;
+        /*
+         * Write to the LBCIF Control Register:  bit 7=1, bit 6=0, bit 3=0,
+         * and bits 1:0 both =0.  Bit 5 should be set according to the type
+         * of EEPROM being accessed (1=two byte addressing, 0=one byte
+         * addressing).
+         */
+        if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
+                                  LBCIF_CONTROL_LBCIF_ENABLE))
+                return -EIO;
+        /*
+         * Write the address to the LBCIF Address Register (I2C read will
+         * begin).
+         */
+        if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
+                return -EIO;
+        /*
+         * Monitor bit 0 of the LBCIF Status Register.  When = 1, I2C read
+         * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
+         * has occurred).
+         */
+        err = eeprom_wait_ready(pdev, &status);
+        if (err < 0)
+                return err;
+        /*
+         * Regardless of error status, read data byte from LBCIF Data
+         * Register.
+         */
+        *pdata = err;
+        /*
+         * Check bit 2 of the LBCIF Status Register.  If = 1,
+         * then an error has occurred.
+         */
+        return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
+}
+
+int et131x_init_eeprom(struct et131x_adapter *etdev)
+{
+        struct pci_dev *pdev = etdev->pdev;
+        u8 eestatus;
+
+        /* We first need to check the EEPROM Status code located at offset
+         * 0xB2 of config space
+         */
+        pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
+                                      &eestatus);
+
+        /* THIS IS A WORKAROUND:
+         * I need to call this function twice to get my card in a
+         * LG M1 Express Dual running. I tried also a msleep before this
+         * function, because I thougth there could be some time condidions
+         * but it didn't work. Call the whole function twice also work.
+         */
+        if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
+                dev_err(&pdev->dev,
+                       "Could not read PCI config space for EEPROM Status\n");
+                return -EIO;
+        }
+
+        /* Determine if the error(s) we care about are present. If they are
+         * present we need to fail.
+         */
+        if (eestatus & 0x4C) {
+                int write_failed = 0;
+                if (pdev->revision == 0x01) {
+                        int     i;
+                        static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
+
+                        /* Re-write the first 4 bytes if we have an eeprom
+                         * present and the revision id is 1, this fixes the
+                         * corruption seen with 1310 B Silicon
+                         */
+                        for (i = 0; i < 3; i++)
+                                if (eeprom_write(etdev, i, eedata[i]) < 0)
+                                        write_failed = 1;
+                }
+                if (pdev->revision  != 0x01 || write_failed) {
+                        dev_err(&pdev->dev,
+                            "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
+
+                        /* This error could mean that there was an error
+                         * reading the eeprom or that the eeprom doesn't exist.
+                         * We will treat each case the same and not try to
+                         * gather additional information that normally would
+                         * come from the eeprom, like MAC Address
+                         */
+                        etdev->has_eeprom = 0;
+                        return -EIO;
+                }
+        }
+        etdev->has_eeprom = 1;
+
+        /* Read the EEPROM for information regarding LED behavior. Refer to
+         * ET1310_phy.c, et131x_xcvr_init(), for its use.
+         */
+        eeprom_read(etdev, 0x70, &etdev->eeprom_data[0]);
+        eeprom_read(etdev, 0x71, &etdev->eeprom_data[1]);
+
+        if (etdev->eeprom_data[0] != 0xcd)
+                /* Disable all optional features */
+                etdev->eeprom_data[1] = 0x00;
+
+        return 0;
+}
diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c
new file mode 100644
index 00000000000..656be4b99cf
--- /dev/null
+++ b/drivers/staging/et131x/et1310_mac.c
@@ -0,0 +1,654 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_mac.c - All code and routines pertaining to the MAC
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+
+#include "et1310_phy.h"
+#include "et131x_adapter.h"
+#include "et131x.h"
+
+
+#define COUNTER_WRAP_28_BIT 0x10000000
+#define COUNTER_WRAP_22_BIT 0x400000
+#define COUNTER_WRAP_16_BIT 0x10000
+#define COUNTER_WRAP_12_BIT 0x1000
+
+#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
+#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
+#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
+#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
+
+/**
+ * ConfigMacRegs1 - Initialize the first part of MAC regs
+ * @pAdpater: pointer to our adapter structure
+ */
+void ConfigMACRegs1(struct et131x_adapter *etdev)
+{
+        struct mac_regs __iomem *pMac = &etdev->regs->mac;
+        u32 station1;
+        u32 station2;
+        u32 ipg;
+
+        /* First we need to reset everything.  Write to MAC configuration
+         * register 1 to perform reset.
+         */
+        writel(0xC00F0000, &pMac->cfg1);
+
+        /* Next lets configure the MAC Inter-packet gap register */
+        ipg = 0x38005860;               /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
+        ipg |= 0x50 << 8;               /* ifg enforce 0x50 */
+        writel(ipg, &pMac->ipg);
+
+        /* Next lets configure the MAC Half Duplex register */
+        /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
+        writel(0x00A1F037, &pMac->hfdp);
+
+        /* Next lets configure the MAC Interface Control register */
+        writel(0, &pMac->if_ctrl);
+
+        /* Let's move on to setting up the mii management configuration */
+        writel(0x07, &pMac->mii_mgmt_cfg);      /* Clock reset 0x7 */
+
+        /* Next lets configure the MAC Station Address register.  These
+         * values are read from the EEPROM during initialization and stored
+         * in the adapter structure.  We write what is stored in the adapter
+         * structure to the MAC Station Address registers high and low.  This
+         * station address is used for generating and checking pause control
+         * packets.
+         */
+        station2 = (etdev->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
+                   (etdev->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
+        station1 = (etdev->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
+                   (etdev->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
+                   (etdev->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
+                    etdev->addr[2];
+        writel(station1, &pMac->station_addr_1);
+        writel(station2, &pMac->station_addr_2);
+
+        /* Max ethernet packet in bytes that will passed by the mac without
+         * being truncated.  Allow the MAC to pass 4 more than our max packet
+         * size.  This is 4 for the Ethernet CRC.
+         *
+         * Packets larger than (RegistryJumboPacket) that do not contain a
+         * VLAN ID will be dropped by the Rx function.
+         */
+        writel(etdev->RegistryJumboPacket + 4, &pMac->max_fm_len);
+
+        /* clear out MAC config reset */
+        writel(0, &pMac->cfg1);
+}
+
+/**
+ * ConfigMacRegs2 - Initialize the second part of MAC regs
+ * @pAdpater: pointer to our adapter structure
+ */
+void ConfigMACRegs2(struct et131x_adapter *etdev)
+{
+        int32_t delay = 0;
+        struct mac_regs __iomem *pMac = &etdev->regs->mac;
+        u32 cfg1;
+        u32 cfg2;
+        u32 ifctrl;
+        u32 ctl;
+
+        ctl = readl(&etdev->regs->txmac.ctl);
+        cfg1 = readl(&pMac->cfg1);
+        cfg2 = readl(&pMac->cfg2);
+        ifctrl = readl(&pMac->if_ctrl);
+
+        /* Set up the if mode bits */
+        cfg2 &= ~0x300;
+        if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
+                cfg2 |= 0x200;
+                /* Phy mode bit */
+                ifctrl &= ~(1 << 24);
+        } else {
+                cfg2 |= 0x100;
+                ifctrl |= (1 << 24);
+        }
+
+        /* We need to enable Rx/Tx */
+        cfg1 |= CFG1_RX_ENABLE|CFG1_TX_ENABLE|CFG1_TX_FLOW;
+        /* Initialize loop back to off */
+        cfg1 &= ~(CFG1_LOOPBACK|CFG1_RX_FLOW);
+        if (etdev->flowcontrol == FLOW_RXONLY || etdev->flowcontrol == FLOW_BOTH)
+                cfg1 |= CFG1_RX_FLOW;
+        writel(cfg1, &pMac->cfg1);
+
+        /* Now we need to initialize the MAC Configuration 2 register */
+        /* preamble 7, check length, huge frame off, pad crc, crc enable
+           full duplex off */
+        cfg2 |= 0x7016;
+        cfg2 &= ~0x0021;
+
+        /* Turn on duplex if needed */
+        if (etdev->duplex_mode)
+                cfg2 |= 0x01;
+
+        ifctrl &= ~(1 << 26);
+        if (!etdev->duplex_mode)
+                ifctrl |= (1<<26);      /* Enable ghd */
+
+        writel(ifctrl, &pMac->if_ctrl);
+        writel(cfg2, &pMac->cfg2);
+
+        do {
+                udelay(10);
+                delay++;
+                cfg1 = readl(&pMac->cfg1);
+        } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
+
+        if (delay == 100) {
+                dev_warn(&etdev->pdev->dev,
+                    "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
+                        cfg1);
+        }
+
+        /* Enable TXMAC */
+        ctl |= 0x09;    /* TX mac enable, FC disable */
+        writel(ctl, &etdev->regs->txmac.ctl);
+
+        /* Ready to start the RXDMA/TXDMA engine */
+        if (etdev->flags & fMP_ADAPTER_LOWER_POWER) {
+                et131x_rx_dma_enable(etdev);
+                et131x_tx_dma_enable(etdev);
+        }
+}
+
+void ConfigRxMacRegs(struct et131x_adapter *etdev)
+{
+        struct rxmac_regs __iomem *pRxMac = &etdev->regs->rxmac;
+        u32 sa_lo;
+        u32 sa_hi = 0;
+        u32 pf_ctrl = 0;
+
+        /* Disable the MAC while it is being configured (also disable WOL) */
+        writel(0x8, &pRxMac->ctrl);
+
+        /* Initialize WOL to disabled. */
+        writel(0, &pRxMac->crc0);
+        writel(0, &pRxMac->crc12);
+        writel(0, &pRxMac->crc34);
+
+        /* We need to set the WOL mask0 - mask4 next.  We initialize it to
+         * its default Values of 0x00000000 because there are not WOL masks
+         * as of this time.
+         */
+        writel(0, &pRxMac->mask0_word0);
+        writel(0, &pRxMac->mask0_word1);
+        writel(0, &pRxMac->mask0_word2);
+        writel(0, &pRxMac->mask0_word3);
+
+        writel(0, &pRxMac->mask1_word0);
+        writel(0, &pRxMac->mask1_word1);
+        writel(0, &pRxMac->mask1_word2);
+        writel(0, &pRxMac->mask1_word3);
+
+        writel(0, &pRxMac->mask2_word0);
+        writel(0, &pRxMac->mask2_word1);
+        writel(0, &pRxMac->mask2_word2);
+        writel(0, &pRxMac->mask2_word3);
+
+        writel(0, &pRxMac->mask3_word0);
+        writel(0, &pRxMac->mask3_word1);
+        writel(0, &pRxMac->mask3_word2);
+        writel(0, &pRxMac->mask3_word3);
+
+        writel(0, &pRxMac->mask4_word0);
+        writel(0, &pRxMac->mask4_word1);
+        writel(0, &pRxMac->mask4_word2);
+        writel(0, &pRxMac->mask4_word3);
+
+        /* Lets setup the WOL Source Address */
+        sa_lo = (etdev->addr[2] << ET_WOL_LO_SA3_SHIFT) |
+                (etdev->addr[3] << ET_WOL_LO_SA4_SHIFT) |
+                (etdev->addr[4] << ET_WOL_LO_SA5_SHIFT) |
+                 etdev->addr[5];
+        writel(sa_lo, &pRxMac->sa_lo);
+
+        sa_hi = (u32) (etdev->addr[0] << ET_WOL_HI_SA1_SHIFT) |
+                       etdev->addr[1];
+        writel(sa_hi, &pRxMac->sa_hi);
+
+        /* Disable all Packet Filtering */
+        writel(0, &pRxMac->pf_ctrl);
+
+        /* Let's initialize the Unicast Packet filtering address */
+        if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
+                SetupDeviceForUnicast(etdev);
+                pf_ctrl |= 4;   /* Unicast filter */
+        } else {
+                writel(0, &pRxMac->uni_pf_addr1);
+                writel(0, &pRxMac->uni_pf_addr2);
+                writel(0, &pRxMac->uni_pf_addr3);
+        }
+
+        /* Let's initialize the Multicast hash */
+        if (!(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
+                pf_ctrl |= 2;   /* Multicast filter */
+                SetupDeviceForMulticast(etdev);
+        }
+
+        /* Runt packet filtering.  Didn't work in version A silicon. */
+        pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
+        pf_ctrl |= 8;   /* Fragment filter */
+
+        if (etdev->RegistryJumboPacket > 8192)
+                /* In order to transmit jumbo packets greater than 8k, the
+                 * FIFO between RxMAC and RxDMA needs to be reduced in size
+                 * to (16k - Jumbo packet size).  In order to implement this,
+                 * we must use "cut through" mode in the RxMAC, which chops
+                 * packets down into segments which are (max_size * 16).  In
+                 * this case we selected 256 bytes, since this is the size of
+                 * the PCI-Express TLP's that the 1310 uses.
+                 *
+                 * seg_en on, fc_en off, size 0x10
+                 */
+                writel(0x41, &pRxMac->mcif_ctrl_max_seg);
+        else
+                writel(0, &pRxMac->mcif_ctrl_max_seg);
+
+        /* Initialize the MCIF water marks */
+        writel(0, &pRxMac->mcif_water_mark);
+
+        /*  Initialize the MIF control */
+        writel(0, &pRxMac->mif_ctrl);
+
+        /* Initialize the Space Available Register */
+        writel(0, &pRxMac->space_avail);
+
+        /* Initialize the the mif_ctrl register
+         * bit 3:  Receive code error. One or more nibbles were signaled as
+         *         errors  during the reception of the packet.  Clear this
+         *         bit in Gigabit, set it in 100Mbit.  This was derived
+         *         experimentally at UNH.
+         * bit 4:  Receive CRC error. The packet's CRC did not match the
+         *         internally generated CRC.
+         * bit 5:  Receive length check error. Indicates that frame length
+         *         field value in the packet does not match the actual data
+         *         byte length and is not a type field.
+         * bit 16: Receive frame truncated.
+         * bit 17: Drop packet enable
+         */
+        if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS)
+                writel(0x30038, &pRxMac->mif_ctrl);
+        else
+                writel(0x30030, &pRxMac->mif_ctrl);
+
+        /* Finally we initialize RxMac to be enabled & WOL disabled.  Packet
+         * filter is always enabled since it is where the runt packets are
+         * supposed to be dropped.  For version A silicon, runt packet
+         * dropping doesn't work, so it is disabled in the pf_ctrl register,
+         * but we still leave the packet filter on.
+         */
+        writel(pf_ctrl, &pRxMac->pf_ctrl);
+        writel(0x9, &pRxMac->ctrl);
+}
+
+void ConfigTxMacRegs(struct et131x_adapter *etdev)
+{
+        struct txmac_regs *txmac = &etdev->regs->txmac;
+
+        /* We need to update the Control Frame Parameters
+         * cfpt - control frame pause timer set to 64 (0x40)
+         * cfep - control frame extended pause timer set to 0x0
+         */
+        if (etdev->flowcontrol == FLOW_NONE)
+                writel(0, &txmac->cf_param);
+        else
+                writel(0x40, &txmac->cf_param);
+}
+
+void ConfigMacStatRegs(struct et131x_adapter *etdev)
+{
+        struct macstat_regs __iomem *macstat =
+                &etdev->regs->macstat;
+
+        /* Next we need to initialize all the macstat registers to zero on
+         * the device.
+         */
+        writel(0, &macstat->txrx_0_64_byte_frames);
+        writel(0, &macstat->txrx_65_127_byte_frames);
+        writel(0, &macstat->txrx_128_255_byte_frames);
+        writel(0, &macstat->txrx_256_511_byte_frames);
+        writel(0, &macstat->txrx_512_1023_byte_frames);
+        writel(0, &macstat->txrx_1024_1518_byte_frames);
+        writel(0, &macstat->txrx_1519_1522_gvln_frames);
+
+        writel(0, &macstat->rx_bytes);
+        writel(0, &macstat->rx_packets);
+        writel(0, &macstat->rx_fcs_errs);
+        writel(0, &macstat->rx_multicast_packets);
+        writel(0, &macstat->rx_broadcast_packets);
+        writel(0, &macstat->rx_control_frames);
+        writel(0, &macstat->rx_pause_frames);
+        writel(0, &macstat->rx_unknown_opcodes);
+        writel(0, &macstat->rx_align_errs);
+        writel(0, &macstat->rx_frame_len_errs);
+        writel(0, &macstat->rx_code_errs);
+        writel(0, &macstat->rx_carrier_sense_errs);
+        writel(0, &macstat->rx_undersize_packets);
+        writel(0, &macstat->rx_oversize_packets);
+        writel(0, &macstat->rx_fragment_packets);
+        writel(0, &macstat->rx_jabbers);
+        writel(0, &macstat->rx_drops);
+
+        writel(0, &macstat->tx_bytes);
+        writel(0, &macstat->tx_packets);
+        writel(0, &macstat->tx_multicast_packets);
+        writel(0, &macstat->tx_broadcast_packets);
+        writel(0, &macstat->tx_pause_frames);
+        writel(0, &macstat->tx_deferred);
+        writel(0, &macstat->tx_excessive_deferred);
+        writel(0, &macstat->tx_single_collisions);
+        writel(0, &macstat->tx_multiple_collisions);
+        writel(0, &macstat->tx_late_collisions);
+        writel(0, &macstat->tx_excessive_collisions);
+        writel(0, &macstat->tx_total_collisions);
+        writel(0, &macstat->tx_pause_honored_frames);
+        writel(0, &macstat->tx_drops);
+        writel(0, &macstat->tx_jabbers);
+        writel(0, &macstat->tx_fcs_errs);
+        writel(0, &macstat->tx_control_frames);
+        writel(0, &macstat->tx_oversize_frames);
+        writel(0, &macstat->tx_undersize_frames);
+        writel(0, &macstat->tx_fragments);
+        writel(0, &macstat->carry_reg1);
+        writel(0, &macstat->carry_reg2);
+
+        /* Unmask any counters that we want to track the overflow of.
+         * Initially this will be all counters.  It may become clear later
+         * that we do not need to track all counters.
+         */
+        writel(0xFFFFBE32, &macstat->carry_reg1_mask);
+        writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
+}
+
+void ConfigFlowControl(struct et131x_adapter *etdev)
+{
+        if (etdev->duplex_mode == 0) {
+                etdev->flowcontrol = FLOW_NONE;
+        } else {
+                char remote_pause, remote_async_pause;
+
+                ET1310_PhyAccessMiBit(etdev,
+                                      TRUEPHY_BIT_READ, 5, 10, &remote_pause);
+                ET1310_PhyAccessMiBit(etdev,
+                                      TRUEPHY_BIT_READ, 5, 11,
+                                      &remote_async_pause);
+
+                if ((remote_pause == TRUEPHY_BIT_SET) &&
+                    (remote_async_pause == TRUEPHY_BIT_SET)) {
+                        etdev->flowcontrol = etdev->wanted_flow;
+                } else if ((remote_pause == TRUEPHY_BIT_SET) &&
+                           (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
+                        if (etdev->wanted_flow == FLOW_BOTH)
+                                etdev->flowcontrol = FLOW_BOTH;
+                        else
+                                etdev->flowcontrol = FLOW_NONE;
+                } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
+                           (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
+                        etdev->flowcontrol = FLOW_NONE;
+                } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
+                               remote_async_pause == TRUEPHY_SET_BIT) */
+                        if (etdev->wanted_flow == FLOW_BOTH)
+                                etdev->flowcontrol = FLOW_RXONLY;
+                        else
+                                etdev->flowcontrol = FLOW_NONE;
+                }
+        }
+}
+
+/**
+ * UpdateMacStatHostCounters - Update the local copy of the statistics
+ * @etdev: pointer to the adapter structure
+ */
+void UpdateMacStatHostCounters(struct et131x_adapter *etdev)
+{
+        struct ce_stats *stats = &etdev->stats;
+        struct macstat_regs __iomem *macstat =
+                &etdev->regs->macstat;
+
+        stats->collisions += readl(&macstat->tx_total_collisions);
+        stats->first_collision += readl(&macstat->tx_single_collisions);
+        stats->tx_deferred += readl(&macstat->tx_deferred);
+        stats->excessive_collisions += readl(&macstat->tx_multiple_collisions);
+        stats->late_collisions += readl(&macstat->tx_late_collisions);
+        stats->tx_uflo += readl(&macstat->tx_undersize_frames);
+        stats->max_pkt_error += readl(&macstat->tx_oversize_frames);
+
+        stats->alignment_err += readl(&macstat->rx_align_errs);
+        stats->crc_err += readl(&macstat->rx_code_errs);
+        stats->norcvbuf += readl(&macstat->rx_drops);
+        stats->rx_ov_flow += readl(&macstat->rx_oversize_packets);
+        stats->code_violations += readl(&macstat->rx_fcs_errs);
+        stats->length_err += readl(&macstat->rx_frame_len_errs);
+
+        stats->other_errors += readl(&macstat->rx_fragment_packets);
+}
+
+/**
+ * HandleMacStatInterrupt
+ * @etdev: pointer to the adapter structure
+ *
+ * One of the MACSTAT counters has wrapped.  Update the local copy of
+ * the statistics held in the adapter structure, checking the "wrap"
+ * bit for each counter.
+ */
+void HandleMacStatInterrupt(struct et131x_adapter *etdev)
+{
+        u32 carry_reg1;
+        u32 carry_reg2;
+
+        /* Read the interrupt bits from the register(s).  These are Clear On
+         * Write.
+         */
+        carry_reg1 = readl(&etdev->regs->macstat.carry_reg1);
+        carry_reg2 = readl(&etdev->regs->macstat.carry_reg2);
+
+        writel(carry_reg2, &etdev->regs->macstat.carry_reg1);
+        writel(carry_reg2, &etdev->regs->macstat.carry_reg2);
+
+        /* We need to do update the host copy of all the MAC_STAT counters.
+         * For each counter, check it's overflow bit.  If the overflow bit is
+         * set, then increment the host version of the count by one complete
+         * revolution of the counter.  This routine is called when the counter
+         * block indicates that one of the counters has wrapped.
+         */
+        if (carry_reg1 & (1 << 14))
+                etdev->stats.code_violations += COUNTER_WRAP_16_BIT;
+        if (carry_reg1 & (1 << 8))
+                etdev->stats.alignment_err += COUNTER_WRAP_12_BIT;
+        if (carry_reg1 & (1 << 7))
+                etdev->stats.length_err += COUNTER_WRAP_16_BIT;
+        if (carry_reg1 & (1 << 2))
+                etdev->stats.other_errors += COUNTER_WRAP_16_BIT;
+        if (carry_reg1 & (1 << 6))
+                etdev->stats.crc_err += COUNTER_WRAP_16_BIT;
+        if (carry_reg1 & (1 << 3))
+                etdev->stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
+        if (carry_reg1 & (1 << 0))
+                etdev->stats.norcvbuf += COUNTER_WRAP_16_BIT;
+        if (carry_reg2 & (1 << 16))
+                etdev->stats.max_pkt_error += COUNTER_WRAP_12_BIT;
+        if (carry_reg2 & (1 << 15))
+                etdev->stats.tx_uflo += COUNTER_WRAP_12_BIT;
+        if (carry_reg2 & (1 << 6))
+                etdev->stats.first_collision += COUNTER_WRAP_12_BIT;
+        if (carry_reg2 & (1 << 8))
+                etdev->stats.tx_deferred += COUNTER_WRAP_12_BIT;
+        if (carry_reg2 & (1 << 5))
+                etdev->stats.excessive_collisions += COUNTER_WRAP_12_BIT;
+        if (carry_reg2 & (1 << 4))
+                etdev->stats.late_collisions += COUNTER_WRAP_12_BIT;
+        if (carry_reg2 & (1 << 2))
+                etdev->stats.collisions += COUNTER_WRAP_12_BIT;
+}
+
+void SetupDeviceForMulticast(struct et131x_adapter *etdev)
+{
+        struct rxmac_regs __iomem *rxmac = &etdev->regs->rxmac;
+        uint32_t nIndex;
+        uint32_t result;
+        uint32_t hash1 = 0;
+        uint32_t hash2 = 0;
+        uint32_t hash3 = 0;
+        uint32_t hash4 = 0;
+        u32 pm_csr;
+
+        /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
+         * the multi-cast LIST.  If it is NOT specified, (and "ALL" is not
+         * specified) then we should pass NO multi-cast addresses to the
+         * driver.
+         */
+        if (etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
+                /* Loop through our multicast array and set up the device */
+                for (nIndex = 0; nIndex < etdev->MCAddressCount; nIndex++) {
+                        result = ether_crc(6, etdev->MCList[nIndex]);
+
+                        result = (result & 0x3F800000) >> 23;
+
+                        if (result < 32) {
+                                hash1 |= (1 << result);
+                        } else if ((31 < result) && (result < 64)) {
+                                result -= 32;
+                                hash2 |= (1 << result);
+                        } else if ((63 < result) && (result < 96)) {
+                                result -= 64;
+                                hash3 |= (1 << result);
+                        } else {
+                                result -= 96;
+                                hash4 |= (1 << result);
+                        }
+                }
+        }
+
+        /* Write out the new hash to the device */
+        pm_csr = readl(&etdev->regs->global.pm_csr);
+        if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
+                writel(hash1, &rxmac->multi_hash1);
+                writel(hash2, &rxmac->multi_hash2);
+                writel(hash3, &rxmac->multi_hash3);
+                writel(hash4, &rxmac->multi_hash4);
+        }
+}
+
+void SetupDeviceForUnicast(struct et131x_adapter *etdev)
+{
+        struct rxmac_regs __iomem *rxmac = &etdev->regs->rxmac;
+        u32 uni_pf1;
+        u32 uni_pf2;
+        u32 uni_pf3;
+        u32 pm_csr;
+
+        /* Set up unicast packet filter reg 3 to be the first two octets of
+         * the MAC address for both address
+         *
+         * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
+         * MAC address for second address
+         *
+         * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
+         * MAC address for first address
+         */
+        uni_pf3 = (etdev->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) |
+                  (etdev->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) |
+                  (etdev->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) |
+                   etdev->addr[1];
+
+        uni_pf2 = (etdev->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) |
+                  (etdev->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) |
+                  (etdev->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) |
+                   etdev->addr[5];
+
+        uni_pf1 = (etdev->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) |
+                  (etdev->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) |
+                  (etdev->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) |
+                   etdev->addr[5];
+
+        pm_csr = readl(&etdev->regs->global.pm_csr);
+        if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
+                writel(uni_pf1, &rxmac->uni_pf_addr1);
+                writel(uni_pf2, &rxmac->uni_pf_addr2);
+                writel(uni_pf3, &rxmac->uni_pf_addr3);
+        }
+}
diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c
new file mode 100644
index 00000000000..0bcb7fb6e2c
--- /dev/null
+++ b/drivers/staging/et131x/et1310_phy.c
@@ -0,0 +1,979 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright * 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_phy.c - Routines for configuring and accessing the PHY
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright * 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+#include <linux/random.h>
+
+#include "et1310_phy.h"
+
+#include "et131x_adapter.h"
+
+#include "et1310_address_map.h"
+#include "et1310_tx.h"
+#include "et1310_rx.h"
+
+#include "et131x.h"
+
+/* Prototypes for functions with local scope */
+static void et131x_xcvr_init(struct et131x_adapter *etdev);
+
+/**
+ * PhyMiRead - Read from the PHY through the MII Interface on the MAC
+ * @etdev: pointer to our private adapter structure
+ * @xcvrAddr: the address of the transceiver
+ * @xcvrReg: the register to read
+ * @value: pointer to a 16-bit value in which the value will be stored
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr,
+              u8 xcvrReg, u16 *value)
+{
+        struct mac_regs __iomem *mac = &etdev->regs->mac;
+        int status = 0;
+        u32 delay;
+        u32 miiAddr;
+        u32 miiCmd;
+        u32 miiIndicator;
+
+        /* Save a local copy of the registers we are dealing with so we can
+         * set them back
+         */
+        miiAddr = readl(&mac->mii_mgmt_addr);
+        miiCmd = readl(&mac->mii_mgmt_cmd);
+
+        /* Stop the current operation */
+        writel(0, &mac->mii_mgmt_cmd);
+
+        /* Set up the register we need to read from on the correct PHY */
+        writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
+
+        /* Kick the read cycle off */
+        delay = 0;
+
+        writel(0x1, &mac->mii_mgmt_cmd);
+
+        do {
+                udelay(50);
+                delay++;
+                miiIndicator = readl(&mac->mii_mgmt_indicator);
+        } while ((miiIndicator & MGMT_WAIT) && delay < 50);
+
+        /* If we hit the max delay, we could not read the register */
+        if (delay == 50) {
+                dev_warn(&etdev->pdev->dev,
+                            "xcvrReg 0x%08x could not be read\n", xcvrReg);
+                dev_warn(&etdev->pdev->dev, "status is  0x%08x\n",
+                            miiIndicator);
+
+                status = -EIO;
+        }
+
+        /* If we hit here we were able to read the register and we need to
+         * return the value to the caller */
+        *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
+
+        /* Stop the read operation */
+        writel(0, &mac->mii_mgmt_cmd);
+
+        /* set the registers we touched back to the state at which we entered
+         * this function
+         */
+        writel(miiAddr, &mac->mii_mgmt_addr);
+        writel(miiCmd, &mac->mii_mgmt_cmd);
+
+        return status;
+}
+
+/**
+ * MiWrite - Write to a PHY register through the MII interface of the MAC
+ * @etdev: pointer to our private adapter structure
+ * @xcvrReg: the register to read
+ * @value: 16-bit value to write
+ *
+ * FIXME: one caller in netdev still
+ *
+ * Return 0 on success, errno on failure (as defined in errno.h)
+ */
+int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
+{
+        struct mac_regs __iomem *mac = &etdev->regs->mac;
+        int status = 0;
+        u8 xcvrAddr = etdev->stats.xcvr_addr;
+        u32 delay;
+        u32 miiAddr;
+        u32 miiCmd;
+        u32 miiIndicator;
+
+        /* Save a local copy of the registers we are dealing with so we can
+         * set them back
+         */
+        miiAddr = readl(&mac->mii_mgmt_addr);
+        miiCmd = readl(&mac->mii_mgmt_cmd);
+
+        /* Stop the current operation */
+        writel(0, &mac->mii_mgmt_cmd);
+
+        /* Set up the register we need to write to on the correct PHY */
+        writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
+
+        /* Add the value to write to the registers to the mac */
+        writel(value, &mac->mii_mgmt_ctrl);
+        delay = 0;
+
+        do {
+                udelay(50);
+                delay++;
+                miiIndicator = readl(&mac->mii_mgmt_indicator);
+        } while ((miiIndicator & MGMT_BUSY) && delay < 100);
+
+        /* If we hit the max delay, we could not write the register */
+        if (delay == 100) {
+                u16 TempValue;
+
+                dev_warn(&etdev->pdev->dev,
+                    "xcvrReg 0x%08x could not be written", xcvrReg);
+                dev_warn(&etdev->pdev->dev, "status is  0x%08x\n",
+                            miiIndicator);
+                dev_warn(&etdev->pdev->dev, "command is  0x%08x\n",
+                            readl(&mac->mii_mgmt_cmd));
+
+                MiRead(etdev, xcvrReg, &TempValue);
+
+                status = -EIO;
+        }
+        /* Stop the write operation */
+        writel(0, &mac->mii_mgmt_cmd);
+
+        /* set the registers we touched back to the state at which we entered
+         * this function
+         */
+        writel(miiAddr, &mac->mii_mgmt_addr);
+        writel(miiCmd, &mac->mii_mgmt_cmd);
+
+        return status;
+}
+
+/**
+ * et131x_xcvr_find - Find the PHY ID
+ * @etdev: pointer to our private adapter structure
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_xcvr_find(struct et131x_adapter *etdev)
+{
+        u8 xcvr_addr;
+        u16 idr1;
+        u16 idr2;
+        u32 xcvr_id;
+
+        /* We need to get xcvr id and address we just get the first one */
+        for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
+                /* Read the ID from the PHY */
+                PhyMiRead(etdev, xcvr_addr,
+                          (u8) offsetof(struct mi_regs, idr1),
+                          &idr1);
+                PhyMiRead(etdev, xcvr_addr,
+                          (u8) offsetof(struct mi_regs, idr2),
+                          &idr2);
+
+                xcvr_id = (u32) ((idr1 << 16) | idr2);
+
+                if (idr1 != 0 && idr1 != 0xffff) {
+                        etdev->stats.xcvr_id = xcvr_id;
+                        etdev->stats.xcvr_addr = xcvr_addr;
+                        return 0;
+                }
+        }
+        return -ENODEV;
+}
+
+void ET1310_PhyReset(struct et131x_adapter *etdev)
+{
+        MiWrite(etdev, PHY_CONTROL, 0x8000);
+}
+
+/**
+ *      ET1310_PhyPowerDown     -       PHY power control
+ *      @etdev: device to control
+ *      @down: true for off/false for back on
+ *
+ *      one hundred, ten, one thousand megs
+ *      How would you like to have your LAN accessed
+ *      Can't you see that this code processed
+ *      Phy power, phy power..
+ */
+
+void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
+{
+        u16 data;
+
+        MiRead(etdev, PHY_CONTROL, &data);
+        data &= ~0x0800;        /* Power UP */
+        if (down) /* Power DOWN */
+                data |= 0x0800;
+        MiWrite(etdev, PHY_CONTROL, data);
+}
+
+/**
+ *      ET130_PhyAutoNEg        -       autonegotiate control
+ *      @etdev: device to control
+ *      @enabe: autoneg on/off
+ *
+ *      Set up the autonegotiation state according to whether we will be
+ *      negotiating the state or forcing a speed.
+ */
+
+static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
+{
+        u16 data;
+
+        MiRead(etdev, PHY_CONTROL, &data);
+        data &= ~0x1000;        /* Autonegotiation OFF */
+        if (enable)
+                data |= 0x1000;         /* Autonegotiation ON */
+        MiWrite(etdev, PHY_CONTROL, data);
+}
+
+/**
+ *      ET130_PhyDuplexMode     -       duplex control
+ *      @etdev: device to control
+ *      @duplex: duplex on/off
+ *
+ *      Set up the duplex state on the PHY
+ */
+
+static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
+{
+        u16 data;
+
+        MiRead(etdev, PHY_CONTROL, &data);
+        data &= ~0x100;         /* Set Half Duplex */
+        if (duplex == TRUEPHY_DUPLEX_FULL)
+                data |= 0x100;  /* Set Full Duplex */
+        MiWrite(etdev, PHY_CONTROL, data);
+}
+
+/**
+ *      ET130_PhySpeedSelect    -       speed control
+ *      @etdev: device to control
+ *      @duplex: duplex on/off
+ *
+ *      Set the speed of our PHY.
+ */
+
+static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
+{
+        u16 data;
+        static const u16 bits[3] = {0x0000, 0x2000, 0x0040};
+
+        /* Read the PHY control register */
+        MiRead(etdev, PHY_CONTROL, &data);
+        /* Clear all Speed settings (Bits 6, 13) */
+        data &= ~0x2040;
+        /* Write back the new speed */
+        MiWrite(etdev, PHY_CONTROL, data | bits[speed]);
+}
+
+/**
+ *      ET1310_PhyLinkStatus    -       read link state
+ *      @etdev: device to read
+ *      @link_status: reported link state
+ *      @autoneg: reported autonegotiation state (complete/incomplete/disabled)
+ *      @linkspeed: returnedlink speed in use
+ *      @duplex_mode: reported half/full duplex state
+ *      @mdi_mdix: not yet working
+ *      @masterslave: report whether we are master or slave
+ *      @polarity: link polarity
+ *
+ *      I can read your lan like a magazine
+ *      I see if your up
+ *      I know your link speed
+ *      I see all the setting that you'd rather keep
+ */
+
+static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
+                          u8 *link_status,
+                          u32 *autoneg,
+                          u32 *linkspeed,
+                          u32 *duplex_mode,
+                          u32 *mdi_mdix,
+                          u32 *masterslave, u32 *polarity)
+{
+        u16 mistatus = 0;
+        u16 is1000BaseT = 0;
+        u16 vmi_phystatus = 0;
+        u16 control = 0;
+
+        MiRead(etdev, PHY_STATUS, &mistatus);
+        MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
+        MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
+        MiRead(etdev, PHY_CONTROL, &control);
+
+        *link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
+        *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
+                                            TRUEPHY_ANEG_COMPLETE :
+                                            TRUEPHY_ANEG_NOT_COMPLETE) :
+                    TRUEPHY_ANEG_DISABLED;
+        *linkspeed = (vmi_phystatus & 0x0300) >> 8;
+        *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
+        /* NOTE: Need to complete this */
+        *mdi_mdix = 0;
+
+        *masterslave = (is1000BaseT & 0x4000) ?
+                        TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
+        *polarity = (vmi_phystatus & 0x0400) ?
+                        TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
+}
+
+static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
+                        u16 regnum, u16 andMask, u16 orMask)
+{
+        u16 reg;
+
+        MiRead(etdev, regnum, &reg);
+        reg &= andMask;
+        reg |= orMask;
+        MiWrite(etdev, regnum, reg);
+}
+
+/* Still used from _mac  for BIT_READ */
+void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
+                           u16 regnum, u16 bitnum, u8 *value)
+{
+        u16 reg;
+        u16 mask = 0x0001 << bitnum;
+
+        /* Read the requested register */
+        MiRead(etdev, regnum, &reg);
+
+        switch (action) {
+        case TRUEPHY_BIT_READ:
+                *value = (reg & mask) >> bitnum;
+                break;
+
+        case TRUEPHY_BIT_SET:
+                MiWrite(etdev, regnum, reg | mask);
+                break;
+
+        case TRUEPHY_BIT_CLEAR:
+                MiWrite(etdev, regnum, reg & ~mask);
+                break;
+
+        default:
+                break;
+        }
+}
+
+void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
+                                  u16 duplex)
+{
+        u16 data;
+
+        /* Read the PHY 1000 Base-T Control Register */
+        MiRead(etdev, PHY_1000_CONTROL, &data);
+
+        /* Clear Bits 8,9 */
+        data &= ~0x0300;
+
+        switch (duplex) {
+        case TRUEPHY_ADV_DUPLEX_NONE:
+                /* Duplex already cleared, do nothing */
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_FULL:
+                /* Set Bit 9 */
+                data |= 0x0200;
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_HALF:
+                /* Set Bit 8 */
+                data |= 0x0100;
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_BOTH:
+        default:
+                data |= 0x0300;
+                break;
+        }
+
+        /* Write back advertisement */
+        MiWrite(etdev, PHY_1000_CONTROL, data);
+}
+
+static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
+                                 u16 duplex)
+{
+        u16 data;
+
+        /* Read the Autonegotiation Register (10/100) */
+        MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
+
+        /* Clear bits 7,8 */
+        data &= ~0x0180;
+
+        switch (duplex) {
+        case TRUEPHY_ADV_DUPLEX_NONE:
+                /* Duplex already cleared, do nothing */
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_FULL:
+                /* Set Bit 8 */
+                data |= 0x0100;
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_HALF:
+                /* Set Bit 7 */
+                data |= 0x0080;
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_BOTH:
+        default:
+                /* Set Bits 7,8 */
+                data |= 0x0180;
+                break;
+        }
+
+        /* Write back advertisement */
+        MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
+}
+
+static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
+                                u16 duplex)
+{
+        u16 data;
+
+        /* Read the Autonegotiation Register (10/100) */
+        MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
+
+        /* Clear bits 5,6 */
+        data &= ~0x0060;
+
+        switch (duplex) {
+        case TRUEPHY_ADV_DUPLEX_NONE:
+                /* Duplex already cleared, do nothing */
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_FULL:
+                /* Set Bit 6 */
+                data |= 0x0040;
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_HALF:
+                /* Set Bit 5 */
+                data |= 0x0020;
+                break;
+
+        case TRUEPHY_ADV_DUPLEX_BOTH:
+        default:
+                /* Set Bits 5,6 */
+                data |= 0x0060;
+                break;
+        }
+
+        /* Write back advertisement */
+        MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
+}
+
+/**
+ * et131x_setphy_normal - Set PHY for normal operation.
+ * @etdev: pointer to our private adapter structure
+ *
+ * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
+ * when going to D3 in WOL mode. Also used during initialization to set the
+ * PHY for normal operation.
+ */
+void et131x_setphy_normal(struct et131x_adapter *etdev)
+{
+        /* Make sure the PHY is powered up */
+        ET1310_PhyPowerDown(etdev, 0);
+        et131x_xcvr_init(etdev);
+}
+
+
+/**
+ * et131x_xcvr_init - Init the phy if we are setting it into force mode
+ * @etdev: pointer to our private adapter structure
+ *
+ */
+static void et131x_xcvr_init(struct et131x_adapter *etdev)
+{
+        u16 imr;
+        u16 isr;
+        u16 lcr2;
+
+        /* Zero out the adapter structure variable representing BMSR */
+        etdev->bmsr = 0;
+
+        MiRead(etdev, (u8) offsetof(struct mi_regs, isr), &isr);
+        MiRead(etdev, (u8) offsetof(struct mi_regs, imr), &imr);
+
+        /* Set the link status interrupt only.  Bad behavior when link status
+         * and auto neg are set, we run into a nested interrupt problem
+         */
+        imr |= 0x0105;
+
+        MiWrite(etdev, (u8) offsetof(struct mi_regs, imr), imr);
+
+        /* Set the LED behavior such that LED 1 indicates speed (off =
+         * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
+         * link and activity (on for link, blink off for activity).
+         *
+         * NOTE: Some customizations have been added here for specific
+         * vendors; The LED behavior is now determined by vendor data in the
+         * EEPROM. However, the above description is the default.
+         */
+        if ((etdev->eeprom_data[1] & 0x4) == 0) {
+                MiRead(etdev, (u8) offsetof(struct mi_regs, lcr2),
+                       &lcr2);
+
+                lcr2 &= 0x00FF;
+                lcr2 |= 0xA000; /* led link */
+
+                if ((etdev->eeprom_data[1] & 0x8) == 0)
+                        lcr2 |= 0x0300;
+                else
+                        lcr2 |= 0x0400;
+
+                MiWrite(etdev, (u8) offsetof(struct mi_regs, lcr2),
+                        lcr2);
+        }
+
+        /* Determine if we need to go into a force mode and set it */
+        if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
+                if (etdev->wanted_flow == FLOW_TXONLY ||
+                    etdev->wanted_flow == FLOW_BOTH)
+                        ET1310_PhyAccessMiBit(etdev,
+                                              TRUEPHY_BIT_SET, 4, 11, NULL);
+                else
+                        ET1310_PhyAccessMiBit(etdev,
+                                              TRUEPHY_BIT_CLEAR, 4, 11, NULL);
+
+                if (etdev->wanted_flow == FLOW_BOTH)
+                        ET1310_PhyAccessMiBit(etdev,
+                                              TRUEPHY_BIT_SET, 4, 10, NULL);
+                else
+                        ET1310_PhyAccessMiBit(etdev,
+                                              TRUEPHY_BIT_CLEAR, 4, 10, NULL);
+
+                /* Set the phy to autonegotiation */
+                ET1310_PhyAutoNeg(etdev, true);
+
+                /* NOTE - Do we need this? */
+                ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL);
+                return;
+        }
+
+        ET1310_PhyAutoNeg(etdev, false);
+
+        /* Set to the correct force mode. */
+        if (etdev->AiForceDpx != 1) {
+                if (etdev->wanted_flow == FLOW_TXONLY ||
+                    etdev->wanted_flow == FLOW_BOTH)
+                        ET1310_PhyAccessMiBit(etdev,
+                                      TRUEPHY_BIT_SET, 4, 11, NULL);
+                else
+                        ET1310_PhyAccessMiBit(etdev,
+                                              TRUEPHY_BIT_CLEAR, 4, 11, NULL);
+
+                if (etdev->wanted_flow == FLOW_BOTH)
+                        ET1310_PhyAccessMiBit(etdev,
+                                              TRUEPHY_BIT_SET, 4, 10, NULL);
+                else
+                        ET1310_PhyAccessMiBit(etdev,
+                                              TRUEPHY_BIT_CLEAR, 4, 10, NULL);
+        } else {
+                ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL);
+                ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL);
+        }
+        ET1310_PhyPowerDown(etdev, 1);
+        switch (etdev->AiForceSpeed) {
+        case 10:
+                /* First we need to turn off all other advertisement */
+                ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
+                ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
+                if (etdev->AiForceDpx == 1) {
+                        /* Set our advertise values accordingly */
+                        ET1310_PhyAdvertise10BaseT(etdev,
+                                                TRUEPHY_ADV_DUPLEX_HALF);
+                } else if (etdev->AiForceDpx == 2) {
+                        /* Set our advertise values accordingly */
+                        ET1310_PhyAdvertise10BaseT(etdev,
+                                                TRUEPHY_ADV_DUPLEX_FULL);
+                } else {
+                        /* Disable autoneg */
+                        ET1310_PhyAutoNeg(etdev, false);
+                        /* Disable rest of the advertisements */
+                        ET1310_PhyAdvertise10BaseT(etdev,
+                                        TRUEPHY_ADV_DUPLEX_NONE);
+                        /* Force 10 Mbps */
+                        ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
+                        /* Force Full duplex */
+                        ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
+                }
+                break;
+        case 100:
+                /* first we need to turn off all other advertisement */
+                ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
+                ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
+                if (etdev->AiForceDpx == 1) {
+                        /* Set our advertise values accordingly */
+                        ET1310_PhyAdvertise100BaseT(etdev,
+                                                TRUEPHY_ADV_DUPLEX_HALF);
+                        /* Set speed */
+                        ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
+                } else if (etdev->AiForceDpx == 2) {
+                        /* Set our advertise values accordingly */
+                        ET1310_PhyAdvertise100BaseT(etdev,
+                                                TRUEPHY_ADV_DUPLEX_FULL);
+                } else {
+                        /* Disable autoneg */
+                        ET1310_PhyAutoNeg(etdev, false);
+                        /* Disable other advertisement */
+                        ET1310_PhyAdvertise100BaseT(etdev,
+                                                TRUEPHY_ADV_DUPLEX_NONE);
+                        /* Force 100 Mbps */
+                        ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
+                        /* Force Full duplex */
+                        ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
+                }
+                break;
+        case 1000:
+                /* first we need to turn off all other advertisement */
+                ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
+                ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
+                /* set our advertise values accordingly */
+                ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
+                break;
+        }
+        ET1310_PhyPowerDown(etdev, 0);
+}
+
+void et131x_Mii_check(struct et131x_adapter *etdev,
+                      u16 bmsr, u16 bmsr_ints)
+{
+        u8 link_status;
+        u32 autoneg_status;
+        u32 speed;
+        u32 duplex;
+        u32 mdi_mdix;
+        u32 masterslave;
+        u32 polarity;
+        unsigned long flags;
+
+        if (bmsr_ints & MI_BMSR_LINK_STATUS) {
+                if (bmsr & MI_BMSR_LINK_STATUS) {
+                        etdev->boot_coma = 20;
+
+                        /* Update our state variables and indicate the
+                         * connected state
+                         */
+                        spin_lock_irqsave(&etdev->Lock, flags);
+
+                        etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
+
+                        spin_unlock_irqrestore(&etdev->Lock, flags);
+
+                        netif_carrier_on(etdev->netdev);
+                } else {
+                        dev_warn(&etdev->pdev->dev,
+                            "Link down - cable problem ?\n");
+
+                        if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
+                                /* NOTE - Is there a way to query this without
+                                 * TruePHY?
+                                 * && TRU_QueryCoreType(etdev->hTruePhy, 0) ==
+                                 * EMI_TRUEPHY_A13O) {
+                                 */
+                                u16 Register18;
+
+                                MiRead(etdev, 0x12, &Register18);
+                                MiWrite(etdev, 0x12, Register18 | 0x4);
+                                MiWrite(etdev, 0x10, Register18 | 0x8402);
+                                MiWrite(etdev, 0x11, Register18 | 511);
+                                MiWrite(etdev, 0x12, Register18);
+                        }
+
+                        /* For the first N seconds of life, we are in "link
+                         * detection" When we are in this state, we should
+                         * only report "connected". When the LinkDetection
+                         * Timer expires, we can report disconnected (handled
+                         * in the LinkDetectionDPC).
+                         */
+                        if ((etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
+                                spin_lock_irqsave(&etdev->Lock, flags);
+                                etdev->MediaState =
+                                    NETIF_STATUS_MEDIA_DISCONNECT;
+                                spin_unlock_irqrestore(&etdev->Lock,
+                                                       flags);
+
+                                netif_carrier_off(etdev->netdev);
+                        }
+
+                        etdev->linkspeed = 0;
+                        etdev->duplex_mode = 0;
+
+                        /* Free the packets being actively sent & stopped */
+                        et131x_free_busy_send_packets(etdev);
+
+                        /* Re-initialize the send structures */
+                        et131x_init_send(etdev);
+
+                        /* Reset the RFD list and re-start RU */
+                        et131x_reset_recv(etdev);
+
+                        /*
+                         * Bring the device back to the state it was during
+                         * init prior to autonegotiation being complete. This
+                         * way, when we get the auto-neg complete interrupt,
+                         * we can complete init by calling ConfigMacREGS2.
+                         */
+                        et131x_soft_reset(etdev);
+
+                        /* Setup ET1310 as per the documentation */
+                        et131x_adapter_setup(etdev);
+
+                        /* Setup the PHY into coma mode until the cable is
+                         * plugged back in
+                         */
+                        if (etdev->RegistryPhyComa == 1)
+                                EnablePhyComa(etdev);
+                }
+        }
+
+        if ((bmsr_ints & MI_BMSR_AUTO_NEG_COMPLETE) ||
+            (etdev->AiForceDpx == 3 && (bmsr_ints & MI_BMSR_LINK_STATUS))) {
+                if ((bmsr & MI_BMSR_AUTO_NEG_COMPLETE) ||
+                    etdev->AiForceDpx == 3) {
+                        ET1310_PhyLinkStatus(etdev,
+                                             &link_status, &autoneg_status,
+                                             &speed, &duplex, &mdi_mdix,
+                                             &masterslave, &polarity);
+
+                        etdev->linkspeed = speed;
+                        etdev->duplex_mode = duplex;
+
+                        etdev->boot_coma = 20;
+
+                        if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
+                                /*
+                                 * NOTE - Is there a way to query this without
+                                 * TruePHY?
+                                 * && TRU_QueryCoreType(etdev->hTruePhy, 0)==
+                                 * EMI_TRUEPHY_A13O) {
+                                 */
+                                u16 Register18;
+
+                                MiRead(etdev, 0x12, &Register18);
+                                MiWrite(etdev, 0x12, Register18 | 0x4);
+                                MiWrite(etdev, 0x10, Register18 | 0x8402);
+                                MiWrite(etdev, 0x11, Register18 | 511);
+                                MiWrite(etdev, 0x12, Register18);
+                        }
+
+                        ConfigFlowControl(etdev);
+
+                        if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
+                                        etdev->RegistryJumboPacket > 2048)
+                                ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
+                                                                   0x2000);
+
+                        SetRxDmaTimer(etdev);
+                        ConfigMACRegs2(etdev);
+                }
+        }
+}
+
+/*
+ * The routines which follow provide low-level access to the PHY, and are used
+ * primarily by the routines above (although there are a few places elsewhere
+ * in the driver where this level of access is required).
+ */
+
+static const u16 ConfigPhy[25][2] = {
+        /* Reg      Value      Register */
+        /* Addr                         */
+        {0x880B, 0x0926},       /* AfeIfCreg4B1000Msbs */
+        {0x880C, 0x0926},       /* AfeIfCreg4B100Msbs */
+        {0x880D, 0x0926},       /* AfeIfCreg4B10Msbs */
+
+        {0x880E, 0xB4D3},       /* AfeIfCreg4B1000Lsbs */
+        {0x880F, 0xB4D3},       /* AfeIfCreg4B100Lsbs */
+        {0x8810, 0xB4D3},       /* AfeIfCreg4B10Lsbs */
+
+        {0x8805, 0xB03E},       /* AfeIfCreg3B1000Msbs */
+        {0x8806, 0xB03E},       /* AfeIfCreg3B100Msbs */
+        {0x8807, 0xFF00},       /* AfeIfCreg3B10Msbs */
+
+        {0x8808, 0xE090},       /* AfeIfCreg3B1000Lsbs */
+        {0x8809, 0xE110},       /* AfeIfCreg3B100Lsbs */
+        {0x880A, 0x0000},       /* AfeIfCreg3B10Lsbs */
+
+        {0x300D, 1},            /* DisableNorm */
+
+        {0x280C, 0x0180},       /* LinkHoldEnd */
+
+        {0x1C21, 0x0002},       /* AlphaM */
+
+        {0x3821, 6},            /* FfeLkgTx0 */
+        {0x381D, 1},            /* FfeLkg1g4 */
+        {0x381E, 1},            /* FfeLkg1g5 */
+        {0x381F, 1},            /* FfeLkg1g6 */
+        {0x3820, 1},            /* FfeLkg1g7 */
+
+        {0x8402, 0x01F0},       /* Btinact */
+        {0x800E, 20},           /* LftrainTime */
+        {0x800F, 24},           /* DvguardTime */
+        {0x8010, 46},           /* IdlguardTime */
+
+        {0, 0}
+
+};
+
+/* condensed version of the phy initialization routine */
+void ET1310_PhyInit(struct et131x_adapter *etdev)
+{
+        u16 data, index;
+
+        if (etdev == NULL)
+                return;
+
+        /* get the identity (again ?) */
+        MiRead(etdev, PHY_ID_1, &data);
+        MiRead(etdev, PHY_ID_2, &data);
+
+        /* what does this do/achieve ? */
+        MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
+        MiWrite(etdev, PHY_MPHY_CONTROL_REG,    0x0006);
+
+        /* read modem register 0402, should I do something with the return
+           data ? */
+        MiWrite(etdev, PHY_INDEX_REG, 0x0402);
+        MiRead(etdev, PHY_DATA_REG, &data);
+
+        /* what does this do/achieve ? */
+        MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
+
+        /* get the identity (again ?) */
+        MiRead(etdev, PHY_ID_1, &data);
+        MiRead(etdev, PHY_ID_2, &data);
+
+        /* what does this achieve ? */
+        MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
+        MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
+
+        /* read modem register 0402, should I do something with
+           the return data? */
+        MiWrite(etdev, PHY_INDEX_REG, 0x0402);
+        MiRead(etdev, PHY_DATA_REG, &data);
+
+        MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
+
+        /* what does this achieve (should return 0x1040) */
+        MiRead(etdev, PHY_CONTROL, &data);
+        MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
+        MiWrite(etdev, PHY_CONTROL, 0x1840);
+
+        MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
+
+        /* here the writing of the array starts.... */
+        index = 0;
+        while (ConfigPhy[index][0] != 0x0000) {
+                /* write value */
+                MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
+                MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
+
+                /* read it back */
+                MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
+                MiRead(etdev, PHY_DATA_REG, &data);
+
+                /* do a check on the value read back ? */
+                index++;
+        }
+        /* here the writing of the array ends... */
+
+        MiRead(etdev, PHY_CONTROL, &data);              /* 0x1840 */
+        MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
+        MiWrite(etdev, PHY_CONTROL, 0x1040);
+        MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
+}
+
diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
new file mode 100644
index 00000000000..6b38a3e0cab
--- /dev/null
+++ b/drivers/staging/et131x/et1310_phy.h
@@ -0,0 +1,458 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
+ *                PHY.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef _ET1310_PHY_H_
+#define _ET1310_PHY_H_
+
+#include "et1310_address_map.h"
+
+/* MI Register Addresses */
+#define MI_CONTROL_REG                      0
+#define MI_STATUS_REG                       1
+#define MI_PHY_IDENTIFIER_1_REG             2
+#define MI_PHY_IDENTIFIER_2_REG             3
+#define MI_AUTONEG_ADVERTISEMENT_REG        4
+#define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
+#define MI_AUTONEG_EXPANSION_REG            6
+#define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG   7
+#define MI_LINK_PARTNER_NEXT_PAGE_REG       8
+#define MI_1000BASET_CONTROL_REG            9
+#define MI_1000BASET_STATUS_REG             10
+#define MI_RESERVED11_REG                   11
+#define MI_RESERVED12_REG                   12
+#define MI_RESERVED13_REG                   13
+#define MI_RESERVED14_REG                   14
+#define MI_EXTENDED_STATUS_REG              15
+
+/* VMI Register Addresses */
+#define VMI_RESERVED16_REG                  16
+#define VMI_RESERVED17_REG                  17
+#define VMI_RESERVED18_REG                  18
+#define VMI_LOOPBACK_CONTROL_REG            19
+#define VMI_RESERVED20_REG                  20
+#define VMI_MI_CONTROL_REG                  21
+#define VMI_PHY_CONFIGURATION_REG           22
+#define VMI_PHY_CONTROL_REG                 23
+#define VMI_INTERRUPT_MASK_REG              24
+#define VMI_INTERRUPT_STATUS_REG            25
+#define VMI_PHY_STATUS_REG                  26
+#define VMI_LED_CONTROL_1_REG               27
+#define VMI_LED_CONTROL_2_REG               28
+#define VMI_RESERVED29_REG                  29
+#define VMI_RESERVED30_REG                  30
+#define VMI_RESERVED31_REG                  31
+
+/* PHY Register Mapping(MI) Management Interface Regs */
+struct mi_regs {
+        u8 bmcr;        /* Basic mode control reg(Reg 0x00) */
+        u8 bmsr;        /* Basic mode status reg(Reg 0x01) */
+        u8 idr1;        /* Phy identifier reg 1(Reg 0x02) */
+        u8 idr2;        /* Phy identifier reg 2(Reg 0x03) */
+        u8 anar;        /* Auto-Negotiation advertisement(Reg 0x04) */
+        u8 anlpar;      /* Auto-Negotiation link Partner Ability(Reg 0x05) */
+        u8 aner;        /* Auto-Negotiation expansion reg(Reg 0x06) */
+        u8 annptr;      /* Auto-Negotiation next page transmit reg(Reg 0x07) */
+        u8 lpnpr;       /* link partner next page reg(Reg 0x08) */
+        u8 gcr;         /* Gigabit basic mode control reg(Reg 0x09) */
+        u8 gsr;         /* Gigabit basic mode status reg(Reg 0x0A) */
+        u8 mi_res1[4];  /* Future use by MI working group(Reg 0x0B - 0x0E) */
+        u8 esr;         /* Extended status reg(Reg 0x0F) */
+        u8 mi_res2[3];  /* Future use by MI working group(Reg 0x10 - 0x12) */
+        u8 loop_ctl;    /* Loopback Control Reg(Reg 0x13) */
+        u8 mi_res3;     /* Future use by MI working group(Reg 0x14) */
+        u8 mcr;         /* MI Control Reg(Reg 0x15) */
+        u8 pcr;         /* Configuration Reg(Reg 0x16) */
+        u8 phy_ctl;     /* PHY Control Reg(Reg 0x17) */
+        u8 imr;         /* Interrupt Mask Reg(Reg 0x18) */
+        u8 isr;         /* Interrupt Status Reg(Reg 0x19) */
+        u8 psr;         /* PHY Status Reg(Reg 0x1A) */
+        u8 lcr1;                /* LED Control 1 Reg(Reg 0x1B) */
+        u8 lcr2;                /* LED Control 2 Reg(Reg 0x1C) */
+        u8 mi_res4[3];  /* Future use by MI working group(Reg 0x1D - 0x1F) */
+};
+
+/*
+ * MI Register 0: Basic mode control register
+ *      15:     reset
+ *      14:     loopback
+ *      13:     speed_sel
+ *      12:     enable_autoneg
+ *      11:     power_down
+ *      10:     isolate
+ *      9:      restart_autoneg
+ *      8:      duplex_mode
+ *      7:      col_test
+ *      6:      speed_1000_sel
+ *      5-0:    res1
+ */
+
+/*
+ * MI Register 1:  Basic mode status register
+ *      15:     link_100T4
+ *      14:     link_100fdx
+ *      13:     link_100hdx
+ *      12:     link_10fdx
+ *      11:     link_10hdx
+ *      10:     link_100T2fdx
+ *      9:      link_100T2hdx
+ *      8:      extend_status
+ *      7:      res1
+ *      6:      preamble_supress
+ *      5:      auto_neg_complete
+ *      4:      remote_fault
+ *      3:      auto_neg_able
+ *      2:      link_status
+ *      1:      jabber_detect
+ *      0:      ext_cap
+ */
+
+#define MI_BMSR_LINK_STATUS       0x04
+#define MI_BMSR_AUTO_NEG_COMPLETE 0x20
+
+/*
+ * MI Register 4: Auto-negotiation advertisement register
+ *
+ *      15:     np_indication
+ *      14:     res2
+ *      13:     remote_fault
+ *      12:     res1
+ *      11:     cap_asmpause
+ *      10:     cap_pause
+ *      9:      cap_100T4
+ *      8:      cap_100fdx
+ *      7:      cap_100hdx
+ *      6:      cap_10fdx
+ *      5:      cap_10hdx
+ *      4-0:    selector
+ */
+
+/* MI Register 5: Auto-negotiation link partner advertisement register
+ *      15:     np_indication
+ *      14:     acknowledge
+ *      13:     remote_fault
+ *      12:     res1
+ *      11:     cap_asmpause
+ *      10:     cap_pause
+ *      9:      cap_100T4
+ *      8:      cap_100fdx
+ *      7:      cap_100hdx
+ *      6:      cap_10fdx
+ *      5:      cap_10hdx
+ *      4-0:    selector
+ */
+
+/* MI Register 6: Auto-negotiation expansion register
+ *      15-5:   reserved
+ *      4:      pdf
+ *      3:      lp_np_able
+ *      2:      np_able
+ *      1:      page_rx
+ *      0:      lp_an_able
+ */
+
+/* MI Register 7: Auto-negotiation next page transmit reg(0x07)
+ *      15:     np
+ *      14:     reserved
+ *      13:     msg_page
+ *      12:     ack2
+ *      11:     toggle
+ *      10-0    msg
+ */
+
+/* MI Register 8: Link Partner Next Page Reg(0x08)
+ *      15:     np
+ *      14:     ack
+ *      13:     msg_page
+ *      12:     ack2
+ *      11:     toggle
+ *      10-0:   msg
+ */
+
+/* MI Register 9: 1000BaseT Control Reg(0x09)
+ *      15-13:  test_mode
+ *      12:     ms_config_en
+ *      11:     ms_value
+ *      10:     port_type
+ *      9:      link_1000fdx
+ *      8:      link_1000hdx
+ *      7-0:    reserved
+ */
+
+/* MI Register 10: 1000BaseT Status Reg(0x0A)
+ *      15:     ms_config_fault
+ *      14:     ms_resolve
+ *      13:     local_rx_status
+ *      12:     remote_rx_status
+ *      11:     link_1000fdx
+ *      10:     link_1000hdx
+ *      9-8:    reserved
+ *      7-0:    idle_err_cnt
+ */
+
+/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
+
+/* MI Register 15: Extended status Reg(0x0F)
+ *      15:     link_1000Xfdx
+ *      14:     link_1000Xhdx
+ *      13:     link_1000fdx
+ *      12:     link_1000hdx
+ *      11-0:   reserved
+ */
+
+/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
+
+/* MI Register 19: Loopback Control Reg(0x13)
+ *      15:     mii_en
+ *      14:     pcs_en
+ *      13:     pmd_en
+ *      12:     all_digital_en
+ *      11:     replica_en
+ *      10:     line_driver_en
+ *      9-0:    reserved
+ */
+
+/* MI Register 20: Reserved Reg(0x14) */
+
+/* MI Register 21: Management Interface Control Reg(0x15)
+ *      15-11:  reserved
+ *      10-4:   mi_error_count
+ *      3:      reserved
+ *      2:      ignore_10g_fr
+ *      1:      reserved
+ *      0:      preamble_supress_en
+ */
+
+/* MI Register 22: PHY Configuration Reg(0x16)
+ *      15:     crs_tx_en
+ *      14:     reserved
+ *      13-12:  tx_fifo_depth
+ *      11-10:  speed_downshift
+ *      9:      pbi_detect
+ *      8:      tbi_rate
+ *      7:      alternate_np
+ *      6:      group_mdio_en
+ *      5:      tx_clock_en
+ *      4:      sys_clock_en
+ *      3:      reserved
+ *      2-0:    mac_if_mode
+ */
+
+/* MI Register 23: PHY CONTROL Reg(0x17)
+ *      15:     reserved
+ *      14:     tdr_en
+ *      13:     reserved
+ *      12-11:  downshift_attempts
+ *      10-6:   reserved
+ *      5:      jabber_10baseT
+ *      4:      sqe_10baseT
+ *      3:      tp_loopback_10baseT
+ *      2:      preamble_gen_en
+ *      1:      reserved
+ *      0:      force_int
+ */
+
+/* MI Register 24: Interrupt Mask Reg(0x18)
+ *      15-10:  reserved
+ *      9:      mdio_sync_lost
+ *      8:      autoneg_status
+ *      7:      hi_bit_err
+ *      6:      np_rx
+ *      5:      err_counter_full
+ *      4:      fifo_over_underflow
+ *      3:      rx_status
+ *      2:      link_status
+ *      1:      automatic_speed
+ *      0:      int_en
+ */
+
+
+/* MI Register 25: Interrupt Status Reg(0x19)
+ *      15-10:  reserved
+ *      9:      mdio_sync_lost
+ *      8:      autoneg_status
+ *      7:      hi_bit_err
+ *      6:      np_rx
+ *      5:      err_counter_full
+ *      4:      fifo_over_underflow
+ *      3:      rx_status
+ *      2:      link_status
+ *      1:      automatic_speed
+ *      0:      int_en
+ */
+
+/* MI Register 26: PHY Status Reg(0x1A)
+ *      15:     reserved
+ *      14-13:  autoneg_fault
+ *      12:     autoneg_status
+ *      11:     mdi_x_status
+ *      10:     polarity_status
+ *      9-8:    speed_status
+ *      7:      duplex_status
+ *      6:      link_status
+ *      5:      tx_status
+ *      4:      rx_status
+ *      3:      collision_status
+ *      2:      autoneg_en
+ *      1:      pause_en
+ *      0:      asymmetric_dir
+ */
+
+/* MI Register 27: LED Control Reg 1(0x1B)
+ *      15-14:  reserved
+ *      13-12:  led_dup_indicate
+ *      11-10:  led_10baseT
+ *      9-8:    led_collision
+ *      7-4:    reserved
+ *      3-2:    pulse_dur
+ *      1:      pulse_stretch1
+ *      0:      pulse_stretch0
+ */
+
+/* MI Register 28: LED Control Reg 2(0x1C)
+ *      15-12:  led_link
+ *      11-8:   led_tx_rx
+ *      7-4:    led_100BaseTX
+ *      3-0:    led_1000BaseT
+ */
+
+/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
+
+
+/* Prototypes for ET1310_phy.c */
+/* Defines for PHY access routines */
+
+/* Define bit operation flags */
+#define TRUEPHY_BIT_CLEAR               0
+#define TRUEPHY_BIT_SET                 1
+#define TRUEPHY_BIT_READ                2
+
+/* Define read/write operation flags */
+#ifndef TRUEPHY_READ
+#define TRUEPHY_READ                    0
+#define TRUEPHY_WRITE                   1
+#define TRUEPHY_MASK                    2
+#endif
+
+/* Define speeds */
+#define TRUEPHY_SPEED_10MBPS            0
+#define TRUEPHY_SPEED_100MBPS           1
+#define TRUEPHY_SPEED_1000MBPS          2
+
+/* Define duplex modes */
+#define TRUEPHY_DUPLEX_HALF             0
+#define TRUEPHY_DUPLEX_FULL             1
+
+/* Define master/slave configuration values */
+#define TRUEPHY_CFG_SLAVE               0
+#define TRUEPHY_CFG_MASTER              1
+
+/* Define MDI/MDI-X settings */
+#define TRUEPHY_MDI                     0
+#define TRUEPHY_MDIX                    1
+#define TRUEPHY_AUTO_MDI_MDIX           2
+
+/* Define 10Base-T link polarities */
+#define TRUEPHY_POLARITY_NORMAL         0
+#define TRUEPHY_POLARITY_INVERTED       1
+
+/* Define auto-negotiation results */
+#define TRUEPHY_ANEG_NOT_COMPLETE       0
+#define TRUEPHY_ANEG_COMPLETE           1
+#define TRUEPHY_ANEG_DISABLED           2
+
+/* Define duplex advertisement flags */
+#define TRUEPHY_ADV_DUPLEX_NONE         0x00
+#define TRUEPHY_ADV_DUPLEX_FULL         0x01
+#define TRUEPHY_ADV_DUPLEX_HALF         0x02
+#define TRUEPHY_ADV_DUPLEX_BOTH     \
+        (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
+
+#define PHY_CONTROL                0x00 /* #define TRU_MI_CONTROL_REGISTER                 0 */
+#define PHY_STATUS                 0x01 /* #define TRU_MI_STATUS_REGISTER                  1 */
+#define PHY_ID_1                   0x02 /* #define TRU_MI_PHY_IDENTIFIER_1_REGISTER        2 */
+#define PHY_ID_2                   0x03 /* #define TRU_MI_PHY_IDENTIFIER_2_REGISTER        3 */
+#define PHY_AUTO_ADVERTISEMENT     0x04 /* #define TRU_MI_ADVERTISEMENT_REGISTER           4 */
+#define PHY_AUTO_LINK_PARTNER      0x05 /* #define TRU_MI_LINK_PARTNER_ABILITY_REGISTER    5 */
+#define PHY_AUTO_EXPANSION         0x06 /* #define TRU_MI_EXPANSION_REGISTER               6 */
+#define PHY_AUTO_NEXT_PAGE_TX      0x07 /* #define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER      7 */
+#define PHY_LINK_PARTNER_NEXT_PAGE 0x08 /* #define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER  8 */
+#define PHY_1000_CONTROL           0x09 /* #define TRU_MI_1000BASET_CONTROL_REGISTER       9 */
+#define PHY_1000_STATUS            0x0A /* #define TRU_MI_1000BASET_STATUS_REGISTER        10 */
+
+#define PHY_EXTENDED_STATUS        0x0F /* #define TRU_MI_EXTENDED_STATUS_REGISTER         15 */
+
+/* some defines for modem registers that seem to be 'reserved' */
+#define PHY_INDEX_REG              0x10
+#define PHY_DATA_REG               0x11
+
+#define PHY_MPHY_CONTROL_REG       0x12 /* #define TRU_VMI_MPHY_CONTROL_REGISTER           18 */
+
+#define PHY_LOOPBACK_CONTROL       0x13 /* #define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER     19 */
+                                        /* #define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER     20 */
+#define PHY_REGISTER_MGMT_CONTROL  0x15 /* #define TRU_VMI_MI_SEQ_CONTROL_REGISTER         21 */
+#define PHY_CONFIG                 0x16 /* #define TRU_VMI_CONFIGURATION_REGISTER          22 */
+#define PHY_PHY_CONTROL            0x17 /* #define TRU_VMI_PHY_CONTROL_REGISTER            23 */
+#define PHY_INTERRUPT_MASK         0x18 /* #define TRU_VMI_INTERRUPT_MASK_REGISTER         24 */
+#define PHY_INTERRUPT_STATUS       0x19 /* #define TRU_VMI_INTERRUPT_STATUS_REGISTER       25 */
+#define PHY_PHY_STATUS             0x1A /* #define TRU_VMI_PHY_STATUS_REGISTER             26 */
+#define PHY_LED_1                  0x1B /* #define TRU_VMI_LED_CONTROL_1_REGISTER          27 */
+#define PHY_LED_2                  0x1C /* #define TRU_VMI_LED_CONTROL_2_REGISTER          28 */
+                                        /* #define TRU_VMI_LINK_CONTROL_REGISTER           29 */
+                                        /* #define TRU_VMI_TIMING_CONTROL_REGISTER */
+
+#endif /* _ET1310_PHY_H_ */
diff --git a/drivers/staging/et131x/et1310_pm.c b/drivers/staging/et131x/et1310_pm.c
new file mode 100644
index 00000000000..29d4d66d345
--- /dev/null
+++ b/drivers/staging/et131x/et1310_pm.c
@@ -0,0 +1,180 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_pm.c - All power management related code (not completely implemented)
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et1310_rx.h"
+#include "et131x_adapter.h"
+#include "et131x.h"
+
+/**
+ * EnablePhyComa - called when network cable is unplugged
+ * @etdev: pointer to our adapter structure
+ *
+ * driver receive an phy status change interrupt while in D0 and check that
+ * phy_status is down.
+ *
+ *          -- gate off JAGCore;
+ *          -- set gigE PHY in Coma mode
+ *          -- wake on phy_interrupt; Perform software reset JAGCore,
+ *             re-initialize jagcore and gigE PHY
+ *
+ *      Add D0-ASPM-PhyLinkDown Support:
+ *          -- while in D0, when there is a phy_interrupt indicating phy link
+ *             down status, call the MPSetPhyComa routine to enter this active
+ *             state power saving mode
+ *          -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
+ *       indicating linkup status, call the MPDisablePhyComa routine to
+ *             restore JAGCore and gigE PHY
+ */
+void EnablePhyComa(struct et131x_adapter *etdev)
+{
+        unsigned long flags;
+        u32 pmcsr;
+
+        pmcsr = readl(&etdev->regs->global.pm_csr);
+
+        /* Save the GbE PHY speed and duplex modes. Need to restore this
+         * when cable is plugged back in
+         */
+        etdev->pdown_speed = etdev->AiForceSpeed;
+        etdev->pdown_duplex = etdev->AiForceDpx;
+
+        /* Stop sending packets. */
+        spin_lock_irqsave(&etdev->send_hw_lock, flags);
+        etdev->flags |= fMP_ADAPTER_LOWER_POWER;
+        spin_unlock_irqrestore(&etdev->send_hw_lock, flags);
+
+        /* Wait for outstanding Receive packets */
+
+        /* Gate off JAGCore 3 clock domains */
+        pmcsr &= ~ET_PMCSR_INIT;
+        writel(pmcsr, &etdev->regs->global.pm_csr);
+
+        /* Program gigE PHY in to Coma mode */
+        pmcsr |= ET_PM_PHY_SW_COMA;
+        writel(pmcsr, &etdev->regs->global.pm_csr);
+}
+
+/**
+ * DisablePhyComa - Disable the Phy Coma Mode
+ * @etdev: pointer to our adapter structure
+ */
+void DisablePhyComa(struct et131x_adapter *etdev)
+{
+        u32 pmcsr;
+
+        pmcsr = readl(&etdev->regs->global.pm_csr);
+
+        /* Disable phy_sw_coma register and re-enable JAGCore clocks */
+        pmcsr |= ET_PMCSR_INIT;
+        pmcsr &= ~ET_PM_PHY_SW_COMA;
+        writel(pmcsr, &etdev->regs->global.pm_csr);
+
+        /* Restore the GbE PHY speed and duplex modes;
+         * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
+         */
+        etdev->AiForceSpeed = etdev->pdown_speed;
+        etdev->AiForceDpx = etdev->pdown_duplex;
+
+        /* Re-initialize the send structures */
+        et131x_init_send(etdev);
+
+        /* Reset the RFD list and re-start RU  */
+        et131x_reset_recv(etdev);
+
+        /* Bring the device back to the state it was during init prior to
+         * autonegotiation being complete.  This way, when we get the auto-neg
+         * complete interrupt, we can complete init by calling ConfigMacREGS2.
+         */
+        et131x_soft_reset(etdev);
+
+        /* setup et1310 as per the documentation ?? */
+        et131x_adapter_setup(etdev);
+
+        /* Allow Tx to restart */
+        etdev->flags &= ~fMP_ADAPTER_LOWER_POWER;
+
+        /* Need to re-enable Rx. */
+        et131x_rx_dma_enable(etdev);
+}
+
diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c
new file mode 100644
index 00000000000..7e386e07ff9
--- /dev/null
+++ b/drivers/staging/et131x/et1310_rx.c
@@ -0,0 +1,1152 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_rx.c - Routines used to perform data reception
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et131x_adapter.h"
+#include "et1310_rx.h"
+#include "et131x.h"
+
+static inline u32 bump_fbr(u32 *fbr, u32 limit)
+{
+        u32 v = *fbr;
+        v++;
+        /* This works for all cases where limit < 1024. The 1023 case
+           works because 1023++ is 1024 which means the if condition is not
+           taken but the carry of the bit into the wrap bit toggles the wrap
+           value correctly */
+        if ((v & ET_DMA10_MASK) > limit) {
+                v &= ~ET_DMA10_MASK;
+                v ^= ET_DMA10_WRAP;
+        }
+        /* For the 1023 case */
+        v &= (ET_DMA10_MASK|ET_DMA10_WRAP);
+        *fbr = v;
+        return v;
+}
+
+/**
+ * et131x_rx_dma_memory_alloc
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success and errno on failure (as defined in errno.h)
+ *
+ * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
+ * and the Packet Status Ring.
+ */
+int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
+{
+        u32 i, j;
+        u32 bufsize;
+        u32 pktStatRingSize, FBRChunkSize;
+        struct rx_ring *rx_ring;
+
+        /* Setup some convenience pointers */
+        rx_ring = &adapter->rx_ring;
+
+        /* Alloc memory for the lookup table */
+#ifdef USE_FBR0
+        rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
+#endif
+        rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
+
+        /* The first thing we will do is configure the sizes of the buffer
+         * rings. These will change based on jumbo packet support.  Larger
+         * jumbo packets increases the size of each entry in FBR0, and the
+         * number of entries in FBR0, while at the same time decreasing the
+         * number of entries in FBR1.
+         *
+         * FBR1 holds "large" frames, FBR0 holds "small" frames.  If FBR1
+         * entries are huge in order to accommodate a "jumbo" frame, then it
+         * will have less entries.  Conversely, FBR1 will now be relied upon
+         * to carry more "normal" frames, thus it's entry size also increases
+         * and the number of entries goes up too (since it now carries
+         * "small" + "regular" packets.
+         *
+         * In this scheme, we try to maintain 512 entries between the two
+         * rings. Also, FBR1 remains a constant size - when it's size doubles
+         * the number of entries halves.  FBR0 increases in size, however.
+         */
+
+        if (adapter->RegistryJumboPacket < 2048) {
+#ifdef USE_FBR0
+                rx_ring->Fbr0BufferSize = 256;
+                rx_ring->Fbr0NumEntries = 512;
+#endif
+                rx_ring->Fbr1BufferSize = 2048;
+                rx_ring->Fbr1NumEntries = 512;
+        } else if (adapter->RegistryJumboPacket < 4096) {
+#ifdef USE_FBR0
+                rx_ring->Fbr0BufferSize = 512;
+                rx_ring->Fbr0NumEntries = 1024;
+#endif
+                rx_ring->Fbr1BufferSize = 4096;
+                rx_ring->Fbr1NumEntries = 512;
+        } else {
+#ifdef USE_FBR0
+                rx_ring->Fbr0BufferSize = 1024;
+                rx_ring->Fbr0NumEntries = 768;
+#endif
+                rx_ring->Fbr1BufferSize = 16384;
+                rx_ring->Fbr1NumEntries = 128;
+        }
+
+#ifdef USE_FBR0
+        adapter->rx_ring.PsrNumEntries = adapter->rx_ring.Fbr0NumEntries +
+            adapter->rx_ring.Fbr1NumEntries;
+#else
+        adapter->rx_ring.PsrNumEntries = adapter->rx_ring.Fbr1NumEntries;
+#endif
+
+        /* Allocate an area of memory for Free Buffer Ring 1 */
+        bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries) + 0xfff;
+        rx_ring->pFbr1RingVa = pci_alloc_consistent(adapter->pdev,
+                                                    bufsize,
+                                                    &rx_ring->pFbr1RingPa);
+        if (!rx_ring->pFbr1RingVa) {
+                dev_err(&adapter->pdev->dev,
+                          "Cannot alloc memory for Free Buffer Ring 1\n");
+                return -ENOMEM;
+        }
+
+        /* Save physical address
+         *
+         * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+         * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+         * are ever returned, make sure the high part is retrieved here
+         * before storing the adjusted address.
+         */
+        rx_ring->Fbr1Realpa = rx_ring->pFbr1RingPa;
+
+        /* Align Free Buffer Ring 1 on a 4K boundary */
+        et131x_align_allocated_memory(adapter,
+                                      &rx_ring->Fbr1Realpa,
+                                      &rx_ring->Fbr1offset, 0x0FFF);
+
+        rx_ring->pFbr1RingVa = (void *)((u8 *) rx_ring->pFbr1RingVa +
+                                        rx_ring->Fbr1offset);
+
+#ifdef USE_FBR0
+        /* Allocate an area of memory for Free Buffer Ring 0 */
+        bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries) + 0xfff;
+        rx_ring->pFbr0RingVa = pci_alloc_consistent(adapter->pdev,
+                                                    bufsize,
+                                                    &rx_ring->pFbr0RingPa);
+        if (!rx_ring->pFbr0RingVa) {
+                dev_err(&adapter->pdev->dev,
+                          "Cannot alloc memory for Free Buffer Ring 0\n");
+                return -ENOMEM;
+        }
+
+        /* Save physical address
+         *
+         * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+         * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+         * are ever returned, make sure the high part is retrieved here before
+         * storing the adjusted address.
+         */
+        rx_ring->Fbr0Realpa = rx_ring->pFbr0RingPa;
+
+        /* Align Free Buffer Ring 0 on a 4K boundary */
+        et131x_align_allocated_memory(adapter,
+                                      &rx_ring->Fbr0Realpa,
+                                      &rx_ring->Fbr0offset, 0x0FFF);
+
+        rx_ring->pFbr0RingVa = (void *)((u8 *) rx_ring->pFbr0RingVa +
+                                        rx_ring->Fbr0offset);
+#endif
+
+        for (i = 0; i < (rx_ring->Fbr1NumEntries / FBR_CHUNKS);
+             i++) {
+                u64 Fbr1Offset;
+                u64 Fbr1TempPa;
+                u32 Fbr1Align;
+
+                /* This code allocates an area of memory big enough for N
+                 * free buffers + (buffer_size - 1) so that the buffers can
+                 * be aligned on 4k boundaries.  If each buffer were aligned
+                 * to a buffer_size boundary, the effect would be to double
+                 * the size of FBR0.  By allocating N buffers at once, we
+                 * reduce this overhead.
+                 */
+                if (rx_ring->Fbr1BufferSize > 4096)
+                        Fbr1Align = 4096;
+                else
+                        Fbr1Align = rx_ring->Fbr1BufferSize;
+
+                FBRChunkSize =
+                    (FBR_CHUNKS * rx_ring->Fbr1BufferSize) + Fbr1Align - 1;
+                rx_ring->Fbr1MemVa[i] =
+                    pci_alloc_consistent(adapter->pdev, FBRChunkSize,
+                                         &rx_ring->Fbr1MemPa[i]);
+
+                if (!rx_ring->Fbr1MemVa[i]) {
+                        dev_err(&adapter->pdev->dev,
+                                "Could not alloc memory\n");
+                        return -ENOMEM;
+                }
+
+                /* See NOTE in "Save Physical Address" comment above */
+                Fbr1TempPa = rx_ring->Fbr1MemPa[i];
+
+                et131x_align_allocated_memory(adapter,
+                                              &Fbr1TempPa,
+                                              &Fbr1Offset, (Fbr1Align - 1));
+
+                for (j = 0; j < FBR_CHUNKS; j++) {
+                        u32 index = (i * FBR_CHUNKS) + j;
+
+                        /* Save the Virtual address of this index for quick
+                         * access later
+                         */
+                        rx_ring->fbr[1]->virt[index] =
+                            (u8 *) rx_ring->Fbr1MemVa[i] +
+                            (j * rx_ring->Fbr1BufferSize) + Fbr1Offset;
+
+                        /* now store the physical address in the descriptor
+                         * so the device can access it
+                         */
+                        rx_ring->fbr[1]->bus_high[index] =
+                            (u32) (Fbr1TempPa >> 32);
+                        rx_ring->fbr[1]->bus_low[index] = (u32) Fbr1TempPa;
+
+                        Fbr1TempPa += rx_ring->Fbr1BufferSize;
+
+                        rx_ring->fbr[1]->buffer1[index] =
+                            rx_ring->fbr[1]->virt[index];
+                        rx_ring->fbr[1]->buffer2[index] =
+                            rx_ring->fbr[1]->virt[index] - 4;
+                }
+        }
+
+#ifdef USE_FBR0
+        /* Same for FBR0 (if in use) */
+        for (i = 0; i < (rx_ring->Fbr0NumEntries / FBR_CHUNKS);
+             i++) {
+                u64 Fbr0Offset;
+                u64 Fbr0TempPa;
+
+                FBRChunkSize = ((FBR_CHUNKS + 1) * rx_ring->Fbr0BufferSize) - 1;
+                rx_ring->Fbr0MemVa[i] =
+                    pci_alloc_consistent(adapter->pdev, FBRChunkSize,
+                                         &rx_ring->Fbr0MemPa[i]);
+
+                if (!rx_ring->Fbr0MemVa[i]) {
+                        dev_err(&adapter->pdev->dev,
+                                "Could not alloc memory\n");
+                        return -ENOMEM;
+                }
+
+                /* See NOTE in "Save Physical Address" comment above */
+                Fbr0TempPa = rx_ring->Fbr0MemPa[i];
+
+                et131x_align_allocated_memory(adapter,
+                                              &Fbr0TempPa,
+                                              &Fbr0Offset,
+                                              rx_ring->Fbr0BufferSize - 1);
+
+                for (j = 0; j < FBR_CHUNKS; j++) {
+                        u32 index = (i * FBR_CHUNKS) + j;
+
+                        rx_ring->fbr[0]->virt[index] =
+                            (u8 *) rx_ring->Fbr0MemVa[i] +
+                            (j * rx_ring->Fbr0BufferSize) + Fbr0Offset;
+
+                        rx_ring->fbr[0]->bus_high[index] =
+                            (u32) (Fbr0TempPa >> 32);
+                        rx_ring->fbr[0]->bus_low[index] = (u32) Fbr0TempPa;
+
+                        Fbr0TempPa += rx_ring->Fbr0BufferSize;
+
+                        rx_ring->fbr[0]->buffer1[index] =
+                            rx_ring->fbr[0]->virt[index];
+                        rx_ring->fbr[0]->buffer2[index] =
+                            rx_ring->fbr[0]->virt[index] - 4;
+                }
+        }
+#endif
+
+        /* Allocate an area of memory for FIFO of Packet Status ring entries */
+        pktStatRingSize =
+            sizeof(struct pkt_stat_desc) * adapter->rx_ring.PsrNumEntries;
+
+        rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev,
+                                                  pktStatRingSize,
+                                                  &rx_ring->pPSRingPa);
+
+        if (!rx_ring->pPSRingVa) {
+                dev_err(&adapter->pdev->dev,
+                          "Cannot alloc memory for Packet Status Ring\n");
+                return -ENOMEM;
+        }
+        printk(KERN_INFO "PSR %lx\n", (unsigned long) rx_ring->pPSRingPa);
+
+        /*
+         * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
+         * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+         * are ever returned, make sure the high part is retrieved here before
+         * storing the adjusted address.
+         */
+
+        /* Allocate an area of memory for writeback of status information */
+        rx_ring->rx_status_block = pci_alloc_consistent(adapter->pdev,
+                                            sizeof(struct rx_status_block),
+                                            &rx_ring->rx_status_bus);
+        if (!rx_ring->rx_status_block) {
+                dev_err(&adapter->pdev->dev,
+                          "Cannot alloc memory for Status Block\n");
+                return -ENOMEM;
+        }
+        rx_ring->NumRfd = NIC_DEFAULT_NUM_RFD;
+        printk(KERN_INFO "PRS %lx\n", (unsigned long)rx_ring->rx_status_bus);
+
+        /* Recv
+         * pci_pool_create initializes a lookaside list. After successful
+         * creation, nonpaged fixed-size blocks can be allocated from and
+         * freed to the lookaside list.
+         * RFDs will be allocated from this pool.
+         */
+        rx_ring->RecvLookaside = kmem_cache_create(adapter->netdev->name,
+                                                   sizeof(struct rfd),
+                                                   0,
+                                                   SLAB_CACHE_DMA |
+                                                   SLAB_HWCACHE_ALIGN,
+                                                   NULL);
+
+        adapter->flags |= fMP_ADAPTER_RECV_LOOKASIDE;
+
+        /* The RFDs are going to be put on lists later on, so initialize the
+         * lists now.
+         */
+        INIT_LIST_HEAD(&rx_ring->RecvList);
+        return 0;
+}
+
+/**
+ * et131x_rx_dma_memory_free - Free all memory allocated within this module.
+ * @adapter: pointer to our private adapter structure
+ */
+void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
+{
+        u32 index;
+        u32 bufsize;
+        u32 pktStatRingSize;
+        struct rfd *rfd;
+        struct rx_ring *rx_ring;
+
+        /* Setup some convenience pointers */
+        rx_ring = &adapter->rx_ring;
+
+        /* Free RFDs and associated packet descriptors */
+        WARN_ON(rx_ring->nReadyRecv != rx_ring->NumRfd);
+
+        while (!list_empty(&rx_ring->RecvList)) {
+                rfd = (struct rfd *) list_entry(rx_ring->RecvList.next,
+                                struct rfd, list_node);
+
+                list_del(&rfd->list_node);
+                rfd->skb = NULL;
+                kmem_cache_free(adapter->rx_ring.RecvLookaside, rfd);
+        }
+
+        /* Free Free Buffer Ring 1 */
+        if (rx_ring->pFbr1RingVa) {
+                /* First the packet memory */
+                for (index = 0; index <
+                     (rx_ring->Fbr1NumEntries / FBR_CHUNKS); index++) {
+                        if (rx_ring->Fbr1MemVa[index]) {
+                                u32 Fbr1Align;
+
+                                if (rx_ring->Fbr1BufferSize > 4096)
+                                        Fbr1Align = 4096;
+                                else
+                                        Fbr1Align = rx_ring->Fbr1BufferSize;
+
+                                bufsize =
+                                    (rx_ring->Fbr1BufferSize * FBR_CHUNKS) +
+                                    Fbr1Align - 1;
+
+                                pci_free_consistent(adapter->pdev,
+                                                    bufsize,
+                                                    rx_ring->Fbr1MemVa[index],
+                                                    rx_ring->Fbr1MemPa[index]);
+
+                                rx_ring->Fbr1MemVa[index] = NULL;
+                        }
+                }
+
+                /* Now the FIFO itself */
+                rx_ring->pFbr1RingVa = (void *)((u8 *)
+                                rx_ring->pFbr1RingVa - rx_ring->Fbr1offset);
+
+                bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries)
+                                                            + 0xfff;
+
+                pci_free_consistent(adapter->pdev, bufsize,
+                                rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa);
+
+                rx_ring->pFbr1RingVa = NULL;
+        }
+
+#ifdef USE_FBR0
+        /* Now the same for Free Buffer Ring 0 */
+        if (rx_ring->pFbr0RingVa) {
+                /* First the packet memory */
+                for (index = 0; index <
+                     (rx_ring->Fbr0NumEntries / FBR_CHUNKS); index++) {
+                        if (rx_ring->Fbr0MemVa[index]) {
+                                bufsize =
+                                    (rx_ring->Fbr0BufferSize *
+                                     (FBR_CHUNKS + 1)) - 1;
+
+                                pci_free_consistent(adapter->pdev,
+                                                    bufsize,
+                                                    rx_ring->Fbr0MemVa[index],
+                                                    rx_ring->Fbr0MemPa[index]);
+
+                                rx_ring->Fbr0MemVa[index] = NULL;
+                        }
+                }
+
+                /* Now the FIFO itself */
+                rx_ring->pFbr0RingVa = (void *)((u8 *)
+                                rx_ring->pFbr0RingVa - rx_ring->Fbr0offset);
+
+                bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries)
+                                                            + 0xfff;
+
+                pci_free_consistent(adapter->pdev,
+                                    bufsize,
+                                    rx_ring->pFbr0RingVa, rx_ring->pFbr0RingPa);
+
+                rx_ring->pFbr0RingVa = NULL;
+        }
+#endif
+
+        /* Free Packet Status Ring */
+        if (rx_ring->pPSRingVa) {
+                pktStatRingSize =
+                  sizeof(struct pkt_stat_desc) * adapter->rx_ring.PsrNumEntries;
+
+                pci_free_consistent(adapter->pdev, pktStatRingSize,
+                                    rx_ring->pPSRingVa, rx_ring->pPSRingPa);
+
+                rx_ring->pPSRingVa = NULL;
+        }
+
+        /* Free area of memory for the writeback of status information */
+        if (rx_ring->rx_status_block) {
+                pci_free_consistent(adapter->pdev,
+                        sizeof(struct rx_status_block),
+                        rx_ring->rx_status_block, rx_ring->rx_status_bus);
+                rx_ring->rx_status_block = NULL;
+        }
+
+        /* Free receive buffer pool */
+
+        /* Free receive packet pool */
+
+        /* Destroy the lookaside (RFD) pool */
+        if (adapter->flags & fMP_ADAPTER_RECV_LOOKASIDE) {
+                kmem_cache_destroy(rx_ring->RecvLookaside);
+                adapter->flags &= ~fMP_ADAPTER_RECV_LOOKASIDE;
+        }
+
+        /* Free the FBR Lookup Table */
+#ifdef USE_FBR0
+        kfree(rx_ring->fbr[0]);
+#endif
+
+        kfree(rx_ring->fbr[1]);
+
+        /* Reset Counters */
+        rx_ring->nReadyRecv = 0;
+}
+
+/**
+ * et131x_init_recv - Initialize receive data structures.
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success and errno on failure (as defined in errno.h)
+ */
+int et131x_init_recv(struct et131x_adapter *adapter)
+{
+        int status = -ENOMEM;
+        struct rfd *rfd = NULL;
+        u32 rfdct;
+        u32 numrfd = 0;
+        struct rx_ring *rx_ring;
+
+        /* Setup some convenience pointers */
+        rx_ring = &adapter->rx_ring;
+
+        /* Setup each RFD */
+        for (rfdct = 0; rfdct < rx_ring->NumRfd; rfdct++) {
+                rfd = kmem_cache_alloc(rx_ring->RecvLookaside,
+                                                     GFP_ATOMIC | GFP_DMA);
+
+                if (!rfd) {
+                        dev_err(&adapter->pdev->dev,
+                                  "Couldn't alloc RFD out of kmem_cache\n");
+                        status = -ENOMEM;
+                        continue;
+                }
+
+                rfd->skb = NULL;
+
+                /* Add this RFD to the RecvList */
+                list_add_tail(&rfd->list_node, &rx_ring->RecvList);
+
+                /* Increment both the available RFD's, and the total RFD's. */
+                rx_ring->nReadyRecv++;
+                numrfd++;
+        }
+
+        if (numrfd > NIC_MIN_NUM_RFD)
+                status = 0;
+
+        rx_ring->NumRfd = numrfd;
+
+        if (status != 0) {
+                kmem_cache_free(rx_ring->RecvLookaside, rfd);
+                dev_err(&adapter->pdev->dev,
+                          "Allocation problems in et131x_init_recv\n");
+        }
+        return status;
+}
+
+/**
+ * ConfigRxDmaRegs - Start of Rx_DMA init sequence
+ * @etdev: pointer to our adapter structure
+ */
+void ConfigRxDmaRegs(struct et131x_adapter *etdev)
+{
+        struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma;
+        struct rx_ring *rx_local = &etdev->rx_ring;
+        struct fbr_desc *fbr_entry;
+        u32 entry;
+        u32 psr_num_des;
+        unsigned long flags;
+
+        /* Halt RXDMA to perform the reconfigure.  */
+        et131x_rx_dma_disable(etdev);
+
+        /* Load the completion writeback physical address
+         *
+         * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
+         * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+         * are ever returned, make sure the high part is retrieved here
+         * before storing the adjusted address.
+         */
+        writel((u32) ((u64)rx_local->rx_status_bus >> 32),
+               &rx_dma->dma_wb_base_hi);
+        writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo);
+
+        memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
+
+        /* Set the address and parameters of the packet status ring into the
+         * 1310's registers
+         */
+        writel((u32) ((u64)rx_local->pPSRingPa >> 32),
+               &rx_dma->psr_base_hi);
+        writel((u32) rx_local->pPSRingPa, &rx_dma->psr_base_lo);
+        writel(rx_local->PsrNumEntries - 1, &rx_dma->psr_num_des);
+        writel(0, &rx_dma->psr_full_offset);
+
+        psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
+        writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
+               &rx_dma->psr_min_des);
+
+        spin_lock_irqsave(&etdev->rcv_lock, flags);
+
+        /* These local variables track the PSR in the adapter structure */
+        rx_local->local_psr_full = 0;
+
+        /* Now's the best time to initialize FBR1 contents */
+        fbr_entry = (struct fbr_desc *) rx_local->pFbr1RingVa;
+        for (entry = 0; entry < rx_local->Fbr1NumEntries; entry++) {
+                fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
+                fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
+                fbr_entry->word2 = entry;
+                fbr_entry++;
+        }
+
+        /* Set the address and parameters of Free buffer ring 1 (and 0 if
+         * required) into the 1310's registers
+         */
+        writel((u32) (rx_local->Fbr1Realpa >> 32), &rx_dma->fbr1_base_hi);
+        writel((u32) rx_local->Fbr1Realpa, &rx_dma->fbr1_base_lo);
+        writel(rx_local->Fbr1NumEntries - 1, &rx_dma->fbr1_num_des);
+        writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
+
+        /* This variable tracks the free buffer ring 1 full position, so it
+         * has to match the above.
+         */
+        rx_local->local_Fbr1_full = ET_DMA10_WRAP;
+        writel(((rx_local->Fbr1NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+               &rx_dma->fbr1_min_des);
+
+#ifdef USE_FBR0
+        /* Now's the best time to initialize FBR0 contents */
+        fbr_entry = (struct fbr_desc *) rx_local->pFbr0RingVa;
+        for (entry = 0; entry < rx_local->Fbr0NumEntries; entry++) {
+                fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
+                fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
+                fbr_entry->word2 = entry;
+                fbr_entry++;
+        }
+
+        writel((u32) (rx_local->Fbr0Realpa >> 32), &rx_dma->fbr0_base_hi);
+        writel((u32) rx_local->Fbr0Realpa, &rx_dma->fbr0_base_lo);
+        writel(rx_local->Fbr0NumEntries - 1, &rx_dma->fbr0_num_des);
+        writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
+
+        /* This variable tracks the free buffer ring 0 full position, so it
+         * has to match the above.
+         */
+        rx_local->local_Fbr0_full = ET_DMA10_WRAP;
+        writel(((rx_local->Fbr0NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+               &rx_dma->fbr0_min_des);
+#endif
+
+        /* Program the number of packets we will receive before generating an
+         * interrupt.
+         * For version B silicon, this value gets updated once autoneg is
+         *complete.
+         */
+        writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
+
+        /* The "time_done" is not working correctly to coalesce interrupts
+         * after a given time period, but rather is giving us an interrupt
+         * regardless of whether we have received packets.
+         * This value gets updated once autoneg is complete.
+         */
+        writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
+
+        spin_unlock_irqrestore(&etdev->rcv_lock, flags);
+}
+
+/**
+ * SetRxDmaTimer - Set the heartbeat timer according to line rate.
+ * @etdev: pointer to our adapter structure
+ */
+void SetRxDmaTimer(struct et131x_adapter *etdev)
+{
+        /* For version B silicon, we do not use the RxDMA timer for 10 and 100
+         * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
+         */
+        if ((etdev->linkspeed == TRUEPHY_SPEED_100MBPS) ||
+            (etdev->linkspeed == TRUEPHY_SPEED_10MBPS)) {
+                writel(0, &etdev->regs->rxdma.max_pkt_time);
+                writel(1, &etdev->regs->rxdma.num_pkt_done);
+        }
+}
+
+/**
+ * NICReturnRFD - Recycle a RFD and put it back onto the receive list
+ * @etdev: pointer to our adapter
+ * @rfd: pointer to the RFD
+ */
+void nic_return_rfd(struct et131x_adapter *etdev, struct rfd *rfd)
+{
+        struct rx_ring *rx_local = &etdev->rx_ring;
+        struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma;
+        u16 bi = rfd->bufferindex;
+        u8 ri = rfd->ringindex;
+        unsigned long flags;
+
+        /* We don't use any of the OOB data besides status. Otherwise, we
+         * need to clean up OOB data
+         */
+        if (
+#ifdef USE_FBR0
+            (ri == 0 && bi < rx_local->Fbr0NumEntries) ||
+#endif
+            (ri == 1 && bi < rx_local->Fbr1NumEntries)) {
+                spin_lock_irqsave(&etdev->FbrLock, flags);
+
+                if (ri == 1) {
+                        struct fbr_desc *next =
+                            (struct fbr_desc *) (rx_local->pFbr1RingVa) +
+                                         INDEX10(rx_local->local_Fbr1_full);
+
+                        /* Handle the Free Buffer Ring advancement here. Write
+                         * the PA / Buffer Index for the returned buffer into
+                         * the oldest (next to be freed)FBR entry
+                         */
+                        next->addr_hi = rx_local->fbr[1]->bus_high[bi];
+                        next->addr_lo = rx_local->fbr[1]->bus_low[bi];
+                        next->word2 = bi;
+
+                        writel(bump_fbr(&rx_local->local_Fbr1_full,
+                                rx_local->Fbr1NumEntries - 1),
+                                &rx_dma->fbr1_full_offset);
+                }
+#ifdef USE_FBR0
+                else {
+                        struct fbr_desc *next = (struct fbr_desc *)
+                                rx_local->pFbr0RingVa +
+                                        INDEX10(rx_local->local_Fbr0_full);
+
+                        /* Handle the Free Buffer Ring advancement here. Write
+                         * the PA / Buffer Index for the returned buffer into
+                         * the oldest (next to be freed) FBR entry
+                         */
+                        next->addr_hi = rx_local->fbr[0]->bus_high[bi];
+                        next->addr_lo = rx_local->fbr[0]->bus_low[bi];
+                        next->word2 = bi;
+
+                        writel(bump_fbr(&rx_local->local_Fbr0_full,
+                                        rx_local->Fbr0NumEntries - 1),
+                               &rx_dma->fbr0_full_offset);
+                }
+#endif
+                spin_unlock_irqrestore(&etdev->FbrLock, flags);
+        } else {
+                dev_err(&etdev->pdev->dev,
+                          "NICReturnRFD illegal Buffer Index returned\n");
+        }
+
+        /* The processing on this RFD is done, so put it back on the tail of
+         * our list
+         */
+        spin_lock_irqsave(&etdev->rcv_lock, flags);
+        list_add_tail(&rfd->list_node, &rx_local->RecvList);
+        rx_local->nReadyRecv++;
+        spin_unlock_irqrestore(&etdev->rcv_lock, flags);
+
+        WARN_ON(rx_local->nReadyRecv > rx_local->NumRfd);
+}
+
+/**
+ * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
+ * @etdev: pointer to our adapter structure
+ */
+void et131x_rx_dma_disable(struct et131x_adapter *etdev)
+{
+        u32 csr;
+        /* Setup the receive dma configuration register */
+        writel(0x00002001, &etdev->regs->rxdma.csr);
+        csr = readl(&etdev->regs->rxdma.csr);
+        if ((csr & 0x00020000) == 0) {  /* Check halt status (bit 17) */
+                udelay(5);
+                csr = readl(&etdev->regs->rxdma.csr);
+                if ((csr & 0x00020000) == 0)
+                        dev_err(&etdev->pdev->dev,
+                        "RX Dma failed to enter halt state. CSR 0x%08x\n",
+                                csr);
+        }
+}
+
+/**
+ * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
+ * @etdev: pointer to our adapter structure
+ */
+void et131x_rx_dma_enable(struct et131x_adapter *etdev)
+{
+        /* Setup the receive dma configuration register for normal operation */
+        u32 csr =  0x2000;      /* FBR1 enable */
+
+        if (etdev->rx_ring.Fbr1BufferSize == 4096)
+                csr |= 0x0800;
+        else if (etdev->rx_ring.Fbr1BufferSize == 8192)
+                csr |= 0x1000;
+        else if (etdev->rx_ring.Fbr1BufferSize == 16384)
+                csr |= 0x1800;
+#ifdef USE_FBR0
+        csr |= 0x0400;          /* FBR0 enable */
+        if (etdev->rx_ring.Fbr0BufferSize == 256)
+                csr |= 0x0100;
+        else if (etdev->rx_ring.Fbr0BufferSize == 512)
+                csr |= 0x0200;
+        else if (etdev->rx_ring.Fbr0BufferSize == 1024)
+                csr |= 0x0300;
+#endif
+        writel(csr, &etdev->regs->rxdma.csr);
+
+        csr = readl(&etdev->regs->rxdma.csr);
+        if ((csr & 0x00020000) != 0) {
+                udelay(5);
+                csr = readl(&etdev->regs->rxdma.csr);
+                if ((csr & 0x00020000) != 0) {
+                        dev_err(&etdev->pdev->dev,
+                            "RX Dma failed to exit halt state.  CSR 0x%08x\n",
+                                csr);
+                }
+        }
+}
+
+/**
+ * nic_rx_pkts - Checks the hardware for available packets
+ * @etdev: pointer to our adapter
+ *
+ * Returns rfd, a pointer to our MPRFD.
+ *
+ * Checks the hardware for available packets, using completion ring
+ * If packets are available, it gets an RFD from the RecvList, attaches
+ * the packet to it, puts the RFD in the RecvPendList, and also returns
+ * the pointer to the RFD.
+ */
+struct rfd *nic_rx_pkts(struct et131x_adapter *etdev)
+{
+        struct rx_ring *rx_local = &etdev->rx_ring;
+        struct rx_status_block *status;
+        struct pkt_stat_desc *psr;
+        struct rfd *rfd;
+        u32 i;
+        u8 *buf;
+        unsigned long flags;
+        struct list_head *element;
+        u8 rindex;
+        u16 bindex;
+        u32 len;
+        u32 word0;
+        u32 word1;
+
+        /* RX Status block is written by the DMA engine prior to every
+         * interrupt. It contains the next to be used entry in the Packet
+         * Status Ring, and also the two Free Buffer rings.
+         */
+        status = rx_local->rx_status_block;
+        word1 = status->Word1 >> 16;    /* Get the useful bits */
+
+        /* Check the PSR and wrap bits do not match */
+        if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
+                /* Looks like this ring is not updated yet */
+                return NULL;
+
+        /* The packet status ring indicates that data is available. */
+        psr = (struct pkt_stat_desc *) (rx_local->pPSRingVa) +
+                        (rx_local->local_psr_full & 0xFFF);
+
+        /* Grab any information that is required once the PSR is
+         * advanced, since we can no longer rely on the memory being
+         * accurate
+         */
+        len = psr->word1 & 0xFFFF;
+        rindex = (psr->word1 >> 26) & 0x03;
+        bindex = (psr->word1 >> 16) & 0x3FF;
+        word0 = psr->word0;
+
+        /* Indicate that we have used this PSR entry. */
+        /* FIXME wrap 12 */
+        add_12bit(&rx_local->local_psr_full, 1);
+        if ((rx_local->local_psr_full & 0xFFF)  > rx_local->PsrNumEntries - 1) {
+                /* Clear psr full and toggle the wrap bit */
+                rx_local->local_psr_full &=  ~0xFFF;
+                rx_local->local_psr_full ^= 0x1000;
+        }
+
+        writel(rx_local->local_psr_full,
+               &etdev->regs->rxdma.psr_full_offset);
+
+#ifndef USE_FBR0
+        if (rindex != 1)
+                return NULL;
+#endif
+
+#ifdef USE_FBR0
+        if (rindex > 1 ||
+                (rindex == 0 &&
+                bindex > rx_local->Fbr0NumEntries - 1) ||
+                (rindex == 1 &&
+                bindex > rx_local->Fbr1NumEntries - 1))
+#else
+        if (rindex != 1 || bindex > rx_local->Fbr1NumEntries - 1)
+#endif
+        {
+                /* Illegal buffer or ring index cannot be used by S/W*/
+                dev_err(&etdev->pdev->dev,
+                          "NICRxPkts PSR Entry %d indicates "
+                          "length of %d and/or bad bi(%d)\n",
+                          rx_local->local_psr_full & 0xFFF,
+                          len, bindex);
+                return NULL;
+        }
+
+        /* Get and fill the RFD. */
+        spin_lock_irqsave(&etdev->rcv_lock, flags);
+
+        rfd = NULL;
+        element = rx_local->RecvList.next;
+        rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
+
+        if (rfd == NULL) {
+                spin_unlock_irqrestore(&etdev->rcv_lock, flags);
+                return NULL;
+        }
+
+        list_del(&rfd->list_node);
+        rx_local->nReadyRecv--;
+
+        spin_unlock_irqrestore(&etdev->rcv_lock, flags);
+
+        rfd->bufferindex = bindex;
+        rfd->ringindex = rindex;
+
+        /* In V1 silicon, there is a bug which screws up filtering of
+         * runt packets.  Therefore runt packet filtering is disabled
+         * in the MAC and the packets are dropped here.  They are
+         * also counted here.
+         */
+        if (len < (NIC_MIN_PACKET_SIZE + 4)) {
+                etdev->stats.other_errors++;
+                len = 0;
+        }
+
+        if (len) {
+                if (etdev->ReplicaPhyLoopbk == 1) {
+                        buf = rx_local->fbr[rindex]->virt[bindex];
+
+                        if (memcmp(&buf[6], etdev->addr, ETH_ALEN) == 0) {
+                                if (memcmp(&buf[42], "Replica packet",
+                                           ETH_HLEN)) {
+                                        etdev->ReplicaPhyLoopbkPF = 1;
+                                }
+                        }
+                }
+
+                /* Determine if this is a multicast packet coming in */
+                if ((word0 & ALCATEL_MULTICAST_PKT) &&
+                    !(word0 & ALCATEL_BROADCAST_PKT)) {
+                        /* Promiscuous mode and Multicast mode are
+                         * not mutually exclusive as was first
+                         * thought.  I guess Promiscuous is just
+                         * considered a super-set of the other
+                         * filters. Generally filter is 0x2b when in
+                         * promiscuous mode.
+                         */
+                        if ((etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST)
+                            && !(etdev->PacketFilter & ET131X_PACKET_TYPE_PROMISCUOUS)
+                            && !(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
+                                buf = rx_local->fbr[rindex]->
+                                                virt[bindex];
+
+                                /* Loop through our list to see if the
+                                 * destination address of this packet
+                                 * matches one in our list.
+                                 */
+                                for (i = 0;
+                                     i < etdev->MCAddressCount;
+                                     i++) {
+                                        if (buf[0] ==
+                                            etdev->MCList[i][0]
+                                            && buf[1] ==
+                                            etdev->MCList[i][1]
+                                            && buf[2] ==
+                                            etdev->MCList[i][2]
+                                            && buf[3] ==
+                                            etdev->MCList[i][3]
+                                            && buf[4] ==
+                                            etdev->MCList[i][4]
+                                            && buf[5] ==
+                                            etdev->MCList[i][5]) {
+                                                break;
+                                        }
+                                }
+
+                                /* If our index is equal to the number
+                                 * of Multicast address we have, then
+                                 * this means we did not find this
+                                 * packet's matching address in our
+                                 * list.  Set the len to zero,
+                                 * so we free our RFD when we return
+                                 * from this function.
+                                 */
+                                if (i == etdev->MCAddressCount)
+                                        len = 0;
+                        }
+
+                        if (len > 0)
+                                etdev->stats.multircv++;
+                } else if (word0 & ALCATEL_BROADCAST_PKT)
+                        etdev->stats.brdcstrcv++;
+                else
+                        /* Not sure what this counter measures in
+                         * promiscuous mode. Perhaps we should check
+                         * the MAC address to see if it is directed
+                         * to us in promiscuous mode.
+                         */
+                        etdev->stats.unircv++;
+        }
+
+        if (len > 0) {
+                struct sk_buff *skb = NULL;
+
+                /*rfd->len = len - 4; */
+                rfd->len = len;
+
+                skb = dev_alloc_skb(rfd->len + 2);
+                if (!skb) {
+                        dev_err(&etdev->pdev->dev,
+                                  "Couldn't alloc an SKB for Rx\n");
+                        return NULL;
+                }
+
+                etdev->net_stats.rx_bytes += rfd->len;
+
+                memcpy(skb_put(skb, rfd->len),
+                       rx_local->fbr[rindex]->virt[bindex],
+                       rfd->len);
+
+                skb->dev = etdev->netdev;
+                skb->protocol = eth_type_trans(skb, etdev->netdev);
+                skb->ip_summed = CHECKSUM_NONE;
+
+                netif_rx(skb);
+        } else {
+                rfd->len = 0;
+        }
+
+        nic_return_rfd(etdev, rfd);
+        return rfd;
+}
+
+/**
+ * et131x_reset_recv - Reset the receive list
+ * @etdev: pointer to our adapter
+ *
+ * Assumption, Rcv spinlock has been acquired.
+ */
+void et131x_reset_recv(struct et131x_adapter *etdev)
+{
+        WARN_ON(list_empty(&etdev->rx_ring.RecvList));
+
+}
+
+/**
+ * et131x_handle_recv_interrupt - Interrupt handler for receive processing
+ * @etdev: pointer to our adapter
+ *
+ * Assumption, Rcv spinlock has been acquired.
+ */
+void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
+{
+        struct rfd *rfd = NULL;
+        u32 count = 0;
+        bool done = true;
+
+        /* Process up to available RFD's */
+        while (count < NUM_PACKETS_HANDLED) {
+                if (list_empty(&etdev->rx_ring.RecvList)) {
+                        WARN_ON(etdev->rx_ring.nReadyRecv != 0);
+                        done = false;
+                        break;
+                }
+
+                rfd = nic_rx_pkts(etdev);
+
+                if (rfd == NULL)
+                        break;
+
+                /* Do not receive any packets until a filter has been set.
+                 * Do not receive any packets until we have link.
+                 * If length is zero, return the RFD in order to advance the
+                 * Free buffer ring.
+                 */
+                if (!etdev->PacketFilter ||
+                    !netif_carrier_ok(etdev->netdev) ||
+                    rfd->len == 0)
+                        continue;
+
+                /* Increment the number of packets we received */
+                etdev->net_stats.rx_packets++;
+
+                /* Set the status on the packet, either resources or success */
+                if (etdev->rx_ring.nReadyRecv < RFD_LOW_WATER_MARK) {
+                        dev_warn(&etdev->pdev->dev,
+                                    "RFD's are running out\n");
+                }
+                count++;
+        }
+
+        if (count == NUM_PACKETS_HANDLED || !done) {
+                etdev->rx_ring.UnfinishedReceives = true;
+                writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
+                       &etdev->regs->global.watchdog_timer);
+        } else
+                /* Watchdog timer will disable itself if appropriate. */
+                etdev->rx_ring.UnfinishedReceives = false;
+}
+
diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h
new file mode 100644
index 00000000000..e8c653d37a7
--- /dev/null
+++ b/drivers/staging/et131x/et1310_rx.h
@@ -0,0 +1,243 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
+ *               reception.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef __ET1310_RX_H__
+#define __ET1310_RX_H__
+
+#include "et1310_address_map.h"
+
+#define USE_FBR0 true
+
+#ifdef USE_FBR0
+/* #define FBR0_BUFFER_SIZE 256 */
+#endif
+
+/* #define FBR1_BUFFER_SIZE 2048 */
+
+#define FBR_CHUNKS 32
+
+#define MAX_DESC_PER_RING_RX         1024
+
+/* number of RFDs - default and min */
+#ifdef USE_FBR0
+#define RFD_LOW_WATER_MARK      40
+#define NIC_MIN_NUM_RFD         64
+#define NIC_DEFAULT_NUM_RFD     1024
+#else
+#define RFD_LOW_WATER_MARK      20
+#define NIC_MIN_NUM_RFD         64
+#define NIC_DEFAULT_NUM_RFD     256
+#endif
+
+#define NUM_PACKETS_HANDLED     256
+
+#define ALCATEL_BAD_STATUS      0xe47f0000
+#define ALCATEL_MULTICAST_PKT   0x01000000
+#define ALCATEL_BROADCAST_PKT   0x02000000
+
+/* typedefs for Free Buffer Descriptors */
+struct fbr_desc {
+        u32 addr_lo;
+        u32 addr_hi;
+        u32 word2;              /* Bits 10-31 reserved, 0-9 descriptor */
+};
+
+/* Packet Status Ring Descriptors
+ *
+ * Word 0:
+ *
+ * top 16 bits are from the Alcatel Status Word as enumerated in
+ * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
+ *
+ * 0: hp                        hash pass
+ * 1: ipa                       IP checksum assist
+ * 2: ipp                       IP checksum pass
+ * 3: tcpa                      TCP checksum assist
+ * 4: tcpp                      TCP checksum pass
+ * 5: wol                       WOL Event
+ * 6: rxmac_error               RXMAC Error Indicator
+ * 7: drop                      Drop packet
+ * 8: ft                        Frame Truncated
+ * 9: jp                        Jumbo Packet
+ * 10: vp                       VLAN Packet
+ * 11-15: unused
+ * 16: asw_prev_pkt_dropped     e.g. IFG too small on previous
+ * 17: asw_RX_DV_event          short receive event detected
+ * 18: asw_false_carrier_event  bad carrier since last good packet
+ * 19: asw_code_err             one or more nibbles signalled as errors
+ * 20: asw_CRC_err              CRC error
+ * 21: asw_len_chk_err          frame length field incorrect
+ * 22: asw_too_long             frame length > 1518 bytes
+ * 23: asw_OK                   valid CRC + no code error
+ * 24: asw_multicast            has a multicast address
+ * 25: asw_broadcast            has a broadcast address
+ * 26: asw_dribble_nibble       spurious bits after EOP
+ * 27: asw_control_frame        is a control frame
+ * 28: asw_pause_frame          is a pause frame
+ * 29: asw_unsupported_op       unsupported OP code
+ * 30: asw_VLAN_tag             VLAN tag detected
+ * 31: asw_long_evt             Rx long event
+ *
+ * Word 1:
+ * 0-15: length                 length in bytes
+ * 16-25: bi                    Buffer Index
+ * 26-27: ri                    Ring Index
+ * 28-31: reserved
+ */
+
+struct pkt_stat_desc {
+        u32 word0;
+        u32 word1;
+};
+
+/* Typedefs for the RX DMA status word */
+
+/*
+ * rx status word 0 holds part of the status bits of the Rx DMA engine
+ * that get copied out to memory by the ET-1310.  Word 0 is a 32 bit word
+ * which contains the Free Buffer ring 0 and 1 available offset.
+ *
+ * bit 0-9 FBR1 offset
+ * bit 10 Wrap flag for FBR1
+ * bit 16-25 FBR0 offset
+ * bit 26 Wrap flag for FBR0
+ */
+
+/*
+ * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
+ * that get copied out to memory by the ET-1310.  Word 3 is a 32 bit word
+ * which contains the Packet Status Ring available offset.
+ *
+ * bit 0-15 reserved
+ * bit 16-27 PSRoffset
+ * bit 28 PSRwrap
+ * bit 29-31 unused
+ */
+
+/*
+ * struct rx_status_block is a structure representing the status of the Rx
+ * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
+ */
+struct rx_status_block {
+        u32 Word0;
+        u32 Word1;
+};
+
+/*
+ * Structure for look-up table holding free buffer ring pointers
+ */
+struct fbr_lookup {
+        void *virt[MAX_DESC_PER_RING_RX];
+        void *buffer1[MAX_DESC_PER_RING_RX];
+        void *buffer2[MAX_DESC_PER_RING_RX];
+        u32 bus_high[MAX_DESC_PER_RING_RX];
+        u32 bus_low[MAX_DESC_PER_RING_RX];
+};
+
+/*
+ * struct rx_ring is the ssructure representing the adaptor's local
+ * reference(s) to the rings
+ */
+struct rx_ring {
+#ifdef USE_FBR0
+        void *pFbr0RingVa;
+        dma_addr_t pFbr0RingPa;
+        void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+        dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+        uint64_t Fbr0Realpa;
+        uint64_t Fbr0offset;
+        u32 local_Fbr0_full;
+        u32 Fbr0NumEntries;
+        u32 Fbr0BufferSize;
+#endif
+        void *pFbr1RingVa;
+        dma_addr_t pFbr1RingPa;
+        void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+        dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+        uint64_t Fbr1Realpa;
+        uint64_t Fbr1offset;
+        struct fbr_lookup *fbr[2];      /* One per ring */
+        u32 local_Fbr1_full;
+        u32 Fbr1NumEntries;
+        u32 Fbr1BufferSize;
+
+        void *pPSRingVa;
+        dma_addr_t pPSRingPa;
+        u32 local_psr_full;
+        u32 PsrNumEntries;
+
+        struct rx_status_block *rx_status_block;
+        dma_addr_t rx_status_bus;
+
+        struct list_head RecvBufferPool;
+
+        /* RECV */
+        struct list_head RecvList;
+        u32 nReadyRecv;
+
+        u32 NumRfd;
+
+        bool UnfinishedReceives;
+
+        struct list_head RecvPacketPool;
+
+        /* lookaside lists */
+        struct kmem_cache *RecvLookaside;
+};
+
+#endif /* __ET1310_RX_H__ */
diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c
new file mode 100644
index 00000000000..8fb3051fe28
--- /dev/null
+++ b/drivers/staging/et131x/et1310_tx.c
@@ -0,0 +1,797 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_tx.c - Routines used to perform data transmission.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et131x_adapter.h"
+#include "et1310_tx.h"
+#include "et131x.h"
+
+static inline void et131x_free_send_packet(struct et131x_adapter *etdev,
+                                           struct tcb *tcb);
+static int et131x_send_packet(struct sk_buff *skb,
+                              struct et131x_adapter *etdev);
+static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb);
+
+/**
+ * et131x_tx_dma_memory_alloc
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success and errno on failure (as defined in errno.h).
+ *
+ * Allocates memory that will be visible both to the device and to the CPU.
+ * The OS will pass us packets, pointers to which we will insert in the Tx
+ * Descriptor queue. The device will read this queue to find the packets in
+ * memory. The device will update the "status" in memory each time it xmits a
+ * packet.
+ */
+int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
+{
+        int desc_size = 0;
+        struct tx_ring *tx_ring = &adapter->tx_ring;
+
+        /* Allocate memory for the TCB's (Transmit Control Block) */
+        adapter->tx_ring.tcb_ring =
+                kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
+        if (!adapter->tx_ring.tcb_ring) {
+                dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
+                return -ENOMEM;
+        }
+
+        /* Allocate enough memory for the Tx descriptor ring, and allocate
+         * some extra so that the ring can be aligned on a 4k boundary.
+         */
+        desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
+        tx_ring->tx_desc_ring =
+            (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
+                                                    &tx_ring->tx_desc_ring_pa);
+        if (!adapter->tx_ring.tx_desc_ring) {
+                dev_err(&adapter->pdev->dev,
+                                        "Cannot alloc memory for Tx Ring\n");
+                return -ENOMEM;
+        }
+
+        /* Save physical address
+         *
+         * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+         * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+         * are ever returned, make sure the high part is retrieved here before
+         * storing the adjusted address.
+         */
+        /* Allocate memory for the Tx status block */
+        tx_ring->tx_status = pci_alloc_consistent(adapter->pdev,
+                                                    sizeof(u32),
+                                                    &tx_ring->tx_status_pa);
+        if (!adapter->tx_ring.tx_status_pa) {
+                dev_err(&adapter->pdev->dev,
+                                  "Cannot alloc memory for Tx status block\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+/**
+ * et131x_tx_dma_memory_free - Free all memory allocated within this module
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success and errno on failure (as defined in errno.h).
+ */
+void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
+{
+        int desc_size = 0;
+
+        if (adapter->tx_ring.tx_desc_ring) {
+                /* Free memory relating to Tx rings here */
+                desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
+                                                                + 4096 - 1;
+                pci_free_consistent(adapter->pdev,
+                                    desc_size,
+                                    adapter->tx_ring.tx_desc_ring,
+                                    adapter->tx_ring.tx_desc_ring_pa);
+                adapter->tx_ring.tx_desc_ring = NULL;
+        }
+
+        /* Free memory for the Tx status block */
+        if (adapter->tx_ring.tx_status) {
+                pci_free_consistent(adapter->pdev,
+                                    sizeof(u32),
+                                    adapter->tx_ring.tx_status,
+                                    adapter->tx_ring.tx_status_pa);
+
+                adapter->tx_ring.tx_status = NULL;
+        }
+        /* Free the memory for the tcb structures */
+        kfree(adapter->tx_ring.tcb_ring);
+}
+
+/**
+ * ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
+ * @etdev: pointer to our private adapter structure
+ *
+ * Configure the transmit engine with the ring buffers we have created
+ * and prepare it for use.
+ */
+void ConfigTxDmaRegs(struct et131x_adapter *etdev)
+{
+        struct txdma_regs __iomem *txdma = &etdev->regs->txdma;
+
+        /* Load the hardware with the start of the transmit descriptor ring. */
+        writel((u32) ((u64)etdev->tx_ring.tx_desc_ring_pa >> 32),
+               &txdma->pr_base_hi);
+        writel((u32) etdev->tx_ring.tx_desc_ring_pa,
+               &txdma->pr_base_lo);
+
+        /* Initialise the transmit DMA engine */
+        writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
+
+        /* Load the completion writeback physical address */
+        writel((u32)((u64)etdev->tx_ring.tx_status_pa >> 32),
+                                                &txdma->dma_wb_base_hi);
+        writel((u32)etdev->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo);
+
+        *etdev->tx_ring.tx_status = 0;
+
+        writel(0, &txdma->service_request);
+        etdev->tx_ring.send_idx = 0;
+}
+
+/**
+ * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
+ * @etdev: pointer to our adapter structure
+ */
+void et131x_tx_dma_disable(struct et131x_adapter *etdev)
+{
+        /* Setup the tramsmit dma configuration register */
+        writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
+                                        &etdev->regs->txdma.csr);
+}
+
+/**
+ * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
+ * @etdev: pointer to our adapter structure
+ *
+ * Mainly used after a return to the D0 (full-power) state from a lower state.
+ */
+void et131x_tx_dma_enable(struct et131x_adapter *etdev)
+{
+        /* Setup the transmit dma configuration register for normal
+         * operation
+         */
+        writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
+                                        &etdev->regs->txdma.csr);
+}
+
+/**
+ * et131x_init_send - Initialize send data structures
+ * @adapter: pointer to our private adapter structure
+ */
+void et131x_init_send(struct et131x_adapter *adapter)
+{
+        struct tcb *tcb;
+        u32 ct;
+        struct tx_ring *tx_ring;
+
+        /* Setup some convenience pointers */
+        tx_ring = &adapter->tx_ring;
+        tcb = adapter->tx_ring.tcb_ring;
+
+        tx_ring->tcb_qhead = tcb;
+
+        memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
+
+        /* Go through and set up each TCB */
+        for (ct = 0; ct++ < NUM_TCB; tcb++)
+                /* Set the link pointer in HW TCB to the next TCB in the
+                 * chain
+                 */
+                tcb->next = tcb + 1;
+
+        /* Set the  tail pointer */
+        tcb--;
+        tx_ring->tcb_qtail = tcb;
+        tcb->next = NULL;
+        /* Curr send queue should now be empty */
+        tx_ring->send_head = NULL;
+        tx_ring->send_tail = NULL;
+}
+
+/**
+ * et131x_send_packets - This function is called by the OS to send packets
+ * @skb: the packet(s) to send
+ * @netdev:device on which to TX the above packet(s)
+ *
+ * Return 0 in almost all cases; non-zero value in extreme hard failure only
+ */
+int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
+{
+        int status = 0;
+        struct et131x_adapter *etdev = NULL;
+
+        etdev = netdev_priv(netdev);
+
+        /* Send these packets
+         *
+         * NOTE: The Linux Tx entry point is only given one packet at a time
+         * to Tx, so the PacketCount and it's array used makes no sense here
+         */
+
+        /* TCB is not available */
+        if (etdev->tx_ring.used >= NUM_TCB) {
+                /* NOTE: If there's an error on send, no need to queue the
+                 * packet under Linux; if we just send an error up to the
+                 * netif layer, it will resend the skb to us.
+                 */
+                status = -ENOMEM;
+        } else {
+                /* We need to see if the link is up; if it's not, make the
+                 * netif layer think we're good and drop the packet
+                 */
+                if ((etdev->flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
+                                        !netif_carrier_ok(netdev)) {
+                        dev_kfree_skb_any(skb);
+                        skb = NULL;
+
+                        etdev->net_stats.tx_dropped++;
+                } else {
+                        status = et131x_send_packet(skb, etdev);
+                        if (status != 0 && status != -ENOMEM) {
+                                /* On any other error, make netif think we're
+                                 * OK and drop the packet
+                                 */
+                                dev_kfree_skb_any(skb);
+                                skb = NULL;
+                                etdev->net_stats.tx_dropped++;
+                        }
+                }
+        }
+        return status;
+}
+
+/**
+ * et131x_send_packet - Do the work to send a packet
+ * @skb: the packet(s) to send
+ * @etdev: a pointer to the device's private adapter structure
+ *
+ * Return 0 in almost all cases; non-zero value in extreme hard failure only.
+ *
+ * Assumption: Send spinlock has been acquired
+ */
+static int et131x_send_packet(struct sk_buff *skb,
+                              struct et131x_adapter *etdev)
+{
+        int status;
+        struct tcb *tcb = NULL;
+        u16 *shbufva;
+        unsigned long flags;
+
+        /* All packets must have at least a MAC address and a protocol type */
+        if (skb->len < ETH_HLEN)
+                return -EIO;
+
+        /* Get a TCB for this packet */
+        spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
+
+        tcb = etdev->tx_ring.tcb_qhead;
+
+        if (tcb == NULL) {
+                spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
+                return -ENOMEM;
+        }
+
+        etdev->tx_ring.tcb_qhead = tcb->next;
+
+        if (etdev->tx_ring.tcb_qhead == NULL)
+                etdev->tx_ring.tcb_qtail = NULL;
+
+        spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
+
+        tcb->skb = skb;
+
+        if (skb->data != NULL && skb->len - skb->data_len >= 6) {
+                shbufva = (u16 *) skb->data;
+
+                if ((shbufva[0] == 0xffff) &&
+                    (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
+                        tcb->flags |= fMP_DEST_BROAD;
+                } else if ((shbufva[0] & 0x3) == 0x0001) {
+                        tcb->flags |=  fMP_DEST_MULTI;
+                }
+        }
+
+        tcb->next = NULL;
+
+        /* Call the NIC specific send handler. */
+        status = nic_send_packet(etdev, tcb);
+
+        if (status != 0) {
+                spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
+
+                if (etdev->tx_ring.tcb_qtail)
+                        etdev->tx_ring.tcb_qtail->next = tcb;
+                else
+                        /* Apparently ready Q is empty. */
+                        etdev->tx_ring.tcb_qhead = tcb;
+
+                etdev->tx_ring.tcb_qtail = tcb;
+                spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
+                return status;
+        }
+        WARN_ON(etdev->tx_ring.used > NUM_TCB);
+        return 0;
+}
+
+/**
+ * nic_send_packet - NIC specific send handler for version B silicon.
+ * @etdev: pointer to our adapter
+ * @tcb: pointer to struct tcb
+ *
+ * Returns 0 or errno.
+ */
+static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
+{
+        u32 i;
+        struct tx_desc desc[24];        /* 24 x 16 byte */
+        u32 frag = 0;
+        u32 thiscopy, remainder;
+        struct sk_buff *skb = tcb->skb;
+        u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
+        struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
+        unsigned long flags;
+
+        /* Part of the optimizations of this send routine restrict us to
+         * sending 24 fragments at a pass.  In practice we should never see
+         * more than 5 fragments.
+         *
+         * NOTE: The older version of this function (below) can handle any
+         * number of fragments. If needed, we can call this function,
+         * although it is less efficient.
+         */
+        if (nr_frags > 23)
+                return -EIO;
+
+        memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
+
+        for (i = 0; i < nr_frags; i++) {
+                /* If there is something in this element, lets get a
+                 * descriptor from the ring and get the necessary data
+                 */
+                if (i == 0) {
+                        /* If the fragments are smaller than a standard MTU,
+                         * then map them to a single descriptor in the Tx
+                         * Desc ring. However, if they're larger, as is
+                         * possible with support for jumbo packets, then
+                         * split them each across 2 descriptors.
+                         *
+                         * This will work until we determine why the hardware
+                         * doesn't seem to like large fragments.
+                         */
+                        if ((skb->len - skb->data_len) <= 1514) {
+                                desc[frag].addr_hi = 0;
+                                /* Low 16bits are length, high is vlan and
+                                   unused currently so zero */
+                                desc[frag].len_vlan =
+                                        skb->len - skb->data_len;
+
+                                /* NOTE: Here, the dma_addr_t returned from
+                                 * pci_map_single() is implicitly cast as a
+                                 * u32. Although dma_addr_t can be
+                                 * 64-bit, the address returned by
+                                 * pci_map_single() is always 32-bit
+                                 * addressable (as defined by the pci/dma
+                                 * subsystem)
+                                 */
+                                desc[frag++].addr_lo =
+                                    pci_map_single(etdev->pdev,
+                                                   skb->data,
+                                                   skb->len -
+                                                   skb->data_len,
+                                                   PCI_DMA_TODEVICE);
+                        } else {
+                                desc[frag].addr_hi = 0;
+                                desc[frag].len_vlan =
+                                    (skb->len - skb->data_len) / 2;
+
+                                /* NOTE: Here, the dma_addr_t returned from
+                                 * pci_map_single() is implicitly cast as a
+                                 * u32. Although dma_addr_t can be
+                                 * 64-bit, the address returned by
+                                 * pci_map_single() is always 32-bit
+                                 * addressable (as defined by the pci/dma
+                                 * subsystem)
+                                 */
+                                desc[frag++].addr_lo =
+                                    pci_map_single(etdev->pdev,
+                                                   skb->data,
+                                                   ((skb->len -
+                                                     skb->data_len) / 2),
+                                                   PCI_DMA_TODEVICE);
+                                desc[frag].addr_hi = 0;
+
+                                desc[frag].len_vlan =
+                                    (skb->len - skb->data_len) / 2;
+
+                                /* NOTE: Here, the dma_addr_t returned from
+                                 * pci_map_single() is implicitly cast as a
+                                 * u32. Although dma_addr_t can be
+                                 * 64-bit, the address returned by
+                                 * pci_map_single() is always 32-bit
+                                 * addressable (as defined by the pci/dma
+                                 * subsystem)
+                                 */
+                                desc[frag++].addr_lo =
+                                    pci_map_single(etdev->pdev,
+                                                   skb->data +
+                                                   ((skb->len -
+                                                     skb->data_len) / 2),
+                                                   ((skb->len -
+                                                     skb->data_len) / 2),
+                                                   PCI_DMA_TODEVICE);
+                        }
+                } else {
+                        desc[frag].addr_hi = 0;
+                        desc[frag].len_vlan =
+                                        frags[i - 1].size;
+
+                        /* NOTE: Here, the dma_addr_t returned from
+                         * pci_map_page() is implicitly cast as a u32.
+                         * Although dma_addr_t can be 64-bit, the address
+                         * returned by pci_map_page() is always 32-bit
+                         * addressable (as defined by the pci/dma subsystem)
+                         */
+                        desc[frag++].addr_lo =
+                            pci_map_page(etdev->pdev,
+                                         frags[i - 1].page,
+                                         frags[i - 1].page_offset,
+                                         frags[i - 1].size,
+                                         PCI_DMA_TODEVICE);
+                }
+        }
+
+        if (frag == 0)
+                return -EIO;
+
+        if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
+                if (++etdev->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
+                        /* Last element & Interrupt flag */
+                        desc[frag - 1].flags = 0x5;
+                        etdev->tx_ring.since_irq = 0;
+                } else { /* Last element */
+                        desc[frag - 1].flags = 0x1;
+                }
+        } else
+                desc[frag - 1].flags = 0x5;
+
+        desc[0].flags |= 2;     /* First element flag */
+
+        tcb->index_start = etdev->tx_ring.send_idx;
+        tcb->stale = 0;
+
+        spin_lock_irqsave(&etdev->send_hw_lock, flags);
+
+        thiscopy = NUM_DESC_PER_RING_TX -
+                                INDEX10(etdev->tx_ring.send_idx);
+
+        if (thiscopy >= frag) {
+                remainder = 0;
+                thiscopy = frag;
+        } else {
+                remainder = frag - thiscopy;
+        }
+
+        memcpy(etdev->tx_ring.tx_desc_ring +
+               INDEX10(etdev->tx_ring.send_idx), desc,
+               sizeof(struct tx_desc) * thiscopy);
+
+        add_10bit(&etdev->tx_ring.send_idx, thiscopy);
+
+        if (INDEX10(etdev->tx_ring.send_idx) == 0 ||
+                    INDEX10(etdev->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
+                etdev->tx_ring.send_idx &= ~ET_DMA10_MASK;
+                etdev->tx_ring.send_idx ^= ET_DMA10_WRAP;
+        }
+
+        if (remainder) {
+                memcpy(etdev->tx_ring.tx_desc_ring,
+                       desc + thiscopy,
+                       sizeof(struct tx_desc) * remainder);
+
+                add_10bit(&etdev->tx_ring.send_idx, remainder);
+        }
+
+        if (INDEX10(etdev->tx_ring.send_idx) == 0) {
+                if (etdev->tx_ring.send_idx)
+                        tcb->index = NUM_DESC_PER_RING_TX - 1;
+                else
+                        tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
+        } else
+                tcb->index = etdev->tx_ring.send_idx - 1;
+
+        spin_lock(&etdev->TCBSendQLock);
+
+        if (etdev->tx_ring.send_tail)
+                etdev->tx_ring.send_tail->next = tcb;
+        else
+                etdev->tx_ring.send_head = tcb;
+
+        etdev->tx_ring.send_tail = tcb;
+
+        WARN_ON(tcb->next != NULL);
+
+        etdev->tx_ring.used++;
+
+        spin_unlock(&etdev->TCBSendQLock);
+
+        /* Write the new write pointer back to the device. */
+        writel(etdev->tx_ring.send_idx,
+               &etdev->regs->txdma.service_request);
+
+        /* For Gig only, we use Tx Interrupt coalescing.  Enable the software
+         * timer to wake us up if this packet isn't followed by N more.
+         */
+        if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
+                writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
+                       &etdev->regs->global.watchdog_timer);
+        }
+        spin_unlock_irqrestore(&etdev->send_hw_lock, flags);
+
+        return 0;
+}
+
+
+/**
+ * et131x_free_send_packet - Recycle a struct tcb
+ * @etdev: pointer to our adapter
+ * @tcb: pointer to struct tcb
+ *
+ * Complete the packet if necessary
+ * Assumption - Send spinlock has been acquired
+ */
+inline void et131x_free_send_packet(struct et131x_adapter *etdev,
+                                                struct tcb *tcb)
+{
+        unsigned long flags;
+        struct tx_desc *desc = NULL;
+        struct net_device_stats *stats = &etdev->net_stats;
+
+        if (tcb->flags & fMP_DEST_BROAD)
+                atomic_inc(&etdev->stats.brdcstxmt);
+        else if (tcb->flags & fMP_DEST_MULTI)
+                atomic_inc(&etdev->stats.multixmt);
+        else
+                atomic_inc(&etdev->stats.unixmt);
+
+        if (tcb->skb) {
+                stats->tx_bytes += tcb->skb->len;
+
+                /* Iterate through the TX descriptors on the ring
+                 * corresponding to this packet and umap the fragments
+                 * they point to
+                 */
+                do {
+                        desc = (struct tx_desc *)(etdev->tx_ring.tx_desc_ring +
+                                                INDEX10(tcb->index_start));
+
+                        pci_unmap_single(etdev->pdev,
+                                         desc->addr_lo,
+                                         desc->len_vlan, PCI_DMA_TODEVICE);
+
+                        add_10bit(&tcb->index_start, 1);
+                        if (INDEX10(tcb->index_start) >=
+                                                        NUM_DESC_PER_RING_TX) {
+                                tcb->index_start &= ~ET_DMA10_MASK;
+                                tcb->index_start ^= ET_DMA10_WRAP;
+                        }
+                } while (desc != (etdev->tx_ring.tx_desc_ring +
+                                INDEX10(tcb->index)));
+
+                dev_kfree_skb_any(tcb->skb);
+        }
+
+        memset(tcb, 0, sizeof(struct tcb));
+
+        /* Add the TCB to the Ready Q */
+        spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
+
+        etdev->net_stats.tx_packets++;
+
+        if (etdev->tx_ring.tcb_qtail)
+                etdev->tx_ring.tcb_qtail->next = tcb;
+        else
+                /* Apparently ready Q is empty. */
+                etdev->tx_ring.tcb_qhead = tcb;
+
+        etdev->tx_ring.tcb_qtail = tcb;
+
+        spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
+        WARN_ON(etdev->tx_ring.used < 0);
+}
+
+/**
+ * et131x_free_busy_send_packets - Free and complete the stopped active sends
+ * @etdev: pointer to our adapter
+ *
+ * Assumption - Send spinlock has been acquired
+ */
+void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
+{
+        struct tcb *tcb;
+        unsigned long flags;
+        u32 freed = 0;
+
+        /* Any packets being sent? Check the first TCB on the send list */
+        spin_lock_irqsave(&etdev->TCBSendQLock, flags);
+
+        tcb = etdev->tx_ring.send_head;
+
+        while (tcb != NULL && freed < NUM_TCB) {
+                struct tcb *next = tcb->next;
+
+                etdev->tx_ring.send_head = next;
+
+                if (next == NULL)
+                        etdev->tx_ring.send_tail = NULL;
+
+                etdev->tx_ring.used--;
+
+                spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
+
+                freed++;
+                et131x_free_send_packet(etdev, tcb);
+
+                spin_lock_irqsave(&etdev->TCBSendQLock, flags);
+
+                tcb = etdev->tx_ring.send_head;
+        }
+
+        WARN_ON(freed == NUM_TCB);
+
+        spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
+
+        etdev->tx_ring.used = 0;
+}
+
+/**
+ * et131x_handle_send_interrupt - Interrupt handler for sending processing
+ * @etdev: pointer to our adapter
+ *
+ * Re-claim the send resources, complete sends and get more to send from
+ * the send wait queue.
+ *
+ * Assumption - Send spinlock has been acquired
+ */
+void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
+{
+        unsigned long flags;
+        u32 serviced;
+        struct tcb *tcb;
+        u32 index;
+
+        serviced = readl(&etdev->regs->txdma.new_service_complete);
+        index = INDEX10(serviced);
+
+        /* Has the ring wrapped?  Process any descriptors that do not have
+         * the same "wrap" indicator as the current completion indicator
+         */
+        spin_lock_irqsave(&etdev->TCBSendQLock, flags);
+
+        tcb = etdev->tx_ring.send_head;
+
+        while (tcb &&
+               ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
+               index < INDEX10(tcb->index)) {
+                etdev->tx_ring.used--;
+                etdev->tx_ring.send_head = tcb->next;
+                if (tcb->next == NULL)
+                        etdev->tx_ring.send_tail = NULL;
+
+                spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
+                et131x_free_send_packet(etdev, tcb);
+                spin_lock_irqsave(&etdev->TCBSendQLock, flags);
+
+                /* Goto the next packet */
+                tcb = etdev->tx_ring.send_head;
+        }
+        while (tcb &&
+               !((serviced ^ tcb->index) & ET_DMA10_WRAP)
+               && index > (tcb->index & ET_DMA10_MASK)) {
+                etdev->tx_ring.used--;
+                etdev->tx_ring.send_head = tcb->next;
+                if (tcb->next == NULL)
+                        etdev->tx_ring.send_tail = NULL;
+
+                spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
+                et131x_free_send_packet(etdev, tcb);
+                spin_lock_irqsave(&etdev->TCBSendQLock, flags);
+
+                /* Goto the next packet */
+                tcb = etdev->tx_ring.send_head;
+        }
+
+        /* Wake up the queue when we hit a low-water mark */
+        if (etdev->tx_ring.used <= NUM_TCB / 3)
+                netif_wake_queue(etdev->netdev);
+
+        spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
+}
+
diff --git a/drivers/staging/et131x/et1310_tx.h b/drivers/staging/et131x/et1310_tx.h
new file mode 100644
index 00000000000..82d06e9870d
--- /dev/null
+++ b/drivers/staging/et131x/et1310_tx.h
@@ -0,0 +1,150 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et1310_tx.h - Defines, structs, enums, prototypes, etc. pertaining to data
+ *               transmission.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef __ET1310_TX_H__
+#define __ET1310_TX_H__
+
+
+/* Typedefs for Tx Descriptor Ring */
+
+/*
+ * word 2 of the control bits in the Tx Descriptor ring for the ET-1310
+ *
+ * 0-15: length of packet
+ * 16-27: VLAN tag
+ * 28: VLAN CFI
+ * 29-31: VLAN priority
+ *
+ * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
+ *
+ * 0: last packet in the sequence
+ * 1: first packet in the sequence
+ * 2: interrupt the processor when this pkt sent
+ * 3: Control word - no packet data
+ * 4: Issue half-duplex backpressure : XON/XOFF
+ * 5: send pause frame
+ * 6: Tx frame has error
+ * 7: append CRC
+ * 8: MAC override
+ * 9: pad packet
+ * 10: Packet is a Huge packet
+ * 11: append VLAN tag
+ * 12: IP checksum assist
+ * 13: TCP checksum assist
+ * 14: UDP checksum assist
+ */
+
+/* struct tx_desc represents each descriptor on the ring */
+struct tx_desc {
+        u32 addr_hi;
+        u32 addr_lo;
+        u32 len_vlan;   /* control words how to xmit the */
+        u32 flags;      /* data (detailed above) */
+};
+
+/*
+ * The status of the Tx DMA engine it sits in free memory, and is pointed to
+ * by 0x101c / 0x1020. This is a DMA10 type
+ */
+
+/* TCB (Transmit Control Block: Host Side) */
+struct tcb {
+        struct tcb *next;       /* Next entry in ring */
+        u32 flags;              /* Our flags for the packet */
+        u32 count;              /* Used to spot stuck/lost packets */
+        u32 stale;              /* Used to spot stuck/lost packets */
+        struct sk_buff *skb;    /* Network skb we are tied to */
+        u32 index;              /* Ring indexes */
+        u32 index_start;
+};
+
+/* Structure representing our local reference(s) to the ring */
+struct tx_ring {
+        /* TCB (Transmit Control Block) memory and lists */
+        struct tcb *tcb_ring;
+
+        /* List of TCBs that are ready to be used */
+        struct tcb *tcb_qhead;
+        struct tcb *tcb_qtail;
+
+        /* list of TCBs that are currently being sent.  NOTE that access to all
+         * three of these (including used) are controlled via the
+         * TCBSendQLock.  This lock should be secured prior to incementing /
+         * decrementing used, or any queue manipulation on send_head /
+         * tail
+         */
+        struct tcb *send_head;
+        struct tcb *send_tail;
+        int used;
+
+        /* The actual descriptor ring */
+        struct tx_desc *tx_desc_ring;
+        dma_addr_t tx_desc_ring_pa;
+
+        /* send_idx indicates where we last wrote to in the descriptor ring. */
+        u32 send_idx;
+
+        /* The location of the write-back status block */
+        u32 *tx_status;
+        dma_addr_t tx_status_pa;
+
+        /* Packets since the last IRQ: used for interrupt coalescing */
+        int since_irq;
+};
+
+#endif /* __ET1310_TX_H__ */
diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h
new file mode 100644
index 00000000000..408c50ba4f2
--- /dev/null
+++ b/drivers/staging/et131x/et131x_adapter.h
@@ -0,0 +1,243 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et131x_adapter.h - Header which includes the private adapter structure, along
+ *                    with related support structures, macros, definitions, etc.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef __ET131X_ADAPTER_H__
+#define __ET131X_ADAPTER_H__
+
+#include "et1310_address_map.h"
+#include "et1310_tx.h"
+#include "et1310_rx.h"
+
+/*
+ * Do not change these values: if changed, then change also in respective
+ * TXdma and Rxdma engines
+ */
+#define NUM_DESC_PER_RING_TX         512    /* TX Do not change these values */
+#define NUM_TCB                      64
+
+/*
+ * These values are all superseded by registry entries to facilitate tuning.
+ * Once the desired performance has been achieved, the optimal registry values
+ * should be re-populated to these #defines:
+ */
+#define NUM_TRAFFIC_CLASSES          1
+
+#define TX_ERROR_PERIOD             1000
+
+#define LO_MARK_PERCENT_FOR_PSR     15
+#define LO_MARK_PERCENT_FOR_RX      15
+
+/* RFD (Receive Frame Descriptor) */
+struct rfd {
+        struct list_head list_node;
+        struct sk_buff *skb;
+        u32 len;        /* total size of receive frame */
+        u16 bufferindex;
+        u8 ringindex;
+};
+
+/* Flow Control */
+#define FLOW_BOTH       0
+#define FLOW_TXONLY     1
+#define FLOW_RXONLY     2
+#define FLOW_NONE       3
+
+/* Struct to define some device statistics */
+struct ce_stats {
+        /* MIB II variables
+         *
+         * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
+         * MUST have 32, then we'll need another way to perform atomic
+         * operations
+         */
+        u32 unircv;     /* # multicast packets received */
+        atomic_t unixmt;        /* # multicast packets for Tx */
+        u32 multircv;   /* # multicast packets received */
+        atomic_t multixmt;      /* # multicast packets for Tx */
+        u32 brdcstrcv;  /* # broadcast packets received */
+        atomic_t brdcstxmt;     /* # broadcast packets for Tx */
+        u32 norcvbuf;   /* # Rx packets discarded */
+        u32 noxmtbuf;   /* # Tx packets discarded */
+
+        /* Transceiver state informations. */
+        u8 xcvr_addr;
+        u32 xcvr_id;
+
+        /* Tx Statistics. */
+        u32 tx_uflo;            /* Tx Underruns */
+
+        u32 collisions;
+        u32 excessive_collisions;
+        u32 first_collision;
+        u32 late_collisions;
+        u32 max_pkt_error;
+        u32 tx_deferred;
+
+        /* Rx Statistics. */
+        u32 rx_ov_flow; /* Rx Overflow */
+
+        u32 length_err;
+        u32 alignment_err;
+        u32 crc_err;
+        u32 code_violations;
+        u32 other_errors;
+
+        u32 SynchrounousIterations;
+        u32 InterruptStatus;
+};
+
+
+/* The private adapter structure */
+struct et131x_adapter {
+        struct net_device *netdev;
+        struct pci_dev *pdev;
+
+        struct work_struct task;
+
+        /* Flags that indicate current state of the adapter */
+        u32 flags;
+        u32 HwErrCount;
+
+        /* Configuration  */
+        u8 rom_addr[ETH_ALEN];
+        u8 addr[ETH_ALEN];
+        bool has_eeprom;
+        u8 eeprom_data[2];
+
+        /* Spinlocks */
+        spinlock_t Lock;
+
+        spinlock_t TCBSendQLock;
+        spinlock_t TCBReadyQLock;
+        spinlock_t send_hw_lock;
+
+        spinlock_t rcv_lock;
+        spinlock_t RcvPendLock;
+        spinlock_t FbrLock;
+
+        spinlock_t PHYLock;
+
+        /* Packet Filter and look ahead size */
+        u32 PacketFilter;
+        u32 linkspeed;
+        u32 duplex_mode;
+
+        /* multicast list */
+        u32 MCAddressCount;
+        u8 MCList[NIC_MAX_MCAST_LIST][ETH_ALEN];
+
+        /* Pointer to the device's PCI register space */
+        struct address_map __iomem *regs;
+
+        /* Registry parameters */
+        u8 SpeedDuplex;         /* speed/duplex */
+        u8 wanted_flow;         /* Flow we want for 802.3x flow control */
+        u8 RegistryPhyComa;     /* Phy Coma mode enable/disable */
+
+        u32 RegistryRxMemEnd;   /* Size of internal rx memory */
+        u32 RegistryJumboPacket;        /* Max supported ethernet packet size */
+
+
+        /* Derived from the registry: */
+        u8 AiForceDpx;          /* duplex setting */
+        u16 AiForceSpeed;       /* 'Speed', user over-ride of line speed */
+        u8 flowcontrol;         /* flow control validated by the far-end */
+        enum {
+                NETIF_STATUS_INVALID = 0,
+                NETIF_STATUS_MEDIA_CONNECT,
+                NETIF_STATUS_MEDIA_DISCONNECT,
+                NETIF_STATUS_MAX
+        } MediaState;
+
+        /* Minimize init-time */
+        struct timer_list ErrorTimer;
+
+        /* variable putting the phy into coma mode when boot up with no cable
+         * plugged in after 5 seconds
+         */
+        u8 boot_coma;
+
+        /* Next two used to save power information at power down. This
+         * information will be used during power up to set up parts of Power
+         * Management in JAGCore
+         */
+        u16 pdown_speed;
+        u8 pdown_duplex;
+
+        u32 CachedMaskValue;
+
+        /* Xcvr status at last poll */
+        u16 bmsr;
+
+        /* Tx Memory Variables */
+        struct tx_ring tx_ring;
+
+        /* Rx Memory Variables */
+        struct rx_ring rx_ring;
+
+        /* Loopback specifics */
+        u8 ReplicaPhyLoopbk;    /* Replica Enable */
+        u8 ReplicaPhyLoopbkPF;  /* Replica Enable Pass/Fail */
+
+        /* Stats */
+        struct ce_stats stats;
+
+        struct net_device_stats net_stats;
+};
+
+#endif /* __ET131X_ADAPTER_H__ */
diff --git a/drivers/staging/et131x/et131x_defs.h b/drivers/staging/et131x/et131x_defs.h
new file mode 100644
index 00000000000..3d5193fdb00
--- /dev/null
+++ b/drivers/staging/et131x/et131x_defs.h
@@ -0,0 +1,126 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et131x_defs.h - Defines, structs, enums, prototypes, etc. to assist with OS
+ *                 compatibility
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef __ET131X_DEFS_H__
+#define __ET131X_DEFS_H__
+
+/* Packet and header sizes */
+#define NIC_MIN_PACKET_SIZE     60
+
+/* Multicast list size */
+#define NIC_MAX_MCAST_LIST      128
+
+/* Supported Filters */
+#define ET131X_PACKET_TYPE_DIRECTED             0x0001
+#define ET131X_PACKET_TYPE_MULTICAST            0x0002
+#define ET131X_PACKET_TYPE_BROADCAST            0x0004
+#define ET131X_PACKET_TYPE_PROMISCUOUS          0x0008
+#define ET131X_PACKET_TYPE_ALL_MULTICAST        0x0010
+
+/* Tx Timeout */
+#define ET131X_TX_TIMEOUT       (1 * HZ)
+#define NIC_SEND_HANG_THRESHOLD 0
+
+/* MP_TCB flags */
+#define fMP_DEST_MULTI                  0x00000001
+#define fMP_DEST_BROAD                  0x00000002
+
+/* MP_ADAPTER flags */
+#define fMP_ADAPTER_RECV_LOOKASIDE      0x00000004
+#define fMP_ADAPTER_INTERRUPT_IN_USE    0x00000008
+#define fMP_ADAPTER_SECONDARY           0x00000010
+
+/* MP_SHARED flags */
+#define fMP_ADAPTER_SHUTDOWN            0x00100000
+#define fMP_ADAPTER_LOWER_POWER         0x00200000
+
+#define fMP_ADAPTER_NON_RECOVER_ERROR   0x00800000
+#define fMP_ADAPTER_RESET_IN_PROGRESS   0x01000000
+#define fMP_ADAPTER_NO_CABLE            0x02000000
+#define fMP_ADAPTER_HARDWARE_ERROR      0x04000000
+#define fMP_ADAPTER_REMOVE_IN_PROGRESS  0x08000000
+#define fMP_ADAPTER_HALT_IN_PROGRESS    0x10000000
+
+#define fMP_ADAPTER_FAIL_SEND_MASK      0x3ff00000
+#define fMP_ADAPTER_NOT_READY_MASK      0x3ff00000
+
+/* Some offsets in PCI config space that are actually used. */
+#define ET1310_PCI_MAX_PYLD             0x4C
+#define ET1310_PCI_MAC_ADDRESS          0xA4
+#define ET1310_PCI_EEPROM_STATUS        0xB2
+#define ET1310_PCI_ACK_NACK             0xC0
+#define ET1310_PCI_REPLAY               0xC2
+#define ET1310_PCI_L0L1LATENCY          0xCF
+
+/* PCI Vendor/Product IDs */
+#define ET131X_PCI_VENDOR_ID            0x11C1  /* Agere Systems */
+#define ET131X_PCI_DEVICE_ID_GIG        0xED00  /* ET1310 1000 Base-T 8 */
+#define ET131X_PCI_DEVICE_ID_FAST       0xED01  /* ET1310 100  Base-T */
+
+/* Define order of magnitude converter */
+#define NANO_IN_A_MICRO 1000
+
+#define PARM_RX_NUM_BUFS_DEF    4
+#define PARM_RX_TIME_INT_DEF    10
+#define PARM_RX_MEM_END_DEF     0x2bc
+#define PARM_TX_TIME_INT_DEF    40
+#define PARM_TX_NUM_BUFS_DEF    4
+#define PARM_DMA_CACHE_DEF      0
+
+
+#endif /* __ET131X_DEFS_H__ */
diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c
new file mode 100644
index 00000000000..8c8d6b87a25
--- /dev/null
+++ b/drivers/staging/et131x/et131x_initpci.c
@@ -0,0 +1,848 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et131x_initpci.c - Routines and data used to register the driver with the
+ *                    PCI (and PCI Express) subsystem, as well as basic driver
+ *                    init and startup.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+#include <linux/random.h>
+
+#include "et1310_phy.h"
+
+#include "et131x_adapter.h"
+
+#include "et1310_address_map.h"
+#include "et1310_tx.h"
+#include "et1310_rx.h"
+#include "et131x.h"
+
+#define INTERNAL_MEM_SIZE       0x400   /* 1024 of internal memory */
+#define INTERNAL_MEM_RX_OFFSET  0x1FF   /* 50%   Tx, 50%   Rx */
+
+/* Defines for Parameter Default/Min/Max vaules */
+#define PARM_SPEED_DUPLEX_MIN   0
+#define PARM_SPEED_DUPLEX_MAX   5
+
+/* Module parameter for manual speed setting
+ * Set Link speed and dublex manually (0-5)  [0]
+ *  1 : 10Mb   Half-Duplex
+ *  2 : 10Mb   Full-Duplex
+ *  3 : 100Mb  Half-Duplex
+ *  4 : 100Mb  Full-Duplex
+ *  5 : 1000Mb Full-Duplex
+ *  0 : Auto Speed Auto Duplex // default
+ */
+static u32 et131x_speed_set;
+module_param(et131x_speed_set, uint, 0);
+MODULE_PARM_DESC(et131x_speed_set,
+                "Set Link speed and dublex manually (0-5)  [0]\n"
+                "1 : 10Mb   Half-Duplex\n"
+                "2 : 10Mb   Full-Duplex\n"
+                "3 : 100Mb  Half-Duplex\n"
+                "4 : 100Mb  Full-Duplex\n"
+                "5 : 1000Mb Full-Duplex\n"
+                "0 : Auto Speed Auto Dublex");
+
+/**
+ * et131x_hwaddr_init - set up the MAC Address on the ET1310
+ * @adapter: pointer to our private adapter structure
+ */
+void et131x_hwaddr_init(struct et131x_adapter *adapter)
+{
+        /* If have our default mac from init and no mac address from
+         * EEPROM then we need to generate the last octet and set it on the
+         * device
+         */
+        if (adapter->rom_addr[0] == 0x00 &&
+            adapter->rom_addr[1] == 0x00 &&
+            adapter->rom_addr[2] == 0x00 &&
+            adapter->rom_addr[3] == 0x00 &&
+            adapter->rom_addr[4] == 0x00 &&
+            adapter->rom_addr[5] == 0x00) {
+                /*
+                 * We need to randomly generate the last octet so we
+                 * decrease our chances of setting the mac address to
+                 * same as another one of our cards in the system
+                 */
+                get_random_bytes(&adapter->addr[5], 1);
+                /*
+                 * We have the default value in the register we are
+                 * working with so we need to copy the current
+                 * address into the permanent address
+                 */
+                memcpy(adapter->rom_addr,
+                        adapter->addr, ETH_ALEN);
+        } else {
+                /* We do not have an override address, so set the
+                 * current address to the permanent address and add
+                 * it to the device
+                 */
+                memcpy(adapter->addr,
+                       adapter->rom_addr, ETH_ALEN);
+        }
+}
+
+
+/**
+ * et131x_pci_init       - initial PCI setup
+ * @adapter: pointer to our private adapter structure
+ * @pdev: our PCI device
+ *
+ * Perform the initial setup of PCI registers and if possible initialise
+ * the MAC address. At this point the I/O registers have yet to be mapped
+ */
+
+static int et131x_pci_init(struct et131x_adapter *adapter,
+                                                struct pci_dev *pdev)
+{
+        int i;
+        u8 max_payload;
+        u8 read_size_reg;
+
+        if (et131x_init_eeprom(adapter) < 0)
+                return -EIO;
+
+        /* Let's set up the PORT LOGIC Register.  First we need to know what
+         * the max_payload_size is
+         */
+        if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
+                dev_err(&pdev->dev,
+                    "Could not read PCI config space for Max Payload Size\n");
+                return -EIO;
+        }
+
+        /* Program the Ack/Nak latency and replay timers */
+        max_payload &= 0x07;    /* Only the lower 3 bits are valid */
+
+        if (max_payload < 2) {
+                static const u16 acknak[2] = { 0x76, 0xD0 };
+                static const u16 replay[2] = { 0x1E0, 0x2ED };
+
+                if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
+                                               acknak[max_payload])) {
+                        dev_err(&pdev->dev,
+                          "Could not write PCI config space for ACK/NAK\n");
+                        return -EIO;
+                }
+                if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
+                                               replay[max_payload])) {
+                        dev_err(&pdev->dev,
+                          "Could not write PCI config space for Replay Timer\n");
+                        return -EIO;
+                }
+        }
+
+        /* l0s and l1 latency timers.  We are using default values.
+         * Representing 001 for L0s and 010 for L1
+         */
+        if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
+                dev_err(&pdev->dev,
+                  "Could not write PCI config space for Latency Timers\n");
+                return -EIO;
+        }
+
+        /* Change the max read size to 2k */
+        if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
+                dev_err(&pdev->dev,
+                        "Could not read PCI config space for Max read size\n");
+                return -EIO;
+        }
+
+        read_size_reg &= 0x8f;
+        read_size_reg |= 0x40;
+
+        if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
+                dev_err(&pdev->dev,
+                      "Could not write PCI config space for Max read size\n");
+                return -EIO;
+        }
+
+        /* Get MAC address from config space if an eeprom exists, otherwise
+         * the MAC address there will not be valid
+         */
+        if (!adapter->has_eeprom) {
+                et131x_hwaddr_init(adapter);
+                return 0;
+        }
+
+        for (i = 0; i < ETH_ALEN; i++) {
+                if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
+                                        adapter->rom_addr + i)) {
+                        dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
+                        return -EIO;
+                }
+        }
+        memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
+        return 0;
+}
+
+/**
+ * et131x_error_timer_handler
+ * @data: timer-specific variable; here a pointer to our adapter structure
+ *
+ * The routine called when the error timer expires, to track the number of
+ * recurring errors.
+ */
+void et131x_error_timer_handler(unsigned long data)
+{
+        struct et131x_adapter *etdev = (struct et131x_adapter *) data;
+        u32 pm_csr;
+
+        pm_csr = readl(&etdev->regs->global.pm_csr);
+
+        if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
+                UpdateMacStatHostCounters(etdev);
+        else
+                dev_err(&etdev->pdev->dev,
+                    "No interrupts, in PHY coma, pm_csr = 0x%x\n", pm_csr);
+
+        if (!(etdev->bmsr & MI_BMSR_LINK_STATUS) &&
+            etdev->RegistryPhyComa &&
+            etdev->boot_coma < 11) {
+                etdev->boot_coma++;
+        }
+
+        if (etdev->boot_coma == 10) {
+                if (!(etdev->bmsr & MI_BMSR_LINK_STATUS)
+                    && etdev->RegistryPhyComa) {
+                        if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
+                                /* NOTE - This was originally a 'sync with
+                                 *  interrupt'. How to do that under Linux?
+                                 */
+                                et131x_enable_interrupts(etdev);
+                                EnablePhyComa(etdev);
+                        }
+                }
+        }
+
+        /* This is a periodic timer, so reschedule */
+        mod_timer(&etdev->ErrorTimer, jiffies +
+                                          TX_ERROR_PERIOD * HZ / 1000);
+}
+
+/**
+ * et131x_link_detection_handler
+ *
+ * Timer function for link up at driver load time
+ */
+void et131x_link_detection_handler(unsigned long data)
+{
+        struct et131x_adapter *etdev = (struct et131x_adapter *) data;
+        unsigned long flags;
+
+        if (etdev->MediaState == 0) {
+                spin_lock_irqsave(&etdev->Lock, flags);
+
+                etdev->MediaState = NETIF_STATUS_MEDIA_DISCONNECT;
+
+                spin_unlock_irqrestore(&etdev->Lock, flags);
+
+                netif_carrier_off(etdev->netdev);
+        }
+}
+
+/**
+ * et131x_configure_global_regs -       configure JAGCore global regs
+ * @etdev: pointer to our adapter structure
+ *
+ * Used to configure the global registers on the JAGCore
+ */
+void ConfigGlobalRegs(struct et131x_adapter *etdev)
+{
+        struct global_regs __iomem *regs = &etdev->regs->global;
+
+        writel(0, &regs->rxq_start_addr);
+        writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);
+
+        if (etdev->RegistryJumboPacket < 2048) {
+                /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
+                 * block of RAM that the driver can split between Tx
+                 * and Rx as it desires.  Our default is to split it
+                 * 50/50:
+                 */
+                writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);
+                writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);
+        } else if (etdev->RegistryJumboPacket < 8192) {
+                /* For jumbo packets > 2k but < 8k, split 50-50. */
+                writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);
+                writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);
+        } else {
+                /* 9216 is the only packet size greater than 8k that
+                 * is available. The Tx buffer has to be big enough
+                 * for one whole packet on the Tx side. We'll make
+                 * the Tx 9408, and give the rest to Rx
+                 */
+                writel(0x01b3, &regs->rxq_end_addr);
+                writel(0x01b4, &regs->txq_start_addr);
+        }
+
+        /* Initialize the loopback register. Disable all loopbacks. */
+        writel(0, &regs->loopback);
+
+        /* MSI Register */
+        writel(0, &regs->msi_config);
+
+        /* By default, disable the watchdog timer.  It will be enabled when
+         * a packet is queued.
+         */
+        writel(0, &regs->watchdog_timer);
+}
+
+
+/**
+ * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_adapter_setup(struct et131x_adapter *etdev)
+{
+        int status = 0;
+
+        /* Configure the JAGCore */
+        ConfigGlobalRegs(etdev);
+
+        ConfigMACRegs1(etdev);
+
+        /* Configure the MMC registers */
+        /* All we need to do is initialize the Memory Control Register */
+        writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl);
+
+        ConfigRxMacRegs(etdev);
+        ConfigTxMacRegs(etdev);
+
+        ConfigRxDmaRegs(etdev);
+        ConfigTxDmaRegs(etdev);
+
+        ConfigMacStatRegs(etdev);
+
+        /* Move the following code to Timer function?? */
+        status = et131x_xcvr_find(etdev);
+
+        if (status != 0)
+                dev_warn(&etdev->pdev->dev, "Could not find the xcvr\n");
+
+        /* Prepare the TRUEPHY library. */
+        ET1310_PhyInit(etdev);
+
+        /* Reset the phy now so changes take place */
+        ET1310_PhyReset(etdev);
+
+        /* Power down PHY */
+        ET1310_PhyPowerDown(etdev, 1);
+
+        /*
+         * We need to turn off 1000 base half dulplex, the mac does not
+         * support it. For the 10/100 part, turn off all gig advertisement
+         */
+        if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
+                ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
+        else
+                ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
+
+        /* Power up PHY */
+        ET1310_PhyPowerDown(etdev, 0);
+
+        et131x_setphy_normal(etdev);
+;       return status;
+}
+
+/**
+ * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
+ * @adapter: pointer to our private adapter structure
+ */
+void et131x_soft_reset(struct et131x_adapter *adapter)
+{
+        /* Disable MAC Core */
+        writel(0xc00f0000, &adapter->regs->mac.cfg1);
+
+        /* Set everything to a reset value */
+        writel(0x7F, &adapter->regs->global.sw_reset);
+        writel(0x000f0000, &adapter->regs->mac.cfg1);
+        writel(0x00000000, &adapter->regs->mac.cfg1);
+}
+
+/**
+ * et131x_align_allocated_memory - Align allocated memory on a given boundary
+ * @adapter: pointer to our adapter structure
+ * @phys_addr: pointer to Physical address
+ * @offset: pointer to the offset variable
+ * @mask: correct mask
+ */
+void et131x_align_allocated_memory(struct et131x_adapter *adapter,
+                                   uint64_t *phys_addr,
+                                   uint64_t *offset, uint64_t mask)
+{
+        uint64_t new_addr;
+
+        *offset = 0;
+
+        new_addr = *phys_addr & ~mask;
+
+        if (new_addr != *phys_addr) {
+                /* Move to next aligned block */
+                new_addr += mask + 1;
+                /* Return offset for adjusting virt addr */
+                *offset = new_addr - *phys_addr;
+                /* Return new physical address */
+                *phys_addr = new_addr;
+        }
+}
+
+/**
+ * et131x_adapter_memory_alloc
+ * @adapter: pointer to our private adapter structure
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h).
+ *
+ * Allocate all the memory blocks for send, receive and others.
+ */
+int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
+{
+        int status;
+
+        /* Allocate memory for the Tx Ring */
+        status = et131x_tx_dma_memory_alloc(adapter);
+        if (status != 0) {
+                dev_err(&adapter->pdev->dev,
+                          "et131x_tx_dma_memory_alloc FAILED\n");
+                return status;
+        }
+        /* Receive buffer memory allocation */
+        status = et131x_rx_dma_memory_alloc(adapter);
+        if (status != 0) {
+                dev_err(&adapter->pdev->dev,
+                          "et131x_rx_dma_memory_alloc FAILED\n");
+                et131x_tx_dma_memory_free(adapter);
+                return status;
+        }
+
+        /* Init receive data structures */
+        status = et131x_init_recv(adapter);
+        if (status != 0) {
+                dev_err(&adapter->pdev->dev,
+                        "et131x_init_recv FAILED\n");
+                et131x_tx_dma_memory_free(adapter);
+                et131x_rx_dma_memory_free(adapter);
+        }
+        return status;
+}
+
+/**
+ * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
+ * @adapter: pointer to our private adapter structure
+ */
+void et131x_adapter_memory_free(struct et131x_adapter *adapter)
+{
+        /* Free DMA memory */
+        et131x_tx_dma_memory_free(adapter);
+        et131x_rx_dma_memory_free(adapter);
+}
+
+
+
+/**
+ * et131x_adapter_init
+ * @etdev: pointer to the private adapter struct
+ * @pdev: pointer to the PCI device
+ *
+ * Initialize the data structures for the et131x_adapter object and link
+ * them together with the platform provided device structures.
+ */
+
+
+static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
+                struct pci_dev *pdev)
+{
+        static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
+        static const u8 duplex[] = { 0, 1, 2, 1, 2, 2 };
+        static const u16 speed[] = { 0, 10, 10, 100, 100, 1000 };
+
+        struct et131x_adapter *etdev;
+
+        /* Setup the fundamental net_device and private adapter structure
+         * elements  */
+        SET_NETDEV_DEV(netdev, &pdev->dev);
+
+        /* Allocate private adapter struct and copy in relevant information */
+        etdev = netdev_priv(netdev);
+        etdev->pdev = pci_dev_get(pdev);
+        etdev->netdev = netdev;
+
+        /* Do the same for the netdev struct */
+        netdev->irq = pdev->irq;
+        netdev->base_addr = pci_resource_start(pdev, 0);
+
+        /* Initialize spinlocks here */
+        spin_lock_init(&etdev->Lock);
+        spin_lock_init(&etdev->TCBSendQLock);
+        spin_lock_init(&etdev->TCBReadyQLock);
+        spin_lock_init(&etdev->send_hw_lock);
+        spin_lock_init(&etdev->rcv_lock);
+        spin_lock_init(&etdev->RcvPendLock);
+        spin_lock_init(&etdev->FbrLock);
+        spin_lock_init(&etdev->PHYLock);
+
+        /* Parse configuration parameters into the private adapter struct */
+        if (et131x_speed_set)
+                dev_info(&etdev->pdev->dev,
+                        "Speed set manually to : %d\n", et131x_speed_set);
+
+        etdev->SpeedDuplex = et131x_speed_set;
+        etdev->RegistryJumboPacket = 1514;      /* 1514-9216 */
+
+        /* Set the MAC address to a default */
+        memcpy(etdev->addr, default_mac, ETH_ALEN);
+
+        /* Decode SpeedDuplex
+         *
+         * Set up as if we are auto negotiating always and then change if we
+         * go into force mode
+         *
+         * If we are the 10/100 device, and gigabit is somehow requested then
+         * knock it down to 100 full.
+         */
+        if (etdev->pdev->device == ET131X_PCI_DEVICE_ID_FAST &&
+            etdev->SpeedDuplex == 5)
+                etdev->SpeedDuplex = 4;
+
+        etdev->AiForceSpeed = speed[etdev->SpeedDuplex];
+        etdev->AiForceDpx = duplex[etdev->SpeedDuplex]; /* Auto FDX */
+
+        return etdev;
+}
+
+/**
+ * et131x_pci_setup - Perform device initialization
+ * @pdev: a pointer to the device's pci_dev structure
+ * @ent: this device's entry in the pci_device_id table
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ *
+ * Registered in the pci_driver structure, this function is called when the
+ * PCI subsystem finds a new PCI device which matches the information
+ * contained in the pci_device_id table. This routine is the equivalent to
+ * a device insertion routine.
+ */
+
+static int __devinit et131x_pci_setup(struct pci_dev *pdev,
+                               const struct pci_device_id *ent)
+{
+        int result = -EBUSY;
+        int pm_cap;
+        bool pci_using_dac;
+        struct net_device *netdev;
+        struct et131x_adapter *adapter;
+
+        /* Enable the device via the PCI subsystem */
+        if (pci_enable_device(pdev) != 0) {
+                dev_err(&pdev->dev,
+                        "pci_enable_device() failed\n");
+                return -EIO;
+        }
+
+        /* Perform some basic PCI checks */
+        if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
+                dev_err(&pdev->dev,
+                          "Can't find PCI device's base address\n");
+                goto err_disable;
+        }
+
+        if (pci_request_regions(pdev, DRIVER_NAME)) {
+                dev_err(&pdev->dev,
+                        "Can't get PCI resources\n");
+                goto err_disable;
+        }
+
+        /* Enable PCI bus mastering */
+        pci_set_master(pdev);
+
+        /* Query PCI for Power Mgmt Capabilities
+         *
+         * NOTE: Now reading PowerMgmt in another location; is this still
+         * needed?
+         */
+        pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
+        if (pm_cap == 0) {
+                dev_err(&pdev->dev,
+                          "Cannot find Power Management capabilities\n");
+                result = -EIO;
+                goto err_release_res;
+        }
+
+        /* Check the DMA addressing support of this device */
+        if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
+                pci_using_dac = true;
+
+                result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
+                if (result != 0) {
+                        dev_err(&pdev->dev,
+                                  "Unable to obtain 64 bit DMA for consistent allocations\n");
+                        goto err_release_res;
+                }
+        } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
+                pci_using_dac = false;
+        } else {
+                dev_err(&pdev->dev,
+                        "No usable DMA addressing method\n");
+                result = -EIO;
+                goto err_release_res;
+        }
+
+        /* Allocate netdev and private adapter structs */
+        netdev = et131x_device_alloc();
+        if (netdev == NULL) {
+                dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
+                result = -ENOMEM;
+                goto err_release_res;
+        }
+        adapter = et131x_adapter_init(netdev, pdev);
+        /* Initialise the PCI setup for the device */
+        et131x_pci_init(adapter, pdev);
+
+        /* Map the bus-relative registers to system virtual memory */
+        adapter->regs = pci_ioremap_bar(pdev, 0);
+        if (adapter->regs == NULL) {
+                dev_err(&pdev->dev, "Cannot map device registers\n");
+                result = -ENOMEM;
+                goto err_free_dev;
+        }
+
+        /* If Phy COMA mode was enabled when we went down, disable it here. */
+        writel(ET_PMCSR_INIT,  &adapter->regs->global.pm_csr);
+
+        /* Issue a global reset to the et1310 */
+        et131x_soft_reset(adapter);
+
+        /* Disable all interrupts (paranoid) */
+        et131x_disable_interrupts(adapter);
+
+        /* Allocate DMA memory */
+        result = et131x_adapter_memory_alloc(adapter);
+        if (result != 0) {
+                dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
+                goto err_iounmap;
+        }
+
+        /* Init send data structures */
+        et131x_init_send(adapter);
+
+        /*
+         * Set up the task structure for the ISR's deferred handler
+         */
+        INIT_WORK(&adapter->task, et131x_isr_handler);
+
+        /* Copy address into the net_device struct */
+        memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
+
+        /* Setup et1310 as per the documentation */
+        et131x_adapter_setup(adapter);
+
+        /* Create a timer to count errors received by the NIC */
+        init_timer(&adapter->ErrorTimer);
+
+        adapter->ErrorTimer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
+        adapter->ErrorTimer.function = et131x_error_timer_handler;
+        adapter->ErrorTimer.data = (unsigned long)adapter;
+
+        /* Initialize link state */
+        et131x_link_detection_handler((unsigned long)adapter);
+
+        /* Initialize variable for counting how long we do not have
+                                                        link status */
+        adapter->boot_coma = 0;
+
+        /* We can enable interrupts now
+         *
+         *  NOTE - Because registration of interrupt handler is done in the
+         *         device's open(), defer enabling device interrupts to that
+         *         point
+         */
+
+        /* Register the net_device struct with the Linux network layer */
+        result = register_netdev(netdev);
+        if (result != 0) {
+                dev_err(&pdev->dev, "register_netdev() failed\n");
+                goto err_mem_free;
+        }
+
+        /* Register the net_device struct with the PCI subsystem. Save a copy
+         * of the PCI config space for this device now that the device has
+         * been initialized, just in case it needs to be quickly restored.
+         */
+        pci_set_drvdata(pdev, netdev);
+        pci_save_state(adapter->pdev);
+        return result;
+
+err_mem_free:
+        et131x_adapter_memory_free(adapter);
+err_iounmap:
+        iounmap(adapter->regs);
+err_free_dev:
+        pci_dev_put(pdev);
+        free_netdev(netdev);
+err_release_res:
+        pci_release_regions(pdev);
+err_disable:
+        pci_disable_device(pdev);
+        return result;
+}
+
+/**
+ * et131x_pci_remove
+ * @pdev: a pointer to the device's pci_dev structure
+ *
+ * Registered in the pci_driver structure, this function is called when the
+ * PCI subsystem detects that a PCI device which matches the information
+ * contained in the pci_device_id table has been removed.
+ */
+
+static void __devexit et131x_pci_remove(struct pci_dev *pdev)
+{
+        struct net_device *netdev;
+        struct et131x_adapter *adapter;
+
+        /* Retrieve the net_device pointer from the pci_dev struct, as well
+         * as the private adapter struct
+         */
+        netdev = pci_get_drvdata(pdev);
+        adapter = netdev_priv(netdev);
+
+        /* Perform device cleanup */
+        unregister_netdev(netdev);
+        et131x_adapter_memory_free(adapter);
+        iounmap(adapter->regs);
+        pci_dev_put(adapter->pdev);
+        free_netdev(netdev);
+        pci_release_regions(pdev);
+        pci_disable_device(pdev);
+}
+
+static struct pci_device_id et131x_pci_table[] __devinitdata = {
+        {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
+         PCI_ANY_ID, 0, 0, 0UL},
+        {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
+         PCI_ANY_ID, 0, 0, 0UL},
+        {0,}
+};
+
+MODULE_DEVICE_TABLE(pci, et131x_pci_table);
+
+static struct pci_driver et131x_driver = {
+        .name           = DRIVER_NAME,
+        .id_table       = et131x_pci_table,
+        .probe          = et131x_pci_setup,
+        .remove         = __devexit_p(et131x_pci_remove),
+        .suspend        = NULL,         /* et131x_pci_suspend */
+        .resume         = NULL,         /* et131x_pci_resume */
+};
+
+
+/**
+ * et131x_init_module - The "main" entry point called on driver initialization
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+static int __init et131x_init_module(void)
+{
+        if (et131x_speed_set < PARM_SPEED_DUPLEX_MIN ||
+            et131x_speed_set > PARM_SPEED_DUPLEX_MAX) {
+                printk(KERN_WARNING "et131x: invalid speed setting ignored.\n");
+                et131x_speed_set = 0;
+        }
+        return pci_register_driver(&et131x_driver);
+}
+
+/**
+ * et131x_cleanup_module - The entry point called on driver cleanup
+ */
+static void __exit et131x_cleanup_module(void)
+{
+        pci_unregister_driver(&et131x_driver);
+}
+
+module_init(et131x_init_module);
+module_exit(et131x_cleanup_module);
+
+/* Modinfo parameters (filled out using defines from et131x_version.h) */
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_INFO);
+MODULE_LICENSE(DRIVER_LICENSE);
diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c
new file mode 100644
index 00000000000..9c33209c840
--- /dev/null
+++ b/drivers/staging/et131x/et131x_isr.c
@@ -0,0 +1,480 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
+ *                for processing interrupts from the device.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <asm/system.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et131x_adapter.h"
+#include "et131x.h"
+
+/*
+ * For interrupts, normal running is:
+ *       rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
+ *       watchdog_interrupt & txdma_xfer_done
+ *
+ * In both cases, when flow control is enabled for either Tx or bi-direction,
+ * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
+ * buffer rings are running low.
+ */
+#define INT_MASK_DISABLE            0xffffffff
+
+/* NOTE: Masking out MAC_STAT Interrupt for now...
+ * #define INT_MASK_ENABLE             0xfff6bf17
+ * #define INT_MASK_ENABLE_NO_FLOW     0xfff6bfd7
+ */
+#define INT_MASK_ENABLE             0xfffebf17
+#define INT_MASK_ENABLE_NO_FLOW     0xfffebfd7
+
+
+/**
+ *      et131x_enable_interrupts        -       enable interrupt
+ *      @adapter: et131x device
+ *
+ *      Enable the appropriate interrupts on the ET131x according to our
+ *      configuration
+ */
+
+void et131x_enable_interrupts(struct et131x_adapter *adapter)
+{
+        u32 mask;
+
+        /* Enable all global interrupts */
+        if (adapter->flowcontrol == FLOW_TXONLY || adapter->flowcontrol == FLOW_BOTH)
+                mask = INT_MASK_ENABLE;
+        else
+                mask = INT_MASK_ENABLE_NO_FLOW;
+
+        adapter->CachedMaskValue = mask;
+        writel(mask, &adapter->regs->global.int_mask);
+}
+
+/**
+ *      et131x_disable_interrupts       -       interrupt disable
+ *      @adapter: et131x device
+ *
+ *      Block all interrupts from the et131x device at the device itself
+ */
+
+void et131x_disable_interrupts(struct et131x_adapter *adapter)
+{
+        /* Disable all global interrupts */
+        adapter->CachedMaskValue = INT_MASK_DISABLE;
+        writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
+}
+
+
+/**
+ * et131x_isr - The Interrupt Service Routine for the driver.
+ * @irq: the IRQ on which the interrupt was received.
+ * @dev_id: device-specific info (here a pointer to a net_device struct)
+ *
+ * Returns a value indicating if the interrupt was handled.
+ */
+
+irqreturn_t et131x_isr(int irq, void *dev_id)
+{
+        bool handled = true;
+        struct net_device *netdev = (struct net_device *)dev_id;
+        struct et131x_adapter *adapter = NULL;
+        u32 status;
+
+        if (!netif_device_present(netdev)) {
+                handled = false;
+                goto out;
+        }
+
+        adapter = netdev_priv(netdev);
+
+        /* If the adapter is in low power state, then it should not
+         * recognize any interrupt
+         */
+
+        /* Disable Device Interrupts */
+        et131x_disable_interrupts(adapter);
+
+        /* Get a copy of the value in the interrupt status register
+         * so we can process the interrupting section
+         */
+        status = readl(&adapter->regs->global.int_status);
+
+        if (adapter->flowcontrol == FLOW_TXONLY ||
+            adapter->flowcontrol == FLOW_BOTH) {
+                status &= ~INT_MASK_ENABLE;
+        } else {
+                status &= ~INT_MASK_ENABLE_NO_FLOW;
+        }
+
+        /* Make sure this is our interrupt */
+        if (!status) {
+                handled = false;
+                et131x_enable_interrupts(adapter);
+                goto out;
+        }
+
+        /* This is our interrupt, so process accordingly */
+
+        if (status & ET_INTR_WATCHDOG) {
+                struct tcb *tcb = adapter->tx_ring.send_head;
+
+                if (tcb)
+                        if (++tcb->stale > 1)
+                                status |= ET_INTR_TXDMA_ISR;
+
+                if (adapter->rx_ring.UnfinishedReceives)
+                        status |= ET_INTR_RXDMA_XFR_DONE;
+                else if (tcb == NULL)
+                        writel(0, &adapter->regs->global.watchdog_timer);
+
+                status &= ~ET_INTR_WATCHDOG;
+        }
+
+        if (status == 0) {
+                /* This interrupt has in some way been "handled" by
+                 * the ISR. Either it was a spurious Rx interrupt, or
+                 * it was a Tx interrupt that has been filtered by
+                 * the ISR.
+                 */
+                et131x_enable_interrupts(adapter);
+                goto out;
+        }
+
+        /* We need to save the interrupt status value for use in our
+         * DPC. We will clear the software copy of that in that
+         * routine.
+         */
+        adapter->stats.InterruptStatus = status;
+
+        /* Schedule the ISR handler as a bottom-half task in the
+         * kernel's tq_immediate queue, and mark the queue for
+         * execution
+         */
+        schedule_work(&adapter->task);
+out:
+        return IRQ_RETVAL(handled);
+}
+
+/**
+ * et131x_isr_handler - The ISR handler
+ * @p_adapter, a pointer to the device's private adapter structure
+ *
+ * scheduled to run in a deferred context by the ISR. This is where the ISR's
+ * work actually gets done.
+ */
+void et131x_isr_handler(struct work_struct *work)
+{
+        struct et131x_adapter *etdev =
+                container_of(work, struct et131x_adapter, task);
+        u32 status = etdev->stats.InterruptStatus;
+        struct address_map __iomem *iomem = etdev->regs;
+
+        /*
+         * These first two are by far the most common.  Once handled, we clear
+         * their two bits in the status word.  If the word is now zero, we
+         * exit.
+         */
+        /* Handle all the completed Transmit interrupts */
+        if (status & ET_INTR_TXDMA_ISR)
+                et131x_handle_send_interrupt(etdev);
+
+        /* Handle all the completed Receives interrupts */
+        if (status & ET_INTR_RXDMA_XFR_DONE)
+                et131x_handle_recv_interrupt(etdev);
+
+        status &= 0xffffffd7;
+
+        if (status) {
+                /* Handle the TXDMA Error interrupt */
+                if (status & ET_INTR_TXDMA_ERR) {
+                        u32 txdma_err;
+
+                        /* Following read also clears the register (COR) */
+                        txdma_err = readl(&iomem->txdma.tx_dma_error);
+
+                        dev_warn(&etdev->pdev->dev,
+                                    "TXDMA_ERR interrupt, error = %d\n",
+                                    txdma_err);
+                }
+
+                /* Handle Free Buffer Ring 0 and 1 Low interrupt */
+                if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
+                        /*
+                         * This indicates the number of unused buffers in
+                         * RXDMA free buffer ring 0 is <= the limit you
+                         * programmed. Free buffer resources need to be
+                         * returned.  Free buffers are consumed as packets
+                         * are passed from the network to the host. The host
+                         * becomes aware of the packets from the contents of
+                         * the packet status ring. This ring is queried when
+                         * the packet done interrupt occurs. Packets are then
+                         * passed to the OS. When the OS is done with the
+                         * packets the resources can be returned to the
+                         * ET1310 for re-use. This interrupt is one method of
+                         * returning resources.
+                         */
+
+                        /* If the user has flow control on, then we will
+                         * send a pause packet, otherwise just exit
+                         */
+                        if (etdev->flowcontrol == FLOW_TXONLY ||
+                            etdev->flowcontrol == FLOW_BOTH) {
+                                u32 pm_csr;
+
+                                /* Tell the device to send a pause packet via
+                                 * the back pressure register (bp req  and
+                                 * bp xon/xoff)
+                                 */
+                                pm_csr = readl(&iomem->global.pm_csr);
+                                if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
+                                        writel(3, &iomem->txmac.bp_ctrl);
+                        }
+                }
+
+                /* Handle Packet Status Ring Low Interrupt */
+                if (status & ET_INTR_RXDMA_STAT_LOW) {
+
+                        /*
+                         * Same idea as with the two Free Buffer Rings.
+                         * Packets going from the network to the host each
+                         * consume a free buffer resource and a packet status
+                         * resource.  These resoures are passed to the OS.
+                         * When the OS is done with the resources, they need
+                         * to be returned to the ET1310. This is one method
+                         * of returning the resources.
+                         */
+                }
+
+                /* Handle RXDMA Error Interrupt */
+                if (status & ET_INTR_RXDMA_ERR) {
+                        /*
+                         * The rxdma_error interrupt is sent when a time-out
+                         * on a request issued by the JAGCore has occurred or
+                         * a completion is returned with an un-successful
+                         * status.  In both cases the request is considered
+                         * complete. The JAGCore will automatically re-try the
+                         * request in question. Normally information on events
+                         * like these are sent to the host using the "Advanced
+                         * Error Reporting" capability. This interrupt is
+                         * another way of getting similar information. The
+                         * only thing required is to clear the interrupt by
+                         * reading the ISR in the global resources. The
+                         * JAGCore will do a re-try on the request.  Normally
+                         * you should never see this interrupt. If you start
+                         * to see this interrupt occurring frequently then
+                         * something bad has occurred. A reset might be the
+                         * thing to do.
+                         */
+                        /* TRAP();*/
+
+                        dev_warn(&etdev->pdev->dev,
+                                    "RxDMA_ERR interrupt, error %x\n",
+                                    readl(&iomem->txmac.tx_test));
+                }
+
+                /* Handle the Wake on LAN Event */
+                if (status & ET_INTR_WOL) {
+                        /*
+                         * This is a secondary interrupt for wake on LAN.
+                         * The driver should never see this, if it does,
+                         * something serious is wrong. We will TRAP the
+                         * message when we are in DBG mode, otherwise we
+                         * will ignore it.
+                         */
+                        dev_err(&etdev->pdev->dev, "WAKE_ON_LAN interrupt\n");
+                }
+
+                /* Handle the PHY interrupt */
+                if (status & ET_INTR_PHY) {
+                        u32 pm_csr;
+                        u16 bmsr_ints;
+                        u16 bmsr_data;
+                        u16 myisr;
+
+                        /* If we are in coma mode when we get this interrupt,
+                         * we need to disable it.
+                         */
+                        pm_csr = readl(&iomem->global.pm_csr);
+                        if (pm_csr & ET_PM_PHY_SW_COMA) {
+                                /*
+                                 * Check to see if we are in coma mode and if
+                                 * so, disable it because we will not be able
+                                 * to read PHY values until we are out.
+                                 */
+                                DisablePhyComa(etdev);
+                        }
+
+                        /* Read the PHY ISR to clear the reason for the
+                         * interrupt.
+                         */
+                        MiRead(etdev, (uint8_t) offsetof(struct mi_regs, isr),
+                               &myisr);
+
+                        if (!etdev->ReplicaPhyLoopbk) {
+                                MiRead(etdev,
+                                       (uint8_t) offsetof(struct mi_regs, bmsr),
+                                       &bmsr_data);
+
+                                bmsr_ints = etdev->bmsr ^ bmsr_data;
+                                etdev->bmsr = bmsr_data;
+
+                                /* Do all the cable in / cable out stuff */
+                                et131x_Mii_check(etdev, bmsr_data, bmsr_ints);
+                        }
+                }
+
+                /* Let's move on to the TxMac */
+                if (status & ET_INTR_TXMAC) {
+                        u32 err = readl(&iomem->txmac.err);
+
+                        /*
+                         * When any of the errors occur and TXMAC generates
+                         * an interrupt to report these errors, it usually
+                         * means that TXMAC has detected an error in the data
+                         * stream retrieved from the on-chip Tx Q. All of
+                         * these errors are catastrophic and TXMAC won't be
+                         * able to recover data when these errors occur.  In
+                         * a nutshell, the whole Tx path will have to be reset
+                         * and re-configured afterwards.
+                         */
+                        dev_warn(&etdev->pdev->dev,
+                                    "TXMAC interrupt, error 0x%08x\n",
+                                    err);
+
+                        /* If we are debugging, we want to see this error,
+                         * otherwise we just want the device to be reset and
+                         * continue
+                         */
+                }
+
+                /* Handle RXMAC Interrupt */
+                if (status & ET_INTR_RXMAC) {
+                        /*
+                         * These interrupts are catastrophic to the device,
+                         * what we need to do is disable the interrupts and
+                         * set the flag to cause us to reset so we can solve
+                         * this issue.
+                         */
+                        /* MP_SET_FLAG( etdev,
+                                                fMP_ADAPTER_HARDWARE_ERROR); */
+
+                        dev_warn(&etdev->pdev->dev,
+                          "RXMAC interrupt, error 0x%08x.  Requesting reset\n",
+                                    readl(&iomem->rxmac.err_reg));
+
+                        dev_warn(&etdev->pdev->dev,
+                                    "Enable 0x%08x, Diag 0x%08x\n",
+                                    readl(&iomem->rxmac.ctrl),
+                                    readl(&iomem->rxmac.rxq_diag));
+
+                        /*
+                         * If we are debugging, we want to see this error,
+                         * otherwise we just want the device to be reset and
+                         * continue
+                         */
+                }
+
+                /* Handle MAC_STAT Interrupt */
+                if (status & ET_INTR_MAC_STAT) {
+                        /*
+                         * This means at least one of the un-masked counters
+                         * in the MAC_STAT block has rolled over.  Use this
+                         * to maintain the top, software managed bits of the
+                         * counter(s).
+                         */
+                        HandleMacStatInterrupt(etdev);
+                }
+
+                /* Handle SLV Timeout Interrupt */
+                if (status & ET_INTR_SLV_TIMEOUT) {
+                        /*
+                         * This means a timeout has occurred on a read or
+                         * write request to one of the JAGCore registers. The
+                         * Global Resources block has terminated the request
+                         * and on a read request, returned a "fake" value.
+                         * The most likely reasons are: Bad Address or the
+                         * addressed module is in a power-down state and
+                         * can't respond.
+                         */
+                }
+        }
+        et131x_enable_interrupts(etdev);
+}
diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c
new file mode 100644
index 00000000000..5f25bbad36b
--- /dev/null
+++ b/drivers/staging/et131x/et131x_netdev.c
@@ -0,0 +1,686 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et131x_netdev.c - Routines and data required by all Linux network devices.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#include "et131x_version.h"
+#include "et131x_defs.h"
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/pci.h>
+#include <asm/system.h>
+
+#include <linux/mii.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+
+#include "et1310_phy.h"
+#include "et1310_tx.h"
+#include "et131x_adapter.h"
+#include "et131x.h"
+
+/**
+ * et131x_stats - Return the current device statistics.
+ * @netdev: device whose stats are being queried
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+static struct net_device_stats *et131x_stats(struct net_device *netdev)
+{
+        struct et131x_adapter *adapter = netdev_priv(netdev);
+        struct net_device_stats *stats = &adapter->net_stats;
+        struct ce_stats *devstat = &adapter->stats;
+
+        stats->rx_errors = devstat->length_err + devstat->alignment_err +
+            devstat->crc_err + devstat->code_violations + devstat->other_errors;
+        stats->tx_errors = devstat->max_pkt_error;
+        stats->multicast = devstat->multircv;
+        stats->collisions = devstat->collisions;
+
+        stats->rx_length_errors = devstat->length_err;
+        stats->rx_over_errors = devstat->rx_ov_flow;
+        stats->rx_crc_errors = devstat->crc_err;
+
+        /* NOTE: These stats don't have corresponding values in CE_STATS,
+         * so we're going to have to update these directly from within the
+         * TX/RX code
+         */
+        /* stats->rx_bytes            = 20; devstat->; */
+        /* stats->tx_bytes            = 20;  devstat->; */
+        /* stats->rx_dropped          = devstat->; */
+        /* stats->tx_dropped          = devstat->; */
+
+        /*  NOTE: Not used, can't find analogous statistics */
+        /* stats->rx_frame_errors     = devstat->; */
+        /* stats->rx_fifo_errors      = devstat->; */
+        /* stats->rx_missed_errors    = devstat->; */
+
+        /* stats->tx_aborted_errors   = devstat->; */
+        /* stats->tx_carrier_errors   = devstat->; */
+        /* stats->tx_fifo_errors      = devstat->; */
+        /* stats->tx_heartbeat_errors = devstat->; */
+        /* stats->tx_window_errors    = devstat->; */
+        return stats;
+}
+
+/**
+ * et131x_open - Open the device for use.
+ * @netdev: device to be opened
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_open(struct net_device *netdev)
+{
+        int result = 0;
+        struct et131x_adapter *adapter = netdev_priv(netdev);
+
+        /* Start the timer to track NIC errors */
+        add_timer(&adapter->ErrorTimer);
+
+        /* Register our IRQ */
+        result = request_irq(netdev->irq, et131x_isr, IRQF_SHARED,
+                                        netdev->name, netdev);
+        if (result) {
+                dev_err(&adapter->pdev->dev, "c ould not register IRQ %d\n",
+                        netdev->irq);
+                return result;
+        }
+
+        /* Enable the Tx and Rx DMA engines (if not already enabled) */
+        et131x_rx_dma_enable(adapter);
+        et131x_tx_dma_enable(adapter);
+
+        /* Enable device interrupts */
+        et131x_enable_interrupts(adapter);
+
+        adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE;
+
+        /* We're ready to move some data, so start the queue */
+        netif_start_queue(netdev);
+        return result;
+}
+
+/**
+ * et131x_close - Close the device
+ * @netdev: device to be closed
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_close(struct net_device *netdev)
+{
+        struct et131x_adapter *adapter = netdev_priv(netdev);
+
+        /* First thing is to stop the queue */
+        netif_stop_queue(netdev);
+
+        /* Stop the Tx and Rx DMA engines */
+        et131x_rx_dma_disable(adapter);
+        et131x_tx_dma_disable(adapter);
+
+        /* Disable device interrupts */
+        et131x_disable_interrupts(adapter);
+
+        /* Deregistering ISR */
+        adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE;
+        free_irq(netdev->irq, netdev);
+
+        /* Stop the error timer */
+        del_timer_sync(&adapter->ErrorTimer);
+        return 0;
+}
+
+/**
+ * et131x_ioctl_mii - The function which handles MII IOCTLs
+ * @netdev: device on which the query is being made
+ * @reqbuf: the request-specific data buffer
+ * @cmd: the command request code
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_ioctl_mii(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
+{
+        int status = 0;
+        struct et131x_adapter *etdev = netdev_priv(netdev);
+        struct mii_ioctl_data *data = if_mii(reqbuf);
+
+        switch (cmd) {
+        case SIOCGMIIPHY:
+                data->phy_id = etdev->stats.xcvr_addr;
+                break;
+
+        case SIOCGMIIREG:
+                if (!capable(CAP_NET_ADMIN))
+                        status = -EPERM;
+                else
+                        status = MiRead(etdev,
+                                        data->reg_num, &data->val_out);
+                break;
+
+        case SIOCSMIIREG:
+                if (!capable(CAP_NET_ADMIN))
+                        status = -EPERM;
+                else
+                        status = MiWrite(etdev, data->reg_num,
+                                         data->val_in);
+                break;
+
+        default:
+                status = -EOPNOTSUPP;
+        }
+        return status;
+}
+
+/**
+ * et131x_ioctl - The I/O Control handler for the driver
+ * @netdev: device on which the control request is being made
+ * @reqbuf: a pointer to the IOCTL request buffer
+ * @cmd: the IOCTL command code
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
+{
+        int status = 0;
+
+        switch (cmd) {
+        case SIOCGMIIPHY:
+        case SIOCGMIIREG:
+        case SIOCSMIIREG:
+                status = et131x_ioctl_mii(netdev, reqbuf, cmd);
+                break;
+
+        default:
+                status = -EOPNOTSUPP;
+        }
+        return status;
+}
+
+/**
+ * et131x_set_packet_filter - Configures the Rx Packet filtering on the device
+ * @adapter: pointer to our private adapter structure
+ *
+ * FIXME: lot of dups with MAC code
+ *
+ * Returns 0 on success, errno on failure
+ */
+int et131x_set_packet_filter(struct et131x_adapter *adapter)
+{
+        int status = 0;
+        uint32_t filter = adapter->PacketFilter;
+        u32 ctrl;
+        u32 pf_ctrl;
+
+        ctrl = readl(&adapter->regs->rxmac.ctrl);
+        pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
+
+        /* Default to disabled packet filtering.  Enable it in the individual
+         * case statements that require the device to filter something
+         */
+        ctrl |= 0x04;
+
+        /* Set us to be in promiscuous mode so we receive everything, this
+         * is also true when we get a packet filter of 0
+         */
+        if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
+                pf_ctrl &= ~7;  /* Clear filter bits */
+        else {
+                /*
+                 * Set us up with Multicast packet filtering.  Three cases are
+                 * possible - (1) we have a multi-cast list, (2) we receive ALL
+                 * multicast entries or (3) we receive none.
+                 */
+                if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
+                        pf_ctrl &= ~2;  /* Multicast filter bit */
+                else {
+                        SetupDeviceForMulticast(adapter);
+                        pf_ctrl |= 2;
+                        ctrl &= ~0x04;
+                }
+
+                /* Set us up with Unicast packet filtering */
+                if (filter & ET131X_PACKET_TYPE_DIRECTED) {
+                        SetupDeviceForUnicast(adapter);
+                        pf_ctrl |= 4;
+                        ctrl &= ~0x04;
+                }
+
+                /* Set us up with Broadcast packet filtering */
+                if (filter & ET131X_PACKET_TYPE_BROADCAST) {
+                        pf_ctrl |= 1;   /* Broadcast filter bit */
+                        ctrl &= ~0x04;
+                } else
+                        pf_ctrl &= ~1;
+
+                /* Setup the receive mac configuration registers - Packet
+                 * Filter control + the enable / disable for packet filter
+                 * in the control reg.
+                 */
+                writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
+                writel(ctrl, &adapter->regs->rxmac.ctrl);
+        }
+        return status;
+}
+
+/**
+ * et131x_multicast - The handler to configure multicasting on the interface
+ * @netdev: a pointer to a net_device struct representing the device
+ */
+void et131x_multicast(struct net_device *netdev)
+{
+        struct et131x_adapter *adapter = netdev_priv(netdev);
+        uint32_t PacketFilter = 0;
+        unsigned long flags;
+        struct netdev_hw_addr *ha;
+        int i;
+
+        spin_lock_irqsave(&adapter->Lock, flags);
+
+        /* Before we modify the platform-independent filter flags, store them
+         * locally. This allows us to determine if anything's changed and if
+         * we even need to bother the hardware
+         */
+        PacketFilter = adapter->PacketFilter;
+
+        /* Clear the 'multicast' flag locally; because we only have a single
+         * flag to check multicast, and multiple multicast addresses can be
+         * set, this is the easiest way to determine if more than one
+         * multicast address is being set.
+         */
+        PacketFilter &= ~ET131X_PACKET_TYPE_MULTICAST;
+
+        /* Check the net_device flags and set the device independent flags
+         * accordingly
+         */
+
+        if (netdev->flags & IFF_PROMISC)
+                adapter->PacketFilter |= ET131X_PACKET_TYPE_PROMISCUOUS;
+        else
+                adapter->PacketFilter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
+
+        if (netdev->flags & IFF_ALLMULTI)
+                adapter->PacketFilter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
+
+        if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
+                adapter->PacketFilter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
+
+        if (netdev_mc_count(netdev) < 1) {
+                adapter->PacketFilter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
+                adapter->PacketFilter &= ~ET131X_PACKET_TYPE_MULTICAST;
+        } else
+                adapter->PacketFilter |= ET131X_PACKET_TYPE_MULTICAST;
+
+        /* Set values in the private adapter struct */
+        i = 0;
+        netdev_for_each_mc_addr(ha, netdev) {
+                if (i == NIC_MAX_MCAST_LIST)
+                        break;
+                memcpy(adapter->MCList[i++], ha->addr, ETH_ALEN);
+        }
+        adapter->MCAddressCount = i;
+
+        /* Are the new flags different from the previous ones? If not, then no
+         * action is required
+         *
+         * NOTE - This block will always update the MCList with the hardware,
+         *        even if the addresses aren't the same.
+         */
+        if (PacketFilter != adapter->PacketFilter) {
+                /* Call the device's filter function */
+                et131x_set_packet_filter(adapter);
+        }
+        spin_unlock_irqrestore(&adapter->Lock, flags);
+}
+
+/**
+ * et131x_tx - The handler to tx a packet on the device
+ * @skb: data to be Tx'd
+ * @netdev: device on which data is to be Tx'd
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
+{
+        int status = 0;
+
+        /* Save the timestamp for the TX timeout watchdog */
+        netdev->trans_start = jiffies;
+
+        /* Call the device-specific data Tx routine */
+        status = et131x_send_packets(skb, netdev);
+
+        /* Check status and manage the netif queue if necessary */
+        if (status != 0) {
+                if (status == -ENOMEM) {
+                        /* Put the queue to sleep until resources are
+                         * available
+                         */
+                        netif_stop_queue(netdev);
+                        status = NETDEV_TX_BUSY;
+                } else {
+                        status = NETDEV_TX_OK;
+                }
+        }
+        return status;
+}
+
+/**
+ * et131x_tx_timeout - Timeout handler
+ * @netdev: a pointer to a net_device struct representing the device
+ *
+ * The handler called when a Tx request times out. The timeout period is
+ * specified by the 'tx_timeo" element in the net_device structure (see
+ * et131x_alloc_device() to see how this value is set).
+ */
+void et131x_tx_timeout(struct net_device *netdev)
+{
+        struct et131x_adapter *etdev = netdev_priv(netdev);
+        struct tcb *tcb;
+        unsigned long flags;
+
+        /* Any nonrecoverable hardware error?
+         * Checks adapter->flags for any failure in phy reading
+         */
+        if (etdev->flags & fMP_ADAPTER_NON_RECOVER_ERROR)
+                return;
+
+        /* Hardware failure? */
+        if (etdev->flags & fMP_ADAPTER_HARDWARE_ERROR) {
+                dev_err(&etdev->pdev->dev, "hardware error - reset\n");
+                return;
+        }
+
+        /* Is send stuck? */
+        spin_lock_irqsave(&etdev->TCBSendQLock, flags);
+
+        tcb = etdev->tx_ring.send_head;
+
+        if (tcb != NULL) {
+                tcb->count++;
+
+                if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
+                        spin_unlock_irqrestore(&etdev->TCBSendQLock,
+                                               flags);
+
+                        dev_warn(&etdev->pdev->dev,
+                                "Send stuck - reset.  tcb->WrIndex %x, flags 0x%08x\n",
+                                tcb->index,
+                                tcb->flags);
+
+                        et131x_close(netdev);
+                        et131x_open(netdev);
+
+                        return;
+                }
+        }
+
+        spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
+}
+
+/**
+ * et131x_change_mtu - The handler called to change the MTU for the device
+ * @netdev: device whose MTU is to be changed
+ * @new_mtu: the desired MTU
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ */
+int et131x_change_mtu(struct net_device *netdev, int new_mtu)
+{
+        int result = 0;
+        struct et131x_adapter *adapter = netdev_priv(netdev);
+
+        /* Make sure the requested MTU is valid */
+        if (new_mtu < 64 || new_mtu > 9216)
+                return -EINVAL;
+
+        /* Stop the netif queue */
+        netif_stop_queue(netdev);
+
+        /* Stop the Tx and Rx DMA engines */
+        et131x_rx_dma_disable(adapter);
+        et131x_tx_dma_disable(adapter);
+
+        /* Disable device interrupts */
+        et131x_disable_interrupts(adapter);
+        et131x_handle_send_interrupt(adapter);
+        et131x_handle_recv_interrupt(adapter);
+
+        /* Set the new MTU */
+        netdev->mtu = new_mtu;
+
+        /* Free Rx DMA memory */
+        et131x_adapter_memory_free(adapter);
+
+        /* Set the config parameter for Jumbo Packet support */
+        adapter->RegistryJumboPacket = new_mtu + 14;
+        et131x_soft_reset(adapter);
+
+        /* Alloc and init Rx DMA memory */
+        result = et131x_adapter_memory_alloc(adapter);
+        if (result != 0) {
+                dev_warn(&adapter->pdev->dev,
+                        "Change MTU failed; couldn't re-alloc DMA memory\n");
+                return result;
+        }
+
+        et131x_init_send(adapter);
+
+        et131x_hwaddr_init(adapter);
+        memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
+
+        /* Init the device with the new settings */
+        et131x_adapter_setup(adapter);
+
+        /* Enable interrupts */
+        if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)
+                et131x_enable_interrupts(adapter);
+
+        /* Restart the Tx and Rx DMA engines */
+        et131x_rx_dma_enable(adapter);
+        et131x_tx_dma_enable(adapter);
+
+        /* Restart the netif queue */
+        netif_wake_queue(netdev);
+        return result;
+}
+
+/**
+ * et131x_set_mac_addr - handler to change the MAC address for the device
+ * @netdev: device whose MAC is to be changed
+ * @new_mac: the desired MAC address
+ *
+ * Returns 0 on success, errno on failure (as defined in errno.h)
+ *
+ * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
+ */
+int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
+{
+        int result = 0;
+        struct et131x_adapter *adapter = netdev_priv(netdev);
+        struct sockaddr *address = new_mac;
+
+        /* begin blux */
+
+        if (adapter == NULL)
+                return -ENODEV;
+
+        /* Make sure the requested MAC is valid */
+        if (!is_valid_ether_addr(address->sa_data))
+                return -EINVAL;
+
+        /* Stop the netif queue */
+        netif_stop_queue(netdev);
+
+        /* Stop the Tx and Rx DMA engines */
+        et131x_rx_dma_disable(adapter);
+        et131x_tx_dma_disable(adapter);
+
+        /* Disable device interrupts */
+        et131x_disable_interrupts(adapter);
+        et131x_handle_send_interrupt(adapter);
+        et131x_handle_recv_interrupt(adapter);
+
+        /* Set the new MAC */
+        /* netdev->set_mac_address  = &new_mac; */
+        /* netdev->mtu = new_mtu; */
+
+        memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
+
+        printk(KERN_INFO "%s: Setting MAC address to %pM\n",
+                        netdev->name, netdev->dev_addr);
+
+        /* Free Rx DMA memory */
+        et131x_adapter_memory_free(adapter);
+
+        /* Set the config parameter for Jumbo Packet support */
+        /* adapter->RegistryJumboPacket = new_mtu + 14; */
+        /* blux: not needet here, we'll change the MAC */
+
+        et131x_soft_reset(adapter);
+
+        /* Alloc and init Rx DMA memory */
+        result = et131x_adapter_memory_alloc(adapter);
+        if (result != 0) {
+                dev_err(&adapter->pdev->dev,
+                        "Change MAC failed; couldn't re-alloc DMA memory\n");
+                return result;
+        }
+
+        et131x_init_send(adapter);
+
+        et131x_hwaddr_init(adapter);
+
+        /* Init the device with the new settings */
+        et131x_adapter_setup(adapter);
+
+        /* Enable interrupts */
+        if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)
+                et131x_enable_interrupts(adapter);
+
+        /* Restart the Tx and Rx DMA engines */
+        et131x_rx_dma_enable(adapter);
+        et131x_tx_dma_enable(adapter);
+
+        /* Restart the netif queue */
+        netif_wake_queue(netdev);
+        return result;
+}
+
+static const struct net_device_ops et131x_netdev_ops = {
+        .ndo_open               = et131x_open,
+        .ndo_stop               = et131x_close,
+        .ndo_start_xmit         = et131x_tx,
+        .ndo_set_multicast_list = et131x_multicast,
+        .ndo_tx_timeout         = et131x_tx_timeout,
+        .ndo_change_mtu         = et131x_change_mtu,
+        .ndo_set_mac_address    = et131x_set_mac_addr,
+        .ndo_validate_addr      = eth_validate_addr,
+        .ndo_get_stats          = et131x_stats,
+        .ndo_do_ioctl           = et131x_ioctl,
+};
+
+/**
+ * et131x_device_alloc
+ *
+ * Returns pointer to the allocated and initialized net_device struct for
+ * this device.
+ *
+ * Create instances of net_device and wl_private for the new adapter and
+ * register the device's entry points in the net_device structure.
+ */
+struct net_device *et131x_device_alloc(void)
+{
+        struct net_device *netdev;
+
+        /* Alloc net_device and adapter structs */
+        netdev = alloc_etherdev(sizeof(struct et131x_adapter));
+
+        if (netdev == NULL) {
+                printk(KERN_ERR "et131x: Alloc of net_device struct failed\n");
+                return NULL;
+        }
+
+        /* Setup the function registration table (and other data) for a
+         * net_device
+         */
+        /* netdev->init               = &et131x_init; */
+        /* netdev->set_config = &et131x_config; */
+        netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
+        netdev->netdev_ops = &et131x_netdev_ops;
+
+        /* netdev->ethtool_ops        = &et131x_ethtool_ops; */
+
+        /* Poll? */
+        /* netdev->poll               = &et131x_poll; */
+        /* netdev->poll_controller    = &et131x_poll_controller; */
+        return netdev;
+}
+
diff --git a/drivers/staging/et131x/et131x_version.h b/drivers/staging/et131x/et131x_version.h
new file mode 100644
index 00000000000..2aa9bda44ac
--- /dev/null
+++ b/drivers/staging/et131x/et131x_version.h
@@ -0,0 +1,74 @@
+/*
+ * Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *   http://www.agere.com
+ *
+ *------------------------------------------------------------------------------
+ *
+ * et131x_version.h - This file provides system and device version information.
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software.  Using this
+ * software indicates your acceptance of these terms and conditions.  If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following Disclaimer as comments in the code as
+ *    well as in the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following Disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#ifndef __ET131X_VERSION_H__
+#define __ET131X_VERSION_H__
+
+#define DRIVER_AUTHOR           "Victor Soriano (vjsoriano@agere.com)"
+#define DRIVER_LICENSE          "Dual BSD/GPL"
+#define DRIVER_DEVICE_STRING    "ET1310"
+#define DRIVER_NAME             "et131x"
+#define DRIVER_VERSION_STRING   "1.2.3-lk"
+#define DRIVER_VENDOR           "Agere Systems, http://www.agere.com"
+#define DRIVER_DESC             "10/100/1000 Base-T Ethernet Driver"
+
+#define DRIVER_INFO             DRIVER_DESC " for the "\
+                                DRIVER_DEVICE_STRING ", v" \
+                                DRIVER_VERSION_STRING " by " \
+                                DRIVER_VENDOR
+
+#endif /* __ET131X_VERSION_H__ */