diff options
Diffstat (limited to 'drivers/staging/brcm80211')
81 files changed, 2256 insertions, 2261 deletions
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh.c index bbd03cd5695..8086b62c34b 100644 --- a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c +++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh.c | |||
@@ -390,7 +390,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size) | |||
390 | switch (size) { | 390 | switch (size) { |
391 | case sizeof(u8): | 391 | case sizeof(u8): |
392 | return word & 0xff; | 392 | return word & 0xff; |
393 | case sizeof(uint16): | 393 | case sizeof(u16): |
394 | return word & 0xffff; | 394 | return word & 0xffff; |
395 | case sizeof(uint32): | 395 | case sizeof(uint32): |
396 | return word; | 396 | return word; |
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c index 3e036b7c5a9..8e7be0d7a57 100644 --- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c +++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c | |||
@@ -81,7 +81,7 @@ static bcmsdh_driver_t drvinfo = { NULL, NULL }; | |||
81 | /** | 81 | /** |
82 | * Checks to see if vendor and device IDs match a supported SDIO Host Controller. | 82 | * Checks to see if vendor and device IDs match a supported SDIO Host Controller. |
83 | */ | 83 | */ |
84 | bool bcmsdh_chipmatch(uint16 vendor, uint16 device) | 84 | bool bcmsdh_chipmatch(u16 vendor, u16 device) |
85 | { | 85 | { |
86 | /* Add other vendors and devices as required */ | 86 | /* Add other vendors and devices as required */ |
87 | 87 | ||
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c index b013a65203c..c1b9ade3a0c 100644 --- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c +++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c | |||
@@ -479,7 +479,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, | |||
479 | case IOV_SVAL(IOV_BLOCKSIZE): | 479 | case IOV_SVAL(IOV_BLOCKSIZE): |
480 | { | 480 | { |
481 | uint func = ((uint32) int_val >> 16); | 481 | uint func = ((uint32) int_val >> 16); |
482 | uint blksize = (uint16) int_val; | 482 | uint blksize = (u16) int_val; |
483 | uint maxsize; | 483 | uint maxsize; |
484 | 484 | ||
485 | if (func > si->num_funcs) { | 485 | if (func > si->num_funcs) { |
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmutils.c b/drivers/staging/brcm80211/brcmfmac/bcmutils.c index 7185943a3b4..3eff4fe1739 100644 --- a/drivers/staging/brcm80211/brcmfmac/bcmutils.c +++ b/drivers/staging/brcm80211/brcmfmac/bcmutils.c | |||
@@ -307,9 +307,9 @@ void pktq_init(struct pktq *pq, int num_prec, int max_len) | |||
307 | bzero(pq, | 307 | bzero(pq, |
308 | OFFSETOF(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec)); | 308 | OFFSETOF(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec)); |
309 | 309 | ||
310 | pq->num_prec = (uint16) num_prec; | 310 | pq->num_prec = (u16) num_prec; |
311 | 311 | ||
312 | pq->max = (uint16) max_len; | 312 | pq->max = (u16) max_len; |
313 | 313 | ||
314 | for (prec = 0; prec < num_prec; prec++) | 314 | for (prec = 0; prec < num_prec; prec++) |
315 | pq->q[prec].max = pq->max; | 315 | pq->q[prec].max = pq->max; |
@@ -883,12 +883,12 @@ uint pktsetprio(void *pkt, bool update_vtag) | |||
883 | int rc = 0; | 883 | int rc = 0; |
884 | 884 | ||
885 | pktdata = (u8 *) PKTDATA(pkt); | 885 | pktdata = (u8 *) PKTDATA(pkt); |
886 | ASSERT(ISALIGNED((uintptr) pktdata, sizeof(uint16))); | 886 | ASSERT(ISALIGNED((uintptr) pktdata, sizeof(u16))); |
887 | 887 | ||
888 | eh = (struct ether_header *)pktdata; | 888 | eh = (struct ether_header *)pktdata; |
889 | 889 | ||
890 | if (ntoh16(eh->ether_type) == ETHER_TYPE_8021Q) { | 890 | if (ntoh16(eh->ether_type) == ETHER_TYPE_8021Q) { |
891 | uint16 vlan_tag; | 891 | u16 vlan_tag; |
892 | int vlan_prio, dscp_prio = 0; | 892 | int vlan_prio, dscp_prio = 0; |
893 | 893 | ||
894 | evh = (struct ethervlan_header *)eh; | 894 | evh = (struct ethervlan_header *)eh; |
@@ -920,7 +920,7 @@ uint pktsetprio(void *pkt, bool update_vtag) | |||
920 | */ | 920 | */ |
921 | if (update_vtag && (priority != vlan_prio)) { | 921 | if (update_vtag && (priority != vlan_prio)) { |
922 | vlan_tag &= ~(VLAN_PRI_MASK << VLAN_PRI_SHIFT); | 922 | vlan_tag &= ~(VLAN_PRI_MASK << VLAN_PRI_SHIFT); |
923 | vlan_tag |= (uint16) priority << VLAN_PRI_SHIFT; | 923 | vlan_tag |= (u16) priority << VLAN_PRI_SHIFT; |
924 | evh->vlan_tag = hton16(vlan_tag); | 924 | evh->vlan_tag = hton16(vlan_tag); |
925 | rc |= PKTPRIO_UPD; | 925 | rc |= PKTPRIO_UPD; |
926 | } | 926 | } |
@@ -1124,7 +1124,7 @@ u8 hndcrc8(u8 *pdata, /* pointer to array of data to process */ | |||
1124 | * **************************************************************************** | 1124 | * **************************************************************************** |
1125 | */ | 1125 | */ |
1126 | 1126 | ||
1127 | static const uint16 crc16_table[256] = { | 1127 | static const u16 crc16_table[256] = { |
1128 | 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF, | 1128 | 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF, |
1129 | 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7, | 1129 | 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7, |
1130 | 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E, | 1130 | 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E, |
@@ -1159,9 +1159,9 @@ static const uint16 crc16_table[256] = { | |||
1159 | 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78 | 1159 | 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78 |
1160 | }; | 1160 | }; |
1161 | 1161 | ||
1162 | uint16 hndcrc16(u8 *pdata, /* pointer to array of data to process */ | 1162 | u16 hndcrc16(u8 *pdata, /* pointer to array of data to process */ |
1163 | uint nbytes, /* number of input data bytes to process */ | 1163 | uint nbytes, /* number of input data bytes to process */ |
1164 | uint16 crc /* either CRC16_INIT_VALUE or previous | 1164 | u16 crc /* either CRC16_INIT_VALUE or previous |
1165 | return value */ | 1165 | return value */ |
1166 | ) | 1166 | ) |
1167 | { | 1167 | { |
@@ -1586,7 +1586,7 @@ uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen) | |||
1586 | /* Quarter dBm units to mW | 1586 | /* Quarter dBm units to mW |
1587 | * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153 | 1587 | * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153 |
1588 | * Table is offset so the last entry is largest mW value that fits in | 1588 | * Table is offset so the last entry is largest mW value that fits in |
1589 | * a uint16. | 1589 | * a u16. |
1590 | */ | 1590 | */ |
1591 | 1591 | ||
1592 | #define QDBM_OFFSET 153 /* Offset for first entry */ | 1592 | #define QDBM_OFFSET 153 /* Offset for first entry */ |
@@ -1604,7 +1604,7 @@ uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen) | |||
1604 | */ | 1604 | */ |
1605 | #define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */ | 1605 | #define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */ |
1606 | 1606 | ||
1607 | static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = { | 1607 | static const u16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = { |
1608 | /* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */ | 1608 | /* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */ |
1609 | /* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000, | 1609 | /* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000, |
1610 | /* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849, | 1610 | /* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849, |
@@ -1613,13 +1613,13 @@ static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = { | |||
1613 | /* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096 | 1613 | /* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096 |
1614 | }; | 1614 | }; |
1615 | 1615 | ||
1616 | uint16 bcm_qdbm_to_mw(u8 qdbm) | 1616 | u16 bcm_qdbm_to_mw(u8 qdbm) |
1617 | { | 1617 | { |
1618 | uint factor = 1; | 1618 | uint factor = 1; |
1619 | int idx = qdbm - QDBM_OFFSET; | 1619 | int idx = qdbm - QDBM_OFFSET; |
1620 | 1620 | ||
1621 | if (idx >= QDBM_TABLE_LEN) { | 1621 | if (idx >= QDBM_TABLE_LEN) { |
1622 | /* clamp to max uint16 mW value */ | 1622 | /* clamp to max u16 mW value */ |
1623 | return 0xFFFF; | 1623 | return 0xFFFF; |
1624 | } | 1624 | } |
1625 | 1625 | ||
@@ -1637,7 +1637,7 @@ uint16 bcm_qdbm_to_mw(u8 qdbm) | |||
1637 | return (nqdBm_to_mW_map[idx] + factor / 2) / factor; | 1637 | return (nqdBm_to_mW_map[idx] + factor / 2) / factor; |
1638 | } | 1638 | } |
1639 | 1639 | ||
1640 | u8 bcm_mw_to_qdbm(uint16 mw) | 1640 | u8 bcm_mw_to_qdbm(u16 mw) |
1641 | { | 1641 | { |
1642 | u8 qdbm; | 1642 | u8 qdbm; |
1643 | int offset; | 1643 | int offset; |
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c b/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c index fad3e7225a5..492138f4eb6 100644 --- a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c +++ b/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c | |||
@@ -52,7 +52,7 @@ extern int dhd_preinit_ioctls(dhd_pub_t *dhd); | |||
52 | */ | 52 | */ |
53 | 53 | ||
54 | typedef struct dhd_prot { | 54 | typedef struct dhd_prot { |
55 | uint16 reqid; | 55 | u16 reqid; |
56 | u8 pending; | 56 | u8 pending; |
57 | uint32 lastcmd; | 57 | uint32 lastcmd; |
58 | u8 bus_header[BUS_HEADER_LEN]; | 58 | u8 bus_header[BUS_HEADER_LEN]; |
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_common.c b/drivers/staging/brcm80211/brcmfmac/dhd_common.c index 27c69762c05..90879975dee 100644 --- a/drivers/staging/brcm80211/brcmfmac/dhd_common.c +++ b/drivers/staging/brcm80211/brcmfmac/dhd_common.c | |||
@@ -836,7 +836,7 @@ wl_host_event(struct dhd_info *dhd, int *ifidx, void *pktdata, | |||
836 | bcm_event_t *pvt_data = (bcm_event_t *) pktdata; | 836 | bcm_event_t *pvt_data = (bcm_event_t *) pktdata; |
837 | char *event_data; | 837 | char *event_data; |
838 | uint32 type, status; | 838 | uint32 type, status; |
839 | uint16 flags; | 839 | u16 flags; |
840 | int evlen; | 840 | int evlen; |
841 | 841 | ||
842 | if (bcmp(BRCM_OUI, &pvt_data->bcm_hdr.oui[0], DOT11_OUI_LEN)) { | 842 | if (bcmp(BRCM_OUI, &pvt_data->bcm_hdr.oui[0], DOT11_OUI_LEN)) { |
@@ -1674,7 +1674,7 @@ void dhd_iscan_ind_scan_confirm(void *dhdp, bool status) | |||
1674 | dhd_ind_scan_confirm(dhdp, status); | 1674 | dhd_ind_scan_confirm(dhdp, status); |
1675 | } | 1675 | } |
1676 | 1676 | ||
1677 | int dhd_iscan_request(void *dhdp, uint16 action) | 1677 | int dhd_iscan_request(void *dhdp, u16 action) |
1678 | { | 1678 | { |
1679 | int rc; | 1679 | int rc; |
1680 | wl_iscan_params_t params; | 1680 | wl_iscan_params_t params; |
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c b/drivers/staging/brcm80211/brcmfmac/dhd_linux.c index 75f472411cd..72eed5bac2f 100644 --- a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c +++ b/drivers/staging/brcm80211/brcmfmac/dhd_linux.c | |||
@@ -1249,7 +1249,7 @@ void dhd_txcomplete(dhd_pub_t *dhdp, void *txp, bool success) | |||
1249 | uint ifidx; | 1249 | uint ifidx; |
1250 | dhd_info_t *dhd = (dhd_info_t *) (dhdp->info); | 1250 | dhd_info_t *dhd = (dhd_info_t *) (dhdp->info); |
1251 | struct ether_header *eh; | 1251 | struct ether_header *eh; |
1252 | uint16 type; | 1252 | u16 type; |
1253 | 1253 | ||
1254 | dhd_prot_hdrpull(dhdp, &ifidx, txp); | 1254 | dhd_prot_hdrpull(dhdp, &ifidx, txp); |
1255 | 1255 | ||
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c index 60b499a597f..fb5e4b6a75a 100644 --- a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c +++ b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c | |||
@@ -182,7 +182,7 @@ typedef struct dhd_bus { | |||
182 | bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ | 182 | bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ |
183 | bool fcstate; /* State of dongle flow-control */ | 183 | bool fcstate; /* State of dongle flow-control */ |
184 | 184 | ||
185 | uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */ | 185 | u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */ |
186 | char *fw_path; /* module_param: path to firmware image */ | 186 | char *fw_path; /* module_param: path to firmware image */ |
187 | char *nv_path; /* module_param: path to nvram vars file */ | 187 | char *nv_path; /* module_param: path to nvram vars file */ |
188 | const char *nvram_params; /* user specified nvram params. */ | 188 | const char *nvram_params; /* user specified nvram params. */ |
@@ -197,7 +197,7 @@ typedef struct dhd_bus { | |||
197 | 197 | ||
198 | u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN]; | 198 | u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN]; |
199 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ | 199 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ |
200 | uint16 nextlen; /* Next Read Len from last header */ | 200 | u16 nextlen; /* Next Read Len from last header */ |
201 | u8 rx_seq; /* Receive sequence number (expected) */ | 201 | u8 rx_seq; /* Receive sequence number (expected) */ |
202 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ | 202 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ |
203 | 203 | ||
@@ -271,7 +271,7 @@ typedef struct dhd_bus { | |||
271 | uint pktgen_sent; /* Number of test packets generated */ | 271 | uint pktgen_sent; /* Number of test packets generated */ |
272 | uint pktgen_rcvd; /* Number of test packets received */ | 272 | uint pktgen_rcvd; /* Number of test packets received */ |
273 | uint pktgen_fail; /* Number of failed send attempts */ | 273 | uint pktgen_fail; /* Number of failed send attempts */ |
274 | uint16 pktgen_len; /* Length of next packet to send */ | 274 | u16 pktgen_len; /* Length of next packet to send */ |
275 | #endif /* SDTEST */ | 275 | #endif /* SDTEST */ |
276 | 276 | ||
277 | /* Some additional counters */ | 277 | /* Some additional counters */ |
@@ -432,9 +432,9 @@ static int dhdsdio_download_state(dhd_bus_t *bus, bool enter); | |||
432 | static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh); | 432 | static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh); |
433 | static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh); | 433 | static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh); |
434 | static void dhdsdio_disconnect(void *ptr); | 434 | static void dhdsdio_disconnect(void *ptr); |
435 | static bool dhdsdio_chipmatch(uint16 chipid); | 435 | static bool dhdsdio_chipmatch(u16 chipid); |
436 | static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh, | 436 | static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh, |
437 | void *regsva, uint16 devid); | 437 | void *regsva, u16 devid); |
438 | static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh); | 438 | static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh); |
439 | static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh); | 439 | static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh); |
440 | static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh); | 440 | static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh); |
@@ -904,7 +904,7 @@ static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt) | |||
904 | int ret; | 904 | int ret; |
905 | osl_t *osh; | 905 | osl_t *osh; |
906 | u8 *frame; | 906 | u8 *frame; |
907 | uint16 len, pad = 0; | 907 | u16 len, pad = 0; |
908 | uint32 swheader; | 908 | uint32 swheader; |
909 | uint retries = 0; | 909 | uint retries = 0; |
910 | bcmsdh_info_t *sdh; | 910 | bcmsdh_info_t *sdh; |
@@ -960,9 +960,9 @@ static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt) | |||
960 | ASSERT(pad < DHD_SDALIGN); | 960 | ASSERT(pad < DHD_SDALIGN); |
961 | 961 | ||
962 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ | 962 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ |
963 | len = (uint16) PKTLEN(pkt); | 963 | len = (u16) PKTLEN(pkt); |
964 | *(uint16 *) frame = htol16(len); | 964 | *(u16 *) frame = htol16(len); |
965 | *(((uint16 *) frame) + 1) = htol16(~len); | 965 | *(((u16 *) frame) + 1) = htol16(~len); |
966 | 966 | ||
967 | /* Software tag: channel, sequence number, data offset */ | 967 | /* Software tag: channel, sequence number, data offset */ |
968 | swheader = | 968 | swheader = |
@@ -985,7 +985,7 @@ static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt) | |||
985 | 985 | ||
986 | /* Raise len to next SDIO block to eliminate tail command */ | 986 | /* Raise len to next SDIO block to eliminate tail command */ |
987 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | 987 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { |
988 | uint16 pad = bus->blocksize - (len % bus->blocksize); | 988 | u16 pad = bus->blocksize - (len % bus->blocksize); |
989 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | 989 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) |
990 | #ifdef NOTUSED | 990 | #ifdef NOTUSED |
991 | if (pad <= PKTTAILROOM(pkt)) | 991 | if (pad <= PKTTAILROOM(pkt)) |
@@ -1222,7 +1222,7 @@ static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes) | |||
1222 | int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen) | 1222 | int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen) |
1223 | { | 1223 | { |
1224 | u8 *frame; | 1224 | u8 *frame; |
1225 | uint16 len; | 1225 | u16 len; |
1226 | uint32 swheader; | 1226 | uint32 swheader; |
1227 | uint retries = 0; | 1227 | uint retries = 0; |
1228 | bcmsdh_info_t *sdh = bus->sdh; | 1228 | bcmsdh_info_t *sdh = bus->sdh; |
@@ -1254,7 +1254,7 @@ int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen) | |||
1254 | 1254 | ||
1255 | /* Round send length to next SDIO block */ | 1255 | /* Round send length to next SDIO block */ |
1256 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | 1256 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { |
1257 | uint16 pad = bus->blocksize - (len % bus->blocksize); | 1257 | u16 pad = bus->blocksize - (len % bus->blocksize); |
1258 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | 1258 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) |
1259 | len += pad; | 1259 | len += pad; |
1260 | } else if (len % DHD_SDALIGN) { | 1260 | } else if (len % DHD_SDALIGN) { |
@@ -1276,8 +1276,8 @@ int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen) | |||
1276 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | 1276 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); |
1277 | 1277 | ||
1278 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ | 1278 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ |
1279 | *(uint16 *) frame = htol16((uint16) msglen); | 1279 | *(u16 *) frame = htol16((u16) msglen); |
1280 | *(((uint16 *) frame) + 1) = htol16(~msglen); | 1280 | *(((u16 *) frame) + 1) = htol16(~msglen); |
1281 | 1281 | ||
1282 | /* Software tag: channel, sequence number, data offset */ | 1282 | /* Software tag: channel, sequence number, data offset */ |
1283 | swheader = | 1283 | swheader = |
@@ -3009,7 +3009,7 @@ static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx) | |||
3009 | bcmsdh_info_t *sdh = bus->sdh; | 3009 | bcmsdh_info_t *sdh = bus->sdh; |
3010 | sdpcmd_regs_t *regs = bus->regs; | 3010 | sdpcmd_regs_t *regs = bus->regs; |
3011 | uint retries = 0; | 3011 | uint retries = 0; |
3012 | uint16 lastrbc; | 3012 | u16 lastrbc; |
3013 | u8 hi, lo; | 3013 | u8 hi, lo; |
3014 | int err; | 3014 | int err; |
3015 | 3015 | ||
@@ -3173,10 +3173,10 @@ done: | |||
3173 | 3173 | ||
3174 | static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | 3174 | static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) |
3175 | { | 3175 | { |
3176 | uint16 dlen, totlen; | 3176 | u16 dlen, totlen; |
3177 | u8 *dptr, num = 0; | 3177 | u8 *dptr, num = 0; |
3178 | 3178 | ||
3179 | uint16 sublen, check; | 3179 | u16 sublen, check; |
3180 | void *pfirst, *plast, *pnext, *save_pfirst; | 3180 | void *pfirst, *plast, *pnext, *save_pfirst; |
3181 | osl_t *osh = bus->dhd->osh; | 3181 | osl_t *osh = bus->dhd->osh; |
3182 | 3182 | ||
@@ -3198,7 +3198,7 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3198 | dhd_os_sdlock_rxq(bus->dhd); | 3198 | dhd_os_sdlock_rxq(bus->dhd); |
3199 | 3199 | ||
3200 | pfirst = plast = pnext = NULL; | 3200 | pfirst = plast = pnext = NULL; |
3201 | dlen = (uint16) PKTLEN(bus->glomd); | 3201 | dlen = (u16) PKTLEN(bus->glomd); |
3202 | dptr = PKTDATA(bus->glomd); | 3202 | dptr = PKTDATA(bus->glomd); |
3203 | if (!dlen || (dlen & 1)) { | 3203 | if (!dlen || (dlen & 1)) { |
3204 | DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n", | 3204 | DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n", |
@@ -3209,8 +3209,8 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3209 | for (totlen = num = 0; dlen; num++) { | 3209 | for (totlen = num = 0; dlen; num++) { |
3210 | /* Get (and move past) next length */ | 3210 | /* Get (and move past) next length */ |
3211 | sublen = ltoh16_ua(dptr); | 3211 | sublen = ltoh16_ua(dptr); |
3212 | dlen -= sizeof(uint16); | 3212 | dlen -= sizeof(u16); |
3213 | dptr += sizeof(uint16); | 3213 | dptr += sizeof(u16); |
3214 | if ((sublen < SDPCM_HDRLEN) || | 3214 | if ((sublen < SDPCM_HDRLEN) || |
3215 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | 3215 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { |
3216 | DHD_ERROR(("%s: descriptor len %d bad: %d\n", | 3216 | DHD_ERROR(("%s: descriptor len %d bad: %d\n", |
@@ -3297,7 +3297,7 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3297 | } | 3297 | } |
3298 | 3298 | ||
3299 | pfirst = bus->glom; | 3299 | pfirst = bus->glom; |
3300 | dlen = (uint16) pkttotlen(osh, pfirst); | 3300 | dlen = (u16) pkttotlen(osh, pfirst); |
3301 | 3301 | ||
3302 | /* Do an SDIO read for the superframe. Configurable iovar to | 3302 | /* Do an SDIO read for the superframe. Configurable iovar to |
3303 | * read directly into the chained packet, or allocate a large | 3303 | * read directly into the chained packet, or allocate a large |
@@ -3317,7 +3317,7 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3317 | F2SYNC, bus->dataptr, | 3317 | F2SYNC, bus->dataptr, |
3318 | dlen, NULL, NULL, NULL); | 3318 | dlen, NULL, NULL, NULL); |
3319 | sublen = | 3319 | sublen = |
3320 | (uint16) pktfrombuf(osh, pfirst, 0, dlen, | 3320 | (u16) pktfrombuf(osh, pfirst, 0, dlen, |
3321 | bus->dataptr); | 3321 | bus->dataptr); |
3322 | if (sublen != dlen) { | 3322 | if (sublen != dlen) { |
3323 | DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n", | 3323 | DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n", |
@@ -3362,7 +3362,7 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3362 | /* Validate the superframe header */ | 3362 | /* Validate the superframe header */ |
3363 | dptr = (u8 *) PKTDATA(pfirst); | 3363 | dptr = (u8 *) PKTDATA(pfirst); |
3364 | sublen = ltoh16_ua(dptr); | 3364 | sublen = ltoh16_ua(dptr); |
3365 | check = ltoh16_ua(dptr + sizeof(uint16)); | 3365 | check = ltoh16_ua(dptr + sizeof(u16)); |
3366 | 3366 | ||
3367 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | 3367 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); |
3368 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); | 3368 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); |
@@ -3376,7 +3376,7 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3376 | txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | 3376 | txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); |
3377 | 3377 | ||
3378 | errcode = 0; | 3378 | errcode = 0; |
3379 | if ((uint16)~(sublen ^ check)) { | 3379 | if ((u16)~(sublen ^ check)) { |
3380 | DHD_ERROR(("%s (superframe): HW hdr error: len/check " | 3380 | DHD_ERROR(("%s (superframe): HW hdr error: len/check " |
3381 | "0x%04x/0x%04x\n", __func__, sublen, check)); | 3381 | "0x%04x/0x%04x\n", __func__, sublen, check)); |
3382 | errcode = -1; | 3382 | errcode = -1; |
@@ -3430,9 +3430,9 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3430 | for (num = 0, pnext = pfirst; pnext && !errcode; | 3430 | for (num = 0, pnext = pfirst; pnext && !errcode; |
3431 | num++, pnext = PKTNEXT(pnext)) { | 3431 | num++, pnext = PKTNEXT(pnext)) { |
3432 | dptr = (u8 *) PKTDATA(pnext); | 3432 | dptr = (u8 *) PKTDATA(pnext); |
3433 | dlen = (uint16) PKTLEN(pnext); | 3433 | dlen = (u16) PKTLEN(pnext); |
3434 | sublen = ltoh16_ua(dptr); | 3434 | sublen = ltoh16_ua(dptr); |
3435 | check = ltoh16_ua(dptr + sizeof(uint16)); | 3435 | check = ltoh16_ua(dptr + sizeof(u16)); |
3436 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | 3436 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); |
3437 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | 3437 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); |
3438 | #ifdef DHD_DEBUG | 3438 | #ifdef DHD_DEBUG |
@@ -3440,7 +3440,7 @@ static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq) | |||
3440 | prhex("subframe", dptr, 32); | 3440 | prhex("subframe", dptr, 32); |
3441 | #endif | 3441 | #endif |
3442 | 3442 | ||
3443 | if ((uint16)~(sublen ^ check)) { | 3443 | if ((u16)~(sublen ^ check)) { |
3444 | DHD_ERROR(("%s (subframe %d): HW hdr error: " | 3444 | DHD_ERROR(("%s (subframe %d): HW hdr error: " |
3445 | "len/check 0x%04x/0x%04x\n", | 3445 | "len/check 0x%04x/0x%04x\n", |
3446 | __func__, num, sublen, check)); | 3446 | __func__, num, sublen, check)); |
@@ -3582,14 +3582,14 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) | |||
3582 | osl_t *osh = bus->dhd->osh; | 3582 | osl_t *osh = bus->dhd->osh; |
3583 | bcmsdh_info_t *sdh = bus->sdh; | 3583 | bcmsdh_info_t *sdh = bus->sdh; |
3584 | 3584 | ||
3585 | uint16 len, check; /* Extracted hardware header fields */ | 3585 | u16 len, check; /* Extracted hardware header fields */ |
3586 | u8 chan, seq, doff; /* Extracted software header fields */ | 3586 | u8 chan, seq, doff; /* Extracted software header fields */ |
3587 | u8 fcbits; /* Extracted fcbits from software header */ | 3587 | u8 fcbits; /* Extracted fcbits from software header */ |
3588 | u8 delta; | 3588 | u8 delta; |
3589 | 3589 | ||
3590 | void *pkt; /* Packet for event or data frames */ | 3590 | void *pkt; /* Packet for event or data frames */ |
3591 | uint16 pad; /* Number of pad bytes to read */ | 3591 | u16 pad; /* Number of pad bytes to read */ |
3592 | uint16 rdlen; /* Total number of bytes to read */ | 3592 | u16 rdlen; /* Total number of bytes to read */ |
3593 | u8 rxseq; /* Next sequence number to expect */ | 3593 | u8 rxseq; /* Next sequence number to expect */ |
3594 | uint rxleft = 0; /* Remaining number of frames allowed */ | 3594 | uint rxleft = 0; /* Remaining number of frames allowed */ |
3595 | int sdret; /* Return code from bcmsdh calls */ | 3595 | int sdret; /* Return code from bcmsdh calls */ |
@@ -3637,7 +3637,7 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) | |||
3637 | 3637 | ||
3638 | /* Try doing single read if we can */ | 3638 | /* Try doing single read if we can */ |
3639 | if (dhd_readahead && bus->nextlen) { | 3639 | if (dhd_readahead && bus->nextlen) { |
3640 | uint16 nextlen = bus->nextlen; | 3640 | u16 nextlen = bus->nextlen; |
3641 | bus->nextlen = 0; | 3641 | bus->nextlen = 0; |
3642 | 3642 | ||
3643 | if (bus->bus == SPI_BUS) { | 3643 | if (bus->bus == SPI_BUS) { |
@@ -3768,7 +3768,7 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) | |||
3768 | 3768 | ||
3769 | /* Extract hardware header fields */ | 3769 | /* Extract hardware header fields */ |
3770 | len = ltoh16_ua(bus->rxhdr); | 3770 | len = ltoh16_ua(bus->rxhdr); |
3771 | check = ltoh16_ua(bus->rxhdr + sizeof(uint16)); | 3771 | check = ltoh16_ua(bus->rxhdr + sizeof(u16)); |
3772 | 3772 | ||
3773 | /* All zeros means readahead info was bad */ | 3773 | /* All zeros means readahead info was bad */ |
3774 | if (!(len | check)) { | 3774 | if (!(len | check)) { |
@@ -3782,7 +3782,7 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) | |||
3782 | } | 3782 | } |
3783 | 3783 | ||
3784 | /* Validate check bytes */ | 3784 | /* Validate check bytes */ |
3785 | if ((uint16)~(len ^ check)) { | 3785 | if ((u16)~(len ^ check)) { |
3786 | DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n", | 3786 | DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n", |
3787 | __func__, nextlen, len, check)); | 3787 | __func__, nextlen, len, check)); |
3788 | dhd_os_sdlock_rxq(bus->dhd); | 3788 | dhd_os_sdlock_rxq(bus->dhd); |
@@ -3960,7 +3960,7 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) | |||
3960 | 3960 | ||
3961 | /* Extract hardware header fields */ | 3961 | /* Extract hardware header fields */ |
3962 | len = ltoh16_ua(bus->rxhdr); | 3962 | len = ltoh16_ua(bus->rxhdr); |
3963 | check = ltoh16_ua(bus->rxhdr + sizeof(uint16)); | 3963 | check = ltoh16_ua(bus->rxhdr + sizeof(u16)); |
3964 | 3964 | ||
3965 | /* All zeros means no more frames */ | 3965 | /* All zeros means no more frames */ |
3966 | if (!(len | check)) { | 3966 | if (!(len | check)) { |
@@ -3969,7 +3969,7 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) | |||
3969 | } | 3969 | } |
3970 | 3970 | ||
3971 | /* Validate check bytes */ | 3971 | /* Validate check bytes */ |
3972 | if ((uint16) ~(len ^ check)) { | 3972 | if ((u16) ~(len ^ check)) { |
3973 | DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n", | 3973 | DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n", |
3974 | __func__, len, check)); | 3974 | __func__, len, check)); |
3975 | bus->rx_badhdr++; | 3975 | bus->rx_badhdr++; |
@@ -4611,7 +4611,7 @@ static void dhdsdio_pktgen_init(dhd_bus_t *bus) | |||
4611 | bus->pktgen_maxlen = MAX_PKTGEN_LEN; | 4611 | bus->pktgen_maxlen = MAX_PKTGEN_LEN; |
4612 | bus->pktgen_minlen = 0; | 4612 | bus->pktgen_minlen = 0; |
4613 | } | 4613 | } |
4614 | bus->pktgen_len = (uint16) bus->pktgen_minlen; | 4614 | bus->pktgen_len = (u16) bus->pktgen_minlen; |
4615 | 4615 | ||
4616 | /* Default to per-watchdog burst with 10s print time */ | 4616 | /* Default to per-watchdog burst with 10s print time */ |
4617 | bus->pktgen_freq = 1; | 4617 | bus->pktgen_freq = 1; |
@@ -4630,7 +4630,7 @@ static void dhdsdio_pktgen(dhd_bus_t *bus) | |||
4630 | uint pktcount; | 4630 | uint pktcount; |
4631 | uint fillbyte; | 4631 | uint fillbyte; |
4632 | osl_t *osh = bus->dhd->osh; | 4632 | osl_t *osh = bus->dhd->osh; |
4633 | uint16 len; | 4633 | u16 len; |
4634 | 4634 | ||
4635 | /* Display current count if appropriate */ | 4635 | /* Display current count if appropriate */ |
4636 | if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) { | 4636 | if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) { |
@@ -4722,7 +4722,7 @@ static void dhdsdio_pktgen(dhd_bus_t *bus) | |||
4722 | 4722 | ||
4723 | /* Bump length if not fixed, wrap at max */ | 4723 | /* Bump length if not fixed, wrap at max */ |
4724 | if (++bus->pktgen_len > bus->pktgen_maxlen) | 4724 | if (++bus->pktgen_len > bus->pktgen_maxlen) |
4725 | bus->pktgen_len = (uint16) bus->pktgen_minlen; | 4725 | bus->pktgen_len = (u16) bus->pktgen_minlen; |
4726 | 4726 | ||
4727 | /* Special case for burst mode: just send one request! */ | 4727 | /* Special case for burst mode: just send one request! */ |
4728 | if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) | 4728 | if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) |
@@ -4765,8 +4765,8 @@ static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq) | |||
4765 | 4765 | ||
4766 | u8 cmd; | 4766 | u8 cmd; |
4767 | u8 extra; | 4767 | u8 extra; |
4768 | uint16 len; | 4768 | u16 len; |
4769 | uint16 offset; | 4769 | u16 offset; |
4770 | 4770 | ||
4771 | /* Check for min length */ | 4771 | /* Check for min length */ |
4772 | pktlen = PKTLEN(pkt); | 4772 | pktlen = PKTLEN(pkt); |
@@ -5047,7 +5047,7 @@ static void dhd_dump_cis(uint fn, u8 *cis) | |||
5047 | } | 5047 | } |
5048 | #endif /* DHD_DEBUG */ | 5048 | #endif /* DHD_DEBUG */ |
5049 | 5049 | ||
5050 | static bool dhdsdio_chipmatch(uint16 chipid) | 5050 | static bool dhdsdio_chipmatch(u16 chipid) |
5051 | { | 5051 | { |
5052 | if (chipid == BCM4325_CHIP_ID) | 5052 | if (chipid == BCM4325_CHIP_ID) |
5053 | return TRUE; | 5053 | return TRUE; |
@@ -5058,8 +5058,8 @@ static bool dhdsdio_chipmatch(uint16 chipid) | |||
5058 | return FALSE; | 5058 | return FALSE; |
5059 | } | 5059 | } |
5060 | 5060 | ||
5061 | static void *dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no, | 5061 | static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no, |
5062 | uint16 slot, uint16 func, uint bustype, void *regsva, | 5062 | u16 slot, u16 func, uint bustype, void *regsva, |
5063 | osl_t *osh, void *sdh) | 5063 | osl_t *osh, void *sdh) |
5064 | { | 5064 | { |
5065 | int ret; | 5065 | int ret; |
@@ -5154,7 +5154,7 @@ static void *dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no, | |||
5154 | } | 5154 | } |
5155 | bzero(bus, sizeof(dhd_bus_t)); | 5155 | bzero(bus, sizeof(dhd_bus_t)); |
5156 | bus->sdh = sdh; | 5156 | bus->sdh = sdh; |
5157 | bus->cl_devid = (uint16) devid; | 5157 | bus->cl_devid = (u16) devid; |
5158 | bus->bus = DHD_BUS; | 5158 | bus->bus = DHD_BUS; |
5159 | bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1; | 5159 | bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1; |
5160 | bus->usebufpool = FALSE; /* Use bufpool if allocated, | 5160 | bus->usebufpool = FALSE; /* Use bufpool if allocated, |
@@ -5221,7 +5221,7 @@ fail: | |||
5221 | 5221 | ||
5222 | static bool | 5222 | static bool |
5223 | dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva, | 5223 | dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva, |
5224 | uint16 devid) | 5224 | u16 devid) |
5225 | { | 5225 | { |
5226 | u8 clkctl = 0; | 5226 | u8 clkctl = 0; |
5227 | int err = 0; | 5227 | int err = 0; |
@@ -5315,7 +5315,7 @@ dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva, | |||
5315 | 5315 | ||
5316 | bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev); | 5316 | bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev); |
5317 | 5317 | ||
5318 | if (!dhdsdio_chipmatch((uint16) bus->sih->chip)) { | 5318 | if (!dhdsdio_chipmatch((u16) bus->sih->chip)) { |
5319 | DHD_ERROR(("%s: unsupported chip: 0x%04x\n", | 5319 | DHD_ERROR(("%s: unsupported chip: 0x%04x\n", |
5320 | __func__, bus->sih->chip)); | 5320 | __func__, bus->sih->chip)); |
5321 | goto fail; | 5321 | goto fail; |
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c index b66730c6f85..1c3b0d88f90 100644 --- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c +++ b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c | |||
@@ -86,7 +86,7 @@ static int32 wl_cfg80211_set_bitrate_mask(struct wiphy *wiphy, | |||
86 | static int wl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev, | 86 | static int wl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev, |
87 | struct cfg80211_connect_params *sme); | 87 | struct cfg80211_connect_params *sme); |
88 | static int32 wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev, | 88 | static int32 wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev, |
89 | uint16 reason_code); | 89 | u16 reason_code); |
90 | static int32 wl_cfg80211_set_tx_power(struct wiphy *wiphy, | 90 | static int32 wl_cfg80211_set_tx_power(struct wiphy *wiphy, |
91 | enum nl80211_tx_power_setting type, | 91 | enum nl80211_tx_power_setting type, |
92 | int32 dbm); | 92 | int32 dbm); |
@@ -203,8 +203,8 @@ static int32 wl_get_assoc_ies(struct wl_priv *wl); | |||
203 | */ | 203 | */ |
204 | static void wl_rst_ie(struct wl_priv *wl); | 204 | static void wl_rst_ie(struct wl_priv *wl); |
205 | static int32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v); | 205 | static int32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v); |
206 | static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, uint16 ie_size); | 206 | static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size); |
207 | static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, uint16 dst_size); | 207 | static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size); |
208 | static uint32 wl_get_ielen(struct wl_priv *wl); | 208 | static uint32 wl_get_ielen(struct wl_priv *wl); |
209 | 209 | ||
210 | static int32 wl_mode_to_nl80211_iftype(int32 mode); | 210 | static int32 wl_mode_to_nl80211_iftype(int32 mode); |
@@ -298,7 +298,7 @@ static int32 wl_dev_iovar_getbuf(struct net_device *dev, s8 *iovar, | |||
298 | void *param, int32 paramlen, void *bufptr, | 298 | void *param, int32 paramlen, void *bufptr, |
299 | int32 buflen); | 299 | int32 buflen); |
300 | static int32 wl_run_iscan(struct wl_iscan_ctrl *iscan, struct wlc_ssid *ssid, | 300 | static int32 wl_run_iscan(struct wl_iscan_ctrl *iscan, struct wlc_ssid *ssid, |
301 | uint16 action); | 301 | u16 action); |
302 | static int32 wl_do_iscan(struct wl_priv *wl); | 302 | static int32 wl_do_iscan(struct wl_priv *wl); |
303 | static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan); | 303 | static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan); |
304 | static int32 wl_invoke_iscan(struct wl_priv *wl); | 304 | static int32 wl_invoke_iscan(struct wl_priv *wl); |
@@ -319,7 +319,7 @@ static void wl_init_fw(struct wl_fw_ctrl *fw); | |||
319 | /* | 319 | /* |
320 | * find most significant bit set | 320 | * find most significant bit set |
321 | */ | 321 | */ |
322 | static __used uint32 wl_find_msb(uint16 bit16); | 322 | static __used uint32 wl_find_msb(u16 bit16); |
323 | 323 | ||
324 | /* | 324 | /* |
325 | * update pmklist to dongle | 325 | * update pmklist to dongle |
@@ -686,7 +686,7 @@ wl_dev_iovar_getbuf(struct net_device *dev, s8 * iovar, void *param, | |||
686 | } | 686 | } |
687 | 687 | ||
688 | static int32 | 688 | static int32 |
689 | wl_run_iscan(struct wl_iscan_ctrl *iscan, struct wlc_ssid *ssid, uint16 action) | 689 | wl_run_iscan(struct wl_iscan_ctrl *iscan, struct wlc_ssid *ssid, u16 action) |
690 | { | 690 | { |
691 | int32 params_size = | 691 | int32 params_size = |
692 | (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_iscan_params_t, params)); | 692 | (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_iscan_params_t, params)); |
@@ -1380,7 +1380,7 @@ wl_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev, | |||
1380 | 1380 | ||
1381 | static int32 | 1381 | static int32 |
1382 | wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev, | 1382 | wl_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev, |
1383 | uint16 reason_code) | 1383 | u16 reason_code) |
1384 | { | 1384 | { |
1385 | struct wl_priv *wl = wiphy_to_wl(wiphy); | 1385 | struct wl_priv *wl = wiphy_to_wl(wiphy); |
1386 | scb_val_t scbval; | 1386 | scb_val_t scbval; |
@@ -1412,7 +1412,7 @@ wl_cfg80211_set_tx_power(struct wiphy *wiphy, | |||
1412 | 1412 | ||
1413 | struct wl_priv *wl = wiphy_to_wl(wiphy); | 1413 | struct wl_priv *wl = wiphy_to_wl(wiphy); |
1414 | struct net_device *ndev = wl_to_ndev(wl); | 1414 | struct net_device *ndev = wl_to_ndev(wl); |
1415 | uint16 txpwrmw; | 1415 | u16 txpwrmw; |
1416 | int32 err = 0; | 1416 | int32 err = 0; |
1417 | int32 disable = 0; | 1417 | int32 disable = 0; |
1418 | 1418 | ||
@@ -1445,7 +1445,7 @@ wl_cfg80211_set_tx_power(struct wiphy *wiphy, | |||
1445 | if (dbm > 0xffff) | 1445 | if (dbm > 0xffff) |
1446 | txpwrmw = 0xffff; | 1446 | txpwrmw = 0xffff; |
1447 | else | 1447 | else |
1448 | txpwrmw = (uint16) dbm; | 1448 | txpwrmw = (u16) dbm; |
1449 | err = wl_dev_intvar_set(ndev, "qtxpower", | 1449 | err = wl_dev_intvar_set(ndev, "qtxpower", |
1450 | (int32) (bcm_mw_to_qdbm(txpwrmw))); | 1450 | (int32) (bcm_mw_to_qdbm(txpwrmw))); |
1451 | if (unlikely(err)) { | 1451 | if (unlikely(err)) { |
@@ -1867,7 +1867,7 @@ wl_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev, | |||
1867 | return err; | 1867 | return err; |
1868 | } | 1868 | } |
1869 | 1869 | ||
1870 | static __used uint32 wl_find_msb(uint16 bit16) | 1870 | static __used uint32 wl_find_msb(u16 bit16) |
1871 | { | 1871 | { |
1872 | uint32 ret = 0; | 1872 | uint32 ret = 0; |
1873 | 1873 | ||
@@ -2317,7 +2317,7 @@ static int32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi) | |||
2317 | static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e) | 2317 | static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e) |
2318 | { | 2318 | { |
2319 | uint32 event = ntoh32(e->event_type); | 2319 | uint32 event = ntoh32(e->event_type); |
2320 | uint16 flags = ntoh16(e->flags); | 2320 | u16 flags = ntoh16(e->flags); |
2321 | 2321 | ||
2322 | if (event == WLC_E_JOIN || event == WLC_E_ASSOC_IND | 2322 | if (event == WLC_E_JOIN || event == WLC_E_ASSOC_IND |
2323 | || event == WLC_E_REASSOC_IND) { | 2323 | || event == WLC_E_REASSOC_IND) { |
@@ -2339,7 +2339,7 @@ static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e) | |||
2339 | static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e) | 2339 | static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e) |
2340 | { | 2340 | { |
2341 | uint32 event = ntoh32(e->event_type); | 2341 | uint32 event = ntoh32(e->event_type); |
2342 | uint16 flags = ntoh16(e->flags); | 2342 | u16 flags = ntoh16(e->flags); |
2343 | 2343 | ||
2344 | if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) { | 2344 | if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) { |
2345 | return TRUE; | 2345 | return TRUE; |
@@ -2602,7 +2602,7 @@ static int32 | |||
2602 | wl_notify_mic_status(struct wl_priv *wl, struct net_device *ndev, | 2602 | wl_notify_mic_status(struct wl_priv *wl, struct net_device *ndev, |
2603 | const wl_event_msg_t *e, void *data) | 2603 | const wl_event_msg_t *e, void *data) |
2604 | { | 2604 | { |
2605 | uint16 flags = ntoh16(e->flags); | 2605 | u16 flags = ntoh16(e->flags); |
2606 | enum nl80211_key_type key_type; | 2606 | enum nl80211_key_type key_type; |
2607 | 2607 | ||
2608 | rtnl_lock(); | 2608 | rtnl_lock(); |
@@ -3897,7 +3897,7 @@ static int32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v) | |||
3897 | return err; | 3897 | return err; |
3898 | } | 3898 | } |
3899 | 3899 | ||
3900 | static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, uint16 ie_size) | 3900 | static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size) |
3901 | { | 3901 | { |
3902 | struct wl_ie *ie = wl_to_ie(wl); | 3902 | struct wl_ie *ie = wl_to_ie(wl); |
3903 | int32 err = 0; | 3903 | int32 err = 0; |
@@ -3912,7 +3912,7 @@ static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, uint16 ie_size) | |||
3912 | return err; | 3912 | return err; |
3913 | } | 3913 | } |
3914 | 3914 | ||
3915 | static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, uint16 dst_size) | 3915 | static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size) |
3916 | { | 3916 | { |
3917 | struct wl_ie *ie = wl_to_ie(wl); | 3917 | struct wl_ie *ie = wl_to_ie(wl); |
3918 | int32 err = 0; | 3918 | int32 err = 0; |
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h index ef9b88e154c..518895c015c 100644 --- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h +++ b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h | |||
@@ -180,10 +180,10 @@ struct wl_dev { | |||
180 | 180 | ||
181 | /* bss inform structure for cfg80211 interface */ | 181 | /* bss inform structure for cfg80211 interface */ |
182 | struct wl_cfg80211_bss_info { | 182 | struct wl_cfg80211_bss_info { |
183 | uint16 band; | 183 | u16 band; |
184 | uint16 channel; | 184 | u16 channel; |
185 | int16 rssi; | 185 | int16 rssi; |
186 | uint16 frame_len; | 186 | u16 frame_len; |
187 | u8 frame_buf[1]; | 187 | u8 frame_buf[1]; |
188 | }; | 188 | }; |
189 | 189 | ||
@@ -194,7 +194,7 @@ struct wl_scan_req { | |||
194 | 194 | ||
195 | /* basic structure of information element */ | 195 | /* basic structure of information element */ |
196 | struct wl_ie { | 196 | struct wl_ie { |
197 | uint16 offset; | 197 | u16 offset; |
198 | u8 buf[WL_TLV_INFO_MAX]; | 198 | u8 buf[WL_TLV_INFO_MAX]; |
199 | }; | 199 | }; |
200 | 200 | ||
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_iw.c b/drivers/staging/brcm80211/brcmfmac/wl_iw.c index c105b7fe80f..5306368ecd5 100644 --- a/drivers/staging/brcm80211/brcmfmac/wl_iw.c +++ b/drivers/staging/brcm80211/brcmfmac/wl_iw.c | |||
@@ -148,7 +148,7 @@ typedef struct iscan_info { | |||
148 | iscan_info_t *g_iscan; | 148 | iscan_info_t *g_iscan; |
149 | static void wl_iw_timerfunc(unsigned long data); | 149 | static void wl_iw_timerfunc(unsigned long data); |
150 | static void wl_iw_set_event_mask(struct net_device *dev); | 150 | static void wl_iw_set_event_mask(struct net_device *dev); |
151 | static int wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, uint16 action); | 151 | static int wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, u16 action); |
152 | #endif /* defined(WL_IW_USE_ISCAN) */ | 152 | #endif /* defined(WL_IW_USE_ISCAN) */ |
153 | 153 | ||
154 | static int | 154 | static int |
@@ -503,7 +503,7 @@ wl_iw_get_range(struct net_device *dev, | |||
503 | int bw_cap = 0, sgi_tx = 0, nmode = 0; | 503 | int bw_cap = 0, sgi_tx = 0, nmode = 0; |
504 | channel_info_t ci; | 504 | channel_info_t ci; |
505 | u8 nrate_list2copy = 0; | 505 | u8 nrate_list2copy = 0; |
506 | uint16 nrate_list[4][8] = { {13, 26, 39, 52, 78, 104, 117, 130}, | 506 | u16 nrate_list[4][8] = { {13, 26, 39, 52, 78, 104, 117, 130}, |
507 | {14, 29, 43, 58, 87, 116, 130, 144}, | 507 | {14, 29, 43, 58, 87, 116, 130, 144}, |
508 | {27, 54, 81, 108, 162, 216, 243, 270}, | 508 | {27, 54, 81, 108, 162, 216, 243, 270}, |
509 | {30, 60, 90, 120, 180, 240, 270, 300} | 509 | {30, 60, 90, 120, 180, 240, 270, 300} |
@@ -1048,7 +1048,7 @@ static int wl_iw_iscan_prep(wl_scan_params_t *params, wlc_ssid_t *ssid) | |||
1048 | return err; | 1048 | return err; |
1049 | } | 1049 | } |
1050 | 1050 | ||
1051 | static int wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, uint16 action) | 1051 | static int wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, u16 action) |
1052 | { | 1052 | { |
1053 | int err = 0; | 1053 | int err = 0; |
1054 | 1054 | ||
@@ -2172,7 +2172,7 @@ wl_iw_set_txpow(struct net_device *dev, | |||
2172 | struct iw_param *vwrq, char *extra) | 2172 | struct iw_param *vwrq, char *extra) |
2173 | { | 2173 | { |
2174 | int error, disable; | 2174 | int error, disable; |
2175 | uint16 txpwrmw; | 2175 | u16 txpwrmw; |
2176 | WL_TRACE(("%s: SIOCSIWTXPOW\n", dev->name)); | 2176 | WL_TRACE(("%s: SIOCSIWTXPOW\n", dev->name)); |
2177 | 2177 | ||
2178 | disable = vwrq->disabled ? WL_RADIO_SW_DISABLE : 0; | 2178 | disable = vwrq->disabled ? WL_RADIO_SW_DISABLE : 0; |
@@ -2195,7 +2195,7 @@ wl_iw_set_txpow(struct net_device *dev, | |||
2195 | if (vwrq->value > 0xffff) | 2195 | if (vwrq->value > 0xffff) |
2196 | txpwrmw = 0xffff; | 2196 | txpwrmw = 0xffff; |
2197 | else | 2197 | else |
2198 | txpwrmw = (uint16) vwrq->value; | 2198 | txpwrmw = (u16) vwrq->value; |
2199 | 2199 | ||
2200 | error = | 2200 | error = |
2201 | dev_wlc_intvar_set(dev, "qtxpower", (int)(bcm_mw_to_qdbm(txpwrmw))); | 2201 | dev_wlc_intvar_set(dev, "qtxpower", (int)(bcm_mw_to_qdbm(txpwrmw))); |
@@ -3402,7 +3402,7 @@ void wl_iw_event(struct net_device *dev, wl_event_msg_t *e, void *data) | |||
3402 | char extra[IW_CUSTOM_MAX + 1]; | 3402 | char extra[IW_CUSTOM_MAX + 1]; |
3403 | int cmd = 0; | 3403 | int cmd = 0; |
3404 | uint32 event_type = ntoh32(e->event_type); | 3404 | uint32 event_type = ntoh32(e->event_type); |
3405 | uint16 flags = ntoh16(e->flags); | 3405 | u16 flags = ntoh16(e->flags); |
3406 | uint32 datalen = ntoh32(e->datalen); | 3406 | uint32 datalen = ntoh32(e->datalen); |
3407 | uint32 status = ntoh32(e->status); | 3407 | uint32 status = ntoh32(e->status); |
3408 | wl_iw_t *iw; | 3408 | wl_iw_t *iw; |
@@ -3709,7 +3709,7 @@ int wl_iw_attach(struct net_device *dev, void *dhdp) | |||
3709 | #ifdef CSCAN | 3709 | #ifdef CSCAN |
3710 | params_size = | 3710 | params_size = |
3711 | (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_iscan_params_t, params)) + | 3711 | (WL_SCAN_PARAMS_FIXED_SIZE + OFFSETOF(wl_iscan_params_t, params)) + |
3712 | (WL_NUMCHANNELS * sizeof(uint16)) + | 3712 | (WL_NUMCHANNELS * sizeof(u16)) + |
3713 | WL_SCAN_PARAMS_SSID_MAX * sizeof(wlc_ssid_t); | 3713 | WL_SCAN_PARAMS_SSID_MAX * sizeof(wlc_ssid_t); |
3714 | #else | 3714 | #else |
3715 | params_size = | 3715 | params_size = |
diff --git a/drivers/staging/brcm80211/include/bcm_rpc.h b/drivers/staging/brcm80211/include/bcm_rpc.h index eb989ee5eca..8aa864dcc9c 100644 --- a/drivers/staging/brcm80211/include/bcm_rpc.h +++ b/drivers/staging/brcm80211/include/bcm_rpc.h | |||
@@ -74,7 +74,7 @@ extern int bcm_rpc_dump(rpc_info_t *rpci, struct bcmstrbuf *b); | |||
74 | #define RPC_TRACE_VAL 0x0002 | 74 | #define RPC_TRACE_VAL 0x0002 |
75 | #define RPC_PKTTRACE_VAL 0x0004 | 75 | #define RPC_PKTTRACE_VAL 0x0004 |
76 | #define RPC_PKTLOG_VAL 0x0008 | 76 | #define RPC_PKTLOG_VAL 0x0008 |
77 | extern void bcm_rpc_msglevel_set(struct rpc_info *rpci, uint16 msglevel, | 77 | extern void bcm_rpc_msglevel_set(struct rpc_info *rpci, u16 msglevel, |
78 | bool high_low); | 78 | bool high_low); |
79 | 79 | ||
80 | #endif /* _BCM_RPC_H_ */ | 80 | #endif /* _BCM_RPC_H_ */ |
diff --git a/drivers/staging/brcm80211/include/bcm_rpc_tp.h b/drivers/staging/brcm80211/include/bcm_rpc_tp.h index 66350e5f24b..c0cc425d18d 100644 --- a/drivers/staging/brcm80211/include/bcm_rpc_tp.h +++ b/drivers/staging/brcm80211/include/bcm_rpc_tp.h | |||
@@ -114,9 +114,9 @@ extern void bcm_rpc_tp_txq_wm_get(rpc_tp_info_t *rpc_th, u8 *hiwm, | |||
114 | 114 | ||
115 | extern void bcm_rpc_tp_agg_set(rpc_tp_info_t *rpcb, uint32 reason, bool set); | 115 | extern void bcm_rpc_tp_agg_set(rpc_tp_info_t *rpcb, uint32 reason, bool set); |
116 | extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t *rpc_th, u8 sf, | 116 | extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t *rpc_th, u8 sf, |
117 | uint16 bytes); | 117 | u16 bytes); |
118 | extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t *rpc_th, u8 *sf, | 118 | extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t *rpc_th, u8 *sf, |
119 | uint16 *bytes); | 119 | u16 *bytes); |
120 | 120 | ||
121 | #define BCM_RPC_TP_MSG_LEVEL_MASK 0x00ff | 121 | #define BCM_RPC_TP_MSG_LEVEL_MASK 0x00ff |
122 | /* dongle msg level */ | 122 | /* dongle msg level */ |
diff --git a/drivers/staging/brcm80211/include/bcm_xdr.h b/drivers/staging/brcm80211/include/bcm_xdr.h index e392826aa38..749cb198fe0 100644 --- a/drivers/staging/brcm80211/include/bcm_xdr.h +++ b/drivers/staging/brcm80211/include/bcm_xdr.h | |||
@@ -49,8 +49,8 @@ int bcm_xdr_unpack_string(bcm_xdr_buf_t *b, uint *plen, char **pstr); | |||
49 | 49 | ||
50 | int bcm_xdr_pack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); | 50 | int bcm_xdr_pack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); |
51 | int bcm_xdr_unpack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); | 51 | int bcm_xdr_unpack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); |
52 | int bcm_xdr_pack_uint16_vec(bcm_xdr_buf_t *b, uint len, void *vec); | 52 | int bcm_xdr_pack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec); |
53 | int bcm_xdr_unpack_uint16_vec(bcm_xdr_buf_t *b, uint len, void *vec); | 53 | int bcm_xdr_unpack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec); |
54 | int bcm_xdr_pack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); | 54 | int bcm_xdr_pack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); |
55 | int bcm_xdr_unpack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); | 55 | int bcm_xdr_unpack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); |
56 | 56 | ||
diff --git a/drivers/staging/brcm80211/include/bcmendian.h b/drivers/staging/brcm80211/include/bcmendian.h index cad2720f99b..6a9ca37664f 100644 --- a/drivers/staging/brcm80211/include/bcmendian.h +++ b/drivers/staging/brcm80211/include/bcmendian.h | |||
@@ -21,8 +21,8 @@ | |||
21 | 21 | ||
22 | /* Reverse the bytes in a 16-bit value */ | 22 | /* Reverse the bytes in a 16-bit value */ |
23 | #define BCMSWAP16(val) \ | 23 | #define BCMSWAP16(val) \ |
24 | ((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \ | 24 | ((u16)((((u16)(val) & (u16)0x00ffU) << 8) | \ |
25 | (((uint16)(val) & (uint16)0xff00U) >> 8))) | 25 | (((u16)(val) & (u16)0xff00U) >> 8))) |
26 | 26 | ||
27 | /* Reverse the bytes in a 32-bit value */ | 27 | /* Reverse the bytes in a 32-bit value */ |
28 | #define BCMSWAP32(val) \ | 28 | #define BCMSWAP32(val) \ |
@@ -82,8 +82,8 @@ | |||
82 | #define ltoh16_buf(buf, i) | 82 | #define ltoh16_buf(buf, i) |
83 | #define htol16_buf(buf, i) | 83 | #define htol16_buf(buf, i) |
84 | #else | 84 | #else |
85 | #define ltoh16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i)) | 85 | #define ltoh16_buf(buf, i) bcmswap16_buf((u16 *)(buf), (i)) |
86 | #define htol16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i)) | 86 | #define htol16_buf(buf, i) bcmswap16_buf((u16 *)(buf), (i)) |
87 | #endif /* IL_BIGENDIAN */ | 87 | #endif /* IL_BIGENDIAN */ |
88 | 88 | ||
89 | /* Unaligned loads and stores in host byte order */ | 89 | /* Unaligned loads and stores in host byte order */ |
@@ -106,13 +106,13 @@ | |||
106 | 106 | ||
107 | #define ltoh_ua(ptr) \ | 107 | #define ltoh_ua(ptr) \ |
108 | (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ | 108 | (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ |
109 | sizeof(*(ptr)) == sizeof(uint16) ? _LTOH16_UA((const u8 *)(ptr)) : \ | 109 | sizeof(*(ptr)) == sizeof(u16) ? _LTOH16_UA((const u8 *)(ptr)) : \ |
110 | sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const u8 *)(ptr)) : \ | 110 | sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const u8 *)(ptr)) : \ |
111 | *(u8 *)0) | 111 | *(u8 *)0) |
112 | 112 | ||
113 | #define ntoh_ua(ptr) \ | 113 | #define ntoh_ua(ptr) \ |
114 | (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ | 114 | (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ |
115 | sizeof(*(ptr)) == sizeof(uint16) ? _NTOH16_UA((const u8 *)(ptr)) : \ | 115 | sizeof(*(ptr)) == sizeof(u16) ? _NTOH16_UA((const u8 *)(ptr)) : \ |
116 | sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const u8 *)(ptr)) : \ | 116 | sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const u8 *)(ptr)) : \ |
117 | *(u8 *)0) | 117 | *(u8 *)0) |
118 | 118 | ||
@@ -123,7 +123,7 @@ | |||
123 | */ | 123 | */ |
124 | 124 | ||
125 | #define bcmswap16(val) ({ \ | 125 | #define bcmswap16(val) ({ \ |
126 | uint16 _val = (val); \ | 126 | u16 _val = (val); \ |
127 | BCMSWAP16(_val); \ | 127 | BCMSWAP16(_val); \ |
128 | }) | 128 | }) |
129 | 129 | ||
@@ -138,7 +138,7 @@ | |||
138 | }) | 138 | }) |
139 | 139 | ||
140 | #define bcmswap16_buf(buf, len) ({ \ | 140 | #define bcmswap16_buf(buf, len) ({ \ |
141 | uint16 *_buf = (uint16 *)(buf); \ | 141 | u16 *_buf = (u16 *)(buf); \ |
142 | uint _wds = (len) / 2; \ | 142 | uint _wds = (len) / 2; \ |
143 | while (_wds--) { \ | 143 | while (_wds--) { \ |
144 | *_buf = bcmswap16(*_buf); \ | 144 | *_buf = bcmswap16(*_buf); \ |
@@ -147,7 +147,7 @@ | |||
147 | }) | 147 | }) |
148 | 148 | ||
149 | #define htol16_ua_store(val, bytes) ({ \ | 149 | #define htol16_ua_store(val, bytes) ({ \ |
150 | uint16 _val = (val); \ | 150 | u16 _val = (val); \ |
151 | u8 *_bytes = (u8 *)(bytes); \ | 151 | u8 *_bytes = (u8 *)(bytes); \ |
152 | _bytes[0] = _val & 0xff; \ | 152 | _bytes[0] = _val & 0xff; \ |
153 | _bytes[1] = _val >> 8; \ | 153 | _bytes[1] = _val >> 8; \ |
@@ -163,7 +163,7 @@ | |||
163 | }) | 163 | }) |
164 | 164 | ||
165 | #define hton16_ua_store(val, bytes) ({ \ | 165 | #define hton16_ua_store(val, bytes) ({ \ |
166 | uint16 _val = (val); \ | 166 | u16 _val = (val); \ |
167 | u8 *_bytes = (u8 *)(bytes); \ | 167 | u8 *_bytes = (u8 *)(bytes); \ |
168 | _bytes[0] = _val >> 8; \ | 168 | _bytes[0] = _val >> 8; \ |
169 | _bytes[1] = _val & 0xff; \ | 169 | _bytes[1] = _val & 0xff; \ |
@@ -201,7 +201,7 @@ | |||
201 | #else /* !__GNUC__ */ | 201 | #else /* !__GNUC__ */ |
202 | 202 | ||
203 | /* Inline versions avoid referencing the argument multiple times */ | 203 | /* Inline versions avoid referencing the argument multiple times */ |
204 | static inline uint16 bcmswap16(uint16 val) | 204 | static inline u16 bcmswap16(u16 val) |
205 | { | 205 | { |
206 | return BCMSWAP16(val); | 206 | return BCMSWAP16(val); |
207 | } | 207 | } |
@@ -219,7 +219,7 @@ static inline uint32 bcmswap32by16(uint32 val) | |||
219 | /* Reverse pairs of bytes in a buffer (not for high-performance use) */ | 219 | /* Reverse pairs of bytes in a buffer (not for high-performance use) */ |
220 | /* buf - start of buffer of shorts to swap */ | 220 | /* buf - start of buffer of shorts to swap */ |
221 | /* len - byte length of buffer */ | 221 | /* len - byte length of buffer */ |
222 | static inline void bcmswap16_buf(uint16 *buf, uint len) | 222 | static inline void bcmswap16_buf(u16 *buf, uint len) |
223 | { | 223 | { |
224 | len = len / 2; | 224 | len = len / 2; |
225 | 225 | ||
@@ -232,7 +232,7 @@ static inline void bcmswap16_buf(uint16 *buf, uint len) | |||
232 | /* | 232 | /* |
233 | * Store 16-bit value to unaligned little-endian byte array. | 233 | * Store 16-bit value to unaligned little-endian byte array. |
234 | */ | 234 | */ |
235 | static inline void htol16_ua_store(uint16 val, u8 *bytes) | 235 | static inline void htol16_ua_store(u16 val, u8 *bytes) |
236 | { | 236 | { |
237 | bytes[0] = val & 0xff; | 237 | bytes[0] = val & 0xff; |
238 | bytes[1] = val >> 8; | 238 | bytes[1] = val >> 8; |
@@ -252,7 +252,7 @@ static inline void htol32_ua_store(uint32 val, u8 *bytes) | |||
252 | /* | 252 | /* |
253 | * Store 16-bit value to unaligned network-(big-)endian byte array. | 253 | * Store 16-bit value to unaligned network-(big-)endian byte array. |
254 | */ | 254 | */ |
255 | static inline void hton16_ua_store(uint16 val, u8 *bytes) | 255 | static inline void hton16_ua_store(u16 val, u8 *bytes) |
256 | { | 256 | { |
257 | bytes[0] = val >> 8; | 257 | bytes[0] = val >> 8; |
258 | bytes[1] = val & 0xff; | 258 | bytes[1] = val & 0xff; |
@@ -272,7 +272,7 @@ static inline void hton32_ua_store(uint32 val, u8 *bytes) | |||
272 | /* | 272 | /* |
273 | * Load 16-bit value from unaligned little-endian byte array. | 273 | * Load 16-bit value from unaligned little-endian byte array. |
274 | */ | 274 | */ |
275 | static inline uint16 ltoh16_ua(const void *bytes) | 275 | static inline u16 ltoh16_ua(const void *bytes) |
276 | { | 276 | { |
277 | return _LTOH16_UA((const u8 *)bytes); | 277 | return _LTOH16_UA((const u8 *)bytes); |
278 | } | 278 | } |
@@ -288,7 +288,7 @@ static inline uint32 ltoh32_ua(const void *bytes) | |||
288 | /* | 288 | /* |
289 | * Load 16-bit value from unaligned big-(network-)endian byte array. | 289 | * Load 16-bit value from unaligned big-(network-)endian byte array. |
290 | */ | 290 | */ |
291 | static inline uint16 ntoh16_ua(const void *bytes) | 291 | static inline u16 ntoh16_ua(const void *bytes) |
292 | { | 292 | { |
293 | return _NTOH16_UA((const u8 *)bytes); | 293 | return _NTOH16_UA((const u8 *)bytes); |
294 | } | 294 | } |
diff --git a/drivers/staging/brcm80211/include/bcmotp.h b/drivers/staging/brcm80211/include/bcmotp.h index e011261fdff..5803accaa47 100644 --- a/drivers/staging/brcm80211/include/bcmotp.h +++ b/drivers/staging/brcm80211/include/bcmotp.h | |||
@@ -36,9 +36,9 @@ | |||
36 | /* Exported functions */ | 36 | /* Exported functions */ |
37 | extern int otp_status(void *oh); | 37 | extern int otp_status(void *oh); |
38 | extern int otp_size(void *oh); | 38 | extern int otp_size(void *oh); |
39 | extern uint16 otp_read_bit(void *oh, uint offset); | 39 | extern u16 otp_read_bit(void *oh, uint offset); |
40 | extern void *otp_init(si_t *sih); | 40 | extern void *otp_init(si_t *sih); |
41 | extern int otp_read_region(si_t *sih, int region, uint16 *data, uint *wlen); | 41 | extern int otp_read_region(si_t *sih, int region, u16 *data, uint *wlen); |
42 | extern int otp_nvread(void *oh, char *data, uint *len); | 42 | extern int otp_nvread(void *oh, char *data, uint *len); |
43 | 43 | ||
44 | #endif /* _bcmotp_h_ */ | 44 | #endif /* _bcmotp_h_ */ |
diff --git a/drivers/staging/brcm80211/include/bcmsdh.h b/drivers/staging/brcm80211/include/bcmsdh.h index 52ecb467e8c..a43f9cd0888 100644 --- a/drivers/staging/brcm80211/include/bcmsdh.h +++ b/drivers/staging/brcm80211/include/bcmsdh.h | |||
@@ -173,8 +173,8 @@ extern void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh); | |||
173 | /* callback functions */ | 173 | /* callback functions */ |
174 | typedef struct { | 174 | typedef struct { |
175 | /* attach to device */ | 175 | /* attach to device */ |
176 | void *(*attach) (uint16 vend_id, uint16 dev_id, uint16 bus, uint16 slot, | 176 | void *(*attach) (u16 vend_id, u16 dev_id, u16 bus, u16 slot, |
177 | uint16 func, uint bustype, void *regsva, osl_t *osh, | 177 | u16 func, uint bustype, void *regsva, osl_t *osh, |
178 | void *param); | 178 | void *param); |
179 | /* detach from device */ | 179 | /* detach from device */ |
180 | void (*detach) (void *ch); | 180 | void (*detach) (void *ch); |
@@ -183,7 +183,7 @@ typedef struct { | |||
183 | /* platform specific/high level functions */ | 183 | /* platform specific/high level functions */ |
184 | extern int bcmsdh_register(bcmsdh_driver_t *driver); | 184 | extern int bcmsdh_register(bcmsdh_driver_t *driver); |
185 | extern void bcmsdh_unregister(void); | 185 | extern void bcmsdh_unregister(void); |
186 | extern bool bcmsdh_chipmatch(uint16 vendor, uint16 device); | 186 | extern bool bcmsdh_chipmatch(u16 vendor, u16 device); |
187 | extern void bcmsdh_device_remove(void *sdh); | 187 | extern void bcmsdh_device_remove(void *sdh); |
188 | 188 | ||
189 | /* Function to pass device-status bits to DHD. */ | 189 | /* Function to pass device-status bits to DHD. */ |
diff --git a/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h b/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h index f6302c1c71b..7f237004e6a 100644 --- a/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h +++ b/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h | |||
@@ -56,7 +56,7 @@ struct sdioh_info { | |||
56 | bool intr_handler_valid; /* client driver interrupt handler valid */ | 56 | bool intr_handler_valid; /* client driver interrupt handler valid */ |
57 | sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ | 57 | sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ |
58 | void *intr_handler_arg; /* argument to call interrupt handler */ | 58 | void *intr_handler_arg; /* argument to call interrupt handler */ |
59 | uint16 intmask; /* Current active interrupts */ | 59 | u16 intmask; /* Current active interrupts */ |
60 | void *sdos_info; /* Pointer to per-OS private data */ | 60 | void *sdos_info; /* Pointer to per-OS private data */ |
61 | 61 | ||
62 | uint irq; /* Client irq */ | 62 | uint irq; /* Client irq */ |
diff --git a/drivers/staging/brcm80211/include/bcmsrom.h b/drivers/staging/brcm80211/include/bcmsrom.h index 4e3a509e339..9d53657fdaa 100644 --- a/drivers/staging/brcm80211/include/bcmsrom.h +++ b/drivers/staging/brcm80211/include/bcmsrom.h | |||
@@ -24,7 +24,7 @@ extern int srom_var_init(si_t *sih, uint bus, void *curmap, osl_t *osh, | |||
24 | char **vars, uint *count); | 24 | char **vars, uint *count); |
25 | 25 | ||
26 | extern int srom_read(si_t *sih, uint bus, void *curmap, osl_t *osh, | 26 | extern int srom_read(si_t *sih, uint bus, void *curmap, osl_t *osh, |
27 | uint byteoff, uint nbytes, uint16 *buf, bool check_crc); | 27 | uint byteoff, uint nbytes, u16 *buf, bool check_crc); |
28 | 28 | ||
29 | /* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP | 29 | /* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP |
30 | * and extract from it into name=value pairs | 30 | * and extract from it into name=value pairs |
diff --git a/drivers/staging/brcm80211/include/bcmsrom_tbl.h b/drivers/staging/brcm80211/include/bcmsrom_tbl.h index bf1406127a6..eea3085bc01 100644 --- a/drivers/staging/brcm80211/include/bcmsrom_tbl.h +++ b/drivers/staging/brcm80211/include/bcmsrom_tbl.h | |||
@@ -24,8 +24,8 @@ typedef struct { | |||
24 | const char *name; | 24 | const char *name; |
25 | uint32 revmask; | 25 | uint32 revmask; |
26 | uint32 flags; | 26 | uint32 flags; |
27 | uint16 off; | 27 | u16 off; |
28 | uint16 mask; | 28 | u16 mask; |
29 | } sromvar_t; | 29 | } sromvar_t; |
30 | 30 | ||
31 | #define SRFL_MORE 1 /* value continues as described by the next entry */ | 31 | #define SRFL_MORE 1 /* value continues as described by the next entry */ |
@@ -447,9 +447,9 @@ static const sromvar_t perpath_pci_sromvars[] = { | |||
447 | #endif /* !defined(PHY_TYPE_NULL) */ | 447 | #endif /* !defined(PHY_TYPE_NULL) */ |
448 | 448 | ||
449 | typedef struct { | 449 | typedef struct { |
450 | uint16 phy_type; | 450 | u16 phy_type; |
451 | uint16 bandrange; | 451 | u16 bandrange; |
452 | uint16 chain; | 452 | u16 chain; |
453 | const char *vars; | 453 | const char *vars; |
454 | } pavars_t; | 454 | } pavars_t; |
455 | 455 | ||
@@ -476,8 +476,8 @@ static const pavars_t pavars[] = { | |||
476 | }; | 476 | }; |
477 | 477 | ||
478 | typedef struct { | 478 | typedef struct { |
479 | uint16 phy_type; | 479 | u16 phy_type; |
480 | uint16 bandrange; | 480 | u16 bandrange; |
481 | const char *vars; | 481 | const char *vars; |
482 | } povars_t; | 482 | } povars_t; |
483 | 483 | ||
diff --git a/drivers/staging/brcm80211/include/bcmutils.h b/drivers/staging/brcm80211/include/bcmutils.h index 7dd92109985..652d34c705e 100644 --- a/drivers/staging/brcm80211/include/bcmutils.h +++ b/drivers/staging/brcm80211/include/bcmutils.h | |||
@@ -92,26 +92,26 @@ extern "C" { | |||
92 | typedef struct pktq_prec { | 92 | typedef struct pktq_prec { |
93 | void *head; /* first packet to dequeue */ | 93 | void *head; /* first packet to dequeue */ |
94 | void *tail; /* last packet to dequeue */ | 94 | void *tail; /* last packet to dequeue */ |
95 | uint16 len; /* number of queued packets */ | 95 | u16 len; /* number of queued packets */ |
96 | uint16 max; /* maximum number of queued packets */ | 96 | u16 max; /* maximum number of queued packets */ |
97 | } pktq_prec_t; | 97 | } pktq_prec_t; |
98 | 98 | ||
99 | /* multi-priority pkt queue */ | 99 | /* multi-priority pkt queue */ |
100 | struct pktq { | 100 | struct pktq { |
101 | uint16 num_prec; /* number of precedences in use */ | 101 | u16 num_prec; /* number of precedences in use */ |
102 | uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ | 102 | u16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ |
103 | uint16 max; /* total max packets */ | 103 | u16 max; /* total max packets */ |
104 | uint16 len; /* total number of packets */ | 104 | u16 len; /* total number of packets */ |
105 | /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ | 105 | /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ |
106 | struct pktq_prec q[PKTQ_MAX_PREC]; | 106 | struct pktq_prec q[PKTQ_MAX_PREC]; |
107 | }; | 107 | }; |
108 | 108 | ||
109 | /* simple, non-priority pkt queue */ | 109 | /* simple, non-priority pkt queue */ |
110 | struct spktq { | 110 | struct spktq { |
111 | uint16 num_prec; /* number of precedences in use (always 1) */ | 111 | u16 num_prec; /* number of precedences in use (always 1) */ |
112 | uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ | 112 | u16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ |
113 | uint16 max; /* total max packets */ | 113 | u16 max; /* total max packets */ |
114 | uint16 len; /* total number of packets */ | 114 | u16 len; /* total number of packets */ |
115 | /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ | 115 | /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ |
116 | struct pktq_prec q[1]; | 116 | struct pktq_prec q[1]; |
117 | }; | 117 | }; |
@@ -273,10 +273,10 @@ extern "C" { | |||
273 | /* iovar structure */ | 273 | /* iovar structure */ |
274 | typedef struct bcm_iovar { | 274 | typedef struct bcm_iovar { |
275 | const char *name; /* name for lookup and display */ | 275 | const char *name; /* name for lookup and display */ |
276 | uint16 varid; /* id for switch */ | 276 | u16 varid; /* id for switch */ |
277 | uint16 flags; /* driver-specific flag bits */ | 277 | u16 flags; /* driver-specific flag bits */ |
278 | uint16 type; /* base type of argument */ | 278 | u16 type; /* base type of argument */ |
279 | uint16 minlen; /* min length for buffer vars */ | 279 | u16 minlen; /* min length for buffer vars */ |
280 | } bcm_iovar_t; | 280 | } bcm_iovar_t; |
281 | 281 | ||
282 | /* varid definitions are per-driver, may use these get/set bits */ | 282 | /* varid definitions are per-driver, may use these get/set bits */ |
@@ -325,7 +325,7 @@ extern "C" { | |||
325 | "s8", \ | 325 | "s8", \ |
326 | "u8", \ | 326 | "u8", \ |
327 | "int16", \ | 327 | "int16", \ |
328 | "uint16", \ | 328 | "u16", \ |
329 | "int32", \ | 329 | "int32", \ |
330 | "uint32", \ | 330 | "uint32", \ |
331 | "buffer", \ | 331 | "buffer", \ |
@@ -569,7 +569,7 @@ extern "C" { | |||
569 | /* externs */ | 569 | /* externs */ |
570 | /* crc */ | 570 | /* crc */ |
571 | extern u8 BCMROMFN(hndcrc8) (u8 *p, uint nbytes, u8 crc); | 571 | extern u8 BCMROMFN(hndcrc8) (u8 *p, uint nbytes, u8 crc); |
572 | extern uint16 BCMROMFN(hndcrc16) (u8 *p, uint nbytes, uint16 crc); | 572 | extern u16 BCMROMFN(hndcrc16) (u8 *p, uint nbytes, u16 crc); |
573 | /* format/print */ | 573 | /* format/print */ |
574 | #if defined(BCMDBG) | 574 | #if defined(BCMDBG) |
575 | extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, | 575 | extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, |
@@ -612,8 +612,8 @@ extern "C" { | |||
612 | 612 | ||
613 | #ifdef BRCM_FULLMAC | 613 | #ifdef BRCM_FULLMAC |
614 | /* power conversion */ | 614 | /* power conversion */ |
615 | extern uint16 BCMROMFN(bcm_qdbm_to_mw) (u8 qdbm); | 615 | extern u16 BCMROMFN(bcm_qdbm_to_mw) (u8 qdbm); |
616 | extern u8 BCMROMFN(bcm_mw_to_qdbm) (uint16 mw); | 616 | extern u8 BCMROMFN(bcm_mw_to_qdbm) (u16 mw); |
617 | #endif | 617 | #endif |
618 | 618 | ||
619 | /* generic datastruct to help dump routines */ | 619 | /* generic datastruct to help dump routines */ |
diff --git a/drivers/staging/brcm80211/include/bcmwifi.h b/drivers/staging/brcm80211/include/bcmwifi.h index 848d3844aa0..b85fea31f46 100644 --- a/drivers/staging/brcm80211/include/bcmwifi.h +++ b/drivers/staging/brcm80211/include/bcmwifi.h | |||
@@ -18,7 +18,7 @@ | |||
18 | #define _bcmwifi_h_ | 18 | #define _bcmwifi_h_ |
19 | 19 | ||
20 | /* A chanspec holds the channel number, band, bandwidth and control sideband */ | 20 | /* A chanspec holds the channel number, band, bandwidth and control sideband */ |
21 | typedef uint16 chanspec_t; | 21 | typedef u16 chanspec_t; |
22 | 22 | ||
23 | /* channel defines */ | 23 | /* channel defines */ |
24 | #define CH_UPPER_SB 0x01 | 24 | #define CH_UPPER_SB 0x01 |
diff --git a/drivers/staging/brcm80211/include/d11.h b/drivers/staging/brcm80211/include/d11.h index 3c4304c8454..b2f2afc151b 100644 --- a/drivers/staging/brcm80211/include/d11.h +++ b/drivers/staging/brcm80211/include/d11.h | |||
@@ -75,8 +75,8 @@ typedef volatile struct { | |||
75 | typedef volatile union { | 75 | typedef volatile union { |
76 | uint32 pmqhostdata; /* read only! */ | 76 | uint32 pmqhostdata; /* read only! */ |
77 | struct { | 77 | struct { |
78 | uint16 pmqctrlstatus; /* read/write */ | 78 | u16 pmqctrlstatus; /* read/write */ |
79 | uint16 PAD; | 79 | u16 PAD; |
80 | } w; | 80 | } w; |
81 | } pmqreg_t; | 81 | } pmqreg_t; |
82 | 82 | ||
@@ -188,250 +188,250 @@ typedef volatile struct _d11regs { | |||
188 | uint32 aggfifocnt; /* 0x390 */ | 188 | uint32 aggfifocnt; /* 0x390 */ |
189 | uint32 aggfifodata; /* 0x394 */ | 189 | uint32 aggfifodata; /* 0x394 */ |
190 | uint32 PAD[16]; /* 0x398 - 0x3d4 */ | 190 | uint32 PAD[16]; /* 0x398 - 0x3d4 */ |
191 | uint16 radioregaddr; /* 0x3d8 */ | 191 | u16 radioregaddr; /* 0x3d8 */ |
192 | uint16 radioregdata; /* 0x3da */ | 192 | u16 radioregdata; /* 0x3da */ |
193 | 193 | ||
194 | /* time delay between the change on rf disable input and radio shutdown corerev 10 */ | 194 | /* time delay between the change on rf disable input and radio shutdown corerev 10 */ |
195 | uint32 rfdisabledly; /* 0x3DC */ | 195 | uint32 rfdisabledly; /* 0x3DC */ |
196 | 196 | ||
197 | /* PHY register access */ | 197 | /* PHY register access */ |
198 | uint16 phyversion; /* 0x3e0 - 0x0 */ | 198 | u16 phyversion; /* 0x3e0 - 0x0 */ |
199 | uint16 phybbconfig; /* 0x3e2 - 0x1 */ | 199 | u16 phybbconfig; /* 0x3e2 - 0x1 */ |
200 | uint16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */ | 200 | u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */ |
201 | uint16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */ | 201 | u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */ |
202 | uint16 phyrxstatus0; /* 0x3e8 - 0x4 */ | 202 | u16 phyrxstatus0; /* 0x3e8 - 0x4 */ |
203 | uint16 phyrxstatus1; /* 0x3ea - 0x5 */ | 203 | u16 phyrxstatus1; /* 0x3ea - 0x5 */ |
204 | uint16 phycrsth; /* 0x3ec - 0x6 */ | 204 | u16 phycrsth; /* 0x3ec - 0x6 */ |
205 | uint16 phytxerror; /* 0x3ee - 0x7 */ | 205 | u16 phytxerror; /* 0x3ee - 0x7 */ |
206 | uint16 phychannel; /* 0x3f0 - 0x8 */ | 206 | u16 phychannel; /* 0x3f0 - 0x8 */ |
207 | uint16 PAD[1]; /* 0x3f2 - 0x9 */ | 207 | u16 PAD[1]; /* 0x3f2 - 0x9 */ |
208 | uint16 phytest; /* 0x3f4 - 0xa */ | 208 | u16 phytest; /* 0x3f4 - 0xa */ |
209 | uint16 phy4waddr; /* 0x3f6 - 0xb */ | 209 | u16 phy4waddr; /* 0x3f6 - 0xb */ |
210 | uint16 phy4wdatahi; /* 0x3f8 - 0xc */ | 210 | u16 phy4wdatahi; /* 0x3f8 - 0xc */ |
211 | uint16 phy4wdatalo; /* 0x3fa - 0xd */ | 211 | u16 phy4wdatalo; /* 0x3fa - 0xd */ |
212 | uint16 phyregaddr; /* 0x3fc - 0xe */ | 212 | u16 phyregaddr; /* 0x3fc - 0xe */ |
213 | uint16 phyregdata; /* 0x3fe - 0xf */ | 213 | u16 phyregdata; /* 0x3fe - 0xf */ |
214 | 214 | ||
215 | /* IHR *//* 0x400 - 0x7FE */ | 215 | /* IHR *//* 0x400 - 0x7FE */ |
216 | 216 | ||
217 | /* RXE Block */ | 217 | /* RXE Block */ |
218 | uint16 PAD[3]; /* 0x400 - 0x406 */ | 218 | u16 PAD[3]; /* 0x400 - 0x406 */ |
219 | uint16 rcv_fifo_ctl; /* 0x406 */ | 219 | u16 rcv_fifo_ctl; /* 0x406 */ |
220 | uint16 PAD; /* 0x408 - 0x40a */ | 220 | u16 PAD; /* 0x408 - 0x40a */ |
221 | uint16 rcv_frm_cnt; /* 0x40a */ | 221 | u16 rcv_frm_cnt; /* 0x40a */ |
222 | uint16 PAD[4]; /* 0x40a - 0x414 */ | 222 | u16 PAD[4]; /* 0x40a - 0x414 */ |
223 | uint16 rssi; /* 0x414 */ | 223 | u16 rssi; /* 0x414 */ |
224 | uint16 PAD[5]; /* 0x414 - 0x420 */ | 224 | u16 PAD[5]; /* 0x414 - 0x420 */ |
225 | uint16 rcm_ctl; /* 0x420 */ | 225 | u16 rcm_ctl; /* 0x420 */ |
226 | uint16 rcm_mat_data; /* 0x422 */ | 226 | u16 rcm_mat_data; /* 0x422 */ |
227 | uint16 rcm_mat_mask; /* 0x424 */ | 227 | u16 rcm_mat_mask; /* 0x424 */ |
228 | uint16 rcm_mat_dly; /* 0x426 */ | 228 | u16 rcm_mat_dly; /* 0x426 */ |
229 | uint16 rcm_cond_mask_l; /* 0x428 */ | 229 | u16 rcm_cond_mask_l; /* 0x428 */ |
230 | uint16 rcm_cond_mask_h; /* 0x42A */ | 230 | u16 rcm_cond_mask_h; /* 0x42A */ |
231 | uint16 rcm_cond_dly; /* 0x42C */ | 231 | u16 rcm_cond_dly; /* 0x42C */ |
232 | uint16 PAD[1]; /* 0x42E */ | 232 | u16 PAD[1]; /* 0x42E */ |
233 | uint16 ext_ihr_addr; /* 0x430 */ | 233 | u16 ext_ihr_addr; /* 0x430 */ |
234 | uint16 ext_ihr_data; /* 0x432 */ | 234 | u16 ext_ihr_data; /* 0x432 */ |
235 | uint16 rxe_phyrs_2; /* 0x434 */ | 235 | u16 rxe_phyrs_2; /* 0x434 */ |
236 | uint16 rxe_phyrs_3; /* 0x436 */ | 236 | u16 rxe_phyrs_3; /* 0x436 */ |
237 | uint16 phy_mode; /* 0x438 */ | 237 | u16 phy_mode; /* 0x438 */ |
238 | uint16 rcmta_ctl; /* 0x43a */ | 238 | u16 rcmta_ctl; /* 0x43a */ |
239 | uint16 rcmta_size; /* 0x43c */ | 239 | u16 rcmta_size; /* 0x43c */ |
240 | uint16 rcmta_addr0; /* 0x43e */ | 240 | u16 rcmta_addr0; /* 0x43e */ |
241 | uint16 rcmta_addr1; /* 0x440 */ | 241 | u16 rcmta_addr1; /* 0x440 */ |
242 | uint16 rcmta_addr2; /* 0x442 */ | 242 | u16 rcmta_addr2; /* 0x442 */ |
243 | uint16 PAD[30]; /* 0x444 - 0x480 */ | 243 | u16 PAD[30]; /* 0x444 - 0x480 */ |
244 | 244 | ||
245 | /* PSM Block *//* 0x480 - 0x500 */ | 245 | /* PSM Block *//* 0x480 - 0x500 */ |
246 | 246 | ||
247 | uint16 PAD; /* 0x480 */ | 247 | u16 PAD; /* 0x480 */ |
248 | uint16 psm_maccontrol_h; /* 0x482 */ | 248 | u16 psm_maccontrol_h; /* 0x482 */ |
249 | uint16 psm_macintstatus_l; /* 0x484 */ | 249 | u16 psm_macintstatus_l; /* 0x484 */ |
250 | uint16 psm_macintstatus_h; /* 0x486 */ | 250 | u16 psm_macintstatus_h; /* 0x486 */ |
251 | uint16 psm_macintmask_l; /* 0x488 */ | 251 | u16 psm_macintmask_l; /* 0x488 */ |
252 | uint16 psm_macintmask_h; /* 0x48A */ | 252 | u16 psm_macintmask_h; /* 0x48A */ |
253 | uint16 PAD; /* 0x48C */ | 253 | u16 PAD; /* 0x48C */ |
254 | uint16 psm_maccommand; /* 0x48E */ | 254 | u16 psm_maccommand; /* 0x48E */ |
255 | uint16 psm_brc; /* 0x490 */ | 255 | u16 psm_brc; /* 0x490 */ |
256 | uint16 psm_phy_hdr_param; /* 0x492 */ | 256 | u16 psm_phy_hdr_param; /* 0x492 */ |
257 | uint16 psm_postcard; /* 0x494 */ | 257 | u16 psm_postcard; /* 0x494 */ |
258 | uint16 psm_pcard_loc_l; /* 0x496 */ | 258 | u16 psm_pcard_loc_l; /* 0x496 */ |
259 | uint16 psm_pcard_loc_h; /* 0x498 */ | 259 | u16 psm_pcard_loc_h; /* 0x498 */ |
260 | uint16 psm_gpio_in; /* 0x49A */ | 260 | u16 psm_gpio_in; /* 0x49A */ |
261 | uint16 psm_gpio_out; /* 0x49C */ | 261 | u16 psm_gpio_out; /* 0x49C */ |
262 | uint16 psm_gpio_oe; /* 0x49E */ | 262 | u16 psm_gpio_oe; /* 0x49E */ |
263 | 263 | ||
264 | uint16 psm_bred_0; /* 0x4A0 */ | 264 | u16 psm_bred_0; /* 0x4A0 */ |
265 | uint16 psm_bred_1; /* 0x4A2 */ | 265 | u16 psm_bred_1; /* 0x4A2 */ |
266 | uint16 psm_bred_2; /* 0x4A4 */ | 266 | u16 psm_bred_2; /* 0x4A4 */ |
267 | uint16 psm_bred_3; /* 0x4A6 */ | 267 | u16 psm_bred_3; /* 0x4A6 */ |
268 | uint16 psm_brcl_0; /* 0x4A8 */ | 268 | u16 psm_brcl_0; /* 0x4A8 */ |
269 | uint16 psm_brcl_1; /* 0x4AA */ | 269 | u16 psm_brcl_1; /* 0x4AA */ |
270 | uint16 psm_brcl_2; /* 0x4AC */ | 270 | u16 psm_brcl_2; /* 0x4AC */ |
271 | uint16 psm_brcl_3; /* 0x4AE */ | 271 | u16 psm_brcl_3; /* 0x4AE */ |
272 | uint16 psm_brpo_0; /* 0x4B0 */ | 272 | u16 psm_brpo_0; /* 0x4B0 */ |
273 | uint16 psm_brpo_1; /* 0x4B2 */ | 273 | u16 psm_brpo_1; /* 0x4B2 */ |
274 | uint16 psm_brpo_2; /* 0x4B4 */ | 274 | u16 psm_brpo_2; /* 0x4B4 */ |
275 | uint16 psm_brpo_3; /* 0x4B6 */ | 275 | u16 psm_brpo_3; /* 0x4B6 */ |
276 | uint16 psm_brwk_0; /* 0x4B8 */ | 276 | u16 psm_brwk_0; /* 0x4B8 */ |
277 | uint16 psm_brwk_1; /* 0x4BA */ | 277 | u16 psm_brwk_1; /* 0x4BA */ |
278 | uint16 psm_brwk_2; /* 0x4BC */ | 278 | u16 psm_brwk_2; /* 0x4BC */ |
279 | uint16 psm_brwk_3; /* 0x4BE */ | 279 | u16 psm_brwk_3; /* 0x4BE */ |
280 | 280 | ||
281 | uint16 psm_base_0; /* 0x4C0 */ | 281 | u16 psm_base_0; /* 0x4C0 */ |
282 | uint16 psm_base_1; /* 0x4C2 */ | 282 | u16 psm_base_1; /* 0x4C2 */ |
283 | uint16 psm_base_2; /* 0x4C4 */ | 283 | u16 psm_base_2; /* 0x4C4 */ |
284 | uint16 psm_base_3; /* 0x4C6 */ | 284 | u16 psm_base_3; /* 0x4C6 */ |
285 | uint16 psm_base_4; /* 0x4C8 */ | 285 | u16 psm_base_4; /* 0x4C8 */ |
286 | uint16 psm_base_5; /* 0x4CA */ | 286 | u16 psm_base_5; /* 0x4CA */ |
287 | uint16 psm_base_6; /* 0x4CC */ | 287 | u16 psm_base_6; /* 0x4CC */ |
288 | uint16 psm_pc_reg_0; /* 0x4CE */ | 288 | u16 psm_pc_reg_0; /* 0x4CE */ |
289 | uint16 psm_pc_reg_1; /* 0x4D0 */ | 289 | u16 psm_pc_reg_1; /* 0x4D0 */ |
290 | uint16 psm_pc_reg_2; /* 0x4D2 */ | 290 | u16 psm_pc_reg_2; /* 0x4D2 */ |
291 | uint16 psm_pc_reg_3; /* 0x4D4 */ | 291 | u16 psm_pc_reg_3; /* 0x4D4 */ |
292 | uint16 PAD[0xD]; /* 0x4D6 - 0x4DE */ | 292 | u16 PAD[0xD]; /* 0x4D6 - 0x4DE */ |
293 | uint16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */ | 293 | u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */ |
294 | uint16 PAD[0x7]; /* 0x4f2 - 0x4fE */ | 294 | u16 PAD[0x7]; /* 0x4f2 - 0x4fE */ |
295 | 295 | ||
296 | /* TXE0 Block *//* 0x500 - 0x580 */ | 296 | /* TXE0 Block *//* 0x500 - 0x580 */ |
297 | uint16 txe_ctl; /* 0x500 */ | 297 | u16 txe_ctl; /* 0x500 */ |
298 | uint16 txe_aux; /* 0x502 */ | 298 | u16 txe_aux; /* 0x502 */ |
299 | uint16 txe_ts_loc; /* 0x504 */ | 299 | u16 txe_ts_loc; /* 0x504 */ |
300 | uint16 txe_time_out; /* 0x506 */ | 300 | u16 txe_time_out; /* 0x506 */ |
301 | uint16 txe_wm_0; /* 0x508 */ | 301 | u16 txe_wm_0; /* 0x508 */ |
302 | uint16 txe_wm_1; /* 0x50A */ | 302 | u16 txe_wm_1; /* 0x50A */ |
303 | uint16 txe_phyctl; /* 0x50C */ | 303 | u16 txe_phyctl; /* 0x50C */ |
304 | uint16 txe_status; /* 0x50E */ | 304 | u16 txe_status; /* 0x50E */ |
305 | uint16 txe_mmplcp0; /* 0x510 */ | 305 | u16 txe_mmplcp0; /* 0x510 */ |
306 | uint16 txe_mmplcp1; /* 0x512 */ | 306 | u16 txe_mmplcp1; /* 0x512 */ |
307 | uint16 txe_phyctl1; /* 0x514 */ | 307 | u16 txe_phyctl1; /* 0x514 */ |
308 | 308 | ||
309 | uint16 PAD[0x05]; /* 0x510 - 0x51E */ | 309 | u16 PAD[0x05]; /* 0x510 - 0x51E */ |
310 | 310 | ||
311 | /* Transmit control */ | 311 | /* Transmit control */ |
312 | uint16 xmtfifodef; /* 0x520 */ | 312 | u16 xmtfifodef; /* 0x520 */ |
313 | uint16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */ | 313 | u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */ |
314 | uint16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */ | 314 | u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */ |
315 | uint16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */ | 315 | u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */ |
316 | uint16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */ | 316 | u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */ |
317 | uint16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */ | 317 | u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */ |
318 | uint16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */ | 318 | u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */ |
319 | 319 | ||
320 | uint16 PAD[0x09]; /* 0x52E - 0x53E */ | 320 | u16 PAD[0x09]; /* 0x52E - 0x53E */ |
321 | 321 | ||
322 | uint16 xmtfifocmd; /* 0x540 */ | 322 | u16 xmtfifocmd; /* 0x540 */ |
323 | uint16 xmtfifoflush; /* 0x542 */ | 323 | u16 xmtfifoflush; /* 0x542 */ |
324 | uint16 xmtfifothresh; /* 0x544 */ | 324 | u16 xmtfifothresh; /* 0x544 */ |
325 | uint16 xmtfifordy; /* 0x546 */ | 325 | u16 xmtfifordy; /* 0x546 */ |
326 | uint16 xmtfifoprirdy; /* 0x548 */ | 326 | u16 xmtfifoprirdy; /* 0x548 */ |
327 | uint16 xmtfiforqpri; /* 0x54A */ | 327 | u16 xmtfiforqpri; /* 0x54A */ |
328 | uint16 xmttplatetxptr; /* 0x54C */ | 328 | u16 xmttplatetxptr; /* 0x54C */ |
329 | uint16 PAD; /* 0x54E */ | 329 | u16 PAD; /* 0x54E */ |
330 | uint16 xmttplateptr; /* 0x550 */ | 330 | u16 xmttplateptr; /* 0x550 */ |
331 | uint16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */ | 331 | u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */ |
332 | uint16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */ | 332 | u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */ |
333 | uint16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */ | 333 | u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */ |
334 | uint16 PAD[0x04]; /* 0x558 - 0x55E */ | 334 | u16 PAD[0x04]; /* 0x558 - 0x55E */ |
335 | uint16 xmttplatedatalo; /* 0x560 */ | 335 | u16 xmttplatedatalo; /* 0x560 */ |
336 | uint16 xmttplatedatahi; /* 0x562 */ | 336 | u16 xmttplatedatahi; /* 0x562 */ |
337 | 337 | ||
338 | uint16 PAD[2]; /* 0x564 - 0x566 */ | 338 | u16 PAD[2]; /* 0x564 - 0x566 */ |
339 | 339 | ||
340 | uint16 xmtsel; /* 0x568 */ | 340 | u16 xmtsel; /* 0x568 */ |
341 | uint16 xmttxcnt; /* 0x56A */ | 341 | u16 xmttxcnt; /* 0x56A */ |
342 | uint16 xmttxshmaddr; /* 0x56C */ | 342 | u16 xmttxshmaddr; /* 0x56C */ |
343 | 343 | ||
344 | uint16 PAD[0x09]; /* 0x56E - 0x57E */ | 344 | u16 PAD[0x09]; /* 0x56E - 0x57E */ |
345 | 345 | ||
346 | /* TXE1 Block */ | 346 | /* TXE1 Block */ |
347 | uint16 PAD[0x40]; /* 0x580 - 0x5FE */ | 347 | u16 PAD[0x40]; /* 0x580 - 0x5FE */ |
348 | 348 | ||
349 | /* TSF Block */ | 349 | /* TSF Block */ |
350 | uint16 PAD[0X02]; /* 0x600 - 0x602 */ | 350 | u16 PAD[0X02]; /* 0x600 - 0x602 */ |
351 | uint16 tsf_cfpstrt_l; /* 0x604 */ | 351 | u16 tsf_cfpstrt_l; /* 0x604 */ |
352 | uint16 tsf_cfpstrt_h; /* 0x606 */ | 352 | u16 tsf_cfpstrt_h; /* 0x606 */ |
353 | uint16 PAD[0X05]; /* 0x608 - 0x610 */ | 353 | u16 PAD[0X05]; /* 0x608 - 0x610 */ |
354 | uint16 tsf_cfppretbtt; /* 0x612 */ | 354 | u16 tsf_cfppretbtt; /* 0x612 */ |
355 | uint16 PAD[0XD]; /* 0x614 - 0x62C */ | 355 | u16 PAD[0XD]; /* 0x614 - 0x62C */ |
356 | uint16 tsf_clk_frac_l; /* 0x62E */ | 356 | u16 tsf_clk_frac_l; /* 0x62E */ |
357 | uint16 tsf_clk_frac_h; /* 0x630 */ | 357 | u16 tsf_clk_frac_h; /* 0x630 */ |
358 | uint16 PAD[0X14]; /* 0x632 - 0x658 */ | 358 | u16 PAD[0X14]; /* 0x632 - 0x658 */ |
359 | uint16 tsf_random; /* 0x65A */ | 359 | u16 tsf_random; /* 0x65A */ |
360 | uint16 PAD[0x05]; /* 0x65C - 0x664 */ | 360 | u16 PAD[0x05]; /* 0x65C - 0x664 */ |
361 | /* GPTimer 2 registers are corerev >= 3 */ | 361 | /* GPTimer 2 registers are corerev >= 3 */ |
362 | uint16 tsf_gpt2_stat; /* 0x666 */ | 362 | u16 tsf_gpt2_stat; /* 0x666 */ |
363 | uint16 tsf_gpt2_ctr_l; /* 0x668 */ | 363 | u16 tsf_gpt2_ctr_l; /* 0x668 */ |
364 | uint16 tsf_gpt2_ctr_h; /* 0x66A */ | 364 | u16 tsf_gpt2_ctr_h; /* 0x66A */ |
365 | uint16 tsf_gpt2_val_l; /* 0x66C */ | 365 | u16 tsf_gpt2_val_l; /* 0x66C */ |
366 | uint16 tsf_gpt2_val_h; /* 0x66E */ | 366 | u16 tsf_gpt2_val_h; /* 0x66E */ |
367 | uint16 tsf_gptall_stat; /* 0x670 */ | 367 | u16 tsf_gptall_stat; /* 0x670 */ |
368 | uint16 PAD[0x07]; /* 0x672 - 0x67E */ | 368 | u16 PAD[0x07]; /* 0x672 - 0x67E */ |
369 | 369 | ||
370 | /* IFS Block */ | 370 | /* IFS Block */ |
371 | uint16 ifs_sifs_rx_tx_tx; /* 0x680 */ | 371 | u16 ifs_sifs_rx_tx_tx; /* 0x680 */ |
372 | uint16 ifs_sifs_nav_tx; /* 0x682 */ | 372 | u16 ifs_sifs_nav_tx; /* 0x682 */ |
373 | uint16 ifs_slot; /* 0x684 */ | 373 | u16 ifs_slot; /* 0x684 */ |
374 | uint16 PAD; /* 0x686 */ | 374 | u16 PAD; /* 0x686 */ |
375 | uint16 ifs_ctl; /* 0x688 */ | 375 | u16 ifs_ctl; /* 0x688 */ |
376 | uint16 PAD[0x3]; /* 0x68a - 0x68F */ | 376 | u16 PAD[0x3]; /* 0x68a - 0x68F */ |
377 | uint16 ifsstat; /* 0x690 */ | 377 | u16 ifsstat; /* 0x690 */ |
378 | uint16 ifsmedbusyctl; /* 0x692 */ | 378 | u16 ifsmedbusyctl; /* 0x692 */ |
379 | uint16 iftxdur; /* 0x694 */ | 379 | u16 iftxdur; /* 0x694 */ |
380 | uint16 PAD[0x3]; /* 0x696 - 0x69b */ | 380 | u16 PAD[0x3]; /* 0x696 - 0x69b */ |
381 | /* EDCF support in dot11macs with corerevs >= 16 */ | 381 | /* EDCF support in dot11macs with corerevs >= 16 */ |
382 | uint16 ifs_aifsn; /* 0x69c */ | 382 | u16 ifs_aifsn; /* 0x69c */ |
383 | uint16 ifs_ctl1; /* 0x69e */ | 383 | u16 ifs_ctl1; /* 0x69e */ |
384 | 384 | ||
385 | /* New slow clock registers on corerev >= 5 */ | 385 | /* New slow clock registers on corerev >= 5 */ |
386 | uint16 scc_ctl; /* 0x6a0 */ | 386 | u16 scc_ctl; /* 0x6a0 */ |
387 | uint16 scc_timer_l; /* 0x6a2 */ | 387 | u16 scc_timer_l; /* 0x6a2 */ |
388 | uint16 scc_timer_h; /* 0x6a4 */ | 388 | u16 scc_timer_h; /* 0x6a4 */ |
389 | uint16 scc_frac; /* 0x6a6 */ | 389 | u16 scc_frac; /* 0x6a6 */ |
390 | uint16 scc_fastpwrup_dly; /* 0x6a8 */ | 390 | u16 scc_fastpwrup_dly; /* 0x6a8 */ |
391 | uint16 scc_per; /* 0x6aa */ | 391 | u16 scc_per; /* 0x6aa */ |
392 | uint16 scc_per_frac; /* 0x6ac */ | 392 | u16 scc_per_frac; /* 0x6ac */ |
393 | uint16 scc_cal_timer_l; /* 0x6ae */ | 393 | u16 scc_cal_timer_l; /* 0x6ae */ |
394 | uint16 scc_cal_timer_h; /* 0x6b0 */ | 394 | u16 scc_cal_timer_h; /* 0x6b0 */ |
395 | uint16 PAD; /* 0x6b2 */ | 395 | u16 PAD; /* 0x6b2 */ |
396 | 396 | ||
397 | uint16 PAD[0x26]; | 397 | u16 PAD[0x26]; |
398 | 398 | ||
399 | /* NAV Block */ | 399 | /* NAV Block */ |
400 | uint16 nav_ctl; /* 0x700 */ | 400 | u16 nav_ctl; /* 0x700 */ |
401 | uint16 navstat; /* 0x702 */ | 401 | u16 navstat; /* 0x702 */ |
402 | uint16 PAD[0x3e]; /* 0x702 - 0x77E */ | 402 | u16 PAD[0x3e]; /* 0x702 - 0x77E */ |
403 | 403 | ||
404 | /* WEP/PMQ Block *//* 0x780 - 0x7FE */ | 404 | /* WEP/PMQ Block *//* 0x780 - 0x7FE */ |
405 | uint16 PAD[0x20]; /* 0x780 - 0x7BE */ | 405 | u16 PAD[0x20]; /* 0x780 - 0x7BE */ |
406 | 406 | ||
407 | uint16 wepctl; /* 0x7C0 */ | 407 | u16 wepctl; /* 0x7C0 */ |
408 | uint16 wepivloc; /* 0x7C2 */ | 408 | u16 wepivloc; /* 0x7C2 */ |
409 | uint16 wepivkey; /* 0x7C4 */ | 409 | u16 wepivkey; /* 0x7C4 */ |
410 | uint16 wepwkey; /* 0x7C6 */ | 410 | u16 wepwkey; /* 0x7C6 */ |
411 | 411 | ||
412 | uint16 PAD[4]; /* 0x7C8 - 0x7CE */ | 412 | u16 PAD[4]; /* 0x7C8 - 0x7CE */ |
413 | uint16 pcmctl; /* 0X7D0 */ | 413 | u16 pcmctl; /* 0X7D0 */ |
414 | uint16 pcmstat; /* 0X7D2 */ | 414 | u16 pcmstat; /* 0X7D2 */ |
415 | uint16 PAD[6]; /* 0x7D4 - 0x7DE */ | 415 | u16 PAD[6]; /* 0x7D4 - 0x7DE */ |
416 | 416 | ||
417 | uint16 pmqctl; /* 0x7E0 */ | 417 | u16 pmqctl; /* 0x7E0 */ |
418 | uint16 pmqstatus; /* 0x7E2 */ | 418 | u16 pmqstatus; /* 0x7E2 */ |
419 | uint16 pmqpat0; /* 0x7E4 */ | 419 | u16 pmqpat0; /* 0x7E4 */ |
420 | uint16 pmqpat1; /* 0x7E6 */ | 420 | u16 pmqpat1; /* 0x7E6 */ |
421 | uint16 pmqpat2; /* 0x7E8 */ | 421 | u16 pmqpat2; /* 0x7E8 */ |
422 | 422 | ||
423 | uint16 pmqdat; /* 0x7EA */ | 423 | u16 pmqdat; /* 0x7EA */ |
424 | uint16 pmqdator; /* 0x7EC */ | 424 | u16 pmqdator; /* 0x7EC */ |
425 | uint16 pmqhst; /* 0x7EE */ | 425 | u16 pmqhst; /* 0x7EE */ |
426 | uint16 pmqpath0; /* 0x7F0 */ | 426 | u16 pmqpath0; /* 0x7F0 */ |
427 | uint16 pmqpath1; /* 0x7F2 */ | 427 | u16 pmqpath1; /* 0x7F2 */ |
428 | uint16 pmqpath2; /* 0x7F4 */ | 428 | u16 pmqpath2; /* 0x7F4 */ |
429 | uint16 pmqdath; /* 0x7F6 */ | 429 | u16 pmqdath; /* 0x7F6 */ |
430 | 430 | ||
431 | uint16 PAD[0x04]; /* 0x7F8 - 0x7FE */ | 431 | u16 PAD[0x04]; /* 0x7F8 - 0x7FE */ |
432 | 432 | ||
433 | /* SHM *//* 0x800 - 0xEFE */ | 433 | /* SHM *//* 0x800 - 0xEFE */ |
434 | uint16 PAD[0x380]; /* 0x800 - 0xEFE */ | 434 | u16 PAD[0x380]; /* 0x800 - 0xEFE */ |
435 | 435 | ||
436 | /* SB configuration registers: 0xF00 */ | 436 | /* SB configuration registers: 0xF00 */ |
437 | sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */ | 437 | sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */ |
@@ -634,7 +634,7 @@ typedef volatile struct _d11regs { | |||
634 | typedef struct ofdm_phy_hdr ofdm_phy_hdr_t; | 634 | typedef struct ofdm_phy_hdr ofdm_phy_hdr_t; |
635 | BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr { | 635 | BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr { |
636 | u8 rlpt[3]; /* rate, length, parity, tail */ | 636 | u8 rlpt[3]; /* rate, length, parity, tail */ |
637 | uint16 service; | 637 | u16 service; |
638 | u8 pad; | 638 | u8 pad; |
639 | } BWL_POST_PACKED_STRUCT; | 639 | } BWL_POST_PACKED_STRUCT; |
640 | 640 | ||
@@ -670,8 +670,8 @@ typedef struct cck_phy_hdr cck_phy_hdr_t; | |||
670 | BWL_PRE_PACKED_STRUCT struct cck_phy_hdr { | 670 | BWL_PRE_PACKED_STRUCT struct cck_phy_hdr { |
671 | u8 signal; | 671 | u8 signal; |
672 | u8 service; | 672 | u8 service; |
673 | uint16 length; | 673 | u16 length; |
674 | uint16 crc; | 674 | u16 crc; |
675 | } BWL_POST_PACKED_STRUCT; | 675 | } BWL_POST_PACKED_STRUCT; |
676 | 676 | ||
677 | #define D11B_PHY_HDR_LEN 6 | 677 | #define D11B_PHY_HDR_LEN 6 |
@@ -714,40 +714,40 @@ BWL_PRE_PACKED_STRUCT struct cck_phy_hdr { | |||
714 | /* TX DMA buffer header */ | 714 | /* TX DMA buffer header */ |
715 | typedef struct d11txh d11txh_t; | 715 | typedef struct d11txh d11txh_t; |
716 | BWL_PRE_PACKED_STRUCT struct d11txh { | 716 | BWL_PRE_PACKED_STRUCT struct d11txh { |
717 | uint16 MacTxControlLow; /* 0x0 */ | 717 | u16 MacTxControlLow; /* 0x0 */ |
718 | uint16 MacTxControlHigh; /* 0x1 */ | 718 | u16 MacTxControlHigh; /* 0x1 */ |
719 | uint16 MacFrameControl; /* 0x2 */ | 719 | u16 MacFrameControl; /* 0x2 */ |
720 | uint16 TxFesTimeNormal; /* 0x3 */ | 720 | u16 TxFesTimeNormal; /* 0x3 */ |
721 | uint16 PhyTxControlWord; /* 0x4 */ | 721 | u16 PhyTxControlWord; /* 0x4 */ |
722 | uint16 PhyTxControlWord_1; /* 0x5 */ | 722 | u16 PhyTxControlWord_1; /* 0x5 */ |
723 | uint16 PhyTxControlWord_1_Fbr; /* 0x6 */ | 723 | u16 PhyTxControlWord_1_Fbr; /* 0x6 */ |
724 | uint16 PhyTxControlWord_1_Rts; /* 0x7 */ | 724 | u16 PhyTxControlWord_1_Rts; /* 0x7 */ |
725 | uint16 PhyTxControlWord_1_FbrRts; /* 0x8 */ | 725 | u16 PhyTxControlWord_1_FbrRts; /* 0x8 */ |
726 | uint16 MainRates; /* 0x9 */ | 726 | u16 MainRates; /* 0x9 */ |
727 | uint16 XtraFrameTypes; /* 0xa */ | 727 | u16 XtraFrameTypes; /* 0xa */ |
728 | u8 IV[16]; /* 0x0b - 0x12 */ | 728 | u8 IV[16]; /* 0x0b - 0x12 */ |
729 | u8 TxFrameRA[6]; /* 0x13 - 0x15 */ | 729 | u8 TxFrameRA[6]; /* 0x13 - 0x15 */ |
730 | uint16 TxFesTimeFallback; /* 0x16 */ | 730 | u16 TxFesTimeFallback; /* 0x16 */ |
731 | u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */ | 731 | u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */ |
732 | uint16 RTSDurFallback; /* 0x1a */ | 732 | u16 RTSDurFallback; /* 0x1a */ |
733 | u8 FragPLCPFallback[6]; /* 0x1b - 1d */ | 733 | u8 FragPLCPFallback[6]; /* 0x1b - 1d */ |
734 | uint16 FragDurFallback; /* 0x1e */ | 734 | u16 FragDurFallback; /* 0x1e */ |
735 | uint16 MModeLen; /* 0x1f */ | 735 | u16 MModeLen; /* 0x1f */ |
736 | uint16 MModeFbrLen; /* 0x20 */ | 736 | u16 MModeFbrLen; /* 0x20 */ |
737 | uint16 TstampLow; /* 0x21 */ | 737 | u16 TstampLow; /* 0x21 */ |
738 | uint16 TstampHigh; /* 0x22 */ | 738 | u16 TstampHigh; /* 0x22 */ |
739 | uint16 ABI_MimoAntSel; /* 0x23 */ | 739 | u16 ABI_MimoAntSel; /* 0x23 */ |
740 | uint16 PreloadSize; /* 0x24 */ | 740 | u16 PreloadSize; /* 0x24 */ |
741 | uint16 AmpduSeqCtl; /* 0x25 */ | 741 | u16 AmpduSeqCtl; /* 0x25 */ |
742 | uint16 TxFrameID; /* 0x26 */ | 742 | u16 TxFrameID; /* 0x26 */ |
743 | uint16 TxStatus; /* 0x27 */ | 743 | u16 TxStatus; /* 0x27 */ |
744 | uint16 MaxNMpdus; /* 0x28 corerev >=16 */ | 744 | u16 MaxNMpdus; /* 0x28 corerev >=16 */ |
745 | uint16 MaxABytes_MRT; /* 0x29 corerev >=16 */ | 745 | u16 MaxABytes_MRT; /* 0x29 corerev >=16 */ |
746 | uint16 MaxABytes_FBR; /* 0x2a corerev >=16 */ | 746 | u16 MaxABytes_FBR; /* 0x2a corerev >=16 */ |
747 | uint16 MinMBytes; /* 0x2b corerev >=16 */ | 747 | u16 MinMBytes; /* 0x2b corerev >=16 */ |
748 | u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */ | 748 | u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */ |
749 | struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */ | 749 | struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */ |
750 | uint16 PAD; /* 0x37 */ | 750 | u16 PAD; /* 0x37 */ |
751 | } BWL_POST_PACKED_STRUCT; | 751 | } BWL_POST_PACKED_STRUCT; |
752 | 752 | ||
753 | #define D11_TXH_LEN 112 /* bytes */ | 753 | #define D11_TXH_LEN 112 /* bytes */ |
@@ -858,14 +858,14 @@ BWL_PRE_PACKED_STRUCT struct d11txh { | |||
858 | /* tx status packet */ | 858 | /* tx status packet */ |
859 | typedef struct tx_status tx_status_t; | 859 | typedef struct tx_status tx_status_t; |
860 | BWL_PRE_PACKED_STRUCT struct tx_status { | 860 | BWL_PRE_PACKED_STRUCT struct tx_status { |
861 | uint16 framelen; | 861 | u16 framelen; |
862 | uint16 PAD; | 862 | u16 PAD; |
863 | uint16 frameid; | 863 | u16 frameid; |
864 | uint16 status; | 864 | u16 status; |
865 | uint16 lasttxtime; | 865 | u16 lasttxtime; |
866 | uint16 sequence; | 866 | u16 sequence; |
867 | uint16 phyerr; | 867 | u16 phyerr; |
868 | uint16 ackphyrxsh; | 868 | u16 ackphyrxsh; |
869 | } BWL_POST_PACKED_STRUCT; | 869 | } BWL_POST_PACKED_STRUCT; |
870 | 870 | ||
871 | #define TXSTATUS_LEN 16 | 871 | #define TXSTATUS_LEN 16 |
@@ -1251,22 +1251,22 @@ BWL_PRE_PACKED_STRUCT struct tx_status { | |||
1251 | 1251 | ||
1252 | typedef struct shm_acparams shm_acparams_t; | 1252 | typedef struct shm_acparams shm_acparams_t; |
1253 | BWL_PRE_PACKED_STRUCT struct shm_acparams { | 1253 | BWL_PRE_PACKED_STRUCT struct shm_acparams { |
1254 | uint16 txop; | 1254 | u16 txop; |
1255 | uint16 cwmin; | 1255 | u16 cwmin; |
1256 | uint16 cwmax; | 1256 | u16 cwmax; |
1257 | uint16 cwcur; | 1257 | u16 cwcur; |
1258 | uint16 aifs; | 1258 | u16 aifs; |
1259 | uint16 bslots; | 1259 | u16 bslots; |
1260 | uint16 reggap; | 1260 | u16 reggap; |
1261 | uint16 status; | 1261 | u16 status; |
1262 | uint16 rsvd[8]; | 1262 | u16 rsvd[8]; |
1263 | } BWL_POST_PACKED_STRUCT; | 1263 | } BWL_POST_PACKED_STRUCT; |
1264 | #define M_EDCF_QLEN (16 * 2) | 1264 | #define M_EDCF_QLEN (16 * 2) |
1265 | 1265 | ||
1266 | #define WME_STATUS_NEWAC (1 << 8) | 1266 | #define WME_STATUS_NEWAC (1 << 8) |
1267 | 1267 | ||
1268 | /* M_HOST_FLAGS */ | 1268 | /* M_HOST_FLAGS */ |
1269 | #define MHFMAX 5 /* Number of valid hostflag half-word (uint16) */ | 1269 | #define MHFMAX 5 /* Number of valid hostflag half-word (u16) */ |
1270 | #define MHF1 0 /* Hostflag 1 index */ | 1270 | #define MHF1 0 /* Hostflag 1 index */ |
1271 | #define MHF2 1 /* Hostflag 2 index */ | 1271 | #define MHF2 1 /* Hostflag 2 index */ |
1272 | #define MHF3 2 /* Hostflag 3 index */ | 1272 | #define MHF3 2 /* Hostflag 3 index */ |
@@ -1310,18 +1310,18 @@ BWL_PRE_PACKED_STRUCT struct shm_acparams { | |||
1310 | /* Receive Frame Data Header for 802.11b DCF-only frames */ | 1310 | /* Receive Frame Data Header for 802.11b DCF-only frames */ |
1311 | typedef struct d11rxhdr d11rxhdr_t; | 1311 | typedef struct d11rxhdr d11rxhdr_t; |
1312 | BWL_PRE_PACKED_STRUCT struct d11rxhdr { | 1312 | BWL_PRE_PACKED_STRUCT struct d11rxhdr { |
1313 | uint16 RxFrameSize; /* Actual byte length of the frame data received */ | 1313 | u16 RxFrameSize; /* Actual byte length of the frame data received */ |
1314 | uint16 PAD; | 1314 | u16 PAD; |
1315 | uint16 PhyRxStatus_0; /* PhyRxStatus 15:0 */ | 1315 | u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */ |
1316 | uint16 PhyRxStatus_1; /* PhyRxStatus 31:16 */ | 1316 | u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */ |
1317 | uint16 PhyRxStatus_2; /* PhyRxStatus 47:32 */ | 1317 | u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */ |
1318 | uint16 PhyRxStatus_3; /* PhyRxStatus 63:48 */ | 1318 | u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */ |
1319 | uint16 PhyRxStatus_4; /* PhyRxStatus 79:64 */ | 1319 | u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */ |
1320 | uint16 PhyRxStatus_5; /* PhyRxStatus 95:80 */ | 1320 | u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */ |
1321 | uint16 RxStatus1; /* MAC Rx Status */ | 1321 | u16 RxStatus1; /* MAC Rx Status */ |
1322 | uint16 RxStatus2; /* extended MAC Rx status */ | 1322 | u16 RxStatus2; /* extended MAC Rx status */ |
1323 | uint16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ | 1323 | u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ |
1324 | uint16 RxChan; /* gain code, channel radio code, and phy type */ | 1324 | u16 RxChan; /* gain code, channel radio code, and phy type */ |
1325 | } BWL_POST_PACKED_STRUCT; | 1325 | } BWL_POST_PACKED_STRUCT; |
1326 | 1326 | ||
1327 | #define RXHDR_LEN 24 /* sizeof d11rxhdr_t */ | 1327 | #define RXHDR_LEN 24 /* sizeof d11rxhdr_t */ |
@@ -1566,63 +1566,63 @@ typedef enum { | |||
1566 | 1566 | ||
1567 | /* ucode mac statistic counters in shared memory */ | 1567 | /* ucode mac statistic counters in shared memory */ |
1568 | typedef struct macstat { | 1568 | typedef struct macstat { |
1569 | uint16 txallfrm; /* 0x80 */ | 1569 | u16 txallfrm; /* 0x80 */ |
1570 | uint16 txrtsfrm; /* 0x82 */ | 1570 | u16 txrtsfrm; /* 0x82 */ |
1571 | uint16 txctsfrm; /* 0x84 */ | 1571 | u16 txctsfrm; /* 0x84 */ |
1572 | uint16 txackfrm; /* 0x86 */ | 1572 | u16 txackfrm; /* 0x86 */ |
1573 | uint16 txdnlfrm; /* 0x88 */ | 1573 | u16 txdnlfrm; /* 0x88 */ |
1574 | uint16 txbcnfrm; /* 0x8a */ | 1574 | u16 txbcnfrm; /* 0x8a */ |
1575 | uint16 txfunfl[8]; /* 0x8c - 0x9b */ | 1575 | u16 txfunfl[8]; /* 0x8c - 0x9b */ |
1576 | uint16 txtplunfl; /* 0x9c */ | 1576 | u16 txtplunfl; /* 0x9c */ |
1577 | uint16 txphyerr; /* 0x9e */ | 1577 | u16 txphyerr; /* 0x9e */ |
1578 | uint16 pktengrxducast; /* 0xa0 */ | 1578 | u16 pktengrxducast; /* 0xa0 */ |
1579 | uint16 pktengrxdmcast; /* 0xa2 */ | 1579 | u16 pktengrxdmcast; /* 0xa2 */ |
1580 | uint16 rxfrmtoolong; /* 0xa4 */ | 1580 | u16 rxfrmtoolong; /* 0xa4 */ |
1581 | uint16 rxfrmtooshrt; /* 0xa6 */ | 1581 | u16 rxfrmtooshrt; /* 0xa6 */ |
1582 | uint16 rxinvmachdr; /* 0xa8 */ | 1582 | u16 rxinvmachdr; /* 0xa8 */ |
1583 | uint16 rxbadfcs; /* 0xaa */ | 1583 | u16 rxbadfcs; /* 0xaa */ |
1584 | uint16 rxbadplcp; /* 0xac */ | 1584 | u16 rxbadplcp; /* 0xac */ |
1585 | uint16 rxcrsglitch; /* 0xae */ | 1585 | u16 rxcrsglitch; /* 0xae */ |
1586 | uint16 rxstrt; /* 0xb0 */ | 1586 | u16 rxstrt; /* 0xb0 */ |
1587 | uint16 rxdfrmucastmbss; /* 0xb2 */ | 1587 | u16 rxdfrmucastmbss; /* 0xb2 */ |
1588 | uint16 rxmfrmucastmbss; /* 0xb4 */ | 1588 | u16 rxmfrmucastmbss; /* 0xb4 */ |
1589 | uint16 rxcfrmucast; /* 0xb6 */ | 1589 | u16 rxcfrmucast; /* 0xb6 */ |
1590 | uint16 rxrtsucast; /* 0xb8 */ | 1590 | u16 rxrtsucast; /* 0xb8 */ |
1591 | uint16 rxctsucast; /* 0xba */ | 1591 | u16 rxctsucast; /* 0xba */ |
1592 | uint16 rxackucast; /* 0xbc */ | 1592 | u16 rxackucast; /* 0xbc */ |
1593 | uint16 rxdfrmocast; /* 0xbe */ | 1593 | u16 rxdfrmocast; /* 0xbe */ |
1594 | uint16 rxmfrmocast; /* 0xc0 */ | 1594 | u16 rxmfrmocast; /* 0xc0 */ |
1595 | uint16 rxcfrmocast; /* 0xc2 */ | 1595 | u16 rxcfrmocast; /* 0xc2 */ |
1596 | uint16 rxrtsocast; /* 0xc4 */ | 1596 | u16 rxrtsocast; /* 0xc4 */ |
1597 | uint16 rxctsocast; /* 0xc6 */ | 1597 | u16 rxctsocast; /* 0xc6 */ |
1598 | uint16 rxdfrmmcast; /* 0xc8 */ | 1598 | u16 rxdfrmmcast; /* 0xc8 */ |
1599 | uint16 rxmfrmmcast; /* 0xca */ | 1599 | u16 rxmfrmmcast; /* 0xca */ |
1600 | uint16 rxcfrmmcast; /* 0xcc */ | 1600 | u16 rxcfrmmcast; /* 0xcc */ |
1601 | uint16 rxbeaconmbss; /* 0xce */ | 1601 | u16 rxbeaconmbss; /* 0xce */ |
1602 | uint16 rxdfrmucastobss; /* 0xd0 */ | 1602 | u16 rxdfrmucastobss; /* 0xd0 */ |
1603 | uint16 rxbeaconobss; /* 0xd2 */ | 1603 | u16 rxbeaconobss; /* 0xd2 */ |
1604 | uint16 rxrsptmout; /* 0xd4 */ | 1604 | u16 rxrsptmout; /* 0xd4 */ |
1605 | uint16 bcntxcancl; /* 0xd6 */ | 1605 | u16 bcntxcancl; /* 0xd6 */ |
1606 | uint16 PAD; | 1606 | u16 PAD; |
1607 | uint16 rxf0ovfl; /* 0xda */ | 1607 | u16 rxf0ovfl; /* 0xda */ |
1608 | uint16 rxf1ovfl; /* 0xdc */ | 1608 | u16 rxf1ovfl; /* 0xdc */ |
1609 | uint16 rxf2ovfl; /* 0xde */ | 1609 | u16 rxf2ovfl; /* 0xde */ |
1610 | uint16 txsfovfl; /* 0xe0 */ | 1610 | u16 txsfovfl; /* 0xe0 */ |
1611 | uint16 pmqovfl; /* 0xe2 */ | 1611 | u16 pmqovfl; /* 0xe2 */ |
1612 | uint16 rxcgprqfrm; /* 0xe4 */ | 1612 | u16 rxcgprqfrm; /* 0xe4 */ |
1613 | uint16 rxcgprsqovfl; /* 0xe6 */ | 1613 | u16 rxcgprsqovfl; /* 0xe6 */ |
1614 | uint16 txcgprsfail; /* 0xe8 */ | 1614 | u16 txcgprsfail; /* 0xe8 */ |
1615 | uint16 txcgprssuc; /* 0xea */ | 1615 | u16 txcgprssuc; /* 0xea */ |
1616 | uint16 prs_timeout; /* 0xec */ | 1616 | u16 prs_timeout; /* 0xec */ |
1617 | uint16 rxnack; | 1617 | u16 rxnack; |
1618 | uint16 frmscons; | 1618 | u16 frmscons; |
1619 | uint16 txnack; | 1619 | u16 txnack; |
1620 | uint16 txglitch_nack; | 1620 | u16 txglitch_nack; |
1621 | uint16 txburst; /* 0xf6 # tx bursts */ | 1621 | u16 txburst; /* 0xf6 # tx bursts */ |
1622 | uint16 bphy_rxcrsglitch; /* bphy rx crs glitch */ | 1622 | u16 bphy_rxcrsglitch; /* bphy rx crs glitch */ |
1623 | uint16 phywatchdog; /* 0xfa # of phy watchdog events */ | 1623 | u16 phywatchdog; /* 0xfa # of phy watchdog events */ |
1624 | uint16 PAD; | 1624 | u16 PAD; |
1625 | uint16 bphy_badplcp; /* bphy bad plcp */ | 1625 | u16 bphy_badplcp; /* bphy bad plcp */ |
1626 | } macstat_t; | 1626 | } macstat_t; |
1627 | 1627 | ||
1628 | /* dot11 core-specific control flags */ | 1628 | /* dot11 core-specific control flags */ |
diff --git a/drivers/staging/brcm80211/include/hnddma.h b/drivers/staging/brcm80211/include/hnddma.h index 1a35f3e7670..c268af61820 100644 --- a/drivers/staging/brcm80211/include/hnddma.h +++ b/drivers/staging/brcm80211/include/hnddma.h | |||
@@ -59,8 +59,8 @@ typedef void *(*di_getnexttxp_t) (hnddma_t *dmah, txd_range_t range); | |||
59 | typedef void *(*di_getnextrxp_t) (hnddma_t *dmah, bool forceall); | 59 | typedef void *(*di_getnextrxp_t) (hnddma_t *dmah, bool forceall); |
60 | typedef void *(*di_peeknexttxp_t) (hnddma_t *dmah); | 60 | typedef void *(*di_peeknexttxp_t) (hnddma_t *dmah); |
61 | typedef void *(*di_peeknextrxp_t) (hnddma_t *dmah); | 61 | typedef void *(*di_peeknextrxp_t) (hnddma_t *dmah); |
62 | typedef void (*di_rxparam_get_t) (hnddma_t *dmah, uint16 *rxoffset, | 62 | typedef void (*di_rxparam_get_t) (hnddma_t *dmah, u16 *rxoffset, |
63 | uint16 *rxbufsize); | 63 | u16 *rxbufsize); |
64 | typedef void (*di_txblock_t) (hnddma_t *dmah); | 64 | typedef void (*di_txblock_t) (hnddma_t *dmah); |
65 | typedef void (*di_txunblock_t) (hnddma_t *dmah); | 65 | typedef void (*di_txunblock_t) (hnddma_t *dmah); |
66 | typedef uint(*di_txactive_t) (hnddma_t *dmah); | 66 | typedef uint(*di_txactive_t) (hnddma_t *dmah); |
diff --git a/drivers/staging/brcm80211/include/hndpmu.h b/drivers/staging/brcm80211/include/hndpmu.h index 2b4f8a0e064..b1011938099 100644 --- a/drivers/staging/brcm80211/include/hndpmu.h +++ b/drivers/staging/brcm80211/include/hndpmu.h | |||
@@ -46,7 +46,7 @@ extern void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh, | |||
46 | u8 bb_voltage, u8 rf_voltage); | 46 | u8 bb_voltage, u8 rf_voltage); |
47 | extern void si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, u8 ldo, | 47 | extern void si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, u8 ldo, |
48 | u8 voltage); | 48 | u8 voltage); |
49 | extern uint16 si_pmu_fast_pwrup_delay(si_t *sih, osl_t *osh); | 49 | extern u16 si_pmu_fast_pwrup_delay(si_t *sih, osl_t *osh); |
50 | extern void si_pmu_rcal(si_t *sih, osl_t *osh); | 50 | extern void si_pmu_rcal(si_t *sih, osl_t *osh); |
51 | extern void si_pmu_pllupd(si_t *sih); | 51 | extern void si_pmu_pllupd(si_t *sih); |
52 | extern void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid); | 52 | extern void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid); |
diff --git a/drivers/staging/brcm80211/include/hndtcam.h b/drivers/staging/brcm80211/include/hndtcam.h index 575456e6764..738ef9135a8 100644 --- a/drivers/staging/brcm80211/include/hndtcam.h +++ b/drivers/staging/brcm80211/include/hndtcam.h | |||
@@ -39,8 +39,8 @@ typedef struct patchaddrvalue { | |||
39 | } patchaddrvalue_t; | 39 | } patchaddrvalue_t; |
40 | 40 | ||
41 | extern void hnd_patch_init(void *srp); | 41 | extern void hnd_patch_init(void *srp); |
42 | extern void hnd_tcam_write(void *srp, uint16 index, uint32 data); | 42 | extern void hnd_tcam_write(void *srp, u16 index, uint32 data); |
43 | extern void hnd_tcam_read(void *srp, uint16 index, uint32 * content); | 43 | extern void hnd_tcam_read(void *srp, u16 index, uint32 * content); |
44 | void *hnd_tcam_init(void *srp, uint no_addrs); | 44 | void *hnd_tcam_init(void *srp, uint no_addrs); |
45 | extern void hnd_tcam_disablepatch(void *srp); | 45 | extern void hnd_tcam_disablepatch(void *srp); |
46 | extern void hnd_tcam_enablepatch(void *srp); | 46 | extern void hnd_tcam_enablepatch(void *srp); |
diff --git a/drivers/staging/brcm80211/include/linux_osl.h b/drivers/staging/brcm80211/include/linux_osl.h index 41cac00824b..1e4a920a174 100644 --- a/drivers/staging/brcm80211/include/linux_osl.h +++ b/drivers/staging/brcm80211/include/linux_osl.h | |||
@@ -128,7 +128,7 @@ extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, unsigned long *pap) | |||
128 | #define DMA_ALLOC_CONSISTENT(osh, size, align, tot, pap, dmah) \ | 128 | #define DMA_ALLOC_CONSISTENT(osh, size, align, tot, pap, dmah) \ |
129 | osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap)) | 129 | osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap)) |
130 | extern uint osl_dma_consistent_align(void); | 130 | extern uint osl_dma_consistent_align(void); |
131 | extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align, | 131 | extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, u16 align, |
132 | uint *tot, unsigned long *pap); | 132 | uint *tot, unsigned long *pap); |
133 | #endif | 133 | #endif |
134 | #define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \ | 134 | #define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \ |
@@ -193,7 +193,7 @@ extern int osl_error(int bcmerror); | |||
193 | #ifndef __mips__ | 193 | #ifndef __mips__ |
194 | #define R_REG(osh, r) (\ | 194 | #define R_REG(osh, r) (\ |
195 | SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(u8) ? readb((volatile u8*)(r)) : \ | 195 | SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(u8) ? readb((volatile u8*)(r)) : \ |
196 | sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \ | 196 | sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \ |
197 | readl((volatile uint32*)(r)), OSL_READ_REG(osh, r)) \ | 197 | readl((volatile uint32*)(r)), OSL_READ_REG(osh, r)) \ |
198 | ) | 198 | ) |
199 | #else /* __mips__ */ | 199 | #else /* __mips__ */ |
@@ -206,8 +206,8 @@ extern int osl_error(int bcmerror); | |||
206 | case sizeof(u8): \ | 206 | case sizeof(u8): \ |
207 | __osl_v = readb((volatile u8*)(r)); \ | 207 | __osl_v = readb((volatile u8*)(r)); \ |
208 | break; \ | 208 | break; \ |
209 | case sizeof(uint16): \ | 209 | case sizeof(u16): \ |
210 | __osl_v = readw((volatile uint16*)(r)); \ | 210 | __osl_v = readw((volatile u16*)(r)); \ |
211 | break; \ | 211 | break; \ |
212 | case sizeof(uint32): \ | 212 | case sizeof(uint32): \ |
213 | __osl_v = \ | 213 | __osl_v = \ |
@@ -232,8 +232,8 @@ extern int osl_error(int bcmerror); | |||
232 | switch (sizeof(*(r))) { \ | 232 | switch (sizeof(*(r))) { \ |
233 | case sizeof(u8): \ | 233 | case sizeof(u8): \ |
234 | writeb((u8)(v), (volatile u8*)(r)); break; \ | 234 | writeb((u8)(v), (volatile u8*)(r)); break; \ |
235 | case sizeof(uint16): \ | 235 | case sizeof(u16): \ |
236 | writew((uint16)(v), (volatile uint16*)(r)); break; \ | 236 | writew((u16)(v), (volatile u16*)(r)); break; \ |
237 | case sizeof(uint32): \ | 237 | case sizeof(uint32): \ |
238 | writel((uint32)(v), (volatile uint32*)(r)); break; \ | 238 | writel((uint32)(v), (volatile uint32*)(r)); break; \ |
239 | }, \ | 239 | }, \ |
@@ -249,9 +249,9 @@ extern int osl_error(int bcmerror); | |||
249 | __osl_v = \ | 249 | __osl_v = \ |
250 | readb((volatile u8*)((uintptr)(r)^3)); \ | 250 | readb((volatile u8*)((uintptr)(r)^3)); \ |
251 | break; \ | 251 | break; \ |
252 | case sizeof(uint16): \ | 252 | case sizeof(u16): \ |
253 | __osl_v = \ | 253 | __osl_v = \ |
254 | readw((volatile uint16*)((uintptr)(r)^2)); \ | 254 | readw((volatile u16*)((uintptr)(r)^2)); \ |
255 | break; \ | 255 | break; \ |
256 | case sizeof(uint32): \ | 256 | case sizeof(uint32): \ |
257 | __osl_v = readl((volatile uint32*)(r)); \ | 257 | __osl_v = readl((volatile uint32*)(r)); \ |
@@ -267,9 +267,9 @@ extern int osl_error(int bcmerror); | |||
267 | case sizeof(u8): \ | 267 | case sizeof(u8): \ |
268 | writeb((u8)(v), \ | 268 | writeb((u8)(v), \ |
269 | (volatile u8*)((uintptr)(r)^3)); break; \ | 269 | (volatile u8*)((uintptr)(r)^3)); break; \ |
270 | case sizeof(uint16): \ | 270 | case sizeof(u16): \ |
271 | writew((uint16)(v), \ | 271 | writew((u16)(v), \ |
272 | (volatile uint16*)((uintptr)(r)^2)); break; \ | 272 | (volatile u16*)((uintptr)(r)^2)); break; \ |
273 | case sizeof(uint32): \ | 273 | case sizeof(uint32): \ |
274 | writel((uint32)(v), \ | 274 | writel((uint32)(v), \ |
275 | (volatile uint32*)(r)); break; \ | 275 | (volatile uint32*)(r)); break; \ |
@@ -413,7 +413,7 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt) | |||
413 | #if defined(BCMSDIO) && !defined(BRCM_FULLMAC) | 413 | #if defined(BCMSDIO) && !defined(BRCM_FULLMAC) |
414 | #define RPC_READ_REG(osh, r) (\ | 414 | #define RPC_READ_REG(osh, r) (\ |
415 | sizeof(*(r)) == sizeof(u8) ? osl_readb((osh), (volatile u8*)(r)) : \ | 415 | sizeof(*(r)) == sizeof(u8) ? osl_readb((osh), (volatile u8*)(r)) : \ |
416 | sizeof(*(r)) == sizeof(uint16) ? osl_readw((osh), (volatile uint16*)(r)) : \ | 416 | sizeof(*(r)) == sizeof(u16) ? osl_readw((osh), (volatile u16*)(r)) : \ |
417 | osl_readl((osh), (volatile uint32*)(r)) \ | 417 | osl_readl((osh), (volatile uint32*)(r)) \ |
418 | ) | 418 | ) |
419 | #define RPC_WRITE_REG(osh, r, v) do { \ | 419 | #define RPC_WRITE_REG(osh, r, v) do { \ |
@@ -421,8 +421,8 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt) | |||
421 | case sizeof(u8): \ | 421 | case sizeof(u8): \ |
422 | osl_writeb((osh), (volatile u8*)(r), (u8)(v)); \ | 422 | osl_writeb((osh), (volatile u8*)(r), (u8)(v)); \ |
423 | break; \ | 423 | break; \ |
424 | case sizeof(uint16): \ | 424 | case sizeof(u16): \ |
425 | osl_writew((osh), (volatile uint16*)(r), (uint16)(v)); \ | 425 | osl_writew((osh), (volatile u16*)(r), (u16)(v)); \ |
426 | break; \ | 426 | break; \ |
427 | case sizeof(uint32): \ | 427 | case sizeof(uint32): \ |
428 | osl_writel((osh), (volatile uint32*)(r), (uint32)(v)); \ | 428 | osl_writel((osh), (volatile uint32*)(r), (uint32)(v)); \ |
@@ -431,10 +431,10 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt) | |||
431 | } while (0) | 431 | } while (0) |
432 | 432 | ||
433 | extern u8 osl_readb(osl_t *osh, volatile u8 *r); | 433 | extern u8 osl_readb(osl_t *osh, volatile u8 *r); |
434 | extern uint16 osl_readw(osl_t *osh, volatile uint16 *r); | 434 | extern u16 osl_readw(osl_t *osh, volatile u16 *r); |
435 | extern uint32 osl_readl(osl_t *osh, volatile uint32 *r); | 435 | extern uint32 osl_readl(osl_t *osh, volatile uint32 *r); |
436 | extern void osl_writeb(osl_t *osh, volatile u8 *r, u8 v); | 436 | extern void osl_writeb(osl_t *osh, volatile u8 *r, u8 v); |
437 | extern void osl_writew(osl_t *osh, volatile uint16 *r, uint16 v); | 437 | extern void osl_writew(osl_t *osh, volatile u16 *r, u16 v); |
438 | extern void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v); | 438 | extern void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v); |
439 | #endif /* BCMSDIO */ | 439 | #endif /* BCMSDIO */ |
440 | 440 | ||
diff --git a/drivers/staging/brcm80211/include/msgtrace.h b/drivers/staging/brcm80211/include/msgtrace.h index 5a3ad909181..f88c7b60da5 100644 --- a/drivers/staging/brcm80211/include/msgtrace.h +++ b/drivers/staging/brcm80211/include/msgtrace.h | |||
@@ -28,7 +28,7 @@ | |||
28 | typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr { | 28 | typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr { |
29 | u8 version; | 29 | u8 version; |
30 | u8 spare; | 30 | u8 spare; |
31 | uint16 len; /* Len of the trace */ | 31 | u16 len; /* Len of the trace */ |
32 | uint32 seqnum; /* Sequence number of message. Useful | 32 | uint32 seqnum; /* Sequence number of message. Useful |
33 | * if the messsage has been lost | 33 | * if the messsage has been lost |
34 | * because of DMA error or a bus reset | 34 | * because of DMA error or a bus reset |
@@ -55,8 +55,8 @@ typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr { | |||
55 | extern bool msgtrace_hbus_trace; | 55 | extern bool msgtrace_hbus_trace; |
56 | 56 | ||
57 | typedef void (*msgtrace_func_send_t) (void *hdl1, void *hdl2, u8 *hdr, | 57 | typedef void (*msgtrace_func_send_t) (void *hdl1, void *hdl2, u8 *hdr, |
58 | uint16 hdrlen, u8 *buf, | 58 | u16 hdrlen, u8 *buf, |
59 | uint16 buflen); | 59 | u16 buflen); |
60 | 60 | ||
61 | extern void msgtrace_sent(void); | 61 | extern void msgtrace_sent(void); |
62 | extern void msgtrace_put(char *buf, int count); | 62 | extern void msgtrace_put(char *buf, int count); |
diff --git a/drivers/staging/brcm80211/include/pci_core.h b/drivers/staging/brcm80211/include/pci_core.h index d0fe4c3ffa8..abd8e88ac0d 100644 --- a/drivers/staging/brcm80211/include/pci_core.h +++ b/drivers/staging/brcm80211/include/pci_core.h | |||
@@ -50,7 +50,7 @@ typedef struct sbpciregs { | |||
50 | uint32 sbtopci2; /* Sonics to PCI translation 2 */ | 50 | uint32 sbtopci2; /* Sonics to PCI translation 2 */ |
51 | uint32 PAD[189]; | 51 | uint32 PAD[189]; |
52 | uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ | 52 | uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ |
53 | uint16 sprom[36]; /* SPROM shadow Area */ | 53 | u16 sprom[36]; /* SPROM shadow Area */ |
54 | uint32 PAD[46]; | 54 | uint32 PAD[46]; |
55 | } sbpciregs_t; | 55 | } sbpciregs_t; |
56 | 56 | ||
diff --git a/drivers/staging/brcm80211/include/pcicfg.h b/drivers/staging/brcm80211/include/pcicfg.h index 3c353ba9e8b..abfc82cc0d9 100644 --- a/drivers/staging/brcm80211/include/pcicfg.h +++ b/drivers/staging/brcm80211/include/pcicfg.h | |||
@@ -103,10 +103,10 @@ | |||
103 | #define PCI_CAPPTR_PRESENT 0x0010 | 103 | #define PCI_CAPPTR_PRESENT 0x0010 |
104 | 104 | ||
105 | typedef struct _pci_config_regs { | 105 | typedef struct _pci_config_regs { |
106 | uint16 vendor; | 106 | u16 vendor; |
107 | uint16 device; | 107 | u16 device; |
108 | uint16 command; | 108 | u16 command; |
109 | uint16 status; | 109 | u16 status; |
110 | u8 rev_id; | 110 | u8 rev_id; |
111 | u8 prog_if; | 111 | u8 prog_if; |
112 | u8 sub_class; | 112 | u8 sub_class; |
@@ -117,8 +117,8 @@ typedef struct _pci_config_regs { | |||
117 | u8 bist; | 117 | u8 bist; |
118 | uint32 base[PCI_BAR_MAX]; | 118 | uint32 base[PCI_BAR_MAX]; |
119 | uint32 cardbus_cis; | 119 | uint32 cardbus_cis; |
120 | uint16 subsys_vendor; | 120 | u16 subsys_vendor; |
121 | uint16 subsys_id; | 121 | u16 subsys_id; |
122 | uint32 baserom; | 122 | uint32 baserom; |
123 | uint32 rsvd_a[PCR_RSVDA_MAX]; | 123 | uint32 rsvd_a[PCR_RSVDA_MAX]; |
124 | u8 int_line; | 124 | u8 int_line; |
@@ -331,10 +331,10 @@ typedef enum { | |||
331 | #define PPB_RSVDD_MAX 8 | 331 | #define PPB_RSVDD_MAX 8 |
332 | 332 | ||
333 | typedef struct _ppb_config_regs { | 333 | typedef struct _ppb_config_regs { |
334 | uint16 vendor; | 334 | u16 vendor; |
335 | uint16 device; | 335 | u16 device; |
336 | uint16 command; | 336 | u16 command; |
337 | uint16 status; | 337 | u16 status; |
338 | u8 rev_id; | 338 | u8 rev_id; |
339 | u8 prog_if; | 339 | u8 prog_if; |
340 | u8 sub_class; | 340 | u8 sub_class; |
@@ -350,24 +350,24 @@ typedef struct _ppb_config_regs { | |||
350 | u8 sec_lat; | 350 | u8 sec_lat; |
351 | u8 io_base; | 351 | u8 io_base; |
352 | u8 io_lim; | 352 | u8 io_lim; |
353 | uint16 sec_status; | 353 | u16 sec_status; |
354 | uint16 mem_base; | 354 | u16 mem_base; |
355 | uint16 mem_lim; | 355 | u16 mem_lim; |
356 | uint16 pf_mem_base; | 356 | u16 pf_mem_base; |
357 | uint16 pf_mem_lim; | 357 | u16 pf_mem_lim; |
358 | uint32 pf_mem_base_hi; | 358 | uint32 pf_mem_base_hi; |
359 | uint32 pf_mem_lim_hi; | 359 | uint32 pf_mem_lim_hi; |
360 | uint16 io_base_hi; | 360 | u16 io_base_hi; |
361 | uint16 io_lim_hi; | 361 | u16 io_lim_hi; |
362 | uint16 subsys_vendor; | 362 | u16 subsys_vendor; |
363 | uint16 subsys_id; | 363 | u16 subsys_id; |
364 | uint32 rsvd_b; | 364 | uint32 rsvd_b; |
365 | u8 rsvd_c; | 365 | u8 rsvd_c; |
366 | u8 int_pin; | 366 | u8 int_pin; |
367 | uint16 bridge_ctrl; | 367 | u16 bridge_ctrl; |
368 | u8 chip_ctrl; | 368 | u8 chip_ctrl; |
369 | u8 diag_ctrl; | 369 | u8 diag_ctrl; |
370 | uint16 arb_ctrl; | 370 | u16 arb_ctrl; |
371 | uint32 rsvd_d[PPB_RSVDD_MAX]; | 371 | uint32 rsvd_d[PPB_RSVDD_MAX]; |
372 | u8 dev_dep[192]; | 372 | u8 dev_dep[192]; |
373 | } ppb_config_regs; | 373 | } ppb_config_regs; |
@@ -384,7 +384,7 @@ typedef struct _ppb_config_regs { | |||
384 | typedef struct _pciconfig_cap_msi { | 384 | typedef struct _pciconfig_cap_msi { |
385 | u8 capID; | 385 | u8 capID; |
386 | u8 nextptr; | 386 | u8 nextptr; |
387 | uint16 msgctrl; | 387 | u16 msgctrl; |
388 | uint32 msgaddr; | 388 | uint32 msgaddr; |
389 | } pciconfig_cap_msi; | 389 | } pciconfig_cap_msi; |
390 | 390 | ||
@@ -394,8 +394,8 @@ typedef struct _pciconfig_cap_msi { | |||
394 | typedef struct _pciconfig_cap_pwrmgmt { | 394 | typedef struct _pciconfig_cap_pwrmgmt { |
395 | u8 capID; | 395 | u8 capID; |
396 | u8 nextptr; | 396 | u8 nextptr; |
397 | uint16 pme_cap; | 397 | u16 pme_cap; |
398 | uint16 pme_sts_ctrl; | 398 | u16 pme_sts_ctrl; |
399 | u8 pme_bridge_ext; | 399 | u8 pme_bridge_ext; |
400 | u8 data; | 400 | u8 data; |
401 | } pciconfig_cap_pwrmgmt; | 401 | } pciconfig_cap_pwrmgmt; |
@@ -409,18 +409,18 @@ typedef struct _pciconfig_cap_pwrmgmt { | |||
409 | typedef struct _pciconfig_cap_pcie { | 409 | typedef struct _pciconfig_cap_pcie { |
410 | u8 capID; | 410 | u8 capID; |
411 | u8 nextptr; | 411 | u8 nextptr; |
412 | uint16 pcie_cap; | 412 | u16 pcie_cap; |
413 | uint32 dev_cap; | 413 | uint32 dev_cap; |
414 | uint16 dev_ctrl; | 414 | u16 dev_ctrl; |
415 | uint16 dev_status; | 415 | u16 dev_status; |
416 | uint32 link_cap; | 416 | uint32 link_cap; |
417 | uint16 link_ctrl; | 417 | u16 link_ctrl; |
418 | uint16 link_status; | 418 | u16 link_status; |
419 | uint32 slot_cap; | 419 | uint32 slot_cap; |
420 | uint16 slot_ctrl; | 420 | u16 slot_ctrl; |
421 | uint16 slot_status; | 421 | u16 slot_status; |
422 | uint16 root_ctrl; | 422 | u16 root_ctrl; |
423 | uint16 root_cap; | 423 | u16 root_cap; |
424 | uint32 root_status; | 424 | uint32 root_status; |
425 | } pciconfig_cap_pcie; | 425 | } pciconfig_cap_pcie; |
426 | 426 | ||
@@ -453,9 +453,9 @@ typedef struct _pciconfig_cap_pcie { | |||
453 | 453 | ||
454 | /* Header to define the PCIE specific capabilities in the extended config space */ | 454 | /* Header to define the PCIE specific capabilities in the extended config space */ |
455 | typedef struct _pcie_enhanced_caphdr { | 455 | typedef struct _pcie_enhanced_caphdr { |
456 | uint16 capID; | 456 | u16 capID; |
457 | uint16 cap_ver:4; | 457 | u16 cap_ver:4; |
458 | uint16 next_ptr:12; | 458 | u16 next_ptr:12; |
459 | } pcie_enhanced_caphdr; | 459 | } pcie_enhanced_caphdr; |
460 | 460 | ||
461 | /* Everything below is BRCM HND proprietary */ | 461 | /* Everything below is BRCM HND proprietary */ |
diff --git a/drivers/staging/brcm80211/include/pcie_core.h b/drivers/staging/brcm80211/include/pcie_core.h index 0f835c15821..9dcd6a00e91 100644 --- a/drivers/staging/brcm80211/include/pcie_core.h +++ b/drivers/staging/brcm80211/include/pcie_core.h | |||
@@ -76,7 +76,7 @@ typedef struct sbpcieregs { | |||
76 | uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ | 76 | uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ |
77 | uint32 PAD[177]; | 77 | uint32 PAD[177]; |
78 | uint32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */ | 78 | uint32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */ |
79 | uint16 sprom[64]; /* SPROM shadow Area */ | 79 | u16 sprom[64]; /* SPROM shadow Area */ |
80 | } sbpcieregs_t; | 80 | } sbpcieregs_t; |
81 | 81 | ||
82 | /* PCI control */ | 82 | /* PCI control */ |
diff --git a/drivers/staging/brcm80211/include/proto/802.11.h b/drivers/staging/brcm80211/include/proto/802.11.h index f2127ab2203..8358d064a63 100644 --- a/drivers/staging/brcm80211/include/proto/802.11.h +++ b/drivers/staging/brcm80211/include/proto/802.11.h | |||
@@ -47,18 +47,18 @@ | |||
47 | #define DOT11_OUI_LEN 3 | 47 | #define DOT11_OUI_LEN 3 |
48 | 48 | ||
49 | BWL_PRE_PACKED_STRUCT struct dot11_header { | 49 | BWL_PRE_PACKED_STRUCT struct dot11_header { |
50 | uint16 fc; | 50 | u16 fc; |
51 | uint16 durid; | 51 | u16 durid; |
52 | struct ether_addr a1; | 52 | struct ether_addr a1; |
53 | struct ether_addr a2; | 53 | struct ether_addr a2; |
54 | struct ether_addr a3; | 54 | struct ether_addr a3; |
55 | uint16 seq; | 55 | u16 seq; |
56 | struct ether_addr a4; | 56 | struct ether_addr a4; |
57 | } BWL_POST_PACKED_STRUCT; | 57 | } BWL_POST_PACKED_STRUCT; |
58 | 58 | ||
59 | BWL_PRE_PACKED_STRUCT struct dot11_rts_frame { | 59 | BWL_PRE_PACKED_STRUCT struct dot11_rts_frame { |
60 | uint16 fc; | 60 | u16 fc; |
61 | uint16 durid; | 61 | u16 durid; |
62 | struct ether_addr ra; | 62 | struct ether_addr ra; |
63 | struct ether_addr ta; | 63 | struct ether_addr ta; |
64 | } BWL_POST_PACKED_STRUCT; | 64 | } BWL_POST_PACKED_STRUCT; |
@@ -71,19 +71,19 @@ BWL_PRE_PACKED_STRUCT struct dot11_rts_frame { | |||
71 | #define DOT11_BA_LEN 4 | 71 | #define DOT11_BA_LEN 4 |
72 | 72 | ||
73 | BWL_PRE_PACKED_STRUCT struct dot11_management_header { | 73 | BWL_PRE_PACKED_STRUCT struct dot11_management_header { |
74 | uint16 fc; | 74 | u16 fc; |
75 | uint16 durid; | 75 | u16 durid; |
76 | struct ether_addr da; | 76 | struct ether_addr da; |
77 | struct ether_addr sa; | 77 | struct ether_addr sa; |
78 | struct ether_addr bssid; | 78 | struct ether_addr bssid; |
79 | uint16 seq; | 79 | u16 seq; |
80 | } BWL_POST_PACKED_STRUCT; | 80 | } BWL_POST_PACKED_STRUCT; |
81 | #define DOT11_MGMT_HDR_LEN 24 | 81 | #define DOT11_MGMT_HDR_LEN 24 |
82 | 82 | ||
83 | BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb { | 83 | BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb { |
84 | uint32 timestamp[2]; | 84 | uint32 timestamp[2]; |
85 | uint16 beacon_interval; | 85 | u16 beacon_interval; |
86 | uint16 capability; | 86 | u16 capability; |
87 | } BWL_POST_PACKED_STRUCT; | 87 | } BWL_POST_PACKED_STRUCT; |
88 | #define DOT11_BCN_PRB_LEN 12 | 88 | #define DOT11_BCN_PRB_LEN 12 |
89 | 89 | ||
@@ -106,7 +106,7 @@ typedef u8 ac_bitmap_t; | |||
106 | BWL_PRE_PACKED_STRUCT struct edcf_acparam { | 106 | BWL_PRE_PACKED_STRUCT struct edcf_acparam { |
107 | u8 ACI; | 107 | u8 ACI; |
108 | u8 ECW; | 108 | u8 ECW; |
109 | uint16 TXOP; | 109 | u16 TXOP; |
110 | } BWL_POST_PACKED_STRUCT; | 110 | } BWL_POST_PACKED_STRUCT; |
111 | typedef struct edcf_acparam edcf_acparam_t; | 111 | typedef struct edcf_acparam edcf_acparam_t; |
112 | 112 | ||
@@ -255,10 +255,10 @@ typedef struct d11cnt { | |||
255 | #define MCSSET_LEN 16 | 255 | #define MCSSET_LEN 16 |
256 | 256 | ||
257 | BWL_PRE_PACKED_STRUCT struct ht_cap_ie { | 257 | BWL_PRE_PACKED_STRUCT struct ht_cap_ie { |
258 | uint16 cap; | 258 | u16 cap; |
259 | u8 params; | 259 | u8 params; |
260 | u8 supp_mcs[MCSSET_LEN]; | 260 | u8 supp_mcs[MCSSET_LEN]; |
261 | uint16 ext_htcap; | 261 | u16 ext_htcap; |
262 | uint32 txbf_cap; | 262 | uint32 txbf_cap; |
263 | u8 as_cap; | 263 | u8 as_cap; |
264 | } BWL_POST_PACKED_STRUCT; | 264 | } BWL_POST_PACKED_STRUCT; |
diff --git a/drivers/staging/brcm80211/include/proto/bcmeth.h b/drivers/staging/brcm80211/include/proto/bcmeth.h index c73ab7b6597..c5da92b9ccd 100644 --- a/drivers/staging/brcm80211/include/proto/bcmeth.h +++ b/drivers/staging/brcm80211/include/proto/bcmeth.h | |||
@@ -37,11 +37,11 @@ | |||
37 | #define BCMILCP_BCM_SUBTYPEHDR_VERSION 0 | 37 | #define BCMILCP_BCM_SUBTYPEHDR_VERSION 0 |
38 | 38 | ||
39 | typedef BWL_PRE_PACKED_STRUCT struct bcmeth_hdr { | 39 | typedef BWL_PRE_PACKED_STRUCT struct bcmeth_hdr { |
40 | uint16 subtype; | 40 | u16 subtype; |
41 | uint16 length; | 41 | u16 length; |
42 | u8 version; | 42 | u8 version; |
43 | u8 oui[3]; | 43 | u8 oui[3]; |
44 | uint16 usr_subtype; | 44 | u16 usr_subtype; |
45 | } BWL_POST_PACKED_STRUCT bcmeth_hdr_t; | 45 | } BWL_POST_PACKED_STRUCT bcmeth_hdr_t; |
46 | 46 | ||
47 | #include <packed_section_end.h> | 47 | #include <packed_section_end.h> |
diff --git a/drivers/staging/brcm80211/include/proto/bcmevent.h b/drivers/staging/brcm80211/include/proto/bcmevent.h index 44d6b69f822..2a5598b6296 100644 --- a/drivers/staging/brcm80211/include/proto/bcmevent.h +++ b/drivers/staging/brcm80211/include/proto/bcmevent.h | |||
@@ -28,8 +28,8 @@ | |||
28 | #define WLC_EVENT_MSG_GROUP 0x04 | 28 | #define WLC_EVENT_MSG_GROUP 0x04 |
29 | 29 | ||
30 | typedef BWL_PRE_PACKED_STRUCT struct { | 30 | typedef BWL_PRE_PACKED_STRUCT struct { |
31 | uint16 version; | 31 | u16 version; |
32 | uint16 flags; | 32 | u16 flags; |
33 | uint32 event_type; | 33 | uint32 event_type; |
34 | uint32 status; | 34 | uint32 status; |
35 | uint32 reason; | 35 | uint32 reason; |
diff --git a/drivers/staging/brcm80211/include/proto/ethernet.h b/drivers/staging/brcm80211/include/proto/ethernet.h index 7fe957ec0ed..d208d5f606a 100644 --- a/drivers/staging/brcm80211/include/proto/ethernet.h +++ b/drivers/staging/brcm80211/include/proto/ethernet.h | |||
@@ -56,7 +56,7 @@ | |||
56 | BWL_PRE_PACKED_STRUCT struct ether_header { | 56 | BWL_PRE_PACKED_STRUCT struct ether_header { |
57 | u8 ether_dhost[ETHER_ADDR_LEN]; | 57 | u8 ether_dhost[ETHER_ADDR_LEN]; |
58 | u8 ether_shost[ETHER_ADDR_LEN]; | 58 | u8 ether_shost[ETHER_ADDR_LEN]; |
59 | uint16 ether_type; | 59 | u16 ether_type; |
60 | } BWL_POST_PACKED_STRUCT; | 60 | } BWL_POST_PACKED_STRUCT; |
61 | 61 | ||
62 | BWL_PRE_PACKED_STRUCT struct ether_addr { | 62 | BWL_PRE_PACKED_STRUCT struct ether_addr { |
diff --git a/drivers/staging/brcm80211/include/proto/vlan.h b/drivers/staging/brcm80211/include/proto/vlan.h index e8a17a158f2..9e1f17836ae 100644 --- a/drivers/staging/brcm80211/include/proto/vlan.h +++ b/drivers/staging/brcm80211/include/proto/vlan.h | |||
@@ -34,9 +34,9 @@ | |||
34 | struct ethervlan_header { | 34 | struct ethervlan_header { |
35 | u8 ether_dhost[ETHER_ADDR_LEN]; | 35 | u8 ether_dhost[ETHER_ADDR_LEN]; |
36 | u8 ether_shost[ETHER_ADDR_LEN]; | 36 | u8 ether_shost[ETHER_ADDR_LEN]; |
37 | uint16 vlan_type; | 37 | u16 vlan_type; |
38 | uint16 vlan_tag; | 38 | u16 vlan_tag; |
39 | uint16 ether_type; | 39 | u16 ether_type; |
40 | }; | 40 | }; |
41 | 41 | ||
42 | #define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN) | 42 | #define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN) |
diff --git a/drivers/staging/brcm80211/include/qmath.h b/drivers/staging/brcm80211/include/qmath.h index ec43121c8eb..471746d2430 100644 --- a/drivers/staging/brcm80211/include/qmath.h +++ b/drivers/staging/brcm80211/include/qmath.h | |||
@@ -27,7 +27,7 @@ int16 qm_mul16(int16 op1, int16 op2); | |||
27 | 27 | ||
28 | int32 qm_muls321616(int16 op1, int16 op2); | 28 | int32 qm_muls321616(int16 op1, int16 op2); |
29 | 29 | ||
30 | uint16 qm_mulu16(uint16 op1, uint16 op2); | 30 | u16 qm_mulu16(u16 op1, u16 op2); |
31 | 31 | ||
32 | int16 qm_muls16(int16 op1, int16 op2); | 32 | int16 qm_muls16(int16 op1, int16 op2); |
33 | 33 | ||
@@ -65,7 +65,7 @@ int16 qm_div163232(int32 num, int32 denom, int16 *qquotient); | |||
65 | 65 | ||
66 | int32 qm_mul323216(int32 op1, int16 op2); | 66 | int32 qm_mul323216(int32 op1, int16 op2); |
67 | 67 | ||
68 | int32 qm_mulsu321616(int16 op1, uint16 op2); | 68 | int32 qm_mulsu321616(int16 op1, u16 op2); |
69 | 69 | ||
70 | int32 qm_muls323216(int32 op1, int16 op2); | 70 | int32 qm_muls323216(int32 op1, int16 op2); |
71 | 71 | ||
diff --git a/drivers/staging/brcm80211/include/sbchipc.h b/drivers/staging/brcm80211/include/sbchipc.h index 4c8fe9e03ef..6a63b65fc72 100644 --- a/drivers/staging/brcm80211/include/sbchipc.h +++ b/drivers/staging/brcm80211/include/sbchipc.h | |||
@@ -220,7 +220,7 @@ typedef volatile struct { | |||
220 | uint32 pmustrapopt; /* 0x668, corerev >= 28 */ | 220 | uint32 pmustrapopt; /* 0x668, corerev >= 28 */ |
221 | uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ | 221 | uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ |
222 | uint32 PAD[100]; | 222 | uint32 PAD[100]; |
223 | uint16 sromotp[768]; | 223 | u16 sromotp[768]; |
224 | } chipcregs_t; | 224 | } chipcregs_t; |
225 | 225 | ||
226 | #endif /* _LANGUAGE_ASSEMBLY */ | 226 | #endif /* _LANGUAGE_ASSEMBLY */ |
diff --git a/drivers/staging/brcm80211/include/sbhnddma.h b/drivers/staging/brcm80211/include/sbhnddma.h index 598d68b7f88..34e78fad515 100644 --- a/drivers/staging/brcm80211/include/sbhnddma.h +++ b/drivers/staging/brcm80211/include/sbhnddma.h | |||
@@ -308,8 +308,8 @@ typedef volatile struct { | |||
308 | 308 | ||
309 | /* receive frame status */ | 309 | /* receive frame status */ |
310 | typedef volatile struct { | 310 | typedef volatile struct { |
311 | uint16 len; | 311 | u16 len; |
312 | uint16 flags; | 312 | u16 flags; |
313 | } dma_rxh_t; | 313 | } dma_rxh_t; |
314 | 314 | ||
315 | #endif /* _sbhnddma_h_ */ | 315 | #endif /* _sbhnddma_h_ */ |
diff --git a/drivers/staging/brcm80211/include/sbhndpio.h b/drivers/staging/brcm80211/include/sbhndpio.h index e64f6aaef3c..a73367c051d 100644 --- a/drivers/staging/brcm80211/include/sbhndpio.h +++ b/drivers/staging/brcm80211/include/sbhndpio.h | |||
@@ -25,10 +25,10 @@ | |||
25 | 25 | ||
26 | /* 2byte-wide pio register set per channel(xmt or rcv) */ | 26 | /* 2byte-wide pio register set per channel(xmt or rcv) */ |
27 | typedef volatile struct { | 27 | typedef volatile struct { |
28 | uint16 fifocontrol; | 28 | u16 fifocontrol; |
29 | uint16 fifodata; | 29 | u16 fifodata; |
30 | uint16 fifofree; /* only valid in xmt channel, not in rcv channel */ | 30 | u16 fifofree; /* only valid in xmt channel, not in rcv channel */ |
31 | uint16 PAD; | 31 | u16 PAD; |
32 | } pio2regs_t; | 32 | } pio2regs_t; |
33 | 33 | ||
34 | /* a pair of pio channels(tx and rx) */ | 34 | /* a pair of pio channels(tx and rx) */ |
diff --git a/drivers/staging/brcm80211/include/sbsdpcmdev.h b/drivers/staging/brcm80211/include/sbsdpcmdev.h index b29d38148fa..ac68e150c88 100644 --- a/drivers/staging/brcm80211/include/sbsdpcmdev.h +++ b/drivers/staging/brcm80211/include/sbsdpcmdev.h | |||
@@ -60,14 +60,14 @@ typedef volatile struct { | |||
60 | uint32 biststatus; /* BistStatus, 0x00c, rev8 */ | 60 | uint32 biststatus; /* BistStatus, 0x00c, rev8 */ |
61 | 61 | ||
62 | /* PCMCIA access */ | 62 | /* PCMCIA access */ |
63 | uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ | 63 | u16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ |
64 | uint16 PAD[1]; | 64 | u16 PAD[1]; |
65 | uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */ | 65 | u16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */ |
66 | uint16 PAD[1]; | 66 | u16 PAD[1]; |
67 | uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */ | 67 | u16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */ |
68 | uint16 PAD[1]; | 68 | u16 PAD[1]; |
69 | uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */ | 69 | u16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */ |
70 | uint16 PAD[1]; | 70 | u16 PAD[1]; |
71 | 71 | ||
72 | /* interrupt */ | 72 | /* interrupt */ |
73 | uint32 intstatus; /* IntStatus, 0x020, rev8 */ | 73 | uint32 intstatus; /* IntStatus, 0x020, rev8 */ |
@@ -125,22 +125,22 @@ typedef volatile struct { | |||
125 | 125 | ||
126 | /* PCMCIA function control registers */ | 126 | /* PCMCIA function control registers */ |
127 | char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */ | 127 | char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */ |
128 | uint16 PAD[55]; | 128 | u16 PAD[55]; |
129 | 129 | ||
130 | /* PCMCIA backplane access */ | 130 | /* PCMCIA backplane access */ |
131 | uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */ | 131 | u16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */ |
132 | uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */ | 132 | u16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */ |
133 | uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */ | 133 | u16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */ |
134 | uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */ | 134 | u16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */ |
135 | uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */ | 135 | u16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */ |
136 | uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */ | 136 | u16 backplanedata0; /* BackplaneData0, 0x778, rev6 */ |
137 | uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */ | 137 | u16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */ |
138 | uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */ | 138 | u16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */ |
139 | uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */ | 139 | u16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */ |
140 | uint16 PAD[31]; | 140 | u16 PAD[31]; |
141 | 141 | ||
142 | /* sprom "size" & "blank" info */ | 142 | /* sprom "size" & "blank" info */ |
143 | uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ | 143 | u16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ |
144 | uint32 PAD[464]; | 144 | uint32 PAD[464]; |
145 | 145 | ||
146 | /* Sonics SiliconBackplane registers */ | 146 | /* Sonics SiliconBackplane registers */ |
@@ -264,8 +264,8 @@ typedef volatile struct { | |||
264 | 264 | ||
265 | /* rx header */ | 265 | /* rx header */ |
266 | typedef volatile struct { | 266 | typedef volatile struct { |
267 | uint16 len; | 267 | u16 len; |
268 | uint16 flags; | 268 | u16 flags; |
269 | } sdpcmd_rxh_t; | 269 | } sdpcmd_rxh_t; |
270 | 270 | ||
271 | /* rx header flags */ | 271 | /* rx header flags */ |
diff --git a/drivers/staging/brcm80211/include/siutils.h b/drivers/staging/brcm80211/include/siutils.h index 7283261f746..713cf0176af 100644 --- a/drivers/staging/brcm80211/include/siutils.h +++ b/drivers/staging/brcm80211/include/siutils.h | |||
@@ -178,7 +178,7 @@ extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, | |||
178 | void *intrsenabled_fn, void *intr_arg); | 178 | void *intrsenabled_fn, void *intr_arg); |
179 | extern void si_deregister_intr_callback(si_t *sih); | 179 | extern void si_deregister_intr_callback(si_t *sih); |
180 | extern void si_clkctl_init(si_t *sih); | 180 | extern void si_clkctl_init(si_t *sih); |
181 | extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih); | 181 | extern u16 si_clkctl_fast_pwrup_delay(si_t *sih); |
182 | extern bool si_clkctl_cc(si_t *sih, uint mode); | 182 | extern bool si_clkctl_cc(si_t *sih, uint mode); |
183 | extern int si_clkctl_xtal(si_t *sih, uint what, bool on); | 183 | extern int si_clkctl_xtal(si_t *sih, uint what, bool on); |
184 | extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val); | 184 | extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val); |
@@ -227,7 +227,7 @@ extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset); | |||
227 | extern void si_sdio_init(si_t *sih); | 227 | extern void si_sdio_init(si_t *sih); |
228 | #endif | 228 | #endif |
229 | 229 | ||
230 | extern uint16 si_d11_devid(si_t *sih); | 230 | extern u16 si_d11_devid(si_t *sih); |
231 | 231 | ||
232 | #define si_eci(sih) 0 | 232 | #define si_eci(sih) 0 |
233 | #define si_eci_init(sih) (0) | 233 | #define si_eci_init(sih) (0) |
diff --git a/drivers/staging/brcm80211/include/spid.h b/drivers/staging/brcm80211/include/spid.h index 935c6f8f8fd..45932be07c1 100644 --- a/drivers/staging/brcm80211/include/spid.h +++ b/drivers/staging/brcm80211/include/spid.h | |||
@@ -29,12 +29,12 @@ typedef volatile struct { | |||
29 | * function selection, command/data error check | 29 | * function selection, command/data error check |
30 | */ | 30 | */ |
31 | u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */ | 31 | u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */ |
32 | uint16 intr_reg; /* 0x04, Intr status register */ | 32 | u16 intr_reg; /* 0x04, Intr status register */ |
33 | uint16 intr_en_reg; /* 0x06, Intr mask register */ | 33 | u16 intr_en_reg; /* 0x06, Intr mask register */ |
34 | uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */ | 34 | uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */ |
35 | uint16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */ | 35 | u16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */ |
36 | uint16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */ | 36 | u16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */ |
37 | uint16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */ | 37 | u16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */ |
38 | uint32 test_read; /* 0x14, RO 0xfeedbead signature */ | 38 | uint32 test_read; /* 0x14, RO 0xfeedbead signature */ |
39 | uint32 test_rw; /* 0x18, RW */ | 39 | uint32 test_rw; /* 0x18, RW */ |
40 | u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */ | 40 | u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */ |
diff --git a/drivers/staging/brcm80211/include/typedefs.h b/drivers/staging/brcm80211/include/typedefs.h index a6ab298c4d3..3a72ce33c20 100644 --- a/drivers/staging/brcm80211/include/typedefs.h +++ b/drivers/staging/brcm80211/include/typedefs.h | |||
@@ -44,10 +44,6 @@ typedef unsigned int uint; | |||
44 | 44 | ||
45 | /* define [u]int16/32/64, uintptr */ | 45 | /* define [u]int16/32/64, uintptr */ |
46 | 46 | ||
47 | #ifndef TYPEDEF_UINT16 | ||
48 | typedef unsigned short uint16; | ||
49 | #endif | ||
50 | |||
51 | #ifndef TYPEDEF_UINT32 | 47 | #ifndef TYPEDEF_UINT32 |
52 | typedef unsigned int uint32; | 48 | typedef unsigned int uint32; |
53 | #endif | 49 | #endif |
@@ -85,7 +81,6 @@ typedef signed int int32; | |||
85 | #define AUTO (-1) /* Auto = -1 */ | 81 | #define AUTO (-1) /* Auto = -1 */ |
86 | 82 | ||
87 | #undef TYPEDEF_UINT | 83 | #undef TYPEDEF_UINT |
88 | #undef TYPEDEF_UINT16 | ||
89 | #undef TYPEDEF_UINT32 | 84 | #undef TYPEDEF_UINT32 |
90 | #undef TYPEDEF_UINTPTR | 85 | #undef TYPEDEF_UINTPTR |
91 | #undef TYPEDEF_INT16 | 86 | #undef TYPEDEF_INT16 |
diff --git a/drivers/staging/brcm80211/include/wlioctl.h b/drivers/staging/brcm80211/include/wlioctl.h index 8216fe2b177..0f60628580f 100644 --- a/drivers/staging/brcm80211/include/wlioctl.h +++ b/drivers/staging/brcm80211/include/wlioctl.h | |||
@@ -44,8 +44,8 @@ typedef struct wl_bss_info_107 { | |||
44 | * starting at version and including IEs | 44 | * starting at version and including IEs |
45 | */ | 45 | */ |
46 | struct ether_addr BSSID; | 46 | struct ether_addr BSSID; |
47 | uint16 beacon_period; /* units are Kusec */ | 47 | u16 beacon_period; /* units are Kusec */ |
48 | uint16 capability; /* Capability information */ | 48 | u16 capability; /* Capability information */ |
49 | u8 SSID_len; | 49 | u8 SSID_len; |
50 | u8 SSID[32]; | 50 | u8 SSID[32]; |
51 | struct { | 51 | struct { |
@@ -53,7 +53,7 @@ typedef struct wl_bss_info_107 { | |||
53 | u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */ | 53 | u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */ |
54 | } rateset; /* supported rates */ | 54 | } rateset; /* supported rates */ |
55 | u8 channel; /* Channel no. */ | 55 | u8 channel; /* Channel no. */ |
56 | uint16 atim_window; /* units are Kusec */ | 56 | u16 atim_window; /* units are Kusec */ |
57 | u8 dtim_period; /* DTIM period */ | 57 | u8 dtim_period; /* DTIM period */ |
58 | int16 RSSI; /* receive signal strength (in dBm) */ | 58 | int16 RSSI; /* receive signal strength (in dBm) */ |
59 | s8 phy_noise; /* noise (in dBm) */ | 59 | s8 phy_noise; /* noise (in dBm) */ |
@@ -77,8 +77,8 @@ typedef struct wl_bss_info_108 { | |||
77 | * starting at version and including IEs | 77 | * starting at version and including IEs |
78 | */ | 78 | */ |
79 | struct ether_addr BSSID; | 79 | struct ether_addr BSSID; |
80 | uint16 beacon_period; /* units are Kusec */ | 80 | u16 beacon_period; /* units are Kusec */ |
81 | uint16 capability; /* Capability information */ | 81 | u16 capability; /* Capability information */ |
82 | u8 SSID_len; | 82 | u8 SSID_len; |
83 | u8 SSID[32]; | 83 | u8 SSID[32]; |
84 | struct { | 84 | struct { |
@@ -86,7 +86,7 @@ typedef struct wl_bss_info_108 { | |||
86 | u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */ | 86 | u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */ |
87 | } rateset; /* supported rates */ | 87 | } rateset; /* supported rates */ |
88 | chanspec_t chanspec; /* chanspec for bss */ | 88 | chanspec_t chanspec; /* chanspec for bss */ |
89 | uint16 atim_window; /* units are Kusec */ | 89 | u16 atim_window; /* units are Kusec */ |
90 | u8 dtim_period; /* DTIM period */ | 90 | u8 dtim_period; /* DTIM period */ |
91 | int16 RSSI; /* receive signal strength (in dBm) */ | 91 | int16 RSSI; /* receive signal strength (in dBm) */ |
92 | s8 phy_noise; /* noise (in dBm) */ | 92 | s8 phy_noise; /* noise (in dBm) */ |
@@ -99,7 +99,7 @@ typedef struct wl_bss_info_108 { | |||
99 | u8 reserved[3]; /* Reserved for expansion of BSS properties */ | 99 | u8 reserved[3]; /* Reserved for expansion of BSS properties */ |
100 | u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */ | 100 | u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */ |
101 | 101 | ||
102 | uint16 ie_offset; /* offset at which IEs start, from beginning */ | 102 | u16 ie_offset; /* offset at which IEs start, from beginning */ |
103 | uint32 ie_length; /* byte length of Information Elements */ | 103 | uint32 ie_length; /* byte length of Information Elements */ |
104 | /* Add new fields here */ | 104 | /* Add new fields here */ |
105 | /* variable length Information Elements */ | 105 | /* variable length Information Elements */ |
@@ -121,8 +121,8 @@ typedef struct wl_bss_info { | |||
121 | * starting at version and including IEs | 121 | * starting at version and including IEs |
122 | */ | 122 | */ |
123 | struct ether_addr BSSID; | 123 | struct ether_addr BSSID; |
124 | uint16 beacon_period; /* units are Kusec */ | 124 | u16 beacon_period; /* units are Kusec */ |
125 | uint16 capability; /* Capability information */ | 125 | u16 capability; /* Capability information */ |
126 | u8 SSID_len; | 126 | u8 SSID_len; |
127 | u8 SSID[32]; | 127 | u8 SSID[32]; |
128 | struct { | 128 | struct { |
@@ -130,7 +130,7 @@ typedef struct wl_bss_info { | |||
130 | u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */ | 130 | u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */ |
131 | } rateset; /* supported rates */ | 131 | } rateset; /* supported rates */ |
132 | chanspec_t chanspec; /* chanspec for bss */ | 132 | chanspec_t chanspec; /* chanspec for bss */ |
133 | uint16 atim_window; /* units are Kusec */ | 133 | u16 atim_window; /* units are Kusec */ |
134 | u8 dtim_period; /* DTIM period */ | 134 | u8 dtim_period; /* DTIM period */ |
135 | int16 RSSI; /* receive signal strength (in dBm) */ | 135 | int16 RSSI; /* receive signal strength (in dBm) */ |
136 | s8 phy_noise; /* noise (in dBm) */ | 136 | s8 phy_noise; /* noise (in dBm) */ |
@@ -143,7 +143,7 @@ typedef struct wl_bss_info { | |||
143 | u8 reserved[3]; /* Reserved for expansion of BSS properties */ | 143 | u8 reserved[3]; /* Reserved for expansion of BSS properties */ |
144 | u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */ | 144 | u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */ |
145 | 145 | ||
146 | uint16 ie_offset; /* offset at which IEs start, from beginning */ | 146 | u16 ie_offset; /* offset at which IEs start, from beginning */ |
147 | uint32 ie_length; /* byte length of Information Elements */ | 147 | uint32 ie_length; /* byte length of Information Elements */ |
148 | int16 SNR; /* average SNR of during frame reception */ | 148 | int16 SNR; /* average SNR of during frame reception */ |
149 | /* Add new fields here */ | 149 | /* Add new fields here */ |
@@ -229,7 +229,7 @@ typedef struct wl_scan_params { | |||
229 | * parameter portion is assumed, otherwise ssid in | 229 | * parameter portion is assumed, otherwise ssid in |
230 | * the fixed portion is ignored | 230 | * the fixed portion is ignored |
231 | */ | 231 | */ |
232 | uint16 channel_list[1]; /* list of chanspecs */ | 232 | u16 channel_list[1]; /* list of chanspecs */ |
233 | } wl_scan_params_t; | 233 | } wl_scan_params_t; |
234 | 234 | ||
235 | /* size of wl_scan_params not including variable length array */ | 235 | /* size of wl_scan_params not including variable length array */ |
@@ -248,8 +248,8 @@ typedef struct wl_scan_params { | |||
248 | /* incremental scan struct */ | 248 | /* incremental scan struct */ |
249 | typedef struct wl_iscan_params { | 249 | typedef struct wl_iscan_params { |
250 | uint32 version; | 250 | uint32 version; |
251 | uint16 action; | 251 | u16 action; |
252 | uint16 scan_duration; | 252 | u16 scan_duration; |
253 | wl_scan_params_t params; | 253 | wl_scan_params_t params; |
254 | } wl_iscan_params_t; | 254 | } wl_iscan_params_t; |
255 | 255 | ||
@@ -277,8 +277,8 @@ typedef struct wl_scan_results { | |||
277 | 277 | ||
278 | typedef struct wl_escan_params { | 278 | typedef struct wl_escan_params { |
279 | uint32 version; | 279 | uint32 version; |
280 | uint16 action; | 280 | u16 action; |
281 | uint16 sync_id; | 281 | u16 sync_id; |
282 | wl_scan_params_t params; | 282 | wl_scan_params_t params; |
283 | } wl_escan_params_t; | 283 | } wl_escan_params_t; |
284 | 284 | ||
@@ -287,8 +287,8 @@ typedef struct wl_escan_params { | |||
287 | typedef struct wl_escan_result { | 287 | typedef struct wl_escan_result { |
288 | uint32 buflen; | 288 | uint32 buflen; |
289 | uint32 version; | 289 | uint32 version; |
290 | uint16 sync_id; | 290 | u16 sync_id; |
291 | uint16 bss_count; | 291 | u16 bss_count; |
292 | wl_bss_info_t bss_info[1]; | 292 | wl_bss_info_t bss_info[1]; |
293 | } wl_escan_result_t; | 293 | } wl_escan_result_t; |
294 | 294 | ||
@@ -552,7 +552,7 @@ typedef struct wl_wsec_key { | |||
552 | /* Rx IV */ | 552 | /* Rx IV */ |
553 | struct { | 553 | struct { |
554 | uint32 hi; /* upper 32 bits of IV */ | 554 | uint32 hi; /* upper 32 bits of IV */ |
555 | uint16 lo; /* lower 16 bits of IV */ | 555 | u16 lo; /* lower 16 bits of IV */ |
556 | } rxiv; | 556 | } rxiv; |
557 | uint32 pad_5[2]; | 557 | uint32 pad_5[2]; |
558 | struct ether_addr ea; /* per station */ | 558 | struct ether_addr ea; /* per station */ |
@@ -629,7 +629,7 @@ typedef struct wl_led_info { | |||
629 | typedef struct { | 629 | typedef struct { |
630 | uint byteoff; /* byte offset */ | 630 | uint byteoff; /* byte offset */ |
631 | uint nbytes; /* number of bytes */ | 631 | uint nbytes; /* number of bytes */ |
632 | uint16 buf[1]; | 632 | u16 buf[1]; |
633 | } srom_rw_t; | 633 | } srom_rw_t; |
634 | 634 | ||
635 | /* similar cis (srom or otp) struct [iovar: may not be aligned] */ | 635 | /* similar cis (srom or otp) struct [iovar: may not be aligned] */ |
@@ -661,10 +661,10 @@ typedef struct { | |||
661 | #define WL_ATTEN_PCL_OFF 2 /* turn off PCL. */ | 661 | #define WL_ATTEN_PCL_OFF 2 /* turn off PCL. */ |
662 | 662 | ||
663 | typedef struct { | 663 | typedef struct { |
664 | uint16 auto_ctrl; /* WL_ATTEN_XX */ | 664 | u16 auto_ctrl; /* WL_ATTEN_XX */ |
665 | uint16 bb; /* Baseband attenuation */ | 665 | u16 bb; /* Baseband attenuation */ |
666 | uint16 radio; /* Radio attenuation */ | 666 | u16 radio; /* Radio attenuation */ |
667 | uint16 txctl1; /* Radio TX_CTL1 value */ | 667 | u16 txctl1; /* Radio TX_CTL1 value */ |
668 | } atten_t; | 668 | } atten_t; |
669 | 669 | ||
670 | /* Per-AC retry parameters */ | 670 | /* Per-AC retry parameters */ |
@@ -673,7 +673,7 @@ struct wme_tx_params_s { | |||
673 | u8 short_fallback; | 673 | u8 short_fallback; |
674 | u8 long_retry; | 674 | u8 long_retry; |
675 | u8 long_fallback; | 675 | u8 long_fallback; |
676 | uint16 max_rate; /* In units of 512 Kbps */ | 676 | u16 max_rate; /* In units of 512 Kbps */ |
677 | }; | 677 | }; |
678 | 678 | ||
679 | typedef struct wme_tx_params_s wme_tx_params_t; | 679 | typedef struct wme_tx_params_s wme_tx_params_t; |
@@ -701,9 +701,9 @@ typedef struct { | |||
701 | #define BCM_MAC_STATUS_INDICATION (0x40010200L) | 701 | #define BCM_MAC_STATUS_INDICATION (0x40010200L) |
702 | 702 | ||
703 | typedef struct { | 703 | typedef struct { |
704 | uint16 ver; /* version of this struct */ | 704 | u16 ver; /* version of this struct */ |
705 | uint16 len; /* length in bytes of this structure */ | 705 | u16 len; /* length in bytes of this structure */ |
706 | uint16 cap; /* sta's advertised capabilities */ | 706 | u16 cap; /* sta's advertised capabilities */ |
707 | uint32 flags; /* flags defined below */ | 707 | uint32 flags; /* flags defined below */ |
708 | uint32 idle; /* time since data pkt rx'd from sta */ | 708 | uint32 idle; /* time since data pkt rx'd from sta */ |
709 | struct ether_addr ea; /* Station address */ | 709 | struct ether_addr ea; /* Station address */ |
@@ -819,9 +819,9 @@ typedef struct wl_instance_info { | |||
819 | 819 | ||
820 | /* structure to change size of tx fifo */ | 820 | /* structure to change size of tx fifo */ |
821 | typedef struct wl_txfifo_sz { | 821 | typedef struct wl_txfifo_sz { |
822 | uint16 magic; | 822 | u16 magic; |
823 | uint16 fifo; | 823 | u16 fifo; |
824 | uint16 size; | 824 | u16 size; |
825 | } wl_txfifo_sz_t; | 825 | } wl_txfifo_sz_t; |
826 | /* magic pattern used for mismatch driver and wl */ | 826 | /* magic pattern used for mismatch driver and wl */ |
827 | #define WL_TXFIFO_SZ_MAGIC 0xa5a5 | 827 | #define WL_TXFIFO_SZ_MAGIC 0xa5a5 |
@@ -1205,11 +1205,11 @@ typedef struct wlc_iov_trx_s { | |||
1205 | #define WL_PHY_PAVARS_LEN 6 /* Phy type, Band range, chain, a1, b0, b1 */ | 1205 | #define WL_PHY_PAVARS_LEN 6 /* Phy type, Band range, chain, a1, b0, b1 */ |
1206 | 1206 | ||
1207 | typedef struct wl_po { | 1207 | typedef struct wl_po { |
1208 | uint16 phy_type; /* Phy type */ | 1208 | u16 phy_type; /* Phy type */ |
1209 | uint16 band; | 1209 | u16 band; |
1210 | uint16 cckpo; | 1210 | u16 cckpo; |
1211 | uint32 ofdmpo; | 1211 | uint32 ofdmpo; |
1212 | uint16 mcspo[8]; | 1212 | u16 mcspo[8]; |
1213 | } wl_po_t; | 1213 | } wl_po_t; |
1214 | 1214 | ||
1215 | /* a large TX Power as an init value to factor out of MIN() calculations, | 1215 | /* a large TX Power as an init value to factor out of MIN() calculations, |
@@ -1493,8 +1493,8 @@ struct tsinfo_arg { | |||
1493 | #define WL_CNT_T_VERSION 7 /* current version of wl_cnt_t struct */ | 1493 | #define WL_CNT_T_VERSION 7 /* current version of wl_cnt_t struct */ |
1494 | 1494 | ||
1495 | typedef struct { | 1495 | typedef struct { |
1496 | uint16 version; /* see definition of WL_CNT_T_VERSION */ | 1496 | u16 version; /* see definition of WL_CNT_T_VERSION */ |
1497 | uint16 length; /* length of entire structure */ | 1497 | u16 length; /* length of entire structure */ |
1498 | 1498 | ||
1499 | /* transmit stat counters */ | 1499 | /* transmit stat counters */ |
1500 | uint32 txframe; /* tx data frames */ | 1500 | uint32 txframe; /* tx data frames */ |
@@ -1727,8 +1727,8 @@ typedef struct { | |||
1727 | #define WL_DELTA_STATS_T_VERSION 1 /* current version of wl_delta_stats_t struct */ | 1727 | #define WL_DELTA_STATS_T_VERSION 1 /* current version of wl_delta_stats_t struct */ |
1728 | 1728 | ||
1729 | typedef struct { | 1729 | typedef struct { |
1730 | uint16 version; /* see definition of WL_DELTA_STATS_T_VERSION */ | 1730 | u16 version; /* see definition of WL_DELTA_STATS_T_VERSION */ |
1731 | uint16 length; /* length of entire structure */ | 1731 | u16 length; /* length of entire structure */ |
1732 | 1732 | ||
1733 | /* transmit stat counters */ | 1733 | /* transmit stat counters */ |
1734 | uint32 txframe; /* tx data frames */ | 1734 | uint32 txframe; /* tx data frames */ |
@@ -1772,8 +1772,8 @@ typedef struct { | |||
1772 | } wl_traffic_stats_t; | 1772 | } wl_traffic_stats_t; |
1773 | 1773 | ||
1774 | typedef struct { | 1774 | typedef struct { |
1775 | uint16 version; /* see definition of WL_WME_CNT_VERSION */ | 1775 | u16 version; /* see definition of WL_WME_CNT_VERSION */ |
1776 | uint16 length; /* length of entire structure */ | 1776 | u16 length; /* length of entire structure */ |
1777 | 1777 | ||
1778 | wl_traffic_stats_t tx[AC_COUNT]; /* Packets transmitted */ | 1778 | wl_traffic_stats_t tx[AC_COUNT]; /* Packets transmitted */ |
1779 | wl_traffic_stats_t tx_failed[AC_COUNT]; /* Packets dropped or failed to transmit */ | 1779 | wl_traffic_stats_t tx_failed[AC_COUNT]; /* Packets dropped or failed to transmit */ |
@@ -1797,8 +1797,8 @@ struct wl_msglevel2 { | |||
1797 | 1797 | ||
1798 | /* block ack related stats */ | 1798 | /* block ack related stats */ |
1799 | typedef struct wlc_ba_cnt { | 1799 | typedef struct wlc_ba_cnt { |
1800 | uint16 version; /* WLC_BA_CNT_VERSION */ | 1800 | u16 version; /* WLC_BA_CNT_VERSION */ |
1801 | uint16 length; /* length of entire structure */ | 1801 | u16 length; /* length of entire structure */ |
1802 | 1802 | ||
1803 | /* transmit stat counters */ | 1803 | /* transmit stat counters */ |
1804 | uint32 txpdu; /* pdus sent */ | 1804 | uint32 txpdu; /* pdus sent */ |
@@ -1858,13 +1858,13 @@ struct tslist { | |||
1858 | 1858 | ||
1859 | /* structure for addts/delts arguments */ | 1859 | /* structure for addts/delts arguments */ |
1860 | typedef struct tspec_arg { | 1860 | typedef struct tspec_arg { |
1861 | uint16 version; /* see definition of TSPEC_ARG_VERSION */ | 1861 | u16 version; /* see definition of TSPEC_ARG_VERSION */ |
1862 | uint16 length; /* length of entire structure */ | 1862 | u16 length; /* length of entire structure */ |
1863 | uint flag; /* bit field */ | 1863 | uint flag; /* bit field */ |
1864 | /* TSPEC Arguments */ | 1864 | /* TSPEC Arguments */ |
1865 | struct tsinfo_arg tsinfo; /* TS Info bit field */ | 1865 | struct tsinfo_arg tsinfo; /* TS Info bit field */ |
1866 | uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */ | 1866 | u16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */ |
1867 | uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */ | 1867 | u16 max_msdu_size; /* Maximum MSDU Size (bytes) */ |
1868 | uint min_srv_interval; /* Minimum Service Interval (us) */ | 1868 | uint min_srv_interval; /* Minimum Service Interval (us) */ |
1869 | uint max_srv_interval; /* Maximum Service Interval (us) */ | 1869 | uint max_srv_interval; /* Maximum Service Interval (us) */ |
1870 | uint inactivity_interval; /* Inactivity Interval (us) */ | 1870 | uint inactivity_interval; /* Inactivity Interval (us) */ |
@@ -1876,8 +1876,8 @@ typedef struct tspec_arg { | |||
1876 | uint max_burst_size; /* Maximum Burst Size (bytes) */ | 1876 | uint max_burst_size; /* Maximum Burst Size (bytes) */ |
1877 | uint delay_bound; /* Delay Bound (us) */ | 1877 | uint delay_bound; /* Delay Bound (us) */ |
1878 | uint min_phy_rate; /* Minimum PHY Rate (bps) */ | 1878 | uint min_phy_rate; /* Minimum PHY Rate (bps) */ |
1879 | uint16 surplus_bw; /* Surplus Bandwidth Allowance (range 1.0 to 8.0) */ | 1879 | u16 surplus_bw; /* Surplus Bandwidth Allowance (range 1.0 to 8.0) */ |
1880 | uint16 medium_time; /* Medium Time (32 us/s periods) */ | 1880 | u16 medium_time; /* Medium Time (32 us/s periods) */ |
1881 | u8 dialog_token; /* dialog token */ | 1881 | u8 dialog_token; /* dialog token */ |
1882 | } tspec_arg_t; | 1882 | } tspec_arg_t; |
1883 | 1883 | ||
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_cmn.c b/drivers/staging/brcm80211/phy/wlc_phy_cmn.c index 4b315b9ea72..ed0ebd4bbfe 100644 --- a/drivers/staging/brcm80211/phy/wlc_phy_cmn.c +++ b/drivers/staging/brcm80211/phy/wlc_phy_cmn.c | |||
@@ -33,8 +33,8 @@ | |||
33 | uint32 phyhal_msg_level = PHYHAL_ERROR; | 33 | uint32 phyhal_msg_level = PHYHAL_ERROR; |
34 | 34 | ||
35 | typedef struct _chan_info_basic { | 35 | typedef struct _chan_info_basic { |
36 | uint16 chan; | 36 | u16 chan; |
37 | uint16 freq; | 37 | u16 freq; |
38 | } chan_info_basic_t; | 38 | } chan_info_basic_t; |
39 | 39 | ||
40 | static chan_info_basic_t chan_info_all[] = { | 40 | static chan_info_basic_t chan_info_all[] = { |
@@ -97,7 +97,7 @@ static chan_info_basic_t chan_info_all[] = { | |||
97 | {216, 50800} | 97 | {216, 50800} |
98 | }; | 98 | }; |
99 | 99 | ||
100 | uint16 ltrn_list[PHY_LTRN_LIST_LEN] = { | 100 | u16 ltrn_list[PHY_LTRN_LIST_LEN] = { |
101 | 0x18f9, 0x0d01, 0x00e4, 0xdef4, 0x06f1, 0x0ffc, | 101 | 0x18f9, 0x0d01, 0x00e4, 0xdef4, 0x06f1, 0x0ffc, |
102 | 0xfa27, 0x1dff, 0x10f0, 0x0918, 0xf20a, 0xe010, | 102 | 0xfa27, 0x1dff, 0x10f0, 0x0918, 0xf20a, 0xe010, |
103 | 0x1417, 0x1104, 0xf114, 0xf2fa, 0xf7db, 0xe2fc, | 103 | 0x1417, 0x1104, 0xf114, 0xf2fa, 0xf7db, 0xe2fc, |
@@ -207,16 +207,16 @@ void wlc_radioreg_enter(wlc_phy_t *pih) | |||
207 | void wlc_radioreg_exit(wlc_phy_t *pih) | 207 | void wlc_radioreg_exit(wlc_phy_t *pih) |
208 | { | 208 | { |
209 | phy_info_t *pi = (phy_info_t *) pih; | 209 | phy_info_t *pi = (phy_info_t *) pih; |
210 | volatile uint16 dummy; | 210 | volatile u16 dummy; |
211 | 211 | ||
212 | dummy = R_REG(pi->sh->osh, &pi->regs->phyversion); | 212 | dummy = R_REG(pi->sh->osh, &pi->regs->phyversion); |
213 | pi->phy_wreg = 0; | 213 | pi->phy_wreg = 0; |
214 | wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0); | 214 | wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0); |
215 | } | 215 | } |
216 | 216 | ||
217 | uint16 read_radio_reg(phy_info_t *pi, uint16 addr) | 217 | u16 read_radio_reg(phy_info_t *pi, u16 addr) |
218 | { | 218 | { |
219 | uint16 data; | 219 | u16 data; |
220 | 220 | ||
221 | if ((addr == RADIO_IDCODE)) | 221 | if ((addr == RADIO_IDCODE)) |
222 | return 0xffff; | 222 | return 0xffff; |
@@ -270,7 +270,7 @@ uint16 read_radio_reg(phy_info_t *pi, uint16 addr) | |||
270 | return data; | 270 | return data; |
271 | } | 271 | } |
272 | 272 | ||
273 | void write_radio_reg(phy_info_t *pi, uint16 addr, uint16 val) | 273 | void write_radio_reg(phy_info_t *pi, u16 addr, u16 val) |
274 | { | 274 | { |
275 | osl_t *osh; | 275 | osl_t *osh; |
276 | 276 | ||
@@ -344,9 +344,9 @@ static uint32 read_radio_id(phy_info_t *pi) | |||
344 | return id; | 344 | return id; |
345 | } | 345 | } |
346 | 346 | ||
347 | void and_radio_reg(phy_info_t *pi, uint16 addr, uint16 val) | 347 | void and_radio_reg(phy_info_t *pi, u16 addr, u16 val) |
348 | { | 348 | { |
349 | uint16 rval; | 349 | u16 rval; |
350 | 350 | ||
351 | if (NORADIO_ENAB(pi->pubpi)) | 351 | if (NORADIO_ENAB(pi->pubpi)) |
352 | return; | 352 | return; |
@@ -355,9 +355,9 @@ void and_radio_reg(phy_info_t *pi, uint16 addr, uint16 val) | |||
355 | write_radio_reg(pi, addr, (rval & val)); | 355 | write_radio_reg(pi, addr, (rval & val)); |
356 | } | 356 | } |
357 | 357 | ||
358 | void or_radio_reg(phy_info_t *pi, uint16 addr, uint16 val) | 358 | void or_radio_reg(phy_info_t *pi, u16 addr, u16 val) |
359 | { | 359 | { |
360 | uint16 rval; | 360 | u16 rval; |
361 | 361 | ||
362 | if (NORADIO_ENAB(pi->pubpi)) | 362 | if (NORADIO_ENAB(pi->pubpi)) |
363 | return; | 363 | return; |
@@ -366,9 +366,9 @@ void or_radio_reg(phy_info_t *pi, uint16 addr, uint16 val) | |||
366 | write_radio_reg(pi, addr, (rval | val)); | 366 | write_radio_reg(pi, addr, (rval | val)); |
367 | } | 367 | } |
368 | 368 | ||
369 | void xor_radio_reg(phy_info_t *pi, uint16 addr, uint16 mask) | 369 | void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask) |
370 | { | 370 | { |
371 | uint16 rval; | 371 | u16 rval; |
372 | 372 | ||
373 | if (NORADIO_ENAB(pi->pubpi)) | 373 | if (NORADIO_ENAB(pi->pubpi)) |
374 | return; | 374 | return; |
@@ -377,9 +377,9 @@ void xor_radio_reg(phy_info_t *pi, uint16 addr, uint16 mask) | |||
377 | write_radio_reg(pi, addr, (rval ^ mask)); | 377 | write_radio_reg(pi, addr, (rval ^ mask)); |
378 | } | 378 | } |
379 | 379 | ||
380 | void mod_radio_reg(phy_info_t *pi, uint16 addr, uint16 mask, uint16 val) | 380 | void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val) |
381 | { | 381 | { |
382 | uint16 rval; | 382 | u16 rval; |
383 | 383 | ||
384 | if (NORADIO_ENAB(pi->pubpi)) | 384 | if (NORADIO_ENAB(pi->pubpi)) |
385 | return; | 385 | return; |
@@ -403,7 +403,7 @@ static bool wlc_phy_war41476(phy_info_t *pi) | |||
403 | } | 403 | } |
404 | #endif | 404 | #endif |
405 | 405 | ||
406 | uint16 read_phy_reg(phy_info_t *pi, uint16 addr) | 406 | u16 read_phy_reg(phy_info_t *pi, u16 addr) |
407 | { | 407 | { |
408 | osl_t *osh; | 408 | osl_t *osh; |
409 | d11regs_t *regs; | 409 | d11regs_t *regs; |
@@ -424,7 +424,7 @@ uint16 read_phy_reg(phy_info_t *pi, uint16 addr) | |||
424 | return R_REG(osh, ®s->phyregdata); | 424 | return R_REG(osh, ®s->phyregdata); |
425 | } | 425 | } |
426 | 426 | ||
427 | void write_phy_reg(phy_info_t *pi, uint16 addr, uint16 val) | 427 | void write_phy_reg(phy_info_t *pi, u16 addr, u16 val) |
428 | { | 428 | { |
429 | osl_t *osh; | 429 | osl_t *osh; |
430 | d11regs_t *regs; | 430 | d11regs_t *regs; |
@@ -450,7 +450,7 @@ void write_phy_reg(phy_info_t *pi, uint16 addr, uint16 val) | |||
450 | #endif | 450 | #endif |
451 | } | 451 | } |
452 | 452 | ||
453 | void and_phy_reg(phy_info_t *pi, uint16 addr, uint16 val) | 453 | void and_phy_reg(phy_info_t *pi, u16 addr, u16 val) |
454 | { | 454 | { |
455 | osl_t *osh; | 455 | osl_t *osh; |
456 | d11regs_t *regs; | 456 | d11regs_t *regs; |
@@ -471,7 +471,7 @@ void and_phy_reg(phy_info_t *pi, uint16 addr, uint16 val) | |||
471 | pi->phy_wreg = 0; | 471 | pi->phy_wreg = 0; |
472 | } | 472 | } |
473 | 473 | ||
474 | void or_phy_reg(phy_info_t *pi, uint16 addr, uint16 val) | 474 | void or_phy_reg(phy_info_t *pi, u16 addr, u16 val) |
475 | { | 475 | { |
476 | osl_t *osh; | 476 | osl_t *osh; |
477 | d11regs_t *regs; | 477 | d11regs_t *regs; |
@@ -492,7 +492,7 @@ void or_phy_reg(phy_info_t *pi, uint16 addr, uint16 val) | |||
492 | pi->phy_wreg = 0; | 492 | pi->phy_wreg = 0; |
493 | } | 493 | } |
494 | 494 | ||
495 | void mod_phy_reg(phy_info_t *pi, uint16 addr, uint16 mask, uint16 val) | 495 | void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val) |
496 | { | 496 | { |
497 | osl_t *osh; | 497 | osl_t *osh; |
498 | d11regs_t *regs; | 498 | d11regs_t *regs; |
@@ -815,12 +815,12 @@ void BCMATTACHFN(wlc_phy_detach) (wlc_phy_t *pih) | |||
815 | } | 815 | } |
816 | 816 | ||
817 | bool | 817 | bool |
818 | wlc_phy_get_phyversion(wlc_phy_t *pih, uint16 *phytype, uint16 *phyrev, | 818 | wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype, u16 *phyrev, |
819 | uint16 *radioid, uint16 *radiover) | 819 | u16 *radioid, u16 *radiover) |
820 | { | 820 | { |
821 | phy_info_t *pi = (phy_info_t *) pih; | 821 | phy_info_t *pi = (phy_info_t *) pih; |
822 | *phytype = (uint16) pi->pubpi.phy_type; | 822 | *phytype = (u16) pi->pubpi.phy_type; |
823 | *phyrev = (uint16) pi->pubpi.phy_rev; | 823 | *phyrev = (u16) pi->pubpi.phy_rev; |
824 | *radioid = pi->pubpi.radioid; | 824 | *radioid = pi->pubpi.radioid; |
825 | *radiover = pi->pubpi.radiorev; | 825 | *radiover = pi->pubpi.radiorev; |
826 | 826 | ||
@@ -1075,7 +1075,7 @@ static uint32 wlc_phy_get_radio_ver(phy_info_t *pi) | |||
1075 | 1075 | ||
1076 | void | 1076 | void |
1077 | wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset, | 1077 | wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset, |
1078 | uint16 tblAddr, uint16 tblDataHi, uint16 tblDataLo) | 1078 | u16 tblAddr, u16 tblDataHi, u16 tblDataLo) |
1079 | { | 1079 | { |
1080 | write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset); | 1080 | write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset); |
1081 | 1081 | ||
@@ -1108,24 +1108,24 @@ void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val) | |||
1108 | 1108 | ||
1109 | if (width == 32) { | 1109 | if (width == 32) { |
1110 | 1110 | ||
1111 | write_phy_reg(pi, pi->tbl_data_hi, (uint16) (val >> 16)); | 1111 | write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16)); |
1112 | write_phy_reg(pi, pi->tbl_data_lo, (uint16) val); | 1112 | write_phy_reg(pi, pi->tbl_data_lo, (u16) val); |
1113 | } else { | 1113 | } else { |
1114 | 1114 | ||
1115 | write_phy_reg(pi, pi->tbl_data_lo, (uint16) val); | 1115 | write_phy_reg(pi, pi->tbl_data_lo, (u16) val); |
1116 | } | 1116 | } |
1117 | } | 1117 | } |
1118 | 1118 | ||
1119 | void | 1119 | void |
1120 | wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, | 1120 | wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, |
1121 | uint16 tblAddr, uint16 tblDataHi, uint16 tblDataLo) | 1121 | u16 tblAddr, u16 tblDataHi, u16 tblDataLo) |
1122 | { | 1122 | { |
1123 | uint idx; | 1123 | uint idx; |
1124 | uint tbl_id = ptbl_info->tbl_id; | 1124 | uint tbl_id = ptbl_info->tbl_id; |
1125 | uint tbl_offset = ptbl_info->tbl_offset; | 1125 | uint tbl_offset = ptbl_info->tbl_offset; |
1126 | uint tbl_width = ptbl_info->tbl_width; | 1126 | uint tbl_width = ptbl_info->tbl_width; |
1127 | const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr; | 1127 | const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr; |
1128 | const uint16 *ptbl_16b = (const uint16 *)ptbl_info->tbl_ptr; | 1128 | const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr; |
1129 | const uint32 *ptbl_32b = (const uint32 *)ptbl_info->tbl_ptr; | 1129 | const uint32 *ptbl_32b = (const uint32 *)ptbl_info->tbl_ptr; |
1130 | 1130 | ||
1131 | ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); | 1131 | ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); |
@@ -1147,8 +1147,8 @@ wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, | |||
1147 | if (tbl_width == 32) { | 1147 | if (tbl_width == 32) { |
1148 | 1148 | ||
1149 | write_phy_reg(pi, tblDataHi, | 1149 | write_phy_reg(pi, tblDataHi, |
1150 | (uint16) (ptbl_32b[idx] >> 16)); | 1150 | (u16) (ptbl_32b[idx] >> 16)); |
1151 | write_phy_reg(pi, tblDataLo, (uint16) ptbl_32b[idx]); | 1151 | write_phy_reg(pi, tblDataLo, (u16) ptbl_32b[idx]); |
1152 | } else if (tbl_width == 16) { | 1152 | } else if (tbl_width == 16) { |
1153 | 1153 | ||
1154 | write_phy_reg(pi, tblDataLo, ptbl_16b[idx]); | 1154 | write_phy_reg(pi, tblDataLo, ptbl_16b[idx]); |
@@ -1161,14 +1161,14 @@ wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, | |||
1161 | 1161 | ||
1162 | void | 1162 | void |
1163 | wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, | 1163 | wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, |
1164 | uint16 tblAddr, uint16 tblDataHi, uint16 tblDataLo) | 1164 | u16 tblAddr, u16 tblDataHi, u16 tblDataLo) |
1165 | { | 1165 | { |
1166 | uint idx; | 1166 | uint idx; |
1167 | uint tbl_id = ptbl_info->tbl_id; | 1167 | uint tbl_id = ptbl_info->tbl_id; |
1168 | uint tbl_offset = ptbl_info->tbl_offset; | 1168 | uint tbl_offset = ptbl_info->tbl_offset; |
1169 | uint tbl_width = ptbl_info->tbl_width; | 1169 | uint tbl_width = ptbl_info->tbl_width; |
1170 | u8 *ptbl_8b = (u8 *) (uintptr) ptbl_info->tbl_ptr; | 1170 | u8 *ptbl_8b = (u8 *) (uintptr) ptbl_info->tbl_ptr; |
1171 | uint16 *ptbl_16b = (uint16 *) (uintptr) ptbl_info->tbl_ptr; | 1171 | u16 *ptbl_16b = (u16 *) (uintptr) ptbl_info->tbl_ptr; |
1172 | uint32 *ptbl_32b = (uint32 *) (uintptr) ptbl_info->tbl_ptr; | 1172 | uint32 *ptbl_32b = (uint32 *) (uintptr) ptbl_info->tbl_ptr; |
1173 | 1173 | ||
1174 | ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); | 1174 | ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); |
@@ -1208,7 +1208,7 @@ wlc_phy_init_radio_regs_allbands(phy_info_t *pi, radio_20xx_regs_t *radioregs) | |||
1208 | do { | 1208 | do { |
1209 | if (radioregs[i].do_init) { | 1209 | if (radioregs[i].do_init) { |
1210 | write_radio_reg(pi, radioregs[i].address, | 1210 | write_radio_reg(pi, radioregs[i].address, |
1211 | (uint16) radioregs[i].init); | 1211 | (u16) radioregs[i].init); |
1212 | } | 1212 | } |
1213 | 1213 | ||
1214 | i++; | 1214 | i++; |
@@ -1219,7 +1219,7 @@ wlc_phy_init_radio_regs_allbands(phy_info_t *pi, radio_20xx_regs_t *radioregs) | |||
1219 | 1219 | ||
1220 | uint | 1220 | uint |
1221 | wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs, | 1221 | wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs, |
1222 | uint16 core_offset) | 1222 | u16 core_offset) |
1223 | { | 1223 | { |
1224 | uint i = 0; | 1224 | uint i = 0; |
1225 | uint count = 0; | 1225 | uint count = 0; |
@@ -1230,7 +1230,7 @@ wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs, | |||
1230 | write_radio_reg(pi, | 1230 | write_radio_reg(pi, |
1231 | radioregs[i]. | 1231 | radioregs[i]. |
1232 | address | core_offset, | 1232 | address | core_offset, |
1233 | (uint16) radioregs[i].init_a); | 1233 | (u16) radioregs[i].init_a); |
1234 | if (ISNPHY(pi) && (++count % 4 == 0)) | 1234 | if (ISNPHY(pi) && (++count % 4 == 0)) |
1235 | WLC_PHY_WAR_PR51571(pi); | 1235 | WLC_PHY_WAR_PR51571(pi); |
1236 | } | 1236 | } |
@@ -1239,7 +1239,7 @@ wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs, | |||
1239 | write_radio_reg(pi, | 1239 | write_radio_reg(pi, |
1240 | radioregs[i]. | 1240 | radioregs[i]. |
1241 | address | core_offset, | 1241 | address | core_offset, |
1242 | (uint16) radioregs[i].init_g); | 1242 | (u16) radioregs[i].init_g); |
1243 | if (ISNPHY(pi) && (++count % 4 == 0)) | 1243 | if (ISNPHY(pi) && (++count % 4 == 0)) |
1244 | WLC_PHY_WAR_PR51571(pi); | 1244 | WLC_PHY_WAR_PR51571(pi); |
1245 | } | 1245 | } |
@@ -1428,14 +1428,14 @@ void wlc_phy_switch_radio(wlc_phy_t *pih, bool on) | |||
1428 | } | 1428 | } |
1429 | } | 1429 | } |
1430 | 1430 | ||
1431 | uint16 wlc_phy_bw_state_get(wlc_phy_t *ppi) | 1431 | u16 wlc_phy_bw_state_get(wlc_phy_t *ppi) |
1432 | { | 1432 | { |
1433 | phy_info_t *pi = (phy_info_t *) ppi; | 1433 | phy_info_t *pi = (phy_info_t *) ppi; |
1434 | 1434 | ||
1435 | return pi->bw; | 1435 | return pi->bw; |
1436 | } | 1436 | } |
1437 | 1437 | ||
1438 | void wlc_phy_bw_state_set(wlc_phy_t *ppi, uint16 bw) | 1438 | void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw) |
1439 | { | 1439 | { |
1440 | phy_info_t *pi = (phy_info_t *) ppi; | 1440 | phy_info_t *pi = (phy_info_t *) ppi; |
1441 | 1441 | ||
@@ -1459,7 +1459,7 @@ chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi) | |||
1459 | void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec) | 1459 | void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec) |
1460 | { | 1460 | { |
1461 | phy_info_t *pi = (phy_info_t *) ppi; | 1461 | phy_info_t *pi = (phy_info_t *) ppi; |
1462 | uint16 m_cur_channel; | 1462 | u16 m_cur_channel; |
1463 | chansetfn_t chanspec_set = NULL; | 1463 | chansetfn_t chanspec_set = NULL; |
1464 | 1464 | ||
1465 | ASSERT(!wf_chspec_malformed(chanspec)); | 1465 | ASSERT(!wf_chspec_malformed(chanspec)); |
@@ -2090,7 +2090,7 @@ void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap) | |||
2090 | void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end) | 2090 | void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end) |
2091 | { | 2091 | { |
2092 | phy_info_t *pi = (phy_info_t *) ppi; | 2092 | phy_info_t *pi = (phy_info_t *) ppi; |
2093 | uint16 rxc; | 2093 | u16 rxc; |
2094 | rxc = 0; | 2094 | rxc = 0; |
2095 | 2095 | ||
2096 | if (start_end == ON) { | 2096 | if (start_end == ON) { |
@@ -2169,7 +2169,7 @@ void wlc_phy_txpower_update_shm(phy_info_t *pi) | |||
2169 | return; | 2169 | return; |
2170 | 2170 | ||
2171 | if (pi->hwpwrctrl) { | 2171 | if (pi->hwpwrctrl) { |
2172 | uint16 offset; | 2172 | u16 offset; |
2173 | 2173 | ||
2174 | wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63); | 2174 | wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63); |
2175 | wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N, | 2175 | wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N, |
@@ -2203,7 +2203,7 @@ void wlc_phy_txpower_update_shm(phy_info_t *pi) | |||
2203 | pi->tx_power_offset[i] = | 2203 | pi->tx_power_offset[i] = |
2204 | (u8) ROUNDUP(pi->tx_power_offset[i], 8); | 2204 | (u8) ROUNDUP(pi->tx_power_offset[i], 8); |
2205 | wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET, | 2205 | wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET, |
2206 | (uint16) ((pi-> | 2206 | (u16) ((pi-> |
2207 | tx_power_offset[TXP_FIRST_OFDM] | 2207 | tx_power_offset[TXP_FIRST_OFDM] |
2208 | + 7) >> 3)); | 2208 | + 7) >> 3)); |
2209 | } | 2209 | } |
@@ -2275,7 +2275,7 @@ static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi); | |||
2275 | static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi) | 2275 | static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi) |
2276 | { | 2276 | { |
2277 | int16 tx0_status, tx1_status; | 2277 | int16 tx0_status, tx1_status; |
2278 | uint16 estPower1, estPower2; | 2278 | u16 estPower1, estPower2; |
2279 | u8 pwr0, pwr1, adj_pwr0, adj_pwr1; | 2279 | u8 pwr0, pwr1, adj_pwr0, adj_pwr1; |
2280 | uint32 est_pwr; | 2280 | uint32 est_pwr; |
2281 | 2281 | ||
@@ -2444,8 +2444,8 @@ bool wlc_phy_ant_rxdiv_get(wlc_phy_t *ppi, u8 *pval) | |||
2444 | 2444 | ||
2445 | ret = FALSE; | 2445 | ret = FALSE; |
2446 | } else if (ISLCNPHY(pi)) { | 2446 | } else if (ISLCNPHY(pi)) { |
2447 | uint16 crsctrl = read_phy_reg(pi, 0x410); | 2447 | u16 crsctrl = read_phy_reg(pi, 0x410); |
2448 | uint16 div = crsctrl & (0x1 << 1); | 2448 | u16 div = crsctrl & (0x1 << 1); |
2449 | *pval = (div | ((crsctrl & (0x1 << 0)) ^ (div >> 1))); | 2449 | *pval = (div | ((crsctrl & (0x1 << 0)) ^ (div >> 1))); |
2450 | } | 2450 | } |
2451 | 2451 | ||
@@ -2491,7 +2491,7 @@ void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val) | |||
2491 | ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0); | 2491 | ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0); |
2492 | } else { | 2492 | } else { |
2493 | mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1); | 2493 | mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1); |
2494 | mod_phy_reg(pi, 0x410, (0x1 << 0), (uint16) val << 0); | 2494 | mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0); |
2495 | } | 2495 | } |
2496 | } else { | 2496 | } else { |
2497 | ASSERT(0); | 2497 | ASSERT(0); |
@@ -2618,7 +2618,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch) | |||
2618 | phy_iq_est_t est[PHY_CORE_MAX]; | 2618 | phy_iq_est_t est[PHY_CORE_MAX]; |
2619 | uint32 cmplx_pwr[PHY_CORE_MAX]; | 2619 | uint32 cmplx_pwr[PHY_CORE_MAX]; |
2620 | s8 noise_dbm_ant[PHY_CORE_MAX]; | 2620 | s8 noise_dbm_ant[PHY_CORE_MAX]; |
2621 | uint16 log_num_samps, num_samps, classif_state = 0; | 2621 | u16 log_num_samps, num_samps, classif_state = 0; |
2622 | u8 wait_time = 32; | 2622 | u8 wait_time = 32; |
2623 | u8 wait_crs = 0; | 2623 | u8 wait_crs = 0; |
2624 | u8 i; | 2624 | u8 i; |
@@ -2700,7 +2700,7 @@ static s8 wlc_phy_noise_read_shmem(phy_info_t *pi) | |||
2700 | { | 2700 | { |
2701 | uint32 cmplx_pwr[PHY_CORE_MAX]; | 2701 | uint32 cmplx_pwr[PHY_CORE_MAX]; |
2702 | s8 noise_dbm_ant[PHY_CORE_MAX]; | 2702 | s8 noise_dbm_ant[PHY_CORE_MAX]; |
2703 | uint16 lo, hi; | 2703 | u16 lo, hi; |
2704 | uint32 cmplx_pwr_tot = 0; | 2704 | uint32 cmplx_pwr_tot = 0; |
2705 | s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; | 2705 | s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; |
2706 | u8 idx, core; | 2706 | u8 idx, core; |
@@ -2741,15 +2741,15 @@ static s8 wlc_phy_noise_read_shmem(phy_info_t *pi) | |||
2741 | void wlc_phy_noise_sample_intr(wlc_phy_t *pih) | 2741 | void wlc_phy_noise_sample_intr(wlc_phy_t *pih) |
2742 | { | 2742 | { |
2743 | phy_info_t *pi = (phy_info_t *) pih; | 2743 | phy_info_t *pi = (phy_info_t *) pih; |
2744 | uint16 jssi_aux; | 2744 | u16 jssi_aux; |
2745 | u8 channel = 0; | 2745 | u8 channel = 0; |
2746 | s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; | 2746 | s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; |
2747 | 2747 | ||
2748 | if (ISLCNPHY(pi)) { | 2748 | if (ISLCNPHY(pi)) { |
2749 | uint32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1; | 2749 | uint32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1; |
2750 | uint16 lo, hi; | 2750 | u16 lo, hi; |
2751 | int32 pwr_offset_dB, gain_dB; | 2751 | int32 pwr_offset_dB, gain_dB; |
2752 | uint16 status_0, status_1; | 2752 | u16 status_0, status_1; |
2753 | 2753 | ||
2754 | jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX); | 2754 | jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX); |
2755 | channel = jssi_aux & D11_CURCHANNEL_MAX; | 2755 | channel = jssi_aux & D11_CURCHANNEL_MAX; |
@@ -3330,7 +3330,7 @@ void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode) | |||
3330 | if ((CHIPID(pi->sh->chip) == BCM4313_CHIP_ID) && | 3330 | if ((CHIPID(pi->sh->chip) == BCM4313_CHIP_ID) && |
3331 | (pi->sh->boardflags & BFL_FEM)) { | 3331 | (pi->sh->boardflags & BFL_FEM)) { |
3332 | if (mode) { | 3332 | if (mode) { |
3333 | uint16 txant = 0; | 3333 | u16 txant = 0; |
3334 | txant = wlapi_bmac_get_txant(pi->sh->physhim); | 3334 | txant = wlapi_bmac_get_txant(pi->sh->physhim); |
3335 | if (txant == 1) { | 3335 | if (txant == 1) { |
3336 | mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2); | 3336 | mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2); |
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_hal.h b/drivers/staging/brcm80211/phy/wlc_phy_hal.h index e7ae32ccc80..849530a8e00 100644 --- a/drivers/staging/brcm80211/phy/wlc_phy_hal.h +++ b/drivers/staging/brcm80211/phy/wlc_phy_hal.h | |||
@@ -138,8 +138,8 @@ typedef struct shared_phy_params { | |||
138 | uint bustype; | 138 | uint bustype; |
139 | uint buscorerev; | 139 | uint buscorerev; |
140 | char *vars; | 140 | char *vars; |
141 | uint16 vid; | 141 | u16 vid; |
142 | uint16 did; | 142 | u16 did; |
143 | uint chip; | 143 | uint chip; |
144 | uint chiprev; | 144 | uint chiprev; |
145 | uint chippkg; | 145 | uint chippkg; |
@@ -159,9 +159,9 @@ extern wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype, | |||
159 | char *vars); | 159 | char *vars); |
160 | extern void wlc_phy_detach(wlc_phy_t *ppi); | 160 | extern void wlc_phy_detach(wlc_phy_t *ppi); |
161 | 161 | ||
162 | extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, uint16 *phytype, | 162 | extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype, |
163 | uint16 *phyrev, uint16 *radioid, | 163 | u16 *phyrev, u16 *radioid, |
164 | uint16 *radiover); | 164 | u16 *radiover); |
165 | extern bool wlc_phy_get_encore(wlc_phy_t *pih); | 165 | extern bool wlc_phy_get_encore(wlc_phy_t *pih); |
166 | extern uint32 wlc_phy_get_coreflags(wlc_phy_t *pih); | 166 | extern uint32 wlc_phy_get_coreflags(wlc_phy_t *pih); |
167 | 167 | ||
@@ -177,8 +177,8 @@ extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init); | |||
177 | extern void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec); | 177 | extern void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec); |
178 | extern chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi); | 178 | extern chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi); |
179 | extern void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch); | 179 | extern void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch); |
180 | extern uint16 wlc_phy_bw_state_get(wlc_phy_t *ppi); | 180 | extern u16 wlc_phy_bw_state_get(wlc_phy_t *ppi); |
181 | extern void wlc_phy_bw_state_set(wlc_phy_t *ppi, uint16 bw); | 181 | extern void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw); |
182 | 182 | ||
183 | extern void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx); | 183 | extern void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx); |
184 | extern void wlc_phy_por_inform(wlc_phy_t *ppi); | 184 | extern void wlc_phy_por_inform(wlc_phy_t *ppi); |
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_int.h b/drivers/staging/brcm80211/phy/wlc_phy_int.h index 66b04c79a9c..2dd193ebfae 100644 --- a/drivers/staging/brcm80211/phy/wlc_phy_int.h +++ b/drivers/staging/brcm80211/phy/wlc_phy_int.h | |||
@@ -46,9 +46,9 @@ typedef struct phy_info phy_info_t; | |||
46 | typedef void (*initfn_t) (phy_info_t *); | 46 | typedef void (*initfn_t) (phy_info_t *); |
47 | typedef void (*chansetfn_t) (phy_info_t *, chanspec_t); | 47 | typedef void (*chansetfn_t) (phy_info_t *, chanspec_t); |
48 | typedef int (*longtrnfn_t) (phy_info_t *, int); | 48 | typedef int (*longtrnfn_t) (phy_info_t *, int); |
49 | typedef void (*txiqccgetfn_t) (phy_info_t *, uint16 *, uint16 *); | 49 | typedef void (*txiqccgetfn_t) (phy_info_t *, u16 *, u16 *); |
50 | typedef void (*txiqccsetfn_t) (phy_info_t *, uint16, uint16); | 50 | typedef void (*txiqccsetfn_t) (phy_info_t *, u16, u16); |
51 | typedef uint16(*txloccgetfn_t) (phy_info_t *); | 51 | typedef u16(*txloccgetfn_t) (phy_info_t *); |
52 | typedef void (*radioloftgetfn_t) (phy_info_t *, u8 *, u8 *, u8 *, | 52 | typedef void (*radioloftgetfn_t) (phy_info_t *, u8 *, u8 *, u8 *, |
53 | u8 *); | 53 | u8 *); |
54 | typedef int32(*rxsigpwrfn_t) (phy_info_t *, int32); | 54 | typedef int32(*rxsigpwrfn_t) (phy_info_t *, int32); |
@@ -282,7 +282,7 @@ typedef enum { | |||
282 | #endif | 282 | #endif |
283 | 283 | ||
284 | #define PHY_LTRN_LIST_LEN 64 | 284 | #define PHY_LTRN_LIST_LEN 64 |
285 | extern uint16 ltrn_list[PHY_LTRN_LIST_LEN]; | 285 | extern u16 ltrn_list[PHY_LTRN_LIST_LEN]; |
286 | 286 | ||
287 | typedef struct _phy_table_info { | 287 | typedef struct _phy_table_info { |
288 | uint table; | 288 | uint table; |
@@ -300,111 +300,111 @@ typedef struct phytbl_info { | |||
300 | 300 | ||
301 | typedef struct { | 301 | typedef struct { |
302 | u8 curr_home_channel; | 302 | u8 curr_home_channel; |
303 | uint16 crsminpwrthld_40_stored; | 303 | u16 crsminpwrthld_40_stored; |
304 | uint16 crsminpwrthld_20L_stored; | 304 | u16 crsminpwrthld_20L_stored; |
305 | uint16 crsminpwrthld_20U_stored; | 305 | u16 crsminpwrthld_20U_stored; |
306 | uint16 init_gain_code_core1_stored; | 306 | u16 init_gain_code_core1_stored; |
307 | uint16 init_gain_code_core2_stored; | 307 | u16 init_gain_code_core2_stored; |
308 | uint16 init_gain_codeb_core1_stored; | 308 | u16 init_gain_codeb_core1_stored; |
309 | uint16 init_gain_codeb_core2_stored; | 309 | u16 init_gain_codeb_core2_stored; |
310 | uint16 init_gain_table_stored[4]; | 310 | u16 init_gain_table_stored[4]; |
311 | 311 | ||
312 | uint16 clip1_hi_gain_code_core1_stored; | 312 | u16 clip1_hi_gain_code_core1_stored; |
313 | uint16 clip1_hi_gain_code_core2_stored; | 313 | u16 clip1_hi_gain_code_core2_stored; |
314 | uint16 clip1_hi_gain_codeb_core1_stored; | 314 | u16 clip1_hi_gain_codeb_core1_stored; |
315 | uint16 clip1_hi_gain_codeb_core2_stored; | 315 | u16 clip1_hi_gain_codeb_core2_stored; |
316 | uint16 nb_clip_thresh_core1_stored; | 316 | u16 nb_clip_thresh_core1_stored; |
317 | uint16 nb_clip_thresh_core2_stored; | 317 | u16 nb_clip_thresh_core2_stored; |
318 | uint16 init_ofdmlna2gainchange_stored[4]; | 318 | u16 init_ofdmlna2gainchange_stored[4]; |
319 | uint16 init_ccklna2gainchange_stored[4]; | 319 | u16 init_ccklna2gainchange_stored[4]; |
320 | uint16 clip1_lo_gain_code_core1_stored; | 320 | u16 clip1_lo_gain_code_core1_stored; |
321 | uint16 clip1_lo_gain_code_core2_stored; | 321 | u16 clip1_lo_gain_code_core2_stored; |
322 | uint16 clip1_lo_gain_codeb_core1_stored; | 322 | u16 clip1_lo_gain_codeb_core1_stored; |
323 | uint16 clip1_lo_gain_codeb_core2_stored; | 323 | u16 clip1_lo_gain_codeb_core2_stored; |
324 | uint16 w1_clip_thresh_core1_stored; | 324 | u16 w1_clip_thresh_core1_stored; |
325 | uint16 w1_clip_thresh_core2_stored; | 325 | u16 w1_clip_thresh_core2_stored; |
326 | uint16 radio_2056_core1_rssi_gain_stored; | 326 | u16 radio_2056_core1_rssi_gain_stored; |
327 | uint16 radio_2056_core2_rssi_gain_stored; | 327 | u16 radio_2056_core2_rssi_gain_stored; |
328 | uint16 energy_drop_timeout_len_stored; | 328 | u16 energy_drop_timeout_len_stored; |
329 | 329 | ||
330 | uint16 ed_crs40_assertthld0_stored; | 330 | u16 ed_crs40_assertthld0_stored; |
331 | uint16 ed_crs40_assertthld1_stored; | 331 | u16 ed_crs40_assertthld1_stored; |
332 | uint16 ed_crs40_deassertthld0_stored; | 332 | u16 ed_crs40_deassertthld0_stored; |
333 | uint16 ed_crs40_deassertthld1_stored; | 333 | u16 ed_crs40_deassertthld1_stored; |
334 | uint16 ed_crs20L_assertthld0_stored; | 334 | u16 ed_crs20L_assertthld0_stored; |
335 | uint16 ed_crs20L_assertthld1_stored; | 335 | u16 ed_crs20L_assertthld1_stored; |
336 | uint16 ed_crs20L_deassertthld0_stored; | 336 | u16 ed_crs20L_deassertthld0_stored; |
337 | uint16 ed_crs20L_deassertthld1_stored; | 337 | u16 ed_crs20L_deassertthld1_stored; |
338 | uint16 ed_crs20U_assertthld0_stored; | 338 | u16 ed_crs20U_assertthld0_stored; |
339 | uint16 ed_crs20U_assertthld1_stored; | 339 | u16 ed_crs20U_assertthld1_stored; |
340 | uint16 ed_crs20U_deassertthld0_stored; | 340 | u16 ed_crs20U_deassertthld0_stored; |
341 | uint16 ed_crs20U_deassertthld1_stored; | 341 | u16 ed_crs20U_deassertthld1_stored; |
342 | 342 | ||
343 | uint16 badplcp_ma; | 343 | u16 badplcp_ma; |
344 | uint16 badplcp_ma_previous; | 344 | u16 badplcp_ma_previous; |
345 | uint16 badplcp_ma_total; | 345 | u16 badplcp_ma_total; |
346 | uint16 badplcp_ma_list[MA_WINDOW_SZ]; | 346 | u16 badplcp_ma_list[MA_WINDOW_SZ]; |
347 | int badplcp_ma_index; | 347 | int badplcp_ma_index; |
348 | int16 pre_badplcp_cnt; | 348 | int16 pre_badplcp_cnt; |
349 | int16 bphy_pre_badplcp_cnt; | 349 | int16 bphy_pre_badplcp_cnt; |
350 | 350 | ||
351 | uint16 init_gain_core1; | 351 | u16 init_gain_core1; |
352 | uint16 init_gain_core2; | 352 | u16 init_gain_core2; |
353 | uint16 init_gainb_core1; | 353 | u16 init_gainb_core1; |
354 | uint16 init_gainb_core2; | 354 | u16 init_gainb_core2; |
355 | uint16 init_gain_rfseq[4]; | 355 | u16 init_gain_rfseq[4]; |
356 | 356 | ||
357 | uint16 crsminpwr0; | 357 | u16 crsminpwr0; |
358 | uint16 crsminpwrl0; | 358 | u16 crsminpwrl0; |
359 | uint16 crsminpwru0; | 359 | u16 crsminpwru0; |
360 | 360 | ||
361 | int16 crsminpwr_index; | 361 | int16 crsminpwr_index; |
362 | 362 | ||
363 | uint16 radio_2057_core1_rssi_wb1a_gc_stored; | 363 | u16 radio_2057_core1_rssi_wb1a_gc_stored; |
364 | uint16 radio_2057_core2_rssi_wb1a_gc_stored; | 364 | u16 radio_2057_core2_rssi_wb1a_gc_stored; |
365 | uint16 radio_2057_core1_rssi_wb1g_gc_stored; | 365 | u16 radio_2057_core1_rssi_wb1g_gc_stored; |
366 | uint16 radio_2057_core2_rssi_wb1g_gc_stored; | 366 | u16 radio_2057_core2_rssi_wb1g_gc_stored; |
367 | uint16 radio_2057_core1_rssi_wb2_gc_stored; | 367 | u16 radio_2057_core1_rssi_wb2_gc_stored; |
368 | uint16 radio_2057_core2_rssi_wb2_gc_stored; | 368 | u16 radio_2057_core2_rssi_wb2_gc_stored; |
369 | uint16 radio_2057_core1_rssi_nb_gc_stored; | 369 | u16 radio_2057_core1_rssi_nb_gc_stored; |
370 | uint16 radio_2057_core2_rssi_nb_gc_stored; | 370 | u16 radio_2057_core2_rssi_nb_gc_stored; |
371 | 371 | ||
372 | } interference_info_t; | 372 | } interference_info_t; |
373 | 373 | ||
374 | typedef struct { | 374 | typedef struct { |
375 | uint16 rc_cal_ovr; | 375 | u16 rc_cal_ovr; |
376 | uint16 phycrsth1; | 376 | u16 phycrsth1; |
377 | uint16 phycrsth2; | 377 | u16 phycrsth2; |
378 | uint16 init_n1p1_gain; | 378 | u16 init_n1p1_gain; |
379 | uint16 p1_p2_gain; | 379 | u16 p1_p2_gain; |
380 | uint16 n1_n2_gain; | 380 | u16 n1_n2_gain; |
381 | uint16 n1_p1_gain; | 381 | u16 n1_p1_gain; |
382 | uint16 div_search_gain; | 382 | u16 div_search_gain; |
383 | uint16 div_p1_p2_gain; | 383 | u16 div_p1_p2_gain; |
384 | uint16 div_search_gn_change; | 384 | u16 div_search_gn_change; |
385 | uint16 table_7_2; | 385 | u16 table_7_2; |
386 | uint16 table_7_3; | 386 | u16 table_7_3; |
387 | uint16 cckshbits_gnref; | 387 | u16 cckshbits_gnref; |
388 | uint16 clip_thresh; | 388 | u16 clip_thresh; |
389 | uint16 clip2_thresh; | 389 | u16 clip2_thresh; |
390 | uint16 clip3_thresh; | 390 | u16 clip3_thresh; |
391 | uint16 clip_p2_thresh; | 391 | u16 clip_p2_thresh; |
392 | uint16 clip_pwdn_thresh; | 392 | u16 clip_pwdn_thresh; |
393 | uint16 clip_n1p1_thresh; | 393 | u16 clip_n1p1_thresh; |
394 | uint16 clip_n1_pwdn_thresh; | 394 | u16 clip_n1_pwdn_thresh; |
395 | uint16 bbconfig; | 395 | u16 bbconfig; |
396 | uint16 cthr_sthr_shdin; | 396 | u16 cthr_sthr_shdin; |
397 | uint16 energy; | 397 | u16 energy; |
398 | uint16 clip_p1_p2_thresh; | 398 | u16 clip_p1_p2_thresh; |
399 | uint16 threshold; | 399 | u16 threshold; |
400 | uint16 reg15; | 400 | u16 reg15; |
401 | uint16 reg16; | 401 | u16 reg16; |
402 | uint16 reg17; | 402 | u16 reg17; |
403 | uint16 div_srch_idx; | 403 | u16 div_srch_idx; |
404 | uint16 div_srch_p1_p2; | 404 | u16 div_srch_p1_p2; |
405 | uint16 div_srch_gn_back; | 405 | u16 div_srch_gn_back; |
406 | uint16 ant_dwell; | 406 | u16 ant_dwell; |
407 | uint16 ant_wr_settle; | 407 | u16 ant_wr_settle; |
408 | } aci_save_gphy_t; | 408 | } aci_save_gphy_t; |
409 | 409 | ||
410 | typedef struct _lo_complex_t { | 410 | typedef struct _lo_complex_t { |
@@ -423,23 +423,23 @@ typedef struct _nphy_txpwrindex { | |||
423 | s8 index; | 423 | s8 index; |
424 | s8 index_internal; | 424 | s8 index_internal; |
425 | s8 index_internal_save; | 425 | s8 index_internal_save; |
426 | uint16 AfectrlOverride; | 426 | u16 AfectrlOverride; |
427 | uint16 AfeCtrlDacGain; | 427 | u16 AfeCtrlDacGain; |
428 | uint16 rad_gain; | 428 | u16 rad_gain; |
429 | u8 bbmult; | 429 | u8 bbmult; |
430 | uint16 iqcomp_a; | 430 | u16 iqcomp_a; |
431 | uint16 iqcomp_b; | 431 | u16 iqcomp_b; |
432 | uint16 locomp; | 432 | u16 locomp; |
433 | } phy_txpwrindex_t; | 433 | } phy_txpwrindex_t; |
434 | 434 | ||
435 | typedef struct { | 435 | typedef struct { |
436 | 436 | ||
437 | uint16 txcal_coeffs_2G[8]; | 437 | u16 txcal_coeffs_2G[8]; |
438 | uint16 txcal_radio_regs_2G[8]; | 438 | u16 txcal_radio_regs_2G[8]; |
439 | nphy_iq_comp_t rxcal_coeffs_2G; | 439 | nphy_iq_comp_t rxcal_coeffs_2G; |
440 | 440 | ||
441 | uint16 txcal_coeffs_5G[8]; | 441 | u16 txcal_coeffs_5G[8]; |
442 | uint16 txcal_radio_regs_5G[8]; | 442 | u16 txcal_radio_regs_5G[8]; |
443 | nphy_iq_comp_t rxcal_coeffs_5G; | 443 | nphy_iq_comp_t rxcal_coeffs_5G; |
444 | } txiqcal_cache_t; | 444 | } txiqcal_cache_t; |
445 | 445 | ||
@@ -473,11 +473,11 @@ typedef struct _nphy_pwrctrl { | |||
473 | } phy_pwrctrl_t; | 473 | } phy_pwrctrl_t; |
474 | 474 | ||
475 | typedef struct _nphy_txgains { | 475 | typedef struct _nphy_txgains { |
476 | uint16 txlpf[2]; | 476 | u16 txlpf[2]; |
477 | uint16 txgm[2]; | 477 | u16 txgm[2]; |
478 | uint16 pga[2]; | 478 | u16 pga[2]; |
479 | uint16 pad[2]; | 479 | u16 pad[2]; |
480 | uint16 ipa[2]; | 480 | u16 ipa[2]; |
481 | } nphy_txgains_t; | 481 | } nphy_txgains_t; |
482 | 482 | ||
483 | #define PHY_NOISEVAR_BUFSIZE 10 | 483 | #define PHY_NOISEVAR_BUFSIZE 10 |
@@ -490,37 +490,37 @@ typedef struct _nphy_noisevar_buf { | |||
490 | } phy_noisevar_buf_t; | 490 | } phy_noisevar_buf_t; |
491 | 491 | ||
492 | typedef struct { | 492 | typedef struct { |
493 | uint16 rssical_radio_regs_2G[2]; | 493 | u16 rssical_radio_regs_2G[2]; |
494 | uint16 rssical_phyregs_2G[12]; | 494 | u16 rssical_phyregs_2G[12]; |
495 | 495 | ||
496 | uint16 rssical_radio_regs_5G[2]; | 496 | u16 rssical_radio_regs_5G[2]; |
497 | uint16 rssical_phyregs_5G[12]; | 497 | u16 rssical_phyregs_5G[12]; |
498 | } rssical_cache_t; | 498 | } rssical_cache_t; |
499 | 499 | ||
500 | typedef struct { | 500 | typedef struct { |
501 | 501 | ||
502 | uint16 txiqlocal_a; | 502 | u16 txiqlocal_a; |
503 | uint16 txiqlocal_b; | 503 | u16 txiqlocal_b; |
504 | uint16 txiqlocal_didq; | 504 | u16 txiqlocal_didq; |
505 | u8 txiqlocal_ei0; | 505 | u8 txiqlocal_ei0; |
506 | u8 txiqlocal_eq0; | 506 | u8 txiqlocal_eq0; |
507 | u8 txiqlocal_fi0; | 507 | u8 txiqlocal_fi0; |
508 | u8 txiqlocal_fq0; | 508 | u8 txiqlocal_fq0; |
509 | 509 | ||
510 | uint16 txiqlocal_bestcoeffs[11]; | 510 | u16 txiqlocal_bestcoeffs[11]; |
511 | uint16 txiqlocal_bestcoeffs_valid; | 511 | u16 txiqlocal_bestcoeffs_valid; |
512 | 512 | ||
513 | uint32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY]; | 513 | uint32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY]; |
514 | uint16 analog_gain_ref; | 514 | u16 analog_gain_ref; |
515 | uint16 lut_begin; | 515 | u16 lut_begin; |
516 | uint16 lut_end; | 516 | u16 lut_end; |
517 | uint16 lut_step; | 517 | u16 lut_step; |
518 | uint16 rxcompdbm; | 518 | u16 rxcompdbm; |
519 | uint16 papdctrl; | 519 | u16 papdctrl; |
520 | uint16 sslpnCalibClkEnCtrl; | 520 | u16 sslpnCalibClkEnCtrl; |
521 | 521 | ||
522 | uint16 rxiqcal_coeff_a0; | 522 | u16 rxiqcal_coeff_a0; |
523 | uint16 rxiqcal_coeff_b0; | 523 | u16 rxiqcal_coeff_b0; |
524 | } lcnphy_cal_results_t; | 524 | } lcnphy_cal_results_t; |
525 | 525 | ||
526 | struct shared_phy { | 526 | struct shared_phy { |
@@ -534,8 +534,8 @@ struct shared_phy { | |||
534 | bool up; | 534 | bool up; |
535 | bool clk; | 535 | bool clk; |
536 | uint now; | 536 | uint now; |
537 | uint16 vid; | 537 | u16 vid; |
538 | uint16 did; | 538 | u16 did; |
539 | uint chip; | 539 | uint chip; |
540 | uint chiprev; | 540 | uint chiprev; |
541 | uint chippkg; | 541 | uint chippkg; |
@@ -565,7 +565,7 @@ struct phy_pub { | |||
565 | uint phy_type; | 565 | uint phy_type; |
566 | uint phy_rev; | 566 | uint phy_rev; |
567 | u8 phy_corenum; | 567 | u8 phy_corenum; |
568 | uint16 radioid; | 568 | u16 radioid; |
569 | u8 radiorev; | 569 | u8 radiorev; |
570 | u8 radiover; | 570 | u8 radiover; |
571 | 571 | ||
@@ -618,7 +618,7 @@ struct phy_info { | |||
618 | bool bf_preempt_4306; | 618 | bool bf_preempt_4306; |
619 | chanspec_t radio_chanspec; | 619 | chanspec_t radio_chanspec; |
620 | u8 antsel_type; | 620 | u8 antsel_type; |
621 | uint16 bw; | 621 | u16 bw; |
622 | u8 txpwr_percent; | 622 | u8 txpwr_percent; |
623 | bool phy_init_por; | 623 | bool phy_init_por; |
624 | 624 | ||
@@ -663,8 +663,8 @@ struct phy_info { | |||
663 | s8 nphy_txrx_chain; | 663 | s8 nphy_txrx_chain; |
664 | bool phy_5g_pwrgain; | 664 | bool phy_5g_pwrgain; |
665 | 665 | ||
666 | uint16 phy_wreg; | 666 | u16 phy_wreg; |
667 | uint16 phy_wreg_limit; | 667 | u16 phy_wreg_limit; |
668 | 668 | ||
669 | s8 n_preamble_override; | 669 | s8 n_preamble_override; |
670 | u8 antswitch; | 670 | u8 antswitch; |
@@ -683,7 +683,7 @@ struct phy_info { | |||
683 | bool txpwroverride; | 683 | bool txpwroverride; |
684 | bool txpwridx_override_aphy; | 684 | bool txpwridx_override_aphy; |
685 | int16 radiopwr_override; | 685 | int16 radiopwr_override; |
686 | uint16 hwpwr_txcur; | 686 | u16 hwpwr_txcur; |
687 | u8 saved_txpwr_idx; | 687 | u8 saved_txpwr_idx; |
688 | 688 | ||
689 | bool edcrs_threshold_lock; | 689 | bool edcrs_threshold_lock; |
@@ -695,10 +695,10 @@ struct phy_info { | |||
695 | int16 cck_analog_filt_bw_override; | 695 | int16 cck_analog_filt_bw_override; |
696 | int16 ofdm_rccal_override; | 696 | int16 ofdm_rccal_override; |
697 | int16 cck_rccal_override; | 697 | int16 cck_rccal_override; |
698 | uint16 extlna_type; | 698 | u16 extlna_type; |
699 | 699 | ||
700 | uint interference_mode_crs_time; | 700 | uint interference_mode_crs_time; |
701 | uint16 crsglitch_prev; | 701 | u16 crsglitch_prev; |
702 | bool interference_mode_crs; | 702 | bool interference_mode_crs; |
703 | 703 | ||
704 | uint32 phy_tx_tone_freq; | 704 | uint32 phy_tx_tone_freq; |
@@ -719,21 +719,21 @@ struct phy_info { | |||
719 | s8 phy_tempsense_offset; | 719 | s8 phy_tempsense_offset; |
720 | bool phy_txcore_heatedup; | 720 | bool phy_txcore_heatedup; |
721 | 721 | ||
722 | uint16 radiopwr; | 722 | u16 radiopwr; |
723 | uint16 bb_atten; | 723 | u16 bb_atten; |
724 | uint16 txctl1; | 724 | u16 txctl1; |
725 | 725 | ||
726 | uint16 mintxbias; | 726 | u16 mintxbias; |
727 | uint16 mintxmag; | 727 | u16 mintxmag; |
728 | lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB]; | 728 | lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB]; |
729 | s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB]; | 729 | s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB]; |
730 | uint16 gain_table[TX_GAIN_TABLE_LENGTH]; | 730 | u16 gain_table[TX_GAIN_TABLE_LENGTH]; |
731 | bool loopback_gain; | 731 | bool loopback_gain; |
732 | int16 max_lpback_gain_hdB; | 732 | int16 max_lpback_gain_hdB; |
733 | int16 trsw_rx_gain_hdB; | 733 | int16 trsw_rx_gain_hdB; |
734 | u8 power_vec[8]; | 734 | u8 power_vec[8]; |
735 | 735 | ||
736 | uint16 rc_cal; | 736 | u16 rc_cal; |
737 | int nrssi_table_delta; | 737 | int nrssi_table_delta; |
738 | int nrssi_slope_scale; | 738 | int nrssi_slope_scale; |
739 | int nrssi_slope_offset; | 739 | int nrssi_slope_offset; |
@@ -745,18 +745,18 @@ struct phy_info { | |||
745 | 745 | ||
746 | u8 a_band_high_disable; | 746 | u8 a_band_high_disable; |
747 | 747 | ||
748 | uint16 tx_vos; | 748 | u16 tx_vos; |
749 | uint16 global_tx_bb_dc_bias_loft; | 749 | u16 global_tx_bb_dc_bias_loft; |
750 | 750 | ||
751 | int rf_max; | 751 | int rf_max; |
752 | int bb_max; | 752 | int bb_max; |
753 | int rf_list_size; | 753 | int rf_list_size; |
754 | int bb_list_size; | 754 | int bb_list_size; |
755 | uint16 *rf_attn_list; | 755 | u16 *rf_attn_list; |
756 | uint16 *bb_attn_list; | 756 | u16 *bb_attn_list; |
757 | uint16 padmix_mask; | 757 | u16 padmix_mask; |
758 | uint16 padmix_reg; | 758 | u16 padmix_reg; |
759 | uint16 *txmag_list; | 759 | u16 *txmag_list; |
760 | uint txmag_len; | 760 | uint txmag_len; |
761 | bool txmag_enable; | 761 | bool txmag_enable; |
762 | 762 | ||
@@ -766,7 +766,7 @@ struct phy_info { | |||
766 | s8 *h_tssi_to_dbm; | 766 | s8 *h_tssi_to_dbm; |
767 | u8 *hwtxpwr; | 767 | u8 *hwtxpwr; |
768 | 768 | ||
769 | uint16 freqtrack_saved_regs[2]; | 769 | u16 freqtrack_saved_regs[2]; |
770 | int cur_interference_mode; | 770 | int cur_interference_mode; |
771 | bool hwpwrctrl_capable; | 771 | bool hwpwrctrl_capable; |
772 | bool temppwrctrl_capable; | 772 | bool temppwrctrl_capable; |
@@ -782,11 +782,11 @@ struct phy_info { | |||
782 | bool nphy_tableloaded; | 782 | bool nphy_tableloaded; |
783 | s8 nphy_rssisel; | 783 | s8 nphy_rssisel; |
784 | uint32 nphy_bb_mult_save; | 784 | uint32 nphy_bb_mult_save; |
785 | uint16 nphy_txiqlocal_bestc[11]; | 785 | u16 nphy_txiqlocal_bestc[11]; |
786 | bool nphy_txiqlocal_coeffsvalid; | 786 | bool nphy_txiqlocal_coeffsvalid; |
787 | phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2]; | 787 | phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2]; |
788 | phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2]; | 788 | phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2]; |
789 | uint16 cck2gpo; | 789 | u16 cck2gpo; |
790 | uint32 ofdm2gpo; | 790 | uint32 ofdm2gpo; |
791 | uint32 ofdm5gpo; | 791 | uint32 ofdm5gpo; |
792 | uint32 ofdm5glpo; | 792 | uint32 ofdm5glpo; |
@@ -807,10 +807,10 @@ struct phy_info { | |||
807 | u8 bwdup5gpo; | 807 | u8 bwdup5gpo; |
808 | u8 bwdup5glpo; | 808 | u8 bwdup5glpo; |
809 | u8 bwdup5ghpo; | 809 | u8 bwdup5ghpo; |
810 | uint16 mcs2gpo[8]; | 810 | u16 mcs2gpo[8]; |
811 | uint16 mcs5gpo[8]; | 811 | u16 mcs5gpo[8]; |
812 | uint16 mcs5glpo[8]; | 812 | u16 mcs5glpo[8]; |
813 | uint16 mcs5ghpo[8]; | 813 | u16 mcs5ghpo[8]; |
814 | uint32 nphy_rxcalparams; | 814 | uint32 nphy_rxcalparams; |
815 | 815 | ||
816 | u8 phy_spuravoid; | 816 | u8 phy_spuravoid; |
@@ -830,8 +830,8 @@ struct phy_info { | |||
830 | 830 | ||
831 | bool nphy_gain_boost; | 831 | bool nphy_gain_boost; |
832 | bool nphy_elna_gain_config; | 832 | bool nphy_elna_gain_config; |
833 | uint16 old_bphy_test; | 833 | u16 old_bphy_test; |
834 | uint16 old_bphy_testcontrol; | 834 | u16 old_bphy_testcontrol; |
835 | 835 | ||
836 | bool phyhang_avoid; | 836 | bool phyhang_avoid; |
837 | 837 | ||
@@ -842,7 +842,7 @@ struct phy_info { | |||
842 | u8 mphase_cal_phase_id; | 842 | u8 mphase_cal_phase_id; |
843 | u8 mphase_txcal_cmdidx; | 843 | u8 mphase_txcal_cmdidx; |
844 | u8 mphase_txcal_numcmds; | 844 | u8 mphase_txcal_numcmds; |
845 | uint16 mphase_txcal_bestcoeffs[11]; | 845 | u16 mphase_txcal_bestcoeffs[11]; |
846 | chanspec_t nphy_txiqlocal_chanspec; | 846 | chanspec_t nphy_txiqlocal_chanspec; |
847 | chanspec_t nphy_iqcal_chanspec_2G; | 847 | chanspec_t nphy_iqcal_chanspec_2G; |
848 | chanspec_t nphy_iqcal_chanspec_5G; | 848 | chanspec_t nphy_iqcal_chanspec_5G; |
@@ -859,7 +859,7 @@ struct phy_info { | |||
859 | u8 nphy_txpwr_idx[2]; | 859 | u8 nphy_txpwr_idx[2]; |
860 | u8 nphy_papd_cal_type; | 860 | u8 nphy_papd_cal_type; |
861 | uint nphy_papd_last_cal; | 861 | uint nphy_papd_last_cal; |
862 | uint16 nphy_papd_tx_gain_at_last_cal[2]; | 862 | u16 nphy_papd_tx_gain_at_last_cal[2]; |
863 | u8 nphy_papd_cal_gain_index[2]; | 863 | u8 nphy_papd_cal_gain_index[2]; |
864 | int16 nphy_papd_epsilon_offset[2]; | 864 | int16 nphy_papd_epsilon_offset[2]; |
865 | bool nphy_papd_recal_enable; | 865 | bool nphy_papd_recal_enable; |
@@ -869,64 +869,64 @@ struct phy_info { | |||
869 | bool ipa2g_on; | 869 | bool ipa2g_on; |
870 | bool ipa5g_on; | 870 | bool ipa5g_on; |
871 | 871 | ||
872 | uint16 classifier_state; | 872 | u16 classifier_state; |
873 | uint16 clip_state[2]; | 873 | u16 clip_state[2]; |
874 | uint nphy_deaf_count; | 874 | uint nphy_deaf_count; |
875 | u8 rxiq_samps; | 875 | u8 rxiq_samps; |
876 | u8 rxiq_antsel; | 876 | u8 rxiq_antsel; |
877 | 877 | ||
878 | uint16 rfctrlIntc1_save; | 878 | u16 rfctrlIntc1_save; |
879 | uint16 rfctrlIntc2_save; | 879 | u16 rfctrlIntc2_save; |
880 | bool first_cal_after_assoc; | 880 | bool first_cal_after_assoc; |
881 | uint16 tx_rx_cal_radio_saveregs[22]; | 881 | u16 tx_rx_cal_radio_saveregs[22]; |
882 | uint16 tx_rx_cal_phy_saveregs[15]; | 882 | u16 tx_rx_cal_phy_saveregs[15]; |
883 | 883 | ||
884 | u8 nphy_cal_orig_pwr_idx[2]; | 884 | u8 nphy_cal_orig_pwr_idx[2]; |
885 | u8 nphy_txcal_pwr_idx[2]; | 885 | u8 nphy_txcal_pwr_idx[2]; |
886 | u8 nphy_rxcal_pwr_idx[2]; | 886 | u8 nphy_rxcal_pwr_idx[2]; |
887 | uint16 nphy_cal_orig_tx_gain[2]; | 887 | u16 nphy_cal_orig_tx_gain[2]; |
888 | nphy_txgains_t nphy_cal_target_gain; | 888 | nphy_txgains_t nphy_cal_target_gain; |
889 | uint16 nphy_txcal_bbmult; | 889 | u16 nphy_txcal_bbmult; |
890 | uint16 nphy_gmval; | 890 | u16 nphy_gmval; |
891 | 891 | ||
892 | uint16 nphy_saved_bbconf; | 892 | u16 nphy_saved_bbconf; |
893 | 893 | ||
894 | bool nphy_gband_spurwar_en; | 894 | bool nphy_gband_spurwar_en; |
895 | bool nphy_gband_spurwar2_en; | 895 | bool nphy_gband_spurwar2_en; |
896 | bool nphy_aband_spurwar_en; | 896 | bool nphy_aband_spurwar_en; |
897 | uint16 nphy_rccal_value; | 897 | u16 nphy_rccal_value; |
898 | uint16 nphy_crsminpwr[3]; | 898 | u16 nphy_crsminpwr[3]; |
899 | phy_noisevar_buf_t nphy_saved_noisevars; | 899 | phy_noisevar_buf_t nphy_saved_noisevars; |
900 | bool nphy_anarxlpf_adjusted; | 900 | bool nphy_anarxlpf_adjusted; |
901 | bool nphy_crsminpwr_adjusted; | 901 | bool nphy_crsminpwr_adjusted; |
902 | bool nphy_noisevars_adjusted; | 902 | bool nphy_noisevars_adjusted; |
903 | 903 | ||
904 | bool nphy_rxcal_active; | 904 | bool nphy_rxcal_active; |
905 | uint16 radar_percal_mask; | 905 | u16 radar_percal_mask; |
906 | bool dfs_lp_buffer_nphy; | 906 | bool dfs_lp_buffer_nphy; |
907 | 907 | ||
908 | uint16 nphy_fineclockgatecontrol; | 908 | u16 nphy_fineclockgatecontrol; |
909 | 909 | ||
910 | s8 rx2tx_biasentry; | 910 | s8 rx2tx_biasentry; |
911 | 911 | ||
912 | uint16 crsminpwr0; | 912 | u16 crsminpwr0; |
913 | uint16 crsminpwrl0; | 913 | u16 crsminpwrl0; |
914 | uint16 crsminpwru0; | 914 | u16 crsminpwru0; |
915 | int16 noise_crsminpwr_index; | 915 | int16 noise_crsminpwr_index; |
916 | uint16 init_gain_core1; | 916 | u16 init_gain_core1; |
917 | uint16 init_gain_core2; | 917 | u16 init_gain_core2; |
918 | uint16 init_gainb_core1; | 918 | u16 init_gainb_core1; |
919 | uint16 init_gainb_core2; | 919 | u16 init_gainb_core2; |
920 | u8 aci_noise_curr_channel; | 920 | u8 aci_noise_curr_channel; |
921 | uint16 init_gain_rfseq[4]; | 921 | u16 init_gain_rfseq[4]; |
922 | 922 | ||
923 | bool radio_is_on; | 923 | bool radio_is_on; |
924 | 924 | ||
925 | bool nphy_sample_play_lpf_bw_ctl_ovr; | 925 | bool nphy_sample_play_lpf_bw_ctl_ovr; |
926 | 926 | ||
927 | uint16 tbl_data_hi; | 927 | u16 tbl_data_hi; |
928 | uint16 tbl_data_lo; | 928 | u16 tbl_data_lo; |
929 | uint16 tbl_addr; | 929 | u16 tbl_addr; |
930 | 930 | ||
931 | uint tbl_save_id; | 931 | uint tbl_save_id; |
932 | uint tbl_save_offset; | 932 | uint tbl_save_offset; |
@@ -947,7 +947,7 @@ typedef struct _cint32 { | |||
947 | } cint32; | 947 | } cint32; |
948 | 948 | ||
949 | typedef struct radio_regs { | 949 | typedef struct radio_regs { |
950 | uint16 address; | 950 | u16 address; |
951 | uint32 init_a; | 951 | uint32 init_a; |
952 | uint32 init_g; | 952 | uint32 init_g; |
953 | u8 do_init_a; | 953 | u8 do_init_a; |
@@ -955,13 +955,13 @@ typedef struct radio_regs { | |||
955 | } radio_regs_t; | 955 | } radio_regs_t; |
956 | 956 | ||
957 | typedef struct radio_20xx_regs { | 957 | typedef struct radio_20xx_regs { |
958 | uint16 address; | 958 | u16 address; |
959 | u8 init; | 959 | u8 init; |
960 | u8 do_init; | 960 | u8 do_init; |
961 | } radio_20xx_regs_t; | 961 | } radio_20xx_regs_t; |
962 | 962 | ||
963 | typedef struct lcnphy_radio_regs { | 963 | typedef struct lcnphy_radio_regs { |
964 | uint16 address; | 964 | u16 address; |
965 | u8 init_a; | 965 | u8 init_a; |
966 | u8 init_g; | 966 | u8 init_g; |
967 | u8 do_init_a; | 967 | u8 do_init_a; |
@@ -989,20 +989,20 @@ extern int phy_getintvar(phy_info_t *pi, const char *name); | |||
989 | #define PHY_GETVAR(pi, name) phy_getvar(pi, name) | 989 | #define PHY_GETVAR(pi, name) phy_getvar(pi, name) |
990 | #define PHY_GETINTVAR(pi, name) phy_getintvar(pi, name) | 990 | #define PHY_GETINTVAR(pi, name) phy_getintvar(pi, name) |
991 | 991 | ||
992 | extern uint16 read_phy_reg(phy_info_t *pi, uint16 addr); | 992 | extern u16 read_phy_reg(phy_info_t *pi, u16 addr); |
993 | extern void write_phy_reg(phy_info_t *pi, uint16 addr, uint16 val); | 993 | extern void write_phy_reg(phy_info_t *pi, u16 addr, u16 val); |
994 | extern void and_phy_reg(phy_info_t *pi, uint16 addr, uint16 val); | 994 | extern void and_phy_reg(phy_info_t *pi, u16 addr, u16 val); |
995 | extern void or_phy_reg(phy_info_t *pi, uint16 addr, uint16 val); | 995 | extern void or_phy_reg(phy_info_t *pi, u16 addr, u16 val); |
996 | extern void mod_phy_reg(phy_info_t *pi, uint16 addr, uint16 mask, uint16 val); | 996 | extern void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val); |
997 | 997 | ||
998 | extern uint16 read_radio_reg(phy_info_t *pi, uint16 addr); | 998 | extern u16 read_radio_reg(phy_info_t *pi, u16 addr); |
999 | extern void or_radio_reg(phy_info_t *pi, uint16 addr, uint16 val); | 999 | extern void or_radio_reg(phy_info_t *pi, u16 addr, u16 val); |
1000 | extern void and_radio_reg(phy_info_t *pi, uint16 addr, uint16 val); | 1000 | extern void and_radio_reg(phy_info_t *pi, u16 addr, u16 val); |
1001 | extern void mod_radio_reg(phy_info_t *pi, uint16 addr, uint16 mask, | 1001 | extern void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask, |
1002 | uint16 val); | 1002 | u16 val); |
1003 | extern void xor_radio_reg(phy_info_t *pi, uint16 addr, uint16 mask); | 1003 | extern void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask); |
1004 | 1004 | ||
1005 | extern void write_radio_reg(phy_info_t *pi, uint16 addr, uint16 val); | 1005 | extern void write_radio_reg(phy_info_t *pi, u16 addr, u16 val); |
1006 | 1006 | ||
1007 | extern void wlc_phyreg_enter(wlc_phy_t *pih); | 1007 | extern void wlc_phyreg_enter(wlc_phy_t *pih); |
1008 | extern void wlc_phyreg_exit(wlc_phy_t *pih); | 1008 | extern void wlc_phyreg_exit(wlc_phy_t *pih); |
@@ -1010,14 +1010,14 @@ extern void wlc_radioreg_enter(wlc_phy_t *pih); | |||
1010 | extern void wlc_radioreg_exit(wlc_phy_t *pih); | 1010 | extern void wlc_radioreg_exit(wlc_phy_t *pih); |
1011 | 1011 | ||
1012 | extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, | 1012 | extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, |
1013 | uint16 tblAddr, uint16 tblDataHi, | 1013 | u16 tblAddr, u16 tblDataHi, |
1014 | uint16 tblDatalo); | 1014 | u16 tblDatalo); |
1015 | extern void wlc_phy_write_table(phy_info_t *pi, | 1015 | extern void wlc_phy_write_table(phy_info_t *pi, |
1016 | const phytbl_info_t *ptbl_info, uint16 tblAddr, | 1016 | const phytbl_info_t *ptbl_info, u16 tblAddr, |
1017 | uint16 tblDataHi, uint16 tblDatalo); | 1017 | u16 tblDataHi, u16 tblDatalo); |
1018 | extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset, | 1018 | extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset, |
1019 | uint16 tblAddr, uint16 tblDataHi, | 1019 | u16 tblAddr, u16 tblDataHi, |
1020 | uint16 tblDataLo); | 1020 | u16 tblDataLo); |
1021 | extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val); | 1021 | extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val); |
1022 | 1022 | ||
1023 | extern void write_phy_channel_reg(phy_info_t *pi, uint val); | 1023 | extern void write_phy_channel_reg(phy_info_t *pi, uint val); |
@@ -1031,7 +1031,7 @@ extern void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_dB, u8 core); | |||
1031 | extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi, | 1031 | extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi, |
1032 | radio_20xx_regs_t *radioregs); | 1032 | radio_20xx_regs_t *radioregs); |
1033 | extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs, | 1033 | extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs, |
1034 | uint16 core_offset); | 1034 | u16 core_offset); |
1035 | 1035 | ||
1036 | extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi); | 1036 | extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi); |
1037 | 1037 | ||
@@ -1061,7 +1061,7 @@ extern int wlc_phy_channel2freq(uint channel); | |||
1061 | extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint); | 1061 | extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint); |
1062 | extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t); | 1062 | extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t); |
1063 | 1063 | ||
1064 | extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, uint16 mode); | 1064 | extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode); |
1065 | extern s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi); | 1065 | extern s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi); |
1066 | 1066 | ||
1067 | extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi); | 1067 | extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi); |
@@ -1072,7 +1072,7 @@ extern void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index); | |||
1072 | extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable); | 1072 | extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable); |
1073 | extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi); | 1073 | extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi); |
1074 | extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, | 1074 | extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, |
1075 | uint16 max_val, bool iqcalmode); | 1075 | u16 max_val, bool iqcalmode); |
1076 | 1076 | ||
1077 | extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan, | 1077 | extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan, |
1078 | u8 *max_pwr, u8 rate_id); | 1078 | u8 *max_pwr, u8 rate_id); |
@@ -1084,7 +1084,7 @@ extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, | |||
1084 | u8 rate_ofdm_end, | 1084 | u8 rate_ofdm_end, |
1085 | u8 rate_mcs_start); | 1085 | u8 rate_mcs_start); |
1086 | 1086 | ||
1087 | extern uint16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode); | 1087 | extern u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode); |
1088 | extern int16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode); | 1088 | extern int16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode); |
1089 | extern s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode); | 1089 | extern s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode); |
1090 | extern s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode); | 1090 | extern s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode); |
@@ -1111,10 +1111,10 @@ extern uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor, | |||
1111 | 1111 | ||
1112 | extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti); | 1112 | extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti); |
1113 | extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti); | 1113 | extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti); |
1114 | extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, uint16 a, uint16 b); | 1114 | extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b); |
1115 | extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, uint16 didq); | 1115 | extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq); |
1116 | extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, uint16 *a, uint16 *b); | 1116 | extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b); |
1117 | extern uint16 wlc_lcnphy_get_tx_locc(phy_info_t *pi); | 1117 | extern u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi); |
1118 | extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, u8 *ei0, | 1118 | extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, u8 *ei0, |
1119 | u8 *eq0, u8 *fi0, u8 *fq0); | 1119 | u8 *eq0, u8 *fi0, u8 *fq0); |
1120 | extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode); | 1120 | extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode); |
@@ -1173,10 +1173,10 @@ extern void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi); | |||
1173 | extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd); | 1173 | extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd); |
1174 | extern int16 wlc_phy_tempsense_nphy(phy_info_t *pi); | 1174 | extern int16 wlc_phy_tempsense_nphy(phy_info_t *pi); |
1175 | 1175 | ||
1176 | extern uint16 wlc_phy_classifier_nphy(phy_info_t *pi, uint16 mask, uint16 val); | 1176 | extern u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val); |
1177 | 1177 | ||
1178 | extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est, | 1178 | extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est, |
1179 | uint16 num_samps, u8 wait_time, | 1179 | u16 num_samps, u8 wait_time, |
1180 | u8 wait_for_crs); | 1180 | u8 wait_for_crs); |
1181 | 1181 | ||
1182 | extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write, | 1182 | extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write, |
@@ -1190,7 +1190,7 @@ extern void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type); | |||
1190 | extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi); | 1190 | extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi); |
1191 | extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi); | 1191 | extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi); |
1192 | extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi); | 1192 | extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi); |
1193 | extern uint16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi); | 1193 | extern u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi); |
1194 | 1194 | ||
1195 | extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi); | 1195 | extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi); |
1196 | extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain, | 1196 | extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain, |
@@ -1206,7 +1206,7 @@ extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi); | |||
1206 | extern int wlc_phy_aci_scan_nphy(phy_info_t *pi); | 1206 | extern int wlc_phy_aci_scan_nphy(phy_info_t *pi); |
1207 | extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, | 1207 | extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, |
1208 | bool debug); | 1208 | bool debug); |
1209 | extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, uint16 max_val, | 1209 | extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val, |
1210 | u8 mode, u8, bool); | 1210 | u8 mode, u8, bool); |
1211 | extern void wlc_phy_stopplayback_nphy(phy_info_t *pi); | 1211 | extern void wlc_phy_stopplayback_nphy(phy_info_t *pi); |
1212 | extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, | 1212 | extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, |
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_lcn.c b/drivers/staging/brcm80211/phy/wlc_phy_lcn.c index 15aa799312d..0031361cc48 100644 --- a/drivers/staging/brcm80211/phy/wlc_phy_lcn.c +++ b/drivers/staging/brcm80211/phy/wlc_phy_lcn.c | |||
@@ -143,10 +143,10 @@ | |||
143 | wlapi_bmac_read_shm((pi)->sh->physhim, M_UCODE_MACSTAT + OFFSETOF(macstat_t, txallfrm)) | 143 | wlapi_bmac_read_shm((pi)->sh->physhim, M_UCODE_MACSTAT + OFFSETOF(macstat_t, txallfrm)) |
144 | 144 | ||
145 | typedef struct { | 145 | typedef struct { |
146 | uint16 gm_gain; | 146 | u16 gm_gain; |
147 | uint16 pga_gain; | 147 | u16 pga_gain; |
148 | uint16 pad_gain; | 148 | u16 pad_gain; |
149 | uint16 dac_gain; | 149 | u16 dac_gain; |
150 | } lcnphy_txgains_t; | 150 | } lcnphy_txgains_t; |
151 | 151 | ||
152 | typedef enum { | 152 | typedef enum { |
@@ -175,8 +175,8 @@ typedef struct { | |||
175 | } lcnphy_spb_tone_t; | 175 | } lcnphy_spb_tone_t; |
176 | 176 | ||
177 | typedef struct { | 177 | typedef struct { |
178 | uint16 re; | 178 | u16 re; |
179 | uint16 im; | 179 | u16 im; |
180 | } lcnphy_unsign16_struct; | 180 | } lcnphy_unsign16_struct; |
181 | 181 | ||
182 | typedef struct { | 182 | typedef struct { |
@@ -186,8 +186,8 @@ typedef struct { | |||
186 | } lcnphy_iq_est_t; | 186 | } lcnphy_iq_est_t; |
187 | 187 | ||
188 | typedef struct { | 188 | typedef struct { |
189 | uint16 ptcentreTs20; | 189 | u16 ptcentreTs20; |
190 | uint16 ptcentreFactor; | 190 | u16 ptcentreFactor; |
191 | } lcnphy_sfo_cfg_t; | 191 | } lcnphy_sfo_cfg_t; |
192 | 192 | ||
193 | typedef enum { | 193 | typedef enum { |
@@ -195,7 +195,7 @@ typedef enum { | |||
195 | LCNPHY_PAPD_CAL_OFDM | 195 | LCNPHY_PAPD_CAL_OFDM |
196 | } lcnphy_papd_cal_type_t; | 196 | } lcnphy_papd_cal_type_t; |
197 | 197 | ||
198 | typedef uint16 iqcal_gain_params_lcnphy[9]; | 198 | typedef u16 iqcal_gain_params_lcnphy[9]; |
199 | 199 | ||
200 | static const iqcal_gain_params_lcnphy tbl_iqcal_gainparams_lcnphy_2G[] = { | 200 | static const iqcal_gain_params_lcnphy tbl_iqcal_gainparams_lcnphy_2G[] = { |
201 | {0, 0, 0, 0, 0, 0, 0, 0, 0}, | 201 | {0, 0, 0, 0, 0, 0, 0, 0, 0}, |
@@ -205,7 +205,7 @@ static const iqcal_gain_params_lcnphy *tbl_iqcal_gainparams_lcnphy[1] = { | |||
205 | tbl_iqcal_gainparams_lcnphy_2G, | 205 | tbl_iqcal_gainparams_lcnphy_2G, |
206 | }; | 206 | }; |
207 | 207 | ||
208 | static const uint16 iqcal_gainparams_numgains_lcnphy[1] = { | 208 | static const u16 iqcal_gainparams_numgains_lcnphy[1] = { |
209 | sizeof(tbl_iqcal_gainparams_lcnphy_2G) / | 209 | sizeof(tbl_iqcal_gainparams_lcnphy_2G) / |
210 | sizeof(*tbl_iqcal_gainparams_lcnphy_2G), | 210 | sizeof(*tbl_iqcal_gainparams_lcnphy_2G), |
211 | }; | 211 | }; |
@@ -228,7 +228,7 @@ static const lcnphy_sfo_cfg_t lcnphy_sfo_cfg[] = { | |||
228 | }; | 228 | }; |
229 | 229 | ||
230 | static const | 230 | static const |
231 | uint16 lcnphy_iqcal_loft_gainladder[] = { | 231 | u16 lcnphy_iqcal_loft_gainladder[] = { |
232 | ((2 << 8) | 0), | 232 | ((2 << 8) | 0), |
233 | ((3 << 8) | 0), | 233 | ((3 << 8) | 0), |
234 | ((4 << 8) | 0), | 234 | ((4 << 8) | 0), |
@@ -252,7 +252,7 @@ uint16 lcnphy_iqcal_loft_gainladder[] = { | |||
252 | }; | 252 | }; |
253 | 253 | ||
254 | static const | 254 | static const |
255 | uint16 lcnphy_iqcal_ir_gainladder[] = { | 255 | u16 lcnphy_iqcal_ir_gainladder[] = { |
256 | ((1 << 8) | 0), | 256 | ((1 << 8) | 0), |
257 | ((2 << 8) | 0), | 257 | ((2 << 8) | 0), |
258 | ((4 << 8) | 0), | 258 | ((4 << 8) | 0), |
@@ -312,7 +312,7 @@ lcnphy_spb_tone_t lcnphy_spb_tone_3750[] = { | |||
312 | }; | 312 | }; |
313 | 313 | ||
314 | static const | 314 | static const |
315 | uint16 iqlo_loopback_rf_regs[20] = { | 315 | u16 iqlo_loopback_rf_regs[20] = { |
316 | RADIO_2064_REG036, | 316 | RADIO_2064_REG036, |
317 | RADIO_2064_REG11A, | 317 | RADIO_2064_REG11A, |
318 | RADIO_2064_REG03A, | 318 | RADIO_2064_REG03A, |
@@ -336,7 +336,7 @@ uint16 iqlo_loopback_rf_regs[20] = { | |||
336 | }; | 336 | }; |
337 | 337 | ||
338 | static const | 338 | static const |
339 | uint16 tempsense_phy_regs[14] = { | 339 | u16 tempsense_phy_regs[14] = { |
340 | 0x503, | 340 | 0x503, |
341 | 0x4a4, | 341 | 0x4a4, |
342 | 0x4d0, | 342 | 0x4d0, |
@@ -354,7 +354,7 @@ uint16 tempsense_phy_regs[14] = { | |||
354 | }; | 354 | }; |
355 | 355 | ||
356 | static const | 356 | static const |
357 | uint16 rxiq_cal_rf_reg[11] = { | 357 | u16 rxiq_cal_rf_reg[11] = { |
358 | RADIO_2064_REG098, | 358 | RADIO_2064_REG098, |
359 | RADIO_2064_REG116, | 359 | RADIO_2064_REG116, |
360 | RADIO_2064_REG12C, | 360 | RADIO_2064_REG12C, |
@@ -892,7 +892,7 @@ lcnphy_radio_regs_t lcnphy_radio_regs_2064[] = { | |||
892 | #define LCNPHY_NUM_DIG_FILT_COEFFS 16 | 892 | #define LCNPHY_NUM_DIG_FILT_COEFFS 16 |
893 | #define LCNPHY_NUM_TX_DIG_FILTERS_CCK 13 | 893 | #define LCNPHY_NUM_TX_DIG_FILTERS_CCK 13 |
894 | 894 | ||
895 | uint16 | 895 | u16 |
896 | LCNPHY_txdigfiltcoeffs_cck[LCNPHY_NUM_TX_DIG_FILTERS_CCK] | 896 | LCNPHY_txdigfiltcoeffs_cck[LCNPHY_NUM_TX_DIG_FILTERS_CCK] |
897 | [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = { | 897 | [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = { |
898 | {0, 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, 1582, 64, | 898 | {0, 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, 1582, 64, |
@@ -924,7 +924,7 @@ uint16 | |||
924 | }; | 924 | }; |
925 | 925 | ||
926 | #define LCNPHY_NUM_TX_DIG_FILTERS_OFDM 3 | 926 | #define LCNPHY_NUM_TX_DIG_FILTERS_OFDM 3 |
927 | uint16 | 927 | u16 |
928 | LCNPHY_txdigfiltcoeffs_ofdm[LCNPHY_NUM_TX_DIG_FILTERS_OFDM] | 928 | LCNPHY_txdigfiltcoeffs_ofdm[LCNPHY_NUM_TX_DIG_FILTERS_OFDM] |
929 | [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = { | 929 | [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = { |
930 | {0, 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, 0x0, | 930 | {0, 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, 0x0, |
@@ -938,12 +938,12 @@ uint16 | |||
938 | #define wlc_lcnphy_set_start_tx_pwr_idx(pi, idx) \ | 938 | #define wlc_lcnphy_set_start_tx_pwr_idx(pi, idx) \ |
939 | mod_phy_reg(pi, 0x4a4, \ | 939 | mod_phy_reg(pi, 0x4a4, \ |
940 | (0x1ff << 0), \ | 940 | (0x1ff << 0), \ |
941 | (uint16)(idx) << 0) | 941 | (u16)(idx) << 0) |
942 | 942 | ||
943 | #define wlc_lcnphy_set_tx_pwr_npt(pi, npt) \ | 943 | #define wlc_lcnphy_set_tx_pwr_npt(pi, npt) \ |
944 | mod_phy_reg(pi, 0x4a5, \ | 944 | mod_phy_reg(pi, 0x4a5, \ |
945 | (0x7 << 8), \ | 945 | (0x7 << 8), \ |
946 | (uint16)(npt) << 8) | 946 | (u16)(npt) << 8) |
947 | 947 | ||
948 | #define wlc_lcnphy_get_tx_pwr_ctrl(pi) \ | 948 | #define wlc_lcnphy_get_tx_pwr_ctrl(pi) \ |
949 | (read_phy_reg((pi), 0x4a4) & \ | 949 | (read_phy_reg((pi), 0x4a4) & \ |
@@ -967,7 +967,7 @@ uint16 | |||
967 | #define wlc_lcnphy_set_target_tx_pwr(pi, target) \ | 967 | #define wlc_lcnphy_set_target_tx_pwr(pi, target) \ |
968 | mod_phy_reg(pi, 0x4a7, \ | 968 | mod_phy_reg(pi, 0x4a7, \ |
969 | (0xff << 0), \ | 969 | (0xff << 0), \ |
970 | (uint16)(target) << 0) | 970 | (u16)(target) << 0) |
971 | 971 | ||
972 | #define wlc_radio_2064_rcal_done(pi) (0 != (read_radio_reg(pi, RADIO_2064_REG05C) & 0x20)) | 972 | #define wlc_radio_2064_rcal_done(pi) (0 != (read_radio_reg(pi, RADIO_2064_REG05C) & 0x20)) |
973 | #define tempsense_done(pi) (0x8000 == (read_phy_reg(pi, 0x476) & 0x8000)) | 973 | #define tempsense_done(pi) (0x8000 == (read_phy_reg(pi, 0x476) & 0x8000)) |
@@ -979,12 +979,12 @@ uint16 | |||
979 | static uint32 wlc_lcnphy_qdiv_roundup(uint32 divident, uint32 divisor, | 979 | static uint32 wlc_lcnphy_qdiv_roundup(uint32 divident, uint32 divisor, |
980 | u8 precision); | 980 | u8 precision); |
981 | static void wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi, | 981 | static void wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi, |
982 | uint16 ext_lna, uint16 trsw, | 982 | u16 ext_lna, u16 trsw, |
983 | uint16 biq2, uint16 biq1, | 983 | u16 biq2, u16 biq1, |
984 | uint16 tia, uint16 lna2, | 984 | u16 tia, u16 lna2, |
985 | uint16 lna1); | 985 | u16 lna1); |
986 | static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi); | 986 | static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi); |
987 | static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, uint16 gain); | 987 | static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, u16 gain); |
988 | static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx); | 988 | static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx); |
989 | static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0); | 989 | static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0); |
990 | static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi); | 990 | static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi); |
@@ -994,10 +994,10 @@ static void wlc_lcnphy_toggle_afe_pwdn(phy_info_t *pi); | |||
994 | static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable); | 994 | static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable); |
995 | static void wlc_lcnphy_set_tx_gain(phy_info_t *pi, | 995 | static void wlc_lcnphy_set_tx_gain(phy_info_t *pi, |
996 | lcnphy_txgains_t *target_gains); | 996 | lcnphy_txgains_t *target_gains); |
997 | static bool wlc_lcnphy_rx_iq_est(phy_info_t *pi, uint16 num_samps, | 997 | static bool wlc_lcnphy_rx_iq_est(phy_info_t *pi, u16 num_samps, |
998 | u8 wait_time, lcnphy_iq_est_t *iq_est); | 998 | u8 wait_time, lcnphy_iq_est_t *iq_est); |
999 | static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, uint16 num_samps); | 999 | static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps); |
1000 | static uint16 wlc_lcnphy_get_pa_gain(phy_info_t *pi); | 1000 | static u16 wlc_lcnphy_get_pa_gain(phy_info_t *pi); |
1001 | static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode); | 1001 | static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode); |
1002 | extern void wlc_lcnphy_tx_pwr_ctrl_init(wlc_phy_t *ppi); | 1002 | extern void wlc_lcnphy_tx_pwr_ctrl_init(wlc_phy_t *ppi); |
1003 | extern void wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng, | 1003 | extern void wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng, |
@@ -1010,12 +1010,12 @@ static void wlc_lcnphy_load_tx_gain_table(phy_info_t *pi, | |||
1010 | const lcnphy_tx_gain_tbl_entry *g); | 1010 | const lcnphy_tx_gain_tbl_entry *g); |
1011 | 1011 | ||
1012 | static void wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, | 1012 | static void wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, |
1013 | uint16 thresh, int16 *ptr, int mode); | 1013 | u16 thresh, int16 *ptr, int mode); |
1014 | static int wlc_lcnphy_calc_floor(int16 coeff, int type); | 1014 | static int wlc_lcnphy_calc_floor(int16 coeff, int type); |
1015 | static void wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, | 1015 | static void wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, |
1016 | uint16 *values_to_save); | 1016 | u16 *values_to_save); |
1017 | static void wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi, | 1017 | static void wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi, |
1018 | uint16 *values_to_save); | 1018 | u16 *values_to_save); |
1019 | static void wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, int16 coeff_x, | 1019 | static void wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, int16 coeff_x, |
1020 | int16 coeff_y); | 1020 | int16 coeff_y); |
1021 | static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type); | 1021 | static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type); |
@@ -1035,7 +1035,7 @@ static void wlc_lcnphy_rcal(phy_info_t *pi); | |||
1035 | static void wlc_lcnphy_txrx_spur_avoidance_mode(phy_info_t *pi, bool enable); | 1035 | static void wlc_lcnphy_txrx_spur_avoidance_mode(phy_info_t *pi, bool enable); |
1036 | static int wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm, | 1036 | static int wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm, |
1037 | int16 filt_type); | 1037 | int16 filt_type); |
1038 | static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, uint16 a, uint16 b); | 1038 | static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, u16 a, u16 b); |
1039 | 1039 | ||
1040 | void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti) | 1040 | void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti) |
1041 | { | 1041 | { |
@@ -1140,7 +1140,7 @@ s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi) | |||
1140 | return index; | 1140 | return index; |
1141 | } | 1141 | } |
1142 | 1142 | ||
1143 | static uint32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, uint16 nsamples) | 1143 | static uint32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, u16 nsamples) |
1144 | { | 1144 | { |
1145 | lcnphy_iq_est_t iq_est = { 0, 0, 0 }; | 1145 | lcnphy_iq_est_t iq_est = { 0, 0, 0 }; |
1146 | 1146 | ||
@@ -1151,7 +1151,7 @@ static uint32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, uint16 nsamples) | |||
1151 | 1151 | ||
1152 | void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel) | 1152 | void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel) |
1153 | { | 1153 | { |
1154 | uint16 afectrlovr, afectrlovrval; | 1154 | u16 afectrlovr, afectrlovrval; |
1155 | afectrlovr = read_phy_reg(pi, 0x43b); | 1155 | afectrlovr = read_phy_reg(pi, 0x43b); |
1156 | afectrlovrval = read_phy_reg(pi, 0x43c); | 1156 | afectrlovrval = read_phy_reg(pi, 0x43c); |
1157 | if (channel != 0) { | 1157 | if (channel != 0) { |
@@ -1182,7 +1182,7 @@ void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel) | |||
1182 | 1182 | ||
1183 | static void wlc_lcnphy_toggle_afe_pwdn(phy_info_t *pi) | 1183 | static void wlc_lcnphy_toggle_afe_pwdn(phy_info_t *pi) |
1184 | { | 1184 | { |
1185 | uint16 save_AfeCtrlOvrVal, save_AfeCtrlOvr; | 1185 | u16 save_AfeCtrlOvrVal, save_AfeCtrlOvr; |
1186 | 1186 | ||
1187 | save_AfeCtrlOvrVal = read_phy_reg(pi, 0x43c); | 1187 | save_AfeCtrlOvrVal = read_phy_reg(pi, 0x43c); |
1188 | save_AfeCtrlOvr = read_phy_reg(pi, 0x43b); | 1188 | save_AfeCtrlOvr = read_phy_reg(pi, 0x43b); |
@@ -1253,9 +1253,9 @@ void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec) | |||
1253 | 1253 | ||
1254 | } | 1254 | } |
1255 | 1255 | ||
1256 | static void wlc_lcnphy_set_dac_gain(phy_info_t *pi, uint16 dac_gain) | 1256 | static void wlc_lcnphy_set_dac_gain(phy_info_t *pi, u16 dac_gain) |
1257 | { | 1257 | { |
1258 | uint16 dac_ctrl; | 1258 | u16 dac_ctrl; |
1259 | 1259 | ||
1260 | dac_ctrl = (read_phy_reg(pi, 0x439) >> 0); | 1260 | dac_ctrl = (read_phy_reg(pi, 0x439) >> 0); |
1261 | dac_ctrl = dac_ctrl & 0xc7f; | 1261 | dac_ctrl = dac_ctrl & 0xc7f; |
@@ -1266,7 +1266,7 @@ static void wlc_lcnphy_set_dac_gain(phy_info_t *pi, uint16 dac_gain) | |||
1266 | 1266 | ||
1267 | static void wlc_lcnphy_set_tx_gain_override(phy_info_t *pi, bool bEnable) | 1267 | static void wlc_lcnphy_set_tx_gain_override(phy_info_t *pi, bool bEnable) |
1268 | { | 1268 | { |
1269 | uint16 bit = bEnable ? 1 : 0; | 1269 | u16 bit = bEnable ? 1 : 0; |
1270 | 1270 | ||
1271 | mod_phy_reg(pi, 0x4b0, (0x1 << 7), bit << 7); | 1271 | mod_phy_reg(pi, 0x4b0, (0x1 << 7), bit << 7); |
1272 | 1272 | ||
@@ -1275,9 +1275,9 @@ static void wlc_lcnphy_set_tx_gain_override(phy_info_t *pi, bool bEnable) | |||
1275 | mod_phy_reg(pi, 0x43b, (0x1 << 6), bit << 6); | 1275 | mod_phy_reg(pi, 0x43b, (0x1 << 6), bit << 6); |
1276 | } | 1276 | } |
1277 | 1277 | ||
1278 | static uint16 wlc_lcnphy_get_pa_gain(phy_info_t *pi) | 1278 | static u16 wlc_lcnphy_get_pa_gain(phy_info_t *pi) |
1279 | { | 1279 | { |
1280 | uint16 pa_gain; | 1280 | u16 pa_gain; |
1281 | 1281 | ||
1282 | pa_gain = (read_phy_reg(pi, 0x4fb) & | 1282 | pa_gain = (read_phy_reg(pi, 0x4fb) & |
1283 | LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK) >> | 1283 | LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK) >> |
@@ -1289,7 +1289,7 @@ static uint16 wlc_lcnphy_get_pa_gain(phy_info_t *pi) | |||
1289 | static void | 1289 | static void |
1290 | wlc_lcnphy_set_tx_gain(phy_info_t *pi, lcnphy_txgains_t *target_gains) | 1290 | wlc_lcnphy_set_tx_gain(phy_info_t *pi, lcnphy_txgains_t *target_gains) |
1291 | { | 1291 | { |
1292 | uint16 pa_gain = wlc_lcnphy_get_pa_gain(pi); | 1292 | u16 pa_gain = wlc_lcnphy_get_pa_gain(pi); |
1293 | 1293 | ||
1294 | mod_phy_reg(pi, 0x4b5, | 1294 | mod_phy_reg(pi, 0x4b5, |
1295 | (0xffff << 0), | 1295 | (0xffff << 0), |
@@ -1314,7 +1314,7 @@ wlc_lcnphy_set_tx_gain(phy_info_t *pi, lcnphy_txgains_t *target_gains) | |||
1314 | 1314 | ||
1315 | static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0) | 1315 | static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0) |
1316 | { | 1316 | { |
1317 | uint16 m0m1 = (uint16) m0 << 8; | 1317 | u16 m0m1 = (u16) m0 << 8; |
1318 | phytbl_info_t tab; | 1318 | phytbl_info_t tab; |
1319 | 1319 | ||
1320 | tab.tbl_ptr = &m0m1; | 1320 | tab.tbl_ptr = &m0m1; |
@@ -1393,9 +1393,9 @@ static void wlc_lcnphy_set_tssi_mux(phy_info_t *pi, lcnphy_tssi_mode_t pos) | |||
1393 | } | 1393 | } |
1394 | } | 1394 | } |
1395 | 1395 | ||
1396 | static uint16 wlc_lcnphy_rfseq_tbl_adc_pwrup(phy_info_t *pi) | 1396 | static u16 wlc_lcnphy_rfseq_tbl_adc_pwrup(phy_info_t *pi) |
1397 | { | 1397 | { |
1398 | uint16 N1, N2, N3, N4, N5, N6, N; | 1398 | u16 N1, N2, N3, N4, N5, N6, N; |
1399 | N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0)) | 1399 | N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0)) |
1400 | >> 0); | 1400 | >> 0); |
1401 | N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12)) | 1401 | N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12)) |
@@ -1416,7 +1416,7 @@ static uint16 wlc_lcnphy_rfseq_tbl_adc_pwrup(phy_info_t *pi) | |||
1416 | 1416 | ||
1417 | static void wlc_lcnphy_pwrctrl_rssiparams(phy_info_t *pi) | 1417 | static void wlc_lcnphy_pwrctrl_rssiparams(phy_info_t *pi) |
1418 | { | 1418 | { |
1419 | uint16 auxpga_vmid, auxpga_vmid_temp, auxpga_gain_temp; | 1419 | u16 auxpga_vmid, auxpga_vmid_temp, auxpga_gain_temp; |
1420 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 1420 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
1421 | 1421 | ||
1422 | auxpga_vmid = | 1422 | auxpga_vmid = |
@@ -1574,7 +1574,7 @@ static void wlc_lcnphy_tssi_setup(phy_info_t *pi) | |||
1574 | 1574 | ||
1575 | void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi) | 1575 | void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi) |
1576 | { | 1576 | { |
1577 | uint16 tx_cnt, tx_total, npt; | 1577 | u16 tx_cnt, tx_total, npt; |
1578 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 1578 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
1579 | 1579 | ||
1580 | tx_total = wlc_lcnphy_total_tx_frames(pi); | 1580 | tx_total = wlc_lcnphy_total_tx_frames(pi); |
@@ -1648,7 +1648,7 @@ static void wlc_lcnphy_set_tx_pwr_soft_ctrl(phy_info_t *pi, s8 index) | |||
1648 | uint32 cck_offset[4] = { 22, 22, 22, 22 }; | 1648 | uint32 cck_offset[4] = { 22, 22, 22, 22 }; |
1649 | uint32 ofdm_offset, reg_offset_cck; | 1649 | uint32 ofdm_offset, reg_offset_cck; |
1650 | int i; | 1650 | int i; |
1651 | uint16 index2; | 1651 | u16 index2; |
1652 | phytbl_info_t tab; | 1652 | phytbl_info_t tab; |
1653 | 1653 | ||
1654 | if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) | 1654 | if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) |
@@ -1689,7 +1689,7 @@ static void wlc_lcnphy_set_tx_pwr_soft_ctrl(phy_info_t *pi, s8 index) | |||
1689 | 1689 | ||
1690 | mod_phy_reg(pi, 0x4a9, (0x1 << 15), (1) << 15); | 1690 | mod_phy_reg(pi, 0x4a9, (0x1 << 15), (1) << 15); |
1691 | 1691 | ||
1692 | index2 = (uint16) (index * 2); | 1692 | index2 = (u16) (index * 2); |
1693 | mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0); | 1693 | mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0); |
1694 | 1694 | ||
1695 | mod_phy_reg(pi, 0x6a3, (0x1 << 4), (0) << 4); | 1695 | mod_phy_reg(pi, 0x6a3, (0x1 << 4), (0) << 4); |
@@ -1701,7 +1701,7 @@ static s8 wlc_lcnphy_tempcompensated_txpwrctrl(phy_info_t *pi) | |||
1701 | s8 index, delta_brd, delta_temp, new_index, tempcorrx; | 1701 | s8 index, delta_brd, delta_temp, new_index, tempcorrx; |
1702 | int16 manp, meas_temp, temp_diff; | 1702 | int16 manp, meas_temp, temp_diff; |
1703 | bool neg = 0; | 1703 | bool neg = 0; |
1704 | uint16 temp; | 1704 | u16 temp; |
1705 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 1705 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
1706 | 1706 | ||
1707 | if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) | 1707 | if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) |
@@ -1715,7 +1715,7 @@ static s8 wlc_lcnphy_tempcompensated_txpwrctrl(phy_info_t *pi) | |||
1715 | if (pi_lcn->lcnphy_tempsense_slope == 0) { | 1715 | if (pi_lcn->lcnphy_tempsense_slope == 0) { |
1716 | return index; | 1716 | return index; |
1717 | } | 1717 | } |
1718 | temp = (uint16) wlc_lcnphy_tempsense(pi, 0); | 1718 | temp = (u16) wlc_lcnphy_tempsense(pi, 0); |
1719 | meas_temp = LCNPHY_TEMPSENSE(temp); | 1719 | meas_temp = LCNPHY_TEMPSENSE(temp); |
1720 | 1720 | ||
1721 | if (pi->tx_power_min != 0) { | 1721 | if (pi->tx_power_min != 0) { |
@@ -1761,10 +1761,10 @@ static s8 wlc_lcnphy_tempcompensated_txpwrctrl(phy_info_t *pi) | |||
1761 | return new_index; | 1761 | return new_index; |
1762 | } | 1762 | } |
1763 | 1763 | ||
1764 | static uint16 wlc_lcnphy_set_tx_pwr_ctrl_mode(phy_info_t *pi, uint16 mode) | 1764 | static u16 wlc_lcnphy_set_tx_pwr_ctrl_mode(phy_info_t *pi, u16 mode) |
1765 | { | 1765 | { |
1766 | 1766 | ||
1767 | uint16 current_mode = mode; | 1767 | u16 current_mode = mode; |
1768 | if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) && | 1768 | if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) && |
1769 | mode == LCNPHY_TX_PWR_CTRL_HW) | 1769 | mode == LCNPHY_TX_PWR_CTRL_HW) |
1770 | current_mode = LCNPHY_TX_PWR_CTRL_TEMPBASED; | 1770 | current_mode = LCNPHY_TX_PWR_CTRL_TEMPBASED; |
@@ -1774,9 +1774,9 @@ static uint16 wlc_lcnphy_set_tx_pwr_ctrl_mode(phy_info_t *pi, uint16 mode) | |||
1774 | return current_mode; | 1774 | return current_mode; |
1775 | } | 1775 | } |
1776 | 1776 | ||
1777 | void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, uint16 mode) | 1777 | void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode) |
1778 | { | 1778 | { |
1779 | uint16 old_mode = wlc_lcnphy_get_tx_pwr_ctrl(pi); | 1779 | u16 old_mode = wlc_lcnphy_get_tx_pwr_ctrl(pi); |
1780 | s8 index; | 1780 | s8 index; |
1781 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 1781 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
1782 | 1782 | ||
@@ -1852,40 +1852,40 @@ wlc_lcnphy_tx_iqlo_cal(phy_info_t *pi, | |||
1852 | { | 1852 | { |
1853 | 1853 | ||
1854 | lcnphy_txgains_t cal_gains, temp_gains; | 1854 | lcnphy_txgains_t cal_gains, temp_gains; |
1855 | uint16 hash; | 1855 | u16 hash; |
1856 | u8 band_idx; | 1856 | u8 band_idx; |
1857 | int j; | 1857 | int j; |
1858 | uint16 ncorr_override[5]; | 1858 | u16 ncorr_override[5]; |
1859 | uint16 syst_coeffs[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | 1859 | u16 syst_coeffs[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
1860 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 | 1860 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 |
1861 | }; | 1861 | }; |
1862 | 1862 | ||
1863 | uint16 commands_fullcal[] = { | 1863 | u16 commands_fullcal[] = { |
1864 | 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 }; | 1864 | 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 }; |
1865 | 1865 | ||
1866 | uint16 commands_recal[] = { | 1866 | u16 commands_recal[] = { |
1867 | 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 }; | 1867 | 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 }; |
1868 | 1868 | ||
1869 | uint16 command_nums_fullcal[] = { | 1869 | u16 command_nums_fullcal[] = { |
1870 | 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 }; | 1870 | 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 }; |
1871 | 1871 | ||
1872 | uint16 command_nums_recal[] = { | 1872 | u16 command_nums_recal[] = { |
1873 | 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 }; | 1873 | 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 }; |
1874 | uint16 *command_nums = command_nums_fullcal; | 1874 | u16 *command_nums = command_nums_fullcal; |
1875 | 1875 | ||
1876 | uint16 *start_coeffs = NULL, *cal_cmds = NULL, cal_type, diq_start; | 1876 | u16 *start_coeffs = NULL, *cal_cmds = NULL, cal_type, diq_start; |
1877 | uint16 tx_pwr_ctrl_old, save_txpwrctrlrfctrl2; | 1877 | u16 tx_pwr_ctrl_old, save_txpwrctrlrfctrl2; |
1878 | uint16 save_sslpnCalibClkEnCtrl, save_sslpnRxFeClkEnCtrl; | 1878 | u16 save_sslpnCalibClkEnCtrl, save_sslpnRxFeClkEnCtrl; |
1879 | bool tx_gain_override_old; | 1879 | bool tx_gain_override_old; |
1880 | lcnphy_txgains_t old_gains; | 1880 | lcnphy_txgains_t old_gains; |
1881 | uint i, n_cal_cmds = 0, n_cal_start = 0; | 1881 | uint i, n_cal_cmds = 0, n_cal_start = 0; |
1882 | uint16 *values_to_save; | 1882 | u16 *values_to_save; |
1883 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 1883 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
1884 | 1884 | ||
1885 | if (NORADIO_ENAB(pi->pubpi)) | 1885 | if (NORADIO_ENAB(pi->pubpi)) |
1886 | return; | 1886 | return; |
1887 | 1887 | ||
1888 | values_to_save = MALLOC(pi->sh->osh, sizeof(uint16) * 20); | 1888 | values_to_save = MALLOC(pi->sh->osh, sizeof(u16) * 20); |
1889 | if (NULL == values_to_save) { | 1889 | if (NULL == values_to_save) { |
1890 | return; | 1890 | return; |
1891 | } | 1891 | } |
@@ -1997,9 +1997,9 @@ wlc_lcnphy_tx_iqlo_cal(phy_info_t *pi, | |||
1997 | write_phy_reg(pi, 0x6da, 0xffff); | 1997 | write_phy_reg(pi, 0x6da, 0xffff); |
1998 | 1998 | ||
1999 | for (i = n_cal_start; i < n_cal_cmds; i++) { | 1999 | for (i = n_cal_start; i < n_cal_cmds; i++) { |
2000 | uint16 zero_diq = 0; | 2000 | u16 zero_diq = 0; |
2001 | uint16 best_coeffs[11]; | 2001 | u16 best_coeffs[11]; |
2002 | uint16 command_num; | 2002 | u16 command_num; |
2003 | 2003 | ||
2004 | cal_type = (cal_cmds[i] & 0x0f00) >> 8; | 2004 | cal_type = (cal_cmds[i] & 0x0f00) >> 8; |
2005 | 2005 | ||
@@ -2064,7 +2064,7 @@ wlc_lcnphy_tx_iqlo_cal(phy_info_t *pi, | |||
2064 | 2064 | ||
2065 | cleanup: | 2065 | cleanup: |
2066 | wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, values_to_save); | 2066 | wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, values_to_save); |
2067 | MFREE(pi->sh->osh, values_to_save, 20 * sizeof(uint16)); | 2067 | MFREE(pi->sh->osh, values_to_save, 20 * sizeof(u16)); |
2068 | 2068 | ||
2069 | if (!keep_tone) | 2069 | if (!keep_tone) |
2070 | wlc_lcnphy_stop_tx_tone(pi); | 2070 | wlc_lcnphy_stop_tx_tone(pi); |
@@ -2087,14 +2087,14 @@ static void wlc_lcnphy_idle_tssi_est(wlc_phy_t *ppi) | |||
2087 | bool suspend, tx_gain_override_old; | 2087 | bool suspend, tx_gain_override_old; |
2088 | lcnphy_txgains_t old_gains; | 2088 | lcnphy_txgains_t old_gains; |
2089 | phy_info_t *pi = (phy_info_t *) ppi; | 2089 | phy_info_t *pi = (phy_info_t *) ppi; |
2090 | uint16 idleTssi, idleTssi0_2C, idleTssi0_OB, idleTssi0_regvalue_OB, | 2090 | u16 idleTssi, idleTssi0_2C, idleTssi0_OB, idleTssi0_regvalue_OB, |
2091 | idleTssi0_regvalue_2C; | 2091 | idleTssi0_regvalue_2C; |
2092 | uint16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); | 2092 | u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); |
2093 | uint16 SAVE_lpfgain = read_radio_reg(pi, RADIO_2064_REG112); | 2093 | u16 SAVE_lpfgain = read_radio_reg(pi, RADIO_2064_REG112); |
2094 | uint16 SAVE_jtag_bb_afe_switch = | 2094 | u16 SAVE_jtag_bb_afe_switch = |
2095 | read_radio_reg(pi, RADIO_2064_REG007) & 1; | 2095 | read_radio_reg(pi, RADIO_2064_REG007) & 1; |
2096 | uint16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10; | 2096 | u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10; |
2097 | uint16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4; | 2097 | u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4; |
2098 | idleTssi = read_phy_reg(pi, 0x4ab); | 2098 | idleTssi = read_phy_reg(pi, 0x4ab); |
2099 | suspend = | 2099 | suspend = |
2100 | (0 == | 2100 | (0 == |
@@ -2151,14 +2151,14 @@ static void wlc_lcnphy_idle_tssi_est(wlc_phy_t *ppi) | |||
2151 | static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode) | 2151 | static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode) |
2152 | { | 2152 | { |
2153 | bool suspend; | 2153 | bool suspend; |
2154 | uint16 save_txpwrCtrlEn; | 2154 | u16 save_txpwrCtrlEn; |
2155 | u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain; | 2155 | u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain; |
2156 | uint16 auxpga_vmid; | 2156 | u16 auxpga_vmid; |
2157 | phytbl_info_t tab; | 2157 | phytbl_info_t tab; |
2158 | uint32 val; | 2158 | uint32 val; |
2159 | u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025, | 2159 | u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025, |
2160 | save_reg112; | 2160 | save_reg112; |
2161 | uint16 values_to_save[14]; | 2161 | u16 values_to_save[14]; |
2162 | s8 index; | 2162 | s8 index; |
2163 | int i; | 2163 | int i; |
2164 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 2164 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
@@ -2257,7 +2257,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode) | |||
2257 | auxpga_gain = 2; | 2257 | auxpga_gain = 2; |
2258 | } | 2258 | } |
2259 | auxpga_vmid = | 2259 | auxpga_vmid = |
2260 | (uint16) ((2 << 8) | (auxpga_vmidcourse << 4) | auxpga_vmidfine); | 2260 | (u16) ((2 << 8) | (auxpga_vmidcourse << 4) | auxpga_vmidfine); |
2261 | mod_phy_reg(pi, 0x4d8, (0x1 << 0), (1) << 0); | 2261 | mod_phy_reg(pi, 0x4d8, (0x1 << 0), (1) << 0); |
2262 | 2262 | ||
2263 | mod_phy_reg(pi, 0x4d8, (0x3ff << 2), (auxpga_vmid) << 2); | 2263 | mod_phy_reg(pi, 0x4d8, (0x3ff << 2), (auxpga_vmid) << 2); |
@@ -2274,12 +2274,12 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode) | |||
2274 | if (!tempsense_done(pi)) | 2274 | if (!tempsense_done(pi)) |
2275 | OSL_DELAY(10); | 2275 | OSL_DELAY(10); |
2276 | 2276 | ||
2277 | write_radio_reg(pi, RADIO_2064_REG007, (uint16) save_reg007); | 2277 | write_radio_reg(pi, RADIO_2064_REG007, (u16) save_reg007); |
2278 | write_radio_reg(pi, RADIO_2064_REG0FF, (uint16) save_reg0FF); | 2278 | write_radio_reg(pi, RADIO_2064_REG0FF, (u16) save_reg0FF); |
2279 | write_radio_reg(pi, RADIO_2064_REG11F, (uint16) save_reg11F); | 2279 | write_radio_reg(pi, RADIO_2064_REG11F, (u16) save_reg11F); |
2280 | write_radio_reg(pi, RADIO_2064_REG005, (uint16) save_reg005); | 2280 | write_radio_reg(pi, RADIO_2064_REG005, (u16) save_reg005); |
2281 | write_radio_reg(pi, RADIO_2064_REG025, (uint16) save_reg025); | 2281 | write_radio_reg(pi, RADIO_2064_REG025, (u16) save_reg025); |
2282 | write_radio_reg(pi, RADIO_2064_REG112, (uint16) save_reg112); | 2282 | write_radio_reg(pi, RADIO_2064_REG112, (u16) save_reg112); |
2283 | for (i = 0; i < 14; i++) | 2283 | for (i = 0; i < 14; i++) |
2284 | write_phy_reg(pi, tempsense_phy_regs[i], values_to_save[i]); | 2284 | write_phy_reg(pi, tempsense_phy_regs[i], values_to_save[i]); |
2285 | wlc_lcnphy_set_tx_pwr_by_index(pi, (int)index); | 2285 | wlc_lcnphy_set_tx_pwr_by_index(pi, (int)index); |
@@ -2370,7 +2370,7 @@ void WLBANDINITFN(wlc_lcnphy_tx_pwr_ctrl_init) (wlc_phy_t *ppi) | |||
2370 | 2370 | ||
2371 | static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi) | 2371 | static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi) |
2372 | { | 2372 | { |
2373 | uint16 m0m1; | 2373 | u16 m0m1; |
2374 | phytbl_info_t tab; | 2374 | phytbl_info_t tab; |
2375 | 2375 | ||
2376 | tab.tbl_ptr = &m0m1; | 2376 | tab.tbl_ptr = &m0m1; |
@@ -2383,7 +2383,7 @@ static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi) | |||
2383 | return (u8) ((m0m1 & 0xff00) >> 8); | 2383 | return (u8) ((m0m1 & 0xff00) >> 8); |
2384 | } | 2384 | } |
2385 | 2385 | ||
2386 | static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, uint16 gain) | 2386 | static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, u16 gain) |
2387 | { | 2387 | { |
2388 | mod_phy_reg(pi, 0x4fb, | 2388 | mod_phy_reg(pi, 0x4fb, |
2389 | LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK, | 2389 | LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK, |
@@ -2405,13 +2405,13 @@ wlc_lcnphy_get_radio_loft(phy_info_t *pi, | |||
2405 | 2405 | ||
2406 | static void wlc_lcnphy_get_tx_gain(phy_info_t *pi, lcnphy_txgains_t *gains) | 2406 | static void wlc_lcnphy_get_tx_gain(phy_info_t *pi, lcnphy_txgains_t *gains) |
2407 | { | 2407 | { |
2408 | uint16 dac_gain; | 2408 | u16 dac_gain; |
2409 | 2409 | ||
2410 | dac_gain = read_phy_reg(pi, 0x439) >> 0; | 2410 | dac_gain = read_phy_reg(pi, 0x439) >> 0; |
2411 | gains->dac_gain = (dac_gain & 0x380) >> 7; | 2411 | gains->dac_gain = (dac_gain & 0x380) >> 7; |
2412 | 2412 | ||
2413 | { | 2413 | { |
2414 | uint16 rfgain0, rfgain1; | 2414 | u16 rfgain0, rfgain1; |
2415 | 2415 | ||
2416 | rfgain0 = (read_phy_reg(pi, 0x4b5) & (0xffff << 0)) >> 0; | 2416 | rfgain0 = (read_phy_reg(pi, 0x4b5) & (0xffff << 0)) >> 0; |
2417 | rfgain1 = (read_phy_reg(pi, 0x4fb) & (0x7fff << 0)) >> 0; | 2417 | rfgain1 = (read_phy_reg(pi, 0x4fb) & (0x7fff << 0)) >> 0; |
@@ -2422,10 +2422,10 @@ static void wlc_lcnphy_get_tx_gain(phy_info_t *pi, lcnphy_txgains_t *gains) | |||
2422 | } | 2422 | } |
2423 | } | 2423 | } |
2424 | 2424 | ||
2425 | void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, uint16 a, uint16 b) | 2425 | void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b) |
2426 | { | 2426 | { |
2427 | phytbl_info_t tab; | 2427 | phytbl_info_t tab; |
2428 | uint16 iqcc[2]; | 2428 | u16 iqcc[2]; |
2429 | 2429 | ||
2430 | iqcc[0] = a; | 2430 | iqcc[0] = a; |
2431 | iqcc[1] = b; | 2431 | iqcc[1] = b; |
@@ -2438,7 +2438,7 @@ void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, uint16 a, uint16 b) | |||
2438 | wlc_lcnphy_write_table(pi, &tab); | 2438 | wlc_lcnphy_write_table(pi, &tab); |
2439 | } | 2439 | } |
2440 | 2440 | ||
2441 | void wlc_lcnphy_set_tx_locc(phy_info_t *pi, uint16 didq) | 2441 | void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq) |
2442 | { | 2442 | { |
2443 | phytbl_info_t tab; | 2443 | phytbl_info_t tab; |
2444 | 2444 | ||
@@ -2453,7 +2453,7 @@ void wlc_lcnphy_set_tx_locc(phy_info_t *pi, uint16 didq) | |||
2453 | void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index) | 2453 | void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index) |
2454 | { | 2454 | { |
2455 | phytbl_info_t tab; | 2455 | phytbl_info_t tab; |
2456 | uint16 a, b; | 2456 | u16 a, b; |
2457 | u8 bb_mult; | 2457 | u8 bb_mult; |
2458 | uint32 bbmultiqcomp, txgain, locoeffs, rfpower; | 2458 | uint32 bbmultiqcomp, txgain, locoeffs, rfpower; |
2459 | lcnphy_txgains_t gains; | 2459 | lcnphy_txgains_t gains; |
@@ -2479,12 +2479,12 @@ void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index) | |||
2479 | tab.tbl_ptr = &txgain; | 2479 | tab.tbl_ptr = &txgain; |
2480 | wlc_lcnphy_read_table(pi, &tab); | 2480 | wlc_lcnphy_read_table(pi, &tab); |
2481 | 2481 | ||
2482 | gains.gm_gain = (uint16) (txgain & 0xff); | 2482 | gains.gm_gain = (u16) (txgain & 0xff); |
2483 | gains.pga_gain = (uint16) (txgain >> 8) & 0xff; | 2483 | gains.pga_gain = (u16) (txgain >> 8) & 0xff; |
2484 | gains.pad_gain = (uint16) (txgain >> 16) & 0xff; | 2484 | gains.pad_gain = (u16) (txgain >> 16) & 0xff; |
2485 | gains.dac_gain = (uint16) (bbmultiqcomp >> 28) & 0x07; | 2485 | gains.dac_gain = (u16) (bbmultiqcomp >> 28) & 0x07; |
2486 | wlc_lcnphy_set_tx_gain(pi, &gains); | 2486 | wlc_lcnphy_set_tx_gain(pi, &gains); |
2487 | wlc_lcnphy_set_pa_gain(pi, (uint16) (txgain >> 24) & 0x7f); | 2487 | wlc_lcnphy_set_pa_gain(pi, (u16) (txgain >> 24) & 0x7f); |
2488 | 2488 | ||
2489 | bb_mult = (u8) ((bbmultiqcomp >> 20) & 0xff); | 2489 | bb_mult = (u8) ((bbmultiqcomp >> 20) & 0xff); |
2490 | wlc_lcnphy_set_bbmult(pi, bb_mult); | 2490 | wlc_lcnphy_set_bbmult(pi, bb_mult); |
@@ -2493,15 +2493,15 @@ void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index) | |||
2493 | 2493 | ||
2494 | if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) { | 2494 | if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) { |
2495 | 2495 | ||
2496 | a = (uint16) ((bbmultiqcomp >> 10) & 0x3ff); | 2496 | a = (u16) ((bbmultiqcomp >> 10) & 0x3ff); |
2497 | b = (uint16) (bbmultiqcomp & 0x3ff); | 2497 | b = (u16) (bbmultiqcomp & 0x3ff); |
2498 | wlc_lcnphy_set_tx_iqcc(pi, a, b); | 2498 | wlc_lcnphy_set_tx_iqcc(pi, a, b); |
2499 | 2499 | ||
2500 | tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + index; | 2500 | tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + index; |
2501 | tab.tbl_ptr = &locoeffs; | 2501 | tab.tbl_ptr = &locoeffs; |
2502 | wlc_lcnphy_read_table(pi, &tab); | 2502 | wlc_lcnphy_read_table(pi, &tab); |
2503 | 2503 | ||
2504 | wlc_lcnphy_set_tx_locc(pi, (uint16) locoeffs); | 2504 | wlc_lcnphy_set_tx_locc(pi, (u16) locoeffs); |
2505 | 2505 | ||
2506 | tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index; | 2506 | tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index; |
2507 | tab.tbl_ptr = &rfpower; | 2507 | tab.tbl_ptr = &rfpower; |
@@ -2542,13 +2542,13 @@ static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi) | |||
2542 | 2542 | ||
2543 | static void | 2543 | static void |
2544 | wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi, | 2544 | wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi, |
2545 | uint16 trsw, | 2545 | u16 trsw, |
2546 | uint16 ext_lna, | 2546 | u16 ext_lna, |
2547 | uint16 biq2, | 2547 | u16 biq2, |
2548 | uint16 biq1, | 2548 | u16 biq1, |
2549 | uint16 tia, uint16 lna2, uint16 lna1) | 2549 | u16 tia, u16 lna2, u16 lna1) |
2550 | { | 2550 | { |
2551 | uint16 gain0_15, gain16_19; | 2551 | u16 gain0_15, gain16_19; |
2552 | 2552 | ||
2553 | gain16_19 = biq2 & 0xf; | 2553 | gain16_19 = biq2 & 0xf; |
2554 | gain0_15 = ((biq1 & 0xf) << 12) | | 2554 | gain0_15 = ((biq1 & 0xf) << 12) | |
@@ -2577,7 +2577,7 @@ wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi, | |||
2577 | 2577 | ||
2578 | static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable) | 2578 | static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable) |
2579 | { | 2579 | { |
2580 | uint16 ebit = enable ? 1 : 0; | 2580 | u16 ebit = enable ? 1 : 0; |
2581 | 2581 | ||
2582 | mod_phy_reg(pi, 0x4b0, (0x1 << 8), ebit << 8); | 2582 | mod_phy_reg(pi, 0x4b0, (0x1 << 8), ebit << 8); |
2583 | 2583 | ||
@@ -2604,27 +2604,27 @@ void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable) | |||
2604 | { | 2604 | { |
2605 | if (!bEnable) { | 2605 | if (!bEnable) { |
2606 | 2606 | ||
2607 | and_phy_reg(pi, 0x43b, ~(uint16) ((0x1 << 1) | (0x1 << 4))); | 2607 | and_phy_reg(pi, 0x43b, ~(u16) ((0x1 << 1) | (0x1 << 4))); |
2608 | 2608 | ||
2609 | mod_phy_reg(pi, 0x43c, (0x1 << 1), 1 << 1); | 2609 | mod_phy_reg(pi, 0x43c, (0x1 << 1), 1 << 1); |
2610 | 2610 | ||
2611 | and_phy_reg(pi, 0x44c, | 2611 | and_phy_reg(pi, 0x44c, |
2612 | ~(uint16) ((0x1 << 3) | | 2612 | ~(u16) ((0x1 << 3) | |
2613 | (0x1 << 5) | | 2613 | (0x1 << 5) | |
2614 | (0x1 << 12) | | 2614 | (0x1 << 12) | |
2615 | (0x1 << 0) | (0x1 << 1) | (0x1 << 2))); | 2615 | (0x1 << 0) | (0x1 << 1) | (0x1 << 2))); |
2616 | 2616 | ||
2617 | and_phy_reg(pi, 0x44d, | 2617 | and_phy_reg(pi, 0x44d, |
2618 | ~(uint16) ((0x1 << 3) | (0x1 << 5) | (0x1 << 14))); | 2618 | ~(u16) ((0x1 << 3) | (0x1 << 5) | (0x1 << 14))); |
2619 | mod_phy_reg(pi, 0x44d, (0x1 << 2), 1 << 2); | 2619 | mod_phy_reg(pi, 0x44d, (0x1 << 2), 1 << 2); |
2620 | 2620 | ||
2621 | mod_phy_reg(pi, 0x44d, (0x1 << 1) | (0x1 << 0), (0x1 << 0)); | 2621 | mod_phy_reg(pi, 0x44d, (0x1 << 1) | (0x1 << 0), (0x1 << 0)); |
2622 | 2622 | ||
2623 | and_phy_reg(pi, 0x4f9, | 2623 | and_phy_reg(pi, 0x4f9, |
2624 | ~(uint16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2))); | 2624 | ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2))); |
2625 | 2625 | ||
2626 | and_phy_reg(pi, 0x4fa, | 2626 | and_phy_reg(pi, 0x4fa, |
2627 | ~(uint16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2))); | 2627 | ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2))); |
2628 | } else { | 2628 | } else { |
2629 | 2629 | ||
2630 | mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1); | 2630 | mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1); |
@@ -2679,8 +2679,8 @@ void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable) | |||
2679 | 2679 | ||
2680 | static void | 2680 | static void |
2681 | wlc_lcnphy_run_samples(phy_info_t *pi, | 2681 | wlc_lcnphy_run_samples(phy_info_t *pi, |
2682 | uint16 num_samps, | 2682 | u16 num_samps, |
2683 | uint16 num_loops, uint16 wait, bool iqcalmode) | 2683 | u16 num_loops, u16 wait, bool iqcalmode) |
2684 | { | 2684 | { |
2685 | 2685 | ||
2686 | or_phy_reg(pi, 0x6da, 0x8080); | 2686 | or_phy_reg(pi, 0x6da, 0x8080); |
@@ -2694,7 +2694,7 @@ wlc_lcnphy_run_samples(phy_info_t *pi, | |||
2694 | 2694 | ||
2695 | if (iqcalmode) { | 2695 | if (iqcalmode) { |
2696 | 2696 | ||
2697 | and_phy_reg(pi, 0x453, (uint16) ~(0x1 << 15)); | 2697 | and_phy_reg(pi, 0x453, (u16) ~(0x1 << 15)); |
2698 | or_phy_reg(pi, 0x453, (0x1 << 15)); | 2698 | or_phy_reg(pi, 0x453, (0x1 << 15)); |
2699 | } else { | 2699 | } else { |
2700 | write_phy_reg(pi, 0x63f, 1); | 2700 | write_phy_reg(pi, 0x63f, 1); |
@@ -2729,16 +2729,16 @@ void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode) | |||
2729 | } | 2729 | } |
2730 | 2730 | ||
2731 | void | 2731 | void |
2732 | wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, uint16 max_val, | 2732 | wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, u16 max_val, |
2733 | bool iqcalmode) | 2733 | bool iqcalmode) |
2734 | { | 2734 | { |
2735 | u8 phy_bw; | 2735 | u8 phy_bw; |
2736 | uint16 num_samps, t, k; | 2736 | u16 num_samps, t, k; |
2737 | uint32 bw; | 2737 | uint32 bw; |
2738 | fixed theta = 0, rot = 0; | 2738 | fixed theta = 0, rot = 0; |
2739 | cint32 tone_samp; | 2739 | cint32 tone_samp; |
2740 | uint32 data_buf[64]; | 2740 | uint32 data_buf[64]; |
2741 | uint16 i_samp, q_samp; | 2741 | u16 i_samp, q_samp; |
2742 | phytbl_info_t tab; | 2742 | phytbl_info_t tab; |
2743 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 2743 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
2744 | 2744 | ||
@@ -2774,8 +2774,8 @@ wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, uint16 max_val, | |||
2774 | 2774 | ||
2775 | theta += rot; | 2775 | theta += rot; |
2776 | 2776 | ||
2777 | i_samp = (uint16) (FLOAT(tone_samp.i * max_val) & 0x3ff); | 2777 | i_samp = (u16) (FLOAT(tone_samp.i * max_val) & 0x3ff); |
2778 | q_samp = (uint16) (FLOAT(tone_samp.q * max_val) & 0x3ff); | 2778 | q_samp = (u16) (FLOAT(tone_samp.q * max_val) & 0x3ff); |
2779 | data_buf[t] = (i_samp << 10) | q_samp; | 2779 | data_buf[t] = (i_samp << 10) | q_samp; |
2780 | } | 2780 | } |
2781 | 2781 | ||
@@ -2827,12 +2827,12 @@ void wlc_lcnphy_stop_tx_tone(phy_info_t *pi) | |||
2827 | static void wlc_lcnphy_clear_trsw_override(phy_info_t *pi) | 2827 | static void wlc_lcnphy_clear_trsw_override(phy_info_t *pi) |
2828 | { | 2828 | { |
2829 | 2829 | ||
2830 | and_phy_reg(pi, 0x44c, (uint16) ~((0x1 << 1) | (0x1 << 0))); | 2830 | and_phy_reg(pi, 0x44c, (u16) ~((0x1 << 1) | (0x1 << 0))); |
2831 | } | 2831 | } |
2832 | 2832 | ||
2833 | void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, uint16 *a, uint16 *b) | 2833 | void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b) |
2834 | { | 2834 | { |
2835 | uint16 iqcc[2]; | 2835 | u16 iqcc[2]; |
2836 | phytbl_info_t tab; | 2836 | phytbl_info_t tab; |
2837 | 2837 | ||
2838 | tab.tbl_ptr = iqcc; | 2838 | tab.tbl_ptr = iqcc; |
@@ -2846,10 +2846,10 @@ void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, uint16 *a, uint16 *b) | |||
2846 | *b = iqcc[1]; | 2846 | *b = iqcc[1]; |
2847 | } | 2847 | } |
2848 | 2848 | ||
2849 | uint16 wlc_lcnphy_get_tx_locc(phy_info_t *pi) | 2849 | u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi) |
2850 | { | 2850 | { |
2851 | phytbl_info_t tab; | 2851 | phytbl_info_t tab; |
2852 | uint16 didq; | 2852 | u16 didq; |
2853 | 2853 | ||
2854 | tab.tbl_id = 0; | 2854 | tab.tbl_id = 0; |
2855 | tab.tbl_width = 16; | 2855 | tab.tbl_width = 16; |
@@ -2866,10 +2866,10 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi) | |||
2866 | 2866 | ||
2867 | lcnphy_txgains_t target_gains, old_gains; | 2867 | lcnphy_txgains_t target_gains, old_gains; |
2868 | u8 save_bb_mult; | 2868 | u8 save_bb_mult; |
2869 | uint16 a, b, didq, save_pa_gain = 0; | 2869 | u16 a, b, didq, save_pa_gain = 0; |
2870 | uint idx, SAVE_txpwrindex = 0xFF; | 2870 | uint idx, SAVE_txpwrindex = 0xFF; |
2871 | uint32 val; | 2871 | uint32 val; |
2872 | uint16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); | 2872 | u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); |
2873 | phytbl_info_t tab; | 2873 | phytbl_info_t tab; |
2874 | u8 ei0, eq0, fi0, fq0; | 2874 | u8 ei0, eq0, fi0, fq0; |
2875 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 2875 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
@@ -2977,7 +2977,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi) | |||
2977 | 2977 | ||
2978 | int16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode) | 2978 | int16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode) |
2979 | { | 2979 | { |
2980 | uint16 tempsenseval1, tempsenseval2; | 2980 | u16 tempsenseval1, tempsenseval2; |
2981 | int16 avg = 0; | 2981 | int16 avg = 0; |
2982 | bool suspend = 0; | 2982 | bool suspend = 0; |
2983 | 2983 | ||
@@ -3020,12 +3020,12 @@ int16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode) | |||
3020 | return avg; | 3020 | return avg; |
3021 | } | 3021 | } |
3022 | 3022 | ||
3023 | uint16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode) | 3023 | u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode) |
3024 | { | 3024 | { |
3025 | uint16 tempsenseval1, tempsenseval2; | 3025 | u16 tempsenseval1, tempsenseval2; |
3026 | int32 avg = 0; | 3026 | int32 avg = 0; |
3027 | bool suspend = 0; | 3027 | bool suspend = 0; |
3028 | uint16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); | 3028 | u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); |
3029 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 3029 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
3030 | 3030 | ||
3031 | if (NORADIO_ENAB(pi->pubpi)) | 3031 | if (NORADIO_ENAB(pi->pubpi)) |
@@ -3078,7 +3078,7 @@ uint16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode) | |||
3078 | if (!suspend) | 3078 | if (!suspend) |
3079 | wlapi_enable_mac(pi->sh->physhim); | 3079 | wlapi_enable_mac(pi->sh->physhim); |
3080 | } | 3080 | } |
3081 | return (uint16) avg; | 3081 | return (u16) avg; |
3082 | } | 3082 | } |
3083 | 3083 | ||
3084 | s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode) | 3084 | s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode) |
@@ -3092,7 +3092,7 @@ s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode) | |||
3092 | 3092 | ||
3093 | s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode) | 3093 | s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode) |
3094 | { | 3094 | { |
3095 | uint16 vbatsenseval; | 3095 | u16 vbatsenseval; |
3096 | int32 avg = 0; | 3096 | int32 avg = 0; |
3097 | bool suspend = 0; | 3097 | bool suspend = 0; |
3098 | 3098 | ||
@@ -3142,7 +3142,7 @@ static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode) | |||
3142 | 3142 | ||
3143 | static bool | 3143 | static bool |
3144 | wlc_lcnphy_rx_iq_est(phy_info_t *pi, | 3144 | wlc_lcnphy_rx_iq_est(phy_info_t *pi, |
3145 | uint16 num_samps, | 3145 | u16 num_samps, |
3146 | u8 wait_time, lcnphy_iq_est_t *iq_est) | 3146 | u8 wait_time, lcnphy_iq_est_t *iq_est) |
3147 | { | 3147 | { |
3148 | int wait_count = 0; | 3148 | int wait_count = 0; |
@@ -3156,7 +3156,7 @@ wlc_lcnphy_rx_iq_est(phy_info_t *pi, | |||
3156 | 3156 | ||
3157 | mod_phy_reg(pi, 0x482, (0xffff << 0), (num_samps) << 0); | 3157 | mod_phy_reg(pi, 0x482, (0xffff << 0), (num_samps) << 0); |
3158 | 3158 | ||
3159 | mod_phy_reg(pi, 0x481, (0xff << 0), ((uint16) wait_time) << 0); | 3159 | mod_phy_reg(pi, 0x481, (0xff << 0), ((u16) wait_time) << 0); |
3160 | 3160 | ||
3161 | mod_phy_reg(pi, 0x481, (0x1 << 8), (0) << 8); | 3161 | mod_phy_reg(pi, 0x481, (0x1 << 8), (0) << 8); |
3162 | 3162 | ||
@@ -3187,11 +3187,11 @@ wlc_lcnphy_rx_iq_est(phy_info_t *pi, | |||
3187 | return result; | 3187 | return result; |
3188 | } | 3188 | } |
3189 | 3189 | ||
3190 | static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, uint16 num_samps) | 3190 | static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps) |
3191 | { | 3191 | { |
3192 | #define LCNPHY_MIN_RXIQ_PWR 2 | 3192 | #define LCNPHY_MIN_RXIQ_PWR 2 |
3193 | bool result; | 3193 | bool result; |
3194 | uint16 a0_new, b0_new; | 3194 | u16 a0_new, b0_new; |
3195 | lcnphy_iq_est_t iq_est = { 0, 0, 0 }; | 3195 | lcnphy_iq_est_t iq_est = { 0, 0, 0 }; |
3196 | int32 a, b, temp; | 3196 | int32 a, b, temp; |
3197 | int16 iq_nbits, qq_nbits, arsh, brsh; | 3197 | int16 iq_nbits, qq_nbits, arsh, brsh; |
@@ -3256,8 +3256,8 @@ static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, uint16 num_samps) | |||
3256 | b -= a * a; | 3256 | b -= a * a; |
3257 | b = (int32) wlc_phy_sqrt_int((uint32) b); | 3257 | b = (int32) wlc_phy_sqrt_int((uint32) b); |
3258 | b -= (1 << 10); | 3258 | b -= (1 << 10); |
3259 | a0_new = (uint16) (a & 0x3ff); | 3259 | a0_new = (u16) (a & 0x3ff); |
3260 | b0_new = (uint16) (b & 0x3ff); | 3260 | b0_new = (u16) (b & 0x3ff); |
3261 | cleanup: | 3261 | cleanup: |
3262 | 3262 | ||
3263 | wlc_lcnphy_set_rx_iq_comp(pi, a0_new, b0_new); | 3263 | wlc_lcnphy_set_rx_iq_comp(pi, a0_new, b0_new); |
@@ -3278,17 +3278,17 @@ wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp, | |||
3278 | int tx_gain_idx) | 3278 | int tx_gain_idx) |
3279 | { | 3279 | { |
3280 | lcnphy_txgains_t old_gains; | 3280 | lcnphy_txgains_t old_gains; |
3281 | uint16 tx_pwr_ctrl; | 3281 | u16 tx_pwr_ctrl; |
3282 | u8 tx_gain_index_old = 0; | 3282 | u8 tx_gain_index_old = 0; |
3283 | bool result = FALSE, tx_gain_override_old = FALSE; | 3283 | bool result = FALSE, tx_gain_override_old = FALSE; |
3284 | uint16 i, Core1TxControl_old, RFOverride0_old, | 3284 | u16 i, Core1TxControl_old, RFOverride0_old, |
3285 | RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old, | 3285 | RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old, |
3286 | rfoverride3_old, rfoverride3val_old, rfoverride4_old, | 3286 | rfoverride3_old, rfoverride3val_old, rfoverride4_old, |
3287 | rfoverride4val_old, afectrlovr_old, afectrlovrval_old; | 3287 | rfoverride4val_old, afectrlovr_old, afectrlovrval_old; |
3288 | int tia_gain; | 3288 | int tia_gain; |
3289 | uint32 received_power, rx_pwr_threshold; | 3289 | uint32 received_power, rx_pwr_threshold; |
3290 | uint16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl; | 3290 | u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl; |
3291 | uint16 values_to_save[11]; | 3291 | u16 values_to_save[11]; |
3292 | int16 *ptr; | 3292 | int16 *ptr; |
3293 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 3293 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
3294 | 3294 | ||
@@ -3304,9 +3304,9 @@ wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp, | |||
3304 | CHSPEC_CHANNEL(pi->radio_chanspec)) { | 3304 | CHSPEC_CHANNEL(pi->radio_chanspec)) { |
3305 | 3305 | ||
3306 | wlc_lcnphy_set_rx_iq_comp(pi, | 3306 | wlc_lcnphy_set_rx_iq_comp(pi, |
3307 | (uint16) | 3307 | (u16) |
3308 | iqcomp[iqcomp_sz].a, | 3308 | iqcomp[iqcomp_sz].a, |
3309 | (uint16) | 3309 | (u16) |
3310 | iqcomp[iqcomp_sz].b); | 3310 | iqcomp[iqcomp_sz].b); |
3311 | result = TRUE; | 3311 | result = TRUE; |
3312 | break; | 3312 | break; |
@@ -3393,7 +3393,7 @@ wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp, | |||
3393 | tia_gain -= 1; | 3393 | tia_gain -= 1; |
3394 | wlc_lcnphy_set_rx_gain_by_distribution(pi, | 3394 | wlc_lcnphy_set_rx_gain_by_distribution(pi, |
3395 | 0, 0, 2, 2, | 3395 | 0, 0, 2, 2, |
3396 | (uint16) | 3396 | (u16) |
3397 | tia_gain, 1, 0); | 3397 | tia_gain, 1, 0); |
3398 | OSL_DELAY(500); | 3398 | OSL_DELAY(500); |
3399 | 3399 | ||
@@ -3454,7 +3454,7 @@ static void wlc_lcnphy_glacial_timer_based_cal(phy_info_t *pi) | |||
3454 | { | 3454 | { |
3455 | bool suspend; | 3455 | bool suspend; |
3456 | s8 index; | 3456 | s8 index; |
3457 | uint16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); | 3457 | u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); |
3458 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 3458 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
3459 | suspend = | 3459 | suspend = |
3460 | (0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)); | 3460 | (0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)); |
@@ -3480,7 +3480,7 @@ static void wlc_lcnphy_periodic_cal(phy_info_t *pi) | |||
3480 | bool suspend, full_cal; | 3480 | bool suspend, full_cal; |
3481 | const lcnphy_rx_iqcomp_t *rx_iqcomp; | 3481 | const lcnphy_rx_iqcomp_t *rx_iqcomp; |
3482 | int rx_iqcomp_sz; | 3482 | int rx_iqcomp_sz; |
3483 | uint16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); | 3483 | u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); |
3484 | s8 index; | 3484 | s8 index; |
3485 | phytbl_info_t tab; | 3485 | phytbl_info_t tab; |
3486 | int32 a1, b0, b1; | 3486 | int32 a1, b0, b1; |
@@ -3549,7 +3549,7 @@ static void wlc_lcnphy_periodic_cal(phy_info_t *pi) | |||
3549 | 3549 | ||
3550 | void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode) | 3550 | void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode) |
3551 | { | 3551 | { |
3552 | uint16 temp_new; | 3552 | u16 temp_new; |
3553 | int temp1, temp2, temp_diff; | 3553 | int temp1, temp2, temp_diff; |
3554 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 3554 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
3555 | 3555 | ||
@@ -3592,7 +3592,7 @@ void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode) | |||
3592 | void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr, s8 *cck_pwr) | 3592 | void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr, s8 *cck_pwr) |
3593 | { | 3593 | { |
3594 | s8 cck_offset; | 3594 | s8 cck_offset; |
3595 | uint16 status; | 3595 | u16 status; |
3596 | status = (read_phy_reg(pi, 0x4ab)); | 3596 | status = (read_phy_reg(pi, 0x4ab)); |
3597 | if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) && | 3597 | if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) && |
3598 | (status & (0x1 << 15))) { | 3598 | (status & (0x1 << 15))) { |
@@ -3678,13 +3678,13 @@ wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng, u8 rate, | |||
3678 | void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi) | 3678 | void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi) |
3679 | { | 3679 | { |
3680 | s8 index; | 3680 | s8 index; |
3681 | uint16 index2; | 3681 | u16 index2; |
3682 | phy_info_t *pi = (phy_info_t *) ppi; | 3682 | phy_info_t *pi = (phy_info_t *) ppi; |
3683 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 3683 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
3684 | uint16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); | 3684 | u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); |
3685 | if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) && SAVE_txpwrctrl) { | 3685 | if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) && SAVE_txpwrctrl) { |
3686 | index = wlc_lcnphy_tempcompensated_txpwrctrl(pi); | 3686 | index = wlc_lcnphy_tempcompensated_txpwrctrl(pi); |
3687 | index2 = (uint16) (index * 2); | 3687 | index2 = (u16) (index * 2); |
3688 | mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0); | 3688 | mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0); |
3689 | 3689 | ||
3690 | pi_lcn->lcnphy_current_index = (s8) | 3690 | pi_lcn->lcnphy_current_index = (s8) |
@@ -3692,7 +3692,7 @@ void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi) | |||
3692 | } | 3692 | } |
3693 | } | 3693 | } |
3694 | 3694 | ||
3695 | static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, uint16 a, uint16 b) | 3695 | static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, u16 a, u16 b) |
3696 | { | 3696 | { |
3697 | mod_phy_reg(pi, 0x645, (0x3ff << 0), (a) << 0); | 3697 | mod_phy_reg(pi, 0x645, (0x3ff << 0), (a) << 0); |
3698 | 3698 | ||
@@ -3758,9 +3758,9 @@ void WLBANDINITFN(wlc_phy_init_lcnphy) (phy_info_t *pi) | |||
3758 | } | 3758 | } |
3759 | 3759 | ||
3760 | static void | 3760 | static void |
3761 | wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, uint16 *values_to_save) | 3761 | wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, u16 *values_to_save) |
3762 | { | 3762 | { |
3763 | uint16 vmid; | 3763 | u16 vmid; |
3764 | int i; | 3764 | int i; |
3765 | for (i = 0; i < 20; i++) { | 3765 | for (i = 0; i < 20; i++) { |
3766 | values_to_save[i] = | 3766 | values_to_save[i] = |
@@ -3851,12 +3851,12 @@ wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, uint16 *values_to_save) | |||
3851 | } | 3851 | } |
3852 | 3852 | ||
3853 | static void | 3853 | static void |
3854 | wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, uint16 thresh, | 3854 | wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh, |
3855 | int16 *ptr, int mode) | 3855 | int16 *ptr, int mode) |
3856 | { | 3856 | { |
3857 | uint32 curval1, curval2, stpptr, curptr, strptr, val; | 3857 | uint32 curval1, curval2, stpptr, curptr, strptr, val; |
3858 | uint16 sslpnCalibClkEnCtrl, timer; | 3858 | u16 sslpnCalibClkEnCtrl, timer; |
3859 | uint16 old_sslpnCalibClkEnCtrl; | 3859 | u16 old_sslpnCalibClkEnCtrl; |
3860 | int16 imag, real; | 3860 | int16 imag, real; |
3861 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 3861 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
3862 | 3862 | ||
@@ -3876,7 +3876,7 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, uint16 thresh, | |||
3876 | write_phy_reg(pi, 0x555, 0x0); | 3876 | write_phy_reg(pi, 0x555, 0x0); |
3877 | write_phy_reg(pi, 0x5a6, 0x5); | 3877 | write_phy_reg(pi, 0x5a6, 0x5); |
3878 | 3878 | ||
3879 | write_phy_reg(pi, 0x5a2, (uint16) (mode | mode << 6)); | 3879 | write_phy_reg(pi, 0x5a2, (u16) (mode | mode << 6)); |
3880 | write_phy_reg(pi, 0x5cf, 3); | 3880 | write_phy_reg(pi, 0x5cf, 3); |
3881 | write_phy_reg(pi, 0x5a5, 0x3); | 3881 | write_phy_reg(pi, 0x5a5, 0x3); |
3882 | write_phy_reg(pi, 0x583, 0x0); | 3882 | write_phy_reg(pi, 0x583, 0x0); |
@@ -3952,8 +3952,8 @@ static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi) | |||
3952 | static void | 3952 | static void |
3953 | wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, int16 coeff_x, int16 coeff_y) | 3953 | wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, int16 coeff_x, int16 coeff_y) |
3954 | { | 3954 | { |
3955 | uint16 di0dq0; | 3955 | u16 di0dq0; |
3956 | uint16 x, y, data_rf; | 3956 | u16 x, y, data_rf; |
3957 | int k; | 3957 | int k; |
3958 | switch (cal_type) { | 3958 | switch (cal_type) { |
3959 | case 0: | 3959 | case 0: |
@@ -3996,7 +3996,7 @@ wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, int16 coeff_x, int16 coeff_y) | |||
3996 | 3996 | ||
3997 | static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type) | 3997 | static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type) |
3998 | { | 3998 | { |
3999 | uint16 a, b, didq; | 3999 | u16 a, b, didq; |
4000 | u8 di0, dq0, ei, eq, fi, fq; | 4000 | u8 di0, dq0, ei, eq, fi, fq; |
4001 | lcnphy_unsign16_struct cc; | 4001 | lcnphy_unsign16_struct cc; |
4002 | cc.re = 0; | 4002 | cc.re = 0; |
@@ -4011,18 +4011,18 @@ static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type) | |||
4011 | didq = wlc_lcnphy_get_tx_locc(pi); | 4011 | didq = wlc_lcnphy_get_tx_locc(pi); |
4012 | di0 = (((didq & 0xff00) << 16) >> 24); | 4012 | di0 = (((didq & 0xff00) << 16) >> 24); |
4013 | dq0 = (((didq & 0x00ff) << 24) >> 24); | 4013 | dq0 = (((didq & 0x00ff) << 24) >> 24); |
4014 | cc.re = (uint16) di0; | 4014 | cc.re = (u16) di0; |
4015 | cc.im = (uint16) dq0; | 4015 | cc.im = (u16) dq0; |
4016 | break; | 4016 | break; |
4017 | case 3: | 4017 | case 3: |
4018 | wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq); | 4018 | wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq); |
4019 | cc.re = (uint16) ei; | 4019 | cc.re = (u16) ei; |
4020 | cc.im = (uint16) eq; | 4020 | cc.im = (u16) eq; |
4021 | break; | 4021 | break; |
4022 | case 4: | 4022 | case 4: |
4023 | wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq); | 4023 | wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq); |
4024 | cc.re = (uint16) fi; | 4024 | cc.re = (u16) fi; |
4025 | cc.im = (uint16) fq; | 4025 | cc.im = (u16) fq; |
4026 | break; | 4026 | break; |
4027 | } | 4027 | } |
4028 | return cc; | 4028 | return cc; |
@@ -4035,16 +4035,16 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2) | |||
4035 | lcnphy_spb_tone_t phy_c2; | 4035 | lcnphy_spb_tone_t phy_c2; |
4036 | lcnphy_unsign16_struct phy_c3; | 4036 | lcnphy_unsign16_struct phy_c3; |
4037 | int phy_c4, phy_c5, k, l, j, phy_c6; | 4037 | int phy_c4, phy_c5, k, l, j, phy_c6; |
4038 | uint16 phy_c7, phy_c8, phy_c9; | 4038 | u16 phy_c7, phy_c8, phy_c9; |
4039 | int16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16; | 4039 | int16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16; |
4040 | int16 *ptr, phy_c17; | 4040 | int16 *ptr, phy_c17; |
4041 | int32 phy_c18, phy_c19; | 4041 | int32 phy_c18, phy_c19; |
4042 | uint32 phy_c20, phy_c21; | 4042 | uint32 phy_c20, phy_c21; |
4043 | bool phy_c22, phy_c23, phy_c24, phy_c25; | 4043 | bool phy_c22, phy_c23, phy_c24, phy_c25; |
4044 | uint16 phy_c26, phy_c27; | 4044 | u16 phy_c26, phy_c27; |
4045 | uint16 phy_c28, phy_c29, phy_c30; | 4045 | u16 phy_c28, phy_c29, phy_c30; |
4046 | uint16 phy_c31; | 4046 | u16 phy_c31; |
4047 | uint16 *phy_c32; | 4047 | u16 *phy_c32; |
4048 | phy_c21 = 0; | 4048 | phy_c21 = 0; |
4049 | phy_c10 = phy_c13 = phy_c14 = phy_c8 = 0; | 4049 | phy_c10 = phy_c13 = phy_c14 = phy_c8 = 0; |
4050 | ptr = MALLOC(pi->sh->osh, sizeof(int16) * 131); | 4050 | ptr = MALLOC(pi->sh->osh, sizeof(int16) * 131); |
@@ -4052,7 +4052,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2) | |||
4052 | return; | 4052 | return; |
4053 | } | 4053 | } |
4054 | 4054 | ||
4055 | phy_c32 = MALLOC(pi->sh->osh, sizeof(uint16) * 20); | 4055 | phy_c32 = MALLOC(pi->sh->osh, sizeof(u16) * 20); |
4056 | if (NULL == phy_c32) { | 4056 | if (NULL == phy_c32) { |
4057 | return; | 4057 | return; |
4058 | } | 4058 | } |
@@ -4221,12 +4221,12 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2) | |||
4221 | write_phy_reg(pi, 0x4d8, phy_c30); | 4221 | write_phy_reg(pi, 0x4d8, phy_c30); |
4222 | write_radio_reg(pi, RADIO_2064_REG026, phy_c31); | 4222 | write_radio_reg(pi, RADIO_2064_REG026, phy_c31); |
4223 | 4223 | ||
4224 | MFREE(pi->sh->osh, phy_c32, 20 * sizeof(uint16)); | 4224 | MFREE(pi->sh->osh, phy_c32, 20 * sizeof(u16)); |
4225 | MFREE(pi->sh->osh, ptr, 131 * sizeof(int16)); | 4225 | MFREE(pi->sh->osh, ptr, 131 * sizeof(int16)); |
4226 | } | 4226 | } |
4227 | 4227 | ||
4228 | static void | 4228 | static void |
4229 | wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi, uint16 *values_to_save) | 4229 | wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi, u16 *values_to_save) |
4230 | { | 4230 | { |
4231 | int i; | 4231 | int i; |
4232 | 4232 | ||
@@ -4247,8 +4247,8 @@ WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi, | |||
4247 | uint32 j; | 4247 | uint32 j; |
4248 | phytbl_info_t tab; | 4248 | phytbl_info_t tab; |
4249 | uint32 val; | 4249 | uint32 val; |
4250 | uint16 pa_gain; | 4250 | u16 pa_gain; |
4251 | uint16 gm_gain; | 4251 | u16 gm_gain; |
4252 | 4252 | ||
4253 | if (CHSPEC_IS5G(pi->radio_chanspec)) | 4253 | if (CHSPEC_IS5G(pi->radio_chanspec)) |
4254 | pa_gain = 0x70; | 4254 | pa_gain = 0x70; |
@@ -4423,7 +4423,7 @@ static void WLBANDINITFN(wlc_lcnphy_tbl_init) (phy_info_t *pi) | |||
4423 | 4423 | ||
4424 | static void WLBANDINITFN(wlc_lcnphy_rev0_baseband_init) (phy_info_t *pi) | 4424 | static void WLBANDINITFN(wlc_lcnphy_rev0_baseband_init) (phy_info_t *pi) |
4425 | { | 4425 | { |
4426 | uint16 afectrl1; | 4426 | u16 afectrl1; |
4427 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 4427 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
4428 | 4428 | ||
4429 | write_radio_reg(pi, RADIO_2064_REG11C, 0x0); | 4429 | write_radio_reg(pi, RADIO_2064_REG11C, 0x0); |
@@ -4448,7 +4448,7 @@ static void WLBANDINITFN(wlc_lcnphy_rev0_baseband_init) (phy_info_t *pi) | |||
4448 | 4448 | ||
4449 | if (0) { | 4449 | if (0) { |
4450 | afectrl1 = 0; | 4450 | afectrl1 = 0; |
4451 | afectrl1 = (uint16) ((pi_lcn->lcnphy_rssi_vf) | | 4451 | afectrl1 = (u16) ((pi_lcn->lcnphy_rssi_vf) | |
4452 | (pi_lcn->lcnphy_rssi_vc << 4) | (pi_lcn-> | 4452 | (pi_lcn->lcnphy_rssi_vc << 4) | (pi_lcn-> |
4453 | lcnphy_rssi_gs | 4453 | lcnphy_rssi_gs |
4454 | << 10)); | 4454 | << 10)); |
@@ -4615,12 +4615,12 @@ static void WLBANDINITFN(wlc_radio_2064_init) (phy_info_t *pi) | |||
4615 | write_radio_reg(pi, | 4615 | write_radio_reg(pi, |
4616 | ((lcnphyregs[i].address & 0x3fff) | | 4616 | ((lcnphyregs[i].address & 0x3fff) | |
4617 | RADIO_DEFAULT_CORE), | 4617 | RADIO_DEFAULT_CORE), |
4618 | (uint16) lcnphyregs[i].init_a); | 4618 | (u16) lcnphyregs[i].init_a); |
4619 | else if (lcnphyregs[i].do_init_g) | 4619 | else if (lcnphyregs[i].do_init_g) |
4620 | write_radio_reg(pi, | 4620 | write_radio_reg(pi, |
4621 | ((lcnphyregs[i].address & 0x3fff) | | 4621 | ((lcnphyregs[i].address & 0x3fff) | |
4622 | RADIO_DEFAULT_CORE), | 4622 | RADIO_DEFAULT_CORE), |
4623 | (uint16) lcnphyregs[i].init_g); | 4623 | (u16) lcnphyregs[i].init_g); |
4624 | 4624 | ||
4625 | write_radio_reg(pi, RADIO_2064_REG032, 0x62); | 4625 | write_radio_reg(pi, RADIO_2064_REG032, 0x62); |
4626 | write_radio_reg(pi, RADIO_2064_REG033, 0x19); | 4626 | write_radio_reg(pi, RADIO_2064_REG033, 0x19); |
@@ -4706,7 +4706,7 @@ static void wlc_lcnphy_rcal(phy_info_t *pi) | |||
4706 | static void wlc_lcnphy_rc_cal(phy_info_t *pi) | 4706 | static void wlc_lcnphy_rc_cal(phy_info_t *pi) |
4707 | { | 4707 | { |
4708 | u8 dflt_rc_cal_val; | 4708 | u8 dflt_rc_cal_val; |
4709 | uint16 flt_val; | 4709 | u16 flt_val; |
4710 | 4710 | ||
4711 | if (NORADIO_ENAB(pi->pubpi)) | 4711 | if (NORADIO_ENAB(pi->pubpi)) |
4712 | return; | 4712 | return; |
@@ -4733,7 +4733,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi) | |||
4733 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; | 4733 | phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; |
4734 | 4734 | ||
4735 | if (CHSPEC_IS2G(pi->radio_chanspec)) { | 4735 | if (CHSPEC_IS2G(pi->radio_chanspec)) { |
4736 | uint16 cckpo = 0; | 4736 | u16 cckpo = 0; |
4737 | uint32 offset_ofdm, offset_mcs; | 4737 | uint32 offset_ofdm, offset_mcs; |
4738 | 4738 | ||
4739 | pi_lcn->lcnphy_tr_isolation_mid = | 4739 | pi_lcn->lcnphy_tr_isolation_mid = |
@@ -4771,7 +4771,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi) | |||
4771 | pi->txpa_2g_high_temp[i] = pi->txpa_2g[i]; | 4771 | pi->txpa_2g_high_temp[i] = pi->txpa_2g[i]; |
4772 | } | 4772 | } |
4773 | 4773 | ||
4774 | cckpo = (uint16) PHY_GETINTVAR(pi, "cck2gpo"); | 4774 | cckpo = (u16) PHY_GETINTVAR(pi, "cck2gpo"); |
4775 | if (cckpo) { | 4775 | if (cckpo) { |
4776 | uint max_pwr_chan = txpwr; | 4776 | uint max_pwr_chan = txpwr; |
4777 | 4777 | ||
@@ -4804,8 +4804,8 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi) | |||
4804 | offset_ofdm >>= 4; | 4804 | offset_ofdm >>= 4; |
4805 | } | 4805 | } |
4806 | offset_mcs = | 4806 | offset_mcs = |
4807 | ((uint16) PHY_GETINTVAR(pi, "mcs2gpo1") << 16) | | 4807 | ((u16) PHY_GETINTVAR(pi, "mcs2gpo1") << 16) | |
4808 | (uint16) PHY_GETINTVAR(pi, "mcs2gpo0"); | 4808 | (u16) PHY_GETINTVAR(pi, "mcs2gpo0"); |
4809 | pi_lcn->lcnphy_mcs20_po = offset_mcs; | 4809 | pi_lcn->lcnphy_mcs20_po = offset_mcs; |
4810 | for (i = TXP_FIRST_SISO_MCS_20; | 4810 | for (i = TXP_FIRST_SISO_MCS_20; |
4811 | i <= TXP_LAST_SISO_MCS_20; i++) { | 4811 | i <= TXP_LAST_SISO_MCS_20; i++) { |
@@ -4816,7 +4816,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi) | |||
4816 | } | 4816 | } |
4817 | 4817 | ||
4818 | pi_lcn->lcnphy_rawtempsense = | 4818 | pi_lcn->lcnphy_rawtempsense = |
4819 | (uint16) PHY_GETINTVAR(pi, "rawtempsense"); | 4819 | (u16) PHY_GETINTVAR(pi, "rawtempsense"); |
4820 | pi_lcn->lcnphy_measPower = | 4820 | pi_lcn->lcnphy_measPower = |
4821 | (u8) PHY_GETINTVAR(pi, "measpower"); | 4821 | (u8) PHY_GETINTVAR(pi, "measpower"); |
4822 | pi_lcn->lcnphy_tempsense_slope = | 4822 | pi_lcn->lcnphy_tempsense_slope = |
@@ -4873,7 +4873,7 @@ wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, u8 channel) | |||
4873 | fixed qFxtal, qFref, qFvco, qFcal; | 4873 | fixed qFxtal, qFref, qFvco, qFcal; |
4874 | u8 d15, d16, f16, e44, e45; | 4874 | u8 d15, d16, f16, e44, e45; |
4875 | uint32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div; | 4875 | uint32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div; |
4876 | uint16 loop_bw, d30, setCount; | 4876 | u16 loop_bw, d30, setCount; |
4877 | if (NORADIO_ENAB(pi->pubpi)) | 4877 | if (NORADIO_ENAB(pi->pubpi)) |
4878 | return; | 4878 | return; |
4879 | ci = &chan_info_2064_lcnphy[0]; | 4879 | ci = &chan_info_2064_lcnphy[0]; |
@@ -4991,7 +4991,7 @@ wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, u8 channel) | |||
4991 | 4991 | ||
4992 | { | 4992 | { |
4993 | u8 h29, h23, c28, d29, h28_ten, e30, h30_ten, cp_current; | 4993 | u8 h29, h23, c28, d29, h28_ten, e30, h30_ten, cp_current; |
4994 | uint16 c29, c38, c30, g30, d28; | 4994 | u16 c29, c38, c30, g30, d28; |
4995 | c29 = loop_bw; | 4995 | c29 = loop_bw; |
4996 | d29 = 200; | 4996 | d29 = 200; |
4997 | c38 = 1250; | 4997 | c38 = 1250; |
@@ -5040,7 +5040,7 @@ bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi) | |||
5040 | 5040 | ||
5041 | void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi) | 5041 | void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi) |
5042 | { | 5042 | { |
5043 | uint16 pwr_ctrl; | 5043 | u16 pwr_ctrl; |
5044 | if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) { | 5044 | if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) { |
5045 | wlc_lcnphy_calib_modes(pi, LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL); | 5045 | wlc_lcnphy_calib_modes(pi, LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL); |
5046 | } else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) { | 5046 | } else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) { |
@@ -5113,17 +5113,17 @@ bool wlc_phy_attach_lcnphy(phy_info_t *pi) | |||
5113 | 5113 | ||
5114 | static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, uint32 gain) | 5114 | static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, uint32 gain) |
5115 | { | 5115 | { |
5116 | uint16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19; | 5116 | u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19; |
5117 | 5117 | ||
5118 | trsw = (gain & ((uint32) 1 << 28)) ? 0 : 1; | 5118 | trsw = (gain & ((uint32) 1 << 28)) ? 0 : 1; |
5119 | ext_lna = (uint16) (gain >> 29) & 0x01; | 5119 | ext_lna = (u16) (gain >> 29) & 0x01; |
5120 | lna1 = (uint16) (gain >> 0) & 0x0f; | 5120 | lna1 = (u16) (gain >> 0) & 0x0f; |
5121 | lna2 = (uint16) (gain >> 4) & 0x0f; | 5121 | lna2 = (u16) (gain >> 4) & 0x0f; |
5122 | tia = (uint16) (gain >> 8) & 0xf; | 5122 | tia = (u16) (gain >> 8) & 0xf; |
5123 | biq0 = (uint16) (gain >> 12) & 0xf; | 5123 | biq0 = (u16) (gain >> 12) & 0xf; |
5124 | biq1 = (uint16) (gain >> 16) & 0xf; | 5124 | biq1 = (u16) (gain >> 16) & 0xf; |
5125 | 5125 | ||
5126 | gain0_15 = (uint16) ((lna1 & 0x3) | ((lna1 & 0x3) << 2) | | 5126 | gain0_15 = (u16) ((lna1 & 0x3) | ((lna1 & 0x3) << 2) | |
5127 | ((lna2 & 0x3) << 4) | ((lna2 & 0x3) << 6) | | 5127 | ((lna2 & 0x3) << 4) | ((lna2 & 0x3) << 6) | |
5128 | ((tia & 0xf) << 8) | ((biq0 & 0xf) << 12)); | 5128 | ((tia & 0xf) << 8) | ((biq0 & 0xf) << 12)); |
5129 | gain16_19 = biq1; | 5129 | gain16_19 = biq1; |
@@ -5254,7 +5254,7 @@ wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm, int16 filt_type) | |||
5254 | int16 filt_index = -1; | 5254 | int16 filt_index = -1; |
5255 | int j; | 5255 | int j; |
5256 | 5256 | ||
5257 | uint16 addr[] = { | 5257 | u16 addr[] = { |
5258 | 0x910, | 5258 | 0x910, |
5259 | 0x91e, | 5259 | 0x91e, |
5260 | 0x91f, | 5260 | 0x91f, |
@@ -5273,7 +5273,7 @@ wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm, int16 filt_type) | |||
5273 | 0x932 | 5273 | 0x932 |
5274 | }; | 5274 | }; |
5275 | 5275 | ||
5276 | uint16 addr_ofdm[] = { | 5276 | u16 addr_ofdm[] = { |
5277 | 0x90f, | 5277 | 0x90f, |
5278 | 0x900, | 5278 | 0x900, |
5279 | 0x901, | 5279 | 0x901, |
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h index 5d157a2ce85..3c7e8cf21c4 100644 --- a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h +++ b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h | |||
@@ -23,7 +23,7 @@ struct phy_info_lcnphy { | |||
23 | int lcnphy_txrf_sp_9_override; | 23 | int lcnphy_txrf_sp_9_override; |
24 | u8 lcnphy_full_cal_channel; | 24 | u8 lcnphy_full_cal_channel; |
25 | u8 lcnphy_cal_counter; | 25 | u8 lcnphy_cal_counter; |
26 | uint16 lcnphy_cal_temper; | 26 | u16 lcnphy_cal_temper; |
27 | bool lcnphy_recal; | 27 | bool lcnphy_recal; |
28 | 28 | ||
29 | u8 lcnphy_rc_cap; | 29 | u8 lcnphy_rc_cap; |
@@ -51,7 +51,7 @@ struct phy_info_lcnphy { | |||
51 | int16 lcnphy_pa0b1; | 51 | int16 lcnphy_pa0b1; |
52 | int16 lcnphy_pa0b2; | 52 | int16 lcnphy_pa0b2; |
53 | 53 | ||
54 | uint16 lcnphy_rawtempsense; | 54 | u16 lcnphy_rawtempsense; |
55 | u8 lcnphy_measPower; | 55 | u8 lcnphy_measPower; |
56 | u8 lcnphy_tempsense_slope; | 56 | u8 lcnphy_tempsense_slope; |
57 | u8 lcnphy_freqoffset_corr; | 57 | u8 lcnphy_freqoffset_corr; |
@@ -61,13 +61,13 @@ struct phy_info_lcnphy { | |||
61 | bool lcnphy_hw_iqcal_en; | 61 | bool lcnphy_hw_iqcal_en; |
62 | uint lcnphy_bandedge_corr; | 62 | uint lcnphy_bandedge_corr; |
63 | bool lcnphy_spurmod; | 63 | bool lcnphy_spurmod; |
64 | uint16 lcnphy_tssi_tx_cnt; | 64 | u16 lcnphy_tssi_tx_cnt; |
65 | uint16 lcnphy_tssi_idx; | 65 | u16 lcnphy_tssi_idx; |
66 | uint16 lcnphy_tssi_npt; | 66 | u16 lcnphy_tssi_npt; |
67 | 67 | ||
68 | uint16 lcnphy_target_tx_freq; | 68 | u16 lcnphy_target_tx_freq; |
69 | s8 lcnphy_tx_power_idx_override; | 69 | s8 lcnphy_tx_power_idx_override; |
70 | uint16 lcnphy_noise_samples; | 70 | u16 lcnphy_noise_samples; |
71 | 71 | ||
72 | uint32 lcnphy_papdRxGnIdx; | 72 | uint32 lcnphy_papdRxGnIdx; |
73 | uint32 lcnphy_papd_rxGnCtrl_init; | 73 | uint32 lcnphy_papd_rxGnCtrl_init; |
@@ -81,8 +81,8 @@ struct phy_info_lcnphy { | |||
81 | uint32 lcnphy_tr_R_gain_val; | 81 | uint32 lcnphy_tr_R_gain_val; |
82 | uint32 lcnphy_tr_T_gain_val; | 82 | uint32 lcnphy_tr_T_gain_val; |
83 | s8 lcnphy_input_pwr_offset_db; | 83 | s8 lcnphy_input_pwr_offset_db; |
84 | uint16 lcnphy_Med_Low_Gain_db; | 84 | u16 lcnphy_Med_Low_Gain_db; |
85 | uint16 lcnphy_Very_Low_Gain_db; | 85 | u16 lcnphy_Very_Low_Gain_db; |
86 | s8 lcnphy_lastsensed_temperature; | 86 | s8 lcnphy_lastsensed_temperature; |
87 | s8 lcnphy_pkteng_rssi_slope; | 87 | s8 lcnphy_pkteng_rssi_slope; |
88 | u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES]; | 88 | u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES]; |
@@ -95,9 +95,9 @@ struct phy_info_lcnphy { | |||
95 | u8 lcnphy_psat_2pt3_detected; | 95 | u8 lcnphy_psat_2pt3_detected; |
96 | int32 lcnphy_lowest_Re_div_Im; | 96 | int32 lcnphy_lowest_Re_div_Im; |
97 | s8 lcnphy_final_papd_cal_idx; | 97 | s8 lcnphy_final_papd_cal_idx; |
98 | uint16 lcnphy_extstxctrl4; | 98 | u16 lcnphy_extstxctrl4; |
99 | uint16 lcnphy_extstxctrl0; | 99 | u16 lcnphy_extstxctrl0; |
100 | uint16 lcnphy_extstxctrl1; | 100 | u16 lcnphy_extstxctrl1; |
101 | int16 lcnphy_cck_dig_filt_type; | 101 | int16 lcnphy_cck_dig_filt_type; |
102 | int16 lcnphy_ofdm_dig_filt_type; | 102 | int16 lcnphy_ofdm_dig_filt_type; |
103 | lcnphy_cal_results_t lcnphy_cal_results; | 103 | lcnphy_cal_results_t lcnphy_cal_results; |
@@ -108,11 +108,11 @@ struct phy_info_lcnphy { | |||
108 | u8 lcnphy_final_idx; | 108 | u8 lcnphy_final_idx; |
109 | u8 lcnphy_start_idx; | 109 | u8 lcnphy_start_idx; |
110 | u8 lcnphy_current_index; | 110 | u8 lcnphy_current_index; |
111 | uint16 lcnphy_logen_buf_1; | 111 | u16 lcnphy_logen_buf_1; |
112 | uint16 lcnphy_local_ovr_2; | 112 | u16 lcnphy_local_ovr_2; |
113 | uint16 lcnphy_local_oval_6; | 113 | u16 lcnphy_local_oval_6; |
114 | uint16 lcnphy_local_oval_5; | 114 | u16 lcnphy_local_oval_5; |
115 | uint16 lcnphy_logen_mixer_1; | 115 | u16 lcnphy_logen_mixer_1; |
116 | 116 | ||
117 | u8 lcnphy_aci_stat; | 117 | u8 lcnphy_aci_stat; |
118 | uint lcnphy_aci_start_time; | 118 | uint lcnphy_aci_start_time; |
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_n.c b/drivers/staging/brcm80211/phy/wlc_phy_n.c index 446d22054f6..617fd80ad4b 100644 --- a/drivers/staging/brcm80211/phy/wlc_phy_n.c +++ b/drivers/staging/brcm80211/phy/wlc_phy_n.c | |||
@@ -141,13 +141,13 @@ | |||
141 | #define NPHY_ADJUSTED_MINCRSPOWER 0x1e | 141 | #define NPHY_ADJUSTED_MINCRSPOWER 0x1e |
142 | 142 | ||
143 | typedef struct _nphy_iqcal_params { | 143 | typedef struct _nphy_iqcal_params { |
144 | uint16 txlpf; | 144 | u16 txlpf; |
145 | uint16 txgm; | 145 | u16 txgm; |
146 | uint16 pga; | 146 | u16 pga; |
147 | uint16 pad; | 147 | u16 pad; |
148 | uint16 ipa; | 148 | u16 ipa; |
149 | uint16 cal_gain; | 149 | u16 cal_gain; |
150 | uint16 ncorr[5]; | 150 | u16 ncorr[5]; |
151 | } nphy_iqcal_params_t; | 151 | } nphy_iqcal_params_t; |
152 | 152 | ||
153 | typedef struct _nphy_txiqcal_ladder { | 153 | typedef struct _nphy_txiqcal_ladder { |
@@ -162,22 +162,22 @@ typedef struct { | |||
162 | } nphy_ipa_txcalgains_t; | 162 | } nphy_ipa_txcalgains_t; |
163 | 163 | ||
164 | typedef struct nphy_papd_restore_state_t { | 164 | typedef struct nphy_papd_restore_state_t { |
165 | uint16 fbmix[2]; | 165 | u16 fbmix[2]; |
166 | uint16 vga_master[2]; | 166 | u16 vga_master[2]; |
167 | uint16 intpa_master[2]; | 167 | u16 intpa_master[2]; |
168 | uint16 afectrl[2]; | 168 | u16 afectrl[2]; |
169 | uint16 afeoverride[2]; | 169 | u16 afeoverride[2]; |
170 | uint16 pwrup[2]; | 170 | u16 pwrup[2]; |
171 | uint16 atten[2]; | 171 | u16 atten[2]; |
172 | uint16 mm; | 172 | u16 mm; |
173 | } nphy_papd_restore_state; | 173 | } nphy_papd_restore_state; |
174 | 174 | ||
175 | typedef struct _nphy_ipa_txrxgain { | 175 | typedef struct _nphy_ipa_txrxgain { |
176 | uint16 hpvga; | 176 | u16 hpvga; |
177 | uint16 lpf_biq1; | 177 | u16 lpf_biq1; |
178 | uint16 lpf_biq0; | 178 | u16 lpf_biq0; |
179 | uint16 lna2; | 179 | u16 lna2; |
180 | uint16 lna1; | 180 | u16 lna1; |
181 | s8 txpwrindex; | 181 | s8 txpwrindex; |
182 | } nphy_ipa_txrxgain_t; | 182 | } nphy_ipa_txrxgain_t; |
183 | 183 | ||
@@ -237,7 +237,7 @@ enum { | |||
237 | #define TXFILT_DEFAULT_OFDM20 3 | 237 | #define TXFILT_DEFAULT_OFDM20 3 |
238 | #define TXFILT_DEFAULT_OFDM40 4 | 238 | #define TXFILT_DEFAULT_OFDM40 4 |
239 | 239 | ||
240 | uint16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = { | 240 | u16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = { |
241 | {-377, 137, -407, 208, -1527, 956, 93, 186, 93, | 241 | {-377, 137, -407, 208, -1527, 956, 93, 186, 93, |
242 | 230, -44, 230, 201, -191, 201}, | 242 | 230, -44, 230, 201, -191, 201}, |
243 | {-77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5, | 243 | {-77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5, |
@@ -255,8 +255,8 @@ uint16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = { | |||
255 | }; | 255 | }; |
256 | 256 | ||
257 | typedef struct _chan_info_nphy_2055 { | 257 | typedef struct _chan_info_nphy_2055 { |
258 | uint16 chan; | 258 | u16 chan; |
259 | uint16 freq; | 259 | u16 freq; |
260 | uint unknown; | 260 | uint unknown; |
261 | u8 RF_pll_ref; | 261 | u8 RF_pll_ref; |
262 | u8 RF_rf_pll_mod1; | 262 | u8 RF_rf_pll_mod1; |
@@ -280,17 +280,17 @@ typedef struct _chan_info_nphy_2055 { | |||
280 | u8 RF_core2_rxrf_reg1; | 280 | u8 RF_core2_rxrf_reg1; |
281 | u8 RF_core2_tx_pga_pad_tn; | 281 | u8 RF_core2_tx_pga_pad_tn; |
282 | u8 RF_core2_tx_mx_bgtrim; | 282 | u8 RF_core2_tx_mx_bgtrim; |
283 | uint16 PHY_BW1a; | 283 | u16 PHY_BW1a; |
284 | uint16 PHY_BW2; | 284 | u16 PHY_BW2; |
285 | uint16 PHY_BW3; | 285 | u16 PHY_BW3; |
286 | uint16 PHY_BW4; | 286 | u16 PHY_BW4; |
287 | uint16 PHY_BW5; | 287 | u16 PHY_BW5; |
288 | uint16 PHY_BW6; | 288 | u16 PHY_BW6; |
289 | } chan_info_nphy_2055_t; | 289 | } chan_info_nphy_2055_t; |
290 | 290 | ||
291 | typedef struct _chan_info_nphy_radio205x { | 291 | typedef struct _chan_info_nphy_radio205x { |
292 | uint16 chan; | 292 | u16 chan; |
293 | uint16 freq; | 293 | u16 freq; |
294 | u8 RF_SYN_pll_vcocal1; | 294 | u8 RF_SYN_pll_vcocal1; |
295 | u8 RF_SYN_pll_vcocal2; | 295 | u8 RF_SYN_pll_vcocal2; |
296 | u8 RF_SYN_pll_refdiv; | 296 | u8 RF_SYN_pll_refdiv; |
@@ -328,17 +328,17 @@ typedef struct _chan_info_nphy_radio205x { | |||
328 | u8 RF_TX1_pgag_boost_tune; | 328 | u8 RF_TX1_pgag_boost_tune; |
329 | u8 RF_TX1_mixa_boost_tune; | 329 | u8 RF_TX1_mixa_boost_tune; |
330 | u8 RF_TX1_mixg_boost_tune; | 330 | u8 RF_TX1_mixg_boost_tune; |
331 | uint16 PHY_BW1a; | 331 | u16 PHY_BW1a; |
332 | uint16 PHY_BW2; | 332 | u16 PHY_BW2; |
333 | uint16 PHY_BW3; | 333 | u16 PHY_BW3; |
334 | uint16 PHY_BW4; | 334 | u16 PHY_BW4; |
335 | uint16 PHY_BW5; | 335 | u16 PHY_BW5; |
336 | uint16 PHY_BW6; | 336 | u16 PHY_BW6; |
337 | } chan_info_nphy_radio205x_t; | 337 | } chan_info_nphy_radio205x_t; |
338 | 338 | ||
339 | typedef struct _chan_info_nphy_radio2057 { | 339 | typedef struct _chan_info_nphy_radio2057 { |
340 | uint16 chan; | 340 | u16 chan; |
341 | uint16 freq; | 341 | u16 freq; |
342 | u8 RF_vcocal_countval0; | 342 | u8 RF_vcocal_countval0; |
343 | u8 RF_vcocal_countval1; | 343 | u8 RF_vcocal_countval1; |
344 | u8 RF_rfpll_refmaster_sparextalsize; | 344 | u8 RF_rfpll_refmaster_sparextalsize; |
@@ -367,17 +367,17 @@ typedef struct _chan_info_nphy_radio2057 { | |||
367 | u8 RF_pad5g_tune_misc_pus_core1; | 367 | u8 RF_pad5g_tune_misc_pus_core1; |
368 | u8 RF_lna2g_tune_core1; | 368 | u8 RF_lna2g_tune_core1; |
369 | u8 RF_lna5g_tune_core1; | 369 | u8 RF_lna5g_tune_core1; |
370 | uint16 PHY_BW1a; | 370 | u16 PHY_BW1a; |
371 | uint16 PHY_BW2; | 371 | u16 PHY_BW2; |
372 | uint16 PHY_BW3; | 372 | u16 PHY_BW3; |
373 | uint16 PHY_BW4; | 373 | u16 PHY_BW4; |
374 | uint16 PHY_BW5; | 374 | u16 PHY_BW5; |
375 | uint16 PHY_BW6; | 375 | u16 PHY_BW6; |
376 | } chan_info_nphy_radio2057_t; | 376 | } chan_info_nphy_radio2057_t; |
377 | 377 | ||
378 | typedef struct _chan_info_nphy_radio2057_rev5 { | 378 | typedef struct _chan_info_nphy_radio2057_rev5 { |
379 | uint16 chan; | 379 | u16 chan; |
380 | uint16 freq; | 380 | u16 freq; |
381 | u8 RF_vcocal_countval0; | 381 | u8 RF_vcocal_countval0; |
382 | u8 RF_vcocal_countval1; | 382 | u8 RF_vcocal_countval1; |
383 | u8 RF_rfpll_refmaster_sparextalsize; | 383 | u8 RF_rfpll_refmaster_sparextalsize; |
@@ -396,21 +396,21 @@ typedef struct _chan_info_nphy_radio2057_rev5 { | |||
396 | u8 RF_txmix2g_tune_boost_pu_core1; | 396 | u8 RF_txmix2g_tune_boost_pu_core1; |
397 | u8 RF_pad2g_tune_pus_core1; | 397 | u8 RF_pad2g_tune_pus_core1; |
398 | u8 RF_lna2g_tune_core1; | 398 | u8 RF_lna2g_tune_core1; |
399 | uint16 PHY_BW1a; | 399 | u16 PHY_BW1a; |
400 | uint16 PHY_BW2; | 400 | u16 PHY_BW2; |
401 | uint16 PHY_BW3; | 401 | u16 PHY_BW3; |
402 | uint16 PHY_BW4; | 402 | u16 PHY_BW4; |
403 | uint16 PHY_BW5; | 403 | u16 PHY_BW5; |
404 | uint16 PHY_BW6; | 404 | u16 PHY_BW6; |
405 | } chan_info_nphy_radio2057_rev5_t; | 405 | } chan_info_nphy_radio2057_rev5_t; |
406 | 406 | ||
407 | typedef struct nphy_sfo_cfg { | 407 | typedef struct nphy_sfo_cfg { |
408 | uint16 PHY_BW1a; | 408 | u16 PHY_BW1a; |
409 | uint16 PHY_BW2; | 409 | u16 PHY_BW2; |
410 | uint16 PHY_BW3; | 410 | u16 PHY_BW3; |
411 | uint16 PHY_BW4; | 411 | u16 PHY_BW4; |
412 | uint16 PHY_BW5; | 412 | u16 PHY_BW5; |
413 | uint16 PHY_BW6; | 413 | u16 PHY_BW6; |
414 | } nphy_sfo_cfg_t; | 414 | } nphy_sfo_cfg_t; |
415 | 415 | ||
416 | static chan_info_nphy_2055_t chan_info_nphy_2055[] = { | 416 | static chan_info_nphy_2055_t chan_info_nphy_2055[] = { |
@@ -13285,7 +13285,7 @@ static int16 nphy_def_lnagains[] = { -2, 10, 19, 25 }; | |||
13285 | static int32 nphy_lnagain_est0[] = { -315, 40370 }; | 13285 | static int32 nphy_lnagain_est0[] = { -315, 40370 }; |
13286 | static int32 nphy_lnagain_est1[] = { -224, 23242 }; | 13286 | static int32 nphy_lnagain_est1[] = { -224, 23242 }; |
13287 | 13287 | ||
13288 | static const uint16 tbl_iqcal_gainparams_nphy[2][NPHY_IQCAL_NUMGAINS][8] = { | 13288 | static const u16 tbl_iqcal_gainparams_nphy[2][NPHY_IQCAL_NUMGAINS][8] = { |
13289 | { | 13289 | { |
13290 | {0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69}, | 13290 | {0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69}, |
13291 | {0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69}, | 13291 | {0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69}, |
@@ -13345,7 +13345,7 @@ static const uint32 nphy_tpc_txgain[] = { | |||
13345 | 0x03801442, 0x03801344, 0x03801342, 0x00002b00 | 13345 | 0x03801442, 0x03801344, 0x03801342, 0x00002b00 |
13346 | }; | 13346 | }; |
13347 | 13347 | ||
13348 | static const uint16 nphy_tpc_loscale[] = { | 13348 | static const u16 nphy_tpc_loscale[] = { |
13349 | 256, 256, 271, 271, 287, 256, 256, 271, | 13349 | 256, 256, 271, 271, 287, 256, 256, 271, |
13350 | 271, 287, 287, 304, 304, 256, 256, 271, | 13350 | 271, 287, 287, 304, 304, 256, 256, 271, |
13351 | 271, 287, 287, 304, 304, 322, 322, 341, | 13351 | 271, 287, 287, 304, 304, 322, 322, 341, |
@@ -14091,7 +14091,7 @@ static void wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chans, | |||
14091 | const nphy_sfo_cfg_t *c); | 14091 | const nphy_sfo_cfg_t *c); |
14092 | 14092 | ||
14093 | static void wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, | 14093 | static void wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, |
14094 | uint16 reduction_factr); | 14094 | u16 reduction_factr); |
14095 | static void wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *, | 14095 | static void wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *, |
14096 | uint32 *buf); | 14096 | uint32 *buf); |
14097 | static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr); | 14097 | static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr); |
@@ -14118,7 +14118,7 @@ static void wlc_phy_tx_iq_war_nphy(phy_info_t *pi); | |||
14118 | static int wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t tg, | 14118 | static int wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t tg, |
14119 | u8 type, bool d); | 14119 | u8 type, bool d); |
14120 | static void wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rxcore, | 14120 | static void wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rxcore, |
14121 | uint16 *rg, u8 type); | 14121 | u16 *rg, u8 type); |
14122 | static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, int32 preamble); | 14122 | static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, int32 preamble); |
14123 | static void wlc_phy_savecal_nphy(phy_info_t *pi); | 14123 | static void wlc_phy_savecal_nphy(phy_info_t *pi); |
14124 | static void wlc_phy_restorecal_nphy(phy_info_t *pi); | 14124 | static void wlc_phy_restorecal_nphy(phy_info_t *pi); |
@@ -14127,12 +14127,12 @@ static void wlc_phy_resetcca_nphy(phy_info_t *pi); | |||
14127 | static void wlc_phy_txpwrctrl_config_nphy(phy_info_t *pi); | 14127 | static void wlc_phy_txpwrctrl_config_nphy(phy_info_t *pi); |
14128 | static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi); | 14128 | static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi); |
14129 | static void wlc_phy_precal_txgain_nphy(phy_info_t *pi); | 14129 | static void wlc_phy_precal_txgain_nphy(phy_info_t *pi); |
14130 | static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, uint16 core); | 14130 | static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core); |
14131 | 14131 | ||
14132 | static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi); | 14132 | static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi); |
14133 | static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi); | 14133 | static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi); |
14134 | static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi); | 14134 | static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi); |
14135 | static uint16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi); | 14135 | static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi); |
14136 | static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1); | 14136 | static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1); |
14137 | static uint32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi); | 14137 | static uint32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi); |
14138 | 14138 | ||
@@ -14146,15 +14146,15 @@ static void wlc_phy_papd_cal_cleanup_nphy(phy_info_t *pi, | |||
14146 | static void wlc_phy_papd_cal_setup_nphy(phy_info_t *pi, | 14146 | static void wlc_phy_papd_cal_setup_nphy(phy_info_t *pi, |
14147 | nphy_papd_restore_state *state, u8); | 14147 | nphy_papd_restore_state *state, u8); |
14148 | 14148 | ||
14149 | static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, uint16 *vals); | 14149 | static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, u16 *vals); |
14150 | 14150 | ||
14151 | static void wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *evts, | 14151 | static void wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *evts, |
14152 | u8 *dlys, u8 len); | 14152 | u8 *dlys, u8 len); |
14153 | 14153 | ||
14154 | static uint16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, uint16 offset); | 14154 | static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset); |
14155 | 14155 | ||
14156 | static void | 14156 | static void |
14157 | wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, uint16 field, uint16 value, | 14157 | wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, u16 field, u16 value, |
14158 | u8 core_mask, u8 off, | 14158 | u8 core_mask, u8 off, |
14159 | u8 override_id); | 14159 | u8 override_id); |
14160 | 14160 | ||
@@ -14163,7 +14163,7 @@ static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi); | |||
14163 | 14163 | ||
14164 | static bool wlc_phy_txpwr_srom_read_nphy(phy_info_t *pi); | 14164 | static bool wlc_phy_txpwr_srom_read_nphy(phy_info_t *pi); |
14165 | static void wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max, | 14165 | static void wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max, |
14166 | uint16 *pwr_offset, | 14166 | u16 *pwr_offset, |
14167 | u8 tmp_max_pwr, u8 rate_start, | 14167 | u8 tmp_max_pwr, u8 rate_start, |
14168 | u8 rate_end); | 14168 | u8 rate_end); |
14169 | 14169 | ||
@@ -14178,17 +14178,17 @@ static void wlc_phy_txpwr_idx_cur_set_nphy(phy_info_t *pi, u8 idx0, | |||
14178 | u8 idx1); | 14178 | u8 idx1); |
14179 | static void wlc_phy_a4(phy_info_t *pi, bool full_cal); | 14179 | static void wlc_phy_a4(phy_info_t *pi, bool full_cal); |
14180 | 14180 | ||
14181 | static uint16 wlc_phy_radio205x_rcal(phy_info_t *pi); | 14181 | static u16 wlc_phy_radio205x_rcal(phy_info_t *pi); |
14182 | 14182 | ||
14183 | static uint16 wlc_phy_radio2057_rccal(phy_info_t *pi); | 14183 | static u16 wlc_phy_radio2057_rccal(phy_info_t *pi); |
14184 | 14184 | ||
14185 | static uint16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, | 14185 | static u16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, |
14186 | uint16 max_val, | 14186 | u16 max_val, |
14187 | u8 dac_test_mode); | 14187 | u8 dac_test_mode); |
14188 | static void wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf, | 14188 | static void wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf, |
14189 | uint16 num_samps); | 14189 | u16 num_samps); |
14190 | static void wlc_phy_runsamples_nphy(phy_info_t *pi, uint16 n, uint16 lps, | 14190 | static void wlc_phy_runsamples_nphy(phy_info_t *pi, u16 n, u16 lps, |
14191 | uint16 wait, u8 iq, u8 dac_test_mode, | 14191 | u16 wait, u8 iq, u8 dac_test_mode, |
14192 | bool modify_bbmult); | 14192 | bool modify_bbmult); |
14193 | 14193 | ||
14194 | bool wlc_phy_bist_check_phy(wlc_phy_t *pih) | 14194 | bool wlc_phy_bist_check_phy(wlc_phy_t *pih) |
@@ -14215,7 +14215,7 @@ bool wlc_phy_bist_check_phy(wlc_phy_t *pih) | |||
14215 | 14215 | ||
14216 | static void WLBANDINITFN(wlc_phy_bphy_init_nphy) (phy_info_t *pi) | 14216 | static void WLBANDINITFN(wlc_phy_bphy_init_nphy) (phy_info_t *pi) |
14217 | { | 14217 | { |
14218 | uint16 addr, val; | 14218 | u16 addr, val; |
14219 | 14219 | ||
14220 | ASSERT(ISNPHY(pi)); | 14220 | ASSERT(ISNPHY(pi)); |
14221 | 14221 | ||
@@ -14420,7 +14420,7 @@ static void WLBANDINITFN(wlc_phy_tbl_init_nphy) (phy_info_t *pi) | |||
14420 | } | 14420 | } |
14421 | 14421 | ||
14422 | static void | 14422 | static void |
14423 | wlc_phy_write_txmacreg_nphy(phy_info_t *pi, uint16 holdoff, uint16 delay) | 14423 | wlc_phy_write_txmacreg_nphy(phy_info_t *pi, u16 holdoff, u16 delay) |
14424 | { | 14424 | { |
14425 | write_phy_reg(pi, 0x77, holdoff); | 14425 | write_phy_reg(pi, 0x77, holdoff); |
14426 | write_phy_reg(pi, 0xb4, delay); | 14426 | write_phy_reg(pi, 0xb4, delay); |
@@ -14428,7 +14428,7 @@ wlc_phy_write_txmacreg_nphy(phy_info_t *pi, uint16 holdoff, uint16 delay) | |||
14428 | 14428 | ||
14429 | void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs) | 14429 | void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs) |
14430 | { | 14430 | { |
14431 | uint16 holdoff, delay; | 14431 | u16 holdoff, delay; |
14432 | 14432 | ||
14433 | if (rifs) { | 14433 | if (rifs) { |
14434 | 14434 | ||
@@ -14528,8 +14528,8 @@ static void BCMATTACHFN(wlc_phy_txpwrctrl_config_nphy) (phy_info_t *pi) | |||
14528 | 14528 | ||
14529 | void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi) | 14529 | void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi) |
14530 | { | 14530 | { |
14531 | uint16 val; | 14531 | u16 val; |
14532 | uint16 clip1_ths[2]; | 14532 | u16 clip1_ths[2]; |
14533 | nphy_txgains_t target_gain; | 14533 | nphy_txgains_t target_gain; |
14534 | u8 tx_pwr_ctrl_state; | 14534 | u8 tx_pwr_ctrl_state; |
14535 | bool do_nphy_cal = FALSE; | 14535 | bool do_nphy_cal = FALSE; |
@@ -14705,7 +14705,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi) | |||
14705 | 14705 | ||
14706 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 14706 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
14707 | uint32 *tx_pwrctrl_tbl = NULL; | 14707 | uint32 *tx_pwrctrl_tbl = NULL; |
14708 | uint16 idx; | 14708 | u16 idx; |
14709 | int16 pga_gn = 0; | 14709 | int16 pga_gn = 0; |
14710 | int16 pad_gn = 0; | 14710 | int16 pad_gn = 0; |
14711 | int32 rfpwr_offset = 0; | 14711 | int32 rfpwr_offset = 0; |
@@ -14757,7 +14757,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi) | |||
14757 | wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128, | 14757 | wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128, |
14758 | 192, 32, tx_pwrctrl_tbl); | 14758 | 192, 32, tx_pwrctrl_tbl); |
14759 | 14759 | ||
14760 | pi->nphy_gmval = (uint16) ((*tx_pwrctrl_tbl >> 16) & 0x7000); | 14760 | pi->nphy_gmval = (u16) ((*tx_pwrctrl_tbl >> 16) & 0x7000); |
14761 | 14761 | ||
14762 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 14762 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
14763 | 14763 | ||
@@ -14942,7 +14942,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi) | |||
14942 | static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, int32 preamble) | 14942 | static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, int32 preamble) |
14943 | { | 14943 | { |
14944 | bool gf_preamble = FALSE; | 14944 | bool gf_preamble = FALSE; |
14945 | uint16 val; | 14945 | u16 val; |
14946 | 14946 | ||
14947 | if (preamble == WLC_N_PREAMBLE_GF) { | 14947 | if (preamble == WLC_N_PREAMBLE_GF) { |
14948 | gf_preamble = TRUE; | 14948 | gf_preamble = TRUE; |
@@ -14960,7 +14960,7 @@ static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, int32 preamble) | |||
14960 | 14960 | ||
14961 | static void wlc_phy_resetcca_nphy(phy_info_t *pi) | 14961 | static void wlc_phy_resetcca_nphy(phy_info_t *pi) |
14962 | { | 14962 | { |
14963 | uint16 val; | 14963 | u16 val; |
14964 | 14964 | ||
14965 | ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)); | 14965 | ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)); |
14966 | 14966 | ||
@@ -14978,7 +14978,7 @@ static void wlc_phy_resetcca_nphy(phy_info_t *pi) | |||
14978 | 14978 | ||
14979 | void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en) | 14979 | void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en) |
14980 | { | 14980 | { |
14981 | uint16 rfctrlintc_override_val; | 14981 | u16 rfctrlintc_override_val; |
14982 | 14982 | ||
14983 | if (!en) { | 14983 | if (!en) { |
14984 | 14984 | ||
@@ -15008,7 +15008,7 @@ void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en) | |||
15008 | void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi) | 15008 | void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi) |
15009 | { | 15009 | { |
15010 | 15010 | ||
15011 | uint16 txrx_chain = | 15011 | u16 txrx_chain = |
15012 | (NPHY_RfseqCoreActv_TxRxChain0 | NPHY_RfseqCoreActv_TxRxChain1); | 15012 | (NPHY_RfseqCoreActv_TxRxChain0 | NPHY_RfseqCoreActv_TxRxChain1); |
15013 | bool CoreActv_override = FALSE; | 15013 | bool CoreActv_override = FALSE; |
15014 | 15014 | ||
@@ -15042,11 +15042,11 @@ void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi) | |||
15042 | 15042 | ||
15043 | void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask) | 15043 | void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask) |
15044 | { | 15044 | { |
15045 | uint16 regval; | 15045 | u16 regval; |
15046 | uint16 tbl_buf[16]; | 15046 | u16 tbl_buf[16]; |
15047 | uint i; | 15047 | uint i; |
15048 | phy_info_t *pi = (phy_info_t *) pih; | 15048 | phy_info_t *pi = (phy_info_t *) pih; |
15049 | uint16 tbl_opcode; | 15049 | u16 tbl_opcode; |
15050 | bool suspend; | 15050 | bool suspend; |
15051 | 15051 | ||
15052 | pi->sh->phyrxchain = rxcore_bitmask; | 15052 | pi->sh->phyrxchain = rxcore_bitmask; |
@@ -15064,7 +15064,7 @@ void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask) | |||
15064 | 15064 | ||
15065 | regval = read_phy_reg(pi, 0xa2); | 15065 | regval = read_phy_reg(pi, 0xa2); |
15066 | regval &= ~(0xf << 4); | 15066 | regval &= ~(0xf << 4); |
15067 | regval |= ((uint16) (rxcore_bitmask & 0x3)) << 4; | 15067 | regval |= ((u16) (rxcore_bitmask & 0x3)) << 4; |
15068 | write_phy_reg(pi, 0xa2, regval); | 15068 | write_phy_reg(pi, 0xa2, regval); |
15069 | 15069 | ||
15070 | if ((rxcore_bitmask & 0x3) != 0x3) { | 15070 | if ((rxcore_bitmask & 0x3) != 0x3) { |
@@ -15123,7 +15123,7 @@ void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask) | |||
15123 | 15123 | ||
15124 | u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih) | 15124 | u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih) |
15125 | { | 15125 | { |
15126 | uint16 regval, rxen_bits; | 15126 | u16 regval, rxen_bits; |
15127 | phy_info_t *pi = (phy_info_t *) pih; | 15127 | phy_info_t *pi = (phy_info_t *) pih; |
15128 | 15128 | ||
15129 | regval = read_phy_reg(pi, 0xa2); | 15129 | regval = read_phy_reg(pi, 0xa2); |
@@ -15327,56 +15327,56 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi) | |||
15327 | NPHY_REV3_RFSEQ_CMD_END | 15327 | NPHY_REV3_RFSEQ_CMD_END |
15328 | }; | 15328 | }; |
15329 | u8 rfseq_rx2tx_dlys_rev3_ipa[] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; | 15329 | u8 rfseq_rx2tx_dlys_rev3_ipa[] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; |
15330 | uint16 rfseq_rx2tx_dacbufpu_rev7[] = { 0x10f, 0x10f }; | 15330 | u16 rfseq_rx2tx_dacbufpu_rev7[] = { 0x10f, 0x10f }; |
15331 | 15331 | ||
15332 | int16 alpha0, alpha1, alpha2; | 15332 | int16 alpha0, alpha1, alpha2; |
15333 | int16 beta0, beta1, beta2; | 15333 | int16 beta0, beta1, beta2; |
15334 | uint32 leg_data_weights, ht_data_weights, nss1_data_weights, | 15334 | uint32 leg_data_weights, ht_data_weights, nss1_data_weights, |
15335 | stbc_data_weights; | 15335 | stbc_data_weights; |
15336 | u8 chan_freq_range = 0; | 15336 | u8 chan_freq_range = 0; |
15337 | uint16 dac_control = 0x0002; | 15337 | u16 dac_control = 0x0002; |
15338 | uint16 aux_adc_vmid_rev7_core0[] = { 0x8e, 0x96, 0x96, 0x96 }; | 15338 | u16 aux_adc_vmid_rev7_core0[] = { 0x8e, 0x96, 0x96, 0x96 }; |
15339 | uint16 aux_adc_vmid_rev7_core1[] = { 0x8f, 0x9f, 0x9f, 0x96 }; | 15339 | u16 aux_adc_vmid_rev7_core1[] = { 0x8f, 0x9f, 0x9f, 0x96 }; |
15340 | uint16 aux_adc_vmid_rev4[] = { 0xa2, 0xb4, 0xb4, 0x89 }; | 15340 | u16 aux_adc_vmid_rev4[] = { 0xa2, 0xb4, 0xb4, 0x89 }; |
15341 | uint16 aux_adc_vmid_rev3[] = { 0xa2, 0xb4, 0xb4, 0x89 }; | 15341 | u16 aux_adc_vmid_rev3[] = { 0xa2, 0xb4, 0xb4, 0x89 }; |
15342 | uint16 *aux_adc_vmid; | 15342 | u16 *aux_adc_vmid; |
15343 | uint16 aux_adc_gain_rev7[] = { 0x02, 0x02, 0x02, 0x02 }; | 15343 | u16 aux_adc_gain_rev7[] = { 0x02, 0x02, 0x02, 0x02 }; |
15344 | uint16 aux_adc_gain_rev4[] = { 0x02, 0x02, 0x02, 0x00 }; | 15344 | u16 aux_adc_gain_rev4[] = { 0x02, 0x02, 0x02, 0x00 }; |
15345 | uint16 aux_adc_gain_rev3[] = { 0x02, 0x02, 0x02, 0x00 }; | 15345 | u16 aux_adc_gain_rev3[] = { 0x02, 0x02, 0x02, 0x00 }; |
15346 | uint16 *aux_adc_gain; | 15346 | u16 *aux_adc_gain; |
15347 | uint16 sk_adc_vmid[] = { 0xb4, 0xb4, 0xb4, 0x24 }; | 15347 | u16 sk_adc_vmid[] = { 0xb4, 0xb4, 0xb4, 0x24 }; |
15348 | uint16 sk_adc_gain[] = { 0x02, 0x02, 0x02, 0x02 }; | 15348 | u16 sk_adc_gain[] = { 0x02, 0x02, 0x02, 0x02 }; |
15349 | int32 min_nvar_val = 0x18d; | 15349 | int32 min_nvar_val = 0x18d; |
15350 | int32 min_nvar_offset_6mbps = 20; | 15350 | int32 min_nvar_offset_6mbps = 20; |
15351 | u8 pdetrange; | 15351 | u8 pdetrange; |
15352 | u8 triso; | 15352 | u8 triso; |
15353 | uint16 regval; | 15353 | u16 regval; |
15354 | uint16 afectrl_adc_ctrl1_rev7 = 0x20; | 15354 | u16 afectrl_adc_ctrl1_rev7 = 0x20; |
15355 | uint16 afectrl_adc_ctrl2_rev7 = 0x0; | 15355 | u16 afectrl_adc_ctrl2_rev7 = 0x0; |
15356 | uint16 rfseq_rx2tx_lpf_h_hpc_rev7 = 0x77; | 15356 | u16 rfseq_rx2tx_lpf_h_hpc_rev7 = 0x77; |
15357 | uint16 rfseq_tx2rx_lpf_h_hpc_rev7 = 0x77; | 15357 | u16 rfseq_tx2rx_lpf_h_hpc_rev7 = 0x77; |
15358 | uint16 rfseq_pktgn_lpf_h_hpc_rev7 = 0x77; | 15358 | u16 rfseq_pktgn_lpf_h_hpc_rev7 = 0x77; |
15359 | uint16 rfseq_htpktgn_lpf_hpc_rev7[] = { 0x77, 0x11, 0x11 }; | 15359 | u16 rfseq_htpktgn_lpf_hpc_rev7[] = { 0x77, 0x11, 0x11 }; |
15360 | uint16 rfseq_pktgn_lpf_hpc_rev7[] = { 0x11, 0x11 }; | 15360 | u16 rfseq_pktgn_lpf_hpc_rev7[] = { 0x11, 0x11 }; |
15361 | uint16 rfseq_cckpktgn_lpf_hpc_rev7[] = { 0x11, 0x11 }; | 15361 | u16 rfseq_cckpktgn_lpf_hpc_rev7[] = { 0x11, 0x11 }; |
15362 | uint16 ipalvlshift_3p3_war_en = 0; | 15362 | u16 ipalvlshift_3p3_war_en = 0; |
15363 | uint16 rccal_bcap_val, rccal_scap_val; | 15363 | u16 rccal_bcap_val, rccal_scap_val; |
15364 | uint16 rccal_tx20_11b_bcap = 0; | 15364 | u16 rccal_tx20_11b_bcap = 0; |
15365 | uint16 rccal_tx20_11b_scap = 0; | 15365 | u16 rccal_tx20_11b_scap = 0; |
15366 | uint16 rccal_tx20_11n_bcap = 0; | 15366 | u16 rccal_tx20_11n_bcap = 0; |
15367 | uint16 rccal_tx20_11n_scap = 0; | 15367 | u16 rccal_tx20_11n_scap = 0; |
15368 | uint16 rccal_tx40_11n_bcap = 0; | 15368 | u16 rccal_tx40_11n_bcap = 0; |
15369 | uint16 rccal_tx40_11n_scap = 0; | 15369 | u16 rccal_tx40_11n_scap = 0; |
15370 | uint16 rx2tx_lpf_rc_lut_tx20_11b = 0; | 15370 | u16 rx2tx_lpf_rc_lut_tx20_11b = 0; |
15371 | uint16 rx2tx_lpf_rc_lut_tx20_11n = 0; | 15371 | u16 rx2tx_lpf_rc_lut_tx20_11n = 0; |
15372 | uint16 rx2tx_lpf_rc_lut_tx40_11n = 0; | 15372 | u16 rx2tx_lpf_rc_lut_tx40_11n = 0; |
15373 | uint16 tx_lpf_bw_ofdm_20mhz = 0; | 15373 | u16 tx_lpf_bw_ofdm_20mhz = 0; |
15374 | uint16 tx_lpf_bw_ofdm_40mhz = 0; | 15374 | u16 tx_lpf_bw_ofdm_40mhz = 0; |
15375 | uint16 tx_lpf_bw_11b = 0; | 15375 | u16 tx_lpf_bw_11b = 0; |
15376 | uint16 ipa2g_mainbias, ipa2g_casconv, ipa2g_biasfilt; | 15376 | u16 ipa2g_mainbias, ipa2g_casconv, ipa2g_biasfilt; |
15377 | uint16 txgm_idac_bleed = 0; | 15377 | u16 txgm_idac_bleed = 0; |
15378 | bool rccal_ovrd = FALSE; | 15378 | bool rccal_ovrd = FALSE; |
15379 | uint16 freq; | 15379 | u16 freq; |
15380 | int coreNum; | 15380 | int coreNum; |
15381 | 15381 | ||
15382 | if (CHSPEC_IS5G(pi->radio_chanspec)) { | 15382 | if (CHSPEC_IS5G(pi->radio_chanspec)) { |
@@ -16047,8 +16047,8 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi) | |||
16047 | 0x1c, 16, sk_adc_gain); | 16047 | 0x1c, 16, sk_adc_gain); |
16048 | } else if (pdetrange == 2) { | 16048 | } else if (pdetrange == 2) { |
16049 | 16049 | ||
16050 | uint16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x74 }; | 16050 | u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x74 }; |
16051 | uint16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x04 }; | 16051 | u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x04 }; |
16052 | 16052 | ||
16053 | if (NREV_GE(pi->pubpi.phy_rev, 6)) { | 16053 | if (NREV_GE(pi->pubpi.phy_rev, 6)) { |
16054 | chan_freq_range = | 16054 | chan_freq_range = |
@@ -16079,9 +16079,9 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi) | |||
16079 | if ((NREV_GE(pi->pubpi.phy_rev, 4)) | 16079 | if ((NREV_GE(pi->pubpi.phy_rev, 4)) |
16080 | && (chan_freq_range == WL_CHAN_FREQ_RANGE_2G)) { | 16080 | && (chan_freq_range == WL_CHAN_FREQ_RANGE_2G)) { |
16081 | 16081 | ||
16082 | uint16 auxadc_vmid[] = { | 16082 | u16 auxadc_vmid[] = { |
16083 | 0xa2, 0xb4, 0xb4, 0x270 }; | 16083 | 0xa2, 0xb4, 0xb4, 0x270 }; |
16084 | uint16 auxadc_gain[] = { | 16084 | u16 auxadc_gain[] = { |
16085 | 0x02, 0x02, 0x02, 0x00 }; | 16085 | 0x02, 0x02, 0x02, 0x00 }; |
16086 | 16086 | ||
16087 | wlc_phy_table_write_nphy(pi, | 16087 | wlc_phy_table_write_nphy(pi, |
@@ -16098,9 +16098,9 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi) | |||
16098 | 0x1c, 16, auxadc_gain); | 16098 | 0x1c, 16, auxadc_gain); |
16099 | } | 16099 | } |
16100 | } else if ((pdetrange == 4) || (pdetrange == 5)) { | 16100 | } else if ((pdetrange == 4) || (pdetrange == 5)) { |
16101 | uint16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x0 }; | 16101 | u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x0 }; |
16102 | uint16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x0 }; | 16102 | u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x0 }; |
16103 | uint16 Vmid[2], Av[2]; | 16103 | u16 Vmid[2], Av[2]; |
16104 | 16104 | ||
16105 | chan_freq_range = | 16105 | chan_freq_range = |
16106 | wlc_phy_get_chan_freq_range_nphy(pi, 0); | 16106 | wlc_phy_get_chan_freq_range_nphy(pi, 0); |
@@ -16348,7 +16348,7 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi) | |||
16348 | 16348 | ||
16349 | static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi) | 16349 | static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi) |
16350 | { | 16350 | { |
16351 | uint16 w1th, hpf_code, currband; | 16351 | u16 w1th, hpf_code, currband; |
16352 | int ctr; | 16352 | int ctr; |
16353 | u8 rfseq_updategainu_events[] = { | 16353 | u8 rfseq_updategainu_events[] = { |
16354 | NPHY_RFSEQ_CMD_RX_GAIN, | 16354 | NPHY_RFSEQ_CMD_RX_GAIN, |
@@ -16399,62 +16399,62 @@ static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi) | |||
16399 | s8 *tia_gainbits; | 16399 | s8 *tia_gainbits; |
16400 | s8 lpf_gain_db[] = { 0x00, 0x06, 0x0c, 0x12, 0x12, 0x12 }; | 16400 | s8 lpf_gain_db[] = { 0x00, 0x06, 0x0c, 0x12, 0x12, 0x12 }; |
16401 | s8 lpf_gainbits[] = { 0x00, 0x01, 0x02, 0x03, 0x03, 0x03 }; | 16401 | s8 lpf_gainbits[] = { 0x00, 0x01, 0x02, 0x03, 0x03, 0x03 }; |
16402 | uint16 rfseqG_init_gain[] = { 0x613f, 0x613f, 0x613f, 0x613f }; | 16402 | u16 rfseqG_init_gain[] = { 0x613f, 0x613f, 0x613f, 0x613f }; |
16403 | uint16 rfseqG_init_gain_rev4[] = { 0x513f, 0x513f, 0x513f, 0x513f }; | 16403 | u16 rfseqG_init_gain_rev4[] = { 0x513f, 0x513f, 0x513f, 0x513f }; |
16404 | uint16 rfseqG_init_gain_rev5[] = { 0x413f, 0x413f, 0x413f, 0x413f }; | 16404 | u16 rfseqG_init_gain_rev5[] = { 0x413f, 0x413f, 0x413f, 0x413f }; |
16405 | uint16 rfseqG_init_gain_rev5_elna[] = { | 16405 | u16 rfseqG_init_gain_rev5_elna[] = { |
16406 | 0x013f, 0x013f, 0x013f, 0x013f }; | 16406 | 0x013f, 0x013f, 0x013f, 0x013f }; |
16407 | uint16 rfseqG_init_gain_rev6[] = { 0x513f, 0x513f }; | 16407 | u16 rfseqG_init_gain_rev6[] = { 0x513f, 0x513f }; |
16408 | uint16 rfseqG_init_gain_rev6_224B0[] = { 0x413f, 0x413f }; | 16408 | u16 rfseqG_init_gain_rev6_224B0[] = { 0x413f, 0x413f }; |
16409 | uint16 rfseqG_init_gain_rev6_elna[] = { 0x113f, 0x113f }; | 16409 | u16 rfseqG_init_gain_rev6_elna[] = { 0x113f, 0x113f }; |
16410 | uint16 rfseqA_init_gain[] = { 0x516f, 0x516f, 0x516f, 0x516f }; | 16410 | u16 rfseqA_init_gain[] = { 0x516f, 0x516f, 0x516f, 0x516f }; |
16411 | uint16 rfseqA_init_gain_rev4[] = { 0x614f, 0x614f, 0x614f, 0x614f }; | 16411 | u16 rfseqA_init_gain_rev4[] = { 0x614f, 0x614f, 0x614f, 0x614f }; |
16412 | uint16 rfseqA_init_gain_rev4_elna[] = { | 16412 | u16 rfseqA_init_gain_rev4_elna[] = { |
16413 | 0x314f, 0x314f, 0x314f, 0x314f }; | 16413 | 0x314f, 0x314f, 0x314f, 0x314f }; |
16414 | uint16 rfseqA_init_gain_rev5[] = { 0x714f, 0x714f, 0x714f, 0x714f }; | 16414 | u16 rfseqA_init_gain_rev5[] = { 0x714f, 0x714f, 0x714f, 0x714f }; |
16415 | uint16 rfseqA_init_gain_rev6[] = { 0x714f, 0x714f }; | 16415 | u16 rfseqA_init_gain_rev6[] = { 0x714f, 0x714f }; |
16416 | uint16 *rfseq_init_gain; | 16416 | u16 *rfseq_init_gain; |
16417 | uint16 initG_gaincode = 0x627e; | 16417 | u16 initG_gaincode = 0x627e; |
16418 | uint16 initG_gaincode_rev4 = 0x527e; | 16418 | u16 initG_gaincode_rev4 = 0x527e; |
16419 | uint16 initG_gaincode_rev5 = 0x427e; | 16419 | u16 initG_gaincode_rev5 = 0x427e; |
16420 | uint16 initG_gaincode_rev5_elna = 0x027e; | 16420 | u16 initG_gaincode_rev5_elna = 0x027e; |
16421 | uint16 initG_gaincode_rev6 = 0x527e; | 16421 | u16 initG_gaincode_rev6 = 0x527e; |
16422 | uint16 initG_gaincode_rev6_224B0 = 0x427e; | 16422 | u16 initG_gaincode_rev6_224B0 = 0x427e; |
16423 | uint16 initG_gaincode_rev6_elna = 0x127e; | 16423 | u16 initG_gaincode_rev6_elna = 0x127e; |
16424 | uint16 initA_gaincode = 0x52de; | 16424 | u16 initA_gaincode = 0x52de; |
16425 | uint16 initA_gaincode_rev4 = 0x629e; | 16425 | u16 initA_gaincode_rev4 = 0x629e; |
16426 | uint16 initA_gaincode_rev4_elna = 0x329e; | 16426 | u16 initA_gaincode_rev4_elna = 0x329e; |
16427 | uint16 initA_gaincode_rev5 = 0x729e; | 16427 | u16 initA_gaincode_rev5 = 0x729e; |
16428 | uint16 initA_gaincode_rev6 = 0x729e; | 16428 | u16 initA_gaincode_rev6 = 0x729e; |
16429 | uint16 init_gaincode; | 16429 | u16 init_gaincode; |
16430 | uint16 clip1hiG_gaincode = 0x107e; | 16430 | u16 clip1hiG_gaincode = 0x107e; |
16431 | uint16 clip1hiG_gaincode_rev4 = 0x007e; | 16431 | u16 clip1hiG_gaincode_rev4 = 0x007e; |
16432 | uint16 clip1hiG_gaincode_rev5 = 0x1076; | 16432 | u16 clip1hiG_gaincode_rev5 = 0x1076; |
16433 | uint16 clip1hiG_gaincode_rev6 = 0x007e; | 16433 | u16 clip1hiG_gaincode_rev6 = 0x007e; |
16434 | uint16 clip1hiA_gaincode = 0x00de; | 16434 | u16 clip1hiA_gaincode = 0x00de; |
16435 | uint16 clip1hiA_gaincode_rev4 = 0x029e; | 16435 | u16 clip1hiA_gaincode_rev4 = 0x029e; |
16436 | uint16 clip1hiA_gaincode_rev5 = 0x029e; | 16436 | u16 clip1hiA_gaincode_rev5 = 0x029e; |
16437 | uint16 clip1hiA_gaincode_rev6 = 0x029e; | 16437 | u16 clip1hiA_gaincode_rev6 = 0x029e; |
16438 | uint16 clip1hi_gaincode; | 16438 | u16 clip1hi_gaincode; |
16439 | uint16 clip1mdG_gaincode = 0x0066; | 16439 | u16 clip1mdG_gaincode = 0x0066; |
16440 | uint16 clip1mdA_gaincode = 0x00ca; | 16440 | u16 clip1mdA_gaincode = 0x00ca; |
16441 | uint16 clip1mdA_gaincode_rev4 = 0x1084; | 16441 | u16 clip1mdA_gaincode_rev4 = 0x1084; |
16442 | uint16 clip1mdA_gaincode_rev5 = 0x2084; | 16442 | u16 clip1mdA_gaincode_rev5 = 0x2084; |
16443 | uint16 clip1mdA_gaincode_rev6 = 0x2084; | 16443 | u16 clip1mdA_gaincode_rev6 = 0x2084; |
16444 | uint16 clip1md_gaincode = 0; | 16444 | u16 clip1md_gaincode = 0; |
16445 | uint16 clip1loG_gaincode = 0x0074; | 16445 | u16 clip1loG_gaincode = 0x0074; |
16446 | uint16 clip1loG_gaincode_rev5[] = { | 16446 | u16 clip1loG_gaincode_rev5[] = { |
16447 | 0x0062, 0x0064, 0x006a, 0x106a, 0x106c, 0x1074, 0x107c, 0x207c | 16447 | 0x0062, 0x0064, 0x006a, 0x106a, 0x106c, 0x1074, 0x107c, 0x207c |
16448 | }; | 16448 | }; |
16449 | uint16 clip1loG_gaincode_rev6[] = { | 16449 | u16 clip1loG_gaincode_rev6[] = { |
16450 | 0x106a, 0x106c, 0x1074, 0x107c, 0x007e, 0x107e, 0x207e, 0x307e | 16450 | 0x106a, 0x106c, 0x1074, 0x107c, 0x007e, 0x107e, 0x207e, 0x307e |
16451 | }; | 16451 | }; |
16452 | uint16 clip1loG_gaincode_rev6_224B0 = 0x1074; | 16452 | u16 clip1loG_gaincode_rev6_224B0 = 0x1074; |
16453 | uint16 clip1loA_gaincode = 0x00cc; | 16453 | u16 clip1loA_gaincode = 0x00cc; |
16454 | uint16 clip1loA_gaincode_rev4 = 0x0086; | 16454 | u16 clip1loA_gaincode_rev4 = 0x0086; |
16455 | uint16 clip1loA_gaincode_rev5 = 0x2086; | 16455 | u16 clip1loA_gaincode_rev5 = 0x2086; |
16456 | uint16 clip1loA_gaincode_rev6 = 0x2086; | 16456 | u16 clip1loA_gaincode_rev6 = 0x2086; |
16457 | uint16 clip1lo_gaincode; | 16457 | u16 clip1lo_gaincode; |
16458 | u8 crsminG_th = 0x18; | 16458 | u8 crsminG_th = 0x18; |
16459 | u8 crsminG_th_rev5 = 0x18; | 16459 | u8 crsminG_th_rev5 = 0x18; |
16460 | u8 crsminG_th_rev6 = 0x18; | 16460 | u8 crsminG_th_rev6 = 0x18; |
@@ -16480,15 +16480,15 @@ static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi) | |||
16480 | u8 crsminuA_th_rev6 = 0x24; | 16480 | u8 crsminuA_th_rev6 = 0x24; |
16481 | u8 crsminuA_th_rev6_224B0 = 0x2d; | 16481 | u8 crsminuA_th_rev6_224B0 = 0x2d; |
16482 | u8 crsminu_th; | 16482 | u8 crsminu_th; |
16483 | uint16 nbclipG_th = 0x20d; | 16483 | u16 nbclipG_th = 0x20d; |
16484 | uint16 nbclipG_th_rev4 = 0x1a1; | 16484 | u16 nbclipG_th_rev4 = 0x1a1; |
16485 | uint16 nbclipG_th_rev5 = 0x1d0; | 16485 | u16 nbclipG_th_rev5 = 0x1d0; |
16486 | uint16 nbclipG_th_rev6 = 0x1d0; | 16486 | u16 nbclipG_th_rev6 = 0x1d0; |
16487 | uint16 nbclipA_th = 0x1a1; | 16487 | u16 nbclipA_th = 0x1a1; |
16488 | uint16 nbclipA_th_rev4 = 0x107; | 16488 | u16 nbclipA_th_rev4 = 0x107; |
16489 | uint16 nbclipA_th_rev5 = 0x0a9; | 16489 | u16 nbclipA_th_rev5 = 0x0a9; |
16490 | uint16 nbclipA_th_rev6 = 0x0f0; | 16490 | u16 nbclipA_th_rev6 = 0x0f0; |
16491 | uint16 nbclip_th = 0; | 16491 | u16 nbclip_th = 0; |
16492 | u8 w1clipG_th = 5; | 16492 | u8 w1clipG_th = 5; |
16493 | u8 w1clipG_th_rev5 = 9; | 16493 | u8 w1clipG_th_rev5 = 9; |
16494 | u8 w1clipG_th_rev6 = 5; | 16494 | u8 w1clipG_th_rev6 = 5; |
@@ -16498,7 +16498,7 @@ static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi) | |||
16498 | u8 rssiA_gain_rev5 = 0x90; | 16498 | u8 rssiA_gain_rev5 = 0x90; |
16499 | u8 rssiA_gain_rev6 = 0x90; | 16499 | u8 rssiA_gain_rev6 = 0x90; |
16500 | u8 rssi_gain; | 16500 | u8 rssi_gain; |
16501 | uint16 regval[21]; | 16501 | u16 regval[21]; |
16502 | u8 triso; | 16502 | u8 triso; |
16503 | 16503 | ||
16504 | triso = (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.triso : | 16504 | triso = (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.triso : |
@@ -16945,7 +16945,7 @@ static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi) | |||
16945 | wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval); | 16945 | wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval); |
16946 | 16946 | ||
16947 | for (ctr = 0; ctr < 21; ctr++) { | 16947 | for (ctr = 0; ctr < 21; ctr++) { |
16948 | regval[ctr] = (uint16) ctr; | 16948 | regval[ctr] = (u16) ctr; |
16949 | } | 16949 | } |
16950 | wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval); | 16950 | wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval); |
16951 | wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval); | 16951 | wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval); |
@@ -17023,7 +17023,7 @@ static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(phy_info_t *pi) | |||
17023 | 17023 | ||
17024 | static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi) | 17024 | static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi) |
17025 | { | 17025 | { |
17026 | uint16 currband; | 17026 | u16 currband; |
17027 | s8 lna1G_gain_db_rev7[] = { 9, 14, 19, 24 }; | 17027 | s8 lna1G_gain_db_rev7[] = { 9, 14, 19, 24 }; |
17028 | s8 *lna1_gain_db = NULL; | 17028 | s8 *lna1_gain_db = NULL; |
17029 | s8 *lna1_gain_db_2 = NULL; | 17029 | s8 *lna1_gain_db_2 = NULL; |
@@ -17032,19 +17032,19 @@ static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi) | |||
17032 | s8 *tia_gain_db; | 17032 | s8 *tia_gain_db; |
17033 | s8 tiaA_gainbits_rev7[] = { 0, 1, 2, 3, 4, 4, 4, 4, 4, 4 }; | 17033 | s8 tiaA_gainbits_rev7[] = { 0, 1, 2, 3, 4, 4, 4, 4, 4, 4 }; |
17034 | s8 *tia_gainbits; | 17034 | s8 *tia_gainbits; |
17035 | uint16 rfseqA_init_gain_rev7[] = { 0x624f, 0x624f }; | 17035 | u16 rfseqA_init_gain_rev7[] = { 0x624f, 0x624f }; |
17036 | uint16 *rfseq_init_gain; | 17036 | u16 *rfseq_init_gain; |
17037 | uint16 init_gaincode; | 17037 | u16 init_gaincode; |
17038 | uint16 clip1hi_gaincode; | 17038 | u16 clip1hi_gaincode; |
17039 | uint16 clip1md_gaincode = 0; | 17039 | u16 clip1md_gaincode = 0; |
17040 | uint16 clip1md_gaincode_B; | 17040 | u16 clip1md_gaincode_B; |
17041 | uint16 clip1lo_gaincode; | 17041 | u16 clip1lo_gaincode; |
17042 | uint16 clip1lo_gaincode_B; | 17042 | u16 clip1lo_gaincode_B; |
17043 | u8 crsminl_th = 0; | 17043 | u8 crsminl_th = 0; |
17044 | u8 crsminu_th; | 17044 | u8 crsminu_th; |
17045 | uint16 nbclip_th = 0; | 17045 | u16 nbclip_th = 0; |
17046 | u8 w1clip_th; | 17046 | u8 w1clip_th; |
17047 | uint16 freq; | 17047 | u16 freq; |
17048 | s8 nvar_baseline_offset0 = 0, nvar_baseline_offset1 = 0; | 17048 | s8 nvar_baseline_offset0 = 0, nvar_baseline_offset1 = 0; |
17049 | u8 chg_nbclip_th = 0; | 17049 | u8 chg_nbclip_th = 0; |
17050 | 17050 | ||
@@ -17233,8 +17233,8 @@ static void wlc_phy_adjust_lnagaintbl_nphy(phy_info_t *pi) | |||
17233 | int ctr; | 17233 | int ctr; |
17234 | int16 gain_delta[2]; | 17234 | int16 gain_delta[2]; |
17235 | u8 curr_channel; | 17235 | u8 curr_channel; |
17236 | uint16 minmax_gain[2]; | 17236 | u16 minmax_gain[2]; |
17237 | uint16 regval[4]; | 17237 | u16 regval[4]; |
17238 | 17238 | ||
17239 | if (pi->phyhang_avoid) | 17239 | if (pi->phyhang_avoid) |
17240 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); | 17240 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); |
@@ -17280,7 +17280,7 @@ static void wlc_phy_adjust_lnagaintbl_nphy(phy_info_t *pi) | |||
17280 | wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval); | 17280 | wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval); |
17281 | 17281 | ||
17282 | minmax_gain[core] = | 17282 | minmax_gain[core] = |
17283 | (uint16) (nphy_def_lnagains[2] + gain_delta[core] + 4); | 17283 | (u16) (nphy_def_lnagains[2] + gain_delta[core] + 4); |
17284 | } | 17284 | } |
17285 | 17285 | ||
17286 | mod_phy_reg(pi, 0x1e, (0xff << 0), (minmax_gain[0] << 0)); | 17286 | mod_phy_reg(pi, 0x1e, (0xff << 0), (minmax_gain[0] << 0)); |
@@ -17514,15 +17514,15 @@ static void wlc_phy_radio_init_2056(phy_info_t *pi) | |||
17514 | } | 17514 | } |
17515 | } | 17515 | } |
17516 | 17516 | ||
17517 | wlc_phy_init_radio_regs(pi, regs_SYN_2056_ptr, (uint16) RADIO_2056_SYN); | 17517 | wlc_phy_init_radio_regs(pi, regs_SYN_2056_ptr, (u16) RADIO_2056_SYN); |
17518 | 17518 | ||
17519 | wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (uint16) RADIO_2056_TX0); | 17519 | wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX0); |
17520 | 17520 | ||
17521 | wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (uint16) RADIO_2056_TX1); | 17521 | wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX1); |
17522 | 17522 | ||
17523 | wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (uint16) RADIO_2056_RX0); | 17523 | wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX0); |
17524 | 17524 | ||
17525 | wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (uint16) RADIO_2056_RX1); | 17525 | wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX1); |
17526 | } | 17526 | } |
17527 | 17527 | ||
17528 | static void wlc_phy_radio_postinit_2056(phy_info_t *pi) | 17528 | static void wlc_phy_radio_postinit_2056(phy_info_t *pi) |
@@ -17994,11 +17994,11 @@ wlc_phy_chanspec_radio2056_setup(phy_info_t *pi, | |||
17994 | if (CHSPEC_IS2G(pi->radio_chanspec)) { | 17994 | if (CHSPEC_IS2G(pi->radio_chanspec)) { |
17995 | write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | | 17995 | write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | |
17996 | RADIO_2056_SYN, | 17996 | RADIO_2056_SYN, |
17997 | (uint16) regs_SYN_2056_ptr[0x49 - 2].init_g); | 17997 | (u16) regs_SYN_2056_ptr[0x49 - 2].init_g); |
17998 | } else { | 17998 | } else { |
17999 | write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | | 17999 | write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | |
18000 | RADIO_2056_SYN, | 18000 | RADIO_2056_SYN, |
18001 | (uint16) regs_SYN_2056_ptr[0x49 - 2].init_a); | 18001 | (u16) regs_SYN_2056_ptr[0x49 - 2].init_a); |
18002 | } | 18002 | } |
18003 | 18003 | ||
18004 | if (pi->sh->boardflags2 & BFL2_GPLL_WAR) { | 18004 | if (pi->sh->boardflags2 & BFL2_GPLL_WAR) { |
@@ -18057,11 +18057,11 @@ wlc_phy_chanspec_radio2056_setup(phy_info_t *pi, | |||
18057 | } | 18057 | } |
18058 | 18058 | ||
18059 | if (PHY_IPA(pi) && CHSPEC_IS2G(pi->radio_chanspec)) { | 18059 | if (PHY_IPA(pi) && CHSPEC_IS2G(pi->radio_chanspec)) { |
18060 | uint16 pag_boost_tune; | 18060 | u16 pag_boost_tune; |
18061 | uint16 padg_boost_tune; | 18061 | u16 padg_boost_tune; |
18062 | uint16 pgag_boost_tune; | 18062 | u16 pgag_boost_tune; |
18063 | uint16 mixg_boost_tune; | 18063 | u16 mixg_boost_tune; |
18064 | uint16 bias, cascbias; | 18064 | u16 bias, cascbias; |
18065 | uint core; | 18065 | uint core; |
18066 | 18066 | ||
18067 | for (core = 0; core < pi->pubpi.phy_corenum; core++) { | 18067 | for (core = 0; core < pi->pubpi.phy_corenum; core++) { |
@@ -18140,11 +18140,11 @@ wlc_phy_chanspec_radio2056_setup(phy_info_t *pi, | |||
18140 | 18140 | ||
18141 | if (PHY_IPA(pi) && NREV_IS(pi->pubpi.phy_rev, 6) | 18141 | if (PHY_IPA(pi) && NREV_IS(pi->pubpi.phy_rev, 6) |
18142 | && CHSPEC_IS5G(pi->radio_chanspec)) { | 18142 | && CHSPEC_IS5G(pi->radio_chanspec)) { |
18143 | uint16 paa_boost_tune; | 18143 | u16 paa_boost_tune; |
18144 | uint16 pada_boost_tune; | 18144 | u16 pada_boost_tune; |
18145 | uint16 pgaa_boost_tune; | 18145 | u16 pgaa_boost_tune; |
18146 | uint16 mixa_boost_tune; | 18146 | u16 mixa_boost_tune; |
18147 | uint16 freq, pabias, cascbias; | 18147 | u16 freq, pabias, cascbias; |
18148 | uint core; | 18148 | uint core; |
18149 | 18149 | ||
18150 | freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec)); | 18150 | freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec)); |
@@ -18244,9 +18244,9 @@ void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi) | |||
18244 | 18244 | ||
18245 | #define MAX_205x_RCAL_WAITLOOPS 10000 | 18245 | #define MAX_205x_RCAL_WAITLOOPS 10000 |
18246 | 18246 | ||
18247 | static uint16 wlc_phy_radio205x_rcal(phy_info_t *pi) | 18247 | static u16 wlc_phy_radio205x_rcal(phy_info_t *pi) |
18248 | { | 18248 | { |
18249 | uint16 rcal_reg = 0; | 18249 | u16 rcal_reg = 0; |
18250 | int i; | 18250 | int i; |
18251 | 18251 | ||
18252 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 18252 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
@@ -18298,7 +18298,7 @@ static uint16 wlc_phy_radio205x_rcal(phy_info_t *pi) | |||
18298 | } | 18298 | } |
18299 | 18299 | ||
18300 | } else if (NREV_IS(pi->pubpi.phy_rev, 3)) { | 18300 | } else if (NREV_IS(pi->pubpi.phy_rev, 3)) { |
18301 | uint16 savereg; | 18301 | u16 savereg; |
18302 | 18302 | ||
18303 | savereg = | 18303 | savereg = |
18304 | read_radio_reg(pi, | 18304 | read_radio_reg(pi, |
@@ -18351,8 +18351,8 @@ wlc_phy_chanspec_radio2057_setup(phy_info_t *pi, | |||
18351 | const chan_info_nphy_radio2057_rev5_t *ci2) | 18351 | const chan_info_nphy_radio2057_rev5_t *ci2) |
18352 | { | 18352 | { |
18353 | int coreNum; | 18353 | int coreNum; |
18354 | uint16 txmix2g_tune_boost_pu = 0; | 18354 | u16 txmix2g_tune_boost_pu = 0; |
18355 | uint16 pad2g_tune_pus = 0; | 18355 | u16 pad2g_tune_pus = 0; |
18356 | 18356 | ||
18357 | if (pi->pubpi.radiorev == 5) { | 18357 | if (pi->pubpi.radiorev == 5) { |
18358 | 18358 | ||
@@ -18541,9 +18541,9 @@ wlc_phy_chanspec_radio2057_setup(phy_info_t *pi, | |||
18541 | wlc_phy_radio205x_vcocal_nphy(pi); | 18541 | wlc_phy_radio205x_vcocal_nphy(pi); |
18542 | } | 18542 | } |
18543 | 18543 | ||
18544 | static uint16 wlc_phy_radio2057_rccal(phy_info_t *pi) | 18544 | static u16 wlc_phy_radio2057_rccal(phy_info_t *pi) |
18545 | { | 18545 | { |
18546 | uint16 rccal_valid; | 18546 | u16 rccal_valid; |
18547 | int i; | 18547 | int i; |
18548 | bool chip43226_6362A0; | 18548 | bool chip43226_6362A0; |
18549 | 18549 | ||
@@ -18628,7 +18628,7 @@ static uint16 wlc_phy_radio2057_rccal(phy_info_t *pi) | |||
18628 | } | 18628 | } |
18629 | 18629 | ||
18630 | static void | 18630 | static void |
18631 | wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, uint16 reduction_factr) | 18631 | wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, u16 reduction_factr) |
18632 | { | 18632 | { |
18633 | if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) { | 18633 | if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) { |
18634 | if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) && | 18634 | if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) && |
@@ -18707,7 +18707,7 @@ wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *tone_id_buf, | |||
18707 | 18707 | ||
18708 | static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr) | 18708 | static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr) |
18709 | { | 18709 | { |
18710 | uint16 regval; | 18710 | u16 regval; |
18711 | 18711 | ||
18712 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 18712 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
18713 | if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) && | 18713 | if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) && |
@@ -18716,19 +18716,19 @@ static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr) | |||
18716 | regval = read_phy_reg(pi, 0x27d); | 18716 | regval = read_phy_reg(pi, 0x27d); |
18717 | pi->nphy_crsminpwr[0] = regval & 0xff; | 18717 | pi->nphy_crsminpwr[0] = regval & 0xff; |
18718 | regval &= 0xff00; | 18718 | regval &= 0xff00; |
18719 | regval |= (uint16) minpwr; | 18719 | regval |= (u16) minpwr; |
18720 | write_phy_reg(pi, 0x27d, regval); | 18720 | write_phy_reg(pi, 0x27d, regval); |
18721 | 18721 | ||
18722 | regval = read_phy_reg(pi, 0x280); | 18722 | regval = read_phy_reg(pi, 0x280); |
18723 | pi->nphy_crsminpwr[1] = regval & 0xff; | 18723 | pi->nphy_crsminpwr[1] = regval & 0xff; |
18724 | regval &= 0xff00; | 18724 | regval &= 0xff00; |
18725 | regval |= (uint16) minpwr; | 18725 | regval |= (u16) minpwr; |
18726 | write_phy_reg(pi, 0x280, regval); | 18726 | write_phy_reg(pi, 0x280, regval); |
18727 | 18727 | ||
18728 | regval = read_phy_reg(pi, 0x283); | 18728 | regval = read_phy_reg(pi, 0x283); |
18729 | pi->nphy_crsminpwr[2] = regval & 0xff; | 18729 | pi->nphy_crsminpwr[2] = regval & 0xff; |
18730 | regval &= 0xff00; | 18730 | regval &= 0xff00; |
18731 | regval |= (uint16) minpwr; | 18731 | regval |= (u16) minpwr; |
18732 | write_phy_reg(pi, 0x283, regval); | 18732 | write_phy_reg(pi, 0x283, regval); |
18733 | 18733 | ||
18734 | pi->nphy_crsminpwr_adjusted = TRUE; | 18734 | pi->nphy_crsminpwr_adjusted = TRUE; |
@@ -18797,7 +18797,7 @@ static void wlc_phy_txlpfbw_nphy(phy_info_t *pi) | |||
18797 | 18797 | ||
18798 | static void wlc_phy_spurwar_nphy(phy_info_t *pi) | 18798 | static void wlc_phy_spurwar_nphy(phy_info_t *pi) |
18799 | { | 18799 | { |
18800 | uint16 cur_channel = 0; | 18800 | u16 cur_channel = 0; |
18801 | int nphy_adj_tone_id_buf[] = { 57, 58 }; | 18801 | int nphy_adj_tone_id_buf[] = { 57, 58 }; |
18802 | uint32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff }; | 18802 | uint32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff }; |
18803 | bool isAdjustNoiseVar = FALSE; | 18803 | bool isAdjustNoiseVar = FALSE; |
@@ -18976,7 +18976,7 @@ static void | |||
18976 | wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec, | 18976 | wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec, |
18977 | const nphy_sfo_cfg_t *ci) | 18977 | const nphy_sfo_cfg_t *ci) |
18978 | { | 18978 | { |
18979 | uint16 val; | 18979 | u16 val; |
18980 | 18980 | ||
18981 | val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand; | 18981 | val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand; |
18982 | if (CHSPEC_IS5G(chanspec) && !val) { | 18982 | if (CHSPEC_IS5G(chanspec) && !val) { |
@@ -19000,7 +19000,7 @@ wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec, | |||
19000 | (val | MAC_PHY_FORCE_CLK)); | 19000 | (val | MAC_PHY_FORCE_CLK)); |
19001 | 19001 | ||
19002 | and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG), | 19002 | and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG), |
19003 | (uint16) (~(BBCFG_RESETCCA | BBCFG_RESETRX))); | 19003 | (u16) (~(BBCFG_RESETCCA | BBCFG_RESETRX))); |
19004 | 19004 | ||
19005 | W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, val); | 19005 | W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, val); |
19006 | } | 19006 | } |
@@ -19216,7 +19216,7 @@ static void wlc_phy_savecal_nphy(phy_info_t *pi) | |||
19216 | { | 19216 | { |
19217 | void *tbl_ptr; | 19217 | void *tbl_ptr; |
19218 | int coreNum; | 19218 | int coreNum; |
19219 | uint16 *txcal_radio_regs = NULL; | 19219 | u16 *txcal_radio_regs = NULL; |
19220 | 19220 | ||
19221 | if (pi->phyhang_avoid) | 19221 | if (pi->phyhang_avoid) |
19222 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); | 19222 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); |
@@ -19363,11 +19363,11 @@ static void wlc_phy_savecal_nphy(phy_info_t *pi) | |||
19363 | 19363 | ||
19364 | static void wlc_phy_restorecal_nphy(phy_info_t *pi) | 19364 | static void wlc_phy_restorecal_nphy(phy_info_t *pi) |
19365 | { | 19365 | { |
19366 | uint16 *loft_comp; | 19366 | u16 *loft_comp; |
19367 | uint16 txcal_coeffs_bphy[4]; | 19367 | u16 txcal_coeffs_bphy[4]; |
19368 | uint16 *tbl_ptr; | 19368 | u16 *tbl_ptr; |
19369 | int coreNum; | 19369 | int coreNum; |
19370 | uint16 *txcal_radio_regs = NULL; | 19370 | u16 *txcal_radio_regs = NULL; |
19371 | 19371 | ||
19372 | if (CHSPEC_IS2G(pi->radio_chanspec)) { | 19372 | if (CHSPEC_IS2G(pi->radio_chanspec)) { |
19373 | if (pi->nphy_iqcal_chanspec_2G == 0) | 19373 | if (pi->nphy_iqcal_chanspec_2G == 0) |
@@ -19563,14 +19563,14 @@ static void wlc_phy_restorecal_nphy(phy_info_t *pi) | |||
19563 | void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init) | 19563 | void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init) |
19564 | { | 19564 | { |
19565 | phy_info_t *pi = (phy_info_t *) ppi; | 19565 | phy_info_t *pi = (phy_info_t *) ppi; |
19566 | uint16 mask = 0xfc00; | 19566 | u16 mask = 0xfc00; |
19567 | uint32 mc = 0; | 19567 | uint32 mc = 0; |
19568 | 19568 | ||
19569 | if (NREV_GE(pi->pubpi.phy_rev, 7)) | 19569 | if (NREV_GE(pi->pubpi.phy_rev, 7)) |
19570 | return; | 19570 | return; |
19571 | 19571 | ||
19572 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 19572 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
19573 | uint16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188; | 19573 | u16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188; |
19574 | 19574 | ||
19575 | if (lut_init == FALSE) | 19575 | if (lut_init == FALSE) |
19576 | return; | 19576 | return; |
@@ -19624,9 +19624,9 @@ void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init) | |||
19624 | } | 19624 | } |
19625 | } | 19625 | } |
19626 | 19626 | ||
19627 | uint16 wlc_phy_classifier_nphy(phy_info_t *pi, uint16 mask, uint16 val) | 19627 | u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val) |
19628 | { | 19628 | { |
19629 | uint16 curr_ctl, new_ctl; | 19629 | u16 curr_ctl, new_ctl; |
19630 | bool suspended = FALSE; | 19630 | bool suspended = FALSE; |
19631 | 19631 | ||
19632 | if (D11REV_IS(pi->sh->corerev, 16)) { | 19632 | if (D11REV_IS(pi->sh->corerev, 16)) { |
@@ -19649,7 +19649,7 @@ uint16 wlc_phy_classifier_nphy(phy_info_t *pi, uint16 mask, uint16 val) | |||
19649 | return new_ctl; | 19649 | return new_ctl; |
19650 | } | 19650 | } |
19651 | 19651 | ||
19652 | static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, uint16 *vals) | 19652 | static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, u16 *vals) |
19653 | { | 19653 | { |
19654 | 19654 | ||
19655 | if (write == 0) { | 19655 | if (write == 0) { |
@@ -19663,8 +19663,8 @@ static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, uint16 *vals) | |||
19663 | 19663 | ||
19664 | void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd) | 19664 | void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd) |
19665 | { | 19665 | { |
19666 | uint16 trigger_mask, status_mask; | 19666 | u16 trigger_mask, status_mask; |
19667 | uint16 orig_RfseqCoreActv; | 19667 | u16 orig_RfseqCoreActv; |
19668 | 19668 | ||
19669 | switch (cmd) { | 19669 | switch (cmd) { |
19670 | case NPHY_RFSEQ_RX2TX: | 19670 | case NPHY_RFSEQ_RX2TX: |
@@ -19740,10 +19740,10 @@ wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *events, u8 *dlys, | |||
19740 | wlc_phy_stay_in_carriersearch_nphy(pi, FALSE); | 19740 | wlc_phy_stay_in_carriersearch_nphy(pi, FALSE); |
19741 | } | 19741 | } |
19742 | 19742 | ||
19743 | static uint16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, uint16 offset) | 19743 | static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset) |
19744 | { | 19744 | { |
19745 | uint16 lpf_bw_ctl_val = 0; | 19745 | u16 lpf_bw_ctl_val = 0; |
19746 | uint16 rx2tx_lpf_rc_lut_offset = 0; | 19746 | u16 rx2tx_lpf_rc_lut_offset = 0; |
19747 | 19747 | ||
19748 | if (offset == 0) { | 19748 | if (offset == 0) { |
19749 | if (CHSPEC_IS40(pi->radio_chanspec)) { | 19749 | if (CHSPEC_IS40(pi->radio_chanspec)) { |
@@ -19764,11 +19764,11 @@ static uint16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, uint16 offset) | |||
19764 | } | 19764 | } |
19765 | 19765 | ||
19766 | static void | 19766 | static void |
19767 | wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, uint16 field, uint16 value, | 19767 | wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, u16 field, u16 value, |
19768 | u8 core_mask, u8 off, u8 override_id) | 19768 | u8 core_mask, u8 off, u8 override_id) |
19769 | { | 19769 | { |
19770 | u8 core_num; | 19770 | u8 core_num; |
19771 | uint16 addr = 0, en_addr = 0, val_addr = 0, en_mask = 0, val_mask = 0; | 19771 | u16 addr = 0, en_addr = 0, val_addr = 0, en_mask = 0, val_mask = 0; |
19772 | u8 val_shift = 0; | 19772 | u8 val_shift = 0; |
19773 | 19773 | ||
19774 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 19774 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
@@ -20034,11 +20034,11 @@ wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, uint16 field, uint16 value, | |||
20034 | } | 20034 | } |
20035 | 20035 | ||
20036 | static void | 20036 | static void |
20037 | wlc_phy_rfctrl_override_nphy(phy_info_t *pi, uint16 field, uint16 value, | 20037 | wlc_phy_rfctrl_override_nphy(phy_info_t *pi, u16 field, u16 value, |
20038 | u8 core_mask, u8 off) | 20038 | u8 core_mask, u8 off) |
20039 | { | 20039 | { |
20040 | u8 core_num; | 20040 | u8 core_num; |
20041 | uint16 addr = 0, mask = 0, en_addr = 0, val_addr = 0, en_mask = | 20041 | u16 addr = 0, mask = 0, en_addr = 0, val_addr = 0, en_mask = |
20042 | 0, val_mask = 0; | 20042 | 0, val_mask = 0; |
20043 | u8 shift = 0, val_shift = 0; | 20043 | u8 shift = 0, val_shift = 0; |
20044 | 20044 | ||
@@ -20280,11 +20280,11 @@ wlc_phy_rfctrl_override_nphy(phy_info_t *pi, uint16 field, uint16 value, | |||
20280 | } | 20280 | } |
20281 | 20281 | ||
20282 | static void | 20282 | static void |
20283 | wlc_phy_rfctrl_override_1tomany_nphy(phy_info_t *pi, uint16 cmd, uint16 value, | 20283 | wlc_phy_rfctrl_override_1tomany_nphy(phy_info_t *pi, u16 cmd, u16 value, |
20284 | u8 core_mask, u8 off) | 20284 | u8 core_mask, u8 off) |
20285 | { | 20285 | { |
20286 | uint16 rfmxgain = 0, lpfgain = 0; | 20286 | u16 rfmxgain = 0, lpfgain = 0; |
20287 | uint16 tgain = 0; | 20287 | u16 tgain = 0; |
20288 | 20288 | ||
20289 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 20289 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
20290 | 20290 | ||
@@ -20366,10 +20366,10 @@ wlc_phy_rfctrl_override_1tomany_nphy(phy_info_t *pi, uint16 cmd, uint16 value, | |||
20366 | } | 20366 | } |
20367 | 20367 | ||
20368 | static void | 20368 | static void |
20369 | wlc_phy_scale_offset_rssi_nphy(phy_info_t *pi, uint16 scale, s8 offset, | 20369 | wlc_phy_scale_offset_rssi_nphy(phy_info_t *pi, u16 scale, s8 offset, |
20370 | u8 coresel, u8 rail, u8 rssi_type) | 20370 | u8 coresel, u8 rail, u8 rssi_type) |
20371 | { | 20371 | { |
20372 | uint16 valuetostuff; | 20372 | u16 valuetostuff; |
20373 | 20373 | ||
20374 | offset = (offset > NPHY_RSSICAL_MAXREAD) ? | 20374 | offset = (offset > NPHY_RSSICAL_MAXREAD) ? |
20375 | NPHY_RSSICAL_MAXREAD : offset; | 20375 | NPHY_RSSICAL_MAXREAD : offset; |
@@ -20508,13 +20508,13 @@ wlc_phy_scale_offset_rssi_nphy(phy_info_t *pi, uint16 scale, s8 offset, | |||
20508 | 20508 | ||
20509 | void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core_code, u8 rssi_type) | 20509 | void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core_code, u8 rssi_type) |
20510 | { | 20510 | { |
20511 | uint16 mask, val; | 20511 | u16 mask, val; |
20512 | uint16 afectrlovr_rssi_val, rfctrlcmd_rxen_val, rfctrlcmd_coresel_val, | 20512 | u16 afectrlovr_rssi_val, rfctrlcmd_rxen_val, rfctrlcmd_coresel_val, |
20513 | startseq; | 20513 | startseq; |
20514 | uint16 rfctrlovr_rssi_val, rfctrlovr_rxen_val, rfctrlovr_coresel_val, | 20514 | u16 rfctrlovr_rssi_val, rfctrlovr_rxen_val, rfctrlovr_coresel_val, |
20515 | rfctrlovr_trigger_val; | 20515 | rfctrlovr_trigger_val; |
20516 | uint16 afectrlovr_rssi_mask, rfctrlcmd_mask, rfctrlovr_mask; | 20516 | u16 afectrlovr_rssi_mask, rfctrlcmd_mask, rfctrlovr_mask; |
20517 | uint16 rfctrlcmd_val, rfctrlovr_val; | 20517 | u16 rfctrlcmd_val, rfctrlovr_val; |
20518 | u8 core; | 20518 | u8 core; |
20519 | 20519 | ||
20520 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 20520 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
@@ -20814,22 +20814,22 @@ wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type, int32 *rssi_buf, | |||
20814 | u8 nsamps) | 20814 | u8 nsamps) |
20815 | { | 20815 | { |
20816 | int16 rssi0, rssi1; | 20816 | int16 rssi0, rssi1; |
20817 | uint16 afectrlCore1_save = 0; | 20817 | u16 afectrlCore1_save = 0; |
20818 | uint16 afectrlCore2_save = 0; | 20818 | u16 afectrlCore2_save = 0; |
20819 | uint16 afectrlOverride1_save = 0; | 20819 | u16 afectrlOverride1_save = 0; |
20820 | uint16 afectrlOverride2_save = 0; | 20820 | u16 afectrlOverride2_save = 0; |
20821 | uint16 rfctrlOverrideAux0_save = 0; | 20821 | u16 rfctrlOverrideAux0_save = 0; |
20822 | uint16 rfctrlOverrideAux1_save = 0; | 20822 | u16 rfctrlOverrideAux1_save = 0; |
20823 | uint16 rfctrlMiscReg1_save = 0; | 20823 | u16 rfctrlMiscReg1_save = 0; |
20824 | uint16 rfctrlMiscReg2_save = 0; | 20824 | u16 rfctrlMiscReg2_save = 0; |
20825 | uint16 rfctrlcmd_save = 0; | 20825 | u16 rfctrlcmd_save = 0; |
20826 | uint16 rfctrloverride_save = 0; | 20826 | u16 rfctrloverride_save = 0; |
20827 | uint16 rfctrlrssiothers1_save = 0; | 20827 | u16 rfctrlrssiothers1_save = 0; |
20828 | uint16 rfctrlrssiothers2_save = 0; | 20828 | u16 rfctrlrssiothers2_save = 0; |
20829 | s8 tmp_buf[4]; | 20829 | s8 tmp_buf[4]; |
20830 | u8 ctr = 0, samp = 0; | 20830 | u8 ctr = 0, samp = 0; |
20831 | int32 rssi_out_val; | 20831 | int32 rssi_out_val; |
20832 | uint16 gpiosel_orig; | 20832 | u16 gpiosel_orig; |
20833 | 20833 | ||
20834 | afectrlCore1_save = read_phy_reg(pi, 0xa6); | 20834 | afectrlCore1_save = read_phy_reg(pi, 0xa6); |
20835 | afectrlCore2_save = read_phy_reg(pi, 0xa7); | 20835 | afectrlCore2_save = read_phy_reg(pi, 0xa7); |
@@ -20911,30 +20911,30 @@ wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type, int32 *rssi_buf, | |||
20911 | 20911 | ||
20912 | int16 wlc_phy_tempsense_nphy(phy_info_t *pi) | 20912 | int16 wlc_phy_tempsense_nphy(phy_info_t *pi) |
20913 | { | 20913 | { |
20914 | uint16 core1_txrf_iqcal1_save, core1_txrf_iqcal2_save; | 20914 | u16 core1_txrf_iqcal1_save, core1_txrf_iqcal2_save; |
20915 | uint16 core2_txrf_iqcal1_save, core2_txrf_iqcal2_save; | 20915 | u16 core2_txrf_iqcal1_save, core2_txrf_iqcal2_save; |
20916 | uint16 pwrdet_rxtx_core1_save; | 20916 | u16 pwrdet_rxtx_core1_save; |
20917 | uint16 pwrdet_rxtx_core2_save; | 20917 | u16 pwrdet_rxtx_core2_save; |
20918 | uint16 afectrlCore1_save; | 20918 | u16 afectrlCore1_save; |
20919 | uint16 afectrlCore2_save; | 20919 | u16 afectrlCore2_save; |
20920 | uint16 afectrlOverride_save; | 20920 | u16 afectrlOverride_save; |
20921 | uint16 afectrlOverride2_save; | 20921 | u16 afectrlOverride2_save; |
20922 | uint16 pd_pll_ts_save; | 20922 | u16 pd_pll_ts_save; |
20923 | uint16 gpioSel_save; | 20923 | u16 gpioSel_save; |
20924 | int32 radio_temp[4]; | 20924 | int32 radio_temp[4]; |
20925 | int32 radio_temp2[4]; | 20925 | int32 radio_temp2[4]; |
20926 | uint16 syn_tempprocsense_save; | 20926 | u16 syn_tempprocsense_save; |
20927 | int16 offset = 0; | 20927 | int16 offset = 0; |
20928 | 20928 | ||
20929 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 20929 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
20930 | uint16 auxADC_Vmid, auxADC_Av, auxADC_Vmid_save, auxADC_Av_save; | 20930 | u16 auxADC_Vmid, auxADC_Av, auxADC_Vmid_save, auxADC_Av_save; |
20931 | uint16 auxADC_rssi_ctrlL_save, auxADC_rssi_ctrlH_save; | 20931 | u16 auxADC_rssi_ctrlL_save, auxADC_rssi_ctrlH_save; |
20932 | uint16 auxADC_rssi_ctrlL, auxADC_rssi_ctrlH; | 20932 | u16 auxADC_rssi_ctrlL, auxADC_rssi_ctrlH; |
20933 | int32 auxADC_Vl; | 20933 | int32 auxADC_Vl; |
20934 | uint16 RfctrlOverride5_save, RfctrlOverride6_save; | 20934 | u16 RfctrlOverride5_save, RfctrlOverride6_save; |
20935 | uint16 RfctrlMiscReg5_save, RfctrlMiscReg6_save; | 20935 | u16 RfctrlMiscReg5_save, RfctrlMiscReg6_save; |
20936 | uint16 RSSIMultCoef0QPowerDet_save; | 20936 | u16 RSSIMultCoef0QPowerDet_save; |
20937 | uint16 tempsense_Rcal; | 20937 | u16 tempsense_Rcal; |
20938 | 20938 | ||
20939 | syn_tempprocsense_save = | 20939 | syn_tempprocsense_save = |
20940 | read_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG); | 20940 | read_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG); |
@@ -21262,13 +21262,13 @@ void wlc_phy_rssi_cal_nphy(phy_info_t *pi) | |||
21262 | static void wlc_phy_rssi_cal_nphy_rev2(phy_info_t *pi, u8 rssi_type) | 21262 | static void wlc_phy_rssi_cal_nphy_rev2(phy_info_t *pi, u8 rssi_type) |
21263 | { | 21263 | { |
21264 | int32 target_code; | 21264 | int32 target_code; |
21265 | uint16 classif_state; | 21265 | u16 classif_state; |
21266 | uint16 clip_state[2]; | 21266 | u16 clip_state[2]; |
21267 | uint16 rssi_ctrl_state[2], pd_state[2]; | 21267 | u16 rssi_ctrl_state[2], pd_state[2]; |
21268 | uint16 rfctrlintc_state[2], rfpdcorerxtx_state[2]; | 21268 | u16 rfctrlintc_state[2], rfpdcorerxtx_state[2]; |
21269 | uint16 rfctrlintc_override_val; | 21269 | u16 rfctrlintc_override_val; |
21270 | uint16 clip_off[] = { 0xffff, 0xffff }; | 21270 | u16 clip_off[] = { 0xffff, 0xffff }; |
21271 | uint16 rf_pd_val, pd_mask, rssi_ctrl_mask; | 21271 | u16 rf_pd_val, pd_mask, rssi_ctrl_mask; |
21272 | u8 vcm, min_vcm, vcm_tmp[4]; | 21272 | u8 vcm, min_vcm, vcm_tmp[4]; |
21273 | u8 vcm_final[4] = { 0, 0, 0, 0 }; | 21273 | u8 vcm_final[4] = { 0, 0, 0, 0 }; |
21274 | u8 result_idx, ctr; | 21274 | u8 result_idx, ctr; |
@@ -21509,11 +21509,11 @@ wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh) | |||
21509 | } | 21509 | } |
21510 | 21510 | ||
21511 | static void | 21511 | static void |
21512 | wlc_phy_rfctrlintc_override_nphy(phy_info_t *pi, u8 field, uint16 value, | 21512 | wlc_phy_rfctrlintc_override_nphy(phy_info_t *pi, u8 field, u16 value, |
21513 | u8 core_code) | 21513 | u8 core_code) |
21514 | { | 21514 | { |
21515 | uint16 mask; | 21515 | u16 mask; |
21516 | uint16 val; | 21516 | u16 val; |
21517 | u8 core; | 21517 | u8 core; |
21518 | 21518 | ||
21519 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 21519 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
@@ -21557,7 +21557,7 @@ wlc_phy_rfctrlintc_override_nphy(phy_info_t *pi, u8 field, uint16 value, | |||
21557 | PHY_CORE_0) ? 0x91 : 0x92, | 21557 | PHY_CORE_0) ? 0x91 : 0x92, |
21558 | (0x1 << 10)); | 21558 | (0x1 << 10)); |
21559 | 21559 | ||
21560 | and_phy_reg(pi, 0x2ff, (uint16) | 21560 | and_phy_reg(pi, 0x2ff, (u16) |
21561 | ~(0x3 << 14)); | 21561 | ~(0x3 << 14)); |
21562 | or_phy_reg(pi, 0x2ff, (0x1 << 13)); | 21562 | or_phy_reg(pi, 0x2ff, (0x1 << 13)); |
21563 | or_phy_reg(pi, 0x2ff, (0x1 << 0)); | 21563 | or_phy_reg(pi, 0x2ff, (0x1 << 0)); |
@@ -21745,9 +21745,9 @@ wlc_phy_rfctrlintc_override_nphy(phy_info_t *pi, u8 field, uint16 value, | |||
21745 | 21745 | ||
21746 | static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi) | 21746 | static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi) |
21747 | { | 21747 | { |
21748 | uint16 classif_state; | 21748 | u16 classif_state; |
21749 | uint16 clip_state[2]; | 21749 | u16 clip_state[2]; |
21750 | uint16 clip_off[] = { 0xffff, 0xffff }; | 21750 | u16 clip_off[] = { 0xffff, 0xffff }; |
21751 | int32 target_code; | 21751 | int32 target_code; |
21752 | u8 vcm, min_vcm; | 21752 | u8 vcm, min_vcm; |
21753 | u8 vcm_final = 0; | 21753 | u8 vcm_final = 0; |
@@ -21771,19 +21771,19 @@ static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi) | |||
21771 | u8 core; | 21771 | u8 core; |
21772 | u8 wb_cnt; | 21772 | u8 wb_cnt; |
21773 | u8 rssi_type; | 21773 | u8 rssi_type; |
21774 | uint16 NPHY_Rfctrlintc1_save, NPHY_Rfctrlintc2_save; | 21774 | u16 NPHY_Rfctrlintc1_save, NPHY_Rfctrlintc2_save; |
21775 | uint16 NPHY_AfectrlOverride1_save, NPHY_AfectrlOverride2_save; | 21775 | u16 NPHY_AfectrlOverride1_save, NPHY_AfectrlOverride2_save; |
21776 | uint16 NPHY_AfectrlCore1_save, NPHY_AfectrlCore2_save; | 21776 | u16 NPHY_AfectrlCore1_save, NPHY_AfectrlCore2_save; |
21777 | uint16 NPHY_RfctrlOverride0_save, NPHY_RfctrlOverride1_save; | 21777 | u16 NPHY_RfctrlOverride0_save, NPHY_RfctrlOverride1_save; |
21778 | uint16 NPHY_RfctrlOverrideAux0_save, NPHY_RfctrlOverrideAux1_save; | 21778 | u16 NPHY_RfctrlOverrideAux0_save, NPHY_RfctrlOverrideAux1_save; |
21779 | uint16 NPHY_RfctrlCmd_save; | 21779 | u16 NPHY_RfctrlCmd_save; |
21780 | uint16 NPHY_RfctrlMiscReg1_save, NPHY_RfctrlMiscReg2_save; | 21780 | u16 NPHY_RfctrlMiscReg1_save, NPHY_RfctrlMiscReg2_save; |
21781 | uint16 NPHY_RfctrlRSSIOTHERS1_save, NPHY_RfctrlRSSIOTHERS2_save; | 21781 | u16 NPHY_RfctrlRSSIOTHERS1_save, NPHY_RfctrlRSSIOTHERS2_save; |
21782 | u8 rxcore_state; | 21782 | u8 rxcore_state; |
21783 | uint16 NPHY_REV7_RfctrlOverride3_save, NPHY_REV7_RfctrlOverride4_save; | 21783 | u16 NPHY_REV7_RfctrlOverride3_save, NPHY_REV7_RfctrlOverride4_save; |
21784 | uint16 NPHY_REV7_RfctrlOverride5_save, NPHY_REV7_RfctrlOverride6_save; | 21784 | u16 NPHY_REV7_RfctrlOverride5_save, NPHY_REV7_RfctrlOverride6_save; |
21785 | uint16 NPHY_REV7_RfctrlMiscReg3_save, NPHY_REV7_RfctrlMiscReg4_save; | 21785 | u16 NPHY_REV7_RfctrlMiscReg3_save, NPHY_REV7_RfctrlMiscReg4_save; |
21786 | uint16 NPHY_REV7_RfctrlMiscReg5_save, NPHY_REV7_RfctrlMiscReg6_save; | 21786 | u16 NPHY_REV7_RfctrlMiscReg5_save, NPHY_REV7_RfctrlMiscReg6_save; |
21787 | 21787 | ||
21788 | NPHY_REV7_RfctrlOverride3_save = NPHY_REV7_RfctrlOverride4_save = | 21788 | NPHY_REV7_RfctrlOverride3_save = NPHY_REV7_RfctrlOverride4_save = |
21789 | NPHY_REV7_RfctrlOverride5_save = NPHY_REV7_RfctrlOverride6_save = | 21789 | NPHY_REV7_RfctrlOverride5_save = NPHY_REV7_RfctrlOverride6_save = |
@@ -22338,12 +22338,12 @@ static void wlc_phy_restore_rssical_nphy(phy_info_t *pi) | |||
22338 | } | 22338 | } |
22339 | } | 22339 | } |
22340 | 22340 | ||
22341 | static uint16 | 22341 | static u16 |
22342 | wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, uint16 max_val, | 22342 | wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val, |
22343 | u8 dac_test_mode) | 22343 | u8 dac_test_mode) |
22344 | { | 22344 | { |
22345 | u8 phy_bw, is_phybw40; | 22345 | u8 phy_bw, is_phybw40; |
22346 | uint16 num_samps, t, spur; | 22346 | u16 num_samps, t, spur; |
22347 | fixed theta = 0, rot = 0; | 22347 | fixed theta = 0, rot = 0; |
22348 | uint32 tbl_len; | 22348 | uint32 tbl_len; |
22349 | cint32 *tone_buf = NULL; | 22349 | cint32 *tone_buf = NULL; |
@@ -22366,7 +22366,7 @@ wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, uint16 max_val, | |||
22366 | return 0; | 22366 | return 0; |
22367 | } | 22367 | } |
22368 | 22368 | ||
22369 | num_samps = (uint16) tbl_len; | 22369 | num_samps = (u16) tbl_len; |
22370 | rot = FIXED((f_kHz * 36) / phy_bw) / 100; | 22370 | rot = FIXED((f_kHz * 36) / phy_bw) / 100; |
22371 | theta = 0; | 22371 | theta = 0; |
22372 | 22372 | ||
@@ -22389,12 +22389,12 @@ wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, uint16 max_val, | |||
22389 | } | 22389 | } |
22390 | 22390 | ||
22391 | int | 22391 | int |
22392 | wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, uint16 max_val, | 22392 | wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val, |
22393 | u8 iqmode, u8 dac_test_mode, bool modify_bbmult) | 22393 | u8 iqmode, u8 dac_test_mode, bool modify_bbmult) |
22394 | { | 22394 | { |
22395 | uint16 num_samps; | 22395 | u16 num_samps; |
22396 | uint16 loops = 0xffff; | 22396 | u16 loops = 0xffff; |
22397 | uint16 wait = 0; | 22397 | u16 wait = 0; |
22398 | 22398 | ||
22399 | num_samps = | 22399 | num_samps = |
22400 | wlc_phy_gen_load_samples_nphy(pi, f_kHz, max_val, dac_test_mode); | 22400 | wlc_phy_gen_load_samples_nphy(pi, f_kHz, max_val, dac_test_mode); |
@@ -22410,9 +22410,9 @@ wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, uint16 max_val, | |||
22410 | 22410 | ||
22411 | static void | 22411 | static void |
22412 | wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf, | 22412 | wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf, |
22413 | uint16 num_samps) | 22413 | u16 num_samps) |
22414 | { | 22414 | { |
22415 | uint16 t; | 22415 | u16 t; |
22416 | uint32 *data_buf = NULL; | 22416 | uint32 *data_buf = NULL; |
22417 | 22417 | ||
22418 | data_buf = (uint32 *) MALLOC(pi->sh->osh, sizeof(uint32) * num_samps); | 22418 | data_buf = (uint32 *) MALLOC(pi->sh->osh, sizeof(uint32) * num_samps); |
@@ -22438,14 +22438,14 @@ wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf, | |||
22438 | } | 22438 | } |
22439 | 22439 | ||
22440 | static void | 22440 | static void |
22441 | wlc_phy_runsamples_nphy(phy_info_t *pi, uint16 num_samps, uint16 loops, | 22441 | wlc_phy_runsamples_nphy(phy_info_t *pi, u16 num_samps, u16 loops, |
22442 | uint16 wait, u8 iqmode, u8 dac_test_mode, | 22442 | u16 wait, u8 iqmode, u8 dac_test_mode, |
22443 | bool modify_bbmult) | 22443 | bool modify_bbmult) |
22444 | { | 22444 | { |
22445 | uint16 bb_mult; | 22445 | u16 bb_mult; |
22446 | u8 phy_bw, sample_cmd; | 22446 | u8 phy_bw, sample_cmd; |
22447 | uint16 orig_RfseqCoreActv; | 22447 | u16 orig_RfseqCoreActv; |
22448 | uint16 lpf_bw_ctl_override3, lpf_bw_ctl_override4, lpf_bw_ctl_miscreg3, | 22448 | u16 lpf_bw_ctl_override3, lpf_bw_ctl_override4, lpf_bw_ctl_miscreg3, |
22449 | lpf_bw_ctl_miscreg4; | 22449 | lpf_bw_ctl_miscreg4; |
22450 | 22450 | ||
22451 | if (pi->phyhang_avoid) | 22451 | if (pi->phyhang_avoid) |
@@ -22527,8 +22527,8 @@ wlc_phy_runsamples_nphy(phy_info_t *pi, uint16 num_samps, uint16 loops, | |||
22527 | 22527 | ||
22528 | void wlc_phy_stopplayback_nphy(phy_info_t *pi) | 22528 | void wlc_phy_stopplayback_nphy(phy_info_t *pi) |
22529 | { | 22529 | { |
22530 | uint16 playback_status; | 22530 | u16 playback_status; |
22531 | uint16 bb_mult; | 22531 | u16 bb_mult; |
22532 | 22532 | ||
22533 | if (pi->phyhang_avoid) | 22533 | if (pi->phyhang_avoid) |
22534 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); | 22534 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); |
@@ -22539,10 +22539,10 @@ void wlc_phy_stopplayback_nphy(phy_info_t *pi) | |||
22539 | } else if (playback_status & 0x2) { | 22539 | } else if (playback_status & 0x2) { |
22540 | 22540 | ||
22541 | and_phy_reg(pi, 0xc2, | 22541 | and_phy_reg(pi, 0xc2, |
22542 | (uint16) ~NPHY_iqloCalCmdGctl_IQLO_CAL_EN); | 22542 | (u16) ~NPHY_iqloCalCmdGctl_IQLO_CAL_EN); |
22543 | } | 22543 | } |
22544 | 22544 | ||
22545 | and_phy_reg(pi, 0xc3, (uint16) ~(0x1 << 2)); | 22545 | and_phy_reg(pi, 0xc3, (u16) ~(0x1 << 2)); |
22546 | 22546 | ||
22547 | if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) != 0) { | 22547 | if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) != 0) { |
22548 | 22548 | ||
@@ -22569,7 +22569,7 @@ void wlc_phy_stopplayback_nphy(phy_info_t *pi) | |||
22569 | 22569 | ||
22570 | nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi) | 22570 | nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi) |
22571 | { | 22571 | { |
22572 | uint16 base_idx[2], curr_gain[2]; | 22572 | u16 base_idx[2], curr_gain[2]; |
22573 | u8 core_no; | 22573 | u8 core_no; |
22574 | nphy_txgains_t target_gain; | 22574 | nphy_txgains_t target_gain; |
22575 | uint32 *tx_pwrctrl_tbl = NULL; | 22575 | uint32 *tx_pwrctrl_tbl = NULL; |
@@ -22725,13 +22725,13 @@ nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi) | |||
22725 | } | 22725 | } |
22726 | 22726 | ||
22727 | static void | 22727 | static void |
22728 | wlc_phy_iqcal_gainparams_nphy(phy_info_t *pi, uint16 core_no, | 22728 | wlc_phy_iqcal_gainparams_nphy(phy_info_t *pi, u16 core_no, |
22729 | nphy_txgains_t target_gain, | 22729 | nphy_txgains_t target_gain, |
22730 | nphy_iqcal_params_t *params) | 22730 | nphy_iqcal_params_t *params) |
22731 | { | 22731 | { |
22732 | u8 k; | 22732 | u8 k; |
22733 | int idx; | 22733 | int idx; |
22734 | uint16 gain_index; | 22734 | u16 gain_index; |
22735 | u8 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0); | 22735 | u8 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0); |
22736 | 22736 | ||
22737 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 22737 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
@@ -22792,7 +22792,7 @@ wlc_phy_iqcal_gainparams_nphy(phy_info_t *pi, uint16 core_no, | |||
22792 | 22792 | ||
22793 | static void wlc_phy_txcal_radio_setup_nphy(phy_info_t *pi) | 22793 | static void wlc_phy_txcal_radio_setup_nphy(phy_info_t *pi) |
22794 | { | 22794 | { |
22795 | uint16 jtag_core, core; | 22795 | u16 jtag_core, core; |
22796 | 22796 | ||
22797 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 22797 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
22798 | 22798 | ||
@@ -23102,7 +23102,7 @@ static void wlc_phy_txcal_radio_setup_nphy(phy_info_t *pi) | |||
23102 | 23102 | ||
23103 | static void wlc_phy_txcal_radio_cleanup_nphy(phy_info_t *pi) | 23103 | static void wlc_phy_txcal_radio_cleanup_nphy(phy_info_t *pi) |
23104 | { | 23104 | { |
23105 | uint16 jtag_core, core; | 23105 | u16 jtag_core, core; |
23106 | 23106 | ||
23107 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 23107 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
23108 | for (core = 0; core <= 1; core++) { | 23108 | for (core = 0; core <= 1; core++) { |
@@ -23240,7 +23240,7 @@ static void wlc_phy_txcal_radio_cleanup_nphy(phy_info_t *pi) | |||
23240 | 23240 | ||
23241 | static void wlc_phy_txcal_physetup_nphy(phy_info_t *pi) | 23241 | static void wlc_phy_txcal_physetup_nphy(phy_info_t *pi) |
23242 | { | 23242 | { |
23243 | uint16 val, mask; | 23243 | u16 val, mask; |
23244 | 23244 | ||
23245 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 23245 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
23246 | pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6); | 23246 | pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6); |
@@ -23392,7 +23392,7 @@ static void wlc_phy_txcal_physetup_nphy(phy_info_t *pi) | |||
23392 | 23392 | ||
23393 | static void wlc_phy_txcal_phycleanup_nphy(phy_info_t *pi) | 23393 | static void wlc_phy_txcal_phycleanup_nphy(phy_info_t *pi) |
23394 | { | 23394 | { |
23395 | uint16 mask; | 23395 | u16 mask; |
23396 | 23396 | ||
23397 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 23397 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
23398 | write_phy_reg(pi, 0xa6, pi->tx_rx_cal_phy_saveregs[0]); | 23398 | write_phy_reg(pi, 0xa6, pi->tx_rx_cal_phy_saveregs[0]); |
@@ -23474,7 +23474,7 @@ static void wlc_phy_txcal_phycleanup_nphy(phy_info_t *pi) | |||
23474 | void | 23474 | void |
23475 | wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, u8 num_samps) | 23475 | wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, u8 num_samps) |
23476 | { | 23476 | { |
23477 | uint16 tssi_reg; | 23477 | u16 tssi_reg; |
23478 | int32 temp, pwrindex[2]; | 23478 | int32 temp, pwrindex[2]; |
23479 | int32 idle_tssi[2]; | 23479 | int32 idle_tssi[2]; |
23480 | int32 rssi_buf[4]; | 23480 | int32 rssi_buf[4]; |
@@ -23521,7 +23521,7 @@ wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, u8 num_samps) | |||
23521 | 23521 | ||
23522 | static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi) | 23522 | static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi) |
23523 | { | 23523 | { |
23524 | uint16 txcal_gain[2]; | 23524 | u16 txcal_gain[2]; |
23525 | 23525 | ||
23526 | pi->nphy_txcal_pwr_idx[0] = pi->nphy_cal_orig_pwr_idx[0]; | 23526 | pi->nphy_txcal_pwr_idx[0] = pi->nphy_cal_orig_pwr_idx[0]; |
23527 | pi->nphy_txcal_pwr_idx[1] = pi->nphy_cal_orig_pwr_idx[0]; | 23527 | pi->nphy_txcal_pwr_idx[1] = pi->nphy_cal_orig_pwr_idx[0]; |
@@ -23635,14 +23635,14 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, bool debug) | |||
23635 | { | 23635 | { |
23636 | int gainctrl_loopidx; | 23636 | int gainctrl_loopidx; |
23637 | uint core; | 23637 | uint core; |
23638 | uint16 m0m1, curr_m0m1; | 23638 | u16 m0m1, curr_m0m1; |
23639 | int32 delta_power; | 23639 | int32 delta_power; |
23640 | int32 txpwrindex; | 23640 | int32 txpwrindex; |
23641 | int32 qdBm_power[2]; | 23641 | int32 qdBm_power[2]; |
23642 | uint16 orig_BBConfig; | 23642 | u16 orig_BBConfig; |
23643 | uint16 phy_saveregs[4]; | 23643 | u16 phy_saveregs[4]; |
23644 | uint32 freq_test; | 23644 | uint32 freq_test; |
23645 | uint16 ampl_test = 250; | 23645 | u16 ampl_test = 250; |
23646 | uint stepsize; | 23646 | uint stepsize; |
23647 | bool phyhang_avoid_state = FALSE; | 23647 | bool phyhang_avoid_state = FALSE; |
23648 | 23648 | ||
@@ -23755,8 +23755,8 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, bool debug) | |||
23755 | pi->nphy_txcal_pwr_idx[core] = (u8) txpwrindex; | 23755 | pi->nphy_txcal_pwr_idx[core] = (u8) txpwrindex; |
23756 | 23756 | ||
23757 | if (debug) { | 23757 | if (debug) { |
23758 | uint16 radio_gain; | 23758 | u16 radio_gain; |
23759 | uint16 dbg_m0m1; | 23759 | u16 dbg_m0m1; |
23760 | 23760 | ||
23761 | wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &dbg_m0m1); | 23761 | wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &dbg_m0m1); |
23762 | 23762 | ||
@@ -23798,12 +23798,12 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, bool debug) | |||
23798 | wlc_phy_stay_in_carriersearch_nphy(pi, FALSE); | 23798 | wlc_phy_stay_in_carriersearch_nphy(pi, FALSE); |
23799 | } | 23799 | } |
23800 | 23800 | ||
23801 | static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, uint16 core) | 23801 | static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core) |
23802 | { | 23802 | { |
23803 | int index; | 23803 | int index; |
23804 | uint32 bbmult_scale; | 23804 | uint32 bbmult_scale; |
23805 | uint16 bbmult; | 23805 | u16 bbmult; |
23806 | uint16 tblentry; | 23806 | u16 tblentry; |
23807 | 23807 | ||
23808 | nphy_txiqcal_ladder_t ladder_lo[] = { | 23808 | nphy_txiqcal_ladder_t ladder_lo[] = { |
23809 | {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0}, | 23809 | {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0}, |
@@ -24100,18 +24100,18 @@ int | |||
24100 | wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain, | 24100 | wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain, |
24101 | bool fullcal, bool mphase) | 24101 | bool fullcal, bool mphase) |
24102 | { | 24102 | { |
24103 | uint16 val; | 24103 | u16 val; |
24104 | uint16 tbl_buf[11]; | 24104 | u16 tbl_buf[11]; |
24105 | u8 cal_cnt; | 24105 | u8 cal_cnt; |
24106 | uint16 cal_cmd; | 24106 | u16 cal_cmd; |
24107 | u8 num_cals, max_cal_cmds; | 24107 | u8 num_cals, max_cal_cmds; |
24108 | uint16 core_no, cal_type; | 24108 | u16 core_no, cal_type; |
24109 | uint16 diq_start = 0; | 24109 | u16 diq_start = 0; |
24110 | u8 phy_bw; | 24110 | u8 phy_bw; |
24111 | uint16 max_val; | 24111 | u16 max_val; |
24112 | uint16 tone_freq; | 24112 | u16 tone_freq; |
24113 | uint16 gain_save[2]; | 24113 | u16 gain_save[2]; |
24114 | uint16 cal_gain[2]; | 24114 | u16 cal_gain[2]; |
24115 | nphy_iqcal_params_t cal_params[2]; | 24115 | nphy_iqcal_params_t cal_params[2]; |
24116 | uint32 tbl_len; | 24116 | uint32 tbl_len; |
24117 | void *tbl_ptr; | 24117 | void *tbl_ptr; |
@@ -24120,61 +24120,61 @@ wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain, | |||
24120 | int bcmerror = BCME_OK; | 24120 | int bcmerror = BCME_OK; |
24121 | bool phyhang_avoid_state = FALSE; | 24121 | bool phyhang_avoid_state = FALSE; |
24122 | 24122 | ||
24123 | uint16 tbl_tx_iqlo_cal_loft_ladder_20[] = { | 24123 | u16 tbl_tx_iqlo_cal_loft_ladder_20[] = { |
24124 | 0x0300, 0x0500, 0x0700, 0x0900, 0x0d00, 0x1100, 0x1900, 0x1901, | 24124 | 0x0300, 0x0500, 0x0700, 0x0900, 0x0d00, 0x1100, 0x1900, 0x1901, |
24125 | 0x1902, | 24125 | 0x1902, |
24126 | 0x1903, 0x1904, 0x1905, 0x1906, 0x1907, 0x2407, 0x3207, 0x4607, | 24126 | 0x1903, 0x1904, 0x1905, 0x1906, 0x1907, 0x2407, 0x3207, 0x4607, |
24127 | 0x6407 | 24127 | 0x6407 |
24128 | }; | 24128 | }; |
24129 | 24129 | ||
24130 | uint16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = { | 24130 | u16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = { |
24131 | 0x0200, 0x0300, 0x0600, 0x0900, 0x0d00, 0x1100, 0x1900, 0x2400, | 24131 | 0x0200, 0x0300, 0x0600, 0x0900, 0x0d00, 0x1100, 0x1900, 0x2400, |
24132 | 0x3200, | 24132 | 0x3200, |
24133 | 0x4600, 0x6400, 0x6401, 0x6402, 0x6403, 0x6404, 0x6405, 0x6406, | 24133 | 0x4600, 0x6400, 0x6401, 0x6402, 0x6403, 0x6404, 0x6405, 0x6406, |
24134 | 0x6407 | 24134 | 0x6407 |
24135 | }; | 24135 | }; |
24136 | 24136 | ||
24137 | uint16 tbl_tx_iqlo_cal_loft_ladder_40[] = { | 24137 | u16 tbl_tx_iqlo_cal_loft_ladder_40[] = { |
24138 | 0x0200, 0x0300, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1201, | 24138 | 0x0200, 0x0300, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1201, |
24139 | 0x1202, | 24139 | 0x1202, |
24140 | 0x1203, 0x1204, 0x1205, 0x1206, 0x1207, 0x1907, 0x2307, 0x3207, | 24140 | 0x1203, 0x1204, 0x1205, 0x1206, 0x1207, 0x1907, 0x2307, 0x3207, |
24141 | 0x4707 | 24141 | 0x4707 |
24142 | }; | 24142 | }; |
24143 | 24143 | ||
24144 | uint16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = { | 24144 | u16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = { |
24145 | 0x0100, 0x0200, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1900, | 24145 | 0x0100, 0x0200, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1900, |
24146 | 0x2300, | 24146 | 0x2300, |
24147 | 0x3200, 0x4700, 0x4701, 0x4702, 0x4703, 0x4704, 0x4705, 0x4706, | 24147 | 0x3200, 0x4700, 0x4701, 0x4702, 0x4703, 0x4704, 0x4705, 0x4706, |
24148 | 0x4707 | 24148 | 0x4707 |
24149 | }; | 24149 | }; |
24150 | 24150 | ||
24151 | uint16 tbl_tx_iqlo_cal_startcoefs[] = { | 24151 | u16 tbl_tx_iqlo_cal_startcoefs[] = { |
24152 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | 24152 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
24153 | 0x0000 | 24153 | 0x0000 |
24154 | }; | 24154 | }; |
24155 | 24155 | ||
24156 | uint16 tbl_tx_iqlo_cal_cmds_fullcal[] = { | 24156 | u16 tbl_tx_iqlo_cal_cmds_fullcal[] = { |
24157 | 0x8123, 0x8264, 0x8086, 0x8245, 0x8056, | 24157 | 0x8123, 0x8264, 0x8086, 0x8245, 0x8056, |
24158 | 0x9123, 0x9264, 0x9086, 0x9245, 0x9056 | 24158 | 0x9123, 0x9264, 0x9086, 0x9245, 0x9056 |
24159 | }; | 24159 | }; |
24160 | 24160 | ||
24161 | uint16 tbl_tx_iqlo_cal_cmds_recal[] = { | 24161 | u16 tbl_tx_iqlo_cal_cmds_recal[] = { |
24162 | 0x8101, 0x8253, 0x8053, 0x8234, 0x8034, | 24162 | 0x8101, 0x8253, 0x8053, 0x8234, 0x8034, |
24163 | 0x9101, 0x9253, 0x9053, 0x9234, 0x9034 | 24163 | 0x9101, 0x9253, 0x9053, 0x9234, 0x9034 |
24164 | }; | 24164 | }; |
24165 | 24165 | ||
24166 | uint16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[] = { | 24166 | u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[] = { |
24167 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | 24167 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
24168 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | 24168 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
24169 | 0x0000 | 24169 | 0x0000 |
24170 | }; | 24170 | }; |
24171 | 24171 | ||
24172 | uint16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = { | 24172 | u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = { |
24173 | 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234, | 24173 | 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234, |
24174 | 0x9434, 0x9334, 0x9084, 0x9267, 0x9056, 0x9234 | 24174 | 0x9434, 0x9334, 0x9084, 0x9267, 0x9056, 0x9234 |
24175 | }; | 24175 | }; |
24176 | 24176 | ||
24177 | uint16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = { | 24177 | u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = { |
24178 | 0x8423, 0x8323, 0x8073, 0x8256, 0x8045, 0x8223, | 24178 | 0x8423, 0x8323, 0x8073, 0x8256, 0x8045, 0x8223, |
24179 | 0x9423, 0x9323, 0x9073, 0x9256, 0x9045, 0x9223 | 24179 | 0x9423, 0x9323, 0x9073, 0x9256, 0x9045, 0x9223 |
24180 | }; | 24180 | }; |
@@ -24467,7 +24467,7 @@ wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain, | |||
24467 | 24467 | ||
24468 | static void wlc_phy_reapply_txcal_coeffs_nphy(phy_info_t *pi) | 24468 | static void wlc_phy_reapply_txcal_coeffs_nphy(phy_info_t *pi) |
24469 | { | 24469 | { |
24470 | uint16 tbl_buf[7]; | 24470 | u16 tbl_buf[7]; |
24471 | 24471 | ||
24472 | ASSERT(NREV_LT(pi->pubpi.phy_rev, 2)); | 24472 | ASSERT(NREV_LT(pi->pubpi.phy_rev, 2)); |
24473 | 24473 | ||
@@ -24531,7 +24531,7 @@ wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write, nphy_iq_comp_t *pcomp) | |||
24531 | } | 24531 | } |
24532 | 24532 | ||
24533 | void | 24533 | void |
24534 | wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est, uint16 num_samps, | 24534 | wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est, u16 num_samps, |
24535 | u8 wait_time, u8 wait_for_crs) | 24535 | u8 wait_time, u8 wait_for_crs) |
24536 | { | 24536 | { |
24537 | u8 core; | 24537 | u8 core; |
@@ -24689,9 +24689,9 @@ static void wlc_phy_calc_rx_iq_comp_nphy(phy_info_t *pi, u8 core_mask) | |||
24689 | 24689 | ||
24690 | static void wlc_phy_rxcal_radio_setup_nphy(phy_info_t *pi, u8 rx_core) | 24690 | static void wlc_phy_rxcal_radio_setup_nphy(phy_info_t *pi, u8 rx_core) |
24691 | { | 24691 | { |
24692 | uint16 offtune_val; | 24692 | u16 offtune_val; |
24693 | uint16 bias_g = 0; | 24693 | u16 bias_g = 0; |
24694 | uint16 bias_a = 0; | 24694 | u16 bias_a = 0; |
24695 | 24695 | ||
24696 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 24696 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
24697 | if (rx_core == PHY_CORE_0) { | 24697 | if (rx_core == PHY_CORE_0) { |
@@ -25157,7 +25157,7 @@ static void wlc_phy_rxcal_radio_cleanup_nphy(phy_info_t *pi, u8 rx_core) | |||
25157 | static void wlc_phy_rxcal_physetup_nphy(phy_info_t *pi, u8 rx_core) | 25157 | static void wlc_phy_rxcal_physetup_nphy(phy_info_t *pi, u8 rx_core) |
25158 | { | 25158 | { |
25159 | u8 tx_core; | 25159 | u8 tx_core; |
25160 | uint16 rx_antval, tx_antval; | 25160 | u16 rx_antval, tx_antval; |
25161 | 25161 | ||
25162 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 25162 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
25163 | 25163 | ||
@@ -25309,10 +25309,10 @@ static void wlc_phy_rxcal_phycleanup_nphy(phy_info_t *pi, u8 rx_core) | |||
25309 | 25309 | ||
25310 | static void | 25310 | static void |
25311 | wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core, | 25311 | wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core, |
25312 | uint16 *rxgain, u8 cal_type) | 25312 | u16 *rxgain, u8 cal_type) |
25313 | { | 25313 | { |
25314 | 25314 | ||
25315 | uint16 num_samps; | 25315 | u16 num_samps; |
25316 | phy_iq_est_t est[PHY_CORE_MAX]; | 25316 | phy_iq_est_t est[PHY_CORE_MAX]; |
25317 | u8 tx_core; | 25317 | u8 tx_core; |
25318 | nphy_iq_comp_t save_comp, zero_comp; | 25318 | nphy_iq_comp_t save_comp, zero_comp; |
@@ -25325,10 +25325,10 @@ wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core, | |||
25325 | s8 curr_gaintbl_index = 3; | 25325 | s8 curr_gaintbl_index = 3; |
25326 | u8 gainctrl_dirn = NPHY_RXCAL_GAIN_INIT; | 25326 | u8 gainctrl_dirn = NPHY_RXCAL_GAIN_INIT; |
25327 | nphy_ipa_txrxgain_t *nphy_rxcal_gaintbl; | 25327 | nphy_ipa_txrxgain_t *nphy_rxcal_gaintbl; |
25328 | uint16 hpvga, lpf_biq1, lpf_biq0, lna2, lna1; | 25328 | u16 hpvga, lpf_biq1, lpf_biq0, lna2, lna1; |
25329 | int16 fine_gain_idx; | 25329 | int16 fine_gain_idx; |
25330 | s8 txpwrindex; | 25330 | s8 txpwrindex; |
25331 | uint16 nphy_rxcal_txgain[2]; | 25331 | u16 nphy_rxcal_txgain[2]; |
25332 | 25332 | ||
25333 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 25333 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
25334 | 25334 | ||
@@ -25483,7 +25483,7 @@ wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core, | |||
25483 | if (fine_gain_idx + (int)lpf_biq0 > 10) { | 25483 | if (fine_gain_idx + (int)lpf_biq0 > 10) { |
25484 | lpf_biq1 = 10 - lpf_biq0; | 25484 | lpf_biq1 = 10 - lpf_biq0; |
25485 | } else { | 25485 | } else { |
25486 | lpf_biq1 = (uint16) MAX(fine_gain_idx, 0); | 25486 | lpf_biq1 = (u16) MAX(fine_gain_idx, 0); |
25487 | } | 25487 | } |
25488 | wlc_phy_rfctrl_override_1tomany_nphy(pi, | 25488 | wlc_phy_rfctrl_override_1tomany_nphy(pi, |
25489 | NPHY_REV7_RfctrlOverride_cmd_rxgain, | 25489 | NPHY_REV7_RfctrlOverride_cmd_rxgain, |
@@ -25493,7 +25493,7 @@ wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core, | |||
25493 | (lna2 << 2) | lna1), 0x3, | 25493 | (lna2 << 2) | lna1), 0x3, |
25494 | 0); | 25494 | 0); |
25495 | } else { | 25495 | } else { |
25496 | hpvga = (uint16) MAX(MIN(((int)hpvga) + delta_pwr, 10), 0); | 25496 | hpvga = (u16) MAX(MIN(((int)hpvga) + delta_pwr, 10), 0); |
25497 | wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), | 25497 | wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), |
25498 | ((hpvga << 12) | (lpf_biq1 << 10) | | 25498 | ((hpvga << 12) | (lpf_biq1 << 10) | |
25499 | (lpf_biq0 << 8) | (mix_tia_gain << | 25499 | (lpf_biq0 << 8) | (mix_tia_gain << |
@@ -25516,7 +25516,7 @@ wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core, | |||
25516 | } | 25516 | } |
25517 | 25517 | ||
25518 | static void | 25518 | static void |
25519 | wlc_phy_rxcal_gainctrl_nphy(phy_info_t *pi, u8 rx_core, uint16 *rxgain, | 25519 | wlc_phy_rxcal_gainctrl_nphy(phy_info_t *pi, u8 rx_core, u16 *rxgain, |
25520 | u8 cal_type) | 25520 | u8 cal_type) |
25521 | { | 25521 | { |
25522 | wlc_phy_rxcal_gainctrl_nphy_rev5(pi, rx_core, rxgain, cal_type); | 25522 | wlc_phy_rxcal_gainctrl_nphy_rev5(pi, rx_core, rxgain, cal_type); |
@@ -25532,29 +25532,29 @@ wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type) | |||
25532 | uint32 target_pwr_ratios[2] = { 28606, 18468 }; | 25532 | uint32 target_pwr_ratios[2] = { 28606, 18468 }; |
25533 | uint32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0; | 25533 | uint32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0; |
25534 | 25534 | ||
25535 | uint16 start_rccal_ovr_val = 128; | 25535 | u16 start_rccal_ovr_val = 128; |
25536 | uint16 txlpf_rccal_lpc_ovr_val = 128; | 25536 | u16 txlpf_rccal_lpc_ovr_val = 128; |
25537 | uint16 rxlpf_rccal_hpc_ovr_val = 159; | 25537 | u16 rxlpf_rccal_hpc_ovr_val = 159; |
25538 | 25538 | ||
25539 | uint16 orig_txlpf_rccal_lpc_ovr_val; | 25539 | u16 orig_txlpf_rccal_lpc_ovr_val; |
25540 | uint16 orig_rxlpf_rccal_hpc_ovr_val; | 25540 | u16 orig_rxlpf_rccal_hpc_ovr_val; |
25541 | uint16 radio_addr_offset_rx; | 25541 | u16 radio_addr_offset_rx; |
25542 | uint16 radio_addr_offset_tx; | 25542 | u16 radio_addr_offset_tx; |
25543 | uint16 orig_dcBypass; | 25543 | u16 orig_dcBypass; |
25544 | uint16 orig_RxStrnFilt40Num[6]; | 25544 | u16 orig_RxStrnFilt40Num[6]; |
25545 | uint16 orig_RxStrnFilt40Den[4]; | 25545 | u16 orig_RxStrnFilt40Den[4]; |
25546 | uint16 orig_rfctrloverride[2]; | 25546 | u16 orig_rfctrloverride[2]; |
25547 | uint16 orig_rfctrlauxreg[2]; | 25547 | u16 orig_rfctrlauxreg[2]; |
25548 | uint16 orig_rfctrlrssiothers; | 25548 | u16 orig_rfctrlrssiothers; |
25549 | uint16 tx_lpf_bw = 4; | 25549 | u16 tx_lpf_bw = 4; |
25550 | 25550 | ||
25551 | uint16 rx_lpf_bw, rx_lpf_bws[2] = { 2, 4 }; | 25551 | u16 rx_lpf_bw, rx_lpf_bws[2] = { 2, 4 }; |
25552 | uint16 lpf_hpc = 7, hpvga_hpc = 7; | 25552 | u16 lpf_hpc = 7, hpvga_hpc = 7; |
25553 | 25553 | ||
25554 | s8 rccal_stepsize; | 25554 | s8 rccal_stepsize; |
25555 | uint16 rccal_val, last_rccal_val = 0, best_rccal_val = 0; | 25555 | u16 rccal_val, last_rccal_val = 0, best_rccal_val = 0; |
25556 | uint32 ref_iq_vals = 0, target_iq_vals = 0; | 25556 | uint32 ref_iq_vals = 0, target_iq_vals = 0; |
25557 | uint16 num_samps, log_num_samps = 10; | 25557 | u16 num_samps, log_num_samps = 10; |
25558 | phy_iq_est_t est[PHY_CORE_MAX]; | 25558 | phy_iq_est_t est[PHY_CORE_MAX]; |
25559 | 25559 | ||
25560 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 25560 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
@@ -25767,11 +25767,11 @@ static int | |||
25767 | wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t target_gain, | 25767 | wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t target_gain, |
25768 | u8 cal_type, bool debug) | 25768 | u8 cal_type, bool debug) |
25769 | { | 25769 | { |
25770 | uint16 orig_BBConfig; | 25770 | u16 orig_BBConfig; |
25771 | u8 core_no, rx_core; | 25771 | u8 core_no, rx_core; |
25772 | u8 best_rccal[2]; | 25772 | u8 best_rccal[2]; |
25773 | uint16 gain_save[2]; | 25773 | u16 gain_save[2]; |
25774 | uint16 cal_gain[2]; | 25774 | u16 cal_gain[2]; |
25775 | nphy_iqcal_params_t cal_params[2]; | 25775 | nphy_iqcal_params_t cal_params[2]; |
25776 | u8 rxcore_state; | 25776 | u8 rxcore_state; |
25777 | s8 rxlpf_rccal_hpc, txlpf_rccal_lpc; | 25777 | s8 rxlpf_rccal_hpc, txlpf_rccal_lpc; |
@@ -25926,20 +25926,20 @@ wlc_phy_cal_rxiq_nphy_rev2(phy_info_t *pi, nphy_txgains_t target_gain, | |||
25926 | { | 25926 | { |
25927 | phy_iq_est_t est[PHY_CORE_MAX]; | 25927 | phy_iq_est_t est[PHY_CORE_MAX]; |
25928 | u8 core_num, rx_core, tx_core; | 25928 | u8 core_num, rx_core, tx_core; |
25929 | uint16 lna_vals[] = { 0x3, 0x3, 0x1 }; | 25929 | u16 lna_vals[] = { 0x3, 0x3, 0x1 }; |
25930 | uint16 hpf1_vals[] = { 0x7, 0x2, 0x0 }; | 25930 | u16 hpf1_vals[] = { 0x7, 0x2, 0x0 }; |
25931 | uint16 hpf2_vals[] = { 0x2, 0x0, 0x0 }; | 25931 | u16 hpf2_vals[] = { 0x2, 0x0, 0x0 }; |
25932 | int16 curr_hpf1, curr_hpf2, curr_hpf, curr_lna; | 25932 | int16 curr_hpf1, curr_hpf2, curr_hpf, curr_lna; |
25933 | int16 desired_log2_pwr, actual_log2_pwr, hpf_change; | 25933 | int16 desired_log2_pwr, actual_log2_pwr, hpf_change; |
25934 | uint16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride; | 25934 | u16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride; |
25935 | uint16 orig_RfctrlIntcRx, orig_RfctrlIntcTx; | 25935 | u16 orig_RfctrlIntcRx, orig_RfctrlIntcTx; |
25936 | uint16 num_samps; | 25936 | u16 num_samps; |
25937 | uint32 i_pwr, q_pwr, tot_pwr[3]; | 25937 | uint32 i_pwr, q_pwr, tot_pwr[3]; |
25938 | u8 gain_pass, use_hpf_num; | 25938 | u8 gain_pass, use_hpf_num; |
25939 | uint16 mask, val1, val2; | 25939 | u16 mask, val1, val2; |
25940 | uint16 core_no; | 25940 | u16 core_no; |
25941 | uint16 gain_save[2]; | 25941 | u16 gain_save[2]; |
25942 | uint16 cal_gain[2]; | 25942 | u16 cal_gain[2]; |
25943 | nphy_iqcal_params_t cal_params[2]; | 25943 | nphy_iqcal_params_t cal_params[2]; |
25944 | u8 phy_bw; | 25944 | u8 phy_bw; |
25945 | int bcmerror = BCME_OK; | 25945 | int bcmerror = BCME_OK; |
@@ -26079,7 +26079,7 @@ wlc_phy_cal_rxiq_nphy_rev2(phy_info_t *pi, nphy_txgains_t target_gain, | |||
26079 | 26079 | ||
26080 | if (first_playtone) { | 26080 | if (first_playtone) { |
26081 | bcmerror = wlc_phy_tx_tone_nphy(pi, 4000, | 26081 | bcmerror = wlc_phy_tx_tone_nphy(pi, 4000, |
26082 | (uint16) (pi-> | 26082 | (u16) (pi-> |
26083 | nphy_rxcalparams | 26083 | nphy_rxcalparams |
26084 | & | 26084 | & |
26085 | 0xffff), | 26085 | 0xffff), |
@@ -26165,7 +26165,7 @@ wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain, | |||
26165 | static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi) | 26165 | static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi) |
26166 | { | 26166 | { |
26167 | int j, type = 2; | 26167 | int j, type = 2; |
26168 | uint16 addr_offset = 0x2c5; | 26168 | u16 addr_offset = 0x2c5; |
26169 | 26169 | ||
26170 | for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) { | 26170 | for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) { |
26171 | write_phy_reg(pi, addr_offset + j, | 26171 | write_phy_reg(pi, addr_offset + j, |
@@ -26176,7 +26176,7 @@ static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi) | |||
26176 | static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi) | 26176 | static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi) |
26177 | { | 26177 | { |
26178 | int j, type; | 26178 | int j, type; |
26179 | uint16 addr_offset[] = { 0x186, 0x195, | 26179 | u16 addr_offset[] = { 0x186, 0x195, |
26180 | 0x2c5 | 26180 | 0x2c5 |
26181 | }; | 26181 | }; |
26182 | 26182 | ||
@@ -26228,9 +26228,9 @@ static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi) | |||
26228 | } | 26228 | } |
26229 | } | 26229 | } |
26230 | 26230 | ||
26231 | static uint16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi) | 26231 | static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi) |
26232 | { | 26232 | { |
26233 | uint16 m0m1; | 26233 | u16 m0m1; |
26234 | 26234 | ||
26235 | wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1); | 26235 | wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1); |
26236 | 26236 | ||
@@ -26239,7 +26239,7 @@ static uint16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi) | |||
26239 | 26239 | ||
26240 | static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1) | 26240 | static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1) |
26241 | { | 26241 | { |
26242 | uint16 m0m1 = (uint16) ((m0 << 8) | m1); | 26242 | u16 m0m1 = (u16) ((m0 << 8) | m1); |
26243 | 26243 | ||
26244 | wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m0m1); | 26244 | wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m0m1); |
26245 | wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1); | 26245 | wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1); |
@@ -26322,7 +26322,7 @@ wlc_phy_papd_cal_setup_nphy(phy_info_t *pi, nphy_papd_restore_state *state, | |||
26322 | { | 26322 | { |
26323 | int32 tone_freq; | 26323 | int32 tone_freq; |
26324 | u8 off_core; | 26324 | u8 off_core; |
26325 | uint16 mixgain = 0; | 26325 | u16 mixgain = 0; |
26326 | 26326 | ||
26327 | off_core = core ^ 0x1; | 26327 | off_core = core ^ 0x1; |
26328 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { | 26328 | if (NREV_GE(pi->pubpi.phy_rev, 7)) { |
@@ -26776,8 +26776,8 @@ static void | |||
26776 | wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *txgains, | 26776 | wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *txgains, |
26777 | phy_cal_mode_t cal_mode, u8 core) | 26777 | phy_cal_mode_t cal_mode, u8 core) |
26778 | { | 26778 | { |
26779 | uint16 phy_a1, phy_a2, phy_a3; | 26779 | u16 phy_a1, phy_a2, phy_a3; |
26780 | uint16 phy_a4, phy_a5; | 26780 | u16 phy_a4, phy_a5; |
26781 | bool phy_a6; | 26781 | bool phy_a6; |
26782 | u8 phy_a7, m[2]; | 26782 | u8 phy_a7, m[2]; |
26783 | uint32 phy_a8 = 0; | 26783 | uint32 phy_a8 = 0; |
@@ -27131,10 +27131,10 @@ static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core) | |||
27131 | for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) { | 27131 | for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) { |
27132 | if (CHSPEC_IS2G(pi->radio_chanspec)) { | 27132 | if (CHSPEC_IS2G(pi->radio_chanspec)) { |
27133 | phy_a4.gains.pad[core] = | 27133 | phy_a4.gains.pad[core] = |
27134 | (uint16) phy_a15[phy_a12]; | 27134 | (u16) phy_a15[phy_a12]; |
27135 | } else { | 27135 | } else { |
27136 | phy_a4.gains.pga[core] = | 27136 | phy_a4.gains.pga[core] = |
27137 | (uint16) phy_a15[phy_a12]; | 27137 | (u16) phy_a15[phy_a12]; |
27138 | } | 27138 | } |
27139 | 27139 | ||
27140 | wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core); | 27140 | wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core); |
@@ -27242,7 +27242,7 @@ static void wlc_phy_a4(phy_info_t *pi, bool full_cal) | |||
27242 | u8 phy_b4; | 27242 | u8 phy_b4; |
27243 | u8 phy_b5; | 27243 | u8 phy_b5; |
27244 | int16 phy_b6, phy_b7, phy_b8; | 27244 | int16 phy_b6, phy_b7, phy_b8; |
27245 | uint16 phy_b9; | 27245 | u16 phy_b9; |
27246 | int16 phy_b10, phy_b11, phy_b12; | 27246 | int16 phy_b10, phy_b11, phy_b12; |
27247 | 27247 | ||
27248 | phy_b11 = 0; | 27248 | phy_b11 = 0; |
@@ -27533,7 +27533,7 @@ void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi) | |||
27533 | { | 27533 | { |
27534 | uint core; | 27534 | uint core; |
27535 | uint32 txgain; | 27535 | uint32 txgain; |
27536 | uint16 rad_gain, dac_gain, bbmult, m1m2; | 27536 | u16 rad_gain, dac_gain, bbmult, m1m2; |
27537 | u8 txpi[2], chan_freq_range; | 27537 | u8 txpi[2], chan_freq_range; |
27538 | int32 rfpwr_offset; | 27538 | int32 rfpwr_offset; |
27539 | 27539 | ||
@@ -27680,14 +27680,14 @@ void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi) | |||
27680 | } | 27680 | } |
27681 | } | 27681 | } |
27682 | 27682 | ||
27683 | and_phy_reg(pi, 0xbf, (uint16) (~(0x1f << 0))); | 27683 | and_phy_reg(pi, 0xbf, (u16) (~(0x1f << 0))); |
27684 | 27684 | ||
27685 | if (pi->phyhang_avoid) | 27685 | if (pi->phyhang_avoid) |
27686 | wlc_phy_stay_in_carriersearch_nphy(pi, FALSE); | 27686 | wlc_phy_stay_in_carriersearch_nphy(pi, FALSE); |
27687 | } | 27687 | } |
27688 | 27688 | ||
27689 | static void | 27689 | static void |
27690 | wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max, uint16 *pwr_offset, | 27690 | wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max, u16 *pwr_offset, |
27691 | u8 tmp_max_pwr, u8 rate_start, | 27691 | u8 tmp_max_pwr, u8 rate_start, |
27692 | u8 rate_end) | 27692 | u8 rate_end) |
27693 | { | 27693 | { |
@@ -27748,7 +27748,7 @@ void BCMNMIATTACHFN(wlc_phy_txpwr_apply_nphy) (phy_info_t *pi) | |||
27748 | uint rate1, rate2, band_num; | 27748 | uint rate1, rate2, band_num; |
27749 | u8 tmp_bw40po = 0, tmp_cddpo = 0, tmp_stbcpo = 0; | 27749 | u8 tmp_bw40po = 0, tmp_cddpo = 0, tmp_stbcpo = 0; |
27750 | u8 tmp_max_pwr = 0; | 27750 | u8 tmp_max_pwr = 0; |
27751 | uint16 pwr_offsets1[2], *pwr_offsets2 = NULL; | 27751 | u16 pwr_offsets1[2], *pwr_offsets2 = NULL; |
27752 | u8 *tx_srom_max_rate = NULL; | 27752 | u8 *tx_srom_max_rate = NULL; |
27753 | 27753 | ||
27754 | for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP); band_num++) { | 27754 | for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP); band_num++) { |
@@ -27765,9 +27765,9 @@ void BCMNMIATTACHFN(wlc_phy_txpwr_apply_nphy) (phy_info_t *pi) | |||
27765 | TXP_FIRST_CCK, | 27765 | TXP_FIRST_CCK, |
27766 | TXP_LAST_CCK); | 27766 | TXP_LAST_CCK); |
27767 | 27767 | ||
27768 | pwr_offsets1[0] = (uint16) (pi->ofdm2gpo & 0xffff); | 27768 | pwr_offsets1[0] = (u16) (pi->ofdm2gpo & 0xffff); |
27769 | pwr_offsets1[1] = | 27769 | pwr_offsets1[1] = |
27770 | (uint16) (pi->ofdm2gpo >> 16) & 0xffff; | 27770 | (u16) (pi->ofdm2gpo >> 16) & 0xffff; |
27771 | 27771 | ||
27772 | pwr_offsets2 = pi->mcs2gpo; | 27772 | pwr_offsets2 = pi->mcs2gpo; |
27773 | 27773 | ||
@@ -27782,9 +27782,9 @@ void BCMNMIATTACHFN(wlc_phy_txpwr_apply_nphy) (phy_info_t *pi) | |||
27782 | tmp_max_pwr = MIN(pi->nphy_pwrctrl_info[0].max_pwr_5gm, | 27782 | tmp_max_pwr = MIN(pi->nphy_pwrctrl_info[0].max_pwr_5gm, |
27783 | pi->nphy_pwrctrl_info[1].max_pwr_5gm); | 27783 | pi->nphy_pwrctrl_info[1].max_pwr_5gm); |
27784 | 27784 | ||
27785 | pwr_offsets1[0] = (uint16) (pi->ofdm5gpo & 0xffff); | 27785 | pwr_offsets1[0] = (u16) (pi->ofdm5gpo & 0xffff); |
27786 | pwr_offsets1[1] = | 27786 | pwr_offsets1[1] = |
27787 | (uint16) (pi->ofdm5gpo >> 16) & 0xffff; | 27787 | (u16) (pi->ofdm5gpo >> 16) & 0xffff; |
27788 | 27788 | ||
27789 | pwr_offsets2 = pi->mcs5gpo; | 27789 | pwr_offsets2 = pi->mcs5gpo; |
27790 | 27790 | ||
@@ -27799,9 +27799,9 @@ void BCMNMIATTACHFN(wlc_phy_txpwr_apply_nphy) (phy_info_t *pi) | |||
27799 | tmp_max_pwr = MIN(pi->nphy_pwrctrl_info[0].max_pwr_5gl, | 27799 | tmp_max_pwr = MIN(pi->nphy_pwrctrl_info[0].max_pwr_5gl, |
27800 | pi->nphy_pwrctrl_info[1].max_pwr_5gl); | 27800 | pi->nphy_pwrctrl_info[1].max_pwr_5gl); |
27801 | 27801 | ||
27802 | pwr_offsets1[0] = (uint16) (pi->ofdm5glpo & 0xffff); | 27802 | pwr_offsets1[0] = (u16) (pi->ofdm5glpo & 0xffff); |
27803 | pwr_offsets1[1] = | 27803 | pwr_offsets1[1] = |
27804 | (uint16) (pi->ofdm5glpo >> 16) & 0xffff; | 27804 | (u16) (pi->ofdm5glpo >> 16) & 0xffff; |
27805 | 27805 | ||
27806 | pwr_offsets2 = pi->mcs5glpo; | 27806 | pwr_offsets2 = pi->mcs5glpo; |
27807 | 27807 | ||
@@ -27816,9 +27816,9 @@ void BCMNMIATTACHFN(wlc_phy_txpwr_apply_nphy) (phy_info_t *pi) | |||
27816 | tmp_max_pwr = MIN(pi->nphy_pwrctrl_info[0].max_pwr_5gh, | 27816 | tmp_max_pwr = MIN(pi->nphy_pwrctrl_info[0].max_pwr_5gh, |
27817 | pi->nphy_pwrctrl_info[1].max_pwr_5gh); | 27817 | pi->nphy_pwrctrl_info[1].max_pwr_5gh); |
27818 | 27818 | ||
27819 | pwr_offsets1[0] = (uint16) (pi->ofdm5ghpo & 0xffff); | 27819 | pwr_offsets1[0] = (u16) (pi->ofdm5ghpo & 0xffff); |
27820 | pwr_offsets1[1] = | 27820 | pwr_offsets1[1] = |
27821 | (uint16) (pi->ofdm5ghpo >> 16) & 0xffff; | 27821 | (u16) (pi->ofdm5ghpo >> 16) & 0xffff; |
27822 | 27822 | ||
27823 | pwr_offsets2 = pi->mcs5ghpo; | 27823 | pwr_offsets2 = pi->mcs5ghpo; |
27824 | 27824 | ||
@@ -27943,7 +27943,7 @@ void BCMNMIATTACHFN(wlc_phy_txpwr_apply_nphy) (phy_info_t *pi) | |||
27943 | 27943 | ||
27944 | static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi) | 27944 | static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi) |
27945 | { | 27945 | { |
27946 | uint16 bw40po, cddpo, stbcpo, bwduppo; | 27946 | u16 bw40po, cddpo, stbcpo, bwduppo; |
27947 | uint band_num; | 27947 | uint band_num; |
27948 | 27948 | ||
27949 | if (pi->sh->sromrev >= 9) { | 27949 | if (pi->sh->sromrev >= 9) { |
@@ -27951,25 +27951,25 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi) | |||
27951 | return; | 27951 | return; |
27952 | } | 27952 | } |
27953 | 27953 | ||
27954 | bw40po = (uint16) PHY_GETINTVAR(pi, "bw40po"); | 27954 | bw40po = (u16) PHY_GETINTVAR(pi, "bw40po"); |
27955 | pi->bw402gpo = bw40po & 0xf; | 27955 | pi->bw402gpo = bw40po & 0xf; |
27956 | pi->bw405gpo = (bw40po & 0xf0) >> 4; | 27956 | pi->bw405gpo = (bw40po & 0xf0) >> 4; |
27957 | pi->bw405glpo = (bw40po & 0xf00) >> 8; | 27957 | pi->bw405glpo = (bw40po & 0xf00) >> 8; |
27958 | pi->bw405ghpo = (bw40po & 0xf000) >> 12; | 27958 | pi->bw405ghpo = (bw40po & 0xf000) >> 12; |
27959 | 27959 | ||
27960 | cddpo = (uint16) PHY_GETINTVAR(pi, "cddpo"); | 27960 | cddpo = (u16) PHY_GETINTVAR(pi, "cddpo"); |
27961 | pi->cdd2gpo = cddpo & 0xf; | 27961 | pi->cdd2gpo = cddpo & 0xf; |
27962 | pi->cdd5gpo = (cddpo & 0xf0) >> 4; | 27962 | pi->cdd5gpo = (cddpo & 0xf0) >> 4; |
27963 | pi->cdd5glpo = (cddpo & 0xf00) >> 8; | 27963 | pi->cdd5glpo = (cddpo & 0xf00) >> 8; |
27964 | pi->cdd5ghpo = (cddpo & 0xf000) >> 12; | 27964 | pi->cdd5ghpo = (cddpo & 0xf000) >> 12; |
27965 | 27965 | ||
27966 | stbcpo = (uint16) PHY_GETINTVAR(pi, "stbcpo"); | 27966 | stbcpo = (u16) PHY_GETINTVAR(pi, "stbcpo"); |
27967 | pi->stbc2gpo = stbcpo & 0xf; | 27967 | pi->stbc2gpo = stbcpo & 0xf; |
27968 | pi->stbc5gpo = (stbcpo & 0xf0) >> 4; | 27968 | pi->stbc5gpo = (stbcpo & 0xf0) >> 4; |
27969 | pi->stbc5glpo = (stbcpo & 0xf00) >> 8; | 27969 | pi->stbc5glpo = (stbcpo & 0xf00) >> 8; |
27970 | pi->stbc5ghpo = (stbcpo & 0xf000) >> 12; | 27970 | pi->stbc5ghpo = (stbcpo & 0xf000) >> 12; |
27971 | 27971 | ||
27972 | bwduppo = (uint16) PHY_GETINTVAR(pi, "bwduppo"); | 27972 | bwduppo = (u16) PHY_GETINTVAR(pi, "bwduppo"); |
27973 | pi->bwdup2gpo = bwduppo & 0xf; | 27973 | pi->bwdup2gpo = bwduppo & 0xf; |
27974 | pi->bwdup5gpo = (bwduppo & 0xf0) >> 4; | 27974 | pi->bwdup5gpo = (bwduppo & 0xf0) >> 4; |
27975 | pi->bwdup5glpo = (bwduppo & 0xf00) >> 8; | 27975 | pi->bwdup5glpo = (bwduppo & 0xf00) >> 8; |
@@ -28004,18 +28004,18 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi) | |||
28004 | pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g = | 28004 | pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g = |
28005 | (s8) PHY_GETINTVAR(pi, "itt2ga1"); | 28005 | (s8) PHY_GETINTVAR(pi, "itt2ga1"); |
28006 | 28006 | ||
28007 | pi->cck2gpo = (uint16) PHY_GETINTVAR(pi, "cck2gpo"); | 28007 | pi->cck2gpo = (u16) PHY_GETINTVAR(pi, "cck2gpo"); |
28008 | 28008 | ||
28009 | pi->ofdm2gpo = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo"); | 28009 | pi->ofdm2gpo = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo"); |
28010 | 28010 | ||
28011 | pi->mcs2gpo[0] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo0"); | 28011 | pi->mcs2gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs2gpo0"); |
28012 | pi->mcs2gpo[1] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo1"); | 28012 | pi->mcs2gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs2gpo1"); |
28013 | pi->mcs2gpo[2] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo2"); | 28013 | pi->mcs2gpo[2] = (u16) PHY_GETINTVAR(pi, "mcs2gpo2"); |
28014 | pi->mcs2gpo[3] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo3"); | 28014 | pi->mcs2gpo[3] = (u16) PHY_GETINTVAR(pi, "mcs2gpo3"); |
28015 | pi->mcs2gpo[4] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo4"); | 28015 | pi->mcs2gpo[4] = (u16) PHY_GETINTVAR(pi, "mcs2gpo4"); |
28016 | pi->mcs2gpo[5] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo5"); | 28016 | pi->mcs2gpo[5] = (u16) PHY_GETINTVAR(pi, "mcs2gpo5"); |
28017 | pi->mcs2gpo[6] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo6"); | 28017 | pi->mcs2gpo[6] = (u16) PHY_GETINTVAR(pi, "mcs2gpo6"); |
28018 | pi->mcs2gpo[7] = (uint16) PHY_GETINTVAR(pi, "mcs2gpo7"); | 28018 | pi->mcs2gpo[7] = (u16) PHY_GETINTVAR(pi, "mcs2gpo7"); |
28019 | break; | 28019 | break; |
28020 | case 1: | 28020 | case 1: |
28021 | 28021 | ||
@@ -28046,14 +28046,14 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi) | |||
28046 | 28046 | ||
28047 | pi->ofdm5gpo = (uint32) PHY_GETINTVAR(pi, "ofdm5gpo"); | 28047 | pi->ofdm5gpo = (uint32) PHY_GETINTVAR(pi, "ofdm5gpo"); |
28048 | 28048 | ||
28049 | pi->mcs5gpo[0] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo0"); | 28049 | pi->mcs5gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs5gpo0"); |
28050 | pi->mcs5gpo[1] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo1"); | 28050 | pi->mcs5gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs5gpo1"); |
28051 | pi->mcs5gpo[2] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo2"); | 28051 | pi->mcs5gpo[2] = (u16) PHY_GETINTVAR(pi, "mcs5gpo2"); |
28052 | pi->mcs5gpo[3] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo3"); | 28052 | pi->mcs5gpo[3] = (u16) PHY_GETINTVAR(pi, "mcs5gpo3"); |
28053 | pi->mcs5gpo[4] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo4"); | 28053 | pi->mcs5gpo[4] = (u16) PHY_GETINTVAR(pi, "mcs5gpo4"); |
28054 | pi->mcs5gpo[5] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo5"); | 28054 | pi->mcs5gpo[5] = (u16) PHY_GETINTVAR(pi, "mcs5gpo5"); |
28055 | pi->mcs5gpo[6] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo6"); | 28055 | pi->mcs5gpo[6] = (u16) PHY_GETINTVAR(pi, "mcs5gpo6"); |
28056 | pi->mcs5gpo[7] = (uint16) PHY_GETINTVAR(pi, "mcs5gpo7"); | 28056 | pi->mcs5gpo[7] = (u16) PHY_GETINTVAR(pi, "mcs5gpo7"); |
28057 | break; | 28057 | break; |
28058 | case 2: | 28058 | case 2: |
28059 | 28059 | ||
@@ -28083,21 +28083,21 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi) | |||
28083 | pi->ofdm5glpo = (uint32) PHY_GETINTVAR(pi, "ofdm5glpo"); | 28083 | pi->ofdm5glpo = (uint32) PHY_GETINTVAR(pi, "ofdm5glpo"); |
28084 | 28084 | ||
28085 | pi->mcs5glpo[0] = | 28085 | pi->mcs5glpo[0] = |
28086 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo0"); | 28086 | (u16) PHY_GETINTVAR(pi, "mcs5glpo0"); |
28087 | pi->mcs5glpo[1] = | 28087 | pi->mcs5glpo[1] = |
28088 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo1"); | 28088 | (u16) PHY_GETINTVAR(pi, "mcs5glpo1"); |
28089 | pi->mcs5glpo[2] = | 28089 | pi->mcs5glpo[2] = |
28090 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo2"); | 28090 | (u16) PHY_GETINTVAR(pi, "mcs5glpo2"); |
28091 | pi->mcs5glpo[3] = | 28091 | pi->mcs5glpo[3] = |
28092 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo3"); | 28092 | (u16) PHY_GETINTVAR(pi, "mcs5glpo3"); |
28093 | pi->mcs5glpo[4] = | 28093 | pi->mcs5glpo[4] = |
28094 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo4"); | 28094 | (u16) PHY_GETINTVAR(pi, "mcs5glpo4"); |
28095 | pi->mcs5glpo[5] = | 28095 | pi->mcs5glpo[5] = |
28096 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo5"); | 28096 | (u16) PHY_GETINTVAR(pi, "mcs5glpo5"); |
28097 | pi->mcs5glpo[6] = | 28097 | pi->mcs5glpo[6] = |
28098 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo6"); | 28098 | (u16) PHY_GETINTVAR(pi, "mcs5glpo6"); |
28099 | pi->mcs5glpo[7] = | 28099 | pi->mcs5glpo[7] = |
28100 | (uint16) PHY_GETINTVAR(pi, "mcs5glpo7"); | 28100 | (u16) PHY_GETINTVAR(pi, "mcs5glpo7"); |
28101 | break; | 28101 | break; |
28102 | case 3: | 28102 | case 3: |
28103 | 28103 | ||
@@ -28127,21 +28127,21 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi) | |||
28127 | pi->ofdm5ghpo = (uint32) PHY_GETINTVAR(pi, "ofdm5ghpo"); | 28127 | pi->ofdm5ghpo = (uint32) PHY_GETINTVAR(pi, "ofdm5ghpo"); |
28128 | 28128 | ||
28129 | pi->mcs5ghpo[0] = | 28129 | pi->mcs5ghpo[0] = |
28130 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo0"); | 28130 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo0"); |
28131 | pi->mcs5ghpo[1] = | 28131 | pi->mcs5ghpo[1] = |
28132 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo1"); | 28132 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo1"); |
28133 | pi->mcs5ghpo[2] = | 28133 | pi->mcs5ghpo[2] = |
28134 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo2"); | 28134 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo2"); |
28135 | pi->mcs5ghpo[3] = | 28135 | pi->mcs5ghpo[3] = |
28136 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo3"); | 28136 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo3"); |
28137 | pi->mcs5ghpo[4] = | 28137 | pi->mcs5ghpo[4] = |
28138 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo4"); | 28138 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo4"); |
28139 | pi->mcs5ghpo[5] = | 28139 | pi->mcs5ghpo[5] = |
28140 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo5"); | 28140 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo5"); |
28141 | pi->mcs5ghpo[6] = | 28141 | pi->mcs5ghpo[6] = |
28142 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo6"); | 28142 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo6"); |
28143 | pi->mcs5ghpo[7] = | 28143 | pi->mcs5ghpo[7] = |
28144 | (uint16) PHY_GETINTVAR(pi, "mcs5ghpo7"); | 28144 | (u16) PHY_GETINTVAR(pi, "mcs5ghpo7"); |
28145 | break; | 28145 | break; |
28146 | } | 28146 | } |
28147 | } | 28147 | } |
@@ -28232,7 +28232,7 @@ void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi) | |||
28232 | static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi) | 28232 | static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi) |
28233 | { | 28233 | { |
28234 | uint32 idx; | 28234 | uint32 idx; |
28235 | uint16 iqloCalbuf[7]; | 28235 | u16 iqloCalbuf[7]; |
28236 | uint32 iqcomp, locomp, curr_locomp; | 28236 | uint32 iqcomp, locomp, curr_locomp; |
28237 | s8 locomp_i, locomp_q; | 28237 | s8 locomp_i, locomp_q; |
28238 | s8 curr_locomp_i, curr_locomp_q; | 28238 | s8 curr_locomp_i, curr_locomp_q; |
@@ -28500,7 +28500,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi) | |||
28500 | or_phy_reg(pi, 0x122, (0x1 << 0)); | 28500 | or_phy_reg(pi, 0x122, (0x1 << 0)); |
28501 | 28501 | ||
28502 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 28502 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
28503 | and_phy_reg(pi, 0x1e7, (uint16) (~(0x1 << 15))); | 28503 | and_phy_reg(pi, 0x1e7, (u16) (~(0x1 << 15))); |
28504 | } else { | 28504 | } else { |
28505 | 28505 | ||
28506 | or_phy_reg(pi, 0x1e7, (0x1 << 15)); | 28506 | or_phy_reg(pi, 0x1e7, (0x1 << 15)); |
@@ -28721,7 +28721,7 @@ static bool wlc_phy_txpwr_ison_nphy(phy_info_t *pi) | |||
28721 | 28721 | ||
28722 | static u8 wlc_phy_txpwr_idx_cur_get_nphy(phy_info_t *pi, u8 core) | 28722 | static u8 wlc_phy_txpwr_idx_cur_get_nphy(phy_info_t *pi, u8 core) |
28723 | { | 28723 | { |
28724 | uint16 tmp; | 28724 | u16 tmp; |
28725 | tmp = read_phy_reg(pi, ((core == PHY_CORE_0) ? 0x1ed : 0x1ee)); | 28725 | tmp = read_phy_reg(pi, ((core == PHY_CORE_0) ? 0x1ed : 0x1ee)); |
28726 | 28726 | ||
28727 | tmp = (tmp & (0x7f << 8)) >> 8; | 28727 | tmp = (tmp & (0x7f << 8)) >> 8; |
@@ -28737,10 +28737,10 @@ wlc_phy_txpwr_idx_cur_set_nphy(phy_info_t *pi, u8 idx0, u8 idx1) | |||
28737 | mod_phy_reg(pi, 0x222, (0xff << 0), idx1); | 28737 | mod_phy_reg(pi, 0x222, (0xff << 0), idx1); |
28738 | } | 28738 | } |
28739 | 28739 | ||
28740 | uint16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi) | 28740 | u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi) |
28741 | { | 28741 | { |
28742 | uint16 tmp; | 28742 | u16 tmp; |
28743 | uint16 pwr_idx[2]; | 28743 | u16 pwr_idx[2]; |
28744 | 28744 | ||
28745 | if (wlc_phy_txpwr_ison_nphy(pi)) { | 28745 | if (wlc_phy_txpwr_ison_nphy(pi)) { |
28746 | pwr_idx[0] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_0); | 28746 | pwr_idx[0] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_0); |
@@ -28777,12 +28777,12 @@ void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi) | |||
28777 | 28777 | ||
28778 | void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type) | 28778 | void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type) |
28779 | { | 28779 | { |
28780 | uint16 mask = 0, val = 0, ishw = 0; | 28780 | u16 mask = 0, val = 0, ishw = 0; |
28781 | u8 ctr; | 28781 | u8 ctr; |
28782 | uint core; | 28782 | uint core; |
28783 | uint32 tbl_offset; | 28783 | uint32 tbl_offset; |
28784 | uint32 tbl_len; | 28784 | uint32 tbl_len; |
28785 | uint16 regval[84]; | 28785 | u16 regval[84]; |
28786 | 28786 | ||
28787 | if (pi->phyhang_avoid) | 28787 | if (pi->phyhang_avoid) |
28788 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); | 28788 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); |
@@ -28823,11 +28823,11 @@ void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type) | |||
28823 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 28823 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
28824 | 28824 | ||
28825 | and_phy_reg(pi, 0x1e7, | 28825 | and_phy_reg(pi, 0x1e7, |
28826 | (uint16) (~((0x1 << 15) | | 28826 | (u16) (~((0x1 << 15) | |
28827 | (0x1 << 14) | (0x1 << 13)))); | 28827 | (0x1 << 14) | (0x1 << 13)))); |
28828 | } else { | 28828 | } else { |
28829 | and_phy_reg(pi, 0x1e7, | 28829 | and_phy_reg(pi, 0x1e7, |
28830 | (uint16) (~((0x1 << 14) | (0x1 << 13)))); | 28830 | (u16) (~((0x1 << 14) | (0x1 << 13)))); |
28831 | } | 28831 | } |
28832 | 28832 | ||
28833 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { | 28833 | if (NREV_GE(pi->pubpi.phy_rev, 3)) { |
@@ -28925,18 +28925,18 @@ wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask, s8 txpwrindex, | |||
28925 | bool restore_cals) | 28925 | bool restore_cals) |
28926 | { | 28926 | { |
28927 | u8 core, txpwrctl_tbl; | 28927 | u8 core, txpwrctl_tbl; |
28928 | uint16 tx_ind0, iq_ind0, lo_ind0; | 28928 | u16 tx_ind0, iq_ind0, lo_ind0; |
28929 | uint16 m1m2; | 28929 | u16 m1m2; |
28930 | uint32 txgain; | 28930 | uint32 txgain; |
28931 | uint16 rad_gain, dac_gain; | 28931 | u16 rad_gain, dac_gain; |
28932 | u8 bbmult; | 28932 | u8 bbmult; |
28933 | uint32 iqcomp; | 28933 | uint32 iqcomp; |
28934 | uint16 iqcomp_a, iqcomp_b; | 28934 | u16 iqcomp_a, iqcomp_b; |
28935 | uint32 locomp; | 28935 | uint32 locomp; |
28936 | uint16 tmpval; | 28936 | u16 tmpval; |
28937 | u8 tx_pwr_ctrl_state; | 28937 | u8 tx_pwr_ctrl_state; |
28938 | int32 rfpwr_offset; | 28938 | int32 rfpwr_offset; |
28939 | uint16 regval[2]; | 28939 | u16 regval[2]; |
28940 | 28940 | ||
28941 | if (pi->phyhang_avoid) | 28941 | if (pi->phyhang_avoid) |
28942 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); | 28942 | wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); |
@@ -29112,8 +29112,8 @@ wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask, s8 txpwrindex, | |||
29112 | iqcomp_b = (iqcomp >> 0) & ((1 << (9 - 0 + 1)) - 1); | 29112 | iqcomp_b = (iqcomp >> 0) & ((1 << (9 - 0 + 1)) - 1); |
29113 | 29113 | ||
29114 | if (restore_cals) { | 29114 | if (restore_cals) { |
29115 | regval[0] = (uint16) iqcomp_a; | 29115 | regval[0] = (u16) iqcomp_a; |
29116 | regval[1] = (uint16) iqcomp_b; | 29116 | regval[1] = (u16) iqcomp_b; |
29117 | wlc_phy_table_write_nphy(pi, 15, 2, | 29117 | wlc_phy_table_write_nphy(pi, 15, 2, |
29118 | (80 + 2 * core), 16, | 29118 | (80 + 2 * core), 16, |
29119 | regval); | 29119 | regval); |
@@ -29190,7 +29190,7 @@ wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan, u8 *max_pwr, | |||
29190 | 29190 | ||
29191 | void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable) | 29191 | void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable) |
29192 | { | 29192 | { |
29193 | uint16 clip_off[] = { 0xffff, 0xffff }; | 29193 | u16 clip_off[] = { 0xffff, 0xffff }; |
29194 | 29194 | ||
29195 | ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)); | 29195 | ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)); |
29196 | 29196 | ||
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c index 836564559d0..970a00cfe4f 100644 --- a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c +++ b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c | |||
@@ -217,7 +217,7 @@ const uint32 dot11lcn_gain_tbl_rev1[] = { | |||
217 | 0x00000000, | 217 | 0x00000000, |
218 | }; | 218 | }; |
219 | 219 | ||
220 | const uint16 dot11lcn_aux_gain_idx_tbl_rev0[] = { | 220 | const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = { |
221 | 0x0401, | 221 | 0x0401, |
222 | 0x0402, | 222 | 0x0402, |
223 | 0x0403, | 223 | 0x0403, |
@@ -409,7 +409,7 @@ const uint32 dot11lcn_gain_idx_tbl_rev0[] = { | |||
409 | 0x0000001c, | 409 | 0x0000001c, |
410 | }; | 410 | }; |
411 | 411 | ||
412 | const uint16 dot11lcn_aux_gain_idx_tbl_2G[] = { | 412 | const u16 dot11lcn_aux_gain_idx_tbl_2G[] = { |
413 | 0x0000, | 413 | 0x0000, |
414 | 0x0000, | 414 | 0x0000, |
415 | 0x0000, | 415 | 0x0000, |
@@ -874,7 +874,7 @@ const uint32 dot11lcn_gain_tbl_extlna_2G[] = { | |||
874 | 0x00000000 | 874 | 0x00000000 |
875 | }; | 875 | }; |
876 | 876 | ||
877 | const uint16 dot11lcn_aux_gain_idx_tbl_extlna_2G[] = { | 877 | const u16 dot11lcn_aux_gain_idx_tbl_extlna_2G[] = { |
878 | 0x0400, | 878 | 0x0400, |
879 | 0x0400, | 879 | 0x0400, |
880 | 0x0400, | 880 | 0x0400, |
@@ -1625,7 +1625,7 @@ const uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz = | |||
1625 | sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) / | 1625 | sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) / |
1626 | sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]); | 1626 | sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]); |
1627 | 1627 | ||
1628 | const uint16 dot11lcn_min_sig_sq_tbl_rev0[] = { | 1628 | const u16 dot11lcn_min_sig_sq_tbl_rev0[] = { |
1629 | 0x014d, | 1629 | 0x014d, |
1630 | 0x014d, | 1630 | 0x014d, |
1631 | 0x014d, | 1631 | 0x014d, |
@@ -1692,7 +1692,7 @@ const uint16 dot11lcn_min_sig_sq_tbl_rev0[] = { | |||
1692 | 0x014d, | 1692 | 0x014d, |
1693 | }; | 1693 | }; |
1694 | 1694 | ||
1695 | const uint16 dot11lcn_noise_scale_tbl_rev0[] = { | 1695 | const u16 dot11lcn_noise_scale_tbl_rev0[] = { |
1696 | 0x0000, | 1696 | 0x0000, |
1697 | 0x0000, | 1697 | 0x0000, |
1698 | 0x0000, | 1698 | 0x0000, |
@@ -1795,7 +1795,7 @@ const uint32 dot11lcn_ps_ctrl_tbl_rev0[] = { | |||
1795 | 0x00600f22, | 1795 | 0x00600f22, |
1796 | }; | 1796 | }; |
1797 | 1797 | ||
1798 | const uint16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[] = { | 1798 | const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[] = { |
1799 | 0x0007, | 1799 | 0x0007, |
1800 | 0x0005, | 1800 | 0x0005, |
1801 | 0x0006, | 1801 | 0x0006, |
@@ -1863,7 +1863,7 @@ const uint16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[] = { | |||
1863 | 1863 | ||
1864 | }; | 1864 | }; |
1865 | 1865 | ||
1866 | const uint16 dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[] = { | 1866 | const u16 dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[] = { |
1867 | 0x0007, | 1867 | 0x0007, |
1868 | 0x0005, | 1868 | 0x0005, |
1869 | 0x0002, | 1869 | 0x0002, |
@@ -1930,7 +1930,7 @@ const uint16 dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[] = { | |||
1930 | 0x0002, | 1930 | 0x0002, |
1931 | }; | 1931 | }; |
1932 | 1932 | ||
1933 | const uint16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = { | 1933 | const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = { |
1934 | 0x0002, | 1934 | 0x0002, |
1935 | 0x0008, | 1935 | 0x0008, |
1936 | 0x0004, | 1936 | 0x0004, |
@@ -1997,7 +1997,7 @@ const uint16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = { | |||
1997 | 0x0001, | 1997 | 0x0001, |
1998 | }; | 1998 | }; |
1999 | 1999 | ||
2000 | const uint16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = { | 2000 | const u16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = { |
2001 | 0x000a, | 2001 | 0x000a, |
2002 | 0x0009, | 2002 | 0x0009, |
2003 | 0x0006, | 2003 | 0x0006, |
@@ -2064,7 +2064,7 @@ const uint16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = { | |||
2064 | 0x0005, | 2064 | 0x0005, |
2065 | }; | 2065 | }; |
2066 | 2066 | ||
2067 | const uint16 dot11lcn_sw_ctrl_tbl_rev0[] = { | 2067 | const u16 dot11lcn_sw_ctrl_tbl_rev0[] = { |
2068 | 0x0004, | 2068 | 0x0004, |
2069 | 0x0004, | 2069 | 0x0004, |
2070 | 0x0002, | 2070 | 0x0002, |
@@ -2344,7 +2344,7 @@ const u8 dot11lcn_spur_tbl_rev0[] = { | |||
2344 | 0x01, | 2344 | 0x01, |
2345 | }; | 2345 | }; |
2346 | 2346 | ||
2347 | const uint16 dot11lcn_unsup_mcs_tbl_rev0[] = { | 2347 | const u16 dot11lcn_unsup_mcs_tbl_rev0[] = { |
2348 | 0x001a, | 2348 | 0x001a, |
2349 | 0x0034, | 2349 | 0x0034, |
2350 | 0x004e, | 2350 | 0x004e, |
@@ -2501,7 +2501,7 @@ const uint16 dot11lcn_unsup_mcs_tbl_rev0[] = { | |||
2501 | 0x06f6, | 2501 | 0x06f6, |
2502 | }; | 2502 | }; |
2503 | 2503 | ||
2504 | const uint16 dot11lcn_iq_local_tbl_rev0[] = { | 2504 | const u16 dot11lcn_iq_local_tbl_rev0[] = { |
2505 | 0x0200, | 2505 | 0x0200, |
2506 | 0x0300, | 2506 | 0x0300, |
2507 | 0x0400, | 2507 | 0x0400, |
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_n.c b/drivers/staging/brcm80211/phy/wlc_phytbl_n.c index 2d5bc461a32..303b4acc2de 100644 --- a/drivers/staging/brcm80211/phy/wlc_phytbl_n.c +++ b/drivers/staging/brcm80211/phy/wlc_phytbl_n.c | |||
@@ -2057,7 +2057,7 @@ const uint32 intlv_tbl_rev0[] = { | |||
2057 | 0x00000070, | 2057 | 0x00000070, |
2058 | }; | 2058 | }; |
2059 | 2059 | ||
2060 | const uint16 pilot_tbl_rev0[] = { | 2060 | const u16 pilot_tbl_rev0[] = { |
2061 | 0xff08, | 2061 | 0xff08, |
2062 | 0xff08, | 2062 | 0xff08, |
2063 | 0xff08, | 2063 | 0xff08, |
@@ -2499,7 +2499,7 @@ const uint32 tdi_tbl40_ant1_rev0[] = { | |||
2499 | 0x00000000, | 2499 | 0x00000000, |
2500 | }; | 2500 | }; |
2501 | 2501 | ||
2502 | const uint16 bdi_tbl_rev0[] = { | 2502 | const u16 bdi_tbl_rev0[] = { |
2503 | 0x0070, | 2503 | 0x0070, |
2504 | 0x0126, | 2504 | 0x0126, |
2505 | 0x012c, | 2505 | 0x012c, |
@@ -4176,7 +4176,7 @@ const uint32 iq_lut_core1_rev0[] = { | |||
4176 | 0x0000007f, | 4176 | 0x0000007f, |
4177 | }; | 4177 | }; |
4178 | 4178 | ||
4179 | const uint16 loft_lut_core0_rev0[] = { | 4179 | const u16 loft_lut_core0_rev0[] = { |
4180 | 0x0000, | 4180 | 0x0000, |
4181 | 0x0101, | 4181 | 0x0101, |
4182 | 0x0002, | 4182 | 0x0002, |
@@ -4307,7 +4307,7 @@ const uint16 loft_lut_core0_rev0[] = { | |||
4307 | 0x0103, | 4307 | 0x0103, |
4308 | }; | 4308 | }; |
4309 | 4309 | ||
4310 | const uint16 loft_lut_core1_rev0[] = { | 4310 | const u16 loft_lut_core1_rev0[] = { |
4311 | 0x0000, | 4311 | 0x0000, |
4312 | 0x0101, | 4312 | 0x0101, |
4313 | 0x0002, | 4313 | 0x0002, |
@@ -4542,7 +4542,7 @@ const uint32 mimophytbl_info_sz_rev0_volatile = | |||
4542 | sizeof(mimophytbl_info_rev0_volatile) / | 4542 | sizeof(mimophytbl_info_rev0_volatile) / |
4543 | sizeof(mimophytbl_info_rev0_volatile[0]); | 4543 | sizeof(mimophytbl_info_rev0_volatile[0]); |
4544 | 4544 | ||
4545 | const uint16 ant_swctrl_tbl_rev3[] = { | 4545 | const u16 ant_swctrl_tbl_rev3[] = { |
4546 | 0x0082, | 4546 | 0x0082, |
4547 | 0x0082, | 4547 | 0x0082, |
4548 | 0x0211, | 4548 | 0x0211, |
@@ -4577,7 +4577,7 @@ const uint16 ant_swctrl_tbl_rev3[] = { | |||
4577 | 0x0000, | 4577 | 0x0000, |
4578 | }; | 4578 | }; |
4579 | 4579 | ||
4580 | const uint16 ant_swctrl_tbl_rev3_1[] = { | 4580 | const u16 ant_swctrl_tbl_rev3_1[] = { |
4581 | 0x0022, | 4581 | 0x0022, |
4582 | 0x0022, | 4582 | 0x0022, |
4583 | 0x0011, | 4583 | 0x0011, |
@@ -4612,7 +4612,7 @@ const uint16 ant_swctrl_tbl_rev3_1[] = { | |||
4612 | 0x0000, | 4612 | 0x0000, |
4613 | }; | 4613 | }; |
4614 | 4614 | ||
4615 | const uint16 ant_swctrl_tbl_rev3_2[] = { | 4615 | const u16 ant_swctrl_tbl_rev3_2[] = { |
4616 | 0x0088, | 4616 | 0x0088, |
4617 | 0x0088, | 4617 | 0x0088, |
4618 | 0x0044, | 4618 | 0x0044, |
@@ -4647,7 +4647,7 @@ const uint16 ant_swctrl_tbl_rev3_2[] = { | |||
4647 | 0x0000, | 4647 | 0x0000, |
4648 | }; | 4648 | }; |
4649 | 4649 | ||
4650 | const uint16 ant_swctrl_tbl_rev3_3[] = { | 4650 | const u16 ant_swctrl_tbl_rev3_3[] = { |
4651 | 0x022, | 4651 | 0x022, |
4652 | 0x022, | 4652 | 0x022, |
4653 | 0x011, | 4653 | 0x011, |
@@ -5517,7 +5517,7 @@ const uint32 frame_struct_rev3[] = { | |||
5517 | 0x00000000, | 5517 | 0x00000000, |
5518 | }; | 5518 | }; |
5519 | 5519 | ||
5520 | const uint16 pilot_tbl_rev3[] = { | 5520 | const u16 pilot_tbl_rev3[] = { |
5521 | 0xff08, | 5521 | 0xff08, |
5522 | 0xff08, | 5522 | 0xff08, |
5523 | 0xff08, | 5523 | 0xff08, |
@@ -7035,7 +7035,7 @@ const uint32 noise_var_tbl_rev3[] = { | |||
7035 | 0x0000014d, | 7035 | 0x0000014d, |
7036 | }; | 7036 | }; |
7037 | 7037 | ||
7038 | const uint16 mcs_tbl_rev3[] = { | 7038 | const u16 mcs_tbl_rev3[] = { |
7039 | 0x0000, | 7039 | 0x0000, |
7040 | 0x0008, | 7040 | 0x0008, |
7041 | 0x000a, | 7041 | 0x000a, |
@@ -8571,7 +8571,7 @@ const uint32 iq_lut_core1_rev3[] = { | |||
8571 | 0x00000000, | 8571 | 0x00000000, |
8572 | }; | 8572 | }; |
8573 | 8573 | ||
8574 | const uint16 loft_lut_core0_rev3[] = { | 8574 | const u16 loft_lut_core0_rev3[] = { |
8575 | 0x0000, | 8575 | 0x0000, |
8576 | 0x0000, | 8576 | 0x0000, |
8577 | 0x0000, | 8577 | 0x0000, |
@@ -8702,7 +8702,7 @@ const uint16 loft_lut_core0_rev3[] = { | |||
8702 | 0x0000, | 8702 | 0x0000, |
8703 | }; | 8703 | }; |
8704 | 8704 | ||
8705 | const uint16 loft_lut_core1_rev3[] = { | 8705 | const u16 loft_lut_core1_rev3[] = { |
8706 | 0x0000, | 8706 | 0x0000, |
8707 | 0x0000, | 8707 | 0x0000, |
8708 | 0x0000, | 8708 | 0x0000, |
@@ -8833,7 +8833,7 @@ const uint16 loft_lut_core1_rev3[] = { | |||
8833 | 0x0000, | 8833 | 0x0000, |
8834 | }; | 8834 | }; |
8835 | 8835 | ||
8836 | const uint16 papd_comp_rfpwr_tbl_core0_rev3[] = { | 8836 | const u16 papd_comp_rfpwr_tbl_core0_rev3[] = { |
8837 | 0x0036, | 8837 | 0x0036, |
8838 | 0x0036, | 8838 | 0x0036, |
8839 | 0x0036, | 8839 | 0x0036, |
@@ -8964,7 +8964,7 @@ const uint16 papd_comp_rfpwr_tbl_core0_rev3[] = { | |||
8964 | 0x01d6, | 8964 | 0x01d6, |
8965 | }; | 8965 | }; |
8966 | 8966 | ||
8967 | const uint16 papd_comp_rfpwr_tbl_core1_rev3[] = { | 8967 | const u16 papd_comp_rfpwr_tbl_core1_rev3[] = { |
8968 | 0x0036, | 8968 | 0x0036, |
8969 | 0x0036, | 8969 | 0x0036, |
8970 | 0x0036, | 8970 | 0x0036, |
diff --git a/drivers/staging/brcm80211/sys/wl_mac80211.c b/drivers/staging/brcm80211/sys/wl_mac80211.c index 7c07808a712..d7094e06795 100644 --- a/drivers/staging/brcm80211/sys/wl_mac80211.c +++ b/drivers/staging/brcm80211/sys/wl_mac80211.c | |||
@@ -765,7 +765,7 @@ static int wl_set_hint(wl_info_t *wl, char *abbrev) | |||
765 | * a warning that this function is defined but not used if we declare | 765 | * a warning that this function is defined but not used if we declare |
766 | * it as static. | 766 | * it as static. |
767 | */ | 767 | */ |
768 | static wl_info_t *wl_attach(uint16 vendor, uint16 device, unsigned long regs, | 768 | static wl_info_t *wl_attach(u16 vendor, u16 device, unsigned long regs, |
769 | uint bustype, void *btparam, uint irq) | 769 | uint bustype, void *btparam, uint irq) |
770 | { | 770 | { |
771 | wl_info_t *wl; | 771 | wl_info_t *wl; |
diff --git a/drivers/staging/brcm80211/sys/wl_ucode.h b/drivers/staging/brcm80211/sys/wl_ucode.h index 2763b7cd365..7499cf523e2 100644 --- a/drivers/staging/brcm80211/sys/wl_ucode.h +++ b/drivers/staging/brcm80211/sys/wl_ucode.h | |||
@@ -16,8 +16,8 @@ | |||
16 | 16 | ||
17 | #include <typedefs.h> | 17 | #include <typedefs.h> |
18 | typedef struct d11init { | 18 | typedef struct d11init { |
19 | uint16 addr; | 19 | u16 addr; |
20 | uint16 size; | 20 | u16 size; |
21 | uint32 value; | 21 | uint32 value; |
22 | } d11init_t; | 22 | } d11init_t; |
23 | 23 | ||
diff --git a/drivers/staging/brcm80211/sys/wlc_ampdu.c b/drivers/staging/brcm80211/sys/wlc_ampdu.c index 1d68400bc6d..7fd7a0adb07 100644 --- a/drivers/staging/brcm80211/sys/wlc_ampdu.c +++ b/drivers/staging/brcm80211/sys/wlc_ampdu.c | |||
@@ -90,9 +90,9 @@ uint32 wl_ampdu_dbg = | |||
90 | * how often and/or when the wlc counters are updated. | 90 | * how often and/or when the wlc counters are updated. |
91 | */ | 91 | */ |
92 | typedef struct wlc_fifo_info { | 92 | typedef struct wlc_fifo_info { |
93 | uint16 ampdu_pld_size; /* number of bytes to be pre-loaded */ | 93 | u16 ampdu_pld_size; /* number of bytes to be pre-loaded */ |
94 | u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1]; /* per-mcs max # of mpdus in an ampdu */ | 94 | u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1]; /* per-mcs max # of mpdus in an ampdu */ |
95 | uint16 prev_txfunfl; /* num of underflows last read from the HW macstats counter */ | 95 | u16 prev_txfunfl; /* num of underflows last read from the HW macstats counter */ |
96 | uint32 accum_txfunfl; /* num of underflows since we modified pld params */ | 96 | uint32 accum_txfunfl; /* num of underflows since we modified pld params */ |
97 | uint32 accum_txampdu; /* num of tx ampdu since we modified pld params */ | 97 | uint32 accum_txampdu; /* num of tx ampdu since we modified pld params */ |
98 | uint32 prev_txampdu; /* previous reading of tx ampdu */ | 98 | uint32 prev_txampdu; /* previous reading of tx ampdu */ |
@@ -158,7 +158,7 @@ static void wlc_ampdu_dotxstatus_complete(ampdu_info_t *ampdu, struct scb *scb, | |||
158 | uint32 frmtxstatus, | 158 | uint32 frmtxstatus, |
159 | uint32 frmtxstatus2); | 159 | uint32 frmtxstatus2); |
160 | 160 | ||
161 | static inline uint16 pkt_txh_seqnum(wlc_info_t *wlc, void *p) | 161 | static inline u16 pkt_txh_seqnum(wlc_info_t *wlc, void *p) |
162 | { | 162 | { |
163 | d11txh_t *txh; | 163 | d11txh_t *txh; |
164 | struct dot11_header *h; | 164 | struct dot11_header *h; |
@@ -173,7 +173,7 @@ ampdu_info_t *BCMATTACHFN(wlc_ampdu_attach) (wlc_info_t *wlc) | |||
173 | int i; | 173 | int i; |
174 | 174 | ||
175 | /* some code depends on packed structures */ | 175 | /* some code depends on packed structures */ |
176 | ASSERT(DOT11_MAXNUMFRAGS == NBITS(uint16)); | 176 | ASSERT(DOT11_MAXNUMFRAGS == NBITS(u16)); |
177 | ASSERT(ISPOWEROF2(AMPDU_TX_BA_MAX_WSIZE)); | 177 | ASSERT(ISPOWEROF2(AMPDU_TX_BA_MAX_WSIZE)); |
178 | ASSERT(ISPOWEROF2(AMPDU_RX_BA_MAX_WSIZE)); | 178 | ASSERT(ISPOWEROF2(AMPDU_RX_BA_MAX_WSIZE)); |
179 | ASSERT(wlc->pub->tunables->ampdunummpdu <= AMPDU_MAX_MPDU); | 179 | ASSERT(wlc->pub->tunables->ampdunummpdu <= AMPDU_MAX_MPDU); |
@@ -339,17 +339,17 @@ static int wlc_ffpld_check_txfunfl(wlc_info_t *wlc, int fid) | |||
339 | uint32 txunfl_ratio; | 339 | uint32 txunfl_ratio; |
340 | u8 max_mpdu; | 340 | u8 max_mpdu; |
341 | uint32 current_ampdu_cnt = 0; | 341 | uint32 current_ampdu_cnt = 0; |
342 | uint16 max_pld_size; | 342 | u16 max_pld_size; |
343 | uint32 new_txunfl; | 343 | uint32 new_txunfl; |
344 | wlc_fifo_info_t *fifo = (ampdu->fifo_tb + fid); | 344 | wlc_fifo_info_t *fifo = (ampdu->fifo_tb + fid); |
345 | uint xmtfifo_sz; | 345 | uint xmtfifo_sz; |
346 | uint16 cur_txunfl; | 346 | u16 cur_txunfl; |
347 | 347 | ||
348 | /* return if we got here for a different reason than underflows */ | 348 | /* return if we got here for a different reason than underflows */ |
349 | cur_txunfl = | 349 | cur_txunfl = |
350 | wlc_read_shm(wlc, | 350 | wlc_read_shm(wlc, |
351 | M_UCODE_MACSTAT + OFFSETOF(macstat_t, txfunfl[fid])); | 351 | M_UCODE_MACSTAT + OFFSETOF(macstat_t, txfunfl[fid])); |
352 | new_txunfl = (uint16) (cur_txunfl - fifo->prev_txfunfl); | 352 | new_txunfl = (u16) (cur_txunfl - fifo->prev_txfunfl); |
353 | if (new_txunfl == 0) { | 353 | if (new_txunfl == 0) { |
354 | WL_FFPLD(("check_txunfl : TX status FRAG set but no tx underflows\n")); | 354 | WL_FFPLD(("check_txunfl : TX status FRAG set but no tx underflows\n")); |
355 | return -1; | 355 | return -1; |
@@ -516,7 +516,7 @@ wlc_sendampdu(ampdu_info_t *ampdu, wlc_txq_info_t *qi, void **pdu, int prec) | |||
516 | 516 | ||
517 | bool rr = TRUE, fbr = FALSE; | 517 | bool rr = TRUE, fbr = FALSE; |
518 | uint i, count = 0, fifo, seg_cnt = 0; | 518 | uint i, count = 0, fifo, seg_cnt = 0; |
519 | uint16 plen, len, seq = 0, mcl, mch, index, frameid, dma_len = 0; | 519 | u16 plen, len, seq = 0, mcl, mch, index, frameid, dma_len = 0; |
520 | uint32 ampdu_len, maxlen = 0; | 520 | uint32 ampdu_len, maxlen = 0; |
521 | d11txh_t *txh = NULL; | 521 | d11txh_t *txh = NULL; |
522 | u8 *plcp; | 522 | u8 *plcp; |
@@ -528,13 +528,13 @@ wlc_sendampdu(ampdu_info_t *ampdu, wlc_txq_info_t *qi, void **pdu, int prec) | |||
528 | bool use_rts = FALSE, use_cts = FALSE; | 528 | bool use_rts = FALSE, use_cts = FALSE; |
529 | ratespec_t rspec = 0, rspec_fallback = 0; | 529 | ratespec_t rspec = 0, rspec_fallback = 0; |
530 | ratespec_t rts_rspec = 0, rts_rspec_fallback = 0; | 530 | ratespec_t rts_rspec = 0, rts_rspec_fallback = 0; |
531 | uint16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; | 531 | u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; |
532 | struct dot11_rts_frame *rts; | 532 | struct dot11_rts_frame *rts; |
533 | u8 rr_retry_limit; | 533 | u8 rr_retry_limit; |
534 | wlc_fifo_info_t *f; | 534 | wlc_fifo_info_t *f; |
535 | bool fbr_iscck; | 535 | bool fbr_iscck; |
536 | struct ieee80211_tx_info *tx_info; | 536 | struct ieee80211_tx_info *tx_info; |
537 | uint16 qlen; | 537 | u16 qlen; |
538 | 538 | ||
539 | wlc = ampdu->wlc; | 539 | wlc = ampdu->wlc; |
540 | osh = wlc->osh; | 540 | osh = wlc->osh; |
@@ -643,7 +643,7 @@ wlc_sendampdu(ampdu_info_t *ampdu, wlc_txq_info_t *qi, void **pdu, int prec) | |||
643 | * test whether need to break or change the epoch | 643 | * test whether need to break or change the epoch |
644 | */ | 644 | */ |
645 | if (count == 0) { | 645 | if (count == 0) { |
646 | uint16 fc; | 646 | u16 fc; |
647 | mcl |= (TXC_AMPDU_FIRST << TXC_AMPDU_SHIFT); | 647 | mcl |= (TXC_AMPDU_FIRST << TXC_AMPDU_SHIFT); |
648 | /* refill the bits since might be a retx mpdu */ | 648 | /* refill the bits since might be a retx mpdu */ |
649 | mcl |= TXC_STARTMSDU; | 649 | mcl |= TXC_STARTMSDU; |
@@ -665,7 +665,7 @@ wlc_sendampdu(ampdu_info_t *ampdu, wlc_txq_info_t *qi, void **pdu, int prec) | |||
665 | len = ROUNDUP(len, 4); | 665 | len = ROUNDUP(len, 4); |
666 | ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN); | 666 | ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN); |
667 | 667 | ||
668 | dma_len += (uint16) pkttotlen(osh, p); | 668 | dma_len += (u16) pkttotlen(osh, p); |
669 | 669 | ||
670 | WL_AMPDU_TX(("wl%d: wlc_sendampdu: ampdu_len %d seg_cnt %d null delim %d\n", wlc->pub->unit, ampdu_len, seg_cnt, ndelim)); | 670 | WL_AMPDU_TX(("wl%d: wlc_sendampdu: ampdu_len %d seg_cnt %d null delim %d\n", wlc->pub->unit, ampdu_len, seg_cnt, ndelim)); |
671 | 671 | ||
@@ -818,13 +818,13 @@ wlc_sendampdu(ampdu_info_t *ampdu, wlc_txq_info_t *qi, void **pdu, int prec) | |||
818 | 818 | ||
819 | /* reset the mixed mode header durations */ | 819 | /* reset the mixed mode header durations */ |
820 | if (txh->MModeLen) { | 820 | if (txh->MModeLen) { |
821 | uint16 mmodelen = | 821 | u16 mmodelen = |
822 | wlc_calc_lsig_len(wlc, rspec, ampdu_len); | 822 | wlc_calc_lsig_len(wlc, rspec, ampdu_len); |
823 | txh->MModeLen = htol16(mmodelen); | 823 | txh->MModeLen = htol16(mmodelen); |
824 | preamble_type = WLC_MM_PREAMBLE; | 824 | preamble_type = WLC_MM_PREAMBLE; |
825 | } | 825 | } |
826 | if (txh->MModeFbrLen) { | 826 | if (txh->MModeFbrLen) { |
827 | uint16 mmfbrlen = | 827 | u16 mmfbrlen = |
828 | wlc_calc_lsig_len(wlc, rspec_fallback, ampdu_len); | 828 | wlc_calc_lsig_len(wlc, rspec_fallback, ampdu_len); |
829 | txh->MModeFbrLen = htol16(mmfbrlen); | 829 | txh->MModeFbrLen = htol16(mmfbrlen); |
830 | fbr_preamble_type = WLC_MM_PREAMBLE; | 830 | fbr_preamble_type = WLC_MM_PREAMBLE; |
@@ -841,7 +841,7 @@ wlc_sendampdu(ampdu_info_t *ampdu, wlc_txq_info_t *qi, void **pdu, int prec) | |||
841 | 841 | ||
842 | /* update RTS dur fields */ | 842 | /* update RTS dur fields */ |
843 | if (use_rts || use_cts) { | 843 | if (use_rts || use_cts) { |
844 | uint16 durid; | 844 | u16 durid; |
845 | rts = (struct dot11_rts_frame *)&txh->rts_frame; | 845 | rts = (struct dot11_rts_frame *)&txh->rts_frame; |
846 | if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) == | 846 | if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) == |
847 | TXC_PREAMBLE_RTS_MAIN_SHORT) | 847 | TXC_PREAMBLE_RTS_MAIN_SHORT) |
@@ -1026,13 +1026,13 @@ wlc_ampdu_dotxstatus_complete(ampdu_info_t *ampdu, struct scb *scb, void *p, | |||
1026 | d11txh_t *txh; | 1026 | d11txh_t *txh; |
1027 | u8 *plcp; | 1027 | u8 *plcp; |
1028 | struct dot11_header *h; | 1028 | struct dot11_header *h; |
1029 | uint16 seq, start_seq = 0, bindex, index, mcl; | 1029 | u16 seq, start_seq = 0, bindex, index, mcl; |
1030 | u8 mcs = 0; | 1030 | u8 mcs = 0; |
1031 | bool ba_recd = FALSE, ack_recd = FALSE; | 1031 | bool ba_recd = FALSE, ack_recd = FALSE; |
1032 | u8 suc_mpdu = 0, tot_mpdu = 0; | 1032 | u8 suc_mpdu = 0, tot_mpdu = 0; |
1033 | uint supr_status; | 1033 | uint supr_status; |
1034 | bool update_rate = TRUE, retry = TRUE, tx_error = FALSE; | 1034 | bool update_rate = TRUE, retry = TRUE, tx_error = FALSE; |
1035 | uint16 mimoantsel = 0; | 1035 | u16 mimoantsel = 0; |
1036 | u8 antselid = 0; | 1036 | u8 antselid = 0; |
1037 | u8 retry_limit, rr_retry_limit; | 1037 | u8 retry_limit, rr_retry_limit; |
1038 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p); | 1038 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p); |
diff --git a/drivers/staging/brcm80211/sys/wlc_antsel.c b/drivers/staging/brcm80211/sys/wlc_antsel.c index e36347bf551..3013c82179f 100644 --- a/drivers/staging/brcm80211/sys/wlc_antsel.c +++ b/drivers/staging/brcm80211/sys/wlc_antsel.c | |||
@@ -61,11 +61,11 @@ | |||
61 | /* static functions */ | 61 | /* static functions */ |
62 | static int wlc_antsel_cfgupd(antsel_info_t *asi, wlc_antselcfg_t *antsel); | 62 | static int wlc_antsel_cfgupd(antsel_info_t *asi, wlc_antselcfg_t *antsel); |
63 | static u8 wlc_antsel_id2antcfg(antsel_info_t *asi, u8 id); | 63 | static u8 wlc_antsel_id2antcfg(antsel_info_t *asi, u8 id); |
64 | static uint16 wlc_antsel_antcfg2antsel(antsel_info_t *asi, u8 ant_cfg); | 64 | static u16 wlc_antsel_antcfg2antsel(antsel_info_t *asi, u8 ant_cfg); |
65 | static void wlc_antsel_init_cfg(antsel_info_t *asi, wlc_antselcfg_t *antsel, | 65 | static void wlc_antsel_init_cfg(antsel_info_t *asi, wlc_antselcfg_t *antsel, |
66 | bool auto_sel); | 66 | bool auto_sel); |
67 | 67 | ||
68 | const uint16 mimo_2x4_div_antselpat_tbl[] = { | 68 | const u16 mimo_2x4_div_antselpat_tbl[] = { |
69 | 0, 0, 0x9, 0xa, /* ant0: 0 ant1: 2,3 */ | 69 | 0, 0, 0x9, 0xa, /* ant0: 0 ant1: 2,3 */ |
70 | 0, 0, 0x5, 0x6, /* ant0: 1 ant1: 2,3 */ | 70 | 0, 0, 0x5, 0x6, /* ant0: 1 ant1: 2,3 */ |
71 | 0, 0, 0, 0, /* n.a. */ | 71 | 0, 0, 0, 0, /* n.a. */ |
@@ -77,7 +77,7 @@ const u8 mimo_2x4_div_antselid_tbl[16] = { | |||
77 | 0, 0, 1, 0, 0, 0, 0, 0 /* pat to antselid */ | 77 | 0, 0, 1, 0, 0, 0, 0, 0 /* pat to antselid */ |
78 | }; | 78 | }; |
79 | 79 | ||
80 | const uint16 mimo_2x3_div_antselpat_tbl[] = { | 80 | const u16 mimo_2x3_div_antselpat_tbl[] = { |
81 | 16, 0, 1, 16, /* ant0: 0 ant1: 1,2 */ | 81 | 16, 0, 1, 16, /* ant0: 0 ant1: 1,2 */ |
82 | 16, 16, 16, 16, /* n.a. */ | 82 | 16, 16, 16, 16, /* n.a. */ |
83 | 16, 2, 16, 16, /* ant0: 2 ant1: 1 */ | 83 | 16, 2, 16, 16, /* ant0: 2 ant1: 1 */ |
@@ -116,13 +116,13 @@ antsel_info_t *BCMNMIATTACHFN(wlc_antsel_attach) (wlc_info_t *wlc, osl_t *osh, | |||
116 | /* 4321/2 board with 2x3 switch logic */ | 116 | /* 4321/2 board with 2x3 switch logic */ |
117 | asi->antsel_type = ANTSEL_2x3; | 117 | asi->antsel_type = ANTSEL_2x3; |
118 | /* Antenna selection availability */ | 118 | /* Antenna selection availability */ |
119 | if (((uint16) getintvar(asi->pub->vars, "aa2g") == 7) || | 119 | if (((u16) getintvar(asi->pub->vars, "aa2g") == 7) || |
120 | ((uint16) getintvar(asi->pub->vars, "aa5g") == 7)) { | 120 | ((u16) getintvar(asi->pub->vars, "aa5g") == 7)) { |
121 | asi->antsel_avail = TRUE; | 121 | asi->antsel_avail = TRUE; |
122 | } else | 122 | } else |
123 | if (((uint16) getintvar(asi->pub->vars, "aa2g") == | 123 | if (((u16) getintvar(asi->pub->vars, "aa2g") == |
124 | 3) | 124 | 3) |
125 | || ((uint16) getintvar(asi->pub->vars, "aa5g") | 125 | || ((u16) getintvar(asi->pub->vars, "aa5g") |
126 | == 3)) { | 126 | == 3)) { |
127 | asi->antsel_avail = FALSE; | 127 | asi->antsel_avail = FALSE; |
128 | } else { | 128 | } else { |
@@ -135,8 +135,8 @@ antsel_info_t *BCMNMIATTACHFN(wlc_antsel_attach) (wlc_info_t *wlc, osl_t *osh, | |||
135 | break; | 135 | break; |
136 | } | 136 | } |
137 | } else if ((asi->pub->sromrev == 4) && | 137 | } else if ((asi->pub->sromrev == 4) && |
138 | ((uint16) getintvar(asi->pub->vars, "aa2g") == 7) && | 138 | ((u16) getintvar(asi->pub->vars, "aa2g") == 7) && |
139 | ((uint16) getintvar(asi->pub->vars, "aa5g") == 0)) { | 139 | ((u16) getintvar(asi->pub->vars, "aa5g") == 0)) { |
140 | /* hack to match old 4321CB2 cards with 2of3 antenna switch */ | 140 | /* hack to match old 4321CB2 cards with 2of3 antenna switch */ |
141 | asi->antsel_type = ANTSEL_2x3; | 141 | asi->antsel_type = ANTSEL_2x3; |
142 | asi->antsel_avail = TRUE; | 142 | asi->antsel_avail = TRUE; |
@@ -235,7 +235,7 @@ wlc_antsel_antcfg_get(antsel_info_t *asi, bool usedef, bool sel, | |||
235 | } | 235 | } |
236 | 236 | ||
237 | /* boardlevel antenna selection: convert mimo_antsel (ucode interface) to id */ | 237 | /* boardlevel antenna selection: convert mimo_antsel (ucode interface) to id */ |
238 | u8 wlc_antsel_antsel2id(antsel_info_t *asi, uint16 antsel) | 238 | u8 wlc_antsel_antsel2id(antsel_info_t *asi, u16 antsel) |
239 | { | 239 | { |
240 | u8 antselid = 0; | 240 | u8 antselid = 0; |
241 | 241 | ||
@@ -273,10 +273,10 @@ static u8 wlc_antsel_id2antcfg(antsel_info_t *asi, u8 id) | |||
273 | } | 273 | } |
274 | 274 | ||
275 | /* boardlevel antenna selection: convert ant_cfg to mimo_antsel (ucode interface) */ | 275 | /* boardlevel antenna selection: convert ant_cfg to mimo_antsel (ucode interface) */ |
276 | static uint16 wlc_antsel_antcfg2antsel(antsel_info_t *asi, u8 ant_cfg) | 276 | static u16 wlc_antsel_antcfg2antsel(antsel_info_t *asi, u8 ant_cfg) |
277 | { | 277 | { |
278 | u8 idx = WLC_ANTIDX_11N(WLC_ANTSEL_11N(ant_cfg)); | 278 | u8 idx = WLC_ANTIDX_11N(WLC_ANTSEL_11N(ant_cfg)); |
279 | uint16 mimo_antsel = 0; | 279 | u16 mimo_antsel = 0; |
280 | 280 | ||
281 | if (asi->antsel_type == ANTSEL_2x4) { | 281 | if (asi->antsel_type == ANTSEL_2x4) { |
282 | /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */ | 282 | /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */ |
@@ -297,7 +297,7 @@ static int wlc_antsel_cfgupd(antsel_info_t *asi, wlc_antselcfg_t *antsel) | |||
297 | { | 297 | { |
298 | wlc_info_t *wlc = asi->wlc; | 298 | wlc_info_t *wlc = asi->wlc; |
299 | u8 ant_cfg; | 299 | u8 ant_cfg; |
300 | uint16 mimo_antsel; | 300 | u16 mimo_antsel; |
301 | 301 | ||
302 | ASSERT(asi->antsel_type != ANTSEL_NA); | 302 | ASSERT(asi->antsel_type != ANTSEL_NA); |
303 | 303 | ||
diff --git a/drivers/staging/brcm80211/sys/wlc_antsel.h b/drivers/staging/brcm80211/sys/wlc_antsel.h index fea6f105b15..1d048bbea94 100644 --- a/drivers/staging/brcm80211/sys/wlc_antsel.h +++ b/drivers/staging/brcm80211/sys/wlc_antsel.h | |||
@@ -24,5 +24,5 @@ extern void wlc_antsel_init(antsel_info_t *asi); | |||
24 | extern void wlc_antsel_antcfg_get(antsel_info_t *asi, bool usedef, bool sel, | 24 | extern void wlc_antsel_antcfg_get(antsel_info_t *asi, bool usedef, bool sel, |
25 | u8 id, u8 fbid, u8 *antcfg, | 25 | u8 id, u8 fbid, u8 *antcfg, |
26 | u8 *fbantcfg); | 26 | u8 *fbantcfg); |
27 | extern u8 wlc_antsel_antsel2id(antsel_info_t *asi, uint16 antsel); | 27 | extern u8 wlc_antsel_antsel2id(antsel_info_t *asi, u16 antsel); |
28 | #endif /* _wlc_antsel_h_ */ | 28 | #endif /* _wlc_antsel_h_ */ |
diff --git a/drivers/staging/brcm80211/sys/wlc_bmac.c b/drivers/staging/brcm80211/sys/wlc_bmac.c index ad39cc47bee..53ac604958f 100644 --- a/drivers/staging/brcm80211/sys/wlc_bmac.c +++ b/drivers/staging/brcm80211/sys/wlc_bmac.c | |||
@@ -106,7 +106,7 @@ | |||
106 | 106 | ||
107 | #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */ | 107 | #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */ |
108 | 108 | ||
109 | static uint16 xmtfifo_sz[][NFIFO] = { | 109 | static u16 xmtfifo_sz[][NFIFO] = { |
110 | {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */ | 110 | {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */ |
111 | {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */ | 111 | {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */ |
112 | {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */ | 112 | {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */ |
@@ -134,14 +134,14 @@ static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound); | |||
134 | /* used by wlc_down() */ | 134 | /* used by wlc_down() */ |
135 | static void wlc_flushqueues(wlc_info_t *wlc); | 135 | static void wlc_flushqueues(wlc_info_t *wlc); |
136 | 136 | ||
137 | static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, uint16 *mhfs); | 137 | static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs); |
138 | static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw); | 138 | static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw); |
139 | static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw); | 139 | static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw); |
140 | 140 | ||
141 | /* Low Level Prototypes */ | 141 | /* Low Level Prototypes */ |
142 | static uint16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, | 142 | static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, |
143 | uint32 sel); | 143 | uint32 sel); |
144 | static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, uint16 v, | 144 | static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, |
145 | uint32 sel); | 145 | uint32 sel); |
146 | static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme); | 146 | static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme); |
147 | static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw); | 147 | static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw); |
@@ -149,7 +149,7 @@ static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw); | |||
149 | static bool wlc_validboardtype(wlc_hw_info_t *wlc); | 149 | static bool wlc_validboardtype(wlc_hw_info_t *wlc); |
150 | static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw); | 150 | static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw); |
151 | static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw); | 151 | static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw); |
152 | static void wlc_mhfdef(wlc_info_t *wlc, uint16 *mhfs, uint16 mhf2_init); | 152 | static void wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init); |
153 | static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw); | 153 | static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw); |
154 | static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw); | 154 | static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw); |
155 | static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw); | 155 | static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw); |
@@ -166,7 +166,7 @@ static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit, | |||
166 | chanspec_t chanspec); | 166 | chanspec_t chanspec); |
167 | static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot); | 167 | static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot); |
168 | static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw); | 168 | static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw); |
169 | static uint16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, | 169 | static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, |
170 | u8 rate); | 170 | u8 rate); |
171 | 171 | ||
172 | /* === Low Level functions === */ | 172 | /* === Low Level functions === */ |
@@ -572,7 +572,7 @@ BCMATTACHFN(wlc_bmac_attach_dmapio) (wlc_info_t *wlc, uint j, bool wme) | |||
572 | uint i; | 572 | uint i; |
573 | char name[8]; | 573 | char name[8]; |
574 | /* ucode host flag 2 needed for pio mode, independent of band and fifo */ | 574 | /* ucode host flag 2 needed for pio mode, independent of band and fifo */ |
575 | uint16 pio_mhf2 = 0; | 575 | u16 pio_mhf2 = 0; |
576 | wlc_hw_info_t *wlc_hw = wlc->hw; | 576 | wlc_hw_info_t *wlc_hw = wlc->hw; |
577 | uint unit = wlc_hw->unit; | 577 | uint unit = wlc_hw->unit; |
578 | wlc_tunables_t *tune = wlc->pub->tunables; | 578 | wlc_tunables_t *tune = wlc->pub->tunables; |
@@ -706,7 +706,7 @@ static void BCMATTACHFN(wlc_bmac_detach_dmapio) (wlc_hw_info_t *wlc_hw) | |||
706 | */ | 706 | */ |
707 | 707 | ||
708 | int | 708 | int |
709 | BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, uint16 vendor, uint16 device, | 709 | BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, u16 vendor, u16 device, |
710 | uint unit, bool piomode, osl_t *osh, | 710 | uint unit, bool piomode, osl_t *osh, |
711 | void *regsva, uint bustype, void *btparam) { | 711 | void *regsva, uint bustype, void *btparam) { |
712 | wlc_hw_info_t *wlc_hw; | 712 | wlc_hw_info_t *wlc_hw; |
@@ -762,12 +762,12 @@ BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, uint16 vendor, uint16 device, | |||
762 | 762 | ||
763 | var = getvar(vars, "vendid"); | 763 | var = getvar(vars, "vendid"); |
764 | if (var) { | 764 | if (var) { |
765 | vendor = (uint16) simple_strtoul(var, NULL, 0); | 765 | vendor = (u16) simple_strtoul(var, NULL, 0); |
766 | WL_ERROR(("Overriding vendor id = 0x%x\n", vendor)); | 766 | WL_ERROR(("Overriding vendor id = 0x%x\n", vendor)); |
767 | } | 767 | } |
768 | var = getvar(vars, "devid"); | 768 | var = getvar(vars, "devid"); |
769 | if (var) { | 769 | if (var) { |
770 | uint16 devid = (uint16) simple_strtoul(var, NULL, 0); | 770 | u16 devid = (u16) simple_strtoul(var, NULL, 0); |
771 | if (devid != 0xffff) { | 771 | if (devid != 0xffff) { |
772 | device = devid; | 772 | device = devid; |
773 | WL_ERROR(("Overriding device id = 0x%x\n", | 773 | WL_ERROR(("Overriding device id = 0x%x\n", |
@@ -822,7 +822,7 @@ BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, uint16 vendor, uint16 device, | |||
822 | /* promote srom boardrev of 0xFF to 1 */ | 822 | /* promote srom boardrev of 0xFF to 1 */ |
823 | if (j == BOARDREV_PROMOTABLE) | 823 | if (j == BOARDREV_PROMOTABLE) |
824 | j = BOARDREV_PROMOTED; | 824 | j = BOARDREV_PROMOTED; |
825 | wlc_hw->boardrev = (uint16) j; | 825 | wlc_hw->boardrev = (u16) j; |
826 | if (!wlc_validboardtype(wlc_hw)) { | 826 | if (!wlc_validboardtype(wlc_hw)) { |
827 | WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev)); | 827 | WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev)); |
828 | err = 15; | 828 | err = 15; |
@@ -1458,11 +1458,11 @@ static void wlc_clkctl_clk(wlc_hw_info_t *wlc_hw, uint mode) | |||
1458 | 1458 | ||
1459 | /* set initial host flags value */ | 1459 | /* set initial host flags value */ |
1460 | static void | 1460 | static void |
1461 | BCMINITFN(wlc_mhfdef) (wlc_info_t *wlc, uint16 *mhfs, uint16 mhf2_init) | 1461 | BCMINITFN(wlc_mhfdef) (wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init) |
1462 | { | 1462 | { |
1463 | wlc_hw_info_t *wlc_hw = wlc->hw; | 1463 | wlc_hw_info_t *wlc_hw = wlc->hw; |
1464 | 1464 | ||
1465 | bzero(mhfs, sizeof(uint16) * MHFMAX); | 1465 | bzero(mhfs, sizeof(u16) * MHFMAX); |
1466 | 1466 | ||
1467 | mhfs[MHF2] |= mhf2_init; | 1467 | mhfs[MHF2] |= mhf2_init; |
1468 | 1468 | ||
@@ -1488,11 +1488,11 @@ BCMINITFN(wlc_mhfdef) (wlc_info_t *wlc, uint16 *mhfs, uint16 mhf2_init) | |||
1488 | * WLC_BAND_ALL <--- All bands | 1488 | * WLC_BAND_ALL <--- All bands |
1489 | */ | 1489 | */ |
1490 | void | 1490 | void |
1491 | wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, uint16 mask, uint16 val, | 1491 | wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, u16 val, |
1492 | int bands) | 1492 | int bands) |
1493 | { | 1493 | { |
1494 | uint16 save; | 1494 | u16 save; |
1495 | uint16 addr[MHFMAX] = { | 1495 | u16 addr[MHFMAX] = { |
1496 | M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, | 1496 | M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, |
1497 | M_HOST_FLAGS5 | 1497 | M_HOST_FLAGS5 |
1498 | }; | 1498 | }; |
@@ -1531,7 +1531,7 @@ wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, uint16 mask, uint16 val, | |||
1531 | if (wlc_hw->clk && (band->mhfs[idx] != save) | 1531 | if (wlc_hw->clk && (band->mhfs[idx] != save) |
1532 | && (band == wlc_hw->band)) | 1532 | && (band == wlc_hw->band)) |
1533 | wlc_bmac_write_shm(wlc_hw, addr[idx], | 1533 | wlc_bmac_write_shm(wlc_hw, addr[idx], |
1534 | (uint16) band->mhfs[idx]); | 1534 | (u16) band->mhfs[idx]); |
1535 | } | 1535 | } |
1536 | 1536 | ||
1537 | if (bands == WLC_BAND_ALL) { | 1537 | if (bands == WLC_BAND_ALL) { |
@@ -1542,7 +1542,7 @@ wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, uint16 mask, uint16 val, | |||
1542 | } | 1542 | } |
1543 | } | 1543 | } |
1544 | 1544 | ||
1545 | uint16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands) | 1545 | u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands) |
1546 | { | 1546 | { |
1547 | wlc_hwband_t *band; | 1547 | wlc_hwband_t *band; |
1548 | ASSERT(idx < MHFMAX); | 1548 | ASSERT(idx < MHFMAX); |
@@ -1568,10 +1568,10 @@ uint16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands) | |||
1568 | return band->mhfs[idx]; | 1568 | return band->mhfs[idx]; |
1569 | } | 1569 | } |
1570 | 1570 | ||
1571 | static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, uint16 *mhfs) | 1571 | static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs) |
1572 | { | 1572 | { |
1573 | u8 idx; | 1573 | u8 idx; |
1574 | uint16 addr[] = { | 1574 | u16 addr[] = { |
1575 | M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, | 1575 | M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, |
1576 | M_HOST_FLAGS5 | 1576 | M_HOST_FLAGS5 |
1577 | }; | 1577 | }; |
@@ -1714,10 +1714,10 @@ wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx, | |||
1714 | const struct ether_addr *addr) | 1714 | const struct ether_addr *addr) |
1715 | { | 1715 | { |
1716 | d11regs_t *regs = wlc_hw->regs; | 1716 | d11regs_t *regs = wlc_hw->regs; |
1717 | volatile uint16 *objdata16 = | 1717 | volatile u16 *objdata16 = |
1718 | (volatile uint16 *)(uintptr) & regs->objdata; | 1718 | (volatile u16 *)(uintptr) & regs->objdata; |
1719 | uint32 mac_hm; | 1719 | uint32 mac_hm; |
1720 | uint16 mac_l; | 1720 | u16 mac_l; |
1721 | osl_t *osh; | 1721 | osl_t *osh; |
1722 | 1722 | ||
1723 | WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__)); | 1723 | WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__)); |
@@ -1748,9 +1748,9 @@ wlc_bmac_set_addrmatch(wlc_hw_info_t *wlc_hw, int match_reg_offset, | |||
1748 | const struct ether_addr *addr) | 1748 | const struct ether_addr *addr) |
1749 | { | 1749 | { |
1750 | d11regs_t *regs; | 1750 | d11regs_t *regs; |
1751 | uint16 mac_l; | 1751 | u16 mac_l; |
1752 | uint16 mac_m; | 1752 | u16 mac_m; |
1753 | uint16 mac_h; | 1753 | u16 mac_h; |
1754 | osl_t *osh; | 1754 | osl_t *osh; |
1755 | 1755 | ||
1756 | WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit)); | 1756 | WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit)); |
@@ -1780,7 +1780,7 @@ wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len, | |||
1780 | uint32 word; | 1780 | uint32 word; |
1781 | bool be_bit; | 1781 | bool be_bit; |
1782 | #ifdef IL_BIGENDIAN | 1782 | #ifdef IL_BIGENDIAN |
1783 | volatile uint16 *dptr = NULL; | 1783 | volatile u16 *dptr = NULL; |
1784 | #endif /* IL_BIGENDIAN */ | 1784 | #endif /* IL_BIGENDIAN */ |
1785 | osl_t *osh; | 1785 | osl_t *osh; |
1786 | 1786 | ||
@@ -1816,7 +1816,7 @@ wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len, | |||
1816 | } | 1816 | } |
1817 | } | 1817 | } |
1818 | 1818 | ||
1819 | void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, uint16 newmin) | 1819 | void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin) |
1820 | { | 1820 | { |
1821 | osl_t *osh; | 1821 | osl_t *osh; |
1822 | 1822 | ||
@@ -1828,7 +1828,7 @@ void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, uint16 newmin) | |||
1828 | W_REG(osh, &wlc_hw->regs->objdata, newmin); | 1828 | W_REG(osh, &wlc_hw->regs->objdata, newmin); |
1829 | } | 1829 | } |
1830 | 1830 | ||
1831 | void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, uint16 newmax) | 1831 | void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax) |
1832 | { | 1832 | { |
1833 | osl_t *osh; | 1833 | osl_t *osh; |
1834 | 1834 | ||
@@ -1840,7 +1840,7 @@ void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, uint16 newmax) | |||
1840 | W_REG(osh, &wlc_hw->regs->objdata, newmax); | 1840 | W_REG(osh, &wlc_hw->regs->objdata, newmax); |
1841 | } | 1841 | } |
1842 | 1842 | ||
1843 | void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, uint16 bw) | 1843 | void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw) |
1844 | { | 1844 | { |
1845 | bool fastclk; | 1845 | bool fastclk; |
1846 | uint32 tmp; | 1846 | uint32 tmp; |
@@ -1873,7 +1873,7 @@ wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn, int len) | |||
1873 | bcn); | 1873 | bcn); |
1874 | /* write beacon length to SCR */ | 1874 | /* write beacon length to SCR */ |
1875 | ASSERT(len < 65536); | 1875 | ASSERT(len < 65536); |
1876 | wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (uint16) len); | 1876 | wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len); |
1877 | /* mark beacon0 valid */ | 1877 | /* mark beacon0 valid */ |
1878 | OR_REG(wlc_hw->osh, ®s->maccommand, MCMD_BCN0VLD); | 1878 | OR_REG(wlc_hw->osh, ®s->maccommand, MCMD_BCN0VLD); |
1879 | } | 1879 | } |
@@ -1887,7 +1887,7 @@ wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn, int len) | |||
1887 | bcn); | 1887 | bcn); |
1888 | /* write beacon length to SCR */ | 1888 | /* write beacon length to SCR */ |
1889 | ASSERT(len < 65536); | 1889 | ASSERT(len < 65536); |
1890 | wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (uint16) len); | 1890 | wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len); |
1891 | /* mark beacon1 valid */ | 1891 | /* mark beacon1 valid */ |
1892 | OR_REG(wlc_hw->osh, ®s->maccommand, MCMD_BCN1VLD); | 1892 | OR_REG(wlc_hw->osh, ®s->maccommand, MCMD_BCN1VLD); |
1893 | } | 1893 | } |
@@ -1917,7 +1917,7 @@ wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, int len, | |||
1917 | 1917 | ||
1918 | static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t *wlc_hw) | 1918 | static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t *wlc_hw) |
1919 | { | 1919 | { |
1920 | uint16 v; | 1920 | u16 v; |
1921 | wlc_info_t *wlc = wlc_hw->wlc; | 1921 | wlc_info_t *wlc = wlc_hw->wlc; |
1922 | /* update SYNTHPU_DLY */ | 1922 | /* update SYNTHPU_DLY */ |
1923 | 1923 | ||
@@ -1964,8 +1964,8 @@ WLBANDINITFN(wlc_bmac_bsinit) (wlc_info_t *wlc, chanspec_t chanspec) | |||
1964 | shortslot); | 1964 | shortslot); |
1965 | 1965 | ||
1966 | /* write phytype and phyvers */ | 1966 | /* write phytype and phyvers */ |
1967 | wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (uint16) wlc_hw->band->phytype); | 1967 | wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype); |
1968 | wlc_bmac_write_shm(wlc_hw, M_PHYVER, (uint16) wlc_hw->band->phyrev); | 1968 | wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev); |
1969 | 1969 | ||
1970 | /* initialize the txphyctl1 rate table since shmem is shared between bands */ | 1970 | /* initialize the txphyctl1 rate table since shmem is shared between bands */ |
1971 | wlc_upd_ofdm_pctl1_table(wlc_hw); | 1971 | wlc_upd_ofdm_pctl1_table(wlc_hw); |
@@ -2302,7 +2302,7 @@ static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo) | |||
2302 | 2302 | ||
2303 | if (D11REV_LT(wlc_hw->corerev, 12)) { | 2303 | if (D11REV_LT(wlc_hw->corerev, 12)) { |
2304 | bool rxidle = TRUE; | 2304 | bool rxidle = TRUE; |
2305 | uint16 rcv_frm_cnt = 0; | 2305 | u16 rcv_frm_cnt = 0; |
2306 | 2306 | ||
2307 | osh = wlc_hw->osh; | 2307 | osh = wlc_hw->osh; |
2308 | 2308 | ||
@@ -2420,10 +2420,10 @@ void BCMINITFN(wlc_bmac_corereset) (wlc_hw_info_t *wlc_hw, uint32 flags) | |||
2420 | static void BCMINITFN(wlc_corerev_fifofixup) (wlc_hw_info_t *wlc_hw) | 2420 | static void BCMINITFN(wlc_corerev_fifofixup) (wlc_hw_info_t *wlc_hw) |
2421 | { | 2421 | { |
2422 | d11regs_t *regs = wlc_hw->regs; | 2422 | d11regs_t *regs = wlc_hw->regs; |
2423 | uint16 fifo_nu; | 2423 | u16 fifo_nu; |
2424 | uint16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk; | 2424 | u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk; |
2425 | uint16 txfifo_def, txfifo_def1; | 2425 | u16 txfifo_def, txfifo_def1; |
2426 | uint16 txfifo_cmd; | 2426 | u16 txfifo_cmd; |
2427 | osl_t *osh; | 2427 | osl_t *osh; |
2428 | 2428 | ||
2429 | if (D11REV_LT(wlc_hw->corerev, 9)) | 2429 | if (D11REV_LT(wlc_hw->corerev, 9)) |
@@ -2487,7 +2487,7 @@ static void BCMINITFN(wlc_coreinit) (wlc_info_t *wlc) | |||
2487 | bool fifosz_fixup = FALSE; | 2487 | bool fifosz_fixup = FALSE; |
2488 | osl_t *osh; | 2488 | osl_t *osh; |
2489 | int err = 0; | 2489 | int err = 0; |
2490 | uint16 buf[NFIFO]; | 2490 | u16 buf[NFIFO]; |
2491 | 2491 | ||
2492 | regs = wlc_hw->regs; | 2492 | regs = wlc_hw->regs; |
2493 | osh = wlc_hw->osh; | 2493 | osh = wlc_hw->osh; |
@@ -2629,14 +2629,14 @@ static void BCMINITFN(wlc_coreinit) (wlc_info_t *wlc) | |||
2629 | } | 2629 | } |
2630 | 2630 | ||
2631 | /* tell the ucode the corerev */ | 2631 | /* tell the ucode the corerev */ |
2632 | wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (uint16) wlc_hw->corerev); | 2632 | wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev); |
2633 | 2633 | ||
2634 | /* tell the ucode MAC capabilities */ | 2634 | /* tell the ucode MAC capabilities */ |
2635 | if (D11REV_GE(wlc_hw->corerev, 13)) { | 2635 | if (D11REV_GE(wlc_hw->corerev, 13)) { |
2636 | wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L, | 2636 | wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L, |
2637 | (uint16) (wlc_hw->machwcap & 0xffff)); | 2637 | (u16) (wlc_hw->machwcap & 0xffff)); |
2638 | wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H, | 2638 | wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H, |
2639 | (uint16) ((wlc_hw-> | 2639 | (u16) ((wlc_hw-> |
2640 | machwcap >> 16) & 0xffff)); | 2640 | machwcap >> 16) & 0xffff)); |
2641 | } | 2641 | } |
2642 | 2642 | ||
@@ -2849,7 +2849,7 @@ static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits) | |||
2849 | ASSERT((inits[i].size == 2) || (inits[i].size == 4)); | 2849 | ASSERT((inits[i].size == 2) || (inits[i].size == 4)); |
2850 | 2850 | ||
2851 | if (inits[i].size == 2) | 2851 | if (inits[i].size == 2) |
2852 | W_REG(osh, (uint16 *) (uintptr) (base + inits[i].addr), | 2852 | W_REG(osh, (u16 *) (uintptr) (base + inits[i].addr), |
2853 | inits[i].value); | 2853 | inits[i].value); |
2854 | else if (inits[i].size == 4) | 2854 | else if (inits[i].size == 4) |
2855 | W_REG(osh, (uint32 *) (uintptr) (base + inits[i].addr), | 2855 | W_REG(osh, (uint32 *) (uintptr) (base + inits[i].addr), |
@@ -2859,9 +2859,9 @@ static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits) | |||
2859 | 2859 | ||
2860 | static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw) | 2860 | static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw) |
2861 | { | 2861 | { |
2862 | uint16 phyctl; | 2862 | u16 phyctl; |
2863 | uint16 phytxant = wlc_hw->bmac_phytxant; | 2863 | u16 phytxant = wlc_hw->bmac_phytxant; |
2864 | uint16 mask = PHY_TXC_ANT_MASK; | 2864 | u16 mask = PHY_TXC_ANT_MASK; |
2865 | 2865 | ||
2866 | /* set the Probe Response frame phy control word */ | 2866 | /* set the Probe Response frame phy control word */ |
2867 | phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS); | 2867 | phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS); |
@@ -2874,7 +2874,7 @@ static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw) | |||
2874 | wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl); | 2874 | wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl); |
2875 | } | 2875 | } |
2876 | 2876 | ||
2877 | void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, uint16 phytxant) | 2877 | void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, u16 phytxant) |
2878 | { | 2878 | { |
2879 | /* update sw state */ | 2879 | /* update sw state */ |
2880 | wlc_hw->bmac_phytxant = phytxant; | 2880 | wlc_hw->bmac_phytxant = phytxant; |
@@ -2886,9 +2886,9 @@ void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, uint16 phytxant) | |||
2886 | 2886 | ||
2887 | } | 2887 | } |
2888 | 2888 | ||
2889 | uint16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw) | 2889 | u16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw) |
2890 | { | 2890 | { |
2891 | return (uint16) wlc_hw->wlc->stf->txant; | 2891 | return (u16) wlc_hw->wlc->stf->txant; |
2892 | } | 2892 | } |
2893 | 2893 | ||
2894 | void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type) | 2894 | void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type) |
@@ -3081,8 +3081,8 @@ int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, uint blocks) | |||
3081 | if (fifo >= NFIFO || blocks > 299) | 3081 | if (fifo >= NFIFO || blocks > 299) |
3082 | return BCME_RANGE; | 3082 | return BCME_RANGE; |
3083 | 3083 | ||
3084 | /* BMAC_NOTE, change blocks to uint16 */ | 3084 | /* BMAC_NOTE, change blocks to u16 */ |
3085 | wlc_hw->xmtfifo_sz[fifo] = (uint16) blocks; | 3085 | wlc_hw->xmtfifo_sz[fifo] = (u16) blocks; |
3086 | 3086 | ||
3087 | return 0; | 3087 | return 0; |
3088 | } | 3088 | } |
@@ -3587,8 +3587,8 @@ static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw) | |||
3587 | WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M, | 3587 | WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M, |
3588 | WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M | 3588 | WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M |
3589 | }; | 3589 | }; |
3590 | uint16 entry_ptr; | 3590 | u16 entry_ptr; |
3591 | uint16 pctl1; | 3591 | u16 pctl1; |
3592 | uint i; | 3592 | uint i; |
3593 | 3593 | ||
3594 | if (!WLC_PHY_11N_CAP(wlc_hw->band)) | 3594 | if (!WLC_PHY_11N_CAP(wlc_hw->band)) |
@@ -3614,7 +3614,7 @@ static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw) | |||
3614 | } | 3614 | } |
3615 | } | 3615 | } |
3616 | 3616 | ||
3617 | static uint16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, u8 rate) | 3617 | static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, u8 rate) |
3618 | { | 3618 | { |
3619 | uint i; | 3619 | uint i; |
3620 | u8 plcp_rate = 0; | 3620 | u8 plcp_rate = 0; |
@@ -3672,7 +3672,7 @@ bool BCMATTACHFN(wlc_bmac_validate_chip_access) (wlc_hw_info_t *wlc_hw) | |||
3672 | { | 3672 | { |
3673 | d11regs_t *regs; | 3673 | d11regs_t *regs; |
3674 | uint32 w, val; | 3674 | uint32 w, val; |
3675 | volatile uint16 *reg16; | 3675 | volatile u16 *reg16; |
3676 | osl_t *osh; | 3676 | osl_t *osh; |
3677 | 3677 | ||
3678 | WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit)); | 3678 | WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit)); |
@@ -3719,7 +3719,7 @@ bool BCMATTACHFN(wlc_bmac_validate_chip_access) (wlc_hw_info_t *wlc_hw) | |||
3719 | /* if 32 bit writes are split into 16 bit writes, are they in the correct order | 3719 | /* if 32 bit writes are split into 16 bit writes, are they in the correct order |
3720 | * for our interface, low to high | 3720 | * for our interface, low to high |
3721 | */ | 3721 | */ |
3722 | reg16 = (volatile uint16 *)(uintptr) & regs->tsf_cfpstart; | 3722 | reg16 = (volatile u16 *)(uintptr) & regs->tsf_cfpstart; |
3723 | 3723 | ||
3724 | /* write the CFPStart register low half explicitly, starting a buffered write */ | 3724 | /* write the CFPStart register low half explicitly, starting a buffered write */ |
3725 | W_REG(osh, reg16, 0xAAAA); | 3725 | W_REG(osh, reg16, 0xAAAA); |
@@ -3903,12 +3903,12 @@ static void wlc_flushqueues(wlc_info_t *wlc) | |||
3903 | dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]); | 3903 | dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]); |
3904 | } | 3904 | } |
3905 | 3905 | ||
3906 | uint16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset) | 3906 | u16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset) |
3907 | { | 3907 | { |
3908 | return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL); | 3908 | return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL); |
3909 | } | 3909 | } |
3910 | 3910 | ||
3911 | void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, uint16 v) | 3911 | void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v) |
3912 | { | 3912 | { |
3913 | wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL); | 3913 | wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL); |
3914 | } | 3914 | } |
@@ -3917,7 +3917,7 @@ void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, uint16 v) | |||
3917 | * SHM 'offset' needs to be an even address and | 3917 | * SHM 'offset' needs to be an even address and |
3918 | * Buffer length 'len' must be an even number of bytes | 3918 | * Buffer length 'len' must be an even number of bytes |
3919 | */ | 3919 | */ |
3920 | void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, uint16 v, int len) | 3920 | void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, int len) |
3921 | { | 3921 | { |
3922 | int i; | 3922 | int i; |
3923 | 3923 | ||
@@ -3933,14 +3933,14 @@ void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, uint16 v, int len) | |||
3933 | } | 3933 | } |
3934 | } | 3934 | } |
3935 | 3935 | ||
3936 | static uint16 | 3936 | static u16 |
3937 | wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, uint32 sel) | 3937 | wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, uint32 sel) |
3938 | { | 3938 | { |
3939 | d11regs_t *regs = wlc_hw->regs; | 3939 | d11regs_t *regs = wlc_hw->regs; |
3940 | volatile uint16 *objdata_lo = | 3940 | volatile u16 *objdata_lo = |
3941 | (volatile uint16 *)(uintptr) & regs->objdata; | 3941 | (volatile u16 *)(uintptr) & regs->objdata; |
3942 | volatile uint16 *objdata_hi = objdata_lo + 1; | 3942 | volatile u16 *objdata_hi = objdata_lo + 1; |
3943 | uint16 v; | 3943 | u16 v; |
3944 | 3944 | ||
3945 | ASSERT((offset & 1) == 0); | 3945 | ASSERT((offset & 1) == 0); |
3946 | 3946 | ||
@@ -3956,12 +3956,12 @@ wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, uint32 sel) | |||
3956 | } | 3956 | } |
3957 | 3957 | ||
3958 | static void | 3958 | static void |
3959 | wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, uint16 v, uint32 sel) | 3959 | wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, uint32 sel) |
3960 | { | 3960 | { |
3961 | d11regs_t *regs = wlc_hw->regs; | 3961 | d11regs_t *regs = wlc_hw->regs; |
3962 | volatile uint16 *objdata_lo = | 3962 | volatile u16 *objdata_lo = |
3963 | (volatile uint16 *)(uintptr) & regs->objdata; | 3963 | (volatile u16 *)(uintptr) & regs->objdata; |
3964 | volatile uint16 *objdata_hi = objdata_lo + 1; | 3964 | volatile u16 *objdata_hi = objdata_lo + 1; |
3965 | 3965 | ||
3966 | ASSERT((offset & 1) == 0); | 3966 | ASSERT((offset & 1) == 0); |
3967 | 3967 | ||
@@ -3983,7 +3983,7 @@ void | |||
3983 | wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf, | 3983 | wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf, |
3984 | int len, uint32 sel) | 3984 | int len, uint32 sel) |
3985 | { | 3985 | { |
3986 | uint16 v; | 3986 | u16 v; |
3987 | const u8 *p = (const u8 *)buf; | 3987 | const u8 *p = (const u8 *)buf; |
3988 | int i; | 3988 | int i; |
3989 | 3989 | ||
@@ -4009,7 +4009,7 @@ void | |||
4009 | wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf, | 4009 | wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf, |
4010 | int len, uint32 sel) | 4010 | int len, uint32 sel) |
4011 | { | 4011 | { |
4012 | uint16 v; | 4012 | u16 v; |
4013 | u8 *p = (u8 *) buf; | 4013 | u8 *p = (u8 *) buf; |
4014 | int i; | 4014 | int i; |
4015 | 4015 | ||
@@ -4036,7 +4036,7 @@ void wlc_bmac_copyfrom_vars(wlc_hw_info_t *wlc_hw, char **buf, uint *len) | |||
4036 | *len = wlc_hw->vars_size; | 4036 | *len = wlc_hw->vars_size; |
4037 | } | 4037 | } |
4038 | 4038 | ||
4039 | void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, uint16 SRL, uint16 LRL) | 4039 | void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, u16 SRL, u16 LRL) |
4040 | { | 4040 | { |
4041 | wlc_hw->SRL = SRL; | 4041 | wlc_hw->SRL = SRL; |
4042 | wlc_hw->LRL = LRL; | 4042 | wlc_hw->LRL = LRL; |
@@ -4178,9 +4178,9 @@ bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable) | |||
4178 | return TRUE; | 4178 | return TRUE; |
4179 | } | 4179 | } |
4180 | 4180 | ||
4181 | uint16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate) | 4181 | u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate) |
4182 | { | 4182 | { |
4183 | uint16 table_ptr; | 4183 | u16 table_ptr; |
4184 | u8 phy_rate, index; | 4184 | u8 phy_rate, index; |
4185 | 4185 | ||
4186 | /* get the phy specific rate encoding for the PLCP SIGNAL field */ | 4186 | /* get the phy specific rate encoding for the PLCP SIGNAL field */ |
diff --git a/drivers/staging/brcm80211/sys/wlc_bmac.h b/drivers/staging/brcm80211/sys/wlc_bmac.h index 05fc15ac362..056d2e4a00d 100644 --- a/drivers/staging/brcm80211/sys/wlc_bmac.h +++ b/drivers/staging/brcm80211/sys/wlc_bmac.h | |||
@@ -130,7 +130,7 @@ typedef enum { | |||
130 | WLCHW_STATE_LAST | 130 | WLCHW_STATE_LAST |
131 | } wlc_bmac_state_id_t; | 131 | } wlc_bmac_state_id_t; |
132 | 132 | ||
133 | extern int wlc_bmac_attach(wlc_info_t *wlc, uint16 vendor, uint16 device, | 133 | extern int wlc_bmac_attach(wlc_info_t *wlc, u16 vendor, u16 device, |
134 | uint unit, bool piomode, osl_t *osh, void *regsva, | 134 | uint unit, bool piomode, osl_t *osh, void *regsva, |
135 | uint bustype, void *btparam); | 135 | uint bustype, void *btparam); |
136 | extern int wlc_bmac_detach(wlc_info_t *wlc); | 136 | extern int wlc_bmac_detach(wlc_info_t *wlc); |
@@ -175,24 +175,24 @@ extern void wlc_bmac_set_chanspec(wlc_hw_info_t *wlc_hw, chanspec_t chanspec, | |||
175 | bool mute, struct txpwr_limits *txpwr); | 175 | bool mute, struct txpwr_limits *txpwr); |
176 | 176 | ||
177 | extern void wlc_bmac_txfifo(wlc_hw_info_t *wlc_hw, uint fifo, void *p, | 177 | extern void wlc_bmac_txfifo(wlc_hw_info_t *wlc_hw, uint fifo, void *p, |
178 | bool commit, uint16 frameid, u8 txpktpend); | 178 | bool commit, u16 frameid, u8 txpktpend); |
179 | extern int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo, | 179 | extern int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo, |
180 | uint *blocks); | 180 | uint *blocks); |
181 | extern void wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, uint16 mask, | 181 | extern void wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, |
182 | uint16 val, int bands); | 182 | u16 val, int bands); |
183 | extern void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, uint32 mask, uint32 val); | 183 | extern void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, uint32 mask, uint32 val); |
184 | extern uint16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands); | 184 | extern u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands); |
185 | extern int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, | 185 | extern int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, |
186 | uint blocks); | 186 | uint blocks); |
187 | extern void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, uint16 phytxant); | 187 | extern void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, u16 phytxant); |
188 | extern uint16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw); | 188 | extern u16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw); |
189 | extern void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type); | 189 | extern void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type); |
190 | extern int wlc_bmac_revinfo_get(wlc_hw_info_t *wlc_hw, | 190 | extern int wlc_bmac_revinfo_get(wlc_hw_info_t *wlc_hw, |
191 | wlc_bmac_revinfo_t *revinfo); | 191 | wlc_bmac_revinfo_t *revinfo); |
192 | extern int wlc_bmac_state_get(wlc_hw_info_t *wlc_hw, wlc_bmac_state_t *state); | 192 | extern int wlc_bmac_state_get(wlc_hw_info_t *wlc_hw, wlc_bmac_state_t *state); |
193 | extern void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, uint16 v); | 193 | extern void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v); |
194 | extern uint16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset); | 194 | extern u16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset); |
195 | extern void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, uint16 v, | 195 | extern void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, |
196 | int len); | 196 | int len); |
197 | extern void wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, | 197 | extern void wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, |
198 | int len, void *buf); | 198 | int len, void *buf); |
@@ -232,20 +232,20 @@ extern void wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, | |||
232 | 232 | ||
233 | extern void wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, uint32 *tsf_l_ptr, | 233 | extern void wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, uint32 *tsf_l_ptr, |
234 | uint32 *tsf_h_ptr); | 234 | uint32 *tsf_h_ptr); |
235 | extern void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, uint16 newmin); | 235 | extern void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin); |
236 | extern void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, uint16 newmax); | 236 | extern void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax); |
237 | extern void wlc_bmac_set_noreset(wlc_hw_info_t *wlc, bool noreset_flag); | 237 | extern void wlc_bmac_set_noreset(wlc_hw_info_t *wlc, bool noreset_flag); |
238 | extern void wlc_bmac_set_ucode_loaded(wlc_hw_info_t *wlc, bool ucode_loaded); | 238 | extern void wlc_bmac_set_ucode_loaded(wlc_hw_info_t *wlc, bool ucode_loaded); |
239 | 239 | ||
240 | extern void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, uint16 SRL, | 240 | extern void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, u16 SRL, |
241 | uint16 LRL); | 241 | u16 LRL); |
242 | 242 | ||
243 | extern void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw); | 243 | extern void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw); |
244 | 244 | ||
245 | #ifdef WLC_HIGH_ONLY | 245 | #ifdef WLC_HIGH_ONLY |
246 | extern void wlc_bmac_dngl_reboot(rpc_info_t *); | 246 | extern void wlc_bmac_dngl_reboot(rpc_info_t *); |
247 | extern void wlc_bmac_dngl_rpc_agg(rpc_info_t *, uint16 agg); | 247 | extern void wlc_bmac_dngl_rpc_agg(rpc_info_t *, u16 agg); |
248 | extern void wlc_bmac_dngl_rpc_msglevel(rpc_info_t *, uint16 level); | 248 | extern void wlc_bmac_dngl_rpc_msglevel(rpc_info_t *, u16 level); |
249 | extern void wlc_bmac_dngl_rpc_txq_wm_set(rpc_info_t *rpc, uint32 wm); | 249 | extern void wlc_bmac_dngl_rpc_txq_wm_set(rpc_info_t *rpc, uint32 wm); |
250 | extern void wlc_bmac_dngl_rpc_txq_wm_get(rpc_info_t *rpc, uint32 *wm); | 250 | extern void wlc_bmac_dngl_rpc_txq_wm_get(rpc_info_t *rpc, uint32 *wm); |
251 | extern void wlc_bmac_dngl_rpc_agg_limit_set(rpc_info_t *rpc, uint32 val); | 251 | extern void wlc_bmac_dngl_rpc_agg_limit_set(rpc_info_t *rpc, uint32 val); |
@@ -255,7 +255,7 @@ extern int wlc_bmac_debug_template(wlc_hw_info_t *wlc_hw); | |||
255 | 255 | ||
256 | /* API for BMAC driver (e.g. wlc_phy.c etc) */ | 256 | /* API for BMAC driver (e.g. wlc_phy.c etc) */ |
257 | 257 | ||
258 | extern void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, uint16 bw); | 258 | extern void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw); |
259 | extern void wlc_bmac_pllreq(wlc_hw_info_t *wlc_hw, bool set, mbool req_bit); | 259 | extern void wlc_bmac_pllreq(wlc_hw_info_t *wlc_hw, bool set, mbool req_bit); |
260 | extern void wlc_bmac_set_clk(wlc_hw_info_t *wlc_hw, bool on); | 260 | extern void wlc_bmac_set_clk(wlc_hw_info_t *wlc_hw, bool on); |
261 | extern bool wlc_bmac_taclear(wlc_hw_info_t *wlc_hw, bool ta_ok); | 261 | extern bool wlc_bmac_taclear(wlc_hw_info_t *wlc_hw, bool ta_ok); |
@@ -266,7 +266,7 @@ extern void wlc_bmac_dump(wlc_hw_info_t *wlc_hw, struct bcmstrbuf *b, | |||
266 | extern void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw); | 266 | extern void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw); |
267 | 267 | ||
268 | extern bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable); | 268 | extern bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable); |
269 | extern uint16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate); | 269 | extern u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate); |
270 | 270 | ||
271 | extern void wlc_bmac_assert_type_set(wlc_hw_info_t *wlc_hw, uint32 type); | 271 | extern void wlc_bmac_assert_type_set(wlc_hw_info_t *wlc_hw, uint32 type); |
272 | extern void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val); | 272 | extern void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val); |
diff --git a/drivers/staging/brcm80211/sys/wlc_bsscfg.h b/drivers/staging/brcm80211/sys/wlc_bsscfg.h index 9fd6788ec5f..b498bb7ca76 100644 --- a/drivers/staging/brcm80211/sys/wlc_bsscfg.h +++ b/drivers/staging/brcm80211/sys/wlc_bsscfg.h | |||
@@ -78,7 +78,7 @@ struct wlc_bsscfg { | |||
78 | int16 openshared; /* try Open auth first, then Shared Key */ | 78 | int16 openshared; /* try Open auth first, then Shared Key */ |
79 | bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */ | 79 | bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */ |
80 | bool eap_restrict; /* restrict data until 802.1X auth succeeds */ | 80 | bool eap_restrict; /* restrict data until 802.1X auth succeeds */ |
81 | uint16 WPA_auth; /* WPA: authenticated key management */ | 81 | u16 WPA_auth; /* WPA: authenticated key management */ |
82 | bool wpa2_preauth; /* default is TRUE, wpa_cap sets value */ | 82 | bool wpa2_preauth; /* default is TRUE, wpa_cap sets value */ |
83 | bool wsec_portopen; /* indicates keys are plumbed */ | 83 | bool wsec_portopen; /* indicates keys are plumbed */ |
84 | wsec_iv_t wpa_none_txiv; /* global txiv for WPA_NONE, tkip and aes */ | 84 | wsec_iv_t wpa_none_txiv; /* global txiv for WPA_NONE, tkip and aes */ |
@@ -94,8 +94,8 @@ struct wlc_bsscfg { | |||
94 | 94 | ||
95 | struct ether_addr BSSID; /* BSSID (associated) */ | 95 | struct ether_addr BSSID; /* BSSID (associated) */ |
96 | struct ether_addr cur_etheraddr; /* h/w address */ | 96 | struct ether_addr cur_etheraddr; /* h/w address */ |
97 | uint16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */ | 97 | u16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */ |
98 | uint16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */ | 98 | u16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */ |
99 | 99 | ||
100 | uint32 flags; /* WLC_BSSCFG flags; see below */ | 100 | uint32 flags; /* WLC_BSSCFG flags; see below */ |
101 | 101 | ||
@@ -125,7 +125,7 @@ struct wlc_bsscfg { | |||
125 | wsec_key_t *rcmta; | 125 | wsec_key_t *rcmta; |
126 | 126 | ||
127 | /* 'unique' ID of this bsscfg, assigned at bsscfg allocation */ | 127 | /* 'unique' ID of this bsscfg, assigned at bsscfg allocation */ |
128 | uint16 ID; | 128 | u16 ID; |
129 | 129 | ||
130 | uint txrspecidx; /* index into tx rate circular buffer */ | 130 | uint txrspecidx; /* index into tx rate circular buffer */ |
131 | ratespec_t txrspec[NTXRATE][2]; /* circular buffer of prev MPDUs tx rates */ | 131 | ratespec_t txrspec[NTXRATE][2]; /* circular buffer of prev MPDUs tx rates */ |
diff --git a/drivers/staging/brcm80211/sys/wlc_event.h b/drivers/staging/brcm80211/sys/wlc_event.h index 23fd5b18765..5921bba318f 100644 --- a/drivers/staging/brcm80211/sys/wlc_event.h +++ b/drivers/staging/brcm80211/sys/wlc_event.h | |||
@@ -44,8 +44,8 @@ extern void wlc_assign_event_msg(wlc_info_t *wlc, wl_event_msg_t *msg, | |||
44 | 44 | ||
45 | #ifdef MSGTRACE | 45 | #ifdef MSGTRACE |
46 | extern void wlc_event_sendup_trace(struct wlc_info *wlc, hndrte_dev_t *bus, | 46 | extern void wlc_event_sendup_trace(struct wlc_info *wlc, hndrte_dev_t *bus, |
47 | u8 *hdr, uint16 hdrlen, u8 *buf, | 47 | u8 *hdr, u16 hdrlen, u8 *buf, |
48 | uint16 buflen); | 48 | u16 buflen); |
49 | #endif | 49 | #endif |
50 | 50 | ||
51 | #endif /* _WLC_EVENT_H_ */ | 51 | #endif /* _WLC_EVENT_H_ */ |
diff --git a/drivers/staging/brcm80211/sys/wlc_key.h b/drivers/staging/brcm80211/sys/wlc_key.h index 3a9624afbba..ce251c0802c 100644 --- a/drivers/staging/brcm80211/sys/wlc_key.h +++ b/drivers/staging/brcm80211/sys/wlc_key.h | |||
@@ -81,7 +81,7 @@ struct wlc_bsscfg; | |||
81 | 81 | ||
82 | typedef struct wsec_iv { | 82 | typedef struct wsec_iv { |
83 | uint32 hi; /* upper 32 bits of IV */ | 83 | uint32 hi; /* upper 32 bits of IV */ |
84 | uint16 lo; /* lower 16 bits of IV */ | 84 | u16 lo; /* lower 16 bits of IV */ |
85 | } wsec_iv_t; | 85 | } wsec_iv_t; |
86 | 86 | ||
87 | #define WLC_NUMRXIVS 16 /* # rx IVs (one per 802.11e TID) */ | 87 | #define WLC_NUMRXIVS 16 /* # rx IVs (one per 802.11e TID) */ |
@@ -92,7 +92,7 @@ typedef struct wsec_key { | |||
92 | u8 id; /* key ID [0-3] */ | 92 | u8 id; /* key ID [0-3] */ |
93 | u8 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */ | 93 | u8 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */ |
94 | u8 rcmta; /* rcmta entry index, same as idx by default */ | 94 | u8 rcmta; /* rcmta entry index, same as idx by default */ |
95 | uint16 flags; /* misc flags */ | 95 | u16 flags; /* misc flags */ |
96 | u8 algo_hw; /* cache for hw register */ | 96 | u8 algo_hw; /* cache for hw register */ |
97 | u8 aes_mode; /* cache for hw register */ | 97 | u8 aes_mode; /* cache for hw register */ |
98 | s8 iv_len; /* IV length */ | 98 | s8 iv_len; /* IV length */ |
diff --git a/drivers/staging/brcm80211/sys/wlc_mac80211.c b/drivers/staging/brcm80211/sys/wlc_mac80211.c index f3d8d3a6c59..46362d188e1 100644 --- a/drivers/staging/brcm80211/sys/wlc_mac80211.c +++ b/drivers/staging/brcm80211/sys/wlc_mac80211.c | |||
@@ -250,7 +250,7 @@ static const u8 acbitmap2maxprio[] = { | |||
250 | 250 | ||
251 | /* local prototypes */ | 251 | /* local prototypes */ |
252 | extern void wlc_txq_enq(void *ctx, struct scb *scb, void *sdu, uint prec); | 252 | extern void wlc_txq_enq(void *ctx, struct scb *scb, void *sdu, uint prec); |
253 | static uint16 BCMFASTPATH wlc_d11hdrs_mac80211(wlc_info_t *wlc, | 253 | static u16 BCMFASTPATH wlc_d11hdrs_mac80211(wlc_info_t *wlc, |
254 | struct ieee80211_hw *hw, void *p, | 254 | struct ieee80211_hw *hw, void *p, |
255 | struct scb *scb, uint frag, | 255 | struct scb *scb, uint frag, |
256 | uint nfrags, uint queue, | 256 | uint nfrags, uint queue, |
@@ -277,12 +277,12 @@ static void wlc_txq_free(wlc_info_t *wlc, osl_t *osh, wlc_txq_info_t *qi); | |||
277 | static void wlc_txflowcontrol_signal(wlc_info_t *wlc, wlc_txq_info_t *qi, | 277 | static void wlc_txflowcontrol_signal(wlc_info_t *wlc, wlc_txq_info_t *qi, |
278 | bool on, int prio); | 278 | bool on, int prio); |
279 | static void wlc_txflowcontrol_reset(wlc_info_t *wlc); | 279 | static void wlc_txflowcontrol_reset(wlc_info_t *wlc); |
280 | static uint16 wlc_compute_airtime(wlc_info_t *wlc, ratespec_t rspec, | 280 | static u16 wlc_compute_airtime(wlc_info_t *wlc, ratespec_t rspec, |
281 | uint length); | 281 | uint length); |
282 | static void wlc_compute_cck_plcp(ratespec_t rate, uint length, u8 *plcp); | 282 | static void wlc_compute_cck_plcp(ratespec_t rate, uint length, u8 *plcp); |
283 | static void wlc_compute_ofdm_plcp(ratespec_t rate, uint length, u8 *plcp); | 283 | static void wlc_compute_ofdm_plcp(ratespec_t rate, uint length, u8 *plcp); |
284 | static void wlc_compute_mimo_plcp(ratespec_t rate, uint length, u8 *plcp); | 284 | static void wlc_compute_mimo_plcp(ratespec_t rate, uint length, u8 *plcp); |
285 | static uint16 wlc_compute_frame_dur(wlc_info_t *wlc, ratespec_t rate, | 285 | static u16 wlc_compute_frame_dur(wlc_info_t *wlc, ratespec_t rate, |
286 | u8 preamble_type, uint next_frag_len); | 286 | u8 preamble_type, uint next_frag_len); |
287 | static void wlc_recvctl(wlc_info_t *wlc, osl_t *osh, d11rxhdr_t *rxh, | 287 | static void wlc_recvctl(wlc_info_t *wlc, osl_t *osh, d11rxhdr_t *rxh, |
288 | void *p); | 288 | void *p); |
@@ -348,7 +348,7 @@ void wlc_get_rcmta(wlc_info_t *wlc, int idx, struct ether_addr *addr) | |||
348 | addr->octet[3] = (u8) (v32 >> 24); | 348 | addr->octet[3] = (u8) (v32 >> 24); |
349 | W_REG(osh, ®s->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1))); | 349 | W_REG(osh, ®s->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1))); |
350 | (void)R_REG(osh, ®s->objaddr); | 350 | (void)R_REG(osh, ®s->objaddr); |
351 | v32 = R_REG(osh, (volatile uint16 *)(uintptr) & regs->objdata); | 351 | v32 = R_REG(osh, (volatile u16 *)(uintptr) & regs->objdata); |
352 | addr->octet[4] = (u8) v32; | 352 | addr->octet[4] = (u8) v32; |
353 | addr->octet[5] = (u8) (v32 >> 8); | 353 | addr->octet[5] = (u8) (v32 >> 8); |
354 | } | 354 | } |
@@ -559,7 +559,7 @@ void BCMINITFN(wlc_init) (wlc_info_t *wlc) | |||
559 | /* read the ucode version if we have not yet done so */ | 559 | /* read the ucode version if we have not yet done so */ |
560 | if (wlc->ucode_rev == 0) { | 560 | if (wlc->ucode_rev == 0) { |
561 | wlc->ucode_rev = | 561 | wlc->ucode_rev = |
562 | wlc_read_shm(wlc, M_BOM_REV_MAJOR) << NBITS(uint16); | 562 | wlc_read_shm(wlc, M_BOM_REV_MAJOR) << NBITS(u16); |
563 | wlc->ucode_rev |= wlc_read_shm(wlc, M_BOM_REV_MINOR); | 563 | wlc->ucode_rev |= wlc_read_shm(wlc, M_BOM_REV_MINOR); |
564 | } | 564 | } |
565 | 565 | ||
@@ -1153,9 +1153,9 @@ ratespec_t wlc_lowest_basic_rspec(wlc_info_t *wlc, wlc_rateset_t *rs) | |||
1153 | */ | 1153 | */ |
1154 | void wlc_beacon_phytxctl_txant_upd(wlc_info_t *wlc, ratespec_t bcn_rspec) | 1154 | void wlc_beacon_phytxctl_txant_upd(wlc_info_t *wlc, ratespec_t bcn_rspec) |
1155 | { | 1155 | { |
1156 | uint16 phyctl; | 1156 | u16 phyctl; |
1157 | uint16 phytxant = wlc->stf->phytxant; | 1157 | u16 phytxant = wlc->stf->phytxant; |
1158 | uint16 mask = PHY_TXC_ANT_MASK; | 1158 | u16 mask = PHY_TXC_ANT_MASK; |
1159 | 1159 | ||
1160 | /* for non-siso rates or default setting, use the available chains */ | 1160 | /* for non-siso rates or default setting, use the available chains */ |
1161 | if (WLC_PHY_11N_CAP(wlc->band)) { | 1161 | if (WLC_PHY_11N_CAP(wlc->band)) { |
@@ -1393,7 +1393,7 @@ void wlc_wme_setparams(wlc_info_t *wlc, u16 aci, void *arg, bool suspend) | |||
1393 | { | 1393 | { |
1394 | int i; | 1394 | int i; |
1395 | shm_acparams_t acp_shm; | 1395 | shm_acparams_t acp_shm; |
1396 | uint16 *shm_entry; | 1396 | u16 *shm_entry; |
1397 | struct ieee80211_tx_queue_params *params = arg; | 1397 | struct ieee80211_tx_queue_params *params = arg; |
1398 | 1398 | ||
1399 | ASSERT(wlc); | 1399 | ASSERT(wlc); |
@@ -1451,7 +1451,7 @@ void wlc_wme_setparams(wlc_info_t *wlc, u16 aci, void *arg, bool suspend) | |||
1451 | acp_shm.status |= WME_STATUS_NEWAC; | 1451 | acp_shm.status |= WME_STATUS_NEWAC; |
1452 | 1452 | ||
1453 | /* Fill in shm acparam table */ | 1453 | /* Fill in shm acparam table */ |
1454 | shm_entry = (uint16 *) &acp_shm; | 1454 | shm_entry = (u16 *) &acp_shm; |
1455 | for (i = 0; i < (int)sizeof(shm_acparams_t); i += 2) | 1455 | for (i = 0; i < (int)sizeof(shm_acparams_t); i += 2) |
1456 | wlc_write_shm(wlc, | 1456 | wlc_write_shm(wlc, |
1457 | M_EDCF_QINFO + | 1457 | M_EDCF_QINFO + |
@@ -1474,7 +1474,7 @@ void wlc_edcf_setparams(wlc_bsscfg_t *cfg, bool suspend) | |||
1474 | uint aci, i, j; | 1474 | uint aci, i, j; |
1475 | edcf_acparam_t *edcf_acp; | 1475 | edcf_acparam_t *edcf_acp; |
1476 | shm_acparams_t acp_shm; | 1476 | shm_acparams_t acp_shm; |
1477 | uint16 *shm_entry; | 1477 | u16 *shm_entry; |
1478 | 1478 | ||
1479 | ASSERT(cfg); | 1479 | ASSERT(cfg); |
1480 | ASSERT(wlc); | 1480 | ASSERT(wlc); |
@@ -1538,7 +1538,7 @@ void wlc_edcf_setparams(wlc_bsscfg_t *cfg, bool suspend) | |||
1538 | acp_shm.status |= WME_STATUS_NEWAC; | 1538 | acp_shm.status |= WME_STATUS_NEWAC; |
1539 | 1539 | ||
1540 | /* Fill in shm acparam table */ | 1540 | /* Fill in shm acparam table */ |
1541 | shm_entry = (uint16 *) &acp_shm; | 1541 | shm_entry = (u16 *) &acp_shm; |
1542 | for (j = 0; j < (int)sizeof(shm_acparams_t); j += 2) | 1542 | for (j = 0; j < (int)sizeof(shm_acparams_t); j += 2) |
1543 | wlc_write_shm(wlc, | 1543 | wlc_write_shm(wlc, |
1544 | M_EDCF_QINFO + | 1544 | M_EDCF_QINFO + |
@@ -1760,7 +1760,7 @@ wlc_pub_t *wlc_pub(void *wlc) | |||
1760 | /* | 1760 | /* |
1761 | * The common driver entry routine. Error codes should be unique | 1761 | * The common driver entry routine. Error codes should be unique |
1762 | */ | 1762 | */ |
1763 | void *BCMATTACHFN(wlc_attach) (void *wl, uint16 vendor, uint16 device, | 1763 | void *BCMATTACHFN(wlc_attach) (void *wl, u16 vendor, u16 device, |
1764 | uint unit, bool piomode, osl_t *osh, | 1764 | uint unit, bool piomode, osl_t *osh, |
1765 | void *regsva, uint bustype, void *btparam, | 1765 | void *regsva, uint bustype, void *btparam, |
1766 | uint *perr) { | 1766 | uint *perr) { |
@@ -1869,9 +1869,9 @@ void *BCMATTACHFN(wlc_attach) (void *wl, uint16 vendor, uint16 device, | |||
1869 | 1869 | ||
1870 | /* set maximum allowed duty cycle */ | 1870 | /* set maximum allowed duty cycle */ |
1871 | wlc->tx_duty_cycle_ofdm = | 1871 | wlc->tx_duty_cycle_ofdm = |
1872 | (uint16) getintvar(pub->vars, "tx_duty_cycle_ofdm"); | 1872 | (u16) getintvar(pub->vars, "tx_duty_cycle_ofdm"); |
1873 | wlc->tx_duty_cycle_cck = | 1873 | wlc->tx_duty_cycle_cck = |
1874 | (uint16) getintvar(pub->vars, "tx_duty_cycle_cck"); | 1874 | (u16) getintvar(pub->vars, "tx_duty_cycle_cck"); |
1875 | 1875 | ||
1876 | wlc_stf_phy_chain_calc(wlc); | 1876 | wlc_stf_phy_chain_calc(wlc); |
1877 | 1877 | ||
@@ -2146,7 +2146,7 @@ static bool BCMATTACHFN(wlc_attach_stf_ant_init) (wlc_info_t *wlc) | |||
2146 | #ifdef WLC_HIGH_ONLY | 2146 | #ifdef WLC_HIGH_ONLY |
2147 | /* HIGH_ONLY bmac_attach, which sync over LOW_ONLY bmac_attach states */ | 2147 | /* HIGH_ONLY bmac_attach, which sync over LOW_ONLY bmac_attach states */ |
2148 | int | 2148 | int |
2149 | BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, uint16 vendor, uint16 device, | 2149 | BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, u16 vendor, u16 device, |
2150 | uint unit, bool piomode, osl_t *osh, | 2150 | uint unit, bool piomode, osl_t *osh, |
2151 | void *regsva, uint bustype, void *btparam) { | 2151 | void *regsva, uint bustype, void *btparam) { |
2152 | wlc_bmac_revinfo_t revinfo; | 2152 | wlc_bmac_revinfo_t revinfo; |
@@ -2192,10 +2192,10 @@ BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, uint16 vendor, uint16 device, | |||
2192 | bzero(&revinfo, sizeof(wlc_bmac_revinfo_t)); | 2192 | bzero(&revinfo, sizeof(wlc_bmac_revinfo_t)); |
2193 | if (wlc_bmac_revinfo_get(wlc->hw, &revinfo) != 0) | 2193 | if (wlc_bmac_revinfo_get(wlc->hw, &revinfo) != 0) |
2194 | return -1; | 2194 | return -1; |
2195 | wlc->vendorid = (uint16) revinfo.vendorid; | 2195 | wlc->vendorid = (u16) revinfo.vendorid; |
2196 | wlc->deviceid = (uint16) revinfo.deviceid; | 2196 | wlc->deviceid = (u16) revinfo.deviceid; |
2197 | 2197 | ||
2198 | wlc->pub->boardrev = (uint16) revinfo.boardrev; | 2198 | wlc->pub->boardrev = (u16) revinfo.boardrev; |
2199 | wlc->pub->corerev = revinfo.corerev; | 2199 | wlc->pub->corerev = revinfo.corerev; |
2200 | wlc->pub->sromrev = (u8) revinfo.sromrev; | 2200 | wlc->pub->sromrev = (u8) revinfo.sromrev; |
2201 | wlc->pub->sih->chiprev = revinfo.chiprev; | 2201 | wlc->pub->sih->chiprev = revinfo.chiprev; |
@@ -2227,11 +2227,11 @@ BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, uint16 vendor, uint16 device, | |||
2227 | wlc->bandstate[bandunit]->radiorev = | 2227 | wlc->bandstate[bandunit]->radiorev = |
2228 | (u8) revinfo.band[idx].radiorev; | 2228 | (u8) revinfo.band[idx].radiorev; |
2229 | wlc->bandstate[bandunit]->phytype = | 2229 | wlc->bandstate[bandunit]->phytype = |
2230 | (uint16) revinfo.band[idx].phytype; | 2230 | (u16) revinfo.band[idx].phytype; |
2231 | wlc->bandstate[bandunit]->phyrev = | 2231 | wlc->bandstate[bandunit]->phyrev = |
2232 | (uint16) revinfo.band[idx].phyrev; | 2232 | (u16) revinfo.band[idx].phyrev; |
2233 | wlc->bandstate[bandunit]->radioid = | 2233 | wlc->bandstate[bandunit]->radioid = |
2234 | (uint16) revinfo.band[idx].radioid; | 2234 | (u16) revinfo.band[idx].radioid; |
2235 | wlc->bandstate[bandunit]->abgphy_encore = | 2235 | wlc->bandstate[bandunit]->abgphy_encore = |
2236 | revinfo.band[idx].abgphy_encore; | 2236 | revinfo.band[idx].abgphy_encore; |
2237 | 2237 | ||
@@ -2838,7 +2838,7 @@ int BCMINITFN(wlc_up) (wlc_info_t *wlc) | |||
2838 | static void BCMINITFN(wlc_tx_prec_map_init) (wlc_info_t *wlc) | 2838 | static void BCMINITFN(wlc_tx_prec_map_init) (wlc_info_t *wlc) |
2839 | { | 2839 | { |
2840 | wlc->tx_prec_map = WLC_PREC_BMP_ALL; | 2840 | wlc->tx_prec_map = WLC_PREC_BMP_ALL; |
2841 | bzero(wlc->fifo2prec_map, sizeof(uint16) * NFIFO); | 2841 | bzero(wlc->fifo2prec_map, sizeof(u16) * NFIFO); |
2842 | 2842 | ||
2843 | /* For non-WME, both fifos have overlapping MAXPRIO. So just disable all precedences | 2843 | /* For non-WME, both fifos have overlapping MAXPRIO. So just disable all precedences |
2844 | * if either is full. | 2844 | * if either is full. |
@@ -3449,13 +3449,13 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3449 | if (bcmerror) | 3449 | if (bcmerror) |
3450 | break; | 3450 | break; |
3451 | 3451 | ||
3452 | i = (uint16) val; | 3452 | i = (u16) val; |
3453 | if (i >= MHFMAX) { | 3453 | if (i >= MHFMAX) { |
3454 | bcmerror = BCME_RANGE; | 3454 | bcmerror = BCME_RANGE; |
3455 | break; | 3455 | break; |
3456 | } | 3456 | } |
3457 | 3457 | ||
3458 | wlc_mhf(wlc, (u8) i, 0xffff, (uint16) (val >> NBITS(uint16)), | 3458 | wlc_mhf(wlc, (u8) i, 0xffff, (u16) (val >> NBITS(u16)), |
3459 | WLC_BAND_AUTO); | 3459 | WLC_BAND_AUTO); |
3460 | break; | 3460 | break; |
3461 | 3461 | ||
@@ -3477,7 +3477,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3477 | break; | 3477 | break; |
3478 | } | 3478 | } |
3479 | 3479 | ||
3480 | *pval = wlc_read_shm(wlc, (uint16) val); | 3480 | *pval = wlc_read_shm(wlc, (u16) val); |
3481 | break; | 3481 | break; |
3482 | 3482 | ||
3483 | case WLC_SET_SHMEM: | 3483 | case WLC_SET_SHMEM: |
@@ -3498,8 +3498,8 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3498 | break; | 3498 | break; |
3499 | } | 3499 | } |
3500 | 3500 | ||
3501 | wlc_write_shm(wlc, (uint16) val, | 3501 | wlc_write_shm(wlc, (u16) val, |
3502 | (uint16) (val >> NBITS(uint16))); | 3502 | (u16) (val >> NBITS(u16))); |
3503 | break; | 3503 | break; |
3504 | 3504 | ||
3505 | case WLC_R_REG: /* MAC registers */ | 3505 | case WLC_R_REG: /* MAC registers */ |
@@ -3529,10 +3529,10 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3529 | R_REG(osh, | 3529 | R_REG(osh, |
3530 | (uint32 *) ((unsigned char *) (uintptr) regs + | 3530 | (uint32 *) ((unsigned char *) (uintptr) regs + |
3531 | r->byteoff)); | 3531 | r->byteoff)); |
3532 | else if (r->size == sizeof(uint16)) | 3532 | else if (r->size == sizeof(u16)) |
3533 | r->val = | 3533 | r->val = |
3534 | R_REG(osh, | 3534 | R_REG(osh, |
3535 | (uint16 *) ((unsigned char *) (uintptr) regs + | 3535 | (u16 *) ((unsigned char *) (uintptr) regs + |
3536 | r->byteoff)); | 3536 | r->byteoff)); |
3537 | else | 3537 | else |
3538 | bcmerror = BCME_BADADDR; | 3538 | bcmerror = BCME_BADADDR; |
@@ -3564,9 +3564,9 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3564 | W_REG(osh, | 3564 | W_REG(osh, |
3565 | (uint32 *) ((unsigned char *) (uintptr) regs + | 3565 | (uint32 *) ((unsigned char *) (uintptr) regs + |
3566 | r->byteoff), r->val); | 3566 | r->byteoff), r->val); |
3567 | else if (r->size == sizeof(uint16)) | 3567 | else if (r->size == sizeof(u16)) |
3568 | W_REG(osh, | 3568 | W_REG(osh, |
3569 | (uint16 *) ((unsigned char *) (uintptr) regs + | 3569 | (u16 *) ((unsigned char *) (uintptr) regs + |
3570 | r->byteoff), r->val); | 3570 | r->byteoff), r->val); |
3571 | else | 3571 | else |
3572 | bcmerror = BCME_BADADDR; | 3572 | bcmerror = BCME_BADADDR; |
@@ -3629,7 +3629,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3629 | break; | 3629 | break; |
3630 | 3630 | ||
3631 | case WLC_GET_RX_ANT:{ /* get latest used rx antenna */ | 3631 | case WLC_GET_RX_ANT:{ /* get latest used rx antenna */ |
3632 | uint16 rxstatus; | 3632 | u16 rxstatus; |
3633 | 3633 | ||
3634 | if (!wlc->pub->up) { | 3634 | if (!wlc->pub->up) { |
3635 | bcmerror = BCME_NOTUP; | 3635 | bcmerror = BCME_NOTUP; |
@@ -3637,7 +3637,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3637 | } | 3637 | } |
3638 | 3638 | ||
3639 | rxstatus = R_REG(wlc->osh, &wlc->regs->phyrxstatus0); | 3639 | rxstatus = R_REG(wlc->osh, &wlc->regs->phyrxstatus0); |
3640 | if (rxstatus == 0xdead || rxstatus == (uint16) -1) { | 3640 | if (rxstatus == 0xdead || rxstatus == (u16) -1) { |
3641 | bcmerror = BCME_ERROR; | 3641 | bcmerror = BCME_ERROR; |
3642 | break; | 3642 | break; |
3643 | } | 3643 | } |
@@ -3689,7 +3689,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3689 | case WLC_SET_SRL: | 3689 | case WLC_SET_SRL: |
3690 | if (val >= 1 && val <= RETRY_SHORT_MAX) { | 3690 | if (val >= 1 && val <= RETRY_SHORT_MAX) { |
3691 | int ac; | 3691 | int ac; |
3692 | wlc->SRL = (uint16) val; | 3692 | wlc->SRL = (u16) val; |
3693 | 3693 | ||
3694 | wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); | 3694 | wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); |
3695 | 3695 | ||
@@ -3708,7 +3708,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3708 | case WLC_SET_LRL: | 3708 | case WLC_SET_LRL: |
3709 | if (val >= 1 && val <= 255) { | 3709 | if (val >= 1 && val <= 255) { |
3710 | int ac; | 3710 | int ac; |
3711 | wlc->LRL = (uint16) val; | 3711 | wlc->LRL = (u16) val; |
3712 | 3712 | ||
3713 | wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); | 3713 | wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); |
3714 | 3714 | ||
@@ -3731,7 +3731,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3731 | } | 3731 | } |
3732 | 3732 | ||
3733 | if (val >= 1 && val <= 255) { | 3733 | if (val >= 1 && val <= 255) { |
3734 | wlc_set_cwmin(wlc, (uint16) val); | 3734 | wlc_set_cwmin(wlc, (u16) val); |
3735 | } else | 3735 | } else |
3736 | bcmerror = BCME_RANGE; | 3736 | bcmerror = BCME_RANGE; |
3737 | break; | 3737 | break; |
@@ -3747,7 +3747,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3747 | } | 3747 | } |
3748 | 3748 | ||
3749 | if (val >= 255 && val <= 2047) { | 3749 | if (val >= 255 && val <= 2047) { |
3750 | wlc_set_cwmax(wlc, (uint16) val); | 3750 | wlc_set_cwmax(wlc, (u16) val); |
3751 | } else | 3751 | } else |
3752 | bcmerror = BCME_RANGE; | 3752 | bcmerror = BCME_RANGE; |
3753 | break; | 3753 | break; |
@@ -3759,7 +3759,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3759 | case WLC_SET_RADIO:{ /* 32 bits input, higher 16 bits are mask, lower 16 bits are value to | 3759 | case WLC_SET_RADIO:{ /* 32 bits input, higher 16 bits are mask, lower 16 bits are value to |
3760 | * set | 3760 | * set |
3761 | */ | 3761 | */ |
3762 | uint16 radiomask, radioval; | 3762 | u16 radiomask, radioval; |
3763 | uint validbits = | 3763 | uint validbits = |
3764 | WL_RADIO_SW_DISABLE | WL_RADIO_HW_DISABLE; | 3764 | WL_RADIO_SW_DISABLE | WL_RADIO_HW_DISABLE; |
3765 | mbool new = 0; | 3765 | mbool new = 0; |
@@ -3845,7 +3845,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3845 | if ((val >= 0) && (val < WLC_MAX_WSEC_KEYS(wlc)) && | 3845 | if ((val >= 0) && (val < WLC_MAX_WSEC_KEYS(wlc)) && |
3846 | (key != NULL)) { | 3846 | (key != NULL)) { |
3847 | u8 seq[DOT11_WPA_KEY_RSC_LEN]; | 3847 | u8 seq[DOT11_WPA_KEY_RSC_LEN]; |
3848 | uint16 lo; | 3848 | u16 lo; |
3849 | uint32 hi; | 3849 | uint32 hi; |
3850 | /* group keys in WPA-NONE (IBSS only, AES and TKIP) use a global TXIV */ | 3850 | /* group keys in WPA-NONE (IBSS only, AES and TKIP) use a global TXIV */ |
3851 | if ((bsscfg->WPA_auth & WPA_AUTH_NONE) | 3851 | if ((bsscfg->WPA_auth & WPA_AUTH_NONE) |
@@ -3961,7 +3961,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
3961 | /* range [1, 0xffff] */ | 3961 | /* range [1, 0xffff] */ |
3962 | if (val >= DOT11_MIN_BEACON_PERIOD | 3962 | if (val >= DOT11_MIN_BEACON_PERIOD |
3963 | && val <= DOT11_MAX_BEACON_PERIOD) { | 3963 | && val <= DOT11_MAX_BEACON_PERIOD) { |
3964 | wlc->default_bss->beacon_period = (uint16) val; | 3964 | wlc->default_bss->beacon_period = (u16) val; |
3965 | } else | 3965 | } else |
3966 | bcmerror = BCME_RANGE; | 3966 | bcmerror = BCME_RANGE; |
3967 | break; | 3967 | break; |
@@ -4085,9 +4085,9 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
4085 | case WLC_SET_WPA_AUTH: | 4085 | case WLC_SET_WPA_AUTH: |
4086 | /* change of WPA_Auth modifies the PS_ALLOWED state */ | 4086 | /* change of WPA_Auth modifies the PS_ALLOWED state */ |
4087 | if (BSSCFG_STA(bsscfg)) { | 4087 | if (BSSCFG_STA(bsscfg)) { |
4088 | bsscfg->WPA_auth = (uint16) val; | 4088 | bsscfg->WPA_auth = (u16) val; |
4089 | } else | 4089 | } else |
4090 | bsscfg->WPA_auth = (uint16) val; | 4090 | bsscfg->WPA_auth = (u16) val; |
4091 | break; | 4091 | break; |
4092 | #endif /* SUPPORT_HWKEY */ | 4092 | #endif /* SUPPORT_HWKEY */ |
4093 | 4093 | ||
@@ -4320,7 +4320,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif) | |||
4320 | bcmerror = BCME_RANGE; /* bad value */ | 4320 | bcmerror = BCME_RANGE; /* bad value */ |
4321 | break; | 4321 | break; |
4322 | } | 4322 | } |
4323 | wlc->prb_resp_timeout = (uint16) val; | 4323 | wlc->prb_resp_timeout = (u16) val; |
4324 | break; | 4324 | break; |
4325 | 4325 | ||
4326 | case WLC_GET_KEY_PRIMARY:{ | 4326 | case WLC_GET_KEY_PRIMARY:{ |
@@ -4900,7 +4900,7 @@ static const char *supr_reason[] = { | |||
4900 | "Lifetime Expiry", "Underflow" | 4900 | "Lifetime Expiry", "Underflow" |
4901 | }; | 4901 | }; |
4902 | 4902 | ||
4903 | static void wlc_print_txs_status(uint16 s) | 4903 | static void wlc_print_txs_status(u16 s) |
4904 | { | 4904 | { |
4905 | printf("[15:12] %d frame attempts\n", (s & TX_STATUS_FRM_RTX_MASK) >> | 4905 | printf("[15:12] %d frame attempts\n", (s & TX_STATUS_FRM_RTX_MASK) >> |
4906 | TX_STATUS_FRM_RTX_SHIFT); | 4906 | TX_STATUS_FRM_RTX_SHIFT); |
@@ -4921,8 +4921,8 @@ static void wlc_print_txs_status(uint16 s) | |||
4921 | void wlc_print_txstatus(tx_status_t *txs) | 4921 | void wlc_print_txstatus(tx_status_t *txs) |
4922 | { | 4922 | { |
4923 | #if defined(BCMDBG) | 4923 | #if defined(BCMDBG) |
4924 | uint16 s = txs->status; | 4924 | u16 s = txs->status; |
4925 | uint16 ackphyrxsh = txs->ackphyrxsh; | 4925 | u16 ackphyrxsh = txs->ackphyrxsh; |
4926 | 4926 | ||
4927 | printf("\ntxpkt (MPDU) Complete\n"); | 4927 | printf("\ntxpkt (MPDU) Complete\n"); |
4928 | 4928 | ||
@@ -4949,9 +4949,9 @@ void wlc_statsupd(wlc_info_t *wlc) | |||
4949 | { | 4949 | { |
4950 | int i; | 4950 | int i; |
4951 | #ifdef BCMDBG | 4951 | #ifdef BCMDBG |
4952 | uint16 delta; | 4952 | u16 delta; |
4953 | uint16 rxf0ovfl; | 4953 | u16 rxf0ovfl; |
4954 | uint16 txfunfl[NFIFO]; | 4954 | u16 txfunfl[NFIFO]; |
4955 | #endif /* BCMDBG */ | 4955 | #endif /* BCMDBG */ |
4956 | 4956 | ||
4957 | /* if driver down, make no sense to update stats */ | 4957 | /* if driver down, make no sense to update stats */ |
@@ -4969,7 +4969,7 @@ void wlc_statsupd(wlc_info_t *wlc) | |||
4969 | 4969 | ||
4970 | #ifdef BCMDBG | 4970 | #ifdef BCMDBG |
4971 | /* check for rx fifo 0 overflow */ | 4971 | /* check for rx fifo 0 overflow */ |
4972 | delta = (uint16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl); | 4972 | delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl); |
4973 | if (delta) | 4973 | if (delta) |
4974 | WL_ERROR(("wl%d: %u rx fifo 0 overflows!\n", wlc->pub->unit, | 4974 | WL_ERROR(("wl%d: %u rx fifo 0 overflows!\n", wlc->pub->unit, |
4975 | delta)); | 4975 | delta)); |
@@ -4977,7 +4977,7 @@ void wlc_statsupd(wlc_info_t *wlc) | |||
4977 | /* check for tx fifo underflows */ | 4977 | /* check for tx fifo underflows */ |
4978 | for (i = 0; i < NFIFO; i++) { | 4978 | for (i = 0; i < NFIFO; i++) { |
4979 | delta = | 4979 | delta = |
4980 | (uint16) (wlc->core->macstat_snapshot->txfunfl[i] - | 4980 | (u16) (wlc->core->macstat_snapshot->txfunfl[i] - |
4981 | txfunfl[i]); | 4981 | txfunfl[i]); |
4982 | if (delta) | 4982 | if (delta) |
4983 | WL_ERROR(("wl%d: %u tx fifo %d underflows!\n", | 4983 | WL_ERROR(("wl%d: %u tx fifo %d underflows!\n", |
@@ -5027,7 +5027,7 @@ void wlc_statsupd(wlc_info_t *wlc) | |||
5027 | WLCNTADD(wlc->pub->_cnt->rxerror, wlc->pub->_cnt->rxuflo[i]); | 5027 | WLCNTADD(wlc->pub->_cnt->rxerror, wlc->pub->_cnt->rxuflo[i]); |
5028 | } | 5028 | } |
5029 | 5029 | ||
5030 | bool wlc_chipmatch(uint16 vendor, uint16 device) | 5030 | bool wlc_chipmatch(u16 vendor, u16 device) |
5031 | { | 5031 | { |
5032 | if (vendor != VENDOR_BROADCOM) { | 5032 | if (vendor != VENDOR_BROADCOM) { |
5033 | WL_ERROR(("wlc_chipmatch: unknown vendor id %04x\n", vendor)); | 5033 | WL_ERROR(("wlc_chipmatch: unknown vendor id %04x\n", vendor)); |
@@ -5049,32 +5049,32 @@ bool wlc_chipmatch(uint16 vendor, uint16 device) | |||
5049 | #if defined(BCMDBG) | 5049 | #if defined(BCMDBG) |
5050 | void wlc_print_txdesc(d11txh_t *txh) | 5050 | void wlc_print_txdesc(d11txh_t *txh) |
5051 | { | 5051 | { |
5052 | uint16 mtcl = ltoh16(txh->MacTxControlLow); | 5052 | u16 mtcl = ltoh16(txh->MacTxControlLow); |
5053 | uint16 mtch = ltoh16(txh->MacTxControlHigh); | 5053 | u16 mtch = ltoh16(txh->MacTxControlHigh); |
5054 | uint16 mfc = ltoh16(txh->MacFrameControl); | 5054 | u16 mfc = ltoh16(txh->MacFrameControl); |
5055 | uint16 tfest = ltoh16(txh->TxFesTimeNormal); | 5055 | u16 tfest = ltoh16(txh->TxFesTimeNormal); |
5056 | uint16 ptcw = ltoh16(txh->PhyTxControlWord); | 5056 | u16 ptcw = ltoh16(txh->PhyTxControlWord); |
5057 | uint16 ptcw_1 = ltoh16(txh->PhyTxControlWord_1); | 5057 | u16 ptcw_1 = ltoh16(txh->PhyTxControlWord_1); |
5058 | uint16 ptcw_1_Fbr = ltoh16(txh->PhyTxControlWord_1_Fbr); | 5058 | u16 ptcw_1_Fbr = ltoh16(txh->PhyTxControlWord_1_Fbr); |
5059 | uint16 ptcw_1_Rts = ltoh16(txh->PhyTxControlWord_1_Rts); | 5059 | u16 ptcw_1_Rts = ltoh16(txh->PhyTxControlWord_1_Rts); |
5060 | uint16 ptcw_1_FbrRts = ltoh16(txh->PhyTxControlWord_1_FbrRts); | 5060 | u16 ptcw_1_FbrRts = ltoh16(txh->PhyTxControlWord_1_FbrRts); |
5061 | uint16 mainrates = ltoh16(txh->MainRates); | 5061 | u16 mainrates = ltoh16(txh->MainRates); |
5062 | uint16 xtraft = ltoh16(txh->XtraFrameTypes); | 5062 | u16 xtraft = ltoh16(txh->XtraFrameTypes); |
5063 | u8 *iv = txh->IV; | 5063 | u8 *iv = txh->IV; |
5064 | u8 *ra = txh->TxFrameRA; | 5064 | u8 *ra = txh->TxFrameRA; |
5065 | uint16 tfestfb = ltoh16(txh->TxFesTimeFallback); | 5065 | u16 tfestfb = ltoh16(txh->TxFesTimeFallback); |
5066 | u8 *rtspfb = txh->RTSPLCPFallback; | 5066 | u8 *rtspfb = txh->RTSPLCPFallback; |
5067 | uint16 rtsdfb = ltoh16(txh->RTSDurFallback); | 5067 | u16 rtsdfb = ltoh16(txh->RTSDurFallback); |
5068 | u8 *fragpfb = txh->FragPLCPFallback; | 5068 | u8 *fragpfb = txh->FragPLCPFallback; |
5069 | uint16 fragdfb = ltoh16(txh->FragDurFallback); | 5069 | u16 fragdfb = ltoh16(txh->FragDurFallback); |
5070 | uint16 mmodelen = ltoh16(txh->MModeLen); | 5070 | u16 mmodelen = ltoh16(txh->MModeLen); |
5071 | uint16 mmodefbrlen = ltoh16(txh->MModeFbrLen); | 5071 | u16 mmodefbrlen = ltoh16(txh->MModeFbrLen); |
5072 | uint16 tfid = ltoh16(txh->TxFrameID); | 5072 | u16 tfid = ltoh16(txh->TxFrameID); |
5073 | uint16 txs = ltoh16(txh->TxStatus); | 5073 | u16 txs = ltoh16(txh->TxStatus); |
5074 | uint16 mnmpdu = ltoh16(txh->MaxNMpdus); | 5074 | u16 mnmpdu = ltoh16(txh->MaxNMpdus); |
5075 | uint16 mabyte = ltoh16(txh->MaxABytes_MRT); | 5075 | u16 mabyte = ltoh16(txh->MaxABytes_MRT); |
5076 | uint16 mabyte_f = ltoh16(txh->MaxABytes_FBR); | 5076 | u16 mabyte_f = ltoh16(txh->MaxABytes_FBR); |
5077 | uint16 mmbyte = ltoh16(txh->MinMBytes); | 5077 | u16 mmbyte = ltoh16(txh->MinMBytes); |
5078 | 5078 | ||
5079 | u8 *rtsph = txh->RTSPhyHeader; | 5079 | u8 *rtsph = txh->RTSPhyHeader; |
5080 | struct dot11_rts_frame rts = txh->rts_frame; | 5080 | struct dot11_rts_frame rts = txh->rts_frame; |
@@ -5134,13 +5134,13 @@ void wlc_print_txdesc(d11txh_t *txh) | |||
5134 | #if defined(BCMDBG) | 5134 | #if defined(BCMDBG) |
5135 | void wlc_print_rxh(d11rxhdr_t *rxh) | 5135 | void wlc_print_rxh(d11rxhdr_t *rxh) |
5136 | { | 5136 | { |
5137 | uint16 len = rxh->RxFrameSize; | 5137 | u16 len = rxh->RxFrameSize; |
5138 | uint16 phystatus_0 = rxh->PhyRxStatus_0; | 5138 | u16 phystatus_0 = rxh->PhyRxStatus_0; |
5139 | uint16 phystatus_1 = rxh->PhyRxStatus_1; | 5139 | u16 phystatus_1 = rxh->PhyRxStatus_1; |
5140 | uint16 phystatus_2 = rxh->PhyRxStatus_2; | 5140 | u16 phystatus_2 = rxh->PhyRxStatus_2; |
5141 | uint16 phystatus_3 = rxh->PhyRxStatus_3; | 5141 | u16 phystatus_3 = rxh->PhyRxStatus_3; |
5142 | uint16 macstatus1 = rxh->RxStatus1; | 5142 | u16 macstatus1 = rxh->RxStatus1; |
5143 | uint16 macstatus2 = rxh->RxStatus2; | 5143 | u16 macstatus2 = rxh->RxStatus2; |
5144 | char flagstr[64]; | 5144 | char flagstr[64]; |
5145 | char lenbuf[20]; | 5145 | char lenbuf[20]; |
5146 | static const bcm_bit_desc_t macstat_flags[] = { | 5146 | static const bcm_bit_desc_t macstat_flags[] = { |
@@ -5197,7 +5197,7 @@ int wlc_format_ssid(char *buf, const unsigned char ssid[], uint ssid_len) | |||
5197 | } | 5197 | } |
5198 | #endif /* defined(BCMDBG) */ | 5198 | #endif /* defined(BCMDBG) */ |
5199 | 5199 | ||
5200 | uint16 wlc_rate_shm_offset(wlc_info_t *wlc, u8 rate) | 5200 | u16 wlc_rate_shm_offset(wlc_info_t *wlc, u8 rate) |
5201 | { | 5201 | { |
5202 | return wlc_bmac_rate_shm_offset(wlc->hw, rate); | 5202 | return wlc_bmac_rate_shm_offset(wlc->hw, rate); |
5203 | } | 5203 | } |
@@ -5339,7 +5339,7 @@ wlc_sendpkt_mac80211(wlc_info_t *wlc, void *sdu, struct ieee80211_hw *hw) | |||
5339 | void *pkt; | 5339 | void *pkt; |
5340 | struct scb *scb = &global_scb; | 5340 | struct scb *scb = &global_scb; |
5341 | struct dot11_header *d11_header = (struct dot11_header *)PKTDATA(sdu); | 5341 | struct dot11_header *d11_header = (struct dot11_header *)PKTDATA(sdu); |
5342 | uint16 type, fc; | 5342 | u16 type, fc; |
5343 | 5343 | ||
5344 | ASSERT(sdu); | 5344 | ASSERT(sdu); |
5345 | 5345 | ||
@@ -5371,7 +5371,7 @@ void BCMFASTPATH wlc_send_q(wlc_info_t *wlc, wlc_txq_info_t *qi) | |||
5371 | { | 5371 | { |
5372 | void *pkt[DOT11_MAXNUMFRAGS]; | 5372 | void *pkt[DOT11_MAXNUMFRAGS]; |
5373 | int prec; | 5373 | int prec; |
5374 | uint16 prec_map; | 5374 | u16 prec_map; |
5375 | int err = 0, i, count; | 5375 | int err = 0, i, count; |
5376 | uint fifo; | 5376 | uint fifo; |
5377 | struct pktq *q = &qi->q; | 5377 | struct pktq *q = &qi->q; |
@@ -5441,10 +5441,10 @@ void BCMFASTPATH wlc_send_q(wlc_info_t *wlc, wlc_txq_info_t *qi) | |||
5441 | * Generate frame ID for a BCMC packet. The frag field is not used | 5441 | * Generate frame ID for a BCMC packet. The frag field is not used |
5442 | * for MC frames so is used as part of the sequence number. | 5442 | * for MC frames so is used as part of the sequence number. |
5443 | */ | 5443 | */ |
5444 | static inline uint16 | 5444 | static inline u16 |
5445 | bcmc_fid_generate(wlc_info_t *wlc, wlc_bsscfg_t *bsscfg, d11txh_t *txh) | 5445 | bcmc_fid_generate(wlc_info_t *wlc, wlc_bsscfg_t *bsscfg, d11txh_t *txh) |
5446 | { | 5446 | { |
5447 | uint16 frameid; | 5447 | u16 frameid; |
5448 | 5448 | ||
5449 | frameid = ltoh16(txh->TxFrameID) & ~(TXFID_SEQ_MASK | TXFID_QUEUE_MASK); | 5449 | frameid = ltoh16(txh->TxFrameID) & ~(TXFID_SEQ_MASK | TXFID_QUEUE_MASK); |
5450 | frameid |= | 5450 | frameid |= |
@@ -5458,7 +5458,7 @@ bcmc_fid_generate(wlc_info_t *wlc, wlc_bsscfg_t *bsscfg, d11txh_t *txh) | |||
5458 | void BCMFASTPATH | 5458 | void BCMFASTPATH |
5459 | wlc_txfifo(wlc_info_t *wlc, uint fifo, void *p, bool commit, s8 txpktpend) | 5459 | wlc_txfifo(wlc_info_t *wlc, uint fifo, void *p, bool commit, s8 txpktpend) |
5460 | { | 5460 | { |
5461 | uint16 frameid = INVALIDFID; | 5461 | u16 frameid = INVALIDFID; |
5462 | d11txh_t *txh; | 5462 | d11txh_t *txh; |
5463 | 5463 | ||
5464 | ASSERT(fifo < NFIFO); | 5464 | ASSERT(fifo < NFIFO); |
@@ -5502,10 +5502,10 @@ wlc_txfifo(wlc_info_t *wlc, uint fifo, void *p, bool commit, s8 txpktpend) | |||
5502 | #endif /* WLC_HIGH_ONLY */ | 5502 | #endif /* WLC_HIGH_ONLY */ |
5503 | } | 5503 | } |
5504 | 5504 | ||
5505 | static uint16 | 5505 | static u16 |
5506 | wlc_compute_airtime(wlc_info_t *wlc, ratespec_t rspec, uint length) | 5506 | wlc_compute_airtime(wlc_info_t *wlc, ratespec_t rspec, uint length) |
5507 | { | 5507 | { |
5508 | uint16 usec = 0; | 5508 | u16 usec = 0; |
5509 | uint mac_rate = RSPEC2RATE(rspec); | 5509 | uint mac_rate = RSPEC2RATE(rspec); |
5510 | uint nsyms; | 5510 | uint nsyms; |
5511 | 5511 | ||
@@ -5521,7 +5521,7 @@ wlc_compute_airtime(wlc_info_t *wlc, ratespec_t rspec, uint length) | |||
5521 | nsyms = CEIL((length * 8), (mac_rate * 2)); | 5521 | nsyms = CEIL((length * 8), (mac_rate * 2)); |
5522 | 5522 | ||
5523 | /* usec = symbols * usec/symbol */ | 5523 | /* usec = symbols * usec/symbol */ |
5524 | usec = (uint16) (nsyms * APHY_SYMBOL_TIME); | 5524 | usec = (u16) (nsyms * APHY_SYMBOL_TIME); |
5525 | return usec; | 5525 | return usec; |
5526 | } else { | 5526 | } else { |
5527 | switch (mac_rate) { | 5527 | switch (mac_rate) { |
@@ -5609,7 +5609,7 @@ wlc_compute_ofdm_plcp(ratespec_t rspec, uint32 length, u8 *plcp) | |||
5609 | 5609 | ||
5610 | static void wlc_cck_plcp_set(int rate_500, uint length, u8 *plcp) | 5610 | static void wlc_cck_plcp_set(int rate_500, uint length, u8 *plcp) |
5611 | { | 5611 | { |
5612 | uint16 usec = 0; | 5612 | u16 usec = 0; |
5613 | u8 le = 0; | 5613 | u8 le = 0; |
5614 | 5614 | ||
5615 | switch (rate_500) { | 5615 | switch (rate_500) { |
@@ -5643,7 +5643,7 @@ static void wlc_cck_plcp_set(int rate_500, uint length, u8 *plcp) | |||
5643 | plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */ | 5643 | plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */ |
5644 | /* PLCP service byte */ | 5644 | /* PLCP service byte */ |
5645 | plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED); | 5645 | plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED); |
5646 | /* PLCP length uint16, little endian */ | 5646 | /* PLCP length u16, little endian */ |
5647 | plcp[2] = usec & 0xff; | 5647 | plcp[2] = usec & 0xff; |
5648 | plcp[3] = (usec >> 8) & 0xff; | 5648 | plcp[3] = (usec >> 8) & 0xff; |
5649 | /* PLCP CRC16 */ | 5649 | /* PLCP CRC16 */ |
@@ -5671,16 +5671,16 @@ static void wlc_compute_cck_plcp(ratespec_t rspec, uint length, u8 *plcp) | |||
5671 | * next_frag_len next MPDU length in bytes | 5671 | * next_frag_len next MPDU length in bytes |
5672 | * preamble_type use short/GF or long/MM PLCP header | 5672 | * preamble_type use short/GF or long/MM PLCP header |
5673 | */ | 5673 | */ |
5674 | static uint16 BCMFASTPATH | 5674 | static u16 BCMFASTPATH |
5675 | wlc_compute_frame_dur(wlc_info_t *wlc, ratespec_t rate, u8 preamble_type, | 5675 | wlc_compute_frame_dur(wlc_info_t *wlc, ratespec_t rate, u8 preamble_type, |
5676 | uint next_frag_len) | 5676 | uint next_frag_len) |
5677 | { | 5677 | { |
5678 | uint16 dur, sifs; | 5678 | u16 dur, sifs; |
5679 | 5679 | ||
5680 | sifs = SIFS(wlc->band); | 5680 | sifs = SIFS(wlc->band); |
5681 | 5681 | ||
5682 | dur = sifs; | 5682 | dur = sifs; |
5683 | dur += (uint16) wlc_calc_ack_time(wlc, rate, preamble_type); | 5683 | dur += (u16) wlc_calc_ack_time(wlc, rate, preamble_type); |
5684 | 5684 | ||
5685 | if (next_frag_len) { | 5685 | if (next_frag_len) { |
5686 | /* Double the current DUR to get 2 SIFS + 2 ACKs */ | 5686 | /* Double the current DUR to get 2 SIFS + 2 ACKs */ |
@@ -5688,7 +5688,7 @@ wlc_compute_frame_dur(wlc_info_t *wlc, ratespec_t rate, u8 preamble_type, | |||
5688 | /* add another SIFS and the frag time */ | 5688 | /* add another SIFS and the frag time */ |
5689 | dur += sifs; | 5689 | dur += sifs; |
5690 | dur += | 5690 | dur += |
5691 | (uint16) wlc_calc_frame_time(wlc, rate, preamble_type, | 5691 | (u16) wlc_calc_frame_time(wlc, rate, preamble_type, |
5692 | next_frag_len); | 5692 | next_frag_len); |
5693 | } | 5693 | } |
5694 | return dur; | 5694 | return dur; |
@@ -5705,39 +5705,39 @@ wlc_compute_frame_dur(wlc_info_t *wlc, ratespec_t rate, u8 preamble_type, | |||
5705 | * rate next MPDU rate in unit of 500kbps | 5705 | * rate next MPDU rate in unit of 500kbps |
5706 | * frame_len next MPDU frame length in bytes | 5706 | * frame_len next MPDU frame length in bytes |
5707 | */ | 5707 | */ |
5708 | uint16 BCMFASTPATH | 5708 | u16 BCMFASTPATH |
5709 | wlc_compute_rtscts_dur(wlc_info_t *wlc, bool cts_only, ratespec_t rts_rate, | 5709 | wlc_compute_rtscts_dur(wlc_info_t *wlc, bool cts_only, ratespec_t rts_rate, |
5710 | ratespec_t frame_rate, u8 rts_preamble_type, | 5710 | ratespec_t frame_rate, u8 rts_preamble_type, |
5711 | u8 frame_preamble_type, uint frame_len, bool ba) | 5711 | u8 frame_preamble_type, uint frame_len, bool ba) |
5712 | { | 5712 | { |
5713 | uint16 dur, sifs; | 5713 | u16 dur, sifs; |
5714 | 5714 | ||
5715 | sifs = SIFS(wlc->band); | 5715 | sifs = SIFS(wlc->band); |
5716 | 5716 | ||
5717 | if (!cts_only) { /* RTS/CTS */ | 5717 | if (!cts_only) { /* RTS/CTS */ |
5718 | dur = 3 * sifs; | 5718 | dur = 3 * sifs; |
5719 | dur += | 5719 | dur += |
5720 | (uint16) wlc_calc_cts_time(wlc, rts_rate, | 5720 | (u16) wlc_calc_cts_time(wlc, rts_rate, |
5721 | rts_preamble_type); | 5721 | rts_preamble_type); |
5722 | } else { /* CTS-TO-SELF */ | 5722 | } else { /* CTS-TO-SELF */ |
5723 | dur = 2 * sifs; | 5723 | dur = 2 * sifs; |
5724 | } | 5724 | } |
5725 | 5725 | ||
5726 | dur += | 5726 | dur += |
5727 | (uint16) wlc_calc_frame_time(wlc, frame_rate, frame_preamble_type, | 5727 | (u16) wlc_calc_frame_time(wlc, frame_rate, frame_preamble_type, |
5728 | frame_len); | 5728 | frame_len); |
5729 | if (ba) | 5729 | if (ba) |
5730 | dur += | 5730 | dur += |
5731 | (uint16) wlc_calc_ba_time(wlc, frame_rate, | 5731 | (u16) wlc_calc_ba_time(wlc, frame_rate, |
5732 | WLC_SHORT_PREAMBLE); | 5732 | WLC_SHORT_PREAMBLE); |
5733 | else | 5733 | else |
5734 | dur += | 5734 | dur += |
5735 | (uint16) wlc_calc_ack_time(wlc, frame_rate, | 5735 | (u16) wlc_calc_ack_time(wlc, frame_rate, |
5736 | frame_preamble_type); | 5736 | frame_preamble_type); |
5737 | return dur; | 5737 | return dur; |
5738 | } | 5738 | } |
5739 | 5739 | ||
5740 | static bool wlc_phy_rspec_check(wlc_info_t *wlc, uint16 bw, ratespec_t rspec) | 5740 | static bool wlc_phy_rspec_check(wlc_info_t *wlc, u16 bw, ratespec_t rspec) |
5741 | { | 5741 | { |
5742 | if (IS_MCS(rspec)) { | 5742 | if (IS_MCS(rspec)) { |
5743 | uint mcs = rspec & RSPEC_RATE_MASK; | 5743 | uint mcs = rspec & RSPEC_RATE_MASK; |
@@ -5763,10 +5763,10 @@ static bool wlc_phy_rspec_check(wlc_info_t *wlc, uint16 bw, ratespec_t rspec) | |||
5763 | return TRUE; | 5763 | return TRUE; |
5764 | } | 5764 | } |
5765 | 5765 | ||
5766 | uint16 BCMFASTPATH wlc_phytxctl1_calc(wlc_info_t *wlc, ratespec_t rspec) | 5766 | u16 BCMFASTPATH wlc_phytxctl1_calc(wlc_info_t *wlc, ratespec_t rspec) |
5767 | { | 5767 | { |
5768 | uint16 phyctl1 = 0; | 5768 | u16 phyctl1 = 0; |
5769 | uint16 bw; | 5769 | u16 bw; |
5770 | 5770 | ||
5771 | if (WLCISLCNPHY(wlc->band)) { | 5771 | if (WLCISLCNPHY(wlc->band)) { |
5772 | bw = PHY_TXC1_BW_20MHZ; | 5772 | bw = PHY_TXC1_BW_20MHZ; |
@@ -5823,7 +5823,7 @@ uint16 BCMFASTPATH wlc_phytxctl1_calc(wlc_info_t *wlc, ratespec_t rspec) | |||
5823 | 5823 | ||
5824 | ratespec_t BCMFASTPATH | 5824 | ratespec_t BCMFASTPATH |
5825 | wlc_rspec_to_rts_rspec(wlc_info_t *wlc, ratespec_t rspec, bool use_rspec, | 5825 | wlc_rspec_to_rts_rspec(wlc_info_t *wlc, ratespec_t rspec, bool use_rspec, |
5826 | uint16 mimo_ctlchbw) | 5826 | u16 mimo_ctlchbw) |
5827 | { | 5827 | { |
5828 | ratespec_t rts_rspec = 0; | 5828 | ratespec_t rts_rspec = 0; |
5829 | 5829 | ||
@@ -5877,7 +5877,7 @@ wlc_rspec_to_rts_rspec(wlc_info_t *wlc, ratespec_t rspec, bool use_rspec, | |||
5877 | * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes) | 5877 | * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes) |
5878 | * | 5878 | * |
5879 | */ | 5879 | */ |
5880 | static uint16 BCMFASTPATH | 5880 | static u16 BCMFASTPATH |
5881 | wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | 5881 | wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, |
5882 | void *p, struct scb *scb, uint frag, | 5882 | void *p, struct scb *scb, uint frag, |
5883 | uint nfrags, uint queue, uint next_frag_len, | 5883 | uint nfrags, uint queue, uint next_frag_len, |
@@ -5888,8 +5888,8 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
5888 | u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN]; | 5888 | u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN]; |
5889 | osl_t *osh; | 5889 | osl_t *osh; |
5890 | int len, phylen, rts_phylen; | 5890 | int len, phylen, rts_phylen; |
5891 | uint16 fc, type, frameid, mch, phyctl, xfts, mainrates; | 5891 | u16 fc, type, frameid, mch, phyctl, xfts, mainrates; |
5892 | uint16 seq = 0, mcl = 0, status = 0; | 5892 | u16 seq = 0, mcl = 0, status = 0; |
5893 | ratespec_t rspec[2] = { WLC_RATE_1M, WLC_RATE_1M }, rts_rspec[2] = { | 5893 | ratespec_t rspec[2] = { WLC_RATE_1M, WLC_RATE_1M }, rts_rspec[2] = { |
5894 | WLC_RATE_1M, WLC_RATE_1M}; | 5894 | WLC_RATE_1M, WLC_RATE_1M}; |
5895 | bool use_rts = FALSE; | 5895 | bool use_rts = FALSE; |
@@ -5904,19 +5904,19 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
5904 | uint ac; | 5904 | uint ac; |
5905 | uint32 rate_val[2]; | 5905 | uint32 rate_val[2]; |
5906 | bool hwtkmic = FALSE; | 5906 | bool hwtkmic = FALSE; |
5907 | uint16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; | 5907 | u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; |
5908 | #ifdef WLANTSEL | 5908 | #ifdef WLANTSEL |
5909 | #define ANTCFG_NONE 0xFF | 5909 | #define ANTCFG_NONE 0xFF |
5910 | u8 antcfg = ANTCFG_NONE; | 5910 | u8 antcfg = ANTCFG_NONE; |
5911 | u8 fbantcfg = ANTCFG_NONE; | 5911 | u8 fbantcfg = ANTCFG_NONE; |
5912 | #endif | 5912 | #endif |
5913 | uint phyctl1_stf = 0; | 5913 | uint phyctl1_stf = 0; |
5914 | uint16 durid = 0; | 5914 | u16 durid = 0; |
5915 | struct ieee80211_tx_rate *txrate[2]; | 5915 | struct ieee80211_tx_rate *txrate[2]; |
5916 | int k; | 5916 | int k; |
5917 | struct ieee80211_tx_info *tx_info; | 5917 | struct ieee80211_tx_info *tx_info; |
5918 | bool is_mcs[2]; | 5918 | bool is_mcs[2]; |
5919 | uint16 mimo_txbw; | 5919 | u16 mimo_txbw; |
5920 | u8 mimo_preamble_type; | 5920 | u8 mimo_preamble_type; |
5921 | 5921 | ||
5922 | frameid = 0; | 5922 | frameid = 0; |
@@ -6218,7 +6218,7 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6218 | } else if (use_rifs) { | 6218 | } else if (use_rifs) { |
6219 | /* NAV protect to end of next max packet size */ | 6219 | /* NAV protect to end of next max packet size */ |
6220 | durid = | 6220 | durid = |
6221 | (uint16) wlc_calc_frame_time(wlc, rspec[0], | 6221 | (u16) wlc_calc_frame_time(wlc, rspec[0], |
6222 | preamble_type[0], | 6222 | preamble_type[0], |
6223 | DOT11_MAX_FRAG_LEN); | 6223 | DOT11_MAX_FRAG_LEN); |
6224 | durid += RIFS_11N_TIME; | 6224 | durid += RIFS_11N_TIME; |
@@ -6268,7 +6268,7 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6268 | } | 6268 | } |
6269 | 6269 | ||
6270 | /* MacFrameControl */ | 6270 | /* MacFrameControl */ |
6271 | bcopy((char *)&h->fc, (char *)&txh->MacFrameControl, sizeof(uint16)); | 6271 | bcopy((char *)&h->fc, (char *)&txh->MacFrameControl, sizeof(u16)); |
6272 | 6272 | ||
6273 | txh->TxFesTimeNormal = htol16(0); | 6273 | txh->TxFesTimeNormal = htol16(0); |
6274 | 6274 | ||
@@ -6331,7 +6331,7 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6331 | } | 6331 | } |
6332 | 6332 | ||
6333 | /* RTS PLCP header */ | 6333 | /* RTS PLCP header */ |
6334 | ASSERT(ISALIGNED((uintptr) txh->RTSPhyHeader, sizeof(uint16))); | 6334 | ASSERT(ISALIGNED((uintptr) txh->RTSPhyHeader, sizeof(u16))); |
6335 | rts_plcp = txh->RTSPhyHeader; | 6335 | rts_plcp = txh->RTSPhyHeader; |
6336 | if (use_cts) | 6336 | if (use_cts) |
6337 | rts_phylen = DOT11_CTS_LEN + DOT11_FCS_LEN; | 6337 | rts_phylen = DOT11_CTS_LEN + DOT11_FCS_LEN; |
@@ -6364,7 +6364,7 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6364 | rts->fc = htol16(FC_CTS); | 6364 | rts->fc = htol16(FC_CTS); |
6365 | bcopy((char *)&h->a2, (char *)&rts->ra, ETHER_ADDR_LEN); | 6365 | bcopy((char *)&h->a2, (char *)&rts->ra, ETHER_ADDR_LEN); |
6366 | } else { | 6366 | } else { |
6367 | rts->fc = htol16((uint16) FC_RTS); | 6367 | rts->fc = htol16((u16) FC_RTS); |
6368 | bcopy((char *)&h->a1, (char *)&rts->ra, | 6368 | bcopy((char *)&h->a1, (char *)&rts->ra, |
6369 | 2 * ETHER_ADDR_LEN); | 6369 | 2 * ETHER_ADDR_LEN); |
6370 | } | 6370 | } |
@@ -6423,7 +6423,7 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6423 | 6423 | ||
6424 | /* PhyTxControlWord_1 */ | 6424 | /* PhyTxControlWord_1 */ |
6425 | if (WLC_PHY_11N_CAP(wlc->band)) { | 6425 | if (WLC_PHY_11N_CAP(wlc->band)) { |
6426 | uint16 phyctl1 = 0; | 6426 | u16 phyctl1 = 0; |
6427 | 6427 | ||
6428 | phyctl1 = wlc_phytxctl1_calc(wlc, rspec[0]); | 6428 | phyctl1 = wlc_phytxctl1_calc(wlc, rspec[0]); |
6429 | txh->PhyTxControlWord_1 = htol16(phyctl1); | 6429 | txh->PhyTxControlWord_1 = htol16(phyctl1); |
@@ -6443,13 +6443,13 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6443 | * it will be unnecessary if they are separated | 6443 | * it will be unnecessary if they are separated |
6444 | */ | 6444 | */ |
6445 | if (IS_MCS(rspec[0]) && (preamble_type[0] == WLC_MM_PREAMBLE)) { | 6445 | if (IS_MCS(rspec[0]) && (preamble_type[0] == WLC_MM_PREAMBLE)) { |
6446 | uint16 mmodelen = | 6446 | u16 mmodelen = |
6447 | wlc_calc_lsig_len(wlc, rspec[0], phylen); | 6447 | wlc_calc_lsig_len(wlc, rspec[0], phylen); |
6448 | txh->MModeLen = htol16(mmodelen); | 6448 | txh->MModeLen = htol16(mmodelen); |
6449 | } | 6449 | } |
6450 | 6450 | ||
6451 | if (IS_MCS(rspec[1]) && (preamble_type[1] == WLC_MM_PREAMBLE)) { | 6451 | if (IS_MCS(rspec[1]) && (preamble_type[1] == WLC_MM_PREAMBLE)) { |
6452 | uint16 mmodefbrlen = | 6452 | u16 mmodefbrlen = |
6453 | wlc_calc_lsig_len(wlc, rspec[1], phylen); | 6453 | wlc_calc_lsig_len(wlc, rspec[1], phylen); |
6454 | txh->MModeFbrLen = htol16(mmodefbrlen); | 6454 | txh->MModeFbrLen = htol16(mmodefbrlen); |
6455 | } | 6455 | } |
@@ -6506,9 +6506,9 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6506 | preamble_type[1], 0); | 6506 | preamble_type[1], 0); |
6507 | } | 6507 | } |
6508 | /* NEED to set TxFesTimeNormal (hard) */ | 6508 | /* NEED to set TxFesTimeNormal (hard) */ |
6509 | txh->TxFesTimeNormal = htol16((uint16) dur); | 6509 | txh->TxFesTimeNormal = htol16((u16) dur); |
6510 | /* NEED to set fallback rate version of TxFesTimeNormal (hard) */ | 6510 | /* NEED to set fallback rate version of TxFesTimeNormal (hard) */ |
6511 | txh->TxFesTimeFallback = htol16((uint16) dur_fallback); | 6511 | txh->TxFesTimeFallback = htol16((u16) dur_fallback); |
6512 | 6512 | ||
6513 | /* update txop byte threshold (txop minus intraframe overhead) */ | 6513 | /* update txop byte threshold (txop minus intraframe overhead) */ |
6514 | if (wlc->edcf_txop[ac] >= (dur - frag_dur)) { | 6514 | if (wlc->edcf_txop[ac] >= (dur - frag_dur)) { |
@@ -6532,9 +6532,9 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw, | |||
6532 | wlc->usr_fragthresh; | 6532 | wlc->usr_fragthresh; |
6533 | /* update the fragthresh and do txc update */ | 6533 | /* update the fragthresh and do txc update */ |
6534 | if (wlc->fragthresh[queue] != | 6534 | if (wlc->fragthresh[queue] != |
6535 | (uint16) newfragthresh) { | 6535 | (u16) newfragthresh) { |
6536 | wlc->fragthresh[queue] = | 6536 | wlc->fragthresh[queue] = |
6537 | (uint16) newfragthresh; | 6537 | (u16) newfragthresh; |
6538 | } | 6538 | } |
6539 | } | 6539 | } |
6540 | } else | 6540 | } else |
@@ -6764,8 +6764,8 @@ wlc_dotxstatus(wlc_info_t *wlc, tx_status_t *txs, uint32 frm_tx2) | |||
6764 | uint totlen, supr_status; | 6764 | uint totlen, supr_status; |
6765 | bool lastframe; | 6765 | bool lastframe; |
6766 | struct dot11_header *h; | 6766 | struct dot11_header *h; |
6767 | uint16 fc; | 6767 | u16 fc; |
6768 | uint16 mcl; | 6768 | u16 mcl; |
6769 | struct ieee80211_tx_info *tx_info; | 6769 | struct ieee80211_tx_info *tx_info; |
6770 | struct ieee80211_tx_rate *txrate; | 6770 | struct ieee80211_tx_rate *txrate; |
6771 | int i; | 6771 | int i; |
@@ -6854,7 +6854,7 @@ wlc_dotxstatus(wlc_info_t *wlc, tx_status_t *txs, uint32 frm_tx2) | |||
6854 | if (!lastframe) { | 6854 | if (!lastframe) { |
6855 | WL_ERROR(("Not last frame!\n")); | 6855 | WL_ERROR(("Not last frame!\n")); |
6856 | } else { | 6856 | } else { |
6857 | uint16 sfbl, lfbl; | 6857 | u16 sfbl, lfbl; |
6858 | ieee80211_tx_info_clear_status(tx_info); | 6858 | ieee80211_tx_info_clear_status(tx_info); |
6859 | if (queue < AC_COUNT) { | 6859 | if (queue < AC_COUNT) { |
6860 | sfbl = WLC_WME_RETRY_SFB_GET(wlc, wme_fifo2ac[queue]); | 6860 | sfbl = WLC_WME_RETRY_SFB_GET(wlc, wme_fifo2ac[queue]); |
@@ -6977,7 +6977,7 @@ uint32 wlc_calc_tbtt_offset(uint32 bp, uint32 tsf_h, uint32 tsf_l) | |||
6977 | * and | 6977 | * and |
6978 | * (X + Y) mod Z = ((X mod Z) + (Y mod Z)) mod Z | 6978 | * (X + Y) mod Z = ((X mod Z) + (Y mod Z)) mod Z |
6979 | * | 6979 | * |
6980 | * So, if BTk[n] = uint16 n [0,3] of BTk. | 6980 | * So, if BTk[n] = u16 n [0,3] of BTk. |
6981 | * BTk % BP = SUM((BTk[n] * 2^16n) % BP , 0<=n<4) % BP | 6981 | * BTk % BP = SUM((BTk[n] * 2^16n) % BP , 0<=n<4) % BP |
6982 | * and the SUM term can be broken down: | 6982 | * and the SUM term can be broken down: |
6983 | * (BTk[n] * 2^16n) % BP | 6983 | * (BTk[n] * 2^16n) % BP |
@@ -7222,7 +7222,7 @@ void BCMFASTPATH wlc_recv(wlc_info_t *wlc, void *p) | |||
7222 | d11rxhdr_t *rxh; | 7222 | d11rxhdr_t *rxh; |
7223 | struct dot11_header *h; | 7223 | struct dot11_header *h; |
7224 | osl_t *osh; | 7224 | osl_t *osh; |
7225 | uint16 fc; | 7225 | u16 fc; |
7226 | uint len; | 7226 | uint len; |
7227 | bool is_amsdu; | 7227 | bool is_amsdu; |
7228 | #ifdef BCMDBG | 7228 | #ifdef BCMDBG |
@@ -7313,7 +7313,7 @@ void BCMFASTPATH wlc_recv(wlc_info_t *wlc, void *p) | |||
7313 | * Formula given by HT PHY Spec v 1.13 | 7313 | * Formula given by HT PHY Spec v 1.13 |
7314 | * len = 3(nsyms + nstream + 3) - 3 | 7314 | * len = 3(nsyms + nstream + 3) - 3 |
7315 | */ | 7315 | */ |
7316 | uint16 BCMFASTPATH | 7316 | u16 BCMFASTPATH |
7317 | wlc_calc_lsig_len(wlc_info_t *wlc, ratespec_t ratespec, uint mac_len) | 7317 | wlc_calc_lsig_len(wlc_info_t *wlc, ratespec_t ratespec, uint mac_len) |
7318 | { | 7318 | { |
7319 | uint nsyms, len = 0, kNdps; | 7319 | uint nsyms, len = 0, kNdps; |
@@ -7350,7 +7350,7 @@ wlc_calc_lsig_len(wlc_info_t *wlc, ratespec_t ratespec, uint mac_len) | |||
7350 | len = (3 * nsyms) - 3; /* (-3) excluding service bits and tail bits */ | 7350 | len = (3 * nsyms) - 3; /* (-3) excluding service bits and tail bits */ |
7351 | } | 7351 | } |
7352 | 7352 | ||
7353 | return (uint16) len; | 7353 | return (u16) len; |
7354 | } | 7354 | } |
7355 | 7355 | ||
7356 | /* calculate frame duration of a given rate and length, return time in usec unit */ | 7356 | /* calculate frame duration of a given rate and length, return time in usec unit */ |
@@ -7609,8 +7609,8 @@ static void wlc_write_rate_shm(wlc_info_t *wlc, u8 rate, u8 basic_rate) | |||
7609 | { | 7609 | { |
7610 | u8 phy_rate, index; | 7610 | u8 phy_rate, index; |
7611 | u8 basic_phy_rate, basic_index; | 7611 | u8 basic_phy_rate, basic_index; |
7612 | uint16 dir_table, basic_table; | 7612 | u16 dir_table, basic_table; |
7613 | uint16 basic_ptr; | 7613 | u16 basic_ptr; |
7614 | 7614 | ||
7615 | /* Shared memory address for the table we are reading */ | 7615 | /* Shared memory address for the table we are reading */ |
7616 | dir_table = IS_OFDM(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B; | 7616 | dir_table = IS_OFDM(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B; |
@@ -7756,9 +7756,9 @@ void wlc_mod_prb_rsp_rate_table(wlc_info_t *wlc, uint frame_len) | |||
7756 | const wlc_rateset_t *rs_dflt; | 7756 | const wlc_rateset_t *rs_dflt; |
7757 | wlc_rateset_t rs; | 7757 | wlc_rateset_t rs; |
7758 | u8 rate; | 7758 | u8 rate; |
7759 | uint16 entry_ptr; | 7759 | u16 entry_ptr; |
7760 | u8 plcp[D11_PHY_HDR_LEN]; | 7760 | u8 plcp[D11_PHY_HDR_LEN]; |
7761 | uint16 dur, sifs; | 7761 | u16 dur, sifs; |
7762 | uint i; | 7762 | uint i; |
7763 | 7763 | ||
7764 | sifs = SIFS(wlc->band); | 7764 | sifs = SIFS(wlc->band); |
@@ -7780,20 +7780,20 @@ void wlc_mod_prb_rsp_rate_table(wlc_info_t *wlc, uint frame_len) | |||
7780 | 7780 | ||
7781 | /* Calculate the duration of the Probe Response frame plus SIFS for the MAC */ | 7781 | /* Calculate the duration of the Probe Response frame plus SIFS for the MAC */ |
7782 | dur = | 7782 | dur = |
7783 | (uint16) wlc_calc_frame_time(wlc, rate, WLC_LONG_PREAMBLE, | 7783 | (u16) wlc_calc_frame_time(wlc, rate, WLC_LONG_PREAMBLE, |
7784 | frame_len); | 7784 | frame_len); |
7785 | dur += sifs; | 7785 | dur += sifs; |
7786 | 7786 | ||
7787 | /* Update the SHM Rate Table entry Probe Response values */ | 7787 | /* Update the SHM Rate Table entry Probe Response values */ |
7788 | wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS, | 7788 | wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS, |
7789 | (uint16) (plcp[0] + (plcp[1] << 8))); | 7789 | (u16) (plcp[0] + (plcp[1] << 8))); |
7790 | wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS + 2, | 7790 | wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS + 2, |
7791 | (uint16) (plcp[2] + (plcp[3] << 8))); | 7791 | (u16) (plcp[2] + (plcp[3] << 8))); |
7792 | wlc_write_shm(wlc, entry_ptr + M_RT_PRS_DUR_POS, dur); | 7792 | wlc_write_shm(wlc, entry_ptr + M_RT_PRS_DUR_POS, dur); |
7793 | } | 7793 | } |
7794 | } | 7794 | } |
7795 | 7795 | ||
7796 | uint16 | 7796 | u16 |
7797 | wlc_compute_bcntsfoff(wlc_info_t *wlc, ratespec_t rspec, bool short_preamble, | 7797 | wlc_compute_bcntsfoff(wlc_info_t *wlc, ratespec_t rspec, bool short_preamble, |
7798 | bool phydelay) | 7798 | bool phydelay) |
7799 | { | 7799 | { |
@@ -7825,7 +7825,7 @@ wlc_compute_bcntsfoff(wlc_info_t *wlc, ratespec_t rspec, bool short_preamble, | |||
7825 | D11B_PHY_LPREHDR_TIME; | 7825 | D11B_PHY_LPREHDR_TIME; |
7826 | bcntsfoff += wlc_compute_airtime(wlc, rspec, DOT11_MAC_HDR_LEN); | 7826 | bcntsfoff += wlc_compute_airtime(wlc, rspec, DOT11_MAC_HDR_LEN); |
7827 | } | 7827 | } |
7828 | return (uint16) (bcntsfoff); | 7828 | return (u16) (bcntsfoff); |
7829 | } | 7829 | } |
7830 | 7830 | ||
7831 | /* Max buffering needed for beacon template/prb resp template is 142 bytes. | 7831 | /* Max buffering needed for beacon template/prb resp template is 142 bytes. |
@@ -7842,7 +7842,7 @@ wlc_compute_bcntsfoff(wlc_info_t *wlc, ratespec_t rspec, bool short_preamble, | |||
7842 | */ | 7842 | */ |
7843 | static void | 7843 | static void |
7844 | wlc_bcn_prb_template(wlc_info_t *wlc, uint type, ratespec_t bcn_rspec, | 7844 | wlc_bcn_prb_template(wlc_info_t *wlc, uint type, ratespec_t bcn_rspec, |
7845 | wlc_bsscfg_t *cfg, uint16 *buf, int *len) | 7845 | wlc_bsscfg_t *cfg, u16 *buf, int *len) |
7846 | { | 7846 | { |
7847 | cck_phy_hdr_t *plcp; | 7847 | cck_phy_hdr_t *plcp; |
7848 | struct dot11_management_header *h; | 7848 | struct dot11_management_header *h; |
@@ -7883,7 +7883,7 @@ wlc_bcn_prb_template(wlc_info_t *wlc, uint type, ratespec_t bcn_rspec, | |||
7883 | h = (struct dot11_management_header *)&plcp[1]; | 7883 | h = (struct dot11_management_header *)&plcp[1]; |
7884 | 7884 | ||
7885 | /* fill in 802.11 header */ | 7885 | /* fill in 802.11 header */ |
7886 | h->fc = htol16((uint16) type); | 7886 | h->fc = htol16((u16) type); |
7887 | 7887 | ||
7888 | /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */ | 7888 | /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */ |
7889 | /* A1 filled in by MAC for prb resp, broadcast for bcn */ | 7889 | /* A1 filled in by MAC for prb resp, broadcast for bcn */ |
@@ -7921,7 +7921,7 @@ void wlc_bss_update_beacon(wlc_info_t *wlc, wlc_bsscfg_t *cfg) | |||
7921 | 7921 | ||
7922 | if (MBSS_BCN_ENAB(cfg)) { /* Optimize: Some of if/else could be combined */ | 7922 | if (MBSS_BCN_ENAB(cfg)) { /* Optimize: Some of if/else could be combined */ |
7923 | } else if (HWBCN_ENAB(cfg)) { /* Hardware beaconing for this config */ | 7923 | } else if (HWBCN_ENAB(cfg)) { /* Hardware beaconing for this config */ |
7924 | uint16 bcn[BCN_TMPL_LEN / 2]; | 7924 | u16 bcn[BCN_TMPL_LEN / 2]; |
7925 | uint32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD; | 7925 | uint32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD; |
7926 | d11regs_t *regs = wlc->regs; | 7926 | d11regs_t *regs = wlc->regs; |
7927 | osl_t *osh = NULL; | 7927 | osl_t *osh = NULL; |
@@ -7977,7 +7977,7 @@ void wlc_update_beacon(wlc_info_t *wlc) | |||
7977 | void wlc_shm_ssid_upd(wlc_info_t *wlc, wlc_bsscfg_t *cfg) | 7977 | void wlc_shm_ssid_upd(wlc_info_t *wlc, wlc_bsscfg_t *cfg) |
7978 | { | 7978 | { |
7979 | u8 *ssidptr = cfg->SSID; | 7979 | u8 *ssidptr = cfg->SSID; |
7980 | uint16 base = M_SSID; | 7980 | u16 base = M_SSID; |
7981 | u8 ssidbuf[DOT11_MAX_SSID_LEN]; | 7981 | u8 ssidbuf[DOT11_MAX_SSID_LEN]; |
7982 | 7982 | ||
7983 | /* padding the ssid with zero and copy it into shm */ | 7983 | /* padding the ssid with zero and copy it into shm */ |
@@ -7987,7 +7987,7 @@ void wlc_shm_ssid_upd(wlc_info_t *wlc, wlc_bsscfg_t *cfg) | |||
7987 | wlc_copyto_shm(wlc, base, ssidbuf, DOT11_MAX_SSID_LEN); | 7987 | wlc_copyto_shm(wlc, base, ssidbuf, DOT11_MAX_SSID_LEN); |
7988 | 7988 | ||
7989 | if (!MBSS_BCN_ENAB(cfg)) | 7989 | if (!MBSS_BCN_ENAB(cfg)) |
7990 | wlc_write_shm(wlc, M_SSIDLEN, (uint16) cfg->SSID_len); | 7990 | wlc_write_shm(wlc, M_SSIDLEN, (u16) cfg->SSID_len); |
7991 | } | 7991 | } |
7992 | 7992 | ||
7993 | void wlc_update_probe_resp(wlc_info_t *wlc, bool suspend) | 7993 | void wlc_update_probe_resp(wlc_info_t *wlc, bool suspend) |
@@ -8005,7 +8005,7 @@ void wlc_update_probe_resp(wlc_info_t *wlc, bool suspend) | |||
8005 | void | 8005 | void |
8006 | wlc_bss_update_probe_resp(wlc_info_t *wlc, wlc_bsscfg_t *cfg, bool suspend) | 8006 | wlc_bss_update_probe_resp(wlc_info_t *wlc, wlc_bsscfg_t *cfg, bool suspend) |
8007 | { | 8007 | { |
8008 | uint16 prb_resp[BCN_TMPL_LEN / 2]; | 8008 | u16 prb_resp[BCN_TMPL_LEN / 2]; |
8009 | int len = BCN_TMPL_LEN; | 8009 | int len = BCN_TMPL_LEN; |
8010 | 8010 | ||
8011 | /* write the probe response to hardware, or save in the config structure */ | 8011 | /* write the probe response to hardware, or save in the config structure */ |
@@ -8023,7 +8023,7 @@ wlc_bss_update_probe_resp(wlc_info_t *wlc, wlc_bsscfg_t *cfg, bool suspend) | |||
8023 | (len + 3) & ~3, prb_resp); | 8023 | (len + 3) & ~3, prb_resp); |
8024 | 8024 | ||
8025 | /* write the length of the probe response frame (+PLCP/-FCS) */ | 8025 | /* write the length of the probe response frame (+PLCP/-FCS) */ |
8026 | wlc_write_shm(wlc, M_PRB_RESP_FRM_LEN, (uint16) len); | 8026 | wlc_write_shm(wlc, M_PRB_RESP_FRM_LEN, (u16) len); |
8027 | 8027 | ||
8028 | /* write the SSID and SSID length */ | 8028 | /* write the SSID and SSID length */ |
8029 | wlc_shm_ssid_upd(wlc, cfg); | 8029 | wlc_shm_ssid_upd(wlc, cfg); |
@@ -8034,7 +8034,7 @@ wlc_bss_update_probe_resp(wlc_info_t *wlc, wlc_bsscfg_t *cfg, bool suspend) | |||
8034 | * wlc_mod_prb_rsp_rate_table() by subtracting the PLCP len and adding the FCS. | 8034 | * wlc_mod_prb_rsp_rate_table() by subtracting the PLCP len and adding the FCS. |
8035 | */ | 8035 | */ |
8036 | len += (-D11_PHY_HDR_LEN + DOT11_FCS_LEN); | 8036 | len += (-D11_PHY_HDR_LEN + DOT11_FCS_LEN); |
8037 | wlc_mod_prb_rsp_rate_table(wlc, (uint16) len); | 8037 | wlc_mod_prb_rsp_rate_table(wlc, (u16) len); |
8038 | 8038 | ||
8039 | if (suspend) | 8039 | if (suspend) |
8040 | wlc_enable_mac(wlc); | 8040 | wlc_enable_mac(wlc); |
@@ -8051,7 +8051,7 @@ int wlc_prep_pdu(wlc_info_t *wlc, void *pdu, uint *fifop) | |||
8051 | d11txh_t *txh; | 8051 | d11txh_t *txh; |
8052 | struct dot11_header *h; | 8052 | struct dot11_header *h; |
8053 | struct scb *scb; | 8053 | struct scb *scb; |
8054 | uint16 fc; | 8054 | u16 fc; |
8055 | 8055 | ||
8056 | osh = wlc->osh; | 8056 | osh = wlc->osh; |
8057 | 8057 | ||
@@ -8339,12 +8339,12 @@ wlc_duty_cycle_set(wlc_info_t *wlc, int duty_cycle, bool isOFDM, | |||
8339 | idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle; | 8339 | idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle; |
8340 | /* Only write to shared memory when wl is up */ | 8340 | /* Only write to shared memory when wl is up */ |
8341 | if (writeToShm) | 8341 | if (writeToShm) |
8342 | wlc_write_shm(wlc, offset, (uint16) idle_busy_ratio_x_16); | 8342 | wlc_write_shm(wlc, offset, (u16) idle_busy_ratio_x_16); |
8343 | 8343 | ||
8344 | if (isOFDM) | 8344 | if (isOFDM) |
8345 | wlc->tx_duty_cycle_ofdm = (uint16) duty_cycle; | 8345 | wlc->tx_duty_cycle_ofdm = (u16) duty_cycle; |
8346 | else | 8346 | else |
8347 | wlc->tx_duty_cycle_cck = (uint16) duty_cycle; | 8347 | wlc->tx_duty_cycle_cck = (u16) duty_cycle; |
8348 | 8348 | ||
8349 | return BCME_OK; | 8349 | return BCME_OK; |
8350 | } | 8350 | } |
@@ -8354,8 +8354,8 @@ wlc_pktengtx(wlc_info_t *wlc, wl_pkteng_t *pkteng, u8 rate, | |||
8354 | struct ether_addr *sa, uint32 wait_delay) | 8354 | struct ether_addr *sa, uint32 wait_delay) |
8355 | { | 8355 | { |
8356 | bool suspend; | 8356 | bool suspend; |
8357 | uint16 val = M_PKTENG_MODE_TX; | 8357 | u16 val = M_PKTENG_MODE_TX; |
8358 | volatile uint16 frame_cnt_check; | 8358 | volatile u16 frame_cnt_check; |
8359 | u8 counter = 0; | 8359 | u8 counter = 0; |
8360 | 8360 | ||
8361 | wlc_bmac_set_deaf(wlc->hw, TRUE); | 8361 | wlc_bmac_set_deaf(wlc->hw, TRUE); |
@@ -8388,7 +8388,7 @@ wlc_pktengtx(wlc_info_t *wlc, wl_pkteng_t *pkteng, u8 rate, | |||
8388 | /* CTS frame */ | 8388 | /* CTS frame */ |
8389 | val |= M_PKTENG_MODE_TX_CTS; | 8389 | val |= M_PKTENG_MODE_TX_CTS; |
8390 | wlc_bmac_write_shm(wlc->hw, M_PKTENG_IFS, | 8390 | wlc_bmac_write_shm(wlc->hw, M_PKTENG_IFS, |
8391 | (uint16) pkteng->delay); | 8391 | (u16) pkteng->delay); |
8392 | wlc_bmac_write_shm(wlc->hw, M_PKTENG_CTRL, val); | 8392 | wlc_bmac_write_shm(wlc->hw, M_PKTENG_CTRL, val); |
8393 | } | 8393 | } |
8394 | 8394 | ||
@@ -8409,18 +8409,18 @@ wlc_pktengtx(wlc_info_t *wlc, wl_pkteng_t *pkteng, u8 rate, | |||
8409 | wlc_bmac_set_deaf(wlc->hw, FALSE); | 8409 | wlc_bmac_set_deaf(wlc->hw, FALSE); |
8410 | } | 8410 | } |
8411 | 8411 | ||
8412 | /* Read a single uint16 from shared memory. | 8412 | /* Read a single u16 from shared memory. |
8413 | * SHM 'offset' needs to be an even address | 8413 | * SHM 'offset' needs to be an even address |
8414 | */ | 8414 | */ |
8415 | uint16 wlc_read_shm(wlc_info_t *wlc, uint offset) | 8415 | u16 wlc_read_shm(wlc_info_t *wlc, uint offset) |
8416 | { | 8416 | { |
8417 | return wlc_bmac_read_shm(wlc->hw, offset); | 8417 | return wlc_bmac_read_shm(wlc->hw, offset); |
8418 | } | 8418 | } |
8419 | 8419 | ||
8420 | /* Write a single uint16 to shared memory. | 8420 | /* Write a single u16 to shared memory. |
8421 | * SHM 'offset' needs to be an even address | 8421 | * SHM 'offset' needs to be an even address |
8422 | */ | 8422 | */ |
8423 | void wlc_write_shm(wlc_info_t *wlc, uint offset, uint16 v) | 8423 | void wlc_write_shm(wlc_info_t *wlc, uint offset, u16 v) |
8424 | { | 8424 | { |
8425 | wlc_bmac_write_shm(wlc->hw, offset, v); | 8425 | wlc_bmac_write_shm(wlc->hw, offset, v); |
8426 | } | 8426 | } |
@@ -8429,7 +8429,7 @@ void wlc_write_shm(wlc_info_t *wlc, uint offset, uint16 v) | |||
8429 | * SHM 'offset' needs to be an even address and | 8429 | * SHM 'offset' needs to be an even address and |
8430 | * Range length 'len' must be an even number of bytes | 8430 | * Range length 'len' must be an even number of bytes |
8431 | */ | 8431 | */ |
8432 | void wlc_set_shm(wlc_info_t *wlc, uint offset, uint16 v, int len) | 8432 | void wlc_set_shm(wlc_info_t *wlc, uint offset, u16 v, int len) |
8433 | { | 8433 | { |
8434 | /* offset and len need to be even */ | 8434 | /* offset and len need to be even */ |
8435 | ASSERT((offset & 1) == 0); | 8435 | ASSERT((offset & 1) == 0); |
@@ -8484,12 +8484,12 @@ void wlc_corereset(wlc_info_t *wlc, uint32 flags) | |||
8484 | wlc_bmac_corereset(wlc->hw, flags); | 8484 | wlc_bmac_corereset(wlc->hw, flags); |
8485 | } | 8485 | } |
8486 | 8486 | ||
8487 | void wlc_mhf(wlc_info_t *wlc, u8 idx, uint16 mask, uint16 val, int bands) | 8487 | void wlc_mhf(wlc_info_t *wlc, u8 idx, u16 mask, u16 val, int bands) |
8488 | { | 8488 | { |
8489 | wlc_bmac_mhf(wlc->hw, idx, mask, val, bands); | 8489 | wlc_bmac_mhf(wlc->hw, idx, mask, val, bands); |
8490 | } | 8490 | } |
8491 | 8491 | ||
8492 | uint16 wlc_mhf_get(wlc_info_t *wlc, u8 idx, int bands) | 8492 | u16 wlc_mhf_get(wlc_info_t *wlc, u8 idx, int bands) |
8493 | { | 8493 | { |
8494 | return wlc_bmac_mhf_get(wlc->hw, idx, bands); | 8494 | return wlc_bmac_mhf_get(wlc->hw, idx, bands); |
8495 | } | 8495 | } |
@@ -8526,13 +8526,13 @@ void wlc_read_tsf(wlc_info_t *wlc, uint32 *tsf_l_ptr, uint32 *tsf_h_ptr) | |||
8526 | wlc_bmac_read_tsf(wlc->hw, tsf_l_ptr, tsf_h_ptr); | 8526 | wlc_bmac_read_tsf(wlc->hw, tsf_l_ptr, tsf_h_ptr); |
8527 | } | 8527 | } |
8528 | 8528 | ||
8529 | void wlc_set_cwmin(wlc_info_t *wlc, uint16 newmin) | 8529 | void wlc_set_cwmin(wlc_info_t *wlc, u16 newmin) |
8530 | { | 8530 | { |
8531 | wlc->band->CWmin = newmin; | 8531 | wlc->band->CWmin = newmin; |
8532 | wlc_bmac_set_cwmin(wlc->hw, newmin); | 8532 | wlc_bmac_set_cwmin(wlc->hw, newmin); |
8533 | } | 8533 | } |
8534 | 8534 | ||
8535 | void wlc_set_cwmax(wlc_info_t *wlc, uint16 newmax) | 8535 | void wlc_set_cwmax(wlc_info_t *wlc, u16 newmax) |
8536 | { | 8536 | { |
8537 | wlc->band->CWmax = newmax; | 8537 | wlc->band->CWmax = newmax; |
8538 | wlc_bmac_set_cwmax(wlc->hw, newmax); | 8538 | wlc_bmac_set_cwmax(wlc->hw, newmax); |
diff --git a/drivers/staging/brcm80211/sys/wlc_mac80211.h b/drivers/staging/brcm80211/sys/wlc_mac80211.h index 0b5c41f9b73..b936ca33215 100644 --- a/drivers/staging/brcm80211/sys/wlc_mac80211.h +++ b/drivers/staging/brcm80211/sys/wlc_mac80211.h | |||
@@ -267,12 +267,12 @@ typedef struct wlc_stf { | |||
267 | 267 | ||
268 | u8 ant_rx_ovr; /* rx antenna override */ | 268 | u8 ant_rx_ovr; /* rx antenna override */ |
269 | s8 txant; /* userTx antenna setting */ | 269 | s8 txant; /* userTx antenna setting */ |
270 | uint16 phytxant; /* phyTx antenna setting in txheader */ | 270 | u16 phytxant; /* phyTx antenna setting in txheader */ |
271 | 271 | ||
272 | u8 ss_opmode; /* singlestream Operational mode, 0:siso; 1:cdd */ | 272 | u8 ss_opmode; /* singlestream Operational mode, 0:siso; 1:cdd */ |
273 | bool ss_algosel_auto; /* if TRUE, use wlc->stf->ss_algo_channel; */ | 273 | bool ss_algosel_auto; /* if TRUE, use wlc->stf->ss_algo_channel; */ |
274 | /* else use wlc->band->stf->ss_mode_band; */ | 274 | /* else use wlc->band->stf->ss_mode_band; */ |
275 | uint16 ss_algo_channel; /* ss based on per-channel algo: 0: SISO, 1: CDD 2: STBC */ | 275 | u16 ss_algo_channel; /* ss based on per-channel algo: 0: SISO, 1: CDD 2: STBC */ |
276 | u8 no_cddstbc; /* stf override, 1: no CDD (or STBC) allowed */ | 276 | u8 no_cddstbc; /* stf override, 1: no CDD (or STBC) allowed */ |
277 | 277 | ||
278 | u8 rxchain_restore_delay; /* delay time to restore default rxchain */ | 278 | u8 rxchain_restore_delay; /* delay time to restore default rxchain */ |
@@ -330,10 +330,10 @@ typedef struct wlcband { | |||
330 | int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */ | 330 | int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */ |
331 | uint bandunit; /* bandstate[] index */ | 331 | uint bandunit; /* bandstate[] index */ |
332 | 332 | ||
333 | uint16 phytype; /* phytype */ | 333 | u16 phytype; /* phytype */ |
334 | uint16 phyrev; | 334 | u16 phyrev; |
335 | uint16 radioid; | 335 | u16 radioid; |
336 | uint16 radiorev; | 336 | u16 radiorev; |
337 | wlc_phy_t *pi; /* pointer to phy specific information */ | 337 | wlc_phy_t *pi; /* pointer to phy specific information */ |
338 | bool abgphy_encore; | 338 | bool abgphy_encore; |
339 | 339 | ||
@@ -352,9 +352,9 @@ typedef struct wlcband { | |||
352 | bool mimo_cap_40; /* 40 MHz cap enabled on this band */ | 352 | bool mimo_cap_40; /* 40 MHz cap enabled on this band */ |
353 | s8 antgain; /* antenna gain from srom */ | 353 | s8 antgain; /* antenna gain from srom */ |
354 | 354 | ||
355 | uint16 CWmin; /* The minimum size of contention window, in unit of aSlotTime */ | 355 | u16 CWmin; /* The minimum size of contention window, in unit of aSlotTime */ |
356 | uint16 CWmax; /* The maximum size of contention window, in unit of aSlotTime */ | 356 | u16 CWmax; /* The maximum size of contention window, in unit of aSlotTime */ |
357 | uint16 bcntsfoff; /* beacon tsf offset */ | 357 | u16 bcntsfoff; /* beacon tsf offset */ |
358 | } wlcband_t; | 358 | } wlcband_t; |
359 | 359 | ||
360 | /* generic function callback takes just one arg */ | 360 | /* generic function callback takes just one arg */ |
@@ -416,16 +416,16 @@ struct wlc_if { | |||
416 | typedef struct wlc_hwband { | 416 | typedef struct wlc_hwband { |
417 | int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */ | 417 | int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */ |
418 | uint bandunit; /* bandstate[] index */ | 418 | uint bandunit; /* bandstate[] index */ |
419 | uint16 mhfs[MHFMAX]; /* MHF array shadow */ | 419 | u16 mhfs[MHFMAX]; /* MHF array shadow */ |
420 | u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */ | 420 | u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */ |
421 | uint16 CWmin; | 421 | u16 CWmin; |
422 | uint16 CWmax; | 422 | u16 CWmax; |
423 | uint32 core_flags; | 423 | uint32 core_flags; |
424 | 424 | ||
425 | uint16 phytype; /* phytype */ | 425 | u16 phytype; /* phytype */ |
426 | uint16 phyrev; | 426 | u16 phyrev; |
427 | uint16 radioid; | 427 | u16 radioid; |
428 | uint16 radiorev; | 428 | u16 radiorev; |
429 | wlc_phy_t *pi; /* pointer to phy specific information */ | 429 | wlc_phy_t *pi; /* pointer to phy specific information */ |
430 | bool abgphy_encore; | 430 | bool abgphy_encore; |
431 | } wlc_hwband_t; | 431 | } wlc_hwband_t; |
@@ -446,16 +446,16 @@ struct wlc_hw_info { | |||
446 | uint unit; /* device instance number */ | 446 | uint unit; /* device instance number */ |
447 | 447 | ||
448 | /* version info */ | 448 | /* version info */ |
449 | uint16 vendorid; /* PCI vendor id */ | 449 | u16 vendorid; /* PCI vendor id */ |
450 | uint16 deviceid; /* PCI device id */ | 450 | u16 deviceid; /* PCI device id */ |
451 | uint corerev; /* core revision */ | 451 | uint corerev; /* core revision */ |
452 | u8 sromrev; /* version # of the srom */ | 452 | u8 sromrev; /* version # of the srom */ |
453 | uint16 boardrev; /* version # of particular board */ | 453 | u16 boardrev; /* version # of particular board */ |
454 | uint32 boardflags; /* Board specific flags from srom */ | 454 | uint32 boardflags; /* Board specific flags from srom */ |
455 | uint32 boardflags2; /* More board flags if sromrev >= 4 */ | 455 | uint32 boardflags2; /* More board flags if sromrev >= 4 */ |
456 | uint32 machwcap; /* MAC capabilities (corerev >= 13) */ | 456 | uint32 machwcap; /* MAC capabilities (corerev >= 13) */ |
457 | uint32 machwcap_backup; /* backup of machwcap (corerev >= 13) */ | 457 | uint32 machwcap_backup; /* backup of machwcap (corerev >= 13) */ |
458 | uint16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */ | 458 | u16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */ |
459 | 459 | ||
460 | si_t *sih; /* SB handle (cookie for siutils calls) */ | 460 | si_t *sih; /* SB handle (cookie for siutils calls) */ |
461 | char *vars; /* "environment" name=value */ | 461 | char *vars; /* "environment" name=value */ |
@@ -465,12 +465,12 @@ struct wlc_hw_info { | |||
465 | void *phy_sh; /* pointer to shared phy state */ | 465 | void *phy_sh; /* pointer to shared phy state */ |
466 | wlc_hwband_t *band; /* pointer to active per-band state */ | 466 | wlc_hwband_t *band; /* pointer to active per-band state */ |
467 | wlc_hwband_t *bandstate[MAXBANDS]; /* per-band state (one per phy/radio) */ | 467 | wlc_hwband_t *bandstate[MAXBANDS]; /* per-band state (one per phy/radio) */ |
468 | uint16 bmac_phytxant; /* cache of high phytxant state */ | 468 | u16 bmac_phytxant; /* cache of high phytxant state */ |
469 | bool shortslot; /* currently using 11g ShortSlot timing */ | 469 | bool shortslot; /* currently using 11g ShortSlot timing */ |
470 | uint16 SRL; /* 802.11 dot11ShortRetryLimit */ | 470 | u16 SRL; /* 802.11 dot11ShortRetryLimit */ |
471 | uint16 LRL; /* 802.11 dot11LongRetryLimit */ | 471 | u16 LRL; /* 802.11 dot11LongRetryLimit */ |
472 | uint16 SFBL; /* Short Frame Rate Fallback Limit */ | 472 | u16 SFBL; /* Short Frame Rate Fallback Limit */ |
473 | uint16 LFBL; /* Long Frame Rate Fallback Limit */ | 473 | u16 LFBL; /* Long Frame Rate Fallback Limit */ |
474 | 474 | ||
475 | bool up; /* d11 hardware up and running */ | 475 | bool up; /* d11 hardware up and running */ |
476 | uint now; /* # elapsed seconds */ | 476 | uint now; /* # elapsed seconds */ |
@@ -478,7 +478,7 @@ struct wlc_hw_info { | |||
478 | chanspec_t chanspec; /* bmac chanspec shadow */ | 478 | chanspec_t chanspec; /* bmac chanspec shadow */ |
479 | 479 | ||
480 | uint *txavail[NFIFO]; /* # tx descriptors available */ | 480 | uint *txavail[NFIFO]; /* # tx descriptors available */ |
481 | uint16 *xmtfifo_sz; /* fifo size in 256B for each xmt fifo */ | 481 | u16 *xmtfifo_sz; /* fifo size in 256B for each xmt fifo */ |
482 | 482 | ||
483 | mbool pllreq; /* pll requests to keep PLL on */ | 483 | mbool pllreq; /* pll requests to keep PLL on */ |
484 | 484 | ||
@@ -505,7 +505,7 @@ struct wlc_hw_info { | |||
505 | #ifdef WLC_LOW_ONLY | 505 | #ifdef WLC_LOW_ONLY |
506 | struct wl_timer *wdtimer; /* timer for watchdog routine */ | 506 | struct wl_timer *wdtimer; /* timer for watchdog routine */ |
507 | struct ether_addr orig_etheraddr; /* original hw ethernet address */ | 507 | struct ether_addr orig_etheraddr; /* original hw ethernet address */ |
508 | uint16 rpc_dngl_agg; /* rpc agg control for dongle */ | 508 | u16 rpc_dngl_agg; /* rpc agg control for dongle */ |
509 | uint32 mem_required_def; /* memory required to replenish RX DMA ring */ | 509 | uint32 mem_required_def; /* memory required to replenish RX DMA ring */ |
510 | uint32 mem_required_lower; /* memory required with lower RX bound */ | 510 | uint32 mem_required_lower; /* memory required with lower RX bound */ |
511 | uint32 mem_required_least; /* minimum memory requirement to handle RX */ | 511 | uint32 mem_required_least; /* minimum memory requirement to handle RX */ |
@@ -549,7 +549,7 @@ struct wlc_info { | |||
549 | 549 | ||
550 | /* clock */ | 550 | /* clock */ |
551 | int clkreq_override; /* setting for clkreq for PCIE : Auto, 0, 1 */ | 551 | int clkreq_override; /* setting for clkreq for PCIE : Auto, 0, 1 */ |
552 | uint16 fastpwrup_dly; /* time in us needed to bring up d11 fast clock */ | 552 | u16 fastpwrup_dly; /* time in us needed to bring up d11 fast clock */ |
553 | 553 | ||
554 | /* interrupt */ | 554 | /* interrupt */ |
555 | uint32 macintstatus; /* bit channel between isr and dpc */ | 555 | uint32 macintstatus; /* bit channel between isr and dpc */ |
@@ -595,8 +595,8 @@ struct wlc_info { | |||
595 | 595 | ||
596 | uint vars_size; /* size of vars, free vars on detach */ | 596 | uint vars_size; /* size of vars, free vars on detach */ |
597 | 597 | ||
598 | uint16 vendorid; /* PCI vendor id */ | 598 | u16 vendorid; /* PCI vendor id */ |
599 | uint16 deviceid; /* PCI device id */ | 599 | u16 deviceid; /* PCI device id */ |
600 | uint ucode_rev; /* microcode revision */ | 600 | uint ucode_rev; /* microcode revision */ |
601 | 601 | ||
602 | uint32 machwcap; /* MAC capabilities, BMAC shadow */ | 602 | uint32 machwcap; /* MAC capabilities, BMAC shadow */ |
@@ -667,18 +667,18 @@ struct wlc_info { | |||
667 | ac_bitmap_t wme_dp; /* Discard (oldest first) policy per AC */ | 667 | ac_bitmap_t wme_dp; /* Discard (oldest first) policy per AC */ |
668 | bool wme_apsd; /* enable Advanced Power Save Delivery */ | 668 | bool wme_apsd; /* enable Advanced Power Save Delivery */ |
669 | ac_bitmap_t wme_admctl; /* bit i set if AC i under admission control */ | 669 | ac_bitmap_t wme_admctl; /* bit i set if AC i under admission control */ |
670 | uint16 edcf_txop[AC_COUNT]; /* current txop for each ac */ | 670 | u16 edcf_txop[AC_COUNT]; /* current txop for each ac */ |
671 | wme_param_ie_t wme_param_ie; /* WME parameter info element, which on STA | 671 | wme_param_ie_t wme_param_ie; /* WME parameter info element, which on STA |
672 | * contains parameters in use locally, and on | 672 | * contains parameters in use locally, and on |
673 | * AP contains parameters advertised to STA | 673 | * AP contains parameters advertised to STA |
674 | * in beacons and assoc responses. | 674 | * in beacons and assoc responses. |
675 | */ | 675 | */ |
676 | bool wme_prec_queuing; /* enable/disable non-wme STA prec queuing */ | 676 | bool wme_prec_queuing; /* enable/disable non-wme STA prec queuing */ |
677 | uint16 wme_retries[AC_COUNT]; /* per-AC retry limits */ | 677 | u16 wme_retries[AC_COUNT]; /* per-AC retry limits */ |
678 | 678 | ||
679 | int vlan_mode; /* OK to use 802.1Q Tags (ON, OFF, AUTO) */ | 679 | int vlan_mode; /* OK to use 802.1Q Tags (ON, OFF, AUTO) */ |
680 | uint16 tx_prec_map; /* Precedence map based on HW FIFO space */ | 680 | u16 tx_prec_map; /* Precedence map based on HW FIFO space */ |
681 | uint16 fifo2prec_map[NFIFO]; /* pointer to fifo2_prec map based on WME */ | 681 | u16 fifo2prec_map[NFIFO]; /* pointer to fifo2_prec map based on WME */ |
682 | 682 | ||
683 | /* BSS Configurations */ | 683 | /* BSS Configurations */ |
684 | wlc_bsscfg_t *bsscfg[WLC_MAXBSSCFG]; /* set of BSS configurations, idx 0 is default and | 684 | wlc_bsscfg_t *bsscfg[WLC_MAXBSSCFG]; /* set of BSS configurations, idx 0 is default and |
@@ -708,7 +708,7 @@ struct wlc_info { | |||
708 | u8 mimoft; /* SIGN or 11N */ | 708 | u8 mimoft; /* SIGN or 11N */ |
709 | u8 mimo_band_bwcap; /* bw cap per band type */ | 709 | u8 mimo_band_bwcap; /* bw cap per band type */ |
710 | s8 txburst_limit_override; /* tx burst limit override */ | 710 | s8 txburst_limit_override; /* tx burst limit override */ |
711 | uint16 txburst_limit; /* tx burst limit value */ | 711 | u16 txburst_limit; /* tx burst limit value */ |
712 | s8 cck_40txbw; /* 11N, cck tx b/w override when in 40MHZ mode */ | 712 | s8 cck_40txbw; /* 11N, cck tx b/w override when in 40MHZ mode */ |
713 | s8 ofdm_40txbw; /* 11N, ofdm tx b/w override when in 40MHZ mode */ | 713 | s8 ofdm_40txbw; /* 11N, ofdm tx b/w override when in 40MHZ mode */ |
714 | s8 mimo_40txbw; /* 11N, mimo tx b/w override when in 40MHZ mode */ | 714 | s8 mimo_40txbw; /* 11N, mimo tx b/w override when in 40MHZ mode */ |
@@ -719,9 +719,9 @@ struct wlc_info { | |||
719 | 719 | ||
720 | wlc_bss_info_t *default_bss; /* configured BSS parameters */ | 720 | wlc_bss_info_t *default_bss; /* configured BSS parameters */ |
721 | 721 | ||
722 | uint16 AID; /* association ID */ | 722 | u16 AID; /* association ID */ |
723 | uint16 counter; /* per-sdu monotonically increasing counter */ | 723 | u16 counter; /* per-sdu monotonically increasing counter */ |
724 | uint16 mc_fid_counter; /* BC/MC FIFO frame ID counter */ | 724 | u16 mc_fid_counter; /* BC/MC FIFO frame ID counter */ |
725 | 725 | ||
726 | bool ibss_allowed; /* FALSE, all IBSS will be ignored during a scan | 726 | bool ibss_allowed; /* FALSE, all IBSS will be ignored during a scan |
727 | * and the driver will not allow the creation of | 727 | * and the driver will not allow the creation of |
@@ -739,7 +739,7 @@ struct wlc_info { | |||
739 | bcm_tlv_t *country_ie_override; /* debug override of announced Country IE */ | 739 | bcm_tlv_t *country_ie_override; /* debug override of announced Country IE */ |
740 | #endif | 740 | #endif |
741 | 741 | ||
742 | uint16 prb_resp_timeout; /* do not send prb resp if request older than this, | 742 | u16 prb_resp_timeout; /* do not send prb resp if request older than this, |
743 | * 0 = disable | 743 | * 0 = disable |
744 | */ | 744 | */ |
745 | 745 | ||
@@ -751,13 +751,13 @@ struct wlc_info { | |||
751 | 751 | ||
752 | /* PHY parameters */ | 752 | /* PHY parameters */ |
753 | chanspec_t chanspec; /* target operational channel */ | 753 | chanspec_t chanspec; /* target operational channel */ |
754 | uint16 usr_fragthresh; /* user configured fragmentation threshold */ | 754 | u16 usr_fragthresh; /* user configured fragmentation threshold */ |
755 | uint16 fragthresh[NFIFO]; /* per-fifo fragmentation thresholds */ | 755 | u16 fragthresh[NFIFO]; /* per-fifo fragmentation thresholds */ |
756 | uint16 RTSThresh; /* 802.11 dot11RTSThreshold */ | 756 | u16 RTSThresh; /* 802.11 dot11RTSThreshold */ |
757 | uint16 SRL; /* 802.11 dot11ShortRetryLimit */ | 757 | u16 SRL; /* 802.11 dot11ShortRetryLimit */ |
758 | uint16 LRL; /* 802.11 dot11LongRetryLimit */ | 758 | u16 LRL; /* 802.11 dot11LongRetryLimit */ |
759 | uint16 SFBL; /* Short Frame Rate Fallback Limit */ | 759 | u16 SFBL; /* Short Frame Rate Fallback Limit */ |
760 | uint16 LFBL; /* Long Frame Rate Fallback Limit */ | 760 | u16 LFBL; /* Long Frame Rate Fallback Limit */ |
761 | 761 | ||
762 | /* network config */ | 762 | /* network config */ |
763 | bool shortpreamble; /* currently operating with CCK ShortPreambles */ | 763 | bool shortpreamble; /* currently operating with CCK ShortPreambles */ |
@@ -802,10 +802,10 @@ struct wlc_info { | |||
802 | 802 | ||
803 | uint tempsense_lasttime; | 803 | uint tempsense_lasttime; |
804 | 804 | ||
805 | uint16 tx_duty_cycle_ofdm; /* maximum allowed duty cycle for OFDM */ | 805 | u16 tx_duty_cycle_ofdm; /* maximum allowed duty cycle for OFDM */ |
806 | uint16 tx_duty_cycle_cck; /* maximum allowed duty cycle for CCK */ | 806 | u16 tx_duty_cycle_cck; /* maximum allowed duty cycle for CCK */ |
807 | 807 | ||
808 | uint16 next_bsscfg_ID; | 808 | u16 next_bsscfg_ID; |
809 | 809 | ||
810 | wlc_if_t *wlcif_list; /* linked list of wlc_if structs */ | 810 | wlc_if_t *wlcif_list; /* linked list of wlc_if structs */ |
811 | wlc_txq_info_t *active_queue; /* txq for the currently active transmit context */ | 811 | wlc_txq_info_t *active_queue; /* txq for the currently active transmit context */ |
@@ -894,8 +894,8 @@ extern void wlc_set_addrmatch(wlc_info_t *wlc, int match_reg_offset, | |||
894 | const struct ether_addr *addr); | 894 | const struct ether_addr *addr); |
895 | extern void wlc_read_tsf(wlc_info_t *wlc, uint32 *tsf_l_ptr, | 895 | extern void wlc_read_tsf(wlc_info_t *wlc, uint32 *tsf_l_ptr, |
896 | uint32 *tsf_h_ptr); | 896 | uint32 *tsf_h_ptr); |
897 | extern void wlc_set_cwmin(wlc_info_t *wlc, uint16 newmin); | 897 | extern void wlc_set_cwmin(wlc_info_t *wlc, u16 newmin); |
898 | extern void wlc_set_cwmax(wlc_info_t *wlc, uint16 newmax); | 898 | extern void wlc_set_cwmax(wlc_info_t *wlc, u16 newmax); |
899 | extern void wlc_fifoerrors(wlc_info_t *wlc); | 899 | extern void wlc_fifoerrors(wlc_info_t *wlc); |
900 | extern void wlc_pllreq(wlc_info_t *wlc, bool set, mbool req_bit); | 900 | extern void wlc_pllreq(wlc_info_t *wlc, bool set, mbool req_bit); |
901 | extern void wlc_reset_bmac_done(wlc_info_t *wlc); | 901 | extern void wlc_reset_bmac_done(wlc_info_t *wlc); |
@@ -940,11 +940,11 @@ extern bool wlc_txflowcontrol_prio_isset(wlc_info_t *wlc, wlc_txq_info_t *qi, | |||
940 | extern void wlc_send_q(wlc_info_t *wlc, wlc_txq_info_t *qi); | 940 | extern void wlc_send_q(wlc_info_t *wlc, wlc_txq_info_t *qi); |
941 | extern int wlc_prep_pdu(wlc_info_t *wlc, void *pdu, uint *fifo); | 941 | extern int wlc_prep_pdu(wlc_info_t *wlc, void *pdu, uint *fifo); |
942 | 942 | ||
943 | extern uint16 wlc_calc_lsig_len(wlc_info_t *wlc, ratespec_t ratespec, | 943 | extern u16 wlc_calc_lsig_len(wlc_info_t *wlc, ratespec_t ratespec, |
944 | uint mac_len); | 944 | uint mac_len); |
945 | extern ratespec_t wlc_rspec_to_rts_rspec(wlc_info_t *wlc, ratespec_t rspec, | 945 | extern ratespec_t wlc_rspec_to_rts_rspec(wlc_info_t *wlc, ratespec_t rspec, |
946 | bool use_rspec, uint16 mimo_ctlchbw); | 946 | bool use_rspec, u16 mimo_ctlchbw); |
947 | extern uint16 wlc_compute_rtscts_dur(wlc_info_t *wlc, bool cts_only, | 947 | extern u16 wlc_compute_rtscts_dur(wlc_info_t *wlc, bool cts_only, |
948 | ratespec_t rts_rate, ratespec_t frame_rate, | 948 | ratespec_t rts_rate, ratespec_t frame_rate, |
949 | u8 rts_preamble_type, | 949 | u8 rts_preamble_type, |
950 | u8 frame_preamble_type, uint frame_len, | 950 | u8 frame_preamble_type, uint frame_len, |
@@ -964,9 +964,9 @@ extern void wlc_uint64_sub(uint32 *a_high, uint32 *a_low, uint32 b_high, | |||
964 | extern uint32 wlc_calc_tbtt_offset(uint32 bi, uint32 tsf_h, uint32 tsf_l); | 964 | extern uint32 wlc_calc_tbtt_offset(uint32 bi, uint32 tsf_h, uint32 tsf_l); |
965 | 965 | ||
966 | /* Shared memory access */ | 966 | /* Shared memory access */ |
967 | extern void wlc_write_shm(wlc_info_t *wlc, uint offset, uint16 v); | 967 | extern void wlc_write_shm(wlc_info_t *wlc, uint offset, u16 v); |
968 | extern uint16 wlc_read_shm(wlc_info_t *wlc, uint offset); | 968 | extern u16 wlc_read_shm(wlc_info_t *wlc, uint offset); |
969 | extern void wlc_set_shm(wlc_info_t *wlc, uint offset, uint16 v, int len); | 969 | extern void wlc_set_shm(wlc_info_t *wlc, uint offset, u16 v, int len); |
970 | extern void wlc_copyto_shm(wlc_info_t *wlc, uint offset, const void *buf, | 970 | extern void wlc_copyto_shm(wlc_info_t *wlc, uint offset, const void *buf, |
971 | int len); | 971 | int len); |
972 | extern void wlc_copyfrom_shm(wlc_info_t *wlc, uint offset, void *buf, int len); | 972 | extern void wlc_copyfrom_shm(wlc_info_t *wlc, uint offset, void *buf, int len); |
@@ -984,7 +984,7 @@ extern void wlc_radio_mpc_upd(wlc_info_t *wlc); | |||
984 | extern bool wlc_prec_enq(wlc_info_t *wlc, struct pktq *q, void *pkt, int prec); | 984 | extern bool wlc_prec_enq(wlc_info_t *wlc, struct pktq *q, void *pkt, int prec); |
985 | extern bool wlc_prec_enq_head(wlc_info_t *wlc, struct pktq *q, void *pkt, | 985 | extern bool wlc_prec_enq_head(wlc_info_t *wlc, struct pktq *q, void *pkt, |
986 | int prec, bool head); | 986 | int prec, bool head); |
987 | extern uint16 wlc_phytxctl1_calc(wlc_info_t *wlc, ratespec_t rspec); | 987 | extern u16 wlc_phytxctl1_calc(wlc_info_t *wlc, ratespec_t rspec); |
988 | extern void wlc_compute_plcp(wlc_info_t *wlc, ratespec_t rate, uint length, | 988 | extern void wlc_compute_plcp(wlc_info_t *wlc, ratespec_t rate, uint length, |
989 | u8 *plcp); | 989 | u8 *plcp); |
990 | extern uint wlc_calc_frame_time(wlc_info_t *wlc, ratespec_t ratespec, | 990 | extern uint wlc_calc_frame_time(wlc_info_t *wlc, ratespec_t ratespec, |
@@ -1021,7 +1021,7 @@ extern void wlc_beacon_phytxctl_txant_upd(wlc_info_t *wlc, | |||
1021 | ratespec_t bcn_rate); | 1021 | ratespec_t bcn_rate); |
1022 | extern void wlc_mod_prb_rsp_rate_table(wlc_info_t *wlc, uint frame_len); | 1022 | extern void wlc_mod_prb_rsp_rate_table(wlc_info_t *wlc, uint frame_len); |
1023 | extern ratespec_t wlc_lowest_basic_rspec(wlc_info_t *wlc, wlc_rateset_t *rs); | 1023 | extern ratespec_t wlc_lowest_basic_rspec(wlc_info_t *wlc, wlc_rateset_t *rs); |
1024 | extern uint16 wlc_compute_bcntsfoff(wlc_info_t *wlc, ratespec_t rspec, | 1024 | extern u16 wlc_compute_bcntsfoff(wlc_info_t *wlc, ratespec_t rspec, |
1025 | bool short_preamble, bool phydelay); | 1025 | bool short_preamble, bool phydelay); |
1026 | extern void wlc_radio_disable(wlc_info_t *wlc); | 1026 | extern void wlc_radio_disable(wlc_info_t *wlc); |
1027 | extern void wlc_bcn_li_upd(wlc_info_t *wlc); | 1027 | extern void wlc_bcn_li_upd(wlc_info_t *wlc); |
diff --git a/drivers/staging/brcm80211/sys/wlc_phy_shim.c b/drivers/staging/brcm80211/sys/wlc_phy_shim.c index 1e9db2e3f43..d7bc4c82c83 100644 --- a/drivers/staging/brcm80211/sys/wlc_phy_shim.c +++ b/drivers/staging/brcm80211/sys/wlc_phy_shim.c | |||
@@ -127,19 +127,19 @@ void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, uint32 macintmask) | |||
127 | wl_intrsrestore(physhim->wl, macintmask); | 127 | wl_intrsrestore(physhim->wl, macintmask); |
128 | } | 128 | } |
129 | 129 | ||
130 | void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, uint16 v) | 130 | void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, u16 v) |
131 | { | 131 | { |
132 | wlc_bmac_write_shm(physhim->wlc_hw, offset, v); | 132 | wlc_bmac_write_shm(physhim->wlc_hw, offset, v); |
133 | } | 133 | } |
134 | 134 | ||
135 | uint16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset) | 135 | u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset) |
136 | { | 136 | { |
137 | return wlc_bmac_read_shm(physhim->wlc_hw, offset); | 137 | return wlc_bmac_read_shm(physhim->wlc_hw, offset); |
138 | } | 138 | } |
139 | 139 | ||
140 | void | 140 | void |
141 | wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, uint16 mask, | 141 | wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, u16 mask, |
142 | uint16 val, int bands) | 142 | u16 val, int bands) |
143 | { | 143 | { |
144 | wlc_bmac_mhf(physhim->wlc_hw, idx, mask, val, bands); | 144 | wlc_bmac_mhf(physhim->wlc_hw, idx, mask, val, bands); |
145 | } | 145 | } |
@@ -174,12 +174,12 @@ void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim) | |||
174 | wlc_bmac_phy_reset(physhim->wlc_hw); | 174 | wlc_bmac_phy_reset(physhim->wlc_hw); |
175 | } | 175 | } |
176 | 176 | ||
177 | void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, uint16 bw) | 177 | void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw) |
178 | { | 178 | { |
179 | wlc_bmac_bw_set(physhim->wlc_hw, bw); | 179 | wlc_bmac_bw_set(physhim->wlc_hw, bw); |
180 | } | 180 | } |
181 | 181 | ||
182 | uint16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim) | 182 | u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim) |
183 | { | 183 | { |
184 | return wlc_bmac_get_txant(physhim->wlc_hw); | 184 | return wlc_bmac_get_txant(physhim->wlc_hw); |
185 | } | 185 | } |
@@ -222,7 +222,7 @@ wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int offset, | |||
222 | wlc_bmac_write_template_ram(physhim->wlc_hw, offset, len, buf); | 222 | wlc_bmac_write_template_ram(physhim->wlc_hw, offset, len, buf); |
223 | } | 223 | } |
224 | 224 | ||
225 | uint16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, u8 rate) | 225 | u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, u8 rate) |
226 | { | 226 | { |
227 | return wlc_bmac_rate_shm_offset(physhim->wlc_hw, rate); | 227 | return wlc_bmac_rate_shm_offset(physhim->wlc_hw, rate); |
228 | } | 228 | } |
diff --git a/drivers/staging/brcm80211/sys/wlc_phy_shim.h b/drivers/staging/brcm80211/sys/wlc_phy_shim.h index a6e6492af56..e573fbff6a7 100644 --- a/drivers/staging/brcm80211/sys/wlc_phy_shim.h +++ b/drivers/staging/brcm80211/sys/wlc_phy_shim.h | |||
@@ -76,10 +76,10 @@ extern void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, | |||
76 | uint32 macintmask); | 76 | uint32 macintmask); |
77 | 77 | ||
78 | extern void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, | 78 | extern void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, |
79 | uint16 v); | 79 | u16 v); |
80 | extern uint16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset); | 80 | extern u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset); |
81 | extern void wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, | 81 | extern void wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, |
82 | uint16 mask, uint16 val, int bands); | 82 | u16 mask, u16 val, int bands); |
83 | extern void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, uint32 flags); | 83 | extern void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, uint32 flags); |
84 | extern void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim); | 84 | extern void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim); |
85 | extern void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode); | 85 | extern void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode); |
@@ -87,7 +87,7 @@ extern void wlapi_enable_mac(wlc_phy_shim_info_t *physhim); | |||
87 | extern void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, uint32 mask, | 87 | extern void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, uint32 mask, |
88 | uint32 val); | 88 | uint32 val); |
89 | extern void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim); | 89 | extern void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim); |
90 | extern void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, uint16 bw); | 90 | extern void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw); |
91 | extern void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk); | 91 | extern void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk); |
92 | extern void wlapi_bmac_macphyclk_set(wlc_phy_shim_info_t *physhim, bool clk); | 92 | extern void wlapi_bmac_macphyclk_set(wlc_phy_shim_info_t *physhim, bool clk); |
93 | extern void wlapi_bmac_core_phypll_ctl(wlc_phy_shim_info_t *physhim, bool on); | 93 | extern void wlapi_bmac_core_phypll_ctl(wlc_phy_shim_info_t *physhim, bool on); |
@@ -98,7 +98,7 @@ extern void wlapi_bmac_ucode_wake_override_phyreg_clear(wlc_phy_shim_info_t * | |||
98 | physhim); | 98 | physhim); |
99 | extern void wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int o, | 99 | extern void wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int o, |
100 | int len, void *buf); | 100 | int len, void *buf); |
101 | extern uint16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, | 101 | extern u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, |
102 | u8 rate); | 102 | u8 rate); |
103 | extern void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim); | 103 | extern void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim); |
104 | extern void wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint, | 104 | extern void wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint, |
@@ -111,5 +111,5 @@ extern void wlapi_high_update_phy_mode(wlc_phy_shim_info_t *physhim, | |||
111 | extern void wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim, | 111 | extern void wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim, |
112 | wl_pkteng_t *pkteng, u8 rate, | 112 | wl_pkteng_t *pkteng, u8 rate, |
113 | struct ether_addr *sa, uint32 wait_delay); | 113 | struct ether_addr *sa, uint32 wait_delay); |
114 | extern uint16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim); | 114 | extern u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim); |
115 | #endif /* _wlc_phy_shim_h_ */ | 115 | #endif /* _wlc_phy_shim_h_ */ |
diff --git a/drivers/staging/brcm80211/sys/wlc_pub.h b/drivers/staging/brcm80211/sys/wlc_pub.h index 46a55f14391..6c7f1d4e18f 100644 --- a/drivers/staging/brcm80211/sys/wlc_pub.h +++ b/drivers/staging/brcm80211/sys/wlc_pub.h | |||
@@ -166,25 +166,25 @@ typedef struct wlc_event { | |||
166 | /* wlc internal bss_info, wl external one is in wlioctl.h */ | 166 | /* wlc internal bss_info, wl external one is in wlioctl.h */ |
167 | typedef struct wlc_bss_info { | 167 | typedef struct wlc_bss_info { |
168 | struct ether_addr BSSID; /* network BSSID */ | 168 | struct ether_addr BSSID; /* network BSSID */ |
169 | uint16 flags; /* flags for internal attributes */ | 169 | u16 flags; /* flags for internal attributes */ |
170 | u8 SSID_len; /* the length of SSID */ | 170 | u8 SSID_len; /* the length of SSID */ |
171 | u8 SSID[32]; /* SSID string */ | 171 | u8 SSID[32]; /* SSID string */ |
172 | int16 RSSI; /* receive signal strength (in dBm) */ | 172 | int16 RSSI; /* receive signal strength (in dBm) */ |
173 | int16 SNR; /* receive signal SNR in dB */ | 173 | int16 SNR; /* receive signal SNR in dB */ |
174 | uint16 beacon_period; /* units are Kusec */ | 174 | u16 beacon_period; /* units are Kusec */ |
175 | uint16 atim_window; /* units are Kusec */ | 175 | u16 atim_window; /* units are Kusec */ |
176 | chanspec_t chanspec; /* Channel num, bw, ctrl_sb and band */ | 176 | chanspec_t chanspec; /* Channel num, bw, ctrl_sb and band */ |
177 | s8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */ | 177 | s8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */ |
178 | wlc_rateset_t rateset; /* supported rates */ | 178 | wlc_rateset_t rateset; /* supported rates */ |
179 | u8 dtim_period; /* DTIM period */ | 179 | u8 dtim_period; /* DTIM period */ |
180 | s8 phy_noise; /* noise right after tx (in dBm) */ | 180 | s8 phy_noise; /* noise right after tx (in dBm) */ |
181 | uint16 capability; /* Capability information */ | 181 | u16 capability; /* Capability information */ |
182 | struct dot11_bcn_prb *bcn_prb; /* beacon/probe response frame (ioctl na) */ | 182 | struct dot11_bcn_prb *bcn_prb; /* beacon/probe response frame (ioctl na) */ |
183 | uint16 bcn_prb_len; /* beacon/probe response frame length (ioctl na) */ | 183 | u16 bcn_prb_len; /* beacon/probe response frame length (ioctl na) */ |
184 | u8 wme_qosinfo; /* QoS Info from WME IE; valid if WLC_BSS_WME flag set */ | 184 | u8 wme_qosinfo; /* QoS Info from WME IE; valid if WLC_BSS_WME flag set */ |
185 | struct rsn_parms wpa; | 185 | struct rsn_parms wpa; |
186 | struct rsn_parms wpa2; | 186 | struct rsn_parms wpa2; |
187 | uint16 qbss_load_aac; /* qbss load available admission capacity */ | 187 | u16 qbss_load_aac; /* qbss load available admission capacity */ |
188 | /* qbss_load_chan_free <- (0xff - channel_utilization of qbss_load_ie_t) */ | 188 | /* qbss_load_chan_free <- (0xff - channel_utilization of qbss_load_ie_t) */ |
189 | u8 qbss_load_chan_free; /* indicates how free the channel is */ | 189 | u8 qbss_load_chan_free; /* indicates how free the channel is */ |
190 | u8 mcipher; /* multicast cipher */ | 190 | u8 mcipher; /* multicast cipher */ |
@@ -299,7 +299,7 @@ typedef struct wlc_pub { | |||
299 | uint32 wlfeatureflag; /* Flags to control sw features from registry */ | 299 | uint32 wlfeatureflag; /* Flags to control sw features from registry */ |
300 | int psq_pkts_total; /* total num of ps pkts */ | 300 | int psq_pkts_total; /* total num of ps pkts */ |
301 | 301 | ||
302 | uint16 txmaxpkts; /* max number of large pkts allowed to be pending */ | 302 | u16 txmaxpkts; /* max number of large pkts allowed to be pending */ |
303 | 303 | ||
304 | /* s/w decryption counters */ | 304 | /* s/w decryption counters */ |
305 | uint32 swdecrypt; /* s/w decrypt attempts */ | 305 | uint32 swdecrypt; /* s/w decrypt attempts */ |
@@ -308,7 +308,7 @@ typedef struct wlc_pub { | |||
308 | 308 | ||
309 | mbool radio_disabled; /* bit vector for radio disabled reasons */ | 309 | mbool radio_disabled; /* bit vector for radio disabled reasons */ |
310 | bool radio_active; /* radio on/off state */ | 310 | bool radio_active; /* radio on/off state */ |
311 | uint16 roam_time_thresh; /* Max. # secs. of not hearing beacons | 311 | u16 roam_time_thresh; /* Max. # secs. of not hearing beacons |
312 | * before roaming. | 312 | * before roaming. |
313 | */ | 313 | */ |
314 | bool align_wd_tbtt; /* Align watchdog with tbtt indication | 314 | bool align_wd_tbtt; /* Align watchdog with tbtt indication |
@@ -322,7 +322,7 @@ typedef struct wlc_pub { | |||
322 | uint sdiod_drive_strength; /* SDIO drive strength */ | 322 | uint sdiod_drive_strength; /* SDIO drive strength */ |
323 | #endif /* BCMSDIO */ | 323 | #endif /* BCMSDIO */ |
324 | 324 | ||
325 | uint16 boardrev; /* version # of particular board */ | 325 | u16 boardrev; /* version # of particular board */ |
326 | u8 sromrev; /* version # of the srom */ | 326 | u8 sromrev; /* version # of the srom */ |
327 | char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */ | 327 | char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */ |
328 | uint32 boardflags; /* Board specific flags from srom */ | 328 | uint32 boardflags; /* Board specific flags from srom */ |
@@ -496,7 +496,7 @@ extern const u8 wme_fifo2ac[]; | |||
496 | #define WLCNTVAL(a) 0 /* No stats support */ | 496 | #define WLCNTVAL(a) 0 /* No stats support */ |
497 | 497 | ||
498 | /* common functions for every port */ | 498 | /* common functions for every port */ |
499 | extern void *wlc_attach(void *wl, uint16 vendor, uint16 device, uint unit, | 499 | extern void *wlc_attach(void *wl, u16 vendor, u16 device, uint unit, |
500 | bool piomode, osl_t *osh, void *regsva, uint bustype, | 500 | bool piomode, osl_t *osh, void *regsva, uint bustype, |
501 | void *btparam, uint *perr); | 501 | void *btparam, uint *perr); |
502 | extern uint wlc_detach(struct wlc_info *wlc); | 502 | extern uint wlc_detach(struct wlc_info *wlc); |
@@ -507,7 +507,7 @@ extern int wlc_set(struct wlc_info *wlc, int cmd, int arg); | |||
507 | extern int wlc_get(struct wlc_info *wlc, int cmd, int *arg); | 507 | extern int wlc_get(struct wlc_info *wlc, int cmd, int *arg); |
508 | extern int wlc_iovar_getint(struct wlc_info *wlc, const char *name, int *arg); | 508 | extern int wlc_iovar_getint(struct wlc_info *wlc, const char *name, int *arg); |
509 | extern int wlc_iovar_setint(struct wlc_info *wlc, const char *name, int arg); | 509 | extern int wlc_iovar_setint(struct wlc_info *wlc, const char *name, int arg); |
510 | extern bool wlc_chipmatch(uint16 vendor, uint16 device); | 510 | extern bool wlc_chipmatch(u16 vendor, u16 device); |
511 | extern void wlc_init(struct wlc_info *wlc); | 511 | extern void wlc_init(struct wlc_info *wlc); |
512 | extern void wlc_reset(struct wlc_info *wlc); | 512 | extern void wlc_reset(struct wlc_info *wlc); |
513 | 513 | ||
@@ -539,9 +539,9 @@ extern int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw); | |||
539 | extern uint32 wlc_reg_read(struct wlc_info *wlc, void *r, uint size); | 539 | extern uint32 wlc_reg_read(struct wlc_info *wlc, void *r, uint size); |
540 | extern void wlc_reg_write(struct wlc_info *wlc, void *r, uint32 v, uint size); | 540 | extern void wlc_reg_write(struct wlc_info *wlc, void *r, uint32 v, uint size); |
541 | extern void wlc_corereset(struct wlc_info *wlc, uint32 flags); | 541 | extern void wlc_corereset(struct wlc_info *wlc, uint32 flags); |
542 | extern void wlc_mhf(struct wlc_info *wlc, u8 idx, uint16 mask, uint16 val, | 542 | extern void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val, |
543 | int bands); | 543 | int bands); |
544 | extern uint16 wlc_mhf_get(struct wlc_info *wlc, u8 idx, int bands); | 544 | extern u16 wlc_mhf_get(struct wlc_info *wlc, u8 idx, int bands); |
545 | extern uint32 wlc_delta_txfunfl(struct wlc_info *wlc, int fifo); | 545 | extern uint32 wlc_delta_txfunfl(struct wlc_info *wlc, int fifo); |
546 | extern void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset); | 546 | extern void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset); |
547 | extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs); | 547 | extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs); |
@@ -565,7 +565,7 @@ extern void wlc_event_if(struct wlc_info *wlc, struct wlc_bsscfg *cfg, | |||
565 | wlc_event_t *e, const struct ether_addr *addr); | 565 | wlc_event_t *e, const struct ether_addr *addr); |
566 | extern void wlc_suspend_mac_and_wait(struct wlc_info *wlc); | 566 | extern void wlc_suspend_mac_and_wait(struct wlc_info *wlc); |
567 | extern void wlc_enable_mac(struct wlc_info *wlc); | 567 | extern void wlc_enable_mac(struct wlc_info *wlc); |
568 | extern uint16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate); | 568 | extern u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate); |
569 | extern uint32 wlc_get_rspec_history(struct wlc_bsscfg *cfg); | 569 | extern uint32 wlc_get_rspec_history(struct wlc_bsscfg *cfg); |
570 | extern uint32 wlc_get_current_highest_rate(struct wlc_bsscfg *cfg); | 570 | extern uint32 wlc_get_current_highest_rate(struct wlc_bsscfg *cfg); |
571 | 571 | ||
diff --git a/drivers/staging/brcm80211/sys/wlc_rpctx.h b/drivers/staging/brcm80211/sys/wlc_rpctx.h index 5c177a15d40..ed2989680d2 100644 --- a/drivers/staging/brcm80211/sys/wlc_rpctx.h +++ b/drivers/staging/brcm80211/sys/wlc_rpctx.h | |||
@@ -44,7 +44,7 @@ extern void wlc_rpctx_txreclaim(rpctx_info_t *rpctx); | |||
44 | extern uint wlc_rpctx_txavail(rpctx_info_t *rpctx, uint fifo); | 44 | extern uint wlc_rpctx_txavail(rpctx_info_t *rpctx, uint fifo); |
45 | extern int wlc_rpctx_pkteng(rpctx_info_t *rpctx, uint fifo, void *p); | 45 | extern int wlc_rpctx_pkteng(rpctx_info_t *rpctx, uint fifo, void *p); |
46 | extern int wlc_rpctx_tx(rpctx_info_t *rpctx, uint fifo, void *p, bool commit, | 46 | extern int wlc_rpctx_tx(rpctx_info_t *rpctx, uint fifo, void *p, bool commit, |
47 | uint16 frameid, u8 txpktpend); | 47 | u16 frameid, u8 txpktpend); |
48 | extern void wlc_rpctx_txpktpendinc(rpctx_info_t *rpctx, uint fifo, u8 val); | 48 | extern void wlc_rpctx_txpktpendinc(rpctx_info_t *rpctx, uint fifo, u8 val); |
49 | extern void wlc_rpctx_txpktpenddec(rpctx_info_t *rpctx, uint fifo, u8 val); | 49 | extern void wlc_rpctx_txpktpenddec(rpctx_info_t *rpctx, uint fifo, u8 val); |
50 | extern void wlc_rpctx_txpktpendclr(rpctx_info_t *rpctx, uint fifo); | 50 | extern void wlc_rpctx_txpktpendclr(rpctx_info_t *rpctx, uint fifo); |
diff --git a/drivers/staging/brcm80211/sys/wlc_scb.h b/drivers/staging/brcm80211/sys/wlc_scb.h index 143b7691232..388fff4a35f 100644 --- a/drivers/staging/brcm80211/sys/wlc_scb.h +++ b/drivers/staging/brcm80211/sys/wlc_scb.h | |||
@@ -38,7 +38,7 @@ typedef struct scb_ampdu { | |||
38 | u8 mpdu_density; /* mpdu density */ | 38 | u8 mpdu_density; /* mpdu density */ |
39 | u8 max_pdu; /* max pdus allowed in ampdu */ | 39 | u8 max_pdu; /* max pdus allowed in ampdu */ |
40 | u8 release; /* # of mpdus released at a time */ | 40 | u8 release; /* # of mpdus released at a time */ |
41 | uint16 min_len; /* min mpdu len to support the density */ | 41 | u16 min_len; /* min mpdu len to support the density */ |
42 | uint32 max_rxlen; /* max ampdu rcv length; 8k, 16k, 32k, 64k */ | 42 | uint32 max_rxlen; /* max ampdu rcv length; 8k, 16k, 32k, 64k */ |
43 | struct pktq txq; /* sdu transmit queue pending aggregation */ | 43 | struct pktq txq; /* sdu transmit queue pending aggregation */ |
44 | 44 | ||
@@ -62,11 +62,11 @@ struct scb { | |||
62 | void *fragbuf[NUMPRIO]; /* defragmentation buffer per prio */ | 62 | void *fragbuf[NUMPRIO]; /* defragmentation buffer per prio */ |
63 | uint fragresid[NUMPRIO]; /* #bytes unused in frag buffer per prio */ | 63 | uint fragresid[NUMPRIO]; /* #bytes unused in frag buffer per prio */ |
64 | 64 | ||
65 | uint16 seqctl[NUMPRIO]; /* seqctl of last received frame (for dups) */ | 65 | u16 seqctl[NUMPRIO]; /* seqctl of last received frame (for dups) */ |
66 | uint16 seqctl_nonqos; /* seqctl of last received frame (for dups) for | 66 | u16 seqctl_nonqos; /* seqctl of last received frame (for dups) for |
67 | * non-QoS data and management | 67 | * non-QoS data and management |
68 | */ | 68 | */ |
69 | uint16 seqnum[NUMPRIO]; /* WME: driver maintained sw seqnum per priority */ | 69 | u16 seqnum[NUMPRIO]; /* WME: driver maintained sw seqnum per priority */ |
70 | 70 | ||
71 | scb_ampdu_t scb_ampdu; /* AMPDU state including per tid info */ | 71 | scb_ampdu_t scb_ampdu; /* AMPDU state including per tid info */ |
72 | }; | 72 | }; |
diff --git a/drivers/staging/brcm80211/sys/wlc_stf.c b/drivers/staging/brcm80211/sys/wlc_stf.c index 3bb5037824d..10db2af7b08 100644 --- a/drivers/staging/brcm80211/sys/wlc_stf.c +++ b/drivers/staging/brcm80211/sys/wlc_stf.c | |||
@@ -49,7 +49,7 @@ static int wlc_stf_spatial_policy_set(wlc_info_t *wlc, int val); | |||
49 | static void wlc_stf_stbc_rx_ht_update(wlc_info_t *wlc, int val); | 49 | static void wlc_stf_stbc_rx_ht_update(wlc_info_t *wlc, int val); |
50 | 50 | ||
51 | static void _wlc_stf_phy_txant_upd(wlc_info_t *wlc); | 51 | static void _wlc_stf_phy_txant_upd(wlc_info_t *wlc); |
52 | static uint16 _wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec); | 52 | static u16 _wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec); |
53 | 53 | ||
54 | #define NSTS_1 1 | 54 | #define NSTS_1 1 |
55 | #define NSTS_2 2 | 55 | #define NSTS_2 2 |
@@ -108,7 +108,7 @@ void wlc_tempsense_upd(wlc_info_t *wlc) | |||
108 | } | 108 | } |
109 | 109 | ||
110 | void | 110 | void |
111 | wlc_stf_ss_algo_channel_get(wlc_info_t *wlc, uint16 *ss_algo_channel, | 111 | wlc_stf_ss_algo_channel_get(wlc_info_t *wlc, u16 *ss_algo_channel, |
112 | chanspec_t chanspec) | 112 | chanspec_t chanspec) |
113 | { | 113 | { |
114 | tx_power_t power; | 114 | tx_power_t power; |
@@ -118,7 +118,7 @@ wlc_stf_ss_algo_channel_get(wlc_info_t *wlc, uint16 *ss_algo_channel, | |||
118 | *ss_algo_channel = 0; | 118 | *ss_algo_channel = 0; |
119 | 119 | ||
120 | if (!wlc->pub->up) { | 120 | if (!wlc->pub->up) { |
121 | *ss_algo_channel = (uint16) -1; | 121 | *ss_algo_channel = (u16) -1; |
122 | return; | 122 | return; |
123 | } | 123 | } |
124 | 124 | ||
@@ -380,7 +380,7 @@ int wlc_stf_ss_update(wlc_info_t *wlc, wlcband_t *band) | |||
380 | /* NOTE: opmode can only be SISO or CDD as STBC is decided on a per-packet basis */ | 380 | /* NOTE: opmode can only be SISO or CDD as STBC is decided on a per-packet basis */ |
381 | if (WLC_STBC_CAP_PHY(wlc) && | 381 | if (WLC_STBC_CAP_PHY(wlc) && |
382 | wlc->stf->ss_algosel_auto | 382 | wlc->stf->ss_algosel_auto |
383 | && (wlc->stf->ss_algo_channel != (uint16) -1)) { | 383 | && (wlc->stf->ss_algo_channel != (u16) -1)) { |
384 | ASSERT(isset(&wlc->stf->ss_algo_channel, PHY_TXC1_MODE_CDD) | 384 | ASSERT(isset(&wlc->stf->ss_algo_channel, PHY_TXC1_MODE_CDD) |
385 | || isset(&wlc->stf->ss_algo_channel, | 385 | || isset(&wlc->stf->ss_algo_channel, |
386 | PHY_TXC1_MODE_SISO)); | 386 | PHY_TXC1_MODE_SISO)); |
@@ -422,7 +422,7 @@ int BCMATTACHFN(wlc_stf_attach) (wlc_info_t *wlc) | |||
422 | 422 | ||
423 | if (WLC_STBC_CAP_PHY(wlc)) { | 423 | if (WLC_STBC_CAP_PHY(wlc)) { |
424 | wlc->stf->ss_algosel_auto = TRUE; | 424 | wlc->stf->ss_algosel_auto = TRUE; |
425 | wlc->stf->ss_algo_channel = (uint16) -1; /* Init the default value */ | 425 | wlc->stf->ss_algo_channel = (u16) -1; /* Init the default value */ |
426 | } | 426 | } |
427 | return 0; | 427 | return 0; |
428 | } | 428 | } |
@@ -561,9 +561,9 @@ void BCMATTACHFN(wlc_stf_phy_chain_calc) (wlc_info_t *wlc) | |||
561 | wlc_stf_spatial_policy_set(wlc, MIN_SPATIAL_EXPANSION); | 561 | wlc_stf_spatial_policy_set(wlc, MIN_SPATIAL_EXPANSION); |
562 | } | 562 | } |
563 | 563 | ||
564 | static uint16 _wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec) | 564 | static u16 _wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec) |
565 | { | 565 | { |
566 | uint16 phytxant = wlc->stf->phytxant; | 566 | u16 phytxant = wlc->stf->phytxant; |
567 | 567 | ||
568 | if (RSPEC_STF(rspec) != PHY_TXC1_MODE_SISO) { | 568 | if (RSPEC_STF(rspec) != PHY_TXC1_MODE_SISO) { |
569 | ASSERT(wlc->stf->txstreams > 1); | 569 | ASSERT(wlc->stf->txstreams > 1); |
@@ -574,15 +574,15 @@ static uint16 _wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec) | |||
574 | return phytxant; | 574 | return phytxant; |
575 | } | 575 | } |
576 | 576 | ||
577 | uint16 wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec) | 577 | u16 wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec) |
578 | { | 578 | { |
579 | return _wlc_stf_phytxchain_sel(wlc, rspec); | 579 | return _wlc_stf_phytxchain_sel(wlc, rspec); |
580 | } | 580 | } |
581 | 581 | ||
582 | uint16 wlc_stf_d11hdrs_phyctl_txant(wlc_info_t *wlc, ratespec_t rspec) | 582 | u16 wlc_stf_d11hdrs_phyctl_txant(wlc_info_t *wlc, ratespec_t rspec) |
583 | { | 583 | { |
584 | uint16 phytxant = wlc->stf->phytxant; | 584 | u16 phytxant = wlc->stf->phytxant; |
585 | uint16 mask = PHY_TXC_ANT_MASK; | 585 | u16 mask = PHY_TXC_ANT_MASK; |
586 | 586 | ||
587 | /* for non-siso rates or default setting, use the available chains */ | 587 | /* for non-siso rates or default setting, use the available chains */ |
588 | if (WLCISNPHY(wlc->band)) { | 588 | if (WLCISNPHY(wlc->band)) { |
diff --git a/drivers/staging/brcm80211/sys/wlc_stf.h b/drivers/staging/brcm80211/sys/wlc_stf.h index 8cb34a0ff4f..99bf5cd1ae0 100644 --- a/drivers/staging/brcm80211/sys/wlc_stf.h +++ b/drivers/staging/brcm80211/sys/wlc_stf.h | |||
@@ -25,7 +25,7 @@ extern void wlc_stf_detach(wlc_info_t *wlc); | |||
25 | 25 | ||
26 | extern void wlc_tempsense_upd(wlc_info_t *wlc); | 26 | extern void wlc_tempsense_upd(wlc_info_t *wlc); |
27 | extern void wlc_stf_ss_algo_channel_get(wlc_info_t *wlc, | 27 | extern void wlc_stf_ss_algo_channel_get(wlc_info_t *wlc, |
28 | uint16 *ss_algo_channel, | 28 | u16 *ss_algo_channel, |
29 | chanspec_t chanspec); | 29 | chanspec_t chanspec); |
30 | extern int wlc_stf_ss_update(wlc_info_t *wlc, struct wlcband *band); | 30 | extern int wlc_stf_ss_update(wlc_info_t *wlc, struct wlcband *band); |
31 | extern void wlc_stf_phy_txant_upd(wlc_info_t *wlc); | 31 | extern void wlc_stf_phy_txant_upd(wlc_info_t *wlc); |
@@ -36,7 +36,7 @@ extern bool wlc_stf_stbc_rx_set(wlc_info_t *wlc, int32 int_val); | |||
36 | extern int wlc_stf_ant_txant_validate(wlc_info_t *wlc, s8 val); | 36 | extern int wlc_stf_ant_txant_validate(wlc_info_t *wlc, s8 val); |
37 | extern void wlc_stf_phy_txant_upd(wlc_info_t *wlc); | 37 | extern void wlc_stf_phy_txant_upd(wlc_info_t *wlc); |
38 | extern void wlc_stf_phy_chain_calc(wlc_info_t *wlc); | 38 | extern void wlc_stf_phy_chain_calc(wlc_info_t *wlc); |
39 | extern uint16 wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec); | 39 | extern u16 wlc_stf_phytxchain_sel(wlc_info_t *wlc, ratespec_t rspec); |
40 | extern uint16 wlc_stf_d11hdrs_phyctl_txant(wlc_info_t *wlc, ratespec_t rspec); | 40 | extern u16 wlc_stf_d11hdrs_phyctl_txant(wlc_info_t *wlc, ratespec_t rspec); |
41 | extern uint16 wlc_stf_spatial_expansion_get(wlc_info_t *wlc, ratespec_t rspec); | 41 | extern u16 wlc_stf_spatial_expansion_get(wlc_info_t *wlc, ratespec_t rspec); |
42 | #endif /* _wlc_stf_h_ */ | 42 | #endif /* _wlc_stf_h_ */ |
diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c index 0e257ba51c2..5bfc0eeaa58 100644 --- a/drivers/staging/brcm80211/util/bcmotp.c +++ b/drivers/staging/brcm80211/util/bcmotp.c | |||
@@ -59,8 +59,8 @@ | |||
59 | typedef int (*otp_status_t) (void *oh); | 59 | typedef int (*otp_status_t) (void *oh); |
60 | typedef int (*otp_size_t) (void *oh); | 60 | typedef int (*otp_size_t) (void *oh); |
61 | typedef void *(*otp_init_t) (si_t *sih); | 61 | typedef void *(*otp_init_t) (si_t *sih); |
62 | typedef uint16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off); | 62 | typedef u16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off); |
63 | typedef int (*otp_read_region_t) (si_t *sih, int region, uint16 *data, | 63 | typedef int (*otp_read_region_t) (si_t *sih, int region, u16 *data, |
64 | uint *wlen); | 64 | uint *wlen); |
65 | typedef int (*otp_nvread_t) (void *oh, char *data, uint *len); | 65 | typedef int (*otp_nvread_t) (void *oh, char *data, uint *len); |
66 | 66 | ||
@@ -82,18 +82,18 @@ typedef struct { | |||
82 | 82 | ||
83 | #ifdef BCMIPXOTP | 83 | #ifdef BCMIPXOTP |
84 | /* IPX OTP section */ | 84 | /* IPX OTP section */ |
85 | uint16 wsize; /* Size of otp in words */ | 85 | u16 wsize; /* Size of otp in words */ |
86 | uint16 rows; /* Geometry */ | 86 | u16 rows; /* Geometry */ |
87 | uint16 cols; /* Geometry */ | 87 | u16 cols; /* Geometry */ |
88 | uint32 status; /* Flag bits (lock/prog/rv). | 88 | uint32 status; /* Flag bits (lock/prog/rv). |
89 | * (Reflected only when OTP is power cycled) | 89 | * (Reflected only when OTP is power cycled) |
90 | */ | 90 | */ |
91 | uint16 hwbase; /* hardware subregion offset */ | 91 | u16 hwbase; /* hardware subregion offset */ |
92 | uint16 hwlim; /* hardware subregion boundary */ | 92 | u16 hwlim; /* hardware subregion boundary */ |
93 | uint16 swbase; /* software subregion offset */ | 93 | u16 swbase; /* software subregion offset */ |
94 | uint16 swlim; /* software subregion boundary */ | 94 | u16 swlim; /* software subregion boundary */ |
95 | uint16 fbase; /* fuse subregion offset */ | 95 | u16 fbase; /* fuse subregion offset */ |
96 | uint16 flim; /* fuse subregion boundary */ | 96 | u16 flim; /* fuse subregion boundary */ |
97 | int otpgu_base; /* offset to General Use Region */ | 97 | int otpgu_base; /* offset to General Use Region */ |
98 | #endif /* BCMIPXOTP */ | 98 | #endif /* BCMIPXOTP */ |
99 | 99 | ||
@@ -173,7 +173,7 @@ static int ipxotp_size(void *oh) | |||
173 | return (int)oi->wsize * 2; | 173 | return (int)oi->wsize * 2; |
174 | } | 174 | } |
175 | 175 | ||
176 | static uint16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn) | 176 | static u16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn) |
177 | { | 177 | { |
178 | otpinfo_t *oi; | 178 | otpinfo_t *oi; |
179 | 179 | ||
@@ -185,7 +185,7 @@ static uint16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn) | |||
185 | return R_REG(oi->osh, &cc->sromotp[wn]); | 185 | return R_REG(oi->osh, &cc->sromotp[wn]); |
186 | } | 186 | } |
187 | 187 | ||
188 | static uint16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off) | 188 | static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off) |
189 | { | 189 | { |
190 | otpinfo_t *oi = (otpinfo_t *) oh; | 190 | otpinfo_t *oi = (otpinfo_t *) oh; |
191 | uint k, row, col; | 191 | uint k, row, col; |
@@ -373,7 +373,7 @@ static void *BCMNMIATTACHFN(ipxotp_init) (si_t *sih) | |||
373 | return (void *)oi; | 373 | return (void *)oi; |
374 | } | 374 | } |
375 | 375 | ||
376 | static int ipxotp_read_region(void *oh, int region, uint16 *data, uint *wlen) | 376 | static int ipxotp_read_region(void *oh, int region, u16 *data, uint *wlen) |
377 | { | 377 | { |
378 | otpinfo_t *oi = (otpinfo_t *) oh; | 378 | otpinfo_t *oi = (otpinfo_t *) oh; |
379 | uint idx; | 379 | uint idx; |
@@ -567,26 +567,26 @@ static int hndotp_size(void *oh) | |||
567 | return (int)(oi->size); | 567 | return (int)(oi->size); |
568 | } | 568 | } |
569 | 569 | ||
570 | static uint16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn) | 570 | static u16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn) |
571 | { | 571 | { |
572 | otpinfo_t *oi = (otpinfo_t *) oh; | 572 | otpinfo_t *oi = (otpinfo_t *) oh; |
573 | osl_t *osh; | 573 | osl_t *osh; |
574 | volatile uint16 *ptr; | 574 | volatile u16 *ptr; |
575 | 575 | ||
576 | ASSERT(wn < ((oi->size / 2) + OTP_RC_LIM_OFF)); | 576 | ASSERT(wn < ((oi->size / 2) + OTP_RC_LIM_OFF)); |
577 | ASSERT(cc != NULL); | 577 | ASSERT(cc != NULL); |
578 | 578 | ||
579 | osh = si_osh(oi->sih); | 579 | osh = si_osh(oi->sih); |
580 | 580 | ||
581 | ptr = (volatile uint16 *)((volatile char *)cc + CC_SROM_OTP); | 581 | ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP); |
582 | return R_REG(osh, &ptr[wn]); | 582 | return R_REG(osh, &ptr[wn]); |
583 | } | 583 | } |
584 | 584 | ||
585 | static uint16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff) | 585 | static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff) |
586 | { | 586 | { |
587 | otpinfo_t *oi = (otpinfo_t *) oh; | 587 | otpinfo_t *oi = (otpinfo_t *) oh; |
588 | osl_t *osh; | 588 | osl_t *osh; |
589 | volatile uint16 *ptr; | 589 | volatile u16 *ptr; |
590 | 590 | ||
591 | ASSERT(woff >= (-((int)oi->size / 2))); | 591 | ASSERT(woff >= (-((int)oi->size / 2))); |
592 | ASSERT(woff < OTP_LIM_OFF); | 592 | ASSERT(woff < OTP_LIM_OFF); |
@@ -594,12 +594,12 @@ static uint16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff) | |||
594 | 594 | ||
595 | osh = si_osh(oi->sih); | 595 | osh = si_osh(oi->sih); |
596 | 596 | ||
597 | ptr = (volatile uint16 *)((volatile char *)cc + CC_SROM_OTP); | 597 | ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP); |
598 | 598 | ||
599 | return R_REG(osh, &ptr[(oi->size / 2) + woff]); | 599 | return R_REG(osh, &ptr[(oi->size / 2) + woff]); |
600 | } | 600 | } |
601 | 601 | ||
602 | static uint16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx) | 602 | static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx) |
603 | { | 603 | { |
604 | otpinfo_t *oi = (otpinfo_t *) oh; | 604 | otpinfo_t *oi = (otpinfo_t *) oh; |
605 | uint k, row, col; | 605 | uint k, row, col; |
@@ -627,7 +627,7 @@ static uint16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx) | |||
627 | return 0xffff; | 627 | return 0xffff; |
628 | } | 628 | } |
629 | st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT; | 629 | st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT; |
630 | return (uint16) st; | 630 | return (u16) st; |
631 | } | 631 | } |
632 | 632 | ||
633 | static void *BCMNMIATTACHFN(hndotp_init) (si_t *sih) | 633 | static void *BCMNMIATTACHFN(hndotp_init) (si_t *sih) |
@@ -706,7 +706,7 @@ static void *BCMNMIATTACHFN(hndotp_init) (si_t *sih) | |||
706 | return ret; | 706 | return ret; |
707 | } | 707 | } |
708 | 708 | ||
709 | static int hndotp_read_region(void *oh, int region, uint16 *data, uint *wlen) | 709 | static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen) |
710 | { | 710 | { |
711 | otpinfo_t *oi = (otpinfo_t *) oh; | 711 | otpinfo_t *oi = (otpinfo_t *) oh; |
712 | uint32 idx, st; | 712 | uint32 idx, st; |
@@ -745,7 +745,7 @@ static int hndotp_nvread(void *oh, char *data, uint *len) | |||
745 | uint32 idx; | 745 | uint32 idx; |
746 | chipcregs_t *cc; | 746 | chipcregs_t *cc; |
747 | uint offset; | 747 | uint offset; |
748 | uint16 *rawotp = NULL; | 748 | u16 *rawotp = NULL; |
749 | 749 | ||
750 | /* save the orig core */ | 750 | /* save the orig core */ |
751 | idx = si_coreidx(oi->sih); | 751 | idx = si_coreidx(oi->sih); |
@@ -885,12 +885,12 @@ int otp_size(void *oh) | |||
885 | return oi->fn->size(oh); | 885 | return oi->fn->size(oh); |
886 | } | 886 | } |
887 | 887 | ||
888 | uint16 otp_read_bit(void *oh, uint offset) | 888 | u16 otp_read_bit(void *oh, uint offset) |
889 | { | 889 | { |
890 | otpinfo_t *oi = (otpinfo_t *) oh; | 890 | otpinfo_t *oi = (otpinfo_t *) oh; |
891 | uint idx = si_coreidx(oi->sih); | 891 | uint idx = si_coreidx(oi->sih); |
892 | chipcregs_t *cc = si_setcoreidx(oi->sih, SI_CC_IDX); | 892 | chipcregs_t *cc = si_setcoreidx(oi->sih, SI_CC_IDX); |
893 | uint16 readBit = (uint16) oi->fn->read_bit(oh, cc, offset); | 893 | u16 readBit = (u16) oi->fn->read_bit(oh, cc, offset); |
894 | si_setcoreidx(oi->sih, idx); | 894 | si_setcoreidx(oi->sih, idx); |
895 | return readBit; | 895 | return readBit; |
896 | } | 896 | } |
@@ -928,7 +928,7 @@ void *BCMNMIATTACHFN(otp_init) (si_t *sih) | |||
928 | } | 928 | } |
929 | 929 | ||
930 | int | 930 | int |
931 | BCMNMIATTACHFN(otp_read_region) (si_t *sih, int region, uint16 *data, | 931 | BCMNMIATTACHFN(otp_read_region) (si_t *sih, int region, u16 *data, |
932 | uint *wlen) { | 932 | uint *wlen) { |
933 | bool wasup = FALSE; | 933 | bool wasup = FALSE; |
934 | void *oh; | 934 | void *oh; |
diff --git a/drivers/staging/brcm80211/util/bcmsrom.c b/drivers/staging/brcm80211/util/bcmsrom.c index 842b70ac411..73e48a650d8 100644 --- a/drivers/staging/brcm80211/util/bcmsrom.c +++ b/drivers/staging/brcm80211/util/bcmsrom.c | |||
@@ -70,7 +70,7 @@ extern uint _varsz; | |||
70 | 70 | ||
71 | static int initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, | 71 | static int initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, |
72 | uint *count); | 72 | uint *count); |
73 | static void _initvars_srom_pci(u8 sromrev, uint16 *srom, uint off, | 73 | static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, |
74 | varbuf_t *b); | 74 | varbuf_t *b); |
75 | static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, | 75 | static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, |
76 | uint *count); | 76 | uint *count); |
@@ -78,15 +78,15 @@ static int initvars_flash_si(si_t *sih, char **vars, uint *count); | |||
78 | #ifdef BCMSDIO | 78 | #ifdef BCMSDIO |
79 | static int initvars_cis_sdio(osl_t *osh, char **vars, uint *count); | 79 | static int initvars_cis_sdio(osl_t *osh, char **vars, uint *count); |
80 | static int sprom_cmd_sdio(osl_t *osh, u8 cmd); | 80 | static int sprom_cmd_sdio(osl_t *osh, u8 cmd); |
81 | static int sprom_read_sdio(osl_t *osh, uint16 addr, uint16 *data); | 81 | static int sprom_read_sdio(osl_t *osh, u16 addr, u16 *data); |
82 | #endif /* BCMSDIO */ | 82 | #endif /* BCMSDIO */ |
83 | static int sprom_read_pci(osl_t *osh, si_t *sih, uint16 *sprom, uint wordoff, | 83 | static int sprom_read_pci(osl_t *osh, si_t *sih, u16 *sprom, uint wordoff, |
84 | uint16 *buf, uint nwords, bool check_crc); | 84 | u16 *buf, uint nwords, bool check_crc); |
85 | #if defined(BCMNVRAMR) | 85 | #if defined(BCMNVRAMR) |
86 | static int otp_read_pci(osl_t *osh, si_t *sih, uint16 *buf, uint bufsz); | 86 | static int otp_read_pci(osl_t *osh, si_t *sih, u16 *buf, uint bufsz); |
87 | #endif | 87 | #endif |
88 | static uint16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, | 88 | static u16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, |
89 | uint wordoff, uint16 data); | 89 | uint wordoff, u16 data); |
90 | 90 | ||
91 | static int initvars_table(osl_t *osh, char *start, char *end, char **vars, | 91 | static int initvars_table(osl_t *osh, char *start, char *end, char **vars, |
92 | uint *count); | 92 | uint *count); |
@@ -197,7 +197,7 @@ BCMATTACHFN(srom_var_init) (si_t *sih, uint bustype, void *curmap, osl_t *osh, | |||
197 | /* support only 16-bit word read from srom */ | 197 | /* support only 16-bit word read from srom */ |
198 | int | 198 | int |
199 | srom_read(si_t *sih, uint bustype, void *curmap, osl_t *osh, | 199 | srom_read(si_t *sih, uint bustype, void *curmap, osl_t *osh, |
200 | uint byteoff, uint nbytes, uint16 *buf, bool check_crc) | 200 | uint byteoff, uint nbytes, u16 *buf, bool check_crc) |
201 | { | 201 | { |
202 | uint off, nw; | 202 | uint off, nw; |
203 | #ifdef BCMSDIO | 203 | #ifdef BCMSDIO |
@@ -218,9 +218,9 @@ srom_read(si_t *sih, uint bustype, void *curmap, osl_t *osh, | |||
218 | return 1; | 218 | return 1; |
219 | 219 | ||
220 | if (si_is_sprom_available(sih)) { | 220 | if (si_is_sprom_available(sih)) { |
221 | uint16 *srom; | 221 | u16 *srom; |
222 | 222 | ||
223 | srom = (uint16 *) SROM_OFFSET(sih); | 223 | srom = (u16 *) SROM_OFFSET(sih); |
224 | if (srom == NULL) | 224 | if (srom == NULL) |
225 | return 1; | 225 | return 1; |
226 | 226 | ||
@@ -240,7 +240,7 @@ srom_read(si_t *sih, uint bustype, void *curmap, osl_t *osh, | |||
240 | nw = nbytes / 2; | 240 | nw = nbytes / 2; |
241 | for (i = 0; i < nw; i++) { | 241 | for (i = 0; i < nw; i++) { |
242 | if (sprom_read_sdio | 242 | if (sprom_read_sdio |
243 | (osh, (uint16) (off + i), (uint16 *) (buf + i))) | 243 | (osh, (u16) (off + i), (u16 *) (buf + i))) |
244 | return 1; | 244 | return 1; |
245 | } | 245 | } |
246 | #endif /* BCMSDIO */ | 246 | #endif /* BCMSDIO */ |
@@ -1014,7 +1014,7 @@ BCMATTACHFN(srom_parsecis) (osl_t *osh, u8 *pcis[], uint ciscnt, | |||
1014 | break; | 1014 | break; |
1015 | 1015 | ||
1016 | case HNBU_FEM:{ | 1016 | case HNBU_FEM:{ |
1017 | uint16 fem = | 1017 | u16 fem = |
1018 | (cis[i + 2] << 8) + cis[i + | 1018 | (cis[i + 2] << 8) + cis[i + |
1019 | 1]; | 1019 | 1]; |
1020 | varbuf_append(&b, | 1020 | varbuf_append(&b, |
@@ -1336,7 +1336,7 @@ BCMATTACHFN(srom_parsecis) (osl_t *osh, u8 *pcis[], uint ciscnt, | |||
1336 | #if defined(BCMSDIO) | 1336 | #if defined(BCMSDIO) |
1337 | case HNBU_SROM3SWRGN: | 1337 | case HNBU_SROM3SWRGN: |
1338 | if (tlen >= 73) { | 1338 | if (tlen >= 73) { |
1339 | uint16 srom[35]; | 1339 | u16 srom[35]; |
1340 | u8 srev = cis[i + 1 + 70]; | 1340 | u8 srev = cis[i + 1 + 70]; |
1341 | ASSERT(srev == 3); | 1341 | ASSERT(srev == 3); |
1342 | /* make tuple value 16-bit aligned and parse it */ | 1342 | /* make tuple value 16-bit aligned and parse it */ |
@@ -1412,9 +1412,9 @@ BCMATTACHFN(srom_parsecis) (osl_t *osh, u8 *pcis[], uint ciscnt, | |||
1412 | /* In chips with chipcommon rev 32 and later, the srom is in chipcommon, | 1412 | /* In chips with chipcommon rev 32 and later, the srom is in chipcommon, |
1413 | * not in the bus cores. | 1413 | * not in the bus cores. |
1414 | */ | 1414 | */ |
1415 | static uint16 | 1415 | static u16 |
1416 | srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff, | 1416 | srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff, |
1417 | uint16 data) | 1417 | u16 data) |
1418 | { | 1418 | { |
1419 | chipcregs_t *cc = (chipcregs_t *) ccregs; | 1419 | chipcregs_t *cc = (chipcregs_t *) ccregs; |
1420 | uint wait_cnt = 1000; | 1420 | uint wait_cnt = 1000; |
@@ -1437,7 +1437,7 @@ srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff, | |||
1437 | return 0xffff; | 1437 | return 0xffff; |
1438 | } | 1438 | } |
1439 | if (cmd == SRC_OP_READ) | 1439 | if (cmd == SRC_OP_READ) |
1440 | return (uint16) R_REG(osh, &cc->sromdata); | 1440 | return (u16) R_REG(osh, &cc->sromdata); |
1441 | else | 1441 | else |
1442 | return 0xffff; | 1442 | return 0xffff; |
1443 | } | 1443 | } |
@@ -1447,8 +1447,8 @@ srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff, | |||
1447 | * Return 0 on success, nonzero on error. | 1447 | * Return 0 on success, nonzero on error. |
1448 | */ | 1448 | */ |
1449 | static int | 1449 | static int |
1450 | sprom_read_pci(osl_t *osh, si_t *sih, uint16 *sprom, uint wordoff, | 1450 | sprom_read_pci(osl_t *osh, si_t *sih, u16 *sprom, uint wordoff, |
1451 | uint16 *buf, uint nwords, bool check_crc) | 1451 | u16 *buf, uint nwords, bool check_crc) |
1452 | { | 1452 | { |
1453 | int err = 0; | 1453 | int err = 0; |
1454 | uint i; | 1454 | uint i; |
@@ -1507,7 +1507,7 @@ sprom_read_pci(osl_t *osh, si_t *sih, uint16 *sprom, uint wordoff, | |||
1507 | } | 1507 | } |
1508 | 1508 | ||
1509 | #if defined(BCMNVRAMR) | 1509 | #if defined(BCMNVRAMR) |
1510 | static int otp_read_pci(osl_t *osh, si_t *sih, uint16 *buf, uint bufsz) | 1510 | static int otp_read_pci(osl_t *osh, si_t *sih, u16 *buf, uint bufsz) |
1511 | { | 1511 | { |
1512 | u8 *otp; | 1512 | u8 *otp; |
1513 | uint sz = OTP_SZ_MAX / 2; /* size in words */ | 1513 | uint sz = OTP_SZ_MAX / 2; /* size in words */ |
@@ -1522,7 +1522,7 @@ static int otp_read_pci(osl_t *osh, si_t *sih, uint16 *buf, uint bufsz) | |||
1522 | 1522 | ||
1523 | bzero(otp, OTP_SZ_MAX); | 1523 | bzero(otp, OTP_SZ_MAX); |
1524 | 1524 | ||
1525 | err = otp_read_region(sih, OTP_HW_RGN, (uint16 *) otp, &sz); | 1525 | err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz); |
1526 | 1526 | ||
1527 | bcopy(otp, buf, bufsz); | 1527 | bcopy(otp, buf, bufsz); |
1528 | 1528 | ||
@@ -1673,7 +1673,7 @@ BCMATTACHFN(initvars_flash_si) (si_t *sih, char **vars, uint *count) | |||
1673 | * SROM3_SWRG_OFF (full SROM or software region). | 1673 | * SROM3_SWRG_OFF (full SROM or software region). |
1674 | */ | 1674 | */ |
1675 | 1675 | ||
1676 | static uint mask_shift(uint16 mask) | 1676 | static uint mask_shift(u16 mask) |
1677 | { | 1677 | { |
1678 | uint i; | 1678 | uint i; |
1679 | for (i = 0; i < (sizeof(mask) << 3); i++) { | 1679 | for (i = 0; i < (sizeof(mask) << 3); i++) { |
@@ -1684,7 +1684,7 @@ static uint mask_shift(uint16 mask) | |||
1684 | return 0; | 1684 | return 0; |
1685 | } | 1685 | } |
1686 | 1686 | ||
1687 | static uint mask_width(uint16 mask) | 1687 | static uint mask_width(u16 mask) |
1688 | { | 1688 | { |
1689 | int i; | 1689 | int i; |
1690 | for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) { | 1690 | for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) { |
@@ -1696,7 +1696,7 @@ static uint mask_width(uint16 mask) | |||
1696 | } | 1696 | } |
1697 | 1697 | ||
1698 | #if defined(BCMDBG) | 1698 | #if defined(BCMDBG) |
1699 | static bool mask_valid(uint16 mask) | 1699 | static bool mask_valid(u16 mask) |
1700 | { | 1700 | { |
1701 | uint shift = mask_shift(mask); | 1701 | uint shift = mask_shift(mask); |
1702 | uint width = mask_width(mask); | 1702 | uint width = mask_width(mask); |
@@ -1705,9 +1705,9 @@ static bool mask_valid(uint16 mask) | |||
1705 | #endif /* BCMDBG */ | 1705 | #endif /* BCMDBG */ |
1706 | 1706 | ||
1707 | static void | 1707 | static void |
1708 | BCMATTACHFN(_initvars_srom_pci) (u8 sromrev, uint16 *srom, uint off, | 1708 | BCMATTACHFN(_initvars_srom_pci) (u8 sromrev, u16 *srom, uint off, |
1709 | varbuf_t *b) { | 1709 | varbuf_t *b) { |
1710 | uint16 w; | 1710 | u16 w; |
1711 | uint32 val; | 1711 | uint32 val; |
1712 | const sromvar_t *srv; | 1712 | const sromvar_t *srv; |
1713 | uint width; | 1713 | uint width; |
@@ -1856,7 +1856,7 @@ BCMATTACHFN(_initvars_srom_pci) (u8 sromrev, uint16 *srom, uint off, | |||
1856 | static int | 1856 | static int |
1857 | BCMATTACHFN(initvars_srom_pci) (si_t *sih, void *curmap, char **vars, | 1857 | BCMATTACHFN(initvars_srom_pci) (si_t *sih, void *curmap, char **vars, |
1858 | uint *count) { | 1858 | uint *count) { |
1859 | uint16 *srom, *sromwindow; | 1859 | u16 *srom, *sromwindow; |
1860 | u8 sromrev = 0; | 1860 | u8 sromrev = 0; |
1861 | uint32 sr; | 1861 | uint32 sr; |
1862 | varbuf_t b; | 1862 | varbuf_t b; |
@@ -1876,7 +1876,7 @@ BCMATTACHFN(initvars_srom_pci) (si_t *sih, void *curmap, char **vars, | |||
1876 | if (!srom) | 1876 | if (!srom) |
1877 | return -2; | 1877 | return -2; |
1878 | 1878 | ||
1879 | sromwindow = (uint16 *) SROM_OFFSET(sih); | 1879 | sromwindow = (u16 *) SROM_OFFSET(sih); |
1880 | if (si_is_sprom_available(sih)) { | 1880 | if (si_is_sprom_available(sih)) { |
1881 | err = | 1881 | err = |
1882 | sprom_read_pci(osh, sih, sromwindow, 0, srom, SROM_WORDS, | 1882 | sprom_read_pci(osh, sih, sromwindow, 0, srom, SROM_WORDS, |
@@ -2059,7 +2059,7 @@ static int BCMATTACHFN(sprom_cmd_sdio) (osl_t *osh, u8 cmd) | |||
2059 | } | 2059 | } |
2060 | 2060 | ||
2061 | /* read a word from the SDIO srom */ | 2061 | /* read a word from the SDIO srom */ |
2062 | static int sprom_read_sdio(osl_t *osh, uint16 addr, uint16 *data) | 2062 | static int sprom_read_sdio(osl_t *osh, u16 addr, u16 *data) |
2063 | { | 2063 | { |
2064 | u8 addr_l, addr_h, data_l, data_h; | 2064 | u8 addr_l, addr_h, data_l, data_h; |
2065 | 2065 | ||
diff --git a/drivers/staging/brcm80211/util/bcmutils.c b/drivers/staging/brcm80211/util/bcmutils.c index 6489c1ef9a3..e36937a3950 100644 --- a/drivers/staging/brcm80211/util/bcmutils.c +++ b/drivers/staging/brcm80211/util/bcmutils.c | |||
@@ -200,9 +200,9 @@ void pktq_init(struct pktq *pq, int num_prec, int max_len) | |||
200 | bzero(pq, | 200 | bzero(pq, |
201 | OFFSETOF(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec)); | 201 | OFFSETOF(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec)); |
202 | 202 | ||
203 | pq->num_prec = (uint16) num_prec; | 203 | pq->num_prec = (u16) num_prec; |
204 | 204 | ||
205 | pq->max = (uint16) max_len; | 205 | pq->max = (u16) max_len; |
206 | 206 | ||
207 | for (prec = 0; prec < num_prec; prec++) | 207 | for (prec = 0; prec < num_prec; prec++) |
208 | pq->q[prec].max = pq->max; | 208 | pq->q[prec].max = pq->max; |
@@ -491,7 +491,7 @@ u8 BCMROMFN(hndcrc8) (u8 *pdata, /* pointer to array of data to process */ | |||
491 | * **************************************************************************** | 491 | * **************************************************************************** |
492 | */ | 492 | */ |
493 | 493 | ||
494 | static const uint16 crc16_table[256] = { | 494 | static const u16 crc16_table[256] = { |
495 | 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF, | 495 | 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF, |
496 | 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7, | 496 | 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7, |
497 | 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E, | 497 | 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E, |
@@ -526,9 +526,9 @@ static const uint16 crc16_table[256] = { | |||
526 | 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78 | 526 | 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78 |
527 | }; | 527 | }; |
528 | 528 | ||
529 | uint16 BCMROMFN(hndcrc16) (u8 *pdata, /* pointer to array of data to process */ | 529 | u16 BCMROMFN(hndcrc16) (u8 *pdata, /* pointer to array of data to process */ |
530 | uint nbytes, /* number of input data bytes to process */ | 530 | uint nbytes, /* number of input data bytes to process */ |
531 | uint16 crc /* either CRC16_INIT_VALUE or previous return value */ | 531 | u16 crc /* either CRC16_INIT_VALUE or previous return value */ |
532 | ) { | 532 | ) { |
533 | while (nbytes-- > 0) | 533 | while (nbytes-- > 0) |
534 | CRC_INNER_LOOP(16, crc, *pdata++); | 534 | CRC_INNER_LOOP(16, crc, *pdata++); |
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c index a4e1a0df58a..dd6e0d919f9 100644 --- a/drivers/staging/brcm80211/util/hnddma.c +++ b/drivers/staging/brcm80211/util/hnddma.c | |||
@@ -98,37 +98,37 @@ typedef struct dma_info { | |||
98 | } d64_u; | 98 | } d64_u; |
99 | } dregs; | 99 | } dregs; |
100 | 100 | ||
101 | uint16 dmadesc_align; /* alignment requirement for dma descriptors */ | 101 | u16 dmadesc_align; /* alignment requirement for dma descriptors */ |
102 | 102 | ||
103 | uint16 ntxd; /* # tx descriptors tunable */ | 103 | u16 ntxd; /* # tx descriptors tunable */ |
104 | uint16 txin; /* index of next descriptor to reclaim */ | 104 | u16 txin; /* index of next descriptor to reclaim */ |
105 | uint16 txout; /* index of next descriptor to post */ | 105 | u16 txout; /* index of next descriptor to post */ |
106 | void **txp; /* pointer to parallel array of pointers to packets */ | 106 | void **txp; /* pointer to parallel array of pointers to packets */ |
107 | osldma_t *tx_dmah; /* DMA TX descriptor ring handle */ | 107 | osldma_t *tx_dmah; /* DMA TX descriptor ring handle */ |
108 | hnddma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */ | 108 | hnddma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */ |
109 | dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */ | 109 | dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */ |
110 | dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */ | 110 | dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */ |
111 | uint16 txdalign; /* #bytes added to alloc'd mem to align txd */ | 111 | u16 txdalign; /* #bytes added to alloc'd mem to align txd */ |
112 | uint32 txdalloc; /* #bytes allocated for the ring */ | 112 | uint32 txdalloc; /* #bytes allocated for the ring */ |
113 | uint32 xmtptrbase; /* When using unaligned descriptors, the ptr register | 113 | uint32 xmtptrbase; /* When using unaligned descriptors, the ptr register |
114 | * is not just an index, it needs all 13 bits to be | 114 | * is not just an index, it needs all 13 bits to be |
115 | * an offset from the addr register. | 115 | * an offset from the addr register. |
116 | */ | 116 | */ |
117 | 117 | ||
118 | uint16 nrxd; /* # rx descriptors tunable */ | 118 | u16 nrxd; /* # rx descriptors tunable */ |
119 | uint16 rxin; /* index of next descriptor to reclaim */ | 119 | u16 rxin; /* index of next descriptor to reclaim */ |
120 | uint16 rxout; /* index of next descriptor to post */ | 120 | u16 rxout; /* index of next descriptor to post */ |
121 | void **rxp; /* pointer to parallel array of pointers to packets */ | 121 | void **rxp; /* pointer to parallel array of pointers to packets */ |
122 | osldma_t *rx_dmah; /* DMA RX descriptor ring handle */ | 122 | osldma_t *rx_dmah; /* DMA RX descriptor ring handle */ |
123 | hnddma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */ | 123 | hnddma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */ |
124 | dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */ | 124 | dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */ |
125 | dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */ | 125 | dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */ |
126 | uint16 rxdalign; /* #bytes added to alloc'd mem to align rxd */ | 126 | u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */ |
127 | uint32 rxdalloc; /* #bytes allocated for the ring */ | 127 | uint32 rxdalloc; /* #bytes allocated for the ring */ |
128 | uint32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */ | 128 | uint32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */ |
129 | 129 | ||
130 | /* tunables */ | 130 | /* tunables */ |
131 | uint16 rxbufsize; /* rx buffer size in bytes, | 131 | u16 rxbufsize; /* rx buffer size in bytes, |
132 | * not including the extra headroom | 132 | * not including the extra headroom |
133 | */ | 133 | */ |
134 | uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper stack | 134 | uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper stack |
@@ -206,8 +206,8 @@ static bool _dma_rxfill(dma_info_t *di); | |||
206 | static void _dma_rxreclaim(dma_info_t *di); | 206 | static void _dma_rxreclaim(dma_info_t *di); |
207 | static void _dma_rxenable(dma_info_t *di); | 207 | static void _dma_rxenable(dma_info_t *di); |
208 | static void *_dma_getnextrxp(dma_info_t *di, bool forceall); | 208 | static void *_dma_getnextrxp(dma_info_t *di, bool forceall); |
209 | static void _dma_rx_param_get(dma_info_t *di, uint16 *rxoffset, | 209 | static void _dma_rx_param_get(dma_info_t *di, u16 *rxoffset, |
210 | uint16 *rxbufsize); | 210 | u16 *rxbufsize); |
211 | 211 | ||
212 | static void _dma_txblock(dma_info_t *di); | 212 | static void _dma_txblock(dma_info_t *di); |
213 | static void _dma_txunblock(dma_info_t *di); | 213 | static void _dma_txunblock(dma_info_t *di); |
@@ -224,7 +224,7 @@ static void _dma_fifoloopbackenable(dma_info_t *di); | |||
224 | static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags); | 224 | static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags); |
225 | static u8 dma_align_sizetobits(uint size); | 225 | static u8 dma_align_sizetobits(uint size); |
226 | static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size, | 226 | static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size, |
227 | uint16 *alignbits, uint *alloced, | 227 | u16 *alignbits, uint *alloced, |
228 | dmaaddr_t *descpa, osldma_t **dmah); | 228 | dmaaddr_t *descpa, osldma_t **dmah); |
229 | 229 | ||
230 | /* Prototypes for 32-bit routines */ | 230 | /* Prototypes for 32-bit routines */ |
@@ -446,18 +446,18 @@ hnddma_t *dma_attach(osl_t *osh, char *name, si_t *sih, void *dmaregstx, | |||
446 | di->sih = sih; | 446 | di->sih = sih; |
447 | 447 | ||
448 | /* save tunables */ | 448 | /* save tunables */ |
449 | di->ntxd = (uint16) ntxd; | 449 | di->ntxd = (u16) ntxd; |
450 | di->nrxd = (uint16) nrxd; | 450 | di->nrxd = (u16) nrxd; |
451 | 451 | ||
452 | /* the actual dma size doesn't include the extra headroom */ | 452 | /* the actual dma size doesn't include the extra headroom */ |
453 | di->rxextrahdrroom = | 453 | di->rxextrahdrroom = |
454 | (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom; | 454 | (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom; |
455 | if (rxbufsize > BCMEXTRAHDROOM) | 455 | if (rxbufsize > BCMEXTRAHDROOM) |
456 | di->rxbufsize = (uint16) (rxbufsize - di->rxextrahdrroom); | 456 | di->rxbufsize = (u16) (rxbufsize - di->rxextrahdrroom); |
457 | else | 457 | else |
458 | di->rxbufsize = (uint16) rxbufsize; | 458 | di->rxbufsize = (u16) rxbufsize; |
459 | 459 | ||
460 | di->nrxpost = (uint16) nrxpost; | 460 | di->nrxpost = (u16) nrxpost; |
461 | di->rxoffset = (u8) rxoffset; | 461 | di->rxoffset = (u8) rxoffset; |
462 | 462 | ||
463 | /* | 463 | /* |
@@ -970,11 +970,11 @@ static void _dma_rxenable(dma_info_t *di) | |||
970 | } | 970 | } |
971 | 971 | ||
972 | static void | 972 | static void |
973 | _dma_rx_param_get(dma_info_t *di, uint16 *rxoffset, uint16 *rxbufsize) | 973 | _dma_rx_param_get(dma_info_t *di, u16 *rxoffset, u16 *rxbufsize) |
974 | { | 974 | { |
975 | /* the normal values fit into 16 bits */ | 975 | /* the normal values fit into 16 bits */ |
976 | *rxoffset = (uint16) di->rxoffset; | 976 | *rxoffset = (u16) di->rxoffset; |
977 | *rxbufsize = (uint16) di->rxbufsize; | 977 | *rxbufsize = (u16) di->rxbufsize; |
978 | } | 978 | } |
979 | 979 | ||
980 | /* !! rx entry routine | 980 | /* !! rx entry routine |
@@ -998,15 +998,15 @@ static void *BCMFASTPATH _dma_rx(dma_info_t *di) | |||
998 | if (head == NULL) | 998 | if (head == NULL) |
999 | return NULL; | 999 | return NULL; |
1000 | 1000 | ||
1001 | len = ltoh16(*(uint16 *) (PKTDATA(head))); | 1001 | len = ltoh16(*(u16 *) (PKTDATA(head))); |
1002 | DMA_TRACE(("%s: dma_rx len %d\n", di->name, len)); | 1002 | DMA_TRACE(("%s: dma_rx len %d\n", di->name, len)); |
1003 | 1003 | ||
1004 | #if defined(__mips__) | 1004 | #if defined(__mips__) |
1005 | if (!len) { | 1005 | if (!len) { |
1006 | while (!(len = *(uint16 *) OSL_UNCACHED(PKTDATA(head)))) | 1006 | while (!(len = *(u16 *) OSL_UNCACHED(PKTDATA(head)))) |
1007 | OSL_DELAY(1); | 1007 | OSL_DELAY(1); |
1008 | 1008 | ||
1009 | *(uint16 *) PKTDATA(head) = htol16((uint16) len); | 1009 | *(u16 *) PKTDATA(head) = htol16((u16) len); |
1010 | } | 1010 | } |
1011 | #endif /* defined(__mips__) */ | 1011 | #endif /* defined(__mips__) */ |
1012 | 1012 | ||
@@ -1064,7 +1064,7 @@ static void *BCMFASTPATH _dma_rx(dma_info_t *di) | |||
1064 | static bool BCMFASTPATH _dma_rxfill(dma_info_t *di) | 1064 | static bool BCMFASTPATH _dma_rxfill(dma_info_t *di) |
1065 | { | 1065 | { |
1066 | void *p; | 1066 | void *p; |
1067 | uint16 rxin, rxout; | 1067 | u16 rxin, rxout; |
1068 | uint32 flags = 0; | 1068 | uint32 flags = 0; |
1069 | uint n; | 1069 | uint n; |
1070 | uint i; | 1070 | uint i; |
@@ -1406,7 +1406,7 @@ u8 dma_align_sizetobits(uint size) | |||
1406 | * not cross page boundary | 1406 | * not cross page boundary |
1407 | */ | 1407 | */ |
1408 | static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size, | 1408 | static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size, |
1409 | uint16 *alignbits, uint *alloced, | 1409 | u16 *alignbits, uint *alloced, |
1410 | dmaaddr_t *descpa, osldma_t **dmah) | 1410 | dmaaddr_t *descpa, osldma_t **dmah) |
1411 | { | 1411 | { |
1412 | void *va; | 1412 | void *va; |
@@ -1522,8 +1522,8 @@ static bool dma32_alloc(dma_info_t *di, uint direction) | |||
1522 | uint ddlen; | 1522 | uint ddlen; |
1523 | void *va; | 1523 | void *va; |
1524 | uint alloced; | 1524 | uint alloced; |
1525 | uint16 align; | 1525 | u16 align; |
1526 | uint16 align_bits; | 1526 | u16 align_bits; |
1527 | 1527 | ||
1528 | ddlen = sizeof(dma32dd_t); | 1528 | ddlen = sizeof(dma32dd_t); |
1529 | 1529 | ||
@@ -1666,7 +1666,7 @@ static int dma32_txfast(dma_info_t *di, void *p0, bool commit) | |||
1666 | void *p, *next; | 1666 | void *p, *next; |
1667 | unsigned char *data; | 1667 | unsigned char *data; |
1668 | uint len; | 1668 | uint len; |
1669 | uint16 txout; | 1669 | u16 txout; |
1670 | uint32 flags = 0; | 1670 | uint32 flags = 0; |
1671 | dmaaddr_t pa; | 1671 | dmaaddr_t pa; |
1672 | 1672 | ||
@@ -1789,8 +1789,8 @@ static int dma32_txfast(dma_info_t *di, void *p0, bool commit) | |||
1789 | */ | 1789 | */ |
1790 | static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range) | 1790 | static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range) |
1791 | { | 1791 | { |
1792 | uint16 start, end, i; | 1792 | u16 start, end, i; |
1793 | uint16 active_desc; | 1793 | u16 active_desc; |
1794 | void *txp; | 1794 | void *txp; |
1795 | 1795 | ||
1796 | DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, | 1796 | DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, |
@@ -1811,14 +1811,14 @@ static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range) | |||
1811 | dma32regs_t *dregs = di->d32txregs; | 1811 | dma32regs_t *dregs = di->d32txregs; |
1812 | 1812 | ||
1813 | end = | 1813 | end = |
1814 | (uint16) B2I(R_REG(di->osh, &dregs->status) & XS_CD_MASK, | 1814 | (u16) B2I(R_REG(di->osh, &dregs->status) & XS_CD_MASK, |
1815 | dma32dd_t); | 1815 | dma32dd_t); |
1816 | 1816 | ||
1817 | if (range == HNDDMA_RANGE_TRANSFERED) { | 1817 | if (range == HNDDMA_RANGE_TRANSFERED) { |
1818 | active_desc = | 1818 | active_desc = |
1819 | (uint16) ((R_REG(di->osh, &dregs->status) & | 1819 | (u16) ((R_REG(di->osh, &dregs->status) & |
1820 | XS_AD_MASK) >> XS_AD_SHIFT); | 1820 | XS_AD_MASK) >> XS_AD_SHIFT); |
1821 | active_desc = (uint16) B2I(active_desc, dma32dd_t); | 1821 | active_desc = (u16) B2I(active_desc, dma32dd_t); |
1822 | if (end != active_desc) | 1822 | if (end != active_desc) |
1823 | end = PREVTXD(active_desc); | 1823 | end = PREVTXD(active_desc); |
1824 | } | 1824 | } |
@@ -1918,17 +1918,17 @@ static void *dma32_getnextrxp(dma_info_t *di, bool forceall) | |||
1918 | */ | 1918 | */ |
1919 | static void dma32_txrotate(dma_info_t *di) | 1919 | static void dma32_txrotate(dma_info_t *di) |
1920 | { | 1920 | { |
1921 | uint16 ad; | 1921 | u16 ad; |
1922 | uint nactive; | 1922 | uint nactive; |
1923 | uint rot; | 1923 | uint rot; |
1924 | uint16 old, new; | 1924 | u16 old, new; |
1925 | uint32 w; | 1925 | uint32 w; |
1926 | uint16 first, last; | 1926 | u16 first, last; |
1927 | 1927 | ||
1928 | ASSERT(dma32_txsuspendedidle(di)); | 1928 | ASSERT(dma32_txsuspendedidle(di)); |
1929 | 1929 | ||
1930 | nactive = _dma_txactive(di); | 1930 | nactive = _dma_txactive(di); |
1931 | ad = (uint16) (B2I | 1931 | ad = (u16) (B2I |
1932 | (((R_REG(di->osh, &di->d32txregs->status) & XS_AD_MASK) | 1932 | (((R_REG(di->osh, &di->d32txregs->status) & XS_AD_MASK) |
1933 | >> XS_AD_SHIFT), dma32dd_t)); | 1933 | >> XS_AD_SHIFT), dma32dd_t)); |
1934 | rot = TXD(ad - di->txin); | 1934 | rot = TXD(ad - di->txin); |
@@ -2088,12 +2088,12 @@ static bool dma64_rxstopped(dma_info_t *di) | |||
2088 | 2088 | ||
2089 | static bool dma64_alloc(dma_info_t *di, uint direction) | 2089 | static bool dma64_alloc(dma_info_t *di, uint direction) |
2090 | { | 2090 | { |
2091 | uint16 size; | 2091 | u16 size; |
2092 | uint ddlen; | 2092 | uint ddlen; |
2093 | void *va; | 2093 | void *va; |
2094 | uint alloced = 0; | 2094 | uint alloced = 0; |
2095 | uint16 align; | 2095 | u16 align; |
2096 | uint16 align_bits; | 2096 | u16 align_bits; |
2097 | 2097 | ||
2098 | ddlen = sizeof(dma64dd_t); | 2098 | ddlen = sizeof(dma64dd_t); |
2099 | 2099 | ||
@@ -2260,7 +2260,7 @@ static void *dma64_getpos(dma_info_t *di, bool direction) | |||
2260 | */ | 2260 | */ |
2261 | static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit) | 2261 | static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit) |
2262 | { | 2262 | { |
2263 | uint16 txout; | 2263 | u16 txout; |
2264 | uint32 flags = 0; | 2264 | uint32 flags = 0; |
2265 | dmaaddr_t pa; /* phys addr */ | 2265 | dmaaddr_t pa; /* phys addr */ |
2266 | 2266 | ||
@@ -2317,7 +2317,7 @@ static int BCMFASTPATH dma64_txfast(dma_info_t *di, void *p0, bool commit) | |||
2317 | void *p, *next; | 2317 | void *p, *next; |
2318 | unsigned char *data; | 2318 | unsigned char *data; |
2319 | uint len; | 2319 | uint len; |
2320 | uint16 txout; | 2320 | u16 txout; |
2321 | uint32 flags = 0; | 2321 | uint32 flags = 0; |
2322 | dmaaddr_t pa; | 2322 | dmaaddr_t pa; |
2323 | 2323 | ||
@@ -2439,8 +2439,8 @@ static int BCMFASTPATH dma64_txfast(dma_info_t *di, void *p0, bool commit) | |||
2439 | */ | 2439 | */ |
2440 | static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range) | 2440 | static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range) |
2441 | { | 2441 | { |
2442 | uint16 start, end, i; | 2442 | u16 start, end, i; |
2443 | uint16 active_desc; | 2443 | u16 active_desc; |
2444 | void *txp; | 2444 | void *txp; |
2445 | 2445 | ||
2446 | DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, | 2446 | DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, |
@@ -2461,14 +2461,14 @@ static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range) | |||
2461 | dma64regs_t *dregs = di->d64txregs; | 2461 | dma64regs_t *dregs = di->d64txregs; |
2462 | 2462 | ||
2463 | end = | 2463 | end = |
2464 | (uint16) (B2I | 2464 | (u16) (B2I |
2465 | (((R_REG(di->osh, &dregs->status0) & | 2465 | (((R_REG(di->osh, &dregs->status0) & |
2466 | D64_XS0_CD_MASK) - | 2466 | D64_XS0_CD_MASK) - |
2467 | di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t)); | 2467 | di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t)); |
2468 | 2468 | ||
2469 | if (range == HNDDMA_RANGE_TRANSFERED) { | 2469 | if (range == HNDDMA_RANGE_TRANSFERED) { |
2470 | active_desc = | 2470 | active_desc = |
2471 | (uint16) (R_REG(di->osh, &dregs->status1) & | 2471 | (u16) (R_REG(di->osh, &dregs->status1) & |
2472 | D64_XS1_AD_MASK); | 2472 | D64_XS1_AD_MASK); |
2473 | active_desc = | 2473 | active_desc = |
2474 | (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK; | 2474 | (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK; |
@@ -2589,17 +2589,17 @@ static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs) | |||
2589 | */ | 2589 | */ |
2590 | static void dma64_txrotate(dma_info_t *di) | 2590 | static void dma64_txrotate(dma_info_t *di) |
2591 | { | 2591 | { |
2592 | uint16 ad; | 2592 | u16 ad; |
2593 | uint nactive; | 2593 | uint nactive; |
2594 | uint rot; | 2594 | uint rot; |
2595 | uint16 old, new; | 2595 | u16 old, new; |
2596 | uint32 w; | 2596 | uint32 w; |
2597 | uint16 first, last; | 2597 | u16 first, last; |
2598 | 2598 | ||
2599 | ASSERT(dma64_txsuspendedidle(di)); | 2599 | ASSERT(dma64_txsuspendedidle(di)); |
2600 | 2600 | ||
2601 | nactive = _dma_txactive(di); | 2601 | nactive = _dma_txactive(di); |
2602 | ad = (uint16) (B2I | 2602 | ad = (u16) (B2I |
2603 | ((((R_REG(di->osh, &di->d64txregs->status1) & | 2603 | ((((R_REG(di->osh, &di->d64txregs->status1) & |
2604 | D64_XS1_AD_MASK) | 2604 | D64_XS1_AD_MASK) |
2605 | - di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t)); | 2605 | - di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t)); |
diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c index 4adbd8c7b91..4ba758a9a08 100644 --- a/drivers/staging/brcm80211/util/hndpmu.c +++ b/drivers/staging/brcm80211/util/hndpmu.c | |||
@@ -185,7 +185,7 @@ BCMATTACHFN(si_pmu_set_ldo_voltage) (si_t *sih, osl_t *osh, u8 ldo, | |||
185 | /* d11 slow to fast clock transition time in slow clock cycles */ | 185 | /* d11 slow to fast clock transition time in slow clock cycles */ |
186 | #define D11SCC_SLOW2FAST_TRANSITION 2 | 186 | #define D11SCC_SLOW2FAST_TRANSITION 2 |
187 | 187 | ||
188 | uint16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh) | 188 | u16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh) |
189 | { | 189 | { |
190 | uint delay = PMU_MAX_TRANSITION_DLY; | 190 | uint delay = PMU_MAX_TRANSITION_DLY; |
191 | chipcregs_t *cc; | 191 | chipcregs_t *cc; |
@@ -259,7 +259,7 @@ uint16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh) | |||
259 | /* Return to original core */ | 259 | /* Return to original core */ |
260 | si_setcoreidx(sih, origidx); | 260 | si_setcoreidx(sih, origidx); |
261 | 261 | ||
262 | return (uint16) delay; | 262 | return (u16) delay; |
263 | } | 263 | } |
264 | 264 | ||
265 | uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force) | 265 | uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force) |
@@ -292,7 +292,7 @@ uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force) | |||
292 | /* Setup resource up/down timers */ | 292 | /* Setup resource up/down timers */ |
293 | typedef struct { | 293 | typedef struct { |
294 | u8 resnum; | 294 | u8 resnum; |
295 | uint16 updown; | 295 | u16 updown; |
296 | } pmu_res_updown_t; | 296 | } pmu_res_updown_t; |
297 | 297 | ||
298 | /* Change resource dependancies masks */ | 298 | /* Change resource dependancies masks */ |
@@ -872,7 +872,7 @@ void BCMATTACHFN(si_pmu_res_init) (si_t *sih, osl_t *osh) | |||
872 | 872 | ||
873 | /* setup pll and query clock speed */ | 873 | /* setup pll and query clock speed */ |
874 | typedef struct { | 874 | typedef struct { |
875 | uint16 freq; | 875 | u16 freq; |
876 | u8 xf; | 876 | u8 xf; |
877 | u8 wbint; | 877 | u8 wbint; |
878 | uint32 wbfrac; | 878 | uint32 wbfrac; |
@@ -902,7 +902,7 @@ static const pmu0_xtaltab0_t BCMINITDATA(pmu0_xtaltab0)[] = { | |||
902 | 902 | ||
903 | /* setup pll and query clock speed */ | 903 | /* setup pll and query clock speed */ |
904 | typedef struct { | 904 | typedef struct { |
905 | uint16 fref; | 905 | u16 fref; |
906 | u8 xf; | 906 | u8 xf; |
907 | u8 p1div; | 907 | u8 p1div; |
908 | u8 p2div; | 908 | u8 p2div; |
diff --git a/drivers/staging/brcm80211/util/linux_osl.c b/drivers/staging/brcm80211/util/linux_osl.c index f6046fe480b..76330a8f6d2 100644 --- a/drivers/staging/brcm80211/util/linux_osl.c +++ b/drivers/staging/brcm80211/util/linux_osl.c | |||
@@ -538,10 +538,10 @@ void *osl_dma_alloc_consistent(osl_t *osh, uint size, unsigned long *pap) | |||
538 | return pci_alloc_consistent(osh->pdev, size, (dma_addr_t *) pap); | 538 | return pci_alloc_consistent(osh->pdev, size, (dma_addr_t *) pap); |
539 | } | 539 | } |
540 | #else /* !BRCM_FULLMAC */ | 540 | #else /* !BRCM_FULLMAC */ |
541 | void *osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits, | 541 | void *osl_dma_alloc_consistent(osl_t *osh, uint size, u16 align_bits, |
542 | uint *alloced, unsigned long *pap) | 542 | uint *alloced, unsigned long *pap) |
543 | { | 543 | { |
544 | uint16 align = (1 << align_bits); | 544 | u16 align = (1 << align_bits); |
545 | ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); | 545 | ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); |
546 | 546 | ||
547 | if (!ISALIGNED(DMA_CONSISTENT_ALIGN, align)) | 547 | if (!ISALIGNED(DMA_CONSISTENT_ALIGN, align)) |
@@ -664,12 +664,12 @@ u8 osl_readb(osl_t *osh, volatile u8 *r) | |||
664 | return (u8) ((rreg) (ctx, (void *)r, sizeof(u8))); | 664 | return (u8) ((rreg) (ctx, (void *)r, sizeof(u8))); |
665 | } | 665 | } |
666 | 666 | ||
667 | uint16 osl_readw(osl_t *osh, volatile uint16 *r) | 667 | u16 osl_readw(osl_t *osh, volatile u16 *r) |
668 | { | 668 | { |
669 | osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn; | 669 | osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn; |
670 | void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; | 670 | void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; |
671 | 671 | ||
672 | return (uint16) ((rreg) (ctx, (void *)r, sizeof(uint16))); | 672 | return (u16) ((rreg) (ctx, (void *)r, sizeof(u16))); |
673 | } | 673 | } |
674 | 674 | ||
675 | uint32 osl_readl(osl_t *osh, volatile uint32 *r) | 675 | uint32 osl_readl(osl_t *osh, volatile uint32 *r) |
@@ -688,12 +688,12 @@ void osl_writeb(osl_t *osh, volatile u8 *r, u8 v) | |||
688 | ((wreg) (ctx, (void *)r, v, sizeof(u8))); | 688 | ((wreg) (ctx, (void *)r, v, sizeof(u8))); |
689 | } | 689 | } |
690 | 690 | ||
691 | void osl_writew(osl_t *osh, volatile uint16 *r, uint16 v) | 691 | void osl_writew(osl_t *osh, volatile u16 *r, u16 v) |
692 | { | 692 | { |
693 | osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn; | 693 | osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn; |
694 | void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; | 694 | void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; |
695 | 695 | ||
696 | ((wreg) (ctx, (void *)r, v, sizeof(uint16))); | 696 | ((wreg) (ctx, (void *)r, v, sizeof(u16))); |
697 | } | 697 | } |
698 | 698 | ||
699 | void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v) | 699 | void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v) |
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c index 49844ec8467..e6b16ea1386 100644 --- a/drivers/staging/brcm80211/util/nicpci.c +++ b/drivers/staging/brcm80211/util/nicpci.c | |||
@@ -484,7 +484,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi) | |||
484 | { | 484 | { |
485 | sbpcieregs_t *pcieregs = pi->regs.pcieregs; | 485 | sbpcieregs_t *pcieregs = pi->regs.pcieregs; |
486 | si_t *sih = pi->sih; | 486 | si_t *sih = pi->sih; |
487 | uint16 val16, *reg16; | 487 | u16 val16, *reg16; |
488 | uint32 w; | 488 | uint32 w; |
489 | 489 | ||
490 | if (!PCIE_ASPM(sih)) | 490 | if (!PCIE_ASPM(sih)) |
@@ -548,7 +548,7 @@ static void pcie_war_serdes(pcicore_info_t *pi) | |||
548 | static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t *pi) | 548 | static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t *pi) |
549 | { | 549 | { |
550 | sbpcieregs_t *pcieregs = pi->regs.pcieregs; | 550 | sbpcieregs_t *pcieregs = pi->regs.pcieregs; |
551 | uint16 val16, *reg16; | 551 | u16 val16, *reg16; |
552 | 552 | ||
553 | reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG]; | 553 | reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG]; |
554 | val16 = R_REG(pi->osh, reg16); | 554 | val16 = R_REG(pi->osh, reg16); |
@@ -564,7 +564,7 @@ static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t *pi) | |||
564 | static void pcie_war_noplldown(pcicore_info_t *pi) | 564 | static void pcie_war_noplldown(pcicore_info_t *pi) |
565 | { | 565 | { |
566 | sbpcieregs_t *pcieregs = pi->regs.pcieregs; | 566 | sbpcieregs_t *pcieregs = pi->regs.pcieregs; |
567 | uint16 *reg16; | 567 | u16 *reg16; |
568 | 568 | ||
569 | ASSERT(pi->sih->buscorerev == 7); | 569 | ASSERT(pi->sih->buscorerev == 7); |
570 | 570 | ||
diff --git a/drivers/staging/brcm80211/util/qmath.c b/drivers/staging/brcm80211/util/qmath.c index f9b30a66cae..05b937dda93 100644 --- a/drivers/staging/brcm80211/util/qmath.c +++ b/drivers/staging/brcm80211/util/qmath.c | |||
@@ -81,9 +81,9 @@ int32 qm_muls321616(int16 op1, int16 op2) | |||
81 | Description: This function make 16 bit unsigned multiplication. To fit the output into | 81 | Description: This function make 16 bit unsigned multiplication. To fit the output into |
82 | 16 bits the 32 bit multiplication result is right shifted by 16 bits. | 82 | 16 bits the 32 bit multiplication result is right shifted by 16 bits. |
83 | */ | 83 | */ |
84 | uint16 qm_mulu16(uint16 op1, uint16 op2) | 84 | u16 qm_mulu16(u16 op1, u16 op2) |
85 | { | 85 | { |
86 | return (uint16) (((uint32) op1 * (uint32) op2) >> 16); | 86 | return (u16) (((uint32) op1 * (uint32) op2) >> 16); |
87 | } | 87 | } |
88 | 88 | ||
89 | /* | 89 | /* |
@@ -258,7 +258,7 @@ Example: qm_norm16(0x0080) = 7. | |||
258 | */ | 258 | */ |
259 | int16 qm_norm16(int16 op) | 259 | int16 qm_norm16(int16 op) |
260 | { | 260 | { |
261 | uint16 u16extraSignBits; | 261 | u16 u16extraSignBits; |
262 | if (op == 0) { | 262 | if (op == 0) { |
263 | return 15; | 263 | return 15; |
264 | } else { | 264 | } else { |
@@ -277,7 +277,7 @@ Example: qm_norm32(0x00000080) = 23 | |||
277 | */ | 277 | */ |
278 | int16 qm_norm32(int32 op) | 278 | int16 qm_norm32(int32 op) |
279 | { | 279 | { |
280 | uint16 u16extraSignBits; | 280 | u16 u16extraSignBits; |
281 | if (op == 0) { | 281 | if (op == 0) { |
282 | return 31; | 282 | return 31; |
283 | } else { | 283 | } else { |
@@ -407,7 +407,7 @@ into 32 bit output. | |||
407 | int32 qm_mul323216(int32 op1, int16 op2) | 407 | int32 qm_mul323216(int32 op1, int16 op2) |
408 | { | 408 | { |
409 | int16 hi; | 409 | int16 hi; |
410 | uint16 lo; | 410 | u16 lo; |
411 | int32 result; | 411 | int32 result; |
412 | hi = op1 >> 16; | 412 | hi = op1 >> 16; |
413 | lo = (int16) (op1 & 0xffff); | 413 | lo = (int16) (op1 & 0xffff); |
@@ -420,7 +420,7 @@ int32 qm_mul323216(int32 op1, int16 op2) | |||
420 | Description: This function multiply signed 16 bit number with unsigned 16 bit number and return | 420 | Description: This function multiply signed 16 bit number with unsigned 16 bit number and return |
421 | the result in 32 bits. | 421 | the result in 32 bits. |
422 | */ | 422 | */ |
423 | int32 qm_mulsu321616(int16 op1, uint16 op2) | 423 | int32 qm_mulsu321616(int16 op1, u16 op2) |
424 | { | 424 | { |
425 | return (int32) (op1) * op2; | 425 | return (int32) (op1) * op2; |
426 | } | 426 | } |
@@ -434,7 +434,7 @@ When the input numbers are 0x80000000, 0x8000 the return value is saturated to 0 | |||
434 | int32 qm_muls323216(int32 op1, int16 op2) | 434 | int32 qm_muls323216(int32 op1, int16 op2) |
435 | { | 435 | { |
436 | int16 hi; | 436 | int16 hi; |
437 | uint16 lo; | 437 | u16 lo; |
438 | int32 result; | 438 | int32 result; |
439 | hi = op1 >> 16; | 439 | hi = op1 >> 16; |
440 | lo = (int16) (op1 & 0xffff); | 440 | lo = (int16) (op1 & 0xffff); |
@@ -451,12 +451,12 @@ multiplication result is returned as output. | |||
451 | int32 qm_mul32(int32 a, int32 b) | 451 | int32 qm_mul32(int32 a, int32 b) |
452 | { | 452 | { |
453 | int16 hi1, hi2; | 453 | int16 hi1, hi2; |
454 | uint16 lo1, lo2; | 454 | u16 lo1, lo2; |
455 | int32 result; | 455 | int32 result; |
456 | hi1 = a >> 16; | 456 | hi1 = a >> 16; |
457 | hi2 = b >> 16; | 457 | hi2 = b >> 16; |
458 | lo1 = (uint16) (a & 0xffff); | 458 | lo1 = (u16) (a & 0xffff); |
459 | lo2 = (uint16) (b & 0xffff); | 459 | lo2 = (u16) (b & 0xffff); |
460 | result = qm_mul321616(hi1, hi2); | 460 | result = qm_mul321616(hi1, hi2); |
461 | result = result + (qm_mulsu321616(hi1, lo2) >> 16); | 461 | result = result + (qm_mulsu321616(hi1, lo2) >> 16); |
462 | result = result + (qm_mulsu321616(hi2, lo1) >> 16); | 462 | result = result + (qm_mulsu321616(hi2, lo1) >> 16); |
@@ -474,12 +474,12 @@ When the input numbers are 0x80000000, 0x80000000 the return value is saturated | |||
474 | int32 qm_muls32(int32 a, int32 b) | 474 | int32 qm_muls32(int32 a, int32 b) |
475 | { | 475 | { |
476 | int16 hi1, hi2; | 476 | int16 hi1, hi2; |
477 | uint16 lo1, lo2; | 477 | u16 lo1, lo2; |
478 | int32 result; | 478 | int32 result; |
479 | hi1 = a >> 16; | 479 | hi1 = a >> 16; |
480 | hi2 = b >> 16; | 480 | hi2 = b >> 16; |
481 | lo1 = (uint16) (a & 0xffff); | 481 | lo1 = (u16) (a & 0xffff); |
482 | lo2 = (uint16) (b & 0xffff); | 482 | lo2 = (u16) (b & 0xffff); |
483 | result = qm_muls321616(hi1, hi2); | 483 | result = qm_muls321616(hi1, hi2); |
484 | result = qm_add32(result, (qm_mulsu321616(hi1, lo2) >> 15)); | 484 | result = qm_add32(result, (qm_mulsu321616(hi1, lo2) >> 15)); |
485 | result = qm_add32(result, (qm_mulsu321616(hi2, lo1) >> 15)); | 485 | result = qm_add32(result, (qm_mulsu321616(hi2, lo1) >> 15)); |
@@ -548,7 +548,7 @@ For accurate results input should be in normalized or near normalized form. | |||
548 | void qm_log10(int32 N, int16 qN, int16 *log10N, int16 *qLog10N) | 548 | void qm_log10(int32 N, int16 qN, int16 *log10N, int16 *qLog10N) |
549 | { | 549 | { |
550 | int16 s16norm, s16tableIndex, s16errorApproximation; | 550 | int16 s16norm, s16tableIndex, s16errorApproximation; |
551 | uint16 u16offset; | 551 | u16 u16offset; |
552 | int32 s32log; | 552 | int32 s32log; |
553 | 553 | ||
554 | /* Logerithm of negative values is undefined. | 554 | /* Logerithm of negative values is undefined. |
@@ -580,13 +580,13 @@ void qm_log10(int32 N, int16 qN, int16 *log10N, int16 *qLog10N) | |||
580 | 580 | ||
581 | /* take the offset as the 16 MSBS after table index. | 581 | /* take the offset as the 16 MSBS after table index. |
582 | */ | 582 | */ |
583 | u16offset = (uint16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16))); | 583 | u16offset = (u16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16))); |
584 | 584 | ||
585 | /* look the log value in the table. */ | 585 | /* look the log value in the table. */ |
586 | s32log = log_table[s16tableIndex]; /* q.15 format */ | 586 | s32log = log_table[s16tableIndex]; /* q.15 format */ |
587 | 587 | ||
588 | /* interpolate using the offset. */ | 588 | /* interpolate using the offset. */ |
589 | s16errorApproximation = (int16) qm_mulu16(u16offset, (uint16) (log_table[s16tableIndex + 1] - log_table[s16tableIndex])); /* q.15 */ | 589 | s16errorApproximation = (int16) qm_mulu16(u16offset, (u16) (log_table[s16tableIndex + 1] - log_table[s16tableIndex])); /* q.15 */ |
590 | 590 | ||
591 | s32log = qm_add16((int16) s32log, s16errorApproximation); /* q.15 format */ | 591 | s32log = qm_add16((int16) s32log, s16errorApproximation); /* q.15 format */ |
592 | 592 | ||
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c index 1a4c2b65499..73b8a00a743 100644 --- a/drivers/staging/brcm80211/util/siutils.c +++ b/drivers/staging/brcm80211/util/siutils.c | |||
@@ -320,13 +320,13 @@ static __used void BCMATTACHFN(si_nvram_process) (si_info_t *sii, char *pvars) | |||
320 | /* do a pci config read to get subsystem id and subvendor id */ | 320 | /* do a pci config read to get subsystem id and subvendor id */ |
321 | w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32)); | 321 | w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32)); |
322 | /* Let nvram variables override subsystem Vend/ID */ | 322 | /* Let nvram variables override subsystem Vend/ID */ |
323 | sii->pub.boardvendor = (uint16)si_getdevpathintvar(&sii->pub, | 323 | sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub, |
324 | "boardvendor"); | 324 | "boardvendor"); |
325 | if (sii->pub.boardvendor == 0) | 325 | if (sii->pub.boardvendor == 0) |
326 | sii->pub.boardvendor = w & 0xffff; | 326 | sii->pub.boardvendor = w & 0xffff; |
327 | else | 327 | else |
328 | SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff)); | 328 | SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff)); |
329 | sii->pub.boardtype = (uint16)si_getdevpathintvar(&sii->pub, | 329 | sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub, |
330 | "boardtype"); | 330 | "boardtype"); |
331 | if (sii->pub.boardtype == 0) | 331 | if (sii->pub.boardtype == 0) |
332 | sii->pub.boardtype = (w >> 16) & 0xffff; | 332 | sii->pub.boardtype = (w >> 16) & 0xffff; |
@@ -1389,23 +1389,23 @@ void si_watchdog_ms(si_t *sih, uint32 ms) | |||
1389 | si_watchdog(sih, wd_msticks * ms); | 1389 | si_watchdog(sih, wd_msticks * ms); |
1390 | } | 1390 | } |
1391 | 1391 | ||
1392 | uint16 BCMATTACHFN(si_d11_devid) (si_t *sih) | 1392 | u16 BCMATTACHFN(si_d11_devid) (si_t *sih) |
1393 | { | 1393 | { |
1394 | si_info_t *sii = SI_INFO(sih); | 1394 | si_info_t *sii = SI_INFO(sih); |
1395 | uint16 device; | 1395 | u16 device; |
1396 | 1396 | ||
1397 | /* normal case: nvram variable with devpath->devid->wl0id */ | 1397 | /* normal case: nvram variable with devpath->devid->wl0id */ |
1398 | device = (uint16) si_getdevpathintvar(sih, "devid"); | 1398 | device = (u16) si_getdevpathintvar(sih, "devid"); |
1399 | if (device != 0) | 1399 | if (device != 0) |
1400 | goto bail; | 1400 | goto bail; |
1401 | 1401 | ||
1402 | /* Get devid from OTP/SPROM depending on where the SROM is read */ | 1402 | /* Get devid from OTP/SPROM depending on where the SROM is read */ |
1403 | device = (uint16) getintvar(sii->vars, "devid"); | 1403 | device = (u16) getintvar(sii->vars, "devid"); |
1404 | if (device != 0) | 1404 | if (device != 0) |
1405 | goto bail; | 1405 | goto bail; |
1406 | 1406 | ||
1407 | /* no longer support wl0id, but keep the code here for backward compatibility. */ | 1407 | /* no longer support wl0id, but keep the code here for backward compatibility. */ |
1408 | device = (uint16) getintvar(sii->vars, "wl0id"); | 1408 | device = (u16) getintvar(sii->vars, "wl0id"); |
1409 | if (device != 0) | 1409 | if (device != 0) |
1410 | goto bail; | 1410 | goto bail; |
1411 | 1411 | ||
@@ -1543,13 +1543,13 @@ void BCMINITFN(si_clkctl_init) (si_t *sih) | |||
1543 | } | 1543 | } |
1544 | 1544 | ||
1545 | /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */ | 1545 | /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */ |
1546 | uint16 BCMINITFN(si_clkctl_fast_pwrup_delay) (si_t *sih) | 1546 | u16 BCMINITFN(si_clkctl_fast_pwrup_delay) (si_t *sih) |
1547 | { | 1547 | { |
1548 | si_info_t *sii; | 1548 | si_info_t *sii; |
1549 | uint origidx = 0; | 1549 | uint origidx = 0; |
1550 | chipcregs_t *cc; | 1550 | chipcregs_t *cc; |
1551 | uint slowminfreq; | 1551 | uint slowminfreq; |
1552 | uint16 fpdelay; | 1552 | u16 fpdelay; |
1553 | uint intr_val = 0; | 1553 | uint intr_val = 0; |
1554 | bool fast; | 1554 | bool fast; |
1555 | 1555 | ||
@@ -2183,7 +2183,7 @@ int si_pci_fixcfg(si_t *sih) | |||
2183 | sbpciregs_t *pciregs = NULL; | 2183 | sbpciregs_t *pciregs = NULL; |
2184 | sbpcieregs_t *pcieregs = NULL; | 2184 | sbpcieregs_t *pcieregs = NULL; |
2185 | void *regs = NULL; | 2185 | void *regs = NULL; |
2186 | uint16 val16, *reg16 = NULL; | 2186 | u16 val16, *reg16 = NULL; |
2187 | 2187 | ||
2188 | si_info_t *sii = SI_INFO(sih); | 2188 | si_info_t *sii = SI_INFO(sih); |
2189 | 2189 | ||
@@ -2208,9 +2208,9 @@ int si_pci_fixcfg(si_t *sih) | |||
2208 | } | 2208 | } |
2209 | pciidx = si_coreidx(&sii->pub); | 2209 | pciidx = si_coreidx(&sii->pub); |
2210 | val16 = R_REG(sii->osh, reg16); | 2210 | val16 = R_REG(sii->osh, reg16); |
2211 | if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16) pciidx) { | 2211 | if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) { |
2212 | val16 = | 2212 | val16 = |
2213 | (uint16) (pciidx << SRSH_PI_SHIFT) | (val16 & | 2213 | (u16) (pciidx << SRSH_PI_SHIFT) | (val16 & |
2214 | ~SRSH_PI_MASK); | 2214 | ~SRSH_PI_MASK); |
2215 | W_REG(sii->osh, reg16, val16); | 2215 | W_REG(sii->osh, reg16, val16); |
2216 | } | 2216 | } |