diff options
Diffstat (limited to 'drivers/staging/bcm/Macros.h')
-rw-r--r-- | drivers/staging/bcm/Macros.h | 399 |
1 files changed, 399 insertions, 0 deletions
diff --git a/drivers/staging/bcm/Macros.h b/drivers/staging/bcm/Macros.h new file mode 100644 index 00000000000..f559b599bd2 --- /dev/null +++ b/drivers/staging/bcm/Macros.h | |||
@@ -0,0 +1,399 @@ | |||
1 | /************************************* | ||
2 | * Macros.h | ||
3 | **************************************/ | ||
4 | #ifndef __MACROS_H__ | ||
5 | #define __MACROS_H__ | ||
6 | |||
7 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) | ||
8 | #define kthread_run(threadfn,data,datafmt)(struct task_struct *)kernel_thread(threadfn,data,0) | ||
9 | #endif | ||
10 | |||
11 | #define TX_TIMER_PERIOD 10 //10 msec | ||
12 | #define MAX_CLASSIFIERS 100 | ||
13 | //#define MAX_CLASSIFIERS_PER_SF 20 | ||
14 | #define MAX_TARGET_DSX_BUFFERS 24 | ||
15 | |||
16 | #define MAX_CNTRL_PKTS 100 | ||
17 | #define MAX_DATA_PKTS 200 | ||
18 | #define MAX_ETH_SIZE 1536 | ||
19 | #define MAX_CNTL_PKT_SIZE 2048 | ||
20 | /* TIMER RELATED */ | ||
21 | #define JIFFIES_2_QUADPART() (ULONG)(jiffies * 10000) // jiffies(1msec) to Quadpart(100nsec) | ||
22 | |||
23 | #define MTU_SIZE 1400 | ||
24 | |||
25 | #define MAC_ADDR_REGISTER 0xbf60d000 | ||
26 | |||
27 | |||
28 | ///////////Quality of Service/////////////////////////// | ||
29 | #define NO_OF_QUEUES 17 | ||
30 | #define HiPriority NO_OF_QUEUES-1 | ||
31 | #define LowPriority 0 | ||
32 | #define BE 2 | ||
33 | #define rtPS 4 | ||
34 | #define ERTPS 5 | ||
35 | #define UGS 6 | ||
36 | |||
37 | #define BE_BUCKET_SIZE 1024*1024*100 //32kb | ||
38 | #define rtPS_BUCKET_SIZE 1024*1024*100 //8kb | ||
39 | #define MAX_ALLOWED_RATE 1024*1024*100 | ||
40 | #define TX_PACKET_THRESHOLD 10 | ||
41 | #define XSECONDS 1*HZ | ||
42 | #define DSC_ACTIVATE_REQUEST 248 | ||
43 | #define QUEUE_DEPTH_OFFSET 0x1fc01000 | ||
44 | #define MAX_DEVICE_DESC_SIZE 2040 | ||
45 | #define MAX_CTRL_QUEUE_LEN 100 | ||
46 | #define MAX_APP_QUEUE_LEN 200 | ||
47 | #define MAX_LATENCY_ALLOWED 0xFFFFFFFF | ||
48 | #define DEFAULT_UG_INTERVAL 250 | ||
49 | #define DEFAULT_UGI_FACTOR 4 | ||
50 | |||
51 | #define DEFAULT_PERSFCOUNT 60 | ||
52 | #define MAX_CONNECTIONS 10 | ||
53 | #define MAX_CLASS_NAME_LENGTH 32 | ||
54 | |||
55 | #define ETH_LENGTH_OF_ADDRESS 6 | ||
56 | #define MAX_MULTICAST_ADDRESSES 32 | ||
57 | #define IP_LENGTH_OF_ADDRESS 4 | ||
58 | |||
59 | #define IP_PACKET_ONLY_MODE 0 | ||
60 | #define ETH_PACKET_TUNNELING_MODE 1 | ||
61 | |||
62 | ////////////Link Request////////////// | ||
63 | #define SET_MAC_ADDRESS_REQUEST 0 | ||
64 | #define SYNC_UP_REQUEST 1 | ||
65 | #define SYNCED_UP 2 | ||
66 | #define LINK_UP_REQUEST 3 | ||
67 | #define LINK_CONNECTED 4 | ||
68 | #define SYNC_UP_NOTIFICATION 2 | ||
69 | #define LINK_UP_NOTIFICATION 4 | ||
70 | |||
71 | |||
72 | #define LINK_NET_ENTRY 0x0002 | ||
73 | #define HMC_STATUS 0x0004 | ||
74 | #define LINK_UP_CONTROL_REQ 0x83 | ||
75 | |||
76 | #define STATS_POINTER_REQ_STATUS 0x86 | ||
77 | #define NETWORK_ENTRY_REQ_PAYLOAD 198 | ||
78 | #define LINK_DOWN_REQ_PAYLOAD 226 | ||
79 | #define SYNC_UP_REQ_PAYLOAD 228 | ||
80 | #define STATISTICS_POINTER_REQ 237 | ||
81 | #define LINK_UP_REQ_PAYLOAD 245 | ||
82 | #define LINK_UP_ACK 246 | ||
83 | |||
84 | #define STATS_MSG_SIZE 4 | ||
85 | #define INDEX_TO_DATA 4 | ||
86 | |||
87 | #define GO_TO_IDLE_MODE_PAYLOAD 210 | ||
88 | #define COME_UP_FROM_IDLE_MODE_PAYLOAD 211 | ||
89 | #define IDLE_MODE_SF_UPDATE_MSG 187 | ||
90 | |||
91 | #define SKB_RESERVE_ETHERNET_HEADER 16 | ||
92 | #define SKB_RESERVE_PHS_BYTES 32 | ||
93 | |||
94 | #define IP_PACKET_ONLY_MODE 0 | ||
95 | #define ETH_PACKET_TUNNELING_MODE 1 | ||
96 | |||
97 | #define ETH_CS_802_3 1 | ||
98 | #define ETH_CS_802_1Q_VLAN 3 | ||
99 | #define IPV4_CS 1 | ||
100 | #define IPV6_CS 2 | ||
101 | #define ETH_CS_MASK 0x3f | ||
102 | |||
103 | /** \brief Validity bit maps for TLVs in packet classification rule */ | ||
104 | |||
105 | #define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0 | ||
106 | #define PKT_CLASSIFICATION_VLANID_VALID 1 | ||
107 | |||
108 | #ifndef MIN | ||
109 | #define MIN(_a, _b) ((_a) < (_b)? (_a): (_b)) | ||
110 | #endif | ||
111 | |||
112 | |||
113 | /*Leader related terms */ | ||
114 | #define LEADER_STATUS 0x00 | ||
115 | #define LEADER_STATUS_TCP_ACK 0x1 | ||
116 | #define LEADER_SIZE sizeof(LEADER) | ||
117 | #define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND) | ||
118 | #define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND) | ||
119 | #define CM_REQUEST_SIZE LEADER_SIZE + sizeof(stLocalSFChangeRequest) | ||
120 | #define IDLE_REQ_SIZE sizeof(PACKETTOSEND) | ||
121 | |||
122 | |||
123 | #define MAX_TRANSFER_CTRL_BYTE_USB 2 * 1024 | ||
124 | |||
125 | #define GET_MAILBOX1_REG_REQUEST 0x87 | ||
126 | #define GET_MAILBOX1_REG_RESPONSE 0x67 | ||
127 | #define VCID_CONTROL_PACKET 0x00 | ||
128 | |||
129 | #define TRANSMIT_NETWORK_DATA 0x00 | ||
130 | #define RECEIVED_NETWORK_DATA 0x20 | ||
131 | |||
132 | #define CM_RESPONSES 0xA0 | ||
133 | #define STATUS_RSP 0xA1 | ||
134 | #define LINK_CONTROL_RESP 0xA2 | ||
135 | #define IDLE_MODE_STATUS 0xA3 | ||
136 | #define STATS_POINTER_RESP 0xA6 | ||
137 | #define MGMT_MSG_INFO_SW_STATUS 0xA7 | ||
138 | #define AUTH_SS_HOST_MSG 0xA8 | ||
139 | |||
140 | #define CM_DSA_ACK_PAYLOAD 247 | ||
141 | #define CM_DSC_ACK_PAYLOAD 248 | ||
142 | #define CM_DSD_ACK_PAYLOAD 249 | ||
143 | #define CM_DSDEACTVATE 250 | ||
144 | #define TOTAL_MASKED_ADDRESS_IN_BYTES 32 | ||
145 | |||
146 | #define MAC_REQ 0 | ||
147 | #define LINK_RESP 1 | ||
148 | #define RSSI_INDICATION 2 | ||
149 | |||
150 | #define SS_INFO 4 | ||
151 | #define STATISTICS_INFO 5 | ||
152 | #define CM_INDICATION 6 | ||
153 | #define PARAM_RESP 7 | ||
154 | #define BUFFER_1K 1024 | ||
155 | #define BUFFER_2K BUFFER_1K*2 | ||
156 | #define BUFFER_4K BUFFER_2K*2 | ||
157 | #define BUFFER_8K BUFFER_4K*2 | ||
158 | #define BUFFER_16K BUFFER_8K*2 | ||
159 | #define DOWNLINK_DIR 0 | ||
160 | #define UPLINK_DIR 1 | ||
161 | |||
162 | #define BCM_SIGNATURE "BECEEM" | ||
163 | |||
164 | |||
165 | #define GPIO_OUTPUT_REGISTER 0x0F00003C | ||
166 | #define BCM_GPIO_OUTPUT_SET_REG 0x0F000040 | ||
167 | #define BCM_GPIO_OUTPUT_CLR_REG 0x0F000044 | ||
168 | #define GPIO_MODE_REGISTER 0x0F000034 | ||
169 | #define GPIO_PIN_STATE_REGISTER 0x0F000038 | ||
170 | |||
171 | |||
172 | typedef struct _LINK_STATE { | ||
173 | UCHAR ucLinkStatus; | ||
174 | UCHAR bIdleMode; | ||
175 | UCHAR bShutdownMode; | ||
176 | }LINK_STATE, *PLINK_STATE; | ||
177 | |||
178 | |||
179 | enum enLinkStatus { | ||
180 | WAIT_FOR_SYNC = 1, | ||
181 | PHY_SYNC_ACHIVED = 2, | ||
182 | LINKUP_IN_PROGRESS = 3, | ||
183 | LINKUP_DONE = 4, | ||
184 | DREG_RECIEVED = 5, | ||
185 | LINK_STATUS_RESET_RECIEVED = 6, | ||
186 | PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7, | ||
187 | LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8, | ||
188 | COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW =9 | ||
189 | }; | ||
190 | |||
191 | typedef enum _E_PHS_DSC_ACTION | ||
192 | { | ||
193 | eAddPHSRule=0, | ||
194 | eSetPHSRule, | ||
195 | eDeletePHSRule, | ||
196 | eDeleteAllPHSRules | ||
197 | }E_PHS_DSC_ACTION; | ||
198 | |||
199 | |||
200 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 // Host to Mac | ||
201 | #define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 // Mac to Host | ||
202 | #define MASK_DISABLE_HEADER_SUPPRESSION 0x10 //0b000010000 | ||
203 | #define MINIMUM_PENDING_DESCRIPTORS 5 | ||
204 | |||
205 | #define SHUTDOWN_HOSTINITIATED_REQUESTPAYLOAD 0xCC | ||
206 | #define SHUTDOWN_ACK_FROM_DRIVER 0x1 | ||
207 | #define SHUTDOWN_NACK_FROM_DRIVER 0x2 | ||
208 | |||
209 | #define LINK_SYNC_UP_SUBTYPE 0x0001 | ||
210 | #define LINK_SYNC_DOWN_SUBTYPE 0x0001 | ||
211 | |||
212 | |||
213 | |||
214 | #define CONT_MODE 1 | ||
215 | #define SINGLE_DESCRIPTOR 1 | ||
216 | |||
217 | |||
218 | #define DESCRIPTOR_LENGTH 0x30 | ||
219 | #define FIRMWARE_DESCS_ADDRESS 0x1F100000 | ||
220 | |||
221 | |||
222 | #define CLOCK_RESET_CNTRL_REG_1 0x0F00000C | ||
223 | #define CLOCK_RESET_CNTRL_REG_2 0x0F000840 | ||
224 | |||
225 | |||
226 | |||
227 | #define TX_DESCRIPTOR_HEAD_REGISTER 0x0F010034 | ||
228 | #define RX_DESCRIPTOR_HEAD_REGISTER 0x0F010094 | ||
229 | |||
230 | #define STATISTICS_BEGIN_ADDR 0xbf60f02c | ||
231 | |||
232 | #define MAX_PENDING_CTRL_PACKET (MAX_CTRL_QUEUE_LEN-10) | ||
233 | |||
234 | #define WIMAX_MAX_MTU MTU_SIZE + ETH_HLEN | ||
235 | #define AUTO_LINKUP_ENABLE 0x2 | ||
236 | #define AUTO_SYNC_DISABLE 0x1 | ||
237 | #define AUTO_FIRM_DOWNLOAD 0x1 | ||
238 | #define SETTLE_DOWN_TIME 50 | ||
239 | |||
240 | #define HOST_BUS_SUSPEND_BIT 16 | ||
241 | |||
242 | #define IDLE_MESSAGE 0x81 | ||
243 | |||
244 | #define MIPS_CLOCK_133MHz 1 | ||
245 | |||
246 | #define TARGET_CAN_GO_TO_IDLE_MODE 2 | ||
247 | #define TARGET_CAN_NOT_GO_TO_IDLE_MODE 3 | ||
248 | #define IDLE_MODE_PAYLOAD_LENGTH 8 | ||
249 | |||
250 | #define IP_HEADER(Buffer) ((IPHeaderFormat*)(Buffer)) | ||
251 | #define IPV4 4 | ||
252 | #define IP_VERSION(byte) (((byte&0xF0)>>4)) | ||
253 | |||
254 | #define SET_MAC_ADDRESS 193 | ||
255 | #define SET_MAC_ADDRESS_RESPONSE 236 | ||
256 | |||
257 | #define IDLE_MODE_WAKEUP_PATTERN 0xd0ea1d1e | ||
258 | #define IDLE_MODE_WAKEUP_NOTIFIER_ADDRESS 0x1FC02FA8 | ||
259 | #define IDLE_MODE_MAX_RETRY_COUNT 1000 | ||
260 | |||
261 | #ifdef REL_4_1 | ||
262 | #define CONFIG_BEGIN_ADDR 0xBF60B004 | ||
263 | #else | ||
264 | #define CONFIG_BEGIN_ADDR 0xBF60B000 | ||
265 | #endif | ||
266 | |||
267 | #define FIRMWARE_BEGIN_ADDR 0xBFC00000 | ||
268 | |||
269 | #define INVALID_QUEUE_INDEX (USHORT)-1 | ||
270 | |||
271 | #define INVALID_PID (pid_t)-1 | ||
272 | #define DDR_80_MHZ 0 | ||
273 | #define DDR_100_MHZ 1 | ||
274 | #define DDR_120_MHZ 2 // Additional Frequency for T3LP | ||
275 | #define DDR_133_MHZ 3 | ||
276 | #define DDR_140_MHZ 4 // Not Used (Reserved for future) | ||
277 | #define DDR_160_MHZ 5 // Additional Frequency for T3LP | ||
278 | #define DDR_180_MHZ 6 // Not Used (Reserved for future) | ||
279 | #define DDR_200_MHZ 7 // Not Used (Reserved for future) | ||
280 | |||
281 | #define MIPS_200_MHZ 0 | ||
282 | #define MIPS_160_MHZ 1 | ||
283 | |||
284 | #define PLL_800_MHZ 0 | ||
285 | #define PLL_266_MHZ 1 | ||
286 | |||
287 | #define DEVICE_POWERSAVE_MODE_AS_MANUAL_CLOCK_GATING 0 | ||
288 | #define DEVICE_POWERSAVE_MODE_AS_PMU_CLOCK_GATING 1 | ||
289 | #define DEVICE_POWERSAVE_MODE_AS_PMU_SHUTDOWN 2 | ||
290 | #define DEVICE_POWERSAVE_MODE_AS_RESERVED 3 | ||
291 | #define DEVICE_POWERSAVE_MODE_AS_PROTOCOL_IDLE_MODE 4 | ||
292 | |||
293 | |||
294 | #define EEPROM_REJECT_REG_1 0x0f003018 | ||
295 | #define EEPROM_REJECT_REG_2 0x0f00301c | ||
296 | #define EEPROM_REJECT_REG_3 0x0f003008 | ||
297 | #define EEPROM_REJECT_REG_4 0x0f003020 | ||
298 | #define EEPROM_REJECT_MASK 0x0fffffff | ||
299 | #define VSG_MODE 0x3 | ||
300 | |||
301 | /* Idle Mode Related Registers */ | ||
302 | #define DEBUG_INTERRUPT_GENERATOR_REGISTOR 0x0F00007C | ||
303 | #ifdef BCM_SHM_INTERFACE | ||
304 | #define SW_ABORT_IDLEMODE_LOC 0xbfc02f9c | ||
305 | #define CPE_VIRTUAL_MAILBOX_REG 0xBFC02E58 | ||
306 | #else | ||
307 | #define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC | ||
308 | #endif | ||
309 | |||
310 | #define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e | ||
311 | #define DEVICE_INT_OUT_EP_REG0 0x0F011870 | ||
312 | #define DEVICE_INT_OUT_EP_REG1 0x0F011874 | ||
313 | |||
314 | #define BIN_FILE "/lib/firmware/macxvi200.bin" | ||
315 | #define CFG_FILE "/lib/firmware/macxvi.cfg" | ||
316 | #define SF_MAX_ALLOWED_PACKETS_TO_BACKUP 128 | ||
317 | #define MIN_VAL(x,y) ((x)<(y)?(x):(y)) | ||
318 | #define MAC_ADDRESS_SIZE 6 | ||
319 | #define EEPROM_COMMAND_Q_REG 0x0F003018 | ||
320 | #define EEPROM_READ_DATA_Q_REG 0x0F003020 | ||
321 | #define CHIP_ID_REG 0x0F000000 | ||
322 | #define GPIO_MODE_REG 0x0F000034 | ||
323 | #define GPIO_OUTPUT_REG 0x0F00003C | ||
324 | #define WIMAX_MAX_ALLOWED_RATE 1024*1024*50 | ||
325 | |||
326 | #define T3 0xbece0300 | ||
327 | #define TARGET_SFID_TXDESC_MAP_LOC 0xBFFFF400 | ||
328 | |||
329 | #define RWM_READ 0 | ||
330 | #define RWM_WRITE 1 | ||
331 | |||
332 | #define T3LPB 0xbece3300 | ||
333 | #define BCS220_2 0xbece3311 | ||
334 | #define BCS220_2BC 0xBECE3310 | ||
335 | #define BCS250_BC 0xbece3301 | ||
336 | #define BCS220_3 0xbece3321 | ||
337 | |||
338 | |||
339 | #define HPM_CONFIG_LDO145 0x0F000D54 | ||
340 | #define HPM_CONFIG_MSW 0x0F000D58 | ||
341 | |||
342 | #define T3B 0xbece0310 | ||
343 | typedef enum eNVM_TYPE | ||
344 | { | ||
345 | NVM_AUTODETECT = 0, | ||
346 | NVM_EEPROM, | ||
347 | NVM_FLASH, | ||
348 | NVM_UNKNOWN | ||
349 | }NVM_TYPE; | ||
350 | |||
351 | typedef enum ePMU_MODES | ||
352 | { | ||
353 | HYBRID_MODE_7C = 0, | ||
354 | INTERNAL_MODE_6 = 1, | ||
355 | HYBRID_MODE_6 = 2 | ||
356 | }PMU_MODE; | ||
357 | |||
358 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) | ||
359 | #define MAX_RDM_WRM_RETIRES 16 | ||
360 | #else | ||
361 | #define MAX_RDM_WRM_RETIRES 1 | ||
362 | #endif | ||
363 | |||
364 | |||
365 | enum eAbortPattern { | ||
366 | ABORT_SHUTDOWN_MODE = 1, | ||
367 | ABORT_IDLE_REG = 1, | ||
368 | ABORT_IDLE_MODE = 2, | ||
369 | ABORT_IDLE_SYNCDOWN = 3 | ||
370 | }; | ||
371 | |||
372 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) | ||
373 | #define GET_BCM_ADAPTER(net_dev) ({\ | ||
374 | PMINI_ADAPTER __Adapter = NULL; \ | ||
375 | if (net_dev) { \ | ||
376 | __Adapter = (PMINI_ADAPTER)(net_dev->priv); \ | ||
377 | } \ | ||
378 | else { \ | ||
379 | __Adapter = NULL; \ | ||
380 | }__Adapter;} ) | ||
381 | #else | ||
382 | #define GET_BCM_ADAPTER(net_dev) ({\ | ||
383 | PMINI_ADAPTER __Adapter = NULL; \ | ||
384 | if (net_dev) { \ | ||
385 | __Adapter = (PMINI_ADAPTER)(*((UINT *)netdev_priv(net_dev))); \ | ||
386 | } \ | ||
387 | else { \ | ||
388 | __Adapter = NULL; \ | ||
389 | }__Adapter;}) | ||
390 | |||
391 | |||
392 | #endif | ||
393 | |||
394 | /* Offsets used by driver in skb cb variable */ | ||
395 | #define SKB_CB_CLASSIFICATION_OFFSET 0 | ||
396 | #define SKB_CB_LATENCY_OFFSET 1 | ||
397 | #define SKB_CB_TCPACK_OFFSET 2 | ||
398 | |||
399 | #endif //__MACROS_H__ | ||