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path: root/drivers/staging/bcm/DDRInit.c
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-rw-r--r--drivers/staging/bcm/DDRInit.c1302
1 files changed, 1302 insertions, 0 deletions
diff --git a/drivers/staging/bcm/DDRInit.c b/drivers/staging/bcm/DDRInit.c
new file mode 100644
index 00000000000..8907e211d48
--- /dev/null
+++ b/drivers/staging/bcm/DDRInit.c
@@ -0,0 +1,1302 @@
1#include "headers.h"
2
3#ifndef BCM_SHM_INTERFACE
4
5
6#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
7#define MIPS_CLOCK_REG 0x0f000820
8
9 //DDR INIT-133Mhz
10#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 //index for 0x0F007000
11static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
12 {0x0F000800,0x00007212},
13 {0x0f000820,0x07F13FFF},
14 {0x0f000810,0x00000F95},
15 {0x0f000860,0x00000000},
16 {0x0f000880,0x000003DD},
17 // Changed source for X-bar and MIPS clock to APLL
18 {0x0f000840,0x0FFF1B00},
19 {0x0f000870,0x00000002},
20 {0x0F00a044,0x1fffffff},
21 {0x0F00a040,0x1f000000},
22 {0x0F00a084,0x1Cffffff},
23 {0x0F00a080,0x1C000000},
24 {0x0F00a04C,0x0000000C},
25 //Memcontroller Default values
26 {0x0F007000,0x00010001},
27 {0x0F007004,0x01010100},
28 {0x0F007008,0x01000001},
29 {0x0F00700c,0x00000000},
30 {0x0F007010,0x01000000},
31 {0x0F007014,0x01000100},
32 {0x0F007018,0x01000000},
33 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
34 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
35 {0x0F007024,0x02000007},
36 {0x0F007028,0x02020202},
37 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
38 {0x0F007030,0x05000000},
39 {0x0F007034,0x00000003},
40 {0x0F007038,0x110a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
41 {0x0F00703C,0x02101010},//ROB - 0x02101010,//0x02101018},
42 {0x0F007040,0x45751200},//ROB - 0x45751200,//0x450f1200},
43 {0x0F007044,0x110a0d00},//ROB - 0x110a0d00//0x111f0d00
44 {0x0F007048,0x081b0306},
45 {0x0F00704c,0x00000000},
46 {0x0F007050,0x0000001c},
47 {0x0F007054,0x00000000},
48 {0x0F007058,0x00000000},
49 {0x0F00705c,0x00000000},
50 {0x0F007060,0x0010246c},
51 {0x0F007064,0x00000010},
52 {0x0F007068,0x00000000},
53 {0x0F00706c,0x00000001},
54 {0x0F007070,0x00007000},
55 {0x0F007074,0x00000000},
56 {0x0F007078,0x00000000},
57 {0x0F00707C,0x00000000},
58 {0x0F007080,0x00000000},
59 {0x0F007084,0x00000000},
60 //# Enable BW improvement within memory controller
61 {0x0F007094,0x00000104},
62 //# Enable 2 ports within X-bar
63 {0x0F00A000,0x00000016},
64 //# Enable start bit within memory controller
65 {0x0F007018,0x01010000}
66 };
67//80Mhz
68#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 //index for 0x0F007000
69static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// # DPLL Clock Setting
70 {0x0f000810,0x00000F95},
71 {0x0f000820,0x07f1ffff},
72 {0x0f000860,0x00000000},
73 {0x0f000880,0x000003DD},
74 {0x0F00a044,0x1fffffff},
75 {0x0F00a040,0x1f000000},
76 {0x0F00a084,0x1Cffffff},
77 {0x0F00a080,0x1C000000},
78 {0x0F00a000,0x00000016},
79 {0x0F00a04C,0x0000000C},
80 //Memcontroller Default values
81 {0x0F007000,0x00010001},
82 {0x0F007004,0x01000000},
83 {0x0F007008,0x01000001},
84 {0x0F00700c,0x00000000},
85 {0x0F007010,0x01000000},
86 {0x0F007014,0x01000100},
87 {0x0F007018,0x01000000},
88 {0x0F00701c,0x01020000},
89 {0x0F007020,0x04020107},
90 {0x0F007024,0x00000007},
91 {0x0F007028,0x02020201},
92 {0x0F00702c,0x0204040a},
93 {0x0F007030,0x04000000},
94 {0x0F007034,0x00000002},
95 {0x0F007038,0x1F060200},
96 {0x0F00703C,0x1C22221F},
97 {0x0F007040,0x8A006600},
98 {0x0F007044,0x221a0800},
99 {0x0F007048,0x02690204},
100 {0x0F00704c,0x00000000},
101 {0x0F007050,0x0000001c},
102 {0x0F007054,0x00000000},
103 {0x0F007058,0x00000000},
104 {0x0F00705c,0x00000000},
105 {0x0F007060,0x000A15D6},
106 {0x0F007064,0x0000000A},
107 {0x0F007068,0x00000000},
108 {0x0F00706c,0x00000001},
109 {0x0F007070,0x00004000},
110 {0x0F007074,0x00000000},
111 {0x0F007078,0x00000000},
112 {0x0F00707C,0x00000000},
113 {0x0F007080,0x00000000},
114 {0x0F007084,0x00000000},
115 {0x0F007094,0x00000104},
116 //# Enable start bit within memory controller
117 {0x0F007018,0x01010000}
118 };
119//100Mhz
120#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 //index for 0x0F007000
121static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
122 {0x0F000800,0x00007008},
123 {0x0f000810,0x00000F95},
124 {0x0f000820,0x07F13E3F},
125 {0x0f000860,0x00000000},
126 {0x0f000880,0x000003DD},
127 // Changed source for X-bar and MIPS clock to APLL
128 //0x0f000840,0x0FFF1800,
129 {0x0f000840,0x0FFF1B00},
130 {0x0f000870,0x00000002},
131 {0x0F00a044,0x1fffffff},
132 {0x0F00a040,0x1f000000},
133 {0x0F00a084,0x1Cffffff},
134 {0x0F00a080,0x1C000000},
135 {0x0F00a04C,0x0000000C},
136 //# Enable 2 ports within X-bar
137 {0x0F00A000,0x00000016},
138 //Memcontroller Default values
139 {0x0F007000,0x00010001},
140 {0x0F007004,0x01010100},
141 {0x0F007008,0x01000001},
142 {0x0F00700c,0x00000000},
143 {0x0F007010,0x01000000},
144 {0x0F007014,0x01000100},
145 {0x0F007018,0x01000000},
146 {0x0F00701c,0x01020001}, // POP - 0x00020000 Normal 0x01020000
147 {0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
148 {0x0F007024,0x00000007},
149 {0x0F007028,0x01020201},
150 {0x0F00702c,0x0204040A},
151 {0x0F007030,0x06000000},
152 {0x0F007034,0x00000004},
153 {0x0F007038,0x20080200},
154 {0x0F00703C,0x02030320},
155 {0x0F007040,0x6E7F1200},
156 {0x0F007044,0x01190A00},
157 {0x0F007048,0x06120305},//0x02690204 // 0x06120305
158 {0x0F00704c,0x00000000},
159 {0x0F007050,0x0000001C},
160 {0x0F007054,0x00000000},
161 {0x0F007058,0x00000000},
162 {0x0F00705c,0x00000000},
163 {0x0F007060,0x00082ED6},
164 {0x0F007064,0x0000000A},
165 {0x0F007068,0x00000000},
166 {0x0F00706c,0x00000001},
167 {0x0F007070,0x00005000},
168 {0x0F007074,0x00000000},
169 {0x0F007078,0x00000000},
170 {0x0F00707C,0x00000000},
171 {0x0F007080,0x00000000},
172 {0x0F007084,0x00000000},
173 //# Enable BW improvement within memory controller
174 {0x0F007094,0x00000104},
175 //# Enable start bit within memory controller
176 {0x0F007018,0x01010000}
177 };
178
179//Net T3B DDR Settings
180//DDR INIT-133Mhz
181static DDR_SET_NODE asDPLL_266MHZ[] = {
182 {0x0F000800,0x00007212},
183 {0x0f000820,0x07F13FFF},
184 {0x0f000810,0x00000F95},
185 {0x0f000860,0x00000000},
186 {0x0f000880,0x000003DD},
187 // Changed source for X-bar and MIPS clock to APLL
188 {0x0f000840,0x0FFF1B00},
189 {0x0f000870,0x00000002}
190 };
191#if 0
192static DDR_SET_NODE asDPLL_800MHZ[] = {
193 {0x0f000810,0x00000F95},
194 {0x0f000810,0x00000F95},
195 {0x0f000810,0x00000F95},
196 {0x0f000820,0x03F1365B},
197 {0x0f000840,0x0FFF0000},
198 {0x0f000880,0x000003DD},
199 {0x0f000860,0x00000000}
200 };
201#endif
202
203#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 //index for 0x0F007000
204static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
205 {0x0f000810,0x00000F95},
206 {0x0f000810,0x00000F95},
207 {0x0f000810,0x00000F95},
208 {0x0f000820,0x07F13652},
209 {0x0f000840,0x0FFF0800},
210 // Changed source for X-bar and MIPS clock to APLL
211 {0x0f000880,0x000003DD},
212 {0x0f000860,0x00000000},
213 // Changed source for X-bar and MIPS clock to APLL
214 {0x0F00a044,0x1fffffff},
215 {0x0F00a040,0x1f000000},
216 {0x0F00a084,0x1Cffffff},
217 {0x0F00a080,0x1C000000},
218 //# Enable 2 ports within X-bar
219 {0x0F00A000,0x00000016},
220 //Memcontroller Default values
221 {0x0F007000,0x00010001},
222 {0x0F007004,0x01010100},
223 {0x0F007008,0x01000001},
224 {0x0F00700c,0x00000000},
225 {0x0F007010,0x01000000},
226 {0x0F007014,0x01000100},
227 {0x0F007018,0x01000000},
228 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
229 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
230 {0x0F007024,0x02000007},
231 {0x0F007028,0x02020202},
232 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
233 {0x0F007030,0x05000000},
234 {0x0F007034,0x00000003},
235 {0x0F007038,0x130a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
236 {0x0F00703C,0x02101012},//ROB - 0x02101010,//0x02101018},
237 {0x0F007040,0x457D1200},//ROB - 0x45751200,//0x450f1200},
238 {0x0F007044,0x11130d00},//ROB - 0x110a0d00//0x111f0d00
239 {0x0F007048,0x040D0306},
240 {0x0F00704c,0x00000000},
241 {0x0F007050,0x0000001c},
242 {0x0F007054,0x00000000},
243 {0x0F007058,0x00000000},
244 {0x0F00705c,0x00000000},
245 {0x0F007060,0x0010246c},
246 {0x0F007064,0x00000012},
247 {0x0F007068,0x00000000},
248 {0x0F00706c,0x00000001},
249 {0x0F007070,0x00007000},
250 {0x0F007074,0x00000000},
251 {0x0F007078,0x00000000},
252 {0x0F00707C,0x00000000},
253 {0x0F007080,0x00000000},
254 {0x0F007084,0x00000000},
255 //# Enable BW improvement within memory controller
256 {0x0F007094,0x00000104},
257 //# Enable start bit within memory controller
258 {0x0F007018,0x01010000},
259 };
260
261#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
262static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting
263 {0x0f000810,0x00000F95},
264 {0x0f000820,0x07F13FFF},
265 {0x0f000840,0x0FFF1F00},
266 {0x0f000880,0x000003DD},
267 {0x0f000860,0x00000000},
268
269 {0x0F00a044,0x1fffffff},
270 {0x0F00a040,0x1f000000},
271 {0x0F00a084,0x1Cffffff},
272 {0x0F00a080,0x1C000000},
273 {0x0F00a000,0x00000016},
274 //Memcontroller Default values
275 {0x0F007000,0x00010001},
276 {0x0F007004,0x01000000},
277 {0x0F007008,0x01000001},
278 {0x0F00700c,0x00000000},
279 {0x0F007010,0x01000000},
280 {0x0F007014,0x01000100},
281 {0x0F007018,0x01000000},
282 {0x0F00701c,0x01020000},
283 {0x0F007020,0x04020107},
284 {0x0F007024,0x00000007},
285 {0x0F007028,0x02020201},
286 {0x0F00702c,0x0204040a},
287 {0x0F007030,0x04000000},
288 {0x0F007034,0x02000002},
289 {0x0F007038,0x1F060202},
290 {0x0F00703C,0x1C22221F},
291 {0x0F007040,0x8A006600},
292 {0x0F007044,0x221a0800},
293 {0x0F007048,0x02690204},
294 {0x0F00704c,0x00000000},
295 {0x0F007050,0x0100001c},
296 {0x0F007054,0x00000000},
297 {0x0F007058,0x00000000},
298 {0x0F00705c,0x00000000},
299 {0x0F007060,0x000A15D6},
300 {0x0F007064,0x0000000A},
301 {0x0F007068,0x00000000},
302 {0x0F00706c,0x00000001},
303 {0x0F007070,0x00004000},
304 {0x0F007074,0x00000000},
305 {0x0F007078,0x00000000},
306 {0x0F00707C,0x00000000},
307 {0x0F007080,0x00000000},
308 {0x0F007084,0x00000000},
309 {0x0F007094,0x00000104},
310 //# Enable start bit within memory controller
311 {0x0F007018,0x01010000}
312 };
313
314//100Mhz
315#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 //index for 0x0F007000
316static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
317 {0x0f000810,0x00000F95},
318 {0x0f000820,0x07F1369B},
319 {0x0f000840,0x0FFF0800},
320 {0x0f000880,0x000003DD},
321 {0x0f000860,0x00000000},
322 {0x0F00a044,0x1fffffff},
323 {0x0F00a040,0x1f000000},
324 {0x0F00a084,0x1Cffffff},
325 {0x0F00a080,0x1C000000},
326 //# Enable 2 ports within X-bar
327 {0x0F00A000,0x00000016},
328 //Memcontroller Default values
329 {0x0F007000,0x00010001},
330 {0x0F007004,0x01010100},
331 {0x0F007008,0x01000001},
332 {0x0F00700c,0x00000000},
333 {0x0F007010,0x01000000},
334 {0x0F007014,0x01000100},
335 {0x0F007018,0x01000000},
336 {0x0F00701c,0x01020000}, // POP - 0x00020000 Normal 0x01020000
337 {0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
338 {0x0F007024,0x00000007},
339 {0x0F007028,0x01020201},
340 {0x0F00702c,0x0204040A},
341 {0x0F007030,0x06000000},
342 {0x0F007034,0x02000004},
343 {0x0F007038,0x20080200},
344 {0x0F00703C,0x02030320},
345 {0x0F007040,0x6E7F1200},
346 {0x0F007044,0x01190A00},
347 {0x0F007048,0x06120305},//0x02690204 // 0x06120305
348 {0x0F00704c,0x00000000},
349 {0x0F007050,0x0100001C},
350 {0x0F007054,0x00000000},
351 {0x0F007058,0x00000000},
352 {0x0F00705c,0x00000000},
353 {0x0F007060,0x00082ED6},
354 {0x0F007064,0x0000000A},
355 {0x0F007068,0x00000000},
356 {0x0F00706c,0x00000001},
357 {0x0F007070,0x00005000},
358 {0x0F007074,0x00000000},
359 {0x0F007078,0x00000000},
360 {0x0F00707C,0x00000000},
361 {0x0F007080,0x00000000},
362 {0x0F007084,0x00000000},
363 //# Enable BW improvement within memory controller
364 {0x0F007094,0x00000104},
365 //# Enable start bit within memory controller
366 {0x0F007018,0x01010000}
367 };
368
369
370#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 //index for 0x0F007000
371static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
372 {0x0f000820,0x03F1365B},
373 {0x0f000810,0x00002F95},
374 {0x0f000880,0x000003DD},
375 // Changed source for X-bar and MIPS clock to APLL
376 {0x0f000840,0x0FFF0000},
377 {0x0f000860,0x00000000},
378 {0x0F00a044,0x1fffffff},
379 {0x0F00a040,0x1f000000},
380 {0x0F00a084,0x1Cffffff},
381 {0x0F00a080,0x1C000000},
382 {0x0F00A000,0x00000016},
383 //Memcontroller Default values
384 {0x0F007000,0x00010001},
385 {0x0F007004,0x01010100},
386 {0x0F007008,0x01000001},
387 {0x0F00700c,0x00000000},
388 {0x0F007010,0x01000000},
389 {0x0F007014,0x01000100},
390 {0x0F007018,0x01000000},
391 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
392 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
393 {0x0F007024,0x02000007},
394 {0x0F007028,0x02020200},
395 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
396 {0x0F007030,0x05000000},
397 {0x0F007034,0x00000003},
398 {0x0F007038,0x200a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
399 {0x0F00703C,0x02101020},//ROB - 0x02101010,//0x02101018,
400 {0x0F007040,0x45711200},//ROB - 0x45751200,//0x450f1200,
401 {0x0F007044,0x110D0D00},//ROB - 0x110a0d00//0x111f0d00
402 {0x0F007048,0x04080306},
403 {0x0F00704c,0x00000000},
404 {0x0F007050,0x0100001c},
405 {0x0F007054,0x00000000},
406 {0x0F007058,0x00000000},
407 {0x0F00705c,0x00000000},
408 {0x0F007060,0x0010245F},
409 {0x0F007064,0x00000010},
410 {0x0F007068,0x00000000},
411 {0x0F00706c,0x00000001},
412 {0x0F007070,0x00007000},
413 {0x0F007074,0x00000000},
414 {0x0F007078,0x00000000},
415 {0x0F00707C,0x00000000},
416 {0x0F007080,0x00000000},
417 {0x0F007084,0x00000000},
418 {0x0F007088,0x01000001},
419 {0x0F00708c,0x00000101},
420 {0x0F007090,0x00000000},
421 //# Enable BW improvement within memory controller
422 {0x0F007094,0x00040000},
423 {0x0F007098,0x00000000},
424 {0x0F0070c8,0x00000104},
425 //# Enable 2 ports within X-bar
426 //# Enable start bit within memory controller
427 {0x0F007018,0x01010000}
428};
429
430#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 //index for 0x0F007000
431static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
432 {0x0f000810,0x00002F95},
433 {0x0f000820,0x03F1369B},
434 {0x0f000840,0x0fff0000},
435 {0x0f000860,0x00000000},
436 {0x0f000880,0x000003DD},
437 // Changed source for X-bar and MIPS clock to APLL
438 {0x0f000840,0x0FFF0000},
439 {0x0F00a044,0x1fffffff},
440 {0x0F00a040,0x1f000000},
441 {0x0F00a084,0x1Cffffff},
442 {0x0F00a080,0x1C000000},
443 //Memcontroller Default values
444 {0x0F007000,0x00010001},
445 {0x0F007004,0x01010100},
446 {0x0F007008,0x01000001},
447 {0x0F00700c,0x00000000},
448 {0x0F007010,0x01000000},
449 {0x0F007014,0x01000100},
450 {0x0F007018,0x01000000},
451 {0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
452 {0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
453 {0x0F007024,0x00000007},
454 {0x0F007028,0x01020200},
455 {0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
456 {0x0F007030,0x06000000},
457 {0x0F007034,0x00000004},
458 {0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
459 {0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
460 {0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
461 {0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
462 {0x0F007048,0x03000305},
463 {0x0F00704c,0x00000000},
464 {0x0F007050,0x0100001c},
465 {0x0F007054,0x00000000},
466 {0x0F007058,0x00000000},
467 {0x0F00705c,0x00000000},
468 {0x0F007060,0x00082ED6},
469 {0x0F007064,0x0000000A},
470 {0x0F007068,0x00000000},
471 {0x0F00706c,0x00000001},
472 {0x0F007070,0x00005000},
473 {0x0F007074,0x00000000},
474 {0x0F007078,0x00000000},
475 {0x0F00707C,0x00000000},
476 {0x0F007080,0x00000000},
477 {0x0F007084,0x00000000},
478 {0x0F007088,0x01000001},
479 {0x0F00708c,0x00000101},
480 {0x0F007090,0x00000000},
481 {0x0F007094,0x00010000},
482 {0x0F007098,0x00000000},
483 {0x0F0070C8,0x00000104},
484 //# Enable 2 ports within X-bar
485 {0x0F00A000,0x00000016},
486 //# Enable start bit within memory controller
487 {0x0F007018,0x01010000}
488};
489
490#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
491static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
492 {0x0f000820,0x07F13FFF},
493 {0x0f000810,0x00002F95},
494 {0x0f000860,0x00000000},
495 {0x0f000880,0x000003DD},
496 {0x0f000840,0x0FFF1F00},
497 {0x0F00a044,0x1fffffff},
498 {0x0F00a040,0x1f000000},
499 {0x0F00a084,0x1Cffffff},
500 {0x0F00a080,0x1C000000},
501 {0x0F00A000,0x00000016},
502 {0x0f007000,0x00010001},
503 {0x0f007004,0x01000000},
504 {0x0f007008,0x01000001},
505 {0x0f00700c,0x00000000},
506 {0x0f007010,0x01000000},
507 {0x0f007014,0x01000100},
508 {0x0f007018,0x01000000},
509 {0x0f00701c,0x01020000},
510 {0x0f007020,0x04020107},
511 {0x0f007024,0x00000007},
512 {0x0f007028,0x02020200},
513 {0x0f00702c,0x0204040a},
514 {0x0f007030,0x04000000},
515 {0x0f007034,0x00000002},
516 {0x0f007038,0x1d060200},
517 {0x0f00703c,0x1c22221d},
518 {0x0f007040,0x8A116600},
519 {0x0f007044,0x222d0800},
520 {0x0f007048,0x02690204},
521 {0x0f00704c,0x00000000},
522 {0x0f007050,0x0100001c},
523 {0x0f007054,0x00000000},
524 {0x0f007058,0x00000000},
525 {0x0f00705c,0x00000000},
526 {0x0f007060,0x000A15D6},
527 {0x0f007064,0x0000000A},
528 {0x0f007068,0x00000000},
529 {0x0f00706c,0x00000001},
530 {0x0f007070,0x00004000},
531 {0x0f007074,0x00000000},
532 {0x0f007078,0x00000000},
533 {0x0f00707c,0x00000000},
534 {0x0f007080,0x00000000},
535 {0x0f007084,0x00000000},
536 {0x0f007088,0x01000001},
537 {0x0f00708c,0x00000101},
538 {0x0f007090,0x00000000},
539 {0x0f007094,0x00010000},
540 {0x0f007098,0x00000000},
541 {0x0F0070C8,0x00000104},
542 {0x0F007018,0x01010000}
543};
544
545
546
547
548///T3 LP-B (UMA-B)
549
550#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 //index for 0x0F007000
551static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
552
553 {0x0f000820,0x03F137DB},
554 {0x0f000810,0x01842795},
555 {0x0f000860,0x00000000},
556 {0x0f000880,0x000003DD},
557 {0x0f000840,0x0FFF0400},
558 {0x0F00a044,0x1fffffff},
559 {0x0F00a040,0x1f000000},
560 {0x0f003050,0x00000021},//this is flash/eeprom clock divisor which set the flash clock to 20 MHz
561 {0x0F00a084,0x1Cffffff},//Now dump from her in internal memory
562 {0x0F00a080,0x1C000000},
563 {0x0F00A000,0x00000016},
564 {0x0f007000,0x00010001},
565 {0x0f007004,0x01000001},
566 {0x0f007008,0x01000101},
567 {0x0f00700c,0x00000000},
568 {0x0f007010,0x01000100},
569 {0x0f007014,0x01000100},
570 {0x0f007018,0x01000000},
571 {0x0f00701c,0x01020000},
572 {0x0f007020,0x04030107},
573 {0x0f007024,0x02000007},
574 {0x0f007028,0x02020200},
575 {0x0f00702c,0x0206060a},
576 {0x0f007030,0x050d0d00},
577 {0x0f007034,0x00000003},
578 {0x0f007038,0x170a0200},
579 {0x0f00703c,0x02101012},
580 {0x0f007040,0x45161200},
581 {0x0f007044,0x11250c00},
582 {0x0f007048,0x04da0307},
583 {0x0f00704c,0x00000000},
584 {0x0f007050,0x0000001c},
585 {0x0f007054,0x00000000},
586 {0x0f007058,0x00000000},
587 {0x0f00705c,0x00000000},
588 {0x0f007060,0x00142bb6},
589 {0x0f007064,0x20430014},
590 {0x0f007068,0x00000000},
591 {0x0f00706c,0x00000001},
592 {0x0f007070,0x00009000},
593 {0x0f007074,0x00000000},
594 {0x0f007078,0x00000000},
595 {0x0f00707c,0x00000000},
596 {0x0f007080,0x00000000},
597 {0x0f007084,0x00000000},
598 {0x0f007088,0x01000001},
599 {0x0f00708c,0x00000101},
600 {0x0f007090,0x00000000},
601 {0x0f007094,0x00040000},
602 {0x0f007098,0x00000000},
603 {0x0F0070C8,0x00000104},
604 {0x0F007018,0x01010000}
605};
606
607
608#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 //index for 0x0F007000
609static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
610 {0x0f000820,0x03F1365B},
611 {0x0f000810,0x00002F95},
612 {0x0f000880,0x000003DD},
613 // Changed source for X-bar and MIPS clock to APLL
614 {0x0f000840,0x0FFF0000},
615 {0x0f000860,0x00000000},
616 {0x0F00a044,0x1fffffff},
617 {0x0F00a040,0x1f000000},
618 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
619 {0x0F00a084,0x1Cffffff},//dump from here in internal memory
620 {0x0F00a080,0x1C000000},
621 {0x0F00A000,0x00000016},
622 //Memcontroller Default values
623 {0x0F007000,0x00010001},
624 {0x0F007004,0x01010100},
625 {0x0F007008,0x01000001},
626 {0x0F00700c,0x00000000},
627 {0x0F007010,0x01000000},
628 {0x0F007014,0x01000100},
629 {0x0F007018,0x01000000},
630 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
631 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
632 {0x0F007024,0x02000007},
633 {0x0F007028,0x02020200},
634 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
635 {0x0F007030,0x05000000},
636 {0x0F007034,0x00000003},
637 {0x0F007038,0x190a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
638 {0x0F00703C,0x02101017},//ROB - 0x02101010,//0x02101018,
639 {0x0F007040,0x45171200},//ROB - 0x45751200,//0x450f1200,
640 {0x0F007044,0x11290D00},//ROB - 0x110a0d00//0x111f0d00
641 {0x0F007048,0x04080306},
642 {0x0F00704c,0x00000000},
643 {0x0F007050,0x0100001c},
644 {0x0F007054,0x00000000},
645 {0x0F007058,0x00000000},
646 {0x0F00705c,0x00000000},
647 {0x0F007060,0x0010245F},
648 {0x0F007064,0x00000010},
649 {0x0F007068,0x00000000},
650 {0x0F00706c,0x00000001},
651 {0x0F007070,0x00007000},
652 {0x0F007074,0x00000000},
653 {0x0F007078,0x00000000},
654 {0x0F00707C,0x00000000},
655 {0x0F007080,0x00000000},
656 {0x0F007084,0x00000000},
657 {0x0F007088,0x01000001},
658 {0x0F00708c,0x00000101},
659 {0x0F007090,0x00000000},
660 //# Enable BW improvement within memory controller
661 {0x0F007094,0x00040000},
662 {0x0F007098,0x00000000},
663 {0x0F0070c8,0x00000104},
664 //# Enable 2 ports within X-bar
665 //# Enable start bit within memory controller
666 {0x0F007018,0x01010000}
667};
668
669#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 //index for 0x0F007000
670static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
671 {0x0f000810,0x00002F95},
672 {0x0f000820,0x03F1369B},
673 {0x0f000840,0x0fff0000},
674 {0x0f000860,0x00000000},
675 {0x0f000880,0x000003DD},
676 // Changed source for X-bar and MIPS clock to APLL
677 {0x0f000840,0x0FFF0000},
678 {0x0F00a044,0x1fffffff},
679 {0x0F00a040,0x1f000000},
680 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
681 {0x0F00a084,0x1Cffffff}, //dump from here in internal memory
682 {0x0F00a080,0x1C000000},
683 //Memcontroller Default values
684 {0x0F007000,0x00010001},
685 {0x0F007004,0x01010100},
686 {0x0F007008,0x01000001},
687 {0x0F00700c,0x00000000},
688 {0x0F007010,0x01000000},
689 {0x0F007014,0x01000100},
690 {0x0F007018,0x01000000},
691 {0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
692 {0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
693 {0x0F007024,0x00000007},
694 {0x0F007028,0x01020200},
695 {0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
696 {0x0F007030,0x06000000},
697 {0x0F007034,0x00000004},
698 {0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
699 {0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
700 {0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
701 {0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
702 {0x0F007048,0x03000305},
703 {0x0F00704c,0x00000000},
704 {0x0F007050,0x0100001c},
705 {0x0F007054,0x00000000},
706 {0x0F007058,0x00000000},
707 {0x0F00705c,0x00000000},
708 {0x0F007060,0x00082ED6},
709 {0x0F007064,0x0000000A},
710 {0x0F007068,0x00000000},
711 {0x0F00706c,0x00000001},
712 {0x0F007070,0x00005000},
713 {0x0F007074,0x00000000},
714 {0x0F007078,0x00000000},
715 {0x0F00707C,0x00000000},
716 {0x0F007080,0x00000000},
717 {0x0F007084,0x00000000},
718 {0x0F007088,0x01000001},
719 {0x0F00708c,0x00000101},
720 {0x0F007090,0x00000000},
721 {0x0F007094,0x00010000},
722 {0x0F007098,0x00000000},
723 {0x0F0070C8,0x00000104},
724 //# Enable 2 ports within X-bar
725 {0x0F00A000,0x00000016},
726 //# Enable start bit within memory controller
727 {0x0F007018,0x01010000}
728};
729
730#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 //index for 0x0F007000
731static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
732 {0x0f000820,0x07F13FFF},
733 {0x0f000810,0x00002F95},
734 {0x0f000860,0x00000000},
735 {0x0f000880,0x000003DD},
736 {0x0f000840,0x0FFF1F00},
737 {0x0F00a044,0x1fffffff},
738 {0x0F00a040,0x1f000000},
739 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
740 {0x0F00a084,0x1Cffffff},// dump from here in internal memory
741 {0x0F00a080,0x1C000000},
742 {0x0F00A000,0x00000016},
743 {0x0f007000,0x00010001},
744 {0x0f007004,0x01000000},
745 {0x0f007008,0x01000001},
746 {0x0f00700c,0x00000000},
747 {0x0f007010,0x01000000},
748 {0x0f007014,0x01000100},
749 {0x0f007018,0x01000000},
750 {0x0f00701c,0x01020000},
751 {0x0f007020,0x04020107},
752 {0x0f007024,0x00000007},
753 {0x0f007028,0x02020200},
754 {0x0f00702c,0x0204040a},
755 {0x0f007030,0x04000000},
756 {0x0f007034,0x00000002},
757 {0x0f007038,0x1d060200},
758 {0x0f00703c,0x1c22221d},
759 {0x0f007040,0x8A116600},
760 {0x0f007044,0x222d0800},
761 {0x0f007048,0x02690204},
762 {0x0f00704c,0x00000000},
763 {0x0f007050,0x0100001c},
764 {0x0f007054,0x00000000},
765 {0x0f007058,0x00000000},
766 {0x0f00705c,0x00000000},
767 {0x0f007060,0x000A15D6},
768 {0x0f007064,0x0000000A},
769 {0x0f007068,0x00000000},
770 {0x0f00706c,0x00000001},
771 {0x0f007070,0x00004000},
772 {0x0f007074,0x00000000},
773 {0x0f007078,0x00000000},
774 {0x0f00707c,0x00000000},
775 {0x0f007080,0x00000000},
776 {0x0f007084,0x00000000},
777 {0x0f007088,0x01000001},
778 {0x0f00708c,0x00000101},
779 {0x0f007090,0x00000000},
780 {0x0f007094,0x00010000},
781 {0x0f007098,0x00000000},
782 {0x0F0070C8,0x00000104},
783 {0x0F007018,0x01010000}
784};
785
786
787int ddr_init(MINI_ADAPTER *Adapter)
788{
789 PDDR_SETTING psDDRSetting=NULL;
790 ULONG RegCount=0;
791 ULONG value = 0;
792 UINT uiResetValue = 0;
793 UINT uiClockSetting = 0;
794 int retval = STATUS_SUCCESS;
795
796 switch (Adapter->chip_id)
797 {
798 case 0xbece3200:
799 switch (Adapter->DDRSetting)
800 {
801 case DDR_80_MHZ:
802 psDDRSetting=asT3LP_DDRSetting80MHz;
803 RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
804 sizeof(DDR_SETTING));
805 break;
806 case DDR_100_MHZ:
807 psDDRSetting=asT3LP_DDRSetting100MHz;
808 RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
809 sizeof(DDR_SETTING));
810 break;
811 case DDR_133_MHZ:
812 psDDRSetting=asT3LP_DDRSetting133MHz;
813 RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
814 sizeof(DDR_SETTING));
815 if(Adapter->bMipsConfig == MIPS_200_MHZ)
816 {
817 uiClockSetting = 0x03F13652;
818 }
819 else
820 {
821 uiClockSetting = 0x03F1365B;
822 }
823 break;
824 default:
825 return -EINVAL;
826 }
827
828 break;
829 case T3LPB:
830 case BCS220_2:
831 case BCS220_2BC:
832 case BCS250_BC:
833 case BCS220_3 :
834 /* Set bit 2 and bit 6 to 1 for BBIC 2mA drive
835 * (please check current value and additionally set these bits)
836 */
837 if( (Adapter->chip_id != BCS220_2) &&
838 (Adapter->chip_id != BCS220_2BC) &&
839 (Adapter->chip_id != BCS220_3) )
840 {
841 retval= rdmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
842 if(retval < 0) {
843 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
844 return retval;
845 }
846 uiResetValue |= 0x44;
847 retval = wrmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
848 if(retval < 0) {
849 BCM_DEBUG_PRINT(Adapter,CMHOST, WRM, DBG_LVL_ALL, "%s:%d WRM failed\n", __FUNCTION__, __LINE__);
850 return retval;
851 }
852 }
853 switch(Adapter->DDRSetting)
854 {
855
856
857
858 case DDR_80_MHZ:
859 psDDRSetting = asT3LPB_DDRSetting80MHz;
860 RegCount=(sizeof(asT3B_DDRSetting80MHz)/
861 sizeof(DDR_SETTING));
862 break;
863 case DDR_100_MHZ:
864 psDDRSetting=asT3LPB_DDRSetting100MHz;
865 RegCount=(sizeof(asT3B_DDRSetting100MHz)/
866 sizeof(DDR_SETTING));
867 break;
868 case DDR_133_MHZ:
869 psDDRSetting = asT3LPB_DDRSetting133MHz;
870 RegCount=(sizeof(asT3B_DDRSetting133MHz)/
871 sizeof(DDR_SETTING));
872
873 if(Adapter->bMipsConfig == MIPS_200_MHZ)
874 {
875 uiClockSetting = 0x03F13652;
876 }
877 else
878 {
879 uiClockSetting = 0x03F1365B;
880 }
881 break;
882
883 case DDR_160_MHZ:
884 psDDRSetting = asT3LPB_DDRSetting160MHz;
885 RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING);
886
887 if(Adapter->bMipsConfig == MIPS_200_MHZ)
888 {
889 uiClockSetting = 0x03F137D2;
890 }
891 else
892 {
893 uiClockSetting = 0x03F137DB;
894 }
895 }
896 break;
897
898 case 0xbece0110:
899 case 0xbece0120:
900 case 0xbece0121:
901 case 0xbece0130:
902 case 0xbece0300:
903 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "DDR Setting: %x\n", Adapter->DDRSetting);
904 switch (Adapter->DDRSetting)
905 {
906 case DDR_80_MHZ:
907 psDDRSetting = asT3_DDRSetting80MHz;
908 RegCount = (sizeof(asT3_DDRSetting80MHz)/
909 sizeof(DDR_SETTING));
910 break;
911 case DDR_100_MHZ:
912 psDDRSetting = asT3_DDRSetting100MHz;
913 RegCount = (sizeof(asT3_DDRSetting100MHz)/
914 sizeof(DDR_SETTING));
915 break;
916 case DDR_133_MHZ:
917 psDDRSetting = asT3_DDRSetting133MHz;
918 RegCount = (sizeof(asT3_DDRSetting133MHz)/
919 sizeof(DDR_SETTING));
920 break;
921 default:
922 return -EINVAL;
923 }
924 case 0xbece0310:
925 {
926 switch (Adapter->DDRSetting)
927 {
928 case DDR_80_MHZ:
929 psDDRSetting = asT3B_DDRSetting80MHz;
930 RegCount=(sizeof(asT3B_DDRSetting80MHz)/
931 sizeof(DDR_SETTING));
932 break;
933 case DDR_100_MHZ:
934 psDDRSetting=asT3B_DDRSetting100MHz;
935 RegCount=(sizeof(asT3B_DDRSetting100MHz)/
936 sizeof(DDR_SETTING));
937 break;
938 case DDR_133_MHZ:
939
940 if(Adapter->bDPLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
941 {
942 memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
943 sizeof(asDPLL_266MHZ));
944 psDDRSetting = asT3B_DDRSetting133MHz;
945 RegCount=(sizeof(asT3B_DDRSetting133MHz)/
946 sizeof(DDR_SETTING));
947 }
948 else
949 {
950 psDDRSetting = asT3B_DDRSetting133MHz;
951 RegCount=(sizeof(asT3B_DDRSetting133MHz)/
952 sizeof(DDR_SETTING));
953 if(Adapter->bMipsConfig == MIPS_200_MHZ)
954 {
955 uiClockSetting = 0x07F13652;
956 }
957 else
958 {
959 uiClockSetting = 0x07F1365B;
960 }
961 }
962 break;
963 default:
964 return -EINVAL;
965 }
966 break;
967
968 }
969 default:
970 return -EINVAL;
971 }
972
973 value=0;
974 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "Register Count is =%lu\n", RegCount);
975 while(RegCount && !retval)
976 {
977 if(uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
978 {
979 value = uiClockSetting;
980 }
981 else
982 {
983 value = psDDRSetting->ulRegValue;
984 }
985 retval = wrmalt(Adapter, psDDRSetting->ulRegAddress, (PUINT)&value, sizeof(value));
986 if(STATUS_SUCCESS != retval) {
987 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
988 break;
989 }
990
991 RegCount--;
992 psDDRSetting++;
993 }
994
995 if(Adapter->chip_id >= 0xbece3300 )
996 {
997
998 mdelay(3);
999 if( (Adapter->chip_id != BCS220_2)&&
1000 (Adapter->chip_id != BCS220_2BC)&&
1001 (Adapter->chip_id != BCS220_3))
1002 {
1003 /* drive MDDR to half in case of UMA-B: */
1004 uiResetValue = 0x01010001;
1005 retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
1006 if(retval < 0) {
1007 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1008 return retval;
1009 }
1010 uiResetValue = 0x00040020;
1011 retval = wrmalt(Adapter, (UINT)0x0F007094, &uiResetValue, sizeof(uiResetValue));
1012 if(retval < 0) {
1013 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1014 return retval;
1015 }
1016 uiResetValue = 0x01020101;
1017 retval = wrmalt(Adapter, (UINT)0x0F00701c, &uiResetValue, sizeof(uiResetValue));
1018 if(retval < 0) {
1019 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1020 return retval;
1021 }
1022 uiResetValue = 0x01010000;
1023 retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
1024 if(retval < 0) {
1025 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1026 return retval;
1027 }
1028 }
1029 mdelay(3);
1030
1031 /* DC/DC standby change...
1032 * This is to be done only for Hybrid PMU mode.
1033 * with the current h/w there is no way to detect this.
1034 * and since we dont have internal PMU lets do it under UMA-B chip id.
1035 * we will change this when we will have internal PMU.
1036 */
1037 if(Adapter->PmuMode == HYBRID_MODE_7C)
1038 {
1039 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1040 if(retval < 0) {
1041 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1042 return retval;
1043 }
1044 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1045 if(retval < 0) {
1046 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1047 return retval;
1048 }
1049 uiResetValue = 0x1322a8;
1050 retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1051 if(retval < 0) {
1052 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1053 return retval;
1054 }
1055 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1056 if(retval < 0) {
1057 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1058 return retval;
1059 }
1060 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1061 if(retval < 0) {
1062 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1063 return retval;
1064 }
1065 uiResetValue = 0x132296;
1066 retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1067 if(retval < 0) {
1068 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1069 return retval;
1070 }
1071 }
1072 else if(Adapter->PmuMode == HYBRID_MODE_6 )
1073 {
1074
1075 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1076 if(retval < 0) {
1077 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1078 return retval;
1079 }
1080 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1081 if(retval < 0) {
1082 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1083 return retval;
1084 }
1085 uiResetValue = 0x6003229a;
1086 retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1087 if(retval < 0) {
1088 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1089 return retval;
1090 }
1091 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1092 if(retval < 0) {
1093 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1094 return retval;
1095 }
1096 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1097 if(retval < 0) {
1098 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1099 return retval;
1100 }
1101 uiResetValue = 0x1322a8;
1102 retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1103 if(retval < 0) {
1104 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1105 return retval;
1106 }
1107 }
1108
1109 }
1110 Adapter->bDDRInitDone = TRUE;
1111 return retval;
1112}
1113
1114int download_ddr_settings(PMINI_ADAPTER Adapter)
1115{
1116 PDDR_SET_NODE psDDRSetting=NULL;
1117 ULONG RegCount=0;
1118 unsigned long ul_ddr_setting_load_addr = DDR_DUMP_INTERNAL_DEVICE_MEMORY;
1119 UINT value = 0;
1120 int retval = STATUS_SUCCESS;
1121 BOOLEAN bOverrideSelfRefresh = FALSE;
1122
1123 switch (Adapter->chip_id)
1124 {
1125 case 0xbece3200:
1126 switch (Adapter->DDRSetting)
1127 {
1128 case DDR_80_MHZ:
1129 psDDRSetting = asT3LP_DDRSetting80MHz;
1130 RegCount = (sizeof(asT3LP_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1131 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1132 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1133 break;
1134 case DDR_100_MHZ:
1135 psDDRSetting = asT3LP_DDRSetting100MHz;
1136 RegCount = (sizeof(asT3LP_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1137 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1138 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1139 break;
1140 case DDR_133_MHZ:
1141 bOverrideSelfRefresh = TRUE;
1142 psDDRSetting = asT3LP_DDRSetting133MHz;
1143 RegCount = (sizeof(asT3LP_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1144 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1145 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1146 break;
1147 default:
1148 return -EINVAL;
1149 }
1150 break;
1151
1152 case T3LPB:
1153 case BCS220_2:
1154 case BCS220_2BC:
1155 case BCS250_BC:
1156 case BCS220_3 :
1157 switch (Adapter->DDRSetting)
1158 {
1159 case DDR_80_MHZ:
1160 psDDRSetting = asT3LPB_DDRSetting80MHz;
1161 RegCount=(sizeof(asT3LPB_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1162 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1163 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1164 break;
1165 case DDR_100_MHZ:
1166 psDDRSetting = asT3LPB_DDRSetting100MHz;
1167 RegCount = (sizeof(asT3LPB_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1168 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1169 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1170 break;
1171 case DDR_133_MHZ:
1172 bOverrideSelfRefresh = TRUE;
1173 psDDRSetting = asT3LPB_DDRSetting133MHz;
1174 RegCount = (sizeof(asT3LPB_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1175 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1176 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1177 break;
1178
1179 case DDR_160_MHZ:
1180 bOverrideSelfRefresh = TRUE;
1181 psDDRSetting = asT3LPB_DDRSetting160MHz;
1182 RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SET_NODE);
1183 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1184 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1185
1186 break;
1187 default:
1188 return -EINVAL;
1189 }
1190 break;
1191 case 0xbece0300:
1192 switch (Adapter->DDRSetting)
1193 {
1194 case DDR_80_MHZ:
1195 psDDRSetting = asT3_DDRSetting80MHz;
1196 RegCount = (sizeof(asT3_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1197 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1198 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1199 break;
1200 case DDR_100_MHZ:
1201 psDDRSetting = asT3_DDRSetting100MHz;
1202 RegCount = (sizeof(asT3_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1203 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1204 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1205 break;
1206 case DDR_133_MHZ:
1207 psDDRSetting = asT3_DDRSetting133MHz;
1208 RegCount = (sizeof(asT3_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1209 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1210 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1211 break;
1212 default:
1213 return -EINVAL;
1214 }
1215 break;
1216 case 0xbece0310:
1217 {
1218 switch (Adapter->DDRSetting)
1219 {
1220 case DDR_80_MHZ:
1221 psDDRSetting = asT3B_DDRSetting80MHz;
1222 RegCount = (sizeof(asT3B_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1223 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1224 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1225 break;
1226 case DDR_100_MHZ:
1227 psDDRSetting = asT3B_DDRSetting100MHz;
1228 RegCount = (sizeof(asT3B_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1229 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1230 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1231 break;
1232 case DDR_133_MHZ:
1233 bOverrideSelfRefresh = TRUE;
1234 psDDRSetting = asT3B_DDRSetting133MHz;
1235 RegCount = (sizeof(asT3B_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1236 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1237 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1238 break;
1239 }
1240 break;
1241 }
1242 default:
1243 return -EINVAL;
1244 }
1245 //total number of Register that has to be dumped
1246 value =RegCount ;
1247 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1248 if(retval)
1249 {
1250 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1251
1252 return retval;
1253 }
1254 ul_ddr_setting_load_addr+=sizeof(ULONG);
1255 /*signature */
1256 value =(0x1d1e0dd0);
1257 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1258 if(retval)
1259 {
1260 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1261 return retval;
1262 }
1263
1264 ul_ddr_setting_load_addr+=sizeof(ULONG);
1265 RegCount*=(sizeof(DDR_SETTING)/sizeof(ULONG));
1266
1267 while(RegCount && !retval)
1268 {
1269 value = psDDRSetting->ulRegAddress ;
1270 retval = wrmalt( Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1271 ul_ddr_setting_load_addr+=sizeof(ULONG);
1272 if(!retval)
1273 {
1274 if(bOverrideSelfRefresh && (psDDRSetting->ulRegAddress == 0x0F007018))
1275 {
1276 value = (psDDRSetting->ulRegValue |(1<<8));
1277 if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr,
1278 &value, sizeof(value))){
1279 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1280 break;
1281 }
1282 }
1283 else
1284 {
1285 value = psDDRSetting->ulRegValue;
1286
1287 if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr ,
1288 &value, sizeof(value))){
1289 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1290 break;
1291 }
1292 }
1293 }
1294 ul_ddr_setting_load_addr+=sizeof(ULONG);
1295 RegCount--;
1296 psDDRSetting++;
1297 }
1298 return retval;
1299}
1300
1301#endif
1302
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 05:33:02 -0400