diff options
Diffstat (limited to 'drivers/staging/ath6kl/include/common')
30 files changed, 8093 insertions, 0 deletions
diff --git a/drivers/staging/ath6kl/include/common/AR6002/AR6K_version.h b/drivers/staging/ath6kl/include/common/AR6002/AR6K_version.h new file mode 100644 index 00000000000..5407e05d9b0 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/AR6K_version.h | |||
@@ -0,0 +1,52 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="AR6K_version.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #define __VER_MAJOR_ 3 | ||
25 | #define __VER_MINOR_ 0 | ||
26 | #define __VER_PATCH_ 0 | ||
27 | |||
28 | /* The makear6ksdk script (used for release builds) modifies the following line. */ | ||
29 | #define __BUILD_NUMBER_ 233 | ||
30 | |||
31 | |||
32 | /* Format of the version number. */ | ||
33 | #define VER_MAJOR_BIT_OFFSET 28 | ||
34 | #define VER_MINOR_BIT_OFFSET 24 | ||
35 | #define VER_PATCH_BIT_OFFSET 16 | ||
36 | #define VER_BUILD_NUM_BIT_OFFSET 0 | ||
37 | |||
38 | |||
39 | /* | ||
40 | * The version has the following format: | ||
41 | * Bits 28-31: Major version | ||
42 | * Bits 24-27: Minor version | ||
43 | * Bits 16-23: Patch version | ||
44 | * Bits 0-15: Build number (automatically generated during build process ) | ||
45 | * E.g. Build 1.1.3.7 would be represented as 0x11030007. | ||
46 | * | ||
47 | * DO NOT split the following macro into multiple lines as this may confuse the build scripts. | ||
48 | */ | ||
49 | #define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) | ||
50 | |||
51 | /* ABI Version. Reflects the version of binary interface exposed by AR6K target firmware. Needs to be incremented by 1 for any change in the firmware that requires upgrade of the driver on the host side for the change to work correctly */ | ||
52 | #define AR6K_ABI_VERSION 1 | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/addrs.h b/drivers/staging/ath6kl/include/common/AR6002/addrs.h new file mode 100644 index 00000000000..bbf8d42828c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/addrs.h | |||
@@ -0,0 +1,90 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // | ||
19 | // Author(s): ="Atheros" | ||
20 | //------------------------------------------------------------------------------ | ||
21 | |||
22 | #ifndef __ADDRS_H__ | ||
23 | #define __ADDRS_H__ | ||
24 | |||
25 | /* | ||
26 | * Special AR6002 Addresses that may be needed by special | ||
27 | * applications (e.g. ART) on the Host as well as Target. | ||
28 | */ | ||
29 | |||
30 | #if defined(AR6002_REV2) | ||
31 | #define AR6K_RAM_START 0x00500000 | ||
32 | #define TARG_RAM_OFFSET(vaddr) ((u32)(vaddr) & 0xfffff) | ||
33 | #define TARG_RAM_SZ (184*1024) | ||
34 | #define TARG_ROM_SZ (80*1024) | ||
35 | #endif | ||
36 | #if defined(AR6002_REV4) || defined(AR6003) | ||
37 | #define AR6K_RAM_START 0x00540000 | ||
38 | #define TARG_RAM_OFFSET(vaddr) (((u32)(vaddr) & 0xfffff) - 0x40000) | ||
39 | #define TARG_RAM_SZ (256*1024) | ||
40 | #define TARG_ROM_SZ (256*1024) | ||
41 | #endif | ||
42 | |||
43 | #define AR6002_BOARD_DATA_SZ 768 | ||
44 | #define AR6002_BOARD_EXT_DATA_SZ 0 | ||
45 | #define AR6003_BOARD_DATA_SZ 1024 | ||
46 | #define AR6003_BOARD_EXT_DATA_SZ 768 | ||
47 | |||
48 | #define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset)) | ||
49 | #define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset) | ||
50 | |||
51 | #define AR6K_ROM_START 0x004e0000 | ||
52 | #define TARG_ROM_OFFSET(vaddr) (((u32)(vaddr) & 0x1fffff) - 0xe0000) | ||
53 | #define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) | ||
54 | #define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) | ||
55 | |||
56 | /* | ||
57 | * At this ROM address is a pointer to the start of the ROM DataSet Index. | ||
58 | * If there are no ROM DataSets, there's a 0 at this address. | ||
59 | */ | ||
60 | #define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8) | ||
61 | #define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4) | ||
62 | |||
63 | /* | ||
64 | * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to | ||
65 | * board data. | ||
66 | */ | ||
67 | |||
68 | /* Size of Board Data, in bytes */ | ||
69 | #if defined(AR6002_REV4) || defined(AR6003) | ||
70 | #define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ | ||
71 | #else | ||
72 | #define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ | ||
73 | #endif | ||
74 | |||
75 | |||
76 | /* | ||
77 | * Constants used by ASM code to access fields of host_interest_s, | ||
78 | * which is at a fixed location in RAM. | ||
79 | */ | ||
80 | #if defined(AR6002_REV4) || defined(AR6003) | ||
81 | #define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x60c) | ||
82 | #else | ||
83 | #define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c) | ||
84 | #endif | ||
85 | #define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR | ||
86 | |||
87 | #endif /* __ADDRS_H__ */ | ||
88 | |||
89 | |||
90 | |||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h new file mode 100644 index 00000000000..609eb9841f5 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_athr_wlan_map.h | |||
@@ -0,0 +1,40 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #ifndef _APB_ATHR_WLAN_MAP_H_ | ||
25 | #define _APB_ATHR_WLAN_MAP_H_ | ||
26 | |||
27 | #define WLAN_RTC_BASE_ADDRESS 0x00004000 | ||
28 | #define WLAN_VMC_BASE_ADDRESS 0x00008000 | ||
29 | #define WLAN_UART_BASE_ADDRESS 0x0000c000 | ||
30 | #define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000 | ||
31 | #define WLAN_UMBOX_BASE_ADDRESS 0x0000e000 | ||
32 | #define WLAN_SI_BASE_ADDRESS 0x00010000 | ||
33 | #define WLAN_GPIO_BASE_ADDRESS 0x00014000 | ||
34 | #define WLAN_MBOX_BASE_ADDRESS 0x00018000 | ||
35 | #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 | ||
36 | #define WLAN_MAC_BASE_ADDRESS 0x00020000 | ||
37 | #define WLAN_RDMA_BASE_ADDRESS 0x00030100 | ||
38 | #define EFUSE_BASE_ADDRESS 0x00031000 | ||
39 | |||
40 | #endif /* _APB_ATHR_WLAN_MAP_REG_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h new file mode 100644 index 00000000000..0068ca31b05 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h | |||
@@ -0,0 +1,40 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #include "apb_athr_wlan_map.h" | ||
25 | |||
26 | #ifndef BT_HEADERS | ||
27 | |||
28 | #define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS | ||
29 | #define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS | ||
30 | #define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS | ||
31 | #define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS | ||
32 | #define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS | ||
33 | #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS | ||
34 | #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS | ||
35 | #define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS | ||
36 | #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS | ||
37 | #define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS | ||
38 | #define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS | ||
39 | |||
40 | #endif | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h new file mode 100644 index 00000000000..109f24e10a6 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h | |||
@@ -0,0 +1,24 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #include "mbox_wlan_host_reg.h" | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h new file mode 100644 index 00000000000..72fa483450d --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h | |||
@@ -0,0 +1,552 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #include "mbox_wlan_reg.h" | ||
25 | |||
26 | #ifndef BT_HEADERS | ||
27 | |||
28 | #define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS | ||
29 | #define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET | ||
30 | #define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB | ||
31 | #define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB | ||
32 | #define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK | ||
33 | #define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x) | ||
34 | #define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x) | ||
35 | #define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS | ||
36 | #define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET | ||
37 | #define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB | ||
38 | #define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB | ||
39 | #define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK | ||
40 | #define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) | ||
41 | #define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) | ||
42 | #define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB | ||
43 | #define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB | ||
44 | #define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK | ||
45 | #define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x) | ||
46 | #define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x) | ||
47 | #define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS | ||
48 | #define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET | ||
49 | #define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB | ||
50 | #define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB | ||
51 | #define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK | ||
52 | #define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) | ||
53 | #define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) | ||
54 | #define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB | ||
55 | #define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB | ||
56 | #define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK | ||
57 | #define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) | ||
58 | #define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) | ||
59 | #define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB | ||
60 | #define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB | ||
61 | #define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK | ||
62 | #define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) | ||
63 | #define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) | ||
64 | #define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB | ||
65 | #define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB | ||
66 | #define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK | ||
67 | #define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) | ||
68 | #define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) | ||
69 | #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS | ||
70 | #define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET | ||
71 | #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
72 | #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
73 | #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
74 | #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
75 | #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
76 | #define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS | ||
77 | #define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET | ||
78 | #define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB | ||
79 | #define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB | ||
80 | #define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK | ||
81 | #define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) | ||
82 | #define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) | ||
83 | #define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB | ||
84 | #define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB | ||
85 | #define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK | ||
86 | #define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) | ||
87 | #define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) | ||
88 | #define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB | ||
89 | #define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB | ||
90 | #define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK | ||
91 | #define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) | ||
92 | #define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) | ||
93 | #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS | ||
94 | #define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET | ||
95 | #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
96 | #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
97 | #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
98 | #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
99 | #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
100 | #define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS | ||
101 | #define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET | ||
102 | #define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB | ||
103 | #define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB | ||
104 | #define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK | ||
105 | #define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) | ||
106 | #define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) | ||
107 | #define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB | ||
108 | #define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB | ||
109 | #define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK | ||
110 | #define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) | ||
111 | #define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) | ||
112 | #define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB | ||
113 | #define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB | ||
114 | #define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK | ||
115 | #define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) | ||
116 | #define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) | ||
117 | #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS | ||
118 | #define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET | ||
119 | #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
120 | #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
121 | #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
122 | #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
123 | #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
124 | #define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS | ||
125 | #define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET | ||
126 | #define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB | ||
127 | #define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB | ||
128 | #define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK | ||
129 | #define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) | ||
130 | #define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) | ||
131 | #define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB | ||
132 | #define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB | ||
133 | #define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK | ||
134 | #define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) | ||
135 | #define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) | ||
136 | #define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB | ||
137 | #define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB | ||
138 | #define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK | ||
139 | #define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) | ||
140 | #define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) | ||
141 | #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS | ||
142 | #define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET | ||
143 | #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
144 | #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
145 | #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
146 | #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
147 | #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
148 | #define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS | ||
149 | #define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET | ||
150 | #define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB | ||
151 | #define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB | ||
152 | #define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK | ||
153 | #define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) | ||
154 | #define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) | ||
155 | #define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB | ||
156 | #define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB | ||
157 | #define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK | ||
158 | #define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) | ||
159 | #define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) | ||
160 | #define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB | ||
161 | #define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB | ||
162 | #define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK | ||
163 | #define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) | ||
164 | #define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) | ||
165 | #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS | ||
166 | #define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET | ||
167 | #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
168 | #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
169 | #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
170 | #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
171 | #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
172 | #define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS | ||
173 | #define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET | ||
174 | #define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB | ||
175 | #define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB | ||
176 | #define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK | ||
177 | #define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) | ||
178 | #define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) | ||
179 | #define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB | ||
180 | #define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB | ||
181 | #define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK | ||
182 | #define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) | ||
183 | #define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) | ||
184 | #define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB | ||
185 | #define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB | ||
186 | #define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK | ||
187 | #define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) | ||
188 | #define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) | ||
189 | #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS | ||
190 | #define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET | ||
191 | #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
192 | #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
193 | #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
194 | #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
195 | #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
196 | #define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS | ||
197 | #define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET | ||
198 | #define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB | ||
199 | #define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB | ||
200 | #define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK | ||
201 | #define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) | ||
202 | #define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) | ||
203 | #define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB | ||
204 | #define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB | ||
205 | #define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK | ||
206 | #define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) | ||
207 | #define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) | ||
208 | #define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB | ||
209 | #define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB | ||
210 | #define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK | ||
211 | #define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) | ||
212 | #define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) | ||
213 | #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS | ||
214 | #define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET | ||
215 | #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
216 | #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
217 | #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
218 | #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
219 | #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
220 | #define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS | ||
221 | #define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET | ||
222 | #define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB | ||
223 | #define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB | ||
224 | #define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK | ||
225 | #define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) | ||
226 | #define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) | ||
227 | #define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB | ||
228 | #define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB | ||
229 | #define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK | ||
230 | #define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) | ||
231 | #define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) | ||
232 | #define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB | ||
233 | #define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB | ||
234 | #define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK | ||
235 | #define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) | ||
236 | #define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) | ||
237 | #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS | ||
238 | #define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET | ||
239 | #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
240 | #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
241 | #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
242 | #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
243 | #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
244 | #define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS | ||
245 | #define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET | ||
246 | #define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB | ||
247 | #define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB | ||
248 | #define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK | ||
249 | #define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) | ||
250 | #define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) | ||
251 | #define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB | ||
252 | #define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB | ||
253 | #define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK | ||
254 | #define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) | ||
255 | #define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) | ||
256 | #define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB | ||
257 | #define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB | ||
258 | #define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK | ||
259 | #define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) | ||
260 | #define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) | ||
261 | #define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS | ||
262 | #define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET | ||
263 | #define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB | ||
264 | #define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB | ||
265 | #define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK | ||
266 | #define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) | ||
267 | #define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) | ||
268 | #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB | ||
269 | #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB | ||
270 | #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK | ||
271 | #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) | ||
272 | #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) | ||
273 | #define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB | ||
274 | #define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB | ||
275 | #define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK | ||
276 | #define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) | ||
277 | #define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) | ||
278 | #define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB | ||
279 | #define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB | ||
280 | #define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK | ||
281 | #define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) | ||
282 | #define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) | ||
283 | #define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB | ||
284 | #define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB | ||
285 | #define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK | ||
286 | #define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) | ||
287 | #define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) | ||
288 | #define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB | ||
289 | #define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB | ||
290 | #define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK | ||
291 | #define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) | ||
292 | #define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) | ||
293 | #define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB | ||
294 | #define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB | ||
295 | #define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK | ||
296 | #define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) | ||
297 | #define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) | ||
298 | #define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB | ||
299 | #define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB | ||
300 | #define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK | ||
301 | #define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x) | ||
302 | #define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x) | ||
303 | #define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS | ||
304 | #define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET | ||
305 | #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB | ||
306 | #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB | ||
307 | #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK | ||
308 | #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) | ||
309 | #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) | ||
310 | #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB | ||
311 | #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB | ||
312 | #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK | ||
313 | #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) | ||
314 | #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) | ||
315 | #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB | ||
316 | #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB | ||
317 | #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK | ||
318 | #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) | ||
319 | #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) | ||
320 | #define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB | ||
321 | #define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB | ||
322 | #define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK | ||
323 | #define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) | ||
324 | #define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) | ||
325 | #define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB | ||
326 | #define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB | ||
327 | #define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK | ||
328 | #define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) | ||
329 | #define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) | ||
330 | #define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB | ||
331 | #define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB | ||
332 | #define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK | ||
333 | #define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) | ||
334 | #define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) | ||
335 | #define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB | ||
336 | #define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB | ||
337 | #define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK | ||
338 | #define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) | ||
339 | #define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) | ||
340 | #define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB | ||
341 | #define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB | ||
342 | #define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK | ||
343 | #define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x) | ||
344 | #define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x) | ||
345 | #define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS | ||
346 | #define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET | ||
347 | #define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB | ||
348 | #define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB | ||
349 | #define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK | ||
350 | #define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x) | ||
351 | #define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x) | ||
352 | #define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS | ||
353 | #define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET | ||
354 | #define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB | ||
355 | #define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB | ||
356 | #define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK | ||
357 | #define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x) | ||
358 | #define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x) | ||
359 | #define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS | ||
360 | #define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET | ||
361 | #define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB | ||
362 | #define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB | ||
363 | #define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK | ||
364 | #define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x) | ||
365 | #define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x) | ||
366 | #define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS | ||
367 | #define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET | ||
368 | #define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB | ||
369 | #define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB | ||
370 | #define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK | ||
371 | #define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x) | ||
372 | #define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x) | ||
373 | #define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS | ||
374 | #define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET | ||
375 | #define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB | ||
376 | #define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB | ||
377 | #define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK | ||
378 | #define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) | ||
379 | #define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) | ||
380 | #define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS | ||
381 | #define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET | ||
382 | #define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB | ||
383 | #define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB | ||
384 | #define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK | ||
385 | #define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) | ||
386 | #define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) | ||
387 | #define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS | ||
388 | #define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET | ||
389 | #define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB | ||
390 | #define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB | ||
391 | #define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK | ||
392 | #define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x) | ||
393 | #define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x) | ||
394 | #define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS | ||
395 | #define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET | ||
396 | #define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB | ||
397 | #define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB | ||
398 | #define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK | ||
399 | #define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x) | ||
400 | #define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x) | ||
401 | #define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS | ||
402 | #define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET | ||
403 | #define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB | ||
404 | #define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB | ||
405 | #define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK | ||
406 | #define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x) | ||
407 | #define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x) | ||
408 | #define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS | ||
409 | #define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET | ||
410 | #define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB | ||
411 | #define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB | ||
412 | #define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK | ||
413 | #define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x) | ||
414 | #define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x) | ||
415 | #define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS | ||
416 | #define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET | ||
417 | #define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB | ||
418 | #define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB | ||
419 | #define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK | ||
420 | #define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x) | ||
421 | #define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x) | ||
422 | #define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS | ||
423 | #define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET | ||
424 | #define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
425 | #define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
426 | #define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
427 | #define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
428 | #define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
429 | #define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS | ||
430 | #define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET | ||
431 | #define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB | ||
432 | #define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB | ||
433 | #define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK | ||
434 | #define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) | ||
435 | #define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) | ||
436 | #define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB | ||
437 | #define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB | ||
438 | #define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK | ||
439 | #define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) | ||
440 | #define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) | ||
441 | #define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB | ||
442 | #define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB | ||
443 | #define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK | ||
444 | #define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) | ||
445 | #define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) | ||
446 | #define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS | ||
447 | #define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET | ||
448 | #define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB | ||
449 | #define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB | ||
450 | #define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK | ||
451 | #define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) | ||
452 | #define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) | ||
453 | #define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS | ||
454 | #define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET | ||
455 | #define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB | ||
456 | #define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB | ||
457 | #define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK | ||
458 | #define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) | ||
459 | #define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) | ||
460 | #define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB | ||
461 | #define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB | ||
462 | #define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK | ||
463 | #define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) | ||
464 | #define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) | ||
465 | #define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB | ||
466 | #define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB | ||
467 | #define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK | ||
468 | #define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) | ||
469 | #define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) | ||
470 | #define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS | ||
471 | #define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET | ||
472 | #define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB | ||
473 | #define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB | ||
474 | #define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK | ||
475 | #define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) | ||
476 | #define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) | ||
477 | #define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB | ||
478 | #define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB | ||
479 | #define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK | ||
480 | #define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) | ||
481 | #define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) | ||
482 | #define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB | ||
483 | #define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB | ||
484 | #define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK | ||
485 | #define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) | ||
486 | #define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) | ||
487 | #define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB | ||
488 | #define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB | ||
489 | #define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK | ||
490 | #define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) | ||
491 | #define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) | ||
492 | #define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB | ||
493 | #define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB | ||
494 | #define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK | ||
495 | #define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) | ||
496 | #define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) | ||
497 | #define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB | ||
498 | #define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB | ||
499 | #define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK | ||
500 | #define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) | ||
501 | #define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) | ||
502 | #define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB | ||
503 | #define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB | ||
504 | #define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK | ||
505 | #define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) | ||
506 | #define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) | ||
507 | #define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS | ||
508 | #define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET | ||
509 | #define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB | ||
510 | #define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB | ||
511 | #define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK | ||
512 | #define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) | ||
513 | #define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) | ||
514 | #define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB | ||
515 | #define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB | ||
516 | #define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK | ||
517 | #define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) | ||
518 | #define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) | ||
519 | #define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB | ||
520 | #define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB | ||
521 | #define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK | ||
522 | #define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) | ||
523 | #define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) | ||
524 | #define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB | ||
525 | #define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB | ||
526 | #define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK | ||
527 | #define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) | ||
528 | #define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) | ||
529 | #define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB | ||
530 | #define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB | ||
531 | #define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK | ||
532 | #define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) | ||
533 | #define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) | ||
534 | #define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB | ||
535 | #define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB | ||
536 | #define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK | ||
537 | #define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) | ||
538 | #define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) | ||
539 | #define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB | ||
540 | #define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB | ||
541 | #define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK | ||
542 | #define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) | ||
543 | #define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) | ||
544 | #define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS | ||
545 | #define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET | ||
546 | #define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB | ||
547 | #define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB | ||
548 | #define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK | ||
549 | #define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x) | ||
550 | #define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x) | ||
551 | |||
552 | #endif | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h new file mode 100644 index 00000000000..038d0d01927 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h | |||
@@ -0,0 +1,471 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #ifndef _MBOX_WLAN_HOST_REG_REG_H_ | ||
25 | #define _MBOX_WLAN_HOST_REG_REG_H_ | ||
26 | |||
27 | #define HOST_INT_STATUS_ADDRESS 0x00000400 | ||
28 | #define HOST_INT_STATUS_OFFSET 0x00000400 | ||
29 | #define HOST_INT_STATUS_ERROR_MSB 7 | ||
30 | #define HOST_INT_STATUS_ERROR_LSB 7 | ||
31 | #define HOST_INT_STATUS_ERROR_MASK 0x00000080 | ||
32 | #define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) | ||
33 | #define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) | ||
34 | #define HOST_INT_STATUS_CPU_MSB 6 | ||
35 | #define HOST_INT_STATUS_CPU_LSB 6 | ||
36 | #define HOST_INT_STATUS_CPU_MASK 0x00000040 | ||
37 | #define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) | ||
38 | #define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) | ||
39 | #define HOST_INT_STATUS_INT_MSB 5 | ||
40 | #define HOST_INT_STATUS_INT_LSB 5 | ||
41 | #define HOST_INT_STATUS_INT_MASK 0x00000020 | ||
42 | #define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB) | ||
43 | #define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK) | ||
44 | #define HOST_INT_STATUS_COUNTER_MSB 4 | ||
45 | #define HOST_INT_STATUS_COUNTER_LSB 4 | ||
46 | #define HOST_INT_STATUS_COUNTER_MASK 0x00000010 | ||
47 | #define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) | ||
48 | #define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) | ||
49 | #define HOST_INT_STATUS_MBOX_DATA_MSB 3 | ||
50 | #define HOST_INT_STATUS_MBOX_DATA_LSB 0 | ||
51 | #define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f | ||
52 | #define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) | ||
53 | #define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) | ||
54 | |||
55 | #define CPU_INT_STATUS_ADDRESS 0x00000401 | ||
56 | #define CPU_INT_STATUS_OFFSET 0x00000401 | ||
57 | #define CPU_INT_STATUS_BIT_MSB 7 | ||
58 | #define CPU_INT_STATUS_BIT_LSB 0 | ||
59 | #define CPU_INT_STATUS_BIT_MASK 0x000000ff | ||
60 | #define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) | ||
61 | #define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) | ||
62 | |||
63 | #define ERROR_INT_STATUS_ADDRESS 0x00000402 | ||
64 | #define ERROR_INT_STATUS_OFFSET 0x00000402 | ||
65 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 | ||
66 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 | ||
67 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 | ||
68 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) | ||
69 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) | ||
70 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5 | ||
71 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5 | ||
72 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 | ||
73 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) | ||
74 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) | ||
75 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4 | ||
76 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4 | ||
77 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 | ||
78 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) | ||
79 | #define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) | ||
80 | #define ERROR_INT_STATUS_SPI_MSB 3 | ||
81 | #define ERROR_INT_STATUS_SPI_LSB 3 | ||
82 | #define ERROR_INT_STATUS_SPI_MASK 0x00000008 | ||
83 | #define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) | ||
84 | #define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) | ||
85 | #define ERROR_INT_STATUS_WAKEUP_MSB 2 | ||
86 | #define ERROR_INT_STATUS_WAKEUP_LSB 2 | ||
87 | #define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 | ||
88 | #define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) | ||
89 | #define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) | ||
90 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 | ||
91 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 | ||
92 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 | ||
93 | #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) | ||
94 | #define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) | ||
95 | #define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 | ||
96 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 | ||
97 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 | ||
98 | #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) | ||
99 | #define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) | ||
100 | |||
101 | #define COUNTER_INT_STATUS_ADDRESS 0x00000403 | ||
102 | #define COUNTER_INT_STATUS_OFFSET 0x00000403 | ||
103 | #define COUNTER_INT_STATUS_COUNTER_MSB 7 | ||
104 | #define COUNTER_INT_STATUS_COUNTER_LSB 0 | ||
105 | #define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff | ||
106 | #define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) | ||
107 | #define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) | ||
108 | |||
109 | #define MBOX_FRAME_ADDRESS 0x00000404 | ||
110 | #define MBOX_FRAME_OFFSET 0x00000404 | ||
111 | #define MBOX_FRAME_RX_EOM_MSB 7 | ||
112 | #define MBOX_FRAME_RX_EOM_LSB 4 | ||
113 | #define MBOX_FRAME_RX_EOM_MASK 0x000000f0 | ||
114 | #define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) | ||
115 | #define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) | ||
116 | #define MBOX_FRAME_RX_SOM_MSB 3 | ||
117 | #define MBOX_FRAME_RX_SOM_LSB 0 | ||
118 | #define MBOX_FRAME_RX_SOM_MASK 0x0000000f | ||
119 | #define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) | ||
120 | #define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) | ||
121 | |||
122 | #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 | ||
123 | #define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 | ||
124 | #define RX_LOOKAHEAD_VALID_MBOX_MSB 3 | ||
125 | #define RX_LOOKAHEAD_VALID_MBOX_LSB 0 | ||
126 | #define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f | ||
127 | #define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) | ||
128 | #define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) | ||
129 | |||
130 | #define HOST_INT_STATUS2_ADDRESS 0x00000406 | ||
131 | #define HOST_INT_STATUS2_OFFSET 0x00000406 | ||
132 | #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2 | ||
133 | #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2 | ||
134 | #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004 | ||
135 | #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) | ||
136 | #define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) | ||
137 | #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1 | ||
138 | #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1 | ||
139 | #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002 | ||
140 | #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) | ||
141 | #define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) | ||
142 | #define HOST_INT_STATUS2_GMBOX_DATA_MSB 0 | ||
143 | #define HOST_INT_STATUS2_GMBOX_DATA_LSB 0 | ||
144 | #define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001 | ||
145 | #define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB) | ||
146 | #define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK) | ||
147 | |||
148 | #define GMBOX_RX_AVAIL_ADDRESS 0x00000407 | ||
149 | #define GMBOX_RX_AVAIL_OFFSET 0x00000407 | ||
150 | #define GMBOX_RX_AVAIL_BYTE_MSB 6 | ||
151 | #define GMBOX_RX_AVAIL_BYTE_LSB 0 | ||
152 | #define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f | ||
153 | #define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB) | ||
154 | #define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK) | ||
155 | |||
156 | #define RX_LOOKAHEAD0_ADDRESS 0x00000408 | ||
157 | #define RX_LOOKAHEAD0_OFFSET 0x00000408 | ||
158 | #define RX_LOOKAHEAD0_DATA_MSB 7 | ||
159 | #define RX_LOOKAHEAD0_DATA_LSB 0 | ||
160 | #define RX_LOOKAHEAD0_DATA_MASK 0x000000ff | ||
161 | #define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) | ||
162 | #define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) | ||
163 | |||
164 | #define RX_LOOKAHEAD1_ADDRESS 0x0000040c | ||
165 | #define RX_LOOKAHEAD1_OFFSET 0x0000040c | ||
166 | #define RX_LOOKAHEAD1_DATA_MSB 7 | ||
167 | #define RX_LOOKAHEAD1_DATA_LSB 0 | ||
168 | #define RX_LOOKAHEAD1_DATA_MASK 0x000000ff | ||
169 | #define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) | ||
170 | #define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) | ||
171 | |||
172 | #define RX_LOOKAHEAD2_ADDRESS 0x00000410 | ||
173 | #define RX_LOOKAHEAD2_OFFSET 0x00000410 | ||
174 | #define RX_LOOKAHEAD2_DATA_MSB 7 | ||
175 | #define RX_LOOKAHEAD2_DATA_LSB 0 | ||
176 | #define RX_LOOKAHEAD2_DATA_MASK 0x000000ff | ||
177 | #define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) | ||
178 | #define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) | ||
179 | |||
180 | #define RX_LOOKAHEAD3_ADDRESS 0x00000414 | ||
181 | #define RX_LOOKAHEAD3_OFFSET 0x00000414 | ||
182 | #define RX_LOOKAHEAD3_DATA_MSB 7 | ||
183 | #define RX_LOOKAHEAD3_DATA_LSB 0 | ||
184 | #define RX_LOOKAHEAD3_DATA_MASK 0x000000ff | ||
185 | #define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) | ||
186 | #define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) | ||
187 | |||
188 | #define INT_STATUS_ENABLE_ADDRESS 0x00000418 | ||
189 | #define INT_STATUS_ENABLE_OFFSET 0x00000418 | ||
190 | #define INT_STATUS_ENABLE_ERROR_MSB 7 | ||
191 | #define INT_STATUS_ENABLE_ERROR_LSB 7 | ||
192 | #define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 | ||
193 | #define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) | ||
194 | #define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) | ||
195 | #define INT_STATUS_ENABLE_CPU_MSB 6 | ||
196 | #define INT_STATUS_ENABLE_CPU_LSB 6 | ||
197 | #define INT_STATUS_ENABLE_CPU_MASK 0x00000040 | ||
198 | #define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) | ||
199 | #define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) | ||
200 | #define INT_STATUS_ENABLE_INT_MSB 5 | ||
201 | #define INT_STATUS_ENABLE_INT_LSB 5 | ||
202 | #define INT_STATUS_ENABLE_INT_MASK 0x00000020 | ||
203 | #define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB) | ||
204 | #define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK) | ||
205 | #define INT_STATUS_ENABLE_COUNTER_MSB 4 | ||
206 | #define INT_STATUS_ENABLE_COUNTER_LSB 4 | ||
207 | #define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 | ||
208 | #define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) | ||
209 | #define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) | ||
210 | #define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 | ||
211 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 | ||
212 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f | ||
213 | #define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) | ||
214 | #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) | ||
215 | |||
216 | #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 | ||
217 | #define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 | ||
218 | #define CPU_INT_STATUS_ENABLE_BIT_MSB 7 | ||
219 | #define CPU_INT_STATUS_ENABLE_BIT_LSB 0 | ||
220 | #define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff | ||
221 | #define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) | ||
222 | #define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) | ||
223 | |||
224 | #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a | ||
225 | #define ERROR_STATUS_ENABLE_OFFSET 0x0000041a | ||
226 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 | ||
227 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 | ||
228 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 | ||
229 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) | ||
230 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) | ||
231 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5 | ||
232 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5 | ||
233 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 | ||
234 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) | ||
235 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) | ||
236 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4 | ||
237 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4 | ||
238 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 | ||
239 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) | ||
240 | #define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) | ||
241 | #define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 | ||
242 | #define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 | ||
243 | #define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 | ||
244 | #define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) | ||
245 | #define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) | ||
246 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 | ||
247 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 | ||
248 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 | ||
249 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) | ||
250 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) | ||
251 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 | ||
252 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 | ||
253 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 | ||
254 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) | ||
255 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) | ||
256 | |||
257 | #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b | ||
258 | #define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b | ||
259 | #define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 | ||
260 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 | ||
261 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff | ||
262 | #define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) | ||
263 | #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) | ||
264 | |||
265 | #define COUNT_ADDRESS 0x00000420 | ||
266 | #define COUNT_OFFSET 0x00000420 | ||
267 | #define COUNT_VALUE_MSB 7 | ||
268 | #define COUNT_VALUE_LSB 0 | ||
269 | #define COUNT_VALUE_MASK 0x000000ff | ||
270 | #define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) | ||
271 | #define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) | ||
272 | |||
273 | #define COUNT_DEC_ADDRESS 0x00000440 | ||
274 | #define COUNT_DEC_OFFSET 0x00000440 | ||
275 | #define COUNT_DEC_VALUE_MSB 7 | ||
276 | #define COUNT_DEC_VALUE_LSB 0 | ||
277 | #define COUNT_DEC_VALUE_MASK 0x000000ff | ||
278 | #define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) | ||
279 | #define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) | ||
280 | |||
281 | #define SCRATCH_ADDRESS 0x00000460 | ||
282 | #define SCRATCH_OFFSET 0x00000460 | ||
283 | #define SCRATCH_VALUE_MSB 7 | ||
284 | #define SCRATCH_VALUE_LSB 0 | ||
285 | #define SCRATCH_VALUE_MASK 0x000000ff | ||
286 | #define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) | ||
287 | #define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) | ||
288 | |||
289 | #define FIFO_TIMEOUT_ADDRESS 0x00000468 | ||
290 | #define FIFO_TIMEOUT_OFFSET 0x00000468 | ||
291 | #define FIFO_TIMEOUT_VALUE_MSB 7 | ||
292 | #define FIFO_TIMEOUT_VALUE_LSB 0 | ||
293 | #define FIFO_TIMEOUT_VALUE_MASK 0x000000ff | ||
294 | #define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) | ||
295 | #define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) | ||
296 | |||
297 | #define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 | ||
298 | #define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 | ||
299 | #define FIFO_TIMEOUT_ENABLE_SET_MSB 0 | ||
300 | #define FIFO_TIMEOUT_ENABLE_SET_LSB 0 | ||
301 | #define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 | ||
302 | #define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) | ||
303 | #define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) | ||
304 | |||
305 | #define DISABLE_SLEEP_ADDRESS 0x0000046a | ||
306 | #define DISABLE_SLEEP_OFFSET 0x0000046a | ||
307 | #define DISABLE_SLEEP_FOR_INT_MSB 1 | ||
308 | #define DISABLE_SLEEP_FOR_INT_LSB 1 | ||
309 | #define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 | ||
310 | #define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) | ||
311 | #define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) | ||
312 | #define DISABLE_SLEEP_ON_MSB 0 | ||
313 | #define DISABLE_SLEEP_ON_LSB 0 | ||
314 | #define DISABLE_SLEEP_ON_MASK 0x00000001 | ||
315 | #define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) | ||
316 | #define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) | ||
317 | |||
318 | #define LOCAL_BUS_ADDRESS 0x00000470 | ||
319 | #define LOCAL_BUS_OFFSET 0x00000470 | ||
320 | #define LOCAL_BUS_STATE_MSB 1 | ||
321 | #define LOCAL_BUS_STATE_LSB 0 | ||
322 | #define LOCAL_BUS_STATE_MASK 0x00000003 | ||
323 | #define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) | ||
324 | #define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) | ||
325 | |||
326 | #define INT_WLAN_ADDRESS 0x00000472 | ||
327 | #define INT_WLAN_OFFSET 0x00000472 | ||
328 | #define INT_WLAN_VECTOR_MSB 7 | ||
329 | #define INT_WLAN_VECTOR_LSB 0 | ||
330 | #define INT_WLAN_VECTOR_MASK 0x000000ff | ||
331 | #define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) | ||
332 | #define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) | ||
333 | |||
334 | #define WINDOW_DATA_ADDRESS 0x00000474 | ||
335 | #define WINDOW_DATA_OFFSET 0x00000474 | ||
336 | #define WINDOW_DATA_DATA_MSB 7 | ||
337 | #define WINDOW_DATA_DATA_LSB 0 | ||
338 | #define WINDOW_DATA_DATA_MASK 0x000000ff | ||
339 | #define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) | ||
340 | #define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) | ||
341 | |||
342 | #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 | ||
343 | #define WINDOW_WRITE_ADDR_OFFSET 0x00000478 | ||
344 | #define WINDOW_WRITE_ADDR_ADDR_MSB 7 | ||
345 | #define WINDOW_WRITE_ADDR_ADDR_LSB 0 | ||
346 | #define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff | ||
347 | #define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) | ||
348 | #define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) | ||
349 | |||
350 | #define WINDOW_READ_ADDR_ADDRESS 0x0000047c | ||
351 | #define WINDOW_READ_ADDR_OFFSET 0x0000047c | ||
352 | #define WINDOW_READ_ADDR_ADDR_MSB 7 | ||
353 | #define WINDOW_READ_ADDR_ADDR_LSB 0 | ||
354 | #define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff | ||
355 | #define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) | ||
356 | #define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) | ||
357 | |||
358 | #define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480 | ||
359 | #define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480 | ||
360 | #define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4 | ||
361 | #define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4 | ||
362 | #define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010 | ||
363 | #define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) | ||
364 | #define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) | ||
365 | #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 | ||
366 | #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 | ||
367 | #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 | ||
368 | #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) | ||
369 | #define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) | ||
370 | #define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2 | ||
371 | #define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2 | ||
372 | #define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004 | ||
373 | #define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) | ||
374 | #define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) | ||
375 | #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1 | ||
376 | #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0 | ||
377 | #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003 | ||
378 | #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) | ||
379 | #define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) | ||
380 | |||
381 | #define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481 | ||
382 | #define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481 | ||
383 | #define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3 | ||
384 | #define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3 | ||
385 | #define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008 | ||
386 | #define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) | ||
387 | #define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) | ||
388 | #define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2 | ||
389 | #define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2 | ||
390 | #define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004 | ||
391 | #define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB) | ||
392 | #define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) | ||
393 | #define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1 | ||
394 | #define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1 | ||
395 | #define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002 | ||
396 | #define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB) | ||
397 | #define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) | ||
398 | #define HOST_CTRL_SPI_STATUS_READY_MSB 0 | ||
399 | #define HOST_CTRL_SPI_STATUS_READY_LSB 0 | ||
400 | #define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001 | ||
401 | #define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB) | ||
402 | #define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK) | ||
403 | |||
404 | #define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 | ||
405 | #define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 | ||
406 | #define NON_ASSOC_SLEEP_EN_BIT_MSB 0 | ||
407 | #define NON_ASSOC_SLEEP_EN_BIT_LSB 0 | ||
408 | #define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 | ||
409 | #define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) | ||
410 | #define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) | ||
411 | |||
412 | #define CPU_DBG_SEL_ADDRESS 0x00000483 | ||
413 | #define CPU_DBG_SEL_OFFSET 0x00000483 | ||
414 | #define CPU_DBG_SEL_BIT_MSB 5 | ||
415 | #define CPU_DBG_SEL_BIT_LSB 0 | ||
416 | #define CPU_DBG_SEL_BIT_MASK 0x0000003f | ||
417 | #define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB) | ||
418 | #define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK) | ||
419 | |||
420 | #define CPU_DBG_ADDRESS 0x00000484 | ||
421 | #define CPU_DBG_OFFSET 0x00000484 | ||
422 | #define CPU_DBG_DATA_MSB 7 | ||
423 | #define CPU_DBG_DATA_LSB 0 | ||
424 | #define CPU_DBG_DATA_MASK 0x000000ff | ||
425 | #define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB) | ||
426 | #define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK) | ||
427 | |||
428 | #define INT_STATUS2_ENABLE_ADDRESS 0x00000488 | ||
429 | #define INT_STATUS2_ENABLE_OFFSET 0x00000488 | ||
430 | #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2 | ||
431 | #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2 | ||
432 | #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004 | ||
433 | #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) | ||
434 | #define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) | ||
435 | #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1 | ||
436 | #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1 | ||
437 | #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002 | ||
438 | #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) | ||
439 | #define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) | ||
440 | #define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0 | ||
441 | #define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0 | ||
442 | #define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001 | ||
443 | #define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB) | ||
444 | #define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) | ||
445 | |||
446 | #define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490 | ||
447 | #define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490 | ||
448 | #define GMBOX_RX_LOOKAHEAD_DATA_MSB 7 | ||
449 | #define GMBOX_RX_LOOKAHEAD_DATA_LSB 0 | ||
450 | #define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff | ||
451 | #define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB) | ||
452 | #define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK) | ||
453 | |||
454 | #define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498 | ||
455 | #define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498 | ||
456 | #define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0 | ||
457 | #define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0 | ||
458 | #define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001 | ||
459 | #define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) | ||
460 | #define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) | ||
461 | |||
462 | #define CIS_WINDOW_ADDRESS 0x00000600 | ||
463 | #define CIS_WINDOW_OFFSET 0x00000600 | ||
464 | #define CIS_WINDOW_DATA_MSB 7 | ||
465 | #define CIS_WINDOW_DATA_LSB 0 | ||
466 | #define CIS_WINDOW_DATA_MASK 0x000000ff | ||
467 | #define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) | ||
468 | #define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) | ||
469 | |||
470 | |||
471 | #endif /* _MBOX_WLAN_HOST_REG_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h new file mode 100644 index 00000000000..f5167b9ae8d --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h | |||
@@ -0,0 +1,589 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #ifndef _MBOX_WLAN_REG_REG_H_ | ||
25 | #define _MBOX_WLAN_REG_REG_H_ | ||
26 | |||
27 | #define WLAN_MBOX_FIFO_ADDRESS 0x00000000 | ||
28 | #define WLAN_MBOX_FIFO_OFFSET 0x00000000 | ||
29 | #define WLAN_MBOX_FIFO_DATA_MSB 19 | ||
30 | #define WLAN_MBOX_FIFO_DATA_LSB 0 | ||
31 | #define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff | ||
32 | #define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB) | ||
33 | #define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK) | ||
34 | |||
35 | #define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010 | ||
36 | #define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010 | ||
37 | #define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19 | ||
38 | #define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16 | ||
39 | #define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 | ||
40 | #define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) | ||
41 | #define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) | ||
42 | #define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15 | ||
43 | #define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12 | ||
44 | #define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 | ||
45 | #define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB) | ||
46 | #define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) | ||
47 | |||
48 | #define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014 | ||
49 | #define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014 | ||
50 | #define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 | ||
51 | #define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 | ||
52 | #define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 | ||
53 | #define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) | ||
54 | #define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) | ||
55 | #define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2 | ||
56 | #define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2 | ||
57 | #define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 | ||
58 | #define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) | ||
59 | #define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) | ||
60 | #define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 | ||
61 | #define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 | ||
62 | #define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 | ||
63 | #define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) | ||
64 | #define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) | ||
65 | #define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0 | ||
66 | #define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0 | ||
67 | #define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 | ||
68 | #define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) | ||
69 | #define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) | ||
70 | |||
71 | #define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 | ||
72 | #define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 | ||
73 | #define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
74 | #define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
75 | #define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
76 | #define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
77 | #define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
78 | |||
79 | #define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c | ||
80 | #define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c | ||
81 | #define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 | ||
82 | #define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 | ||
83 | #define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 | ||
84 | #define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) | ||
85 | #define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) | ||
86 | #define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1 | ||
87 | #define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1 | ||
88 | #define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 | ||
89 | #define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) | ||
90 | #define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) | ||
91 | #define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0 | ||
92 | #define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0 | ||
93 | #define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 | ||
94 | #define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) | ||
95 | #define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) | ||
96 | |||
97 | #define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 | ||
98 | #define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 | ||
99 | #define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
100 | #define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
101 | #define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
102 | #define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
103 | #define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
104 | |||
105 | #define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 | ||
106 | #define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 | ||
107 | #define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 | ||
108 | #define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 | ||
109 | #define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 | ||
110 | #define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) | ||
111 | #define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) | ||
112 | #define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1 | ||
113 | #define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1 | ||
114 | #define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 | ||
115 | #define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) | ||
116 | #define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) | ||
117 | #define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0 | ||
118 | #define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0 | ||
119 | #define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 | ||
120 | #define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) | ||
121 | #define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) | ||
122 | |||
123 | #define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 | ||
124 | #define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 | ||
125 | #define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
126 | #define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
127 | #define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
128 | #define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
129 | #define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
130 | |||
131 | #define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c | ||
132 | #define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c | ||
133 | #define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 | ||
134 | #define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 | ||
135 | #define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 | ||
136 | #define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) | ||
137 | #define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) | ||
138 | #define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1 | ||
139 | #define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1 | ||
140 | #define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 | ||
141 | #define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) | ||
142 | #define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) | ||
143 | #define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0 | ||
144 | #define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0 | ||
145 | #define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 | ||
146 | #define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) | ||
147 | #define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) | ||
148 | |||
149 | #define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 | ||
150 | #define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 | ||
151 | #define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
152 | #define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
153 | #define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
154 | #define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
155 | #define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
156 | |||
157 | #define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 | ||
158 | #define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 | ||
159 | #define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 | ||
160 | #define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 | ||
161 | #define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 | ||
162 | #define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) | ||
163 | #define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) | ||
164 | #define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1 | ||
165 | #define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1 | ||
166 | #define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 | ||
167 | #define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) | ||
168 | #define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) | ||
169 | #define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0 | ||
170 | #define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0 | ||
171 | #define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 | ||
172 | #define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) | ||
173 | #define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) | ||
174 | |||
175 | #define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 | ||
176 | #define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 | ||
177 | #define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
178 | #define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
179 | #define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
180 | #define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
181 | #define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
182 | |||
183 | #define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c | ||
184 | #define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c | ||
185 | #define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 | ||
186 | #define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 | ||
187 | #define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 | ||
188 | #define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) | ||
189 | #define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) | ||
190 | #define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1 | ||
191 | #define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1 | ||
192 | #define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 | ||
193 | #define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) | ||
194 | #define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) | ||
195 | #define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0 | ||
196 | #define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0 | ||
197 | #define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 | ||
198 | #define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) | ||
199 | #define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) | ||
200 | |||
201 | #define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 | ||
202 | #define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 | ||
203 | #define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
204 | #define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
205 | #define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
206 | #define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
207 | #define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
208 | |||
209 | #define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 | ||
210 | #define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 | ||
211 | #define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 | ||
212 | #define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 | ||
213 | #define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 | ||
214 | #define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) | ||
215 | #define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) | ||
216 | #define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1 | ||
217 | #define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1 | ||
218 | #define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 | ||
219 | #define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) | ||
220 | #define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) | ||
221 | #define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0 | ||
222 | #define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0 | ||
223 | #define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 | ||
224 | #define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) | ||
225 | #define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) | ||
226 | |||
227 | #define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 | ||
228 | #define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 | ||
229 | #define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
230 | #define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
231 | #define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
232 | #define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
233 | #define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
234 | |||
235 | #define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c | ||
236 | #define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c | ||
237 | #define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 | ||
238 | #define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 | ||
239 | #define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 | ||
240 | #define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) | ||
241 | #define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) | ||
242 | #define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1 | ||
243 | #define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1 | ||
244 | #define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 | ||
245 | #define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) | ||
246 | #define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) | ||
247 | #define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0 | ||
248 | #define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0 | ||
249 | #define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 | ||
250 | #define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) | ||
251 | #define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) | ||
252 | |||
253 | #define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 | ||
254 | #define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 | ||
255 | #define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
256 | #define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
257 | #define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
258 | #define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
259 | #define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
260 | |||
261 | #define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 | ||
262 | #define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 | ||
263 | #define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 | ||
264 | #define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 | ||
265 | #define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 | ||
266 | #define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) | ||
267 | #define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) | ||
268 | #define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1 | ||
269 | #define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1 | ||
270 | #define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 | ||
271 | #define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) | ||
272 | #define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) | ||
273 | #define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0 | ||
274 | #define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0 | ||
275 | #define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 | ||
276 | #define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) | ||
277 | #define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) | ||
278 | |||
279 | #define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058 | ||
280 | #define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058 | ||
281 | #define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 | ||
282 | #define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 | ||
283 | #define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 | ||
284 | #define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) | ||
285 | #define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) | ||
286 | #define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 | ||
287 | #define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 | ||
288 | #define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 | ||
289 | #define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) | ||
290 | #define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) | ||
291 | #define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 | ||
292 | #define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 | ||
293 | #define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 | ||
294 | #define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) | ||
295 | #define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) | ||
296 | #define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 | ||
297 | #define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 | ||
298 | #define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 | ||
299 | #define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) | ||
300 | #define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) | ||
301 | #define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 | ||
302 | #define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 | ||
303 | #define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 | ||
304 | #define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) | ||
305 | #define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) | ||
306 | #define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 | ||
307 | #define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 | ||
308 | #define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 | ||
309 | #define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) | ||
310 | #define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) | ||
311 | #define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 | ||
312 | #define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 | ||
313 | #define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 | ||
314 | #define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) | ||
315 | #define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) | ||
316 | #define WLAN_MBOX_INT_STATUS_HOST_MSB 7 | ||
317 | #define WLAN_MBOX_INT_STATUS_HOST_LSB 0 | ||
318 | #define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff | ||
319 | #define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB) | ||
320 | #define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK) | ||
321 | |||
322 | #define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c | ||
323 | #define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c | ||
324 | #define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 | ||
325 | #define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 | ||
326 | #define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 | ||
327 | #define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) | ||
328 | #define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) | ||
329 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 | ||
330 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 | ||
331 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 | ||
332 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) | ||
333 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) | ||
334 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 | ||
335 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 | ||
336 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 | ||
337 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) | ||
338 | #define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) | ||
339 | #define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 | ||
340 | #define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 | ||
341 | #define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 | ||
342 | #define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) | ||
343 | #define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) | ||
344 | #define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 | ||
345 | #define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 | ||
346 | #define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 | ||
347 | #define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) | ||
348 | #define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) | ||
349 | #define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 | ||
350 | #define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 | ||
351 | #define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 | ||
352 | #define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) | ||
353 | #define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) | ||
354 | #define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 | ||
355 | #define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 | ||
356 | #define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 | ||
357 | #define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) | ||
358 | #define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) | ||
359 | #define WLAN_MBOX_INT_ENABLE_HOST_MSB 7 | ||
360 | #define WLAN_MBOX_INT_ENABLE_HOST_LSB 0 | ||
361 | #define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff | ||
362 | #define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB) | ||
363 | #define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK) | ||
364 | |||
365 | #define WLAN_INT_HOST_ADDRESS 0x00000060 | ||
366 | #define WLAN_INT_HOST_OFFSET 0x00000060 | ||
367 | #define WLAN_INT_HOST_VECTOR_MSB 7 | ||
368 | #define WLAN_INT_HOST_VECTOR_LSB 0 | ||
369 | #define WLAN_INT_HOST_VECTOR_MASK 0x000000ff | ||
370 | #define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB) | ||
371 | #define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK) | ||
372 | |||
373 | #define WLAN_LOCAL_COUNT_ADDRESS 0x00000080 | ||
374 | #define WLAN_LOCAL_COUNT_OFFSET 0x00000080 | ||
375 | #define WLAN_LOCAL_COUNT_VALUE_MSB 7 | ||
376 | #define WLAN_LOCAL_COUNT_VALUE_LSB 0 | ||
377 | #define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff | ||
378 | #define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB) | ||
379 | #define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK) | ||
380 | |||
381 | #define WLAN_COUNT_INC_ADDRESS 0x000000a0 | ||
382 | #define WLAN_COUNT_INC_OFFSET 0x000000a0 | ||
383 | #define WLAN_COUNT_INC_VALUE_MSB 7 | ||
384 | #define WLAN_COUNT_INC_VALUE_LSB 0 | ||
385 | #define WLAN_COUNT_INC_VALUE_MASK 0x000000ff | ||
386 | #define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB) | ||
387 | #define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK) | ||
388 | |||
389 | #define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0 | ||
390 | #define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0 | ||
391 | #define WLAN_LOCAL_SCRATCH_VALUE_MSB 7 | ||
392 | #define WLAN_LOCAL_SCRATCH_VALUE_LSB 0 | ||
393 | #define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff | ||
394 | #define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB) | ||
395 | #define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK) | ||
396 | |||
397 | #define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0 | ||
398 | #define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0 | ||
399 | #define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0 | ||
400 | #define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0 | ||
401 | #define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 | ||
402 | #define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) | ||
403 | #define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) | ||
404 | |||
405 | #define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4 | ||
406 | #define WLAN_SDIO_CONFIG_OFFSET 0x000000e4 | ||
407 | #define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0 | ||
408 | #define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0 | ||
409 | #define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 | ||
410 | #define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) | ||
411 | #define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) | ||
412 | |||
413 | #define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8 | ||
414 | #define WLAN_MBOX_DEBUG_OFFSET 0x000000e8 | ||
415 | #define WLAN_MBOX_DEBUG_SEL_MSB 2 | ||
416 | #define WLAN_MBOX_DEBUG_SEL_LSB 0 | ||
417 | #define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007 | ||
418 | #define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB) | ||
419 | #define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK) | ||
420 | |||
421 | #define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec | ||
422 | #define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec | ||
423 | #define WLAN_MBOX_FIFO_RESET_INIT_MSB 0 | ||
424 | #define WLAN_MBOX_FIFO_RESET_INIT_LSB 0 | ||
425 | #define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001 | ||
426 | #define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB) | ||
427 | #define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK) | ||
428 | |||
429 | #define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0 | ||
430 | #define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0 | ||
431 | #define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0 | ||
432 | #define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0 | ||
433 | #define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001 | ||
434 | #define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB) | ||
435 | #define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) | ||
436 | |||
437 | #define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100 | ||
438 | #define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100 | ||
439 | #define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0 | ||
440 | #define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0 | ||
441 | #define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001 | ||
442 | #define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB) | ||
443 | #define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) | ||
444 | |||
445 | #define WLAN_SDIO_DEBUG_ADDRESS 0x00000110 | ||
446 | #define WLAN_SDIO_DEBUG_OFFSET 0x00000110 | ||
447 | #define WLAN_SDIO_DEBUG_SEL_MSB 3 | ||
448 | #define WLAN_SDIO_DEBUG_SEL_LSB 0 | ||
449 | #define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f | ||
450 | #define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB) | ||
451 | #define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK) | ||
452 | |||
453 | #define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114 | ||
454 | #define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114 | ||
455 | #define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
456 | #define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
457 | #define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
458 | #define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
459 | #define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
460 | |||
461 | #define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118 | ||
462 | #define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118 | ||
463 | #define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 | ||
464 | #define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 | ||
465 | #define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 | ||
466 | #define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) | ||
467 | #define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) | ||
468 | #define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1 | ||
469 | #define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1 | ||
470 | #define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 | ||
471 | #define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) | ||
472 | #define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) | ||
473 | #define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0 | ||
474 | #define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0 | ||
475 | #define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 | ||
476 | #define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) | ||
477 | #define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) | ||
478 | |||
479 | #define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c | ||
480 | #define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c | ||
481 | #define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 | ||
482 | #define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 | ||
483 | #define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc | ||
484 | #define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) | ||
485 | #define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) | ||
486 | |||
487 | #define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120 | ||
488 | #define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120 | ||
489 | #define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 | ||
490 | #define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 | ||
491 | #define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 | ||
492 | #define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) | ||
493 | #define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) | ||
494 | #define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1 | ||
495 | #define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1 | ||
496 | #define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 | ||
497 | #define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) | ||
498 | #define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) | ||
499 | #define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0 | ||
500 | #define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0 | ||
501 | #define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 | ||
502 | #define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) | ||
503 | #define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) | ||
504 | |||
505 | #define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124 | ||
506 | #define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124 | ||
507 | #define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6 | ||
508 | #define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6 | ||
509 | #define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040 | ||
510 | #define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) | ||
511 | #define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) | ||
512 | #define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5 | ||
513 | #define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5 | ||
514 | #define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020 | ||
515 | #define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) | ||
516 | #define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) | ||
517 | #define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4 | ||
518 | #define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4 | ||
519 | #define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010 | ||
520 | #define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) | ||
521 | #define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) | ||
522 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3 | ||
523 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3 | ||
524 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008 | ||
525 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) | ||
526 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) | ||
527 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2 | ||
528 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2 | ||
529 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004 | ||
530 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) | ||
531 | #define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) | ||
532 | #define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 | ||
533 | #define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 | ||
534 | #define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 | ||
535 | #define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) | ||
536 | #define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) | ||
537 | #define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 | ||
538 | #define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 | ||
539 | #define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 | ||
540 | #define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) | ||
541 | #define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) | ||
542 | |||
543 | #define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128 | ||
544 | #define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128 | ||
545 | #define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6 | ||
546 | #define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6 | ||
547 | #define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040 | ||
548 | #define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) | ||
549 | #define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) | ||
550 | #define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5 | ||
551 | #define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5 | ||
552 | #define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020 | ||
553 | #define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) | ||
554 | #define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) | ||
555 | #define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4 | ||
556 | #define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4 | ||
557 | #define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010 | ||
558 | #define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) | ||
559 | #define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) | ||
560 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3 | ||
561 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3 | ||
562 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008 | ||
563 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) | ||
564 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) | ||
565 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2 | ||
566 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2 | ||
567 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004 | ||
568 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) | ||
569 | #define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) | ||
570 | #define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 | ||
571 | #define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 | ||
572 | #define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 | ||
573 | #define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) | ||
574 | #define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) | ||
575 | #define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 | ||
576 | #define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 | ||
577 | #define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 | ||
578 | #define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) | ||
579 | #define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) | ||
580 | |||
581 | #define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000 | ||
582 | #define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000 | ||
583 | #define WLAN_HOST_IF_WINDOW_DATA_MSB 7 | ||
584 | #define WLAN_HOST_IF_WINDOW_DATA_LSB 0 | ||
585 | #define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff | ||
586 | #define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB) | ||
587 | #define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK) | ||
588 | |||
589 | #endif /* _MBOX_WLAN_REG_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h new file mode 100644 index 00000000000..fcafec88a6b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h | |||
@@ -0,0 +1,187 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #include "rtc_wlan_reg.h" | ||
25 | |||
26 | #ifndef BT_HEADERS | ||
27 | |||
28 | #define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS | ||
29 | #define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET | ||
30 | #define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB | ||
31 | #define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB | ||
32 | #define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK | ||
33 | #define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) | ||
34 | #define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) | ||
35 | #define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB | ||
36 | #define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB | ||
37 | #define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK | ||
38 | #define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) | ||
39 | #define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) | ||
40 | #define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB | ||
41 | #define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB | ||
42 | #define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK | ||
43 | #define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) | ||
44 | #define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) | ||
45 | #define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB | ||
46 | #define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB | ||
47 | #define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK | ||
48 | #define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) | ||
49 | #define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) | ||
50 | #define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB | ||
51 | #define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB | ||
52 | #define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK | ||
53 | #define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) | ||
54 | #define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) | ||
55 | #define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB | ||
56 | #define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB | ||
57 | #define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK | ||
58 | #define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x) | ||
59 | #define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x) | ||
60 | #define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB | ||
61 | #define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB | ||
62 | #define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK | ||
63 | #define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x) | ||
64 | #define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x) | ||
65 | #define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB | ||
66 | #define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB | ||
67 | #define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK | ||
68 | #define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x) | ||
69 | #define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x) | ||
70 | #define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB | ||
71 | #define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB | ||
72 | #define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK | ||
73 | #define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) | ||
74 | #define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) | ||
75 | #define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB | ||
76 | #define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB | ||
77 | #define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK | ||
78 | #define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) | ||
79 | #define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) | ||
80 | #define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB | ||
81 | #define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB | ||
82 | #define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK | ||
83 | #define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) | ||
84 | #define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) | ||
85 | #define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB | ||
86 | #define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB | ||
87 | #define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK | ||
88 | #define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x) | ||
89 | #define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x) | ||
90 | #define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB | ||
91 | #define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB | ||
92 | #define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK | ||
93 | #define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x) | ||
94 | #define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x) | ||
95 | #define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB | ||
96 | #define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB | ||
97 | #define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK | ||
98 | #define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x) | ||
99 | #define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x) | ||
100 | #define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS | ||
101 | #define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET | ||
102 | #define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB | ||
103 | #define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB | ||
104 | #define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK | ||
105 | #define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x) | ||
106 | #define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x) | ||
107 | #define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS | ||
108 | #define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET | ||
109 | #define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB | ||
110 | #define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB | ||
111 | #define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK | ||
112 | #define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x) | ||
113 | #define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x) | ||
114 | #define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS | ||
115 | #define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET | ||
116 | #define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB | ||
117 | #define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB | ||
118 | #define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK | ||
119 | #define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) | ||
120 | #define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) | ||
121 | #define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB | ||
122 | #define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB | ||
123 | #define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK | ||
124 | #define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) | ||
125 | #define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) | ||
126 | #define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS | ||
127 | #define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET | ||
128 | #define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB | ||
129 | #define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB | ||
130 | #define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK | ||
131 | #define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x) | ||
132 | #define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x) | ||
133 | #define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS | ||
134 | #define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET | ||
135 | #define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB | ||
136 | #define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB | ||
137 | #define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK | ||
138 | #define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) | ||
139 | #define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) | ||
140 | #define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB | ||
141 | #define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB | ||
142 | #define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK | ||
143 | #define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x) | ||
144 | #define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x) | ||
145 | #define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB | ||
146 | #define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB | ||
147 | #define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK | ||
148 | #define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) | ||
149 | #define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) | ||
150 | #define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB | ||
151 | #define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB | ||
152 | #define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK | ||
153 | #define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x) | ||
154 | #define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x) | ||
155 | #define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB | ||
156 | #define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB | ||
157 | #define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK | ||
158 | #define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x) | ||
159 | #define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x) | ||
160 | #define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS | ||
161 | #define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET | ||
162 | #define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB | ||
163 | #define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB | ||
164 | #define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK | ||
165 | #define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) | ||
166 | #define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) | ||
167 | #define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS | ||
168 | #define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET | ||
169 | #define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB | ||
170 | #define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB | ||
171 | #define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK | ||
172 | #define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) | ||
173 | #define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) | ||
174 | #define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS | ||
175 | #define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET | ||
176 | #define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB | ||
177 | #define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB | ||
178 | #define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK | ||
179 | #define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x) | ||
180 | #define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x) | ||
181 | #define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB | ||
182 | #define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB | ||
183 | #define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK | ||
184 | #define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x) | ||
185 | #define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x) | ||
186 | |||
187 | #endif | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h new file mode 100644 index 00000000000..5c048ff51b0 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h | |||
@@ -0,0 +1,162 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #ifndef _RTC_WLAN_REG_REG_H_ | ||
25 | #define _RTC_WLAN_REG_REG_H_ | ||
26 | |||
27 | #define WLAN_RESET_CONTROL_ADDRESS 0x00000000 | ||
28 | #define WLAN_RESET_CONTROL_OFFSET 0x00000000 | ||
29 | #define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB 14 | ||
30 | #define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB 14 | ||
31 | #define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00004000 | ||
32 | #define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) | ||
33 | #define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) | ||
34 | #define WLAN_RESET_CONTROL_BB_COLD_RST_MSB 13 | ||
35 | #define WLAN_RESET_CONTROL_BB_COLD_RST_LSB 13 | ||
36 | #define WLAN_RESET_CONTROL_BB_COLD_RST_MASK 0x00002000 | ||
37 | #define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB) | ||
38 | #define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) | ||
39 | #define WLAN_RESET_CONTROL_BB_WARM_RST_MSB 12 | ||
40 | #define WLAN_RESET_CONTROL_BB_WARM_RST_LSB 12 | ||
41 | #define WLAN_RESET_CONTROL_BB_WARM_RST_MASK 0x00001000 | ||
42 | #define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB) | ||
43 | #define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) | ||
44 | #define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB 11 | ||
45 | #define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB 11 | ||
46 | #define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 | ||
47 | #define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) | ||
48 | #define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) | ||
49 | #define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB 10 | ||
50 | #define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB 10 | ||
51 | #define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 | ||
52 | #define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) | ||
53 | #define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) | ||
54 | #define WLAN_RESET_CONTROL_RST_OUT_MSB 9 | ||
55 | #define WLAN_RESET_CONTROL_RST_OUT_LSB 9 | ||
56 | #define WLAN_RESET_CONTROL_RST_OUT_MASK 0x00000200 | ||
57 | #define WLAN_RESET_CONTROL_RST_OUT_GET(x) (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB) | ||
58 | #define WLAN_RESET_CONTROL_RST_OUT_SET(x) (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK) | ||
59 | #define WLAN_RESET_CONTROL_COLD_RST_MSB 8 | ||
60 | #define WLAN_RESET_CONTROL_COLD_RST_LSB 8 | ||
61 | #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000100 | ||
62 | #define WLAN_RESET_CONTROL_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB) | ||
63 | #define WLAN_RESET_CONTROL_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK) | ||
64 | #define WLAN_RESET_CONTROL_WARM_RST_MSB 7 | ||
65 | #define WLAN_RESET_CONTROL_WARM_RST_LSB 7 | ||
66 | #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000080 | ||
67 | #define WLAN_RESET_CONTROL_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB) | ||
68 | #define WLAN_RESET_CONTROL_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK) | ||
69 | #define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB 6 | ||
70 | #define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB 6 | ||
71 | #define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 | ||
72 | #define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) | ||
73 | #define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) | ||
74 | #define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB 5 | ||
75 | #define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB 5 | ||
76 | #define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 | ||
77 | #define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) | ||
78 | #define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) | ||
79 | #define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB 4 | ||
80 | #define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB 4 | ||
81 | #define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 | ||
82 | #define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) | ||
83 | #define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) | ||
84 | #define WLAN_RESET_CONTROL_MBOX_RST_MSB 2 | ||
85 | #define WLAN_RESET_CONTROL_MBOX_RST_LSB 2 | ||
86 | #define WLAN_RESET_CONTROL_MBOX_RST_MASK 0x00000004 | ||
87 | #define WLAN_RESET_CONTROL_MBOX_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB) | ||
88 | #define WLAN_RESET_CONTROL_MBOX_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK) | ||
89 | #define WLAN_RESET_CONTROL_UART_RST_MSB 1 | ||
90 | #define WLAN_RESET_CONTROL_UART_RST_LSB 1 | ||
91 | #define WLAN_RESET_CONTROL_UART_RST_MASK 0x00000002 | ||
92 | #define WLAN_RESET_CONTROL_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB) | ||
93 | #define WLAN_RESET_CONTROL_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK) | ||
94 | #define WLAN_RESET_CONTROL_SI0_RST_MSB 0 | ||
95 | #define WLAN_RESET_CONTROL_SI0_RST_LSB 0 | ||
96 | #define WLAN_RESET_CONTROL_SI0_RST_MASK 0x00000001 | ||
97 | #define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB) | ||
98 | #define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK) | ||
99 | |||
100 | #define WLAN_CPU_CLOCK_ADDRESS 0x00000020 | ||
101 | #define WLAN_CPU_CLOCK_OFFSET 0x00000020 | ||
102 | #define WLAN_CPU_CLOCK_STANDARD_MSB 1 | ||
103 | #define WLAN_CPU_CLOCK_STANDARD_LSB 0 | ||
104 | #define WLAN_CPU_CLOCK_STANDARD_MASK 0x00000003 | ||
105 | #define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB) | ||
106 | #define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK) | ||
107 | |||
108 | #define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028 | ||
109 | #define WLAN_CLOCK_CONTROL_OFFSET 0x00000028 | ||
110 | #define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2 | ||
111 | #define WLAN_CLOCK_CONTROL_LF_CLK32_LSB 2 | ||
112 | #define WLAN_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 | ||
113 | #define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB) | ||
114 | #define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) | ||
115 | #define WLAN_CLOCK_CONTROL_SI0_CLK_MSB 0 | ||
116 | #define WLAN_CLOCK_CONTROL_SI0_CLK_LSB 0 | ||
117 | #define WLAN_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 | ||
118 | #define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB) | ||
119 | #define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) | ||
120 | |||
121 | #define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4 | ||
122 | #define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4 | ||
123 | #define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4 | ||
124 | #define WLAN_SYSTEM_SLEEP_HOST_IF_LSB 4 | ||
125 | #define WLAN_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 | ||
126 | #define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB) | ||
127 | #define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) | ||
128 | #define WLAN_SYSTEM_SLEEP_MBOX_MSB 3 | ||
129 | #define WLAN_SYSTEM_SLEEP_MBOX_LSB 3 | ||
130 | #define WLAN_SYSTEM_SLEEP_MBOX_MASK 0x00000008 | ||
131 | #define WLAN_SYSTEM_SLEEP_MBOX_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB) | ||
132 | #define WLAN_SYSTEM_SLEEP_MBOX_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK) | ||
133 | #define WLAN_SYSTEM_SLEEP_MAC_IF_MSB 2 | ||
134 | #define WLAN_SYSTEM_SLEEP_MAC_IF_LSB 2 | ||
135 | #define WLAN_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 | ||
136 | #define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB) | ||
137 | #define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) | ||
138 | #define WLAN_SYSTEM_SLEEP_LIGHT_MSB 1 | ||
139 | #define WLAN_SYSTEM_SLEEP_LIGHT_LSB 1 | ||
140 | #define WLAN_SYSTEM_SLEEP_LIGHT_MASK 0x00000002 | ||
141 | #define WLAN_SYSTEM_SLEEP_LIGHT_GET(x) (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB) | ||
142 | #define WLAN_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) | ||
143 | #define WLAN_SYSTEM_SLEEP_DISABLE_MSB 0 | ||
144 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 | ||
145 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 | ||
146 | #define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB) | ||
147 | #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) | ||
148 | |||
149 | #define WLAN_LPO_CAL_ADDRESS 0x000000e0 | ||
150 | #define WLAN_LPO_CAL_OFFSET 0x000000e0 | ||
151 | #define WLAN_LPO_CAL_ENABLE_MSB 20 | ||
152 | #define WLAN_LPO_CAL_ENABLE_LSB 20 | ||
153 | #define WLAN_LPO_CAL_ENABLE_MASK 0x00100000 | ||
154 | #define WLAN_LPO_CAL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB) | ||
155 | #define WLAN_LPO_CAL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK) | ||
156 | #define WLAN_LPO_CAL_COUNT_MSB 19 | ||
157 | #define WLAN_LPO_CAL_COUNT_LSB 0 | ||
158 | #define WLAN_LPO_CAL_COUNT_MASK 0x000fffff | ||
159 | #define WLAN_LPO_CAL_COUNT_GET(x) (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB) | ||
160 | #define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK) | ||
161 | |||
162 | #endif /* _RTC_WLAN_REG_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h new file mode 100644 index 00000000000..302b20bc1ba --- /dev/null +++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h | |||
@@ -0,0 +1,40 @@ | |||
1 | // ------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // ------------------------------------------------------------------ | ||
19 | //=================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //=================================================================== | ||
22 | |||
23 | |||
24 | #ifndef _UART_REG_REG_H_ | ||
25 | #define _UART_REG_REG_H_ | ||
26 | |||
27 | #define UART_CLKDIV_ADDRESS 0x00000008 | ||
28 | #define UART_CLKDIV_OFFSET 0x00000008 | ||
29 | #define UART_CLKDIV_CLK_SCALE_MSB 23 | ||
30 | #define UART_CLKDIV_CLK_SCALE_LSB 16 | ||
31 | #define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000 | ||
32 | #define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB) | ||
33 | #define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK) | ||
34 | #define UART_CLKDIV_CLK_STEP_MSB 15 | ||
35 | #define UART_CLKDIV_CLK_STEP_LSB 0 | ||
36 | #define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff | ||
37 | #define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB) | ||
38 | #define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK) | ||
39 | |||
40 | #endif /* _UART_REG_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/athdefs.h b/drivers/staging/ath6kl/include/common/athdefs.h new file mode 100644 index 00000000000..74922481e06 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/athdefs.h | |||
@@ -0,0 +1,75 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="athdefs.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | #ifndef __ATHDEFS_H__ | ||
24 | #define __ATHDEFS_H__ | ||
25 | |||
26 | /* | ||
27 | * This file contains definitions that may be used across both | ||
28 | * Host and Target software. Nothing here is module-dependent | ||
29 | * or platform-dependent. | ||
30 | */ | ||
31 | |||
32 | /* | ||
33 | * Generic error codes that can be used by hw, sta, ap, sim, dk | ||
34 | * and any other environments. | ||
35 | * Feel free to add any more non-zero codes that you need. | ||
36 | */ | ||
37 | |||
38 | #define A_ERROR (-1) /* Generic error return */ | ||
39 | #define A_DEVICE_NOT_FOUND 1 /* not able to find PCI device */ | ||
40 | #define A_NO_MEMORY 2 /* not able to allocate memory, | ||
41 | * not avail#defineable */ | ||
42 | #define A_MEMORY_NOT_AVAIL 3 /* memory region is not free for | ||
43 | * mapping */ | ||
44 | #define A_NO_FREE_DESC 4 /* no free descriptors available */ | ||
45 | #define A_BAD_ADDRESS 5 /* address does not match descriptor */ | ||
46 | #define A_WIN_DRIVER_ERROR 6 /* used in NT_HW version, | ||
47 | * if problem at init */ | ||
48 | #define A_REGS_NOT_MAPPED 7 /* registers not correctly mapped */ | ||
49 | #define A_EPERM 8 /* Not superuser */ | ||
50 | #define A_EACCES 0 /* Access denied */ | ||
51 | #define A_ENOENT 10 /* No such entry, search failed, etc. */ | ||
52 | #define A_EEXIST 11 /* The object already exists | ||
53 | * (can't create) */ | ||
54 | #define A_EFAULT 12 /* Bad address fault */ | ||
55 | #define A_EBUSY 13 /* Object is busy */ | ||
56 | #define A_EINVAL 14 /* Invalid parameter */ | ||
57 | #define A_EMSGSIZE 15 /* Bad message buffer length */ | ||
58 | #define A_ECANCELED 16 /* Operation canceled */ | ||
59 | #define A_ENOTSUP 17 /* Operation not supported */ | ||
60 | #define A_ECOMM 18 /* Communication error on send */ | ||
61 | #define A_EPROTO 19 /* Protocol error */ | ||
62 | #define A_ENODEV 20 /* No such device */ | ||
63 | #define A_EDEVNOTUP 21 /* device is not UP */ | ||
64 | #define A_NO_RESOURCE 22 /* No resources for | ||
65 | * requested operation */ | ||
66 | #define A_HARDWARE 23 /* Hardware failure */ | ||
67 | #define A_PENDING 24 /* Asynchronous routine; will send up | ||
68 | * results later | ||
69 | * (typically in callback) */ | ||
70 | #define A_EBADCHANNEL 25 /* The channel cannot be used */ | ||
71 | #define A_DECRYPT_ERROR 26 /* Decryption error */ | ||
72 | #define A_PHY_ERROR 27 /* RX PHY error */ | ||
73 | #define A_CONSUMED 28 /* Object was consumed */ | ||
74 | |||
75 | #endif /* __ATHDEFS_H__ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/bmi_msg.h b/drivers/staging/ath6kl/include/common/bmi_msg.h new file mode 100644 index 00000000000..84e8db569a9 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/bmi_msg.h | |||
@@ -0,0 +1,233 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // | ||
19 | // Author(s): ="Atheros" | ||
20 | //------------------------------------------------------------------------------ | ||
21 | |||
22 | #ifndef __BMI_MSG_H__ | ||
23 | #define __BMI_MSG_H__ | ||
24 | |||
25 | /* | ||
26 | * Bootloader Messaging Interface (BMI) | ||
27 | * | ||
28 | * BMI is a very simple messaging interface used during initialization | ||
29 | * to read memory, write memory, execute code, and to define an | ||
30 | * application entry PC. | ||
31 | * | ||
32 | * It is used to download an application to AR6K, to provide | ||
33 | * patches to code that is already resident on AR6K, and generally | ||
34 | * to examine and modify state. The Host has an opportunity to use | ||
35 | * BMI only once during bootup. Once the Host issues a BMI_DONE | ||
36 | * command, this opportunity ends. | ||
37 | * | ||
38 | * The Host writes BMI requests to mailbox0, and reads BMI responses | ||
39 | * from mailbox0. BMI requests all begin with a command | ||
40 | * (see below for specific commands), and are followed by | ||
41 | * command-specific data. | ||
42 | * | ||
43 | * Flow control: | ||
44 | * The Host can only issue a command once the Target gives it a | ||
45 | * "BMI Command Credit", using AR6K Counter #4. As soon as the | ||
46 | * Target has completed a command, it issues another BMI Command | ||
47 | * Credit (so the Host can issue the next command). | ||
48 | * | ||
49 | * BMI handles all required Target-side cache flushing. | ||
50 | */ | ||
51 | |||
52 | |||
53 | /* Maximum data size used for BMI transfers */ | ||
54 | #define BMI_DATASZ_MAX 256 | ||
55 | |||
56 | /* BMI Commands */ | ||
57 | |||
58 | #define BMI_NO_COMMAND 0 | ||
59 | |||
60 | #define BMI_DONE 1 | ||
61 | /* | ||
62 | * Semantics: Host is done using BMI | ||
63 | * Request format: | ||
64 | * u32 command (BMI_DONE) | ||
65 | * Response format: none | ||
66 | */ | ||
67 | |||
68 | #define BMI_READ_MEMORY 2 | ||
69 | /* | ||
70 | * Semantics: Host reads AR6K memory | ||
71 | * Request format: | ||
72 | * u32 command (BMI_READ_MEMORY) | ||
73 | * u32 address | ||
74 | * u32 length, at most BMI_DATASZ_MAX | ||
75 | * Response format: | ||
76 | * u8 data[length] | ||
77 | */ | ||
78 | |||
79 | #define BMI_WRITE_MEMORY 3 | ||
80 | /* | ||
81 | * Semantics: Host writes AR6K memory | ||
82 | * Request format: | ||
83 | * u32 command (BMI_WRITE_MEMORY) | ||
84 | * u32 address | ||
85 | * u32 length, at most BMI_DATASZ_MAX | ||
86 | * u8 data[length] | ||
87 | * Response format: none | ||
88 | */ | ||
89 | |||
90 | #define BMI_EXECUTE 4 | ||
91 | /* | ||
92 | * Semantics: Causes AR6K to execute code | ||
93 | * Request format: | ||
94 | * u32 command (BMI_EXECUTE) | ||
95 | * u32 address | ||
96 | * u32 parameter | ||
97 | * Response format: | ||
98 | * u32 return value | ||
99 | */ | ||
100 | |||
101 | #define BMI_SET_APP_START 5 | ||
102 | /* | ||
103 | * Semantics: Set Target application starting address | ||
104 | * Request format: | ||
105 | * u32 command (BMI_SET_APP_START) | ||
106 | * u32 address | ||
107 | * Response format: none | ||
108 | */ | ||
109 | |||
110 | #define BMI_READ_SOC_REGISTER 6 | ||
111 | /* | ||
112 | * Semantics: Read a 32-bit Target SOC register. | ||
113 | * Request format: | ||
114 | * u32 command (BMI_READ_REGISTER) | ||
115 | * u32 address | ||
116 | * Response format: | ||
117 | * u32 value | ||
118 | */ | ||
119 | |||
120 | #define BMI_WRITE_SOC_REGISTER 7 | ||
121 | /* | ||
122 | * Semantics: Write a 32-bit Target SOC register. | ||
123 | * Request format: | ||
124 | * u32 command (BMI_WRITE_REGISTER) | ||
125 | * u32 address | ||
126 | * u32 value | ||
127 | * | ||
128 | * Response format: none | ||
129 | */ | ||
130 | |||
131 | #define BMI_GET_TARGET_ID 8 | ||
132 | #define BMI_GET_TARGET_INFO 8 | ||
133 | /* | ||
134 | * Semantics: Fetch the 4-byte Target information | ||
135 | * Request format: | ||
136 | * u32 command (BMI_GET_TARGET_ID/INFO) | ||
137 | * Response format1 (old firmware): | ||
138 | * u32 TargetVersionID | ||
139 | * Response format2 (newer firmware): | ||
140 | * u32 TARGET_VERSION_SENTINAL | ||
141 | * struct bmi_target_info; | ||
142 | */ | ||
143 | |||
144 | PREPACK struct bmi_target_info { | ||
145 | u32 target_info_byte_count; /* size of this structure */ | ||
146 | u32 target_ver; /* Target Version ID */ | ||
147 | u32 target_type; /* Target type */ | ||
148 | } POSTPACK; | ||
149 | #define TARGET_VERSION_SENTINAL 0xffffffff | ||
150 | #define TARGET_TYPE_AR6001 1 | ||
151 | #define TARGET_TYPE_AR6002 2 | ||
152 | #define TARGET_TYPE_AR6003 3 | ||
153 | |||
154 | |||
155 | #define BMI_ROMPATCH_INSTALL 9 | ||
156 | /* | ||
157 | * Semantics: Install a ROM Patch. | ||
158 | * Request format: | ||
159 | * u32 command (BMI_ROMPATCH_INSTALL) | ||
160 | * u32 Target ROM Address | ||
161 | * u32 Target RAM Address or Value (depending on Target Type) | ||
162 | * u32 Size, in bytes | ||
163 | * u32 Activate? 1-->activate; | ||
164 | * 0-->install but do not activate | ||
165 | * Response format: | ||
166 | * u32 PatchID | ||
167 | */ | ||
168 | |||
169 | #define BMI_ROMPATCH_UNINSTALL 10 | ||
170 | /* | ||
171 | * Semantics: Uninstall a previously-installed ROM Patch, | ||
172 | * automatically deactivating, if necessary. | ||
173 | * Request format: | ||
174 | * u32 command (BMI_ROMPATCH_UNINSTALL) | ||
175 | * u32 PatchID | ||
176 | * | ||
177 | * Response format: none | ||
178 | */ | ||
179 | |||
180 | #define BMI_ROMPATCH_ACTIVATE 11 | ||
181 | /* | ||
182 | * Semantics: Activate a list of previously-installed ROM Patches. | ||
183 | * Request format: | ||
184 | * u32 command (BMI_ROMPATCH_ACTIVATE) | ||
185 | * u32 rompatch_count | ||
186 | * u32 PatchID[rompatch_count] | ||
187 | * | ||
188 | * Response format: none | ||
189 | */ | ||
190 | |||
191 | #define BMI_ROMPATCH_DEACTIVATE 12 | ||
192 | /* | ||
193 | * Semantics: Deactivate a list of active ROM Patches. | ||
194 | * Request format: | ||
195 | * u32 command (BMI_ROMPATCH_DEACTIVATE) | ||
196 | * u32 rompatch_count | ||
197 | * u32 PatchID[rompatch_count] | ||
198 | * | ||
199 | * Response format: none | ||
200 | */ | ||
201 | |||
202 | |||
203 | #define BMI_LZ_STREAM_START 13 | ||
204 | /* | ||
205 | * Semantics: Begin an LZ-compressed stream of input | ||
206 | * which is to be uncompressed by the Target to an | ||
207 | * output buffer at address. The output buffer must | ||
208 | * be sufficiently large to hold the uncompressed | ||
209 | * output from the compressed input stream. This BMI | ||
210 | * command should be followed by a series of 1 or more | ||
211 | * BMI_LZ_DATA commands. | ||
212 | * u32 command (BMI_LZ_STREAM_START) | ||
213 | * u32 address | ||
214 | * Note: Not supported on all versions of ROM firmware. | ||
215 | */ | ||
216 | |||
217 | #define BMI_LZ_DATA 14 | ||
218 | /* | ||
219 | * Semantics: Host writes AR6K memory with LZ-compressed | ||
220 | * data which is uncompressed by the Target. This command | ||
221 | * must be preceded by a BMI_LZ_STREAM_START command. A series | ||
222 | * of BMI_LZ_DATA commands are considered part of a single | ||
223 | * input stream until another BMI_LZ_STREAM_START is issued. | ||
224 | * Request format: | ||
225 | * u32 command (BMI_LZ_DATA) | ||
226 | * u32 length (of compressed data), | ||
227 | * at most BMI_DATASZ_MAX | ||
228 | * u8 CompressedData[length] | ||
229 | * Response format: none | ||
230 | * Note: Not supported on all versions of ROM firmware. | ||
231 | */ | ||
232 | |||
233 | #endif /* __BMI_MSG_H__ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/cnxmgmt.h b/drivers/staging/ath6kl/include/common/cnxmgmt.h new file mode 100644 index 00000000000..7a902cb5483 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/cnxmgmt.h | |||
@@ -0,0 +1,36 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="cnxmgmt.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef _CNXMGMT_H_ | ||
25 | #define _CNXMGMT_H_ | ||
26 | |||
27 | typedef enum { | ||
28 | CM_CONNECT_WITHOUT_SCAN = 0x0001, | ||
29 | CM_CONNECT_ASSOC_POLICY_USER = 0x0002, | ||
30 | CM_CONNECT_SEND_REASSOC = 0x0004, | ||
31 | CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008, | ||
32 | CM_CONNECT_DO_WPA_OFFLOAD = 0x0010, | ||
33 | CM_CONNECT_DO_NOT_DEAUTH = 0x0020, | ||
34 | } CM_CONNECT_TYPE; | ||
35 | |||
36 | #endif /* _CNXMGMT_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/dbglog.h b/drivers/staging/ath6kl/include/common/dbglog.h new file mode 100644 index 00000000000..5566e568b83 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/dbglog.h | |||
@@ -0,0 +1,126 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="dbglog.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef _DBGLOG_H_ | ||
25 | #define _DBGLOG_H_ | ||
26 | |||
27 | #ifdef __cplusplus | ||
28 | extern "C" { | ||
29 | #endif | ||
30 | |||
31 | #define DBGLOG_TIMESTAMP_OFFSET 0 | ||
32 | #define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit | ||
33 | 8-23 of the LF0 timer */ | ||
34 | #define DBGLOG_DBGID_OFFSET 16 | ||
35 | #define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ | ||
36 | #define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ | ||
37 | |||
38 | #define DBGLOG_MODULEID_OFFSET 26 | ||
39 | #define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ | ||
40 | #define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ | ||
41 | |||
42 | /* | ||
43 | * Please ensure that the definition of any new module introduced is captured | ||
44 | * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The | ||
45 | * structure is required for the parser to correctly pick up the values for | ||
46 | * different modules. | ||
47 | */ | ||
48 | #define DBGLOG_MODULEID_START | ||
49 | #define DBGLOG_MODULEID_INF 0 | ||
50 | #define DBGLOG_MODULEID_WMI 1 | ||
51 | #define DBGLOG_MODULEID_MISC 2 | ||
52 | #define DBGLOG_MODULEID_PM 3 | ||
53 | #define DBGLOG_MODULEID_TXRX_MGMTBUF 4 | ||
54 | #define DBGLOG_MODULEID_TXRX_TXBUF 5 | ||
55 | #define DBGLOG_MODULEID_TXRX_RXBUF 6 | ||
56 | #define DBGLOG_MODULEID_WOW 7 | ||
57 | #define DBGLOG_MODULEID_WHAL 8 | ||
58 | #define DBGLOG_MODULEID_DC 9 | ||
59 | #define DBGLOG_MODULEID_CO 10 | ||
60 | #define DBGLOG_MODULEID_RO 11 | ||
61 | #define DBGLOG_MODULEID_CM 12 | ||
62 | #define DBGLOG_MODULEID_MGMT 13 | ||
63 | #define DBGLOG_MODULEID_TMR 14 | ||
64 | #define DBGLOG_MODULEID_BTCOEX 15 | ||
65 | #define DBGLOG_MODULEID_END | ||
66 | |||
67 | #define DBGLOG_NUM_ARGS_OFFSET 30 | ||
68 | #define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ | ||
69 | #define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ | ||
70 | |||
71 | #define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 | ||
72 | #define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF | ||
73 | |||
74 | #define DBGLOG_REPORTING_ENABLED_OFFSET 16 | ||
75 | #define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 | ||
76 | |||
77 | #define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 | ||
78 | #define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 | ||
79 | |||
80 | #define DBGLOG_REPORT_SIZE_OFFSET 20 | ||
81 | #define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 | ||
82 | |||
83 | #define DBGLOG_LOG_BUFFER_SIZE 1500 | ||
84 | #define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 | ||
85 | |||
86 | PREPACK struct dbglog_buf_s { | ||
87 | struct dbglog_buf_s *next; | ||
88 | u8 *buffer; | ||
89 | u32 bufsize; | ||
90 | u32 length; | ||
91 | u32 count; | ||
92 | u32 free; | ||
93 | } POSTPACK; | ||
94 | |||
95 | PREPACK struct dbglog_hdr_s { | ||
96 | struct dbglog_buf_s *dbuf; | ||
97 | u32 dropped; | ||
98 | } POSTPACK; | ||
99 | |||
100 | PREPACK struct dbglog_config_s { | ||
101 | u32 cfgvalid; /* Mask with valid config bits */ | ||
102 | union { | ||
103 | /* TODO: Take care of endianness */ | ||
104 | struct { | ||
105 | u32 mmask:16; /* Mask of modules with logging on */ | ||
106 | u32 rep:1; /* Reporting enabled or not */ | ||
107 | u32 tsr:3; /* Time stamp resolution. Def: 1 ms */ | ||
108 | u32 size:10; /* Report size in number of messages */ | ||
109 | u32 reserved:2; | ||
110 | } dbglog_config; | ||
111 | |||
112 | u32 value; | ||
113 | } u; | ||
114 | } POSTPACK; | ||
115 | |||
116 | #define cfgmmask u.dbglog_config.mmask | ||
117 | #define cfgrep u.dbglog_config.rep | ||
118 | #define cfgtsr u.dbglog_config.tsr | ||
119 | #define cfgsize u.dbglog_config.size | ||
120 | #define cfgvalue u.value | ||
121 | |||
122 | #ifdef __cplusplus | ||
123 | } | ||
124 | #endif | ||
125 | |||
126 | #endif /* _DBGLOG_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/dbglog_id.h b/drivers/staging/ath6kl/include/common/dbglog_id.h new file mode 100644 index 00000000000..15ef829cab2 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/dbglog_id.h | |||
@@ -0,0 +1,558 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="dbglog_id.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef _DBGLOG_ID_H_ | ||
25 | #define _DBGLOG_ID_H_ | ||
26 | |||
27 | #ifdef __cplusplus | ||
28 | extern "C" { | ||
29 | #endif | ||
30 | |||
31 | /* | ||
32 | * The nomenclature for the debug identifiers is MODULE_DESCRIPTION. | ||
33 | * Please ensure that the definition of any new debugid introduced is captured | ||
34 | * between the <MODULE>_DBGID_DEFINITION_START and | ||
35 | * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the | ||
36 | * parser to correctly pick up the values for different debug identifiers. | ||
37 | */ | ||
38 | |||
39 | /* INF debug identifier definitions */ | ||
40 | #define INF_DBGID_DEFINITION_START | ||
41 | #define INF_ASSERTION_FAILED 1 | ||
42 | #define INF_TARGET_ID 2 | ||
43 | #define INF_DBGID_DEFINITION_END | ||
44 | |||
45 | /* WMI debug identifier definitions */ | ||
46 | #define WMI_DBGID_DEFINITION_START | ||
47 | #define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1 | ||
48 | #define WMI_EXTENDED_CMD_NOT_HANDLED 2 | ||
49 | #define WMI_CMD_RX_PKT_TOO_SHORT 3 | ||
50 | #define WMI_CALLING_WMI_EXTENSION_FN 4 | ||
51 | #define WMI_CMD_NOT_HANDLED 5 | ||
52 | #define WMI_IN_SYNC 6 | ||
53 | #define WMI_TARGET_WMI_SYNC_CMD 7 | ||
54 | #define WMI_SET_SNR_THRESHOLD_PARAMS 8 | ||
55 | #define WMI_SET_RSSI_THRESHOLD_PARAMS 9 | ||
56 | #define WMI_SET_LQ_TRESHOLD_PARAMS 10 | ||
57 | #define WMI_TARGET_CREATE_PSTREAM_CMD 11 | ||
58 | #define WMI_WI_DTM_INUSE 12 | ||
59 | #define WMI_TARGET_DELETE_PSTREAM_CMD 13 | ||
60 | #define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14 | ||
61 | #define WMI_TARGET_GET_BIT_RATE_CMD 15 | ||
62 | #define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16 | ||
63 | #define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17 | ||
64 | #define WMI_TARGET_GET_TX_PWR_CMD 18 | ||
65 | #define WMI_FREE_EVBUF_WMIBUF 19 | ||
66 | #define WMI_FREE_EVBUF_DATABUF 20 | ||
67 | #define WMI_FREE_EVBUF_BADFLAG 21 | ||
68 | #define WMI_HTC_RX_ERROR_DATA_PACKET 22 | ||
69 | #define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23 | ||
70 | #define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24 | ||
71 | #define WMI_SENDING_READY_EVENT 25 | ||
72 | #define WMI_SETPOWER_MDOE_TO_MAXPERF 26 | ||
73 | #define WMI_SETPOWER_MDOE_TO_REC 27 | ||
74 | #define WMI_BSSINFO_EVENT_FROM 28 | ||
75 | #define WMI_TARGET_GET_STATS_CMD 29 | ||
76 | #define WMI_SENDING_SCAN_COMPLETE_EVENT 30 | ||
77 | #define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31 | ||
78 | #define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32 | ||
79 | #define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33 | ||
80 | #define WMI_SENDING_ERROR_REPORT_EVENT 34 | ||
81 | #define WMI_SENDING_CAC_EVENT 35 | ||
82 | #define WMI_TARGET_GET_ROAM_TABLE_CMD 36 | ||
83 | #define WMI_TARGET_GET_ROAM_DATA_CMD 37 | ||
84 | #define WMI_SENDING_GPIO_INTR_EVENT 38 | ||
85 | #define WMI_SENDING_GPIO_ACK_EVENT 39 | ||
86 | #define WMI_SENDING_GPIO_DATA_EVENT 40 | ||
87 | #define WMI_CMD_RX 41 | ||
88 | #define WMI_CMD_RX_XTND 42 | ||
89 | #define WMI_EVENT_SEND 43 | ||
90 | #define WMI_EVENT_SEND_XTND 44 | ||
91 | #define WMI_CMD_PARAMS_DUMP_START 45 | ||
92 | #define WMI_CMD_PARAMS_DUMP_END 46 | ||
93 | #define WMI_CMD_PARAMS 47 | ||
94 | #define WMI_DBGID_DEFINITION_END | ||
95 | |||
96 | /* MISC debug identifier definitions */ | ||
97 | #define MISC_DBGID_DEFINITION_START | ||
98 | #define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1 | ||
99 | #define TLPM_INIT 2 | ||
100 | #define TLPM_FILTER_POWER_STATE 3 | ||
101 | #define TLPM_NOTIFY_NOT_IDLE 4 | ||
102 | #define TLPM_TIMEOUT_IDLE_HANDLER 5 | ||
103 | #define TLPM_TIMEOUT_WAKEUP_HANDLER 6 | ||
104 | #define TLPM_WAKEUP_SIGNAL_HANDLER 7 | ||
105 | #define TLPM_UNEXPECTED_GPIO_INTR_ERROR 8 | ||
106 | #define TLPM_BREAK_ON_NOT_RECEIVED_ERROR 9 | ||
107 | #define TLPM_BREAK_OFF_NOT_RECIVED_ERROR 10 | ||
108 | #define TLPM_ACK_GPIO_INTR 11 | ||
109 | #define TLPM_ON 12 | ||
110 | #define TLPM_OFF 13 | ||
111 | #define TLPM_WAKEUP_FROM_HOST 14 | ||
112 | #define TLPM_WAKEUP_FROM_BT 15 | ||
113 | #define TLPM_TX_BREAK_RECIVED 16 | ||
114 | #define TLPM_IDLE_TIMER_NOT_RUNNING 17 | ||
115 | #define MISC_DBGID_DEFINITION_END | ||
116 | |||
117 | /* TXRX debug identifier definitions */ | ||
118 | #define TXRX_TXBUF_DBGID_DEFINITION_START | ||
119 | #define TXRX_TXBUF_ALLOCATE_BUF 1 | ||
120 | #define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2 | ||
121 | #define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3 | ||
122 | #define TXRX_TXBUF_TXQ_DEPTH 4 | ||
123 | #define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5 | ||
124 | #define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6 | ||
125 | #define TXRX_TXBUF_INITIALIZE_TIMER 7 | ||
126 | #define TXRX_TXBUF_ARM_TIMER 8 | ||
127 | #define TXRX_TXBUF_DISARM_TIMER 9 | ||
128 | #define TXRX_TXBUF_UNINITIALIZE_TIMER 10 | ||
129 | #define TXRX_TXBUF_DBGID_DEFINITION_END | ||
130 | |||
131 | #define TXRX_RXBUF_DBGID_DEFINITION_START | ||
132 | #define TXRX_RXBUF_ALLOCATE_BUF 1 | ||
133 | #define TXRX_RXBUF_QUEUE_TO_HOST 2 | ||
134 | #define TXRX_RXBUF_QUEUE_TO_WLAN 3 | ||
135 | #define TXRX_RXBUF_ZERO_LEN_BUF 4 | ||
136 | #define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5 | ||
137 | #define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6 | ||
138 | #define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7 | ||
139 | #define TXRX_RXBUF_SEND_TO_RECV_MGMT 8 | ||
140 | #define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9 | ||
141 | #define TXRX_RXBUF_REQUEUE_ERROR 10 | ||
142 | #define TXRX_RXBUF_DBGID_DEFINITION_END | ||
143 | |||
144 | #define TXRX_MGMTBUF_DBGID_DEFINITION_START | ||
145 | #define TXRX_MGMTBUF_ALLOCATE_BUF 1 | ||
146 | #define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2 | ||
147 | #define TXRX_MGMTBUF_ALLOCATE_RMBUF 3 | ||
148 | #define TXRX_MGMTBUF_GET_BUF 4 | ||
149 | #define TXRX_MGMTBUF_GET_SM_BUF 5 | ||
150 | #define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6 | ||
151 | #define TXRX_MGMTBUF_REAPED_BUF 7 | ||
152 | #define TXRX_MGMTBUF_REAPED_SM_BUF 8 | ||
153 | #define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9 | ||
154 | #define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10 | ||
155 | #define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11 | ||
156 | #define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12 | ||
157 | #define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13 | ||
158 | #define TXRX_MGMTBUF_RESUME_DATA_TXQ 14 | ||
159 | #define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15 | ||
160 | #define TXRX_MGMTBUF_DRAINQ 16 | ||
161 | #define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17 | ||
162 | #define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18 | ||
163 | #define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19 | ||
164 | #define TXRX_MGMTBUF_PAUSE_HW_TXQ 20 | ||
165 | #define TXRX_MGMTBUF_RESUME_HW_TXQ 21 | ||
166 | #define TXRX_MGMTBUF_TEAR_DOWN_BA 22 | ||
167 | #define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23 | ||
168 | #define TXRX_MGMTBUF_PROCESS_DELBA 24 | ||
169 | #define TXRX_MGMTBUF_PERFORM_BA 25 | ||
170 | #define TXRX_MGMTBUF_WLAN_RESET_ON_ERROR 26 | ||
171 | #define TXRX_MGMTBUF_DBGID_DEFINITION_END | ||
172 | |||
173 | /* PM (Power Module) debug identifier definitions */ | ||
174 | #define PM_DBGID_DEFINITION_START | ||
175 | #define PM_INIT 1 | ||
176 | #define PM_ENABLE 2 | ||
177 | #define PM_SET_STATE 3 | ||
178 | #define PM_SET_POWERMODE 4 | ||
179 | #define PM_CONN_NOTIFY 5 | ||
180 | #define PM_REF_COUNT_NEGATIVE 6 | ||
181 | #define PM_INFRA_STA_APSD_ENABLE 7 | ||
182 | #define PM_INFRA_STA_UPDATE_APSD_STATE 8 | ||
183 | #define PM_CHAN_OP_REQ 9 | ||
184 | #define PM_SET_MY_BEACON_POLICY 10 | ||
185 | #define PM_SET_ALL_BEACON_POLICY 11 | ||
186 | #define PM_INFRA_STA_SET_PM_PARAMS1 12 | ||
187 | #define PM_INFRA_STA_SET_PM_PARAMS2 13 | ||
188 | #define PM_ADHOC_SET_PM_CAPS_FAIL 14 | ||
189 | #define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15 | ||
190 | #define PM_ADHOC_SET_PM_PARAMS 16 | ||
191 | #define PM_ADHOC_STATE1 18 | ||
192 | #define PM_ADHOC_STATE2 19 | ||
193 | #define PM_ADHOC_CONN_MAP 20 | ||
194 | #define PM_FAKE_SLEEP 21 | ||
195 | #define PM_AP_STATE1 22 | ||
196 | #define PM_AP_SET_PM_PARAMS 23 | ||
197 | #define PM_DBGID_DEFINITION_END | ||
198 | |||
199 | /* Wake on Wireless debug identifier definitions */ | ||
200 | #define WOW_DBGID_DEFINITION_START | ||
201 | #define WOW_INIT 1 | ||
202 | #define WOW_GET_CONFIG_DSET 2 | ||
203 | #define WOW_NO_CONFIG_DSET 3 | ||
204 | #define WOW_INVALID_CONFIG_DSET 4 | ||
205 | #define WOW_USE_DEFAULT_CONFIG 5 | ||
206 | #define WOW_SETUP_GPIO 6 | ||
207 | #define WOW_INIT_DONE 7 | ||
208 | #define WOW_SET_GPIO_PIN 8 | ||
209 | #define WOW_CLEAR_GPIO_PIN 9 | ||
210 | #define WOW_SET_WOW_MODE_CMD 10 | ||
211 | #define WOW_SET_HOST_MODE_CMD 11 | ||
212 | #define WOW_ADD_WOW_PATTERN_CMD 12 | ||
213 | #define WOW_NEW_WOW_PATTERN_AT_INDEX 13 | ||
214 | #define WOW_DEL_WOW_PATTERN_CMD 14 | ||
215 | #define WOW_LIST_CONTAINS_PATTERNS 15 | ||
216 | #define WOW_GET_WOW_LIST_CMD 16 | ||
217 | #define WOW_INVALID_FILTER_ID 17 | ||
218 | #define WOW_INVALID_FILTER_LISTID 18 | ||
219 | #define WOW_NO_VALID_FILTER_AT_ID 19 | ||
220 | #define WOW_NO_VALID_LIST_AT_ID 20 | ||
221 | #define WOW_NUM_PATTERNS_EXCEEDED 21 | ||
222 | #define WOW_NUM_LISTS_EXCEEDED 22 | ||
223 | #define WOW_GET_WOW_STATS 23 | ||
224 | #define WOW_CLEAR_WOW_STATS 24 | ||
225 | #define WOW_WAKEUP_HOST 25 | ||
226 | #define WOW_EVENT_WAKEUP_HOST 26 | ||
227 | #define WOW_EVENT_DISCARD 27 | ||
228 | #define WOW_PATTERN_MATCH 28 | ||
229 | #define WOW_PATTERN_NOT_MATCH 29 | ||
230 | #define WOW_PATTERN_NOT_MATCH_OFFSET 30 | ||
231 | #define WOW_DISABLED_HOST_ASLEEP 31 | ||
232 | #define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32 | ||
233 | #define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33 | ||
234 | #define WOW_DBGID_DEFINITION_END | ||
235 | |||
236 | /* WHAL debug identifier definitions */ | ||
237 | #define WHAL_DBGID_DEFINITION_START | ||
238 | #define WHAL_ERROR_ANI_CONTROL 1 | ||
239 | #define WHAL_ERROR_CHIP_TEST1 2 | ||
240 | #define WHAL_ERROR_CHIP_TEST2 3 | ||
241 | #define WHAL_ERROR_EEPROM_CHECKSUM 4 | ||
242 | #define WHAL_ERROR_EEPROM_MACADDR 5 | ||
243 | #define WHAL_ERROR_INTERRUPT_HIU 6 | ||
244 | #define WHAL_ERROR_KEYCACHE_RESET 7 | ||
245 | #define WHAL_ERROR_KEYCACHE_SET 8 | ||
246 | #define WHAL_ERROR_KEYCACHE_TYPE 9 | ||
247 | #define WHAL_ERROR_KEYCACHE_TKIPENTRY 10 | ||
248 | #define WHAL_ERROR_KEYCACHE_WEPLENGTH 11 | ||
249 | #define WHAL_ERROR_PHY_INVALID_CHANNEL 12 | ||
250 | #define WHAL_ERROR_POWER_AWAKE 13 | ||
251 | #define WHAL_ERROR_POWER_SET 14 | ||
252 | #define WHAL_ERROR_RECV_STOPDMA 15 | ||
253 | #define WHAL_ERROR_RECV_STOPPCU 16 | ||
254 | #define WHAL_ERROR_RESET_CHANNF1 17 | ||
255 | #define WHAL_ERROR_RESET_CHANNF2 18 | ||
256 | #define WHAL_ERROR_RESET_PM 19 | ||
257 | #define WHAL_ERROR_RESET_OFFSETCAL 20 | ||
258 | #define WHAL_ERROR_RESET_RFGRANT 21 | ||
259 | #define WHAL_ERROR_RESET_RXFRAME 22 | ||
260 | #define WHAL_ERROR_RESET_STOPDMA 23 | ||
261 | #define WHAL_ERROR_RESET_RECOVER 24 | ||
262 | #define WHAL_ERROR_XMIT_COMPUTE 25 | ||
263 | #define WHAL_ERROR_XMIT_NOQUEUE 26 | ||
264 | #define WHAL_ERROR_XMIT_ACTIVEQUEUE 27 | ||
265 | #define WHAL_ERROR_XMIT_BADTYPE 28 | ||
266 | #define WHAL_ERROR_XMIT_STOPDMA 29 | ||
267 | #define WHAL_ERROR_INTERRUPT_BB_PANIC 30 | ||
268 | #define WHAL_ERROR_RESET_TXIQCAL 31 | ||
269 | #define WHAL_ERROR_PAPRD_MAXGAIN_ABOVE_WINDOW 32 | ||
270 | #define WHAL_DBGID_DEFINITION_END | ||
271 | |||
272 | /* DC debug identifier definitions */ | ||
273 | #define DC_DBGID_DEFINITION_START | ||
274 | #define DC_SCAN_CHAN_START 1 | ||
275 | #define DC_SCAN_CHAN_FINISH 2 | ||
276 | #define DC_BEACON_RECEIVE7 3 | ||
277 | #define DC_SSID_PROBE_CB 4 | ||
278 | #define DC_SEND_NEXT_SSID_PROBE 5 | ||
279 | #define DC_START_SEARCH 6 | ||
280 | #define DC_CANCEL_SEARCH_CB 7 | ||
281 | #define DC_STOP_SEARCH 8 | ||
282 | #define DC_END_SEARCH 9 | ||
283 | #define DC_MIN_CHDWELL_TIMEOUT 10 | ||
284 | #define DC_START_SEARCH_CANCELED 11 | ||
285 | #define DC_SET_POWER_MODE 12 | ||
286 | #define DC_INIT 13 | ||
287 | #define DC_SEARCH_OPPORTUNITY 14 | ||
288 | #define DC_RECEIVED_ANY_BEACON 15 | ||
289 | #define DC_RECEIVED_MY_BEACON 16 | ||
290 | #define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17 | ||
291 | #define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18 | ||
292 | #define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19 | ||
293 | #define DC_SET_BEACON_UPDATE 20 | ||
294 | #define DC_BEACON_UPDATE_COMPLETE 21 | ||
295 | #define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22 | ||
296 | #define DC_BSSINFO_EVENT_DROPPED 23 | ||
297 | #define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24 | ||
298 | #define DC_DBGID_DEFINITION_END | ||
299 | |||
300 | /* CO debug identifier definitions */ | ||
301 | #define CO_DBGID_DEFINITION_START | ||
302 | #define CO_INIT 1 | ||
303 | #define CO_ACQUIRE_LOCK 2 | ||
304 | #define CO_START_OP1 3 | ||
305 | #define CO_START_OP2 4 | ||
306 | #define CO_DRAIN_TX_COMPLETE_CB 5 | ||
307 | #define CO_CHANGE_CHANNEL_CB 6 | ||
308 | #define CO_RETURN_TO_HOME_CHANNEL 7 | ||
309 | #define CO_FINISH_OP_TIMEOUT 8 | ||
310 | #define CO_OP_END 9 | ||
311 | #define CO_CANCEL_OP 10 | ||
312 | #define CO_CHANGE_CHANNEL 11 | ||
313 | #define CO_RELEASE_LOCK 12 | ||
314 | #define CO_CHANGE_STATE 13 | ||
315 | #define CO_DBGID_DEFINITION_END | ||
316 | |||
317 | /* RO debug identifier definitions */ | ||
318 | #define RO_DBGID_DEFINITION_START | ||
319 | #define RO_REFRESH_ROAM_TABLE 1 | ||
320 | #define RO_UPDATE_ROAM_CANDIDATE 2 | ||
321 | #define RO_UPDATE_ROAM_CANDIDATE_CB 3 | ||
322 | #define RO_UPDATE_ROAM_CANDIDATE_FINISH 4 | ||
323 | #define RO_REFRESH_ROAM_TABLE_DONE 5 | ||
324 | #define RO_PERIODIC_SEARCH_CB 6 | ||
325 | #define RO_PERIODIC_SEARCH_TIMEOUT 7 | ||
326 | #define RO_INIT 8 | ||
327 | #define RO_BMISS_STATE1 9 | ||
328 | #define RO_BMISS_STATE2 10 | ||
329 | #define RO_SET_PERIODIC_SEARCH_ENABLE 11 | ||
330 | #define RO_SET_PERIODIC_SEARCH_DISABLE 12 | ||
331 | #define RO_ENABLE_SQ_THRESHOLD 13 | ||
332 | #define RO_DISABLE_SQ_THRESHOLD 14 | ||
333 | #define RO_ADD_BSS_TO_ROAM_TABLE 15 | ||
334 | #define RO_SET_PERIODIC_SEARCH_MODE 16 | ||
335 | #define RO_CONFIGURE_SQ_THRESHOLD1 17 | ||
336 | #define RO_CONFIGURE_SQ_THRESHOLD2 18 | ||
337 | #define RO_CONFIGURE_SQ_PARAMS 19 | ||
338 | #define RO_LOW_SIGNAL_QUALITY_EVENT 20 | ||
339 | #define RO_HIGH_SIGNAL_QUALITY_EVENT 21 | ||
340 | #define RO_REMOVE_BSS_FROM_ROAM_TABLE 22 | ||
341 | #define RO_UPDATE_CONNECTION_STATE_METRIC 23 | ||
342 | #define RO_DBGID_DEFINITION_END | ||
343 | |||
344 | /* CM debug identifier definitions */ | ||
345 | #define CM_DBGID_DEFINITION_START | ||
346 | #define CM_INITIATE_HANDOFF 1 | ||
347 | #define CM_INITIATE_HANDOFF_CB 2 | ||
348 | #define CM_CONNECT_EVENT 3 | ||
349 | #define CM_DISCONNECT_EVENT 4 | ||
350 | #define CM_INIT 5 | ||
351 | #define CM_HANDOFF_SOURCE 6 | ||
352 | #define CM_SET_HANDOFF_TRIGGERS 7 | ||
353 | #define CM_CONNECT_REQUEST 8 | ||
354 | #define CM_CONNECT_REQUEST_CB 9 | ||
355 | #define CM_CONTINUE_SCAN_CB 10 | ||
356 | #define CM_DBGID_DEFINITION_END | ||
357 | |||
358 | |||
359 | /* mgmt debug identifier definitions */ | ||
360 | #define MGMT_DBGID_DEFINITION_START | ||
361 | #define KEYMGMT_CONNECTION_INIT 1 | ||
362 | #define KEYMGMT_CONNECTION_COMPLETE 2 | ||
363 | #define KEYMGMT_CONNECTION_CLOSE 3 | ||
364 | #define KEYMGMT_ADD_KEY 4 | ||
365 | #define MLME_NEW_STATE 5 | ||
366 | #define MLME_CONN_INIT 6 | ||
367 | #define MLME_CONN_COMPLETE 7 | ||
368 | #define MLME_CONN_CLOSE 8 | ||
369 | #define MGMT_DBGID_DEFINITION_END | ||
370 | |||
371 | /* TMR debug identifier definitions */ | ||
372 | #define TMR_DBGID_DEFINITION_START | ||
373 | #define TMR_HANG_DETECTED 1 | ||
374 | #define TMR_WDT_TRIGGERED 2 | ||
375 | #define TMR_WDT_RESET 3 | ||
376 | #define TMR_HANDLER_ENTRY 4 | ||
377 | #define TMR_HANDLER_EXIT 5 | ||
378 | #define TMR_SAVED_START 6 | ||
379 | #define TMR_SAVED_END 7 | ||
380 | #define TMR_DBGID_DEFINITION_END | ||
381 | |||
382 | /* BTCOEX debug identifier definitions */ | ||
383 | #define BTCOEX_DBGID_DEFINITION_START | ||
384 | #define BTCOEX_STATUS_CMD 1 | ||
385 | #define BTCOEX_PARAMS_CMD 2 | ||
386 | #define BTCOEX_ANT_CONFIG 3 | ||
387 | #define BTCOEX_COLOCATED_BT_DEVICE 4 | ||
388 | #define BTCOEX_CLOSE_RANGE_SCO_ON 5 | ||
389 | #define BTCOEX_CLOSE_RANGE_SCO_OFF 6 | ||
390 | #define BTCOEX_CLOSE_RANGE_A2DP_ON 7 | ||
391 | #define BTCOEX_CLOSE_RANGE_A2DP_OFF 8 | ||
392 | #define BTCOEX_A2DP_PROTECT_ON 9 | ||
393 | #define BTCOEX_A2DP_PROTECT_OFF 10 | ||
394 | #define BTCOEX_SCO_PROTECT_ON 11 | ||
395 | #define BTCOEX_SCO_PROTECT_OFF 12 | ||
396 | #define BTCOEX_CLOSE_RANGE_DETECTOR_START 13 | ||
397 | #define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14 | ||
398 | #define BTCOEX_CLOSE_RANGE_TOGGLE 15 | ||
399 | #define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16 | ||
400 | #define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17 | ||
401 | #define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18 | ||
402 | #define BTCOEX_PTA_PRI_INTR_HANDLER 19 | ||
403 | #define BTCOEX_PSPOLL_QUEUED 20 | ||
404 | #define BTCOEX_PSPOLL_COMPLETE 21 | ||
405 | #define BTCOEX_DBG_PM_AWAKE 22 | ||
406 | #define BTCOEX_DBG_PM_SLEEP 23 | ||
407 | #define BTCOEX_DBG_SCO_COEX_ON 24 | ||
408 | #define BTCOEX_SCO_DATARECEIVE 25 | ||
409 | #define BTCOEX_INTR_INIT 26 | ||
410 | #define BTCOEX_PTA_PRI_DIFF 27 | ||
411 | #define BTCOEX_TIM_NOTIFICATION 28 | ||
412 | #define BTCOEX_SCO_WAKEUP_ON_DATA 29 | ||
413 | #define BTCOEX_SCO_SLEEP 30 | ||
414 | #define BTCOEX_SET_WEIGHTS 31 | ||
415 | #define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32 | ||
416 | #define BTCOEX_SCO_MEASURE_TIME_DIFF 33 | ||
417 | #define BTCOEX_SET_EOL_VAL 34 | ||
418 | #define BTCOEX_OPT_DETECT_HANDLER 35 | ||
419 | #define BTCOEX_SCO_TOGGLE_STATE 36 | ||
420 | #define BTCOEX_SCO_STOMP 37 | ||
421 | #define BTCOEX_NULL_COMP_CALLBACK 38 | ||
422 | #define BTCOEX_RX_INCOMING 39 | ||
423 | #define BTCOEX_RX_INCOMING_CTL 40 | ||
424 | #define BTCOEX_RX_INCOMING_MGMT 41 | ||
425 | #define BTCOEX_RX_INCOMING_DATA 42 | ||
426 | #define BTCOEX_RTS_RECEPTION 43 | ||
427 | #define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44 | ||
428 | #define BTCOEX_PM_FAKE_SLEEP 45 | ||
429 | #define BTCOEX_ACL_COEX_STATUS 46 | ||
430 | #define BTCOEX_ACL_COEX_DETECTION 47 | ||
431 | #define BTCOEX_A2DP_COEX_STATUS 48 | ||
432 | #define BTCOEX_SCO_STATUS 49 | ||
433 | #define BTCOEX_WAKEUP_ON_DATA 50 | ||
434 | #define BTCOEX_DATARECEIVE 51 | ||
435 | #define BTCOEX_GET_MAX_AGGR_SIZE 53 | ||
436 | #define BTCOEX_MAX_AGGR_AVAIL_TIME 54 | ||
437 | #define BTCOEX_DBG_WBTIMER_INTR 55 | ||
438 | #define BTCOEX_DBG_SCO_SYNC 57 | ||
439 | #define BTCOEX_UPLINK_QUEUED_RATE 59 | ||
440 | #define BTCOEX_DBG_UPLINK_ENABLE_EOL 60 | ||
441 | #define BTCOEX_UPLINK_FRAME_DURATION 61 | ||
442 | #define BTCOEX_UPLINK_SET_EOL 62 | ||
443 | #define BTCOEX_DBG_EOL_EXPIRED 63 | ||
444 | #define BTCOEX_DBG_DATA_COMPLETE 64 | ||
445 | #define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65 | ||
446 | #define BTCOEX_DBG_DATA_COMPLETE_TIME 66 | ||
447 | #define BTCOEX_DBG_A2DP_ROLE_IS_SLAVE 67 | ||
448 | #define BTCOEX_DBG_A2DP_ROLE_IS_MASTER 68 | ||
449 | #define BTCOEX_DBG_UPLINK_SEQ_NUM 69 | ||
450 | #define BTCOEX_UPLINK_AGGR_SEQ 70 | ||
451 | #define BTCOEX_DBG_TX_COMP_SEQ_NO 71 | ||
452 | #define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72 | ||
453 | #define BTCOEX_DBG_ACL_TRAFFIC 73 | ||
454 | #define BTCOEX_CURR_AGGR_PROP 74 | ||
455 | #define BTCOEX_DBG_SCO_GET_PER_TIME_DIFF 75 | ||
456 | #define BTCOEX_PSPOLL_PROCESS 76 | ||
457 | #define BTCOEX_RETURN_FROM_MAC 77 | ||
458 | #define BTCOEX_FREED_REQUEUED_CNT 78 | ||
459 | #define BTCOEX_DBG_TOGGLE_LOW_RATES 79 | ||
460 | #define BTCOEX_MAC_GOES_TO_SLEEP 80 | ||
461 | #define BTCOEX_DBG_A2DP_NO_SYNC 81 | ||
462 | #define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82 | ||
463 | #define BTCOEX_RETURN_FROM_MAC_AC 83 | ||
464 | #define BTCOEX_DBG_DTIM_RECV 84 | ||
465 | #define BTCOEX_IS_PRE_UPDATE 86 | ||
466 | #define BTCOEX_ENQUEUED_BIT_MAP 87 | ||
467 | #define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88 | ||
468 | #define BTCOEX_UPLINK_DESC 89 | ||
469 | #define BTCOEX_SCO_GET_PER_FIRST_FRM_TIMESTAMP 90 | ||
470 | #define BTCOEX_DBG_RECV_ACK 94 | ||
471 | #define BTCOEX_DBG_ADDBA_INDICATION 95 | ||
472 | #define BTCOEX_TX_COMPLETE_EOL_FAILED 96 | ||
473 | #define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97 | ||
474 | #define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98 | ||
475 | #define BTCOEX_DBG_A2DP_SYNC_INTR 99 | ||
476 | #define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100 | ||
477 | #define BTCOEX_FORM_AGGR_CURR_AGGR 101 | ||
478 | #define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102 | ||
479 | #define BTCOEX_DBG_BT_TRAFFIC 103 | ||
480 | #define BTCOEX_DBG_STOMP_BT_TRAFFIC 104 | ||
481 | #define BTCOEX_RECV_NULL 105 | ||
482 | #define BTCOEX_DBG_A2DP_MASTER_BT_END 106 | ||
483 | #define BTCOEX_DBG_A2DP_BT_START 107 | ||
484 | #define BTCOEX_DBG_A2DP_SLAVE_BT_END 108 | ||
485 | #define BTCOEX_DBG_A2DP_STOMP_BT 109 | ||
486 | #define BTCOEX_DBG_GO_TO_SLEEP 110 | ||
487 | #define BTCOEX_DBG_A2DP_PKT 111 | ||
488 | #define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112 | ||
489 | #define BTCOEX_DBG_A2DP_NULL 113 | ||
490 | #define BTCOEX_DBG_UPLINK_DATA 114 | ||
491 | #define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115 | ||
492 | #define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116 | ||
493 | #define BTCOEX_DBG_TXQ_STATE 117 | ||
494 | #define BTCOEX_DBG_ALLOW_SCAN 118 | ||
495 | #define BTCOEX_DBG_SCAN_REQUEST 119 | ||
496 | #define BTCOEX_A2DP_SLEEP 127 | ||
497 | #define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128 | ||
498 | #define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129 | ||
499 | #define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130 | ||
500 | #define BTCOEX_DATARECEIVE_AGGR 131 | ||
501 | #define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132 | ||
502 | #define BTCOEX_DBG_DATARESP_TIMEOUT 133 | ||
503 | #define BTCOEX_BDG_BMISS 134 | ||
504 | #define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135 | ||
505 | #define BTCOEX_DBG_SECOND_BMISS 136 | ||
506 | #define BTCOEX_DBG_SET_WLAN_STATE 138 | ||
507 | #define BTCOEX_BDG_FIRST_BMISS 139 | ||
508 | #define BTCOEX_DBG_A2DP_CHAN_OP 140 | ||
509 | #define BTCOEX_DBG_A2DP_INTR 141 | ||
510 | #define BTCOEX_DBG_BT_INQUIRY 142 | ||
511 | #define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143 | ||
512 | #define BTCOEX_DBG_POST_INQUIRY_FINISH 144 | ||
513 | #define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145 | ||
514 | #define BTCOEX_DBG_NULL_FRAME_SLEEP 146 | ||
515 | #define BTCOEX_DBG_NULL_FRAME_AWAKE 147 | ||
516 | #define BTCOEX_DBG_SET_AGGR_SIZE 152 | ||
517 | #define BTCOEX_DBG_TEAR_BA_TIMEOUT 153 | ||
518 | #define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154 | ||
519 | #define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155 | ||
520 | #define BTCOEX_DBG_COLOCATED_BT_DEV 156 | ||
521 | #define BTCOEX_DBG_FE_ANT_TYPE 157 | ||
522 | #define BTCOEX_DBG_BT_INQUIRY_CMD 158 | ||
523 | #define BTCOEX_DBG_SCO_CONFIG 159 | ||
524 | #define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160 | ||
525 | #define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161 | ||
526 | #define BTCOEX_DBG_A2DP_CONFIG 162 | ||
527 | #define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163 | ||
528 | #define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164 | ||
529 | #define BTCOEX_DBG_ACLCOEX_CONFIG 165 | ||
530 | #define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166 | ||
531 | #define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167 | ||
532 | #define BTCOEX_DBG_DEBUG_CMD 168 | ||
533 | #define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169 | ||
534 | #define BTCOEX_DBG_GET_CONFIG 170 | ||
535 | #define BTCOEX_DBG_GET_STATS 171 | ||
536 | #define BTCOEX_DBG_BT_OPERATING_STATUS 172 | ||
537 | #define BTCOEX_DBG_PERFORM_RECONNECT 173 | ||
538 | #define BTCOEX_DBG_ACL_WLAN_MED 175 | ||
539 | #define BTCOEX_DBG_ACL_BT_MED 176 | ||
540 | #define BTCOEX_DBG_WLAN_CONNECT 177 | ||
541 | #define BTCOEX_DBG_A2DP_DUAL_START 178 | ||
542 | #define BTCOEX_DBG_PMAWAKE_NOTIFY 179 | ||
543 | #define BTCOEX_DBG_BEACON_SCAN_ENABLE 180 | ||
544 | #define BTCOEX_DBG_BEACON_SCAN_DISABLE 181 | ||
545 | #define BTCOEX_DBG_RX_NOTIFY 182 | ||
546 | #define BTCOEX_SCO_GET_PER_SECOND_FRM_TIMESTAMP 183 | ||
547 | #define BTCOEX_DBG_TXQ_DETAILS 184 | ||
548 | #define BTCOEX_DBG_SCO_STOMP_LOW_PRI 185 | ||
549 | #define BTCOEX_DBG_A2DP_FORCE_SCAN 186 | ||
550 | #define BTCOEX_DBG_DTIM_STOMP_COMP 187 | ||
551 | #define BTCOEX_ACL_PRESENCE_TIMER 188 | ||
552 | #define BTCOEX_DBGID_DEFINITION_END | ||
553 | |||
554 | #ifdef __cplusplus | ||
555 | } | ||
556 | #endif | ||
557 | |||
558 | #endif /* _DBGLOG_ID_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/discovery.h b/drivers/staging/ath6kl/include/common/discovery.h new file mode 100644 index 00000000000..da1b3324506 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/discovery.h | |||
@@ -0,0 +1,75 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="discovery.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef _DISCOVERY_H_ | ||
25 | #define _DISCOVERY_H_ | ||
26 | |||
27 | /* | ||
28 | * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel | ||
29 | */ | ||
30 | typedef enum { | ||
31 | DEFAULT_SCPRI = 0x01, | ||
32 | POPULAR_SCPRI = 0x02, | ||
33 | SSIDS_SCPRI = 0x04, | ||
34 | PROF_SCPRI = 0x08, | ||
35 | } DC_SCAN_PRIORITY; | ||
36 | |||
37 | /* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */ | ||
38 | typedef enum { | ||
39 | SCAN_RESET = 0, | ||
40 | SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \ | ||
41 | SSIDS_SCPRI | PROF_SCPRI), | ||
42 | |||
43 | SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI), | ||
44 | SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI), | ||
45 | SCAN_PROF_MASK = (PROF_SCPRI), | ||
46 | SCAN_MULTI_CHANNEL = 0x000100, | ||
47 | SCAN_DETERMINISTIC = 0x000200, | ||
48 | SCAN_PROFILE_MATCH_TERMINATED = 0x000400, | ||
49 | SCAN_HOME_CHANNEL_SKIP = 0x000800, | ||
50 | SCAN_CHANNEL_LIST_CONTINUE = 0x001000, | ||
51 | SCAN_CURRENT_SSID_SKIP = 0x002000, | ||
52 | SCAN_ACTIVE_PROBE_DISABLE = 0x004000, | ||
53 | SCAN_CHANNEL_HINT_ONLY = 0x008000, | ||
54 | SCAN_ACTIVE_CHANNELS_ONLY = 0x010000, | ||
55 | SCAN_UNUSED1 = 0x020000, /* unused */ | ||
56 | SCAN_PERIODIC = 0x040000, | ||
57 | SCAN_FIXED_DURATION = 0x080000, | ||
58 | SCAN_AP_ASSISTED = 0x100000, | ||
59 | } DC_SCAN_TYPE; | ||
60 | |||
61 | typedef enum { | ||
62 | BSS_REPORTING_DEFAULT = 0x0, | ||
63 | EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */ | ||
64 | } DC_BSS_REPORTING_POLICY; | ||
65 | |||
66 | typedef enum { | ||
67 | DC_IGNORE_WPAx_GROUP_CIPHER = 0x01, | ||
68 | DC_PROFILE_MATCH_DONE = 0x02, | ||
69 | DC_IGNORE_AAC_BEACON = 0x04, | ||
70 | DC_CSA_FOLLOW_BSS = 0x08, | ||
71 | } DC_PROFILE_FILTER; | ||
72 | |||
73 | #define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS) | ||
74 | |||
75 | #endif /* _DISCOVERY_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/epping_test.h b/drivers/staging/ath6kl/include/common/epping_test.h new file mode 100644 index 00000000000..9eb5fdfa746 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/epping_test.h | |||
@@ -0,0 +1,111 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2009-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | //------------------------------------------------------------------------------ | ||
19 | //============================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | // | ||
22 | |||
23 | /* This file contains shared definitions for the host/target endpoint ping test */ | ||
24 | |||
25 | #ifndef EPPING_TEST_H_ | ||
26 | #define EPPING_TEST_H_ | ||
27 | |||
28 | /* alignment to 4-bytes */ | ||
29 | #define EPPING_ALIGNMENT_PAD (((sizeof(struct htc_frame_hdr) + 3) & (~0x3)) - sizeof(struct htc_frame_hdr)) | ||
30 | |||
31 | #ifndef A_OFFSETOF | ||
32 | #define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) | ||
33 | #endif | ||
34 | |||
35 | #define EPPING_RSVD_FILL 0xCC | ||
36 | |||
37 | #define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7 | ||
38 | |||
39 | typedef PREPACK struct { | ||
40 | u8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */ | ||
41 | u8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */ | ||
42 | u8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target) | ||
43 | When echoed: StreamEchoSent_t == StreamEcho_h */ | ||
44 | u8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */ | ||
45 | u8 StreamNo_h; /* stream number to send on (filled by host) */ | ||
46 | u8 Magic_h[4]; /* magic number to filter for this packet on the host*/ | ||
47 | u8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value | ||
48 | since this packet maps to a 14-byte ethernet frame we want | ||
49 | to make sure ethertype field is set to something unknown */ | ||
50 | |||
51 | u8 _pad[2]; /* padding for alignment */ | ||
52 | u8 TimeStamp[8]; /* timestamp of packet (host or target) */ | ||
53 | u32 HostContext_h; /* 4 byte host context, target echos this back */ | ||
54 | u32 SeqNo; /* sequence number (set by host or target) */ | ||
55 | u16 Cmd_h; /* ping command (filled by host) */ | ||
56 | u16 CmdFlags_h; /* optional flags */ | ||
57 | u8 CmdBuffer_h[8]; /* buffer for command (host -> target) */ | ||
58 | u8 CmdBuffer_t[8]; /* buffer for command (target -> host) */ | ||
59 | u16 DataLength; /* length of data */ | ||
60 | u16 DataCRC; /* 16 bit CRC of data */ | ||
61 | u16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */ | ||
62 | } POSTPACK EPPING_HEADER; | ||
63 | |||
64 | #define EPPING_PING_MAGIC_0 0xAA | ||
65 | #define EPPING_PING_MAGIC_1 0x55 | ||
66 | #define EPPING_PING_MAGIC_2 0xCE | ||
67 | #define EPPING_PING_MAGIC_3 0xEC | ||
68 | |||
69 | |||
70 | |||
71 | #define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \ | ||
72 | ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \ | ||
73 | ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \ | ||
74 | ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3)) | ||
75 | |||
76 | #define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \ | ||
77 | (pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \ | ||
78 | (pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \ | ||
79 | (pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;} | ||
80 | |||
81 | #define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */ | ||
82 | #define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */ | ||
83 | #define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */ | ||
84 | |||
85 | #define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP) | ||
86 | |||
87 | #define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */ | ||
88 | #define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */ | ||
89 | #define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */ | ||
90 | #define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */ | ||
91 | #define EPPING_CMD_CONT_RX_START 5 /* continuous RX packets, parameters are in CmdBuffer_h */ | ||
92 | #define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */ | ||
93 | |||
94 | /* test command parameters may be no more than 8 bytes */ | ||
95 | typedef PREPACK struct { | ||
96 | u16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */ | ||
97 | u16 PacketLength; /* length of packet to generate including header */ | ||
98 | u16 Flags; /* flags */ | ||
99 | |||
100 | #define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */ | ||
101 | #define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */ | ||
102 | #define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */ | ||
103 | } POSTPACK EPPING_CONT_RX_PARAMS; | ||
104 | |||
105 | #define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h) | ||
106 | #define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(u16))) | ||
107 | |||
108 | #define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we | ||
109 | can use this to distinguish packets */ | ||
110 | |||
111 | #endif /*EPPING_TEST_H_*/ | ||
diff --git a/drivers/staging/ath6kl/include/common/gmboxif.h b/drivers/staging/ath6kl/include/common/gmboxif.h new file mode 100644 index 00000000000..ea11c14def4 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/gmboxif.h | |||
@@ -0,0 +1,70 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2009-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | //------------------------------------------------------------------------------ | ||
19 | //============================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //============================================================================== | ||
22 | |||
23 | #ifndef __GMBOXIF_H__ | ||
24 | #define __GMBOXIF_H__ | ||
25 | |||
26 | /* GMBOX interface definitions */ | ||
27 | |||
28 | #define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */ | ||
29 | #define AR6K_GMBOX_CREDIT_SIZE_COUNTER 2 /* credit counter 2 is used to pass the size of each credit */ | ||
30 | |||
31 | |||
32 | /* HCI UART transport definitions when used over GMBOX interface */ | ||
33 | #define HCI_UART_COMMAND_PKT 0x01 | ||
34 | #define HCI_UART_ACL_PKT 0x02 | ||
35 | #define HCI_UART_SCO_PKT 0x03 | ||
36 | #define HCI_UART_EVENT_PKT 0x04 | ||
37 | |||
38 | /* definitions for BT HCI packets */ | ||
39 | typedef PREPACK struct { | ||
40 | u16 Flags_ConnHandle; | ||
41 | u16 Length; | ||
42 | } POSTPACK BT_HCI_ACL_HEADER; | ||
43 | |||
44 | typedef PREPACK struct { | ||
45 | u16 Flags_ConnHandle; | ||
46 | u8 Length; | ||
47 | } POSTPACK BT_HCI_SCO_HEADER; | ||
48 | |||
49 | typedef PREPACK struct { | ||
50 | u16 OpCode; | ||
51 | u8 ParamLength; | ||
52 | } POSTPACK BT_HCI_COMMAND_HEADER; | ||
53 | |||
54 | typedef PREPACK struct { | ||
55 | u8 EventCode; | ||
56 | u8 ParamLength; | ||
57 | } POSTPACK BT_HCI_EVENT_HEADER; | ||
58 | |||
59 | /* MBOX host interrupt signal assignments */ | ||
60 | |||
61 | #define MBOX_SIG_HCI_BRIDGE_MAX 8 | ||
62 | #define MBOX_SIG_HCI_BRIDGE_BT_ON 0 | ||
63 | #define MBOX_SIG_HCI_BRIDGE_BT_OFF 1 | ||
64 | #define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2 | ||
65 | #define MBOX_SIG_HCI_BRIDGE_PWR_SAV_ON 3 | ||
66 | #define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF 4 | ||
67 | |||
68 | |||
69 | #endif /* __GMBOXIF_H__ */ | ||
70 | |||
diff --git a/drivers/staging/ath6kl/include/common/gpio_reg.h b/drivers/staging/ath6kl/include/common/gpio_reg.h new file mode 100644 index 00000000000..f9d425d48dc --- /dev/null +++ b/drivers/staging/ath6kl/include/common/gpio_reg.h | |||
@@ -0,0 +1,9 @@ | |||
1 | #ifndef _GPIO_REG_REG_H_ | ||
2 | #define _GPIO_REG_REG_H_ | ||
3 | |||
4 | #define GPIO_PIN10_ADDRESS 0x00000050 | ||
5 | #define GPIO_PIN11_ADDRESS 0x00000054 | ||
6 | #define GPIO_PIN12_ADDRESS 0x00000058 | ||
7 | #define GPIO_PIN13_ADDRESS 0x0000005c | ||
8 | |||
9 | #endif /* _GPIO_REG_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/htc.h b/drivers/staging/ath6kl/include/common/htc.h new file mode 100644 index 00000000000..85cbfa89d67 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/htc.h | |||
@@ -0,0 +1,227 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="htc.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef __HTC_H__ | ||
25 | #define __HTC_H__ | ||
26 | |||
27 | #define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field)) | ||
28 | |||
29 | #define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ | ||
30 | (((u16)(((u8 *)(p))[(highbyte)])) << 8 | (u16)(((u8 *)(p))[(lowbyte)])) | ||
31 | |||
32 | /* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a | ||
33 | * structure using only the type and field name. | ||
34 | * Use these macros if there is the potential for unaligned buffer accesses. */ | ||
35 | #define A_GET_UINT16_FIELD(p,type,field) \ | ||
36 | ASSEMBLE_UNALIGNED_UINT16(p,\ | ||
37 | A_OFFSETOF(type,field) + 1, \ | ||
38 | A_OFFSETOF(type,field)) | ||
39 | |||
40 | #define A_SET_UINT16_FIELD(p,type,field,value) \ | ||
41 | { \ | ||
42 | ((u8 *)(p))[A_OFFSETOF(type,field)] = (u8)(value); \ | ||
43 | ((u8 *)(p))[A_OFFSETOF(type,field) + 1] = (u8)((value) >> 8); \ | ||
44 | } | ||
45 | |||
46 | #define A_GET_UINT8_FIELD(p,type,field) \ | ||
47 | ((u8 *)(p))[A_OFFSETOF(type,field)] | ||
48 | |||
49 | #define A_SET_UINT8_FIELD(p,type,field,value) \ | ||
50 | ((u8 *)(p))[A_OFFSETOF(type,field)] = (value) | ||
51 | |||
52 | /****** DANGER DANGER *************** | ||
53 | * | ||
54 | * The frame header length and message formats defined herein were | ||
55 | * selected to accommodate optimal alignment for target processing. This reduces code | ||
56 | * size and improves performance. | ||
57 | * | ||
58 | * Any changes to the header length may alter the alignment and cause exceptions | ||
59 | * on the target. When adding to the message structures insure that fields are | ||
60 | * properly aligned. | ||
61 | * | ||
62 | */ | ||
63 | |||
64 | /* HTC frame header */ | ||
65 | PREPACK struct htc_frame_hdr { | ||
66 | /* do not remove or re-arrange these fields, these are minimally required | ||
67 | * to take advantage of 4-byte lookaheads in some hardware implementations */ | ||
68 | u8 EndpointID; | ||
69 | u8 Flags; | ||
70 | u16 PayloadLen; /* length of data (including trailer) that follows the header */ | ||
71 | |||
72 | /***** end of 4-byte lookahead ****/ | ||
73 | |||
74 | u8 ControlBytes[2]; | ||
75 | |||
76 | /* message payload starts after the header */ | ||
77 | |||
78 | } POSTPACK; | ||
79 | |||
80 | /* frame header flags */ | ||
81 | |||
82 | /* send direction */ | ||
83 | #define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) | ||
84 | #define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */ | ||
85 | /* receive direction */ | ||
86 | #define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */ | ||
87 | #define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */ | ||
88 | #define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */ | ||
89 | #define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */ | ||
90 | #define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */ | ||
91 | #define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4 | ||
92 | |||
93 | #define HTC_HDR_LENGTH (sizeof(struct htc_frame_hdr)) | ||
94 | #define HTC_MAX_TRAILER_LENGTH 255 | ||
95 | #define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(struct htc_frame_hdr)) | ||
96 | |||
97 | /* HTC control message IDs */ | ||
98 | |||
99 | #define HTC_MSG_READY_ID 1 | ||
100 | #define HTC_MSG_CONNECT_SERVICE_ID 2 | ||
101 | #define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3 | ||
102 | #define HTC_MSG_SETUP_COMPLETE_ID 4 | ||
103 | #define HTC_MSG_SETUP_COMPLETE_EX_ID 5 | ||
104 | |||
105 | #define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 | ||
106 | |||
107 | /* base message ID header */ | ||
108 | typedef PREPACK struct { | ||
109 | u16 MessageID; | ||
110 | } POSTPACK HTC_UNKNOWN_MSG; | ||
111 | |||
112 | /* HTC ready message | ||
113 | * direction : target-to-host */ | ||
114 | typedef PREPACK struct { | ||
115 | u16 MessageID; /* ID */ | ||
116 | u16 CreditCount; /* number of credits the target can offer */ | ||
117 | u16 CreditSize; /* size of each credit */ | ||
118 | u8 MaxEndpoints; /* maximum number of endpoints the target has resources for */ | ||
119 | u8 _Pad1; | ||
120 | } POSTPACK HTC_READY_MSG; | ||
121 | |||
122 | /* extended HTC ready message */ | ||
123 | typedef PREPACK struct { | ||
124 | HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */ | ||
125 | /* extended information */ | ||
126 | u8 HTCVersion; | ||
127 | u8 MaxMsgsPerHTCBundle; | ||
128 | } POSTPACK HTC_READY_EX_MSG; | ||
129 | |||
130 | #define HTC_VERSION_2P0 0x00 | ||
131 | #define HTC_VERSION_2P1 0x01 /* HTC 2.1 */ | ||
132 | |||
133 | #define HTC_SERVICE_META_DATA_MAX_LENGTH 128 | ||
134 | |||
135 | /* connect service | ||
136 | * direction : host-to-target */ | ||
137 | typedef PREPACK struct { | ||
138 | u16 MessageID; | ||
139 | u16 ServiceID; /* service ID of the service to connect to */ | ||
140 | u16 ConnectionFlags; /* connection flags */ | ||
141 | |||
142 | #define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when | ||
143 | the host needs credits */ | ||
144 | #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) | ||
145 | #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 | ||
146 | #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 | ||
147 | #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 | ||
148 | #define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 | ||
149 | |||
150 | u8 ServiceMetaLength; /* length of meta data that follows */ | ||
151 | u8 _Pad1; | ||
152 | |||
153 | /* service-specific meta data starts after the header */ | ||
154 | |||
155 | } POSTPACK HTC_CONNECT_SERVICE_MSG; | ||
156 | |||
157 | /* connect response | ||
158 | * direction : target-to-host */ | ||
159 | typedef PREPACK struct { | ||
160 | u16 MessageID; | ||
161 | u16 ServiceID; /* service ID that the connection request was made */ | ||
162 | u8 Status; /* service connection status */ | ||
163 | u8 EndpointID; /* assigned endpoint ID */ | ||
164 | u16 MaxMsgSize; /* maximum expected message size on this endpoint */ | ||
165 | u8 ServiceMetaLength; /* length of meta data that follows */ | ||
166 | u8 _Pad1; | ||
167 | |||
168 | /* service-specific meta data starts after the header */ | ||
169 | |||
170 | } POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; | ||
171 | |||
172 | typedef PREPACK struct { | ||
173 | u16 MessageID; | ||
174 | /* currently, no other fields */ | ||
175 | } POSTPACK HTC_SETUP_COMPLETE_MSG; | ||
176 | |||
177 | /* extended setup completion message */ | ||
178 | typedef PREPACK struct { | ||
179 | u16 MessageID; | ||
180 | u32 SetupFlags; | ||
181 | u8 MaxMsgsPerBundledRecv; | ||
182 | u8 Rsvd[3]; | ||
183 | } POSTPACK HTC_SETUP_COMPLETE_EX_MSG; | ||
184 | |||
185 | #define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) | ||
186 | |||
187 | /* connect response status codes */ | ||
188 | #define HTC_SERVICE_SUCCESS 0 /* success */ | ||
189 | #define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ | ||
190 | #define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ | ||
191 | #define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ | ||
192 | #define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more | ||
193 | endpoints */ | ||
194 | |||
195 | /* report record IDs */ | ||
196 | |||
197 | #define HTC_RECORD_NULL 0 | ||
198 | #define HTC_RECORD_CREDITS 1 | ||
199 | #define HTC_RECORD_LOOKAHEAD 2 | ||
200 | #define HTC_RECORD_LOOKAHEAD_BUNDLE 3 | ||
201 | |||
202 | typedef PREPACK struct { | ||
203 | u8 RecordID; /* Record ID */ | ||
204 | u8 Length; /* Length of record */ | ||
205 | } POSTPACK HTC_RECORD_HDR; | ||
206 | |||
207 | typedef PREPACK struct { | ||
208 | u8 EndpointID; /* Endpoint that owns these credits */ | ||
209 | u8 Credits; /* credits to report since last report */ | ||
210 | } POSTPACK HTC_CREDIT_REPORT; | ||
211 | |||
212 | typedef PREPACK struct { | ||
213 | u8 PreValid; /* pre valid guard */ | ||
214 | u8 LookAhead[4]; /* 4 byte lookahead */ | ||
215 | u8 PostValid; /* post valid guard */ | ||
216 | |||
217 | /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. | ||
218 | * The PreValid bytes must equal the inverse of the PostValid byte */ | ||
219 | |||
220 | } POSTPACK HTC_LOOKAHEAD_REPORT; | ||
221 | |||
222 | typedef PREPACK struct { | ||
223 | u8 LookAhead[4]; /* 4 byte lookahead */ | ||
224 | } POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT; | ||
225 | |||
226 | #endif /* __HTC_H__ */ | ||
227 | |||
diff --git a/drivers/staging/ath6kl/include/common/htc_services.h b/drivers/staging/ath6kl/include/common/htc_services.h new file mode 100644 index 00000000000..fb22268a8d8 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/htc_services.h | |||
@@ -0,0 +1,52 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="htc_services.h" company="Atheros"> | ||
3 | // Copyright (c) 2007 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef __HTC_SERVICES_H__ | ||
25 | #define __HTC_SERVICES_H__ | ||
26 | |||
27 | /* Current service IDs */ | ||
28 | |||
29 | typedef enum { | ||
30 | RSVD_SERVICE_GROUP = 0, | ||
31 | WMI_SERVICE_GROUP = 1, | ||
32 | |||
33 | HTC_TEST_GROUP = 254, | ||
34 | HTC_SERVICE_GROUP_LAST = 255 | ||
35 | }HTC_SERVICE_GROUP_IDS; | ||
36 | |||
37 | #define MAKE_SERVICE_ID(group,index) \ | ||
38 | (int)(((int)group << 8) | (int)(index)) | ||
39 | |||
40 | /* NOTE: service ID of 0x0000 is reserved and should never be used */ | ||
41 | #define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) | ||
42 | #define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) | ||
43 | #define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) | ||
44 | #define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) | ||
45 | #define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) | ||
46 | #define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) | ||
47 | #define WMI_MAX_SERVICES 5 | ||
48 | |||
49 | /* raw stream service (i.e. flash, tcmd, calibration apps) */ | ||
50 | #define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) | ||
51 | |||
52 | #endif /*HTC_SERVICES_H_*/ | ||
diff --git a/drivers/staging/ath6kl/include/common/pkt_log.h b/drivers/staging/ath6kl/include/common/pkt_log.h new file mode 100644 index 00000000000..a3719adf54c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/pkt_log.h | |||
@@ -0,0 +1,45 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | //------------------------------------------------------------------------------ | ||
19 | //============================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //============================================================================== | ||
22 | |||
23 | #ifndef __PKT_LOG_H__ | ||
24 | #define __PKT_LOG_H__ | ||
25 | |||
26 | #ifdef __cplusplus | ||
27 | extern "C" { | ||
28 | #endif | ||
29 | |||
30 | |||
31 | /* Pkt log info */ | ||
32 | typedef PREPACK struct pkt_log_t { | ||
33 | struct info_t { | ||
34 | u16 st; | ||
35 | u16 end; | ||
36 | u16 cur; | ||
37 | }info[4096]; | ||
38 | u16 last_idx; | ||
39 | }POSTPACK PACKET_LOG; | ||
40 | |||
41 | |||
42 | #ifdef __cplusplus | ||
43 | } | ||
44 | #endif | ||
45 | #endif /* __PKT_LOG_H__ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/roaming.h b/drivers/staging/ath6kl/include/common/roaming.h new file mode 100644 index 00000000000..8019850a057 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/roaming.h | |||
@@ -0,0 +1,41 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="roaming.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef _ROAMING_H_ | ||
25 | #define _ROAMING_H_ | ||
26 | |||
27 | /* | ||
28 | * The signal quality could be in terms of either snr or rssi. We should | ||
29 | * have an enum for both of them. For the time being, we are going to move | ||
30 | * it to wmi.h that is shared by both host and the target, since we are | ||
31 | * repartitioning the code to the host | ||
32 | */ | ||
33 | #define SIGNAL_QUALITY_NOISE_FLOOR -96 | ||
34 | #define SIGNAL_QUALITY_METRICS_NUM_MAX 2 | ||
35 | typedef enum { | ||
36 | SIGNAL_QUALITY_METRICS_SNR = 0, | ||
37 | SIGNAL_QUALITY_METRICS_RSSI, | ||
38 | SIGNAL_QUALITY_METRICS_ALL, | ||
39 | } SIGNAL_QUALITY_METRICS_TYPE; | ||
40 | |||
41 | #endif /* _ROAMING_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/targaddrs.h b/drivers/staging/ath6kl/include/common/targaddrs.h new file mode 100644 index 00000000000..c866cefbd8f --- /dev/null +++ b/drivers/staging/ath6kl/include/common/targaddrs.h | |||
@@ -0,0 +1,395 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // | ||
19 | // Author(s): ="Atheros" | ||
20 | //------------------------------------------------------------------------------ | ||
21 | |||
22 | #ifndef __TARGADDRS_H__ | ||
23 | #define __TARGADDRS_H__ | ||
24 | |||
25 | #if defined(AR6002) | ||
26 | #include "AR6002/addrs.h" | ||
27 | #endif | ||
28 | |||
29 | /* | ||
30 | * AR6K option bits, to enable/disable various features. | ||
31 | * By default, all option bits are 0. | ||
32 | * These bits can be set in LOCAL_SCRATCH register 0. | ||
33 | */ | ||
34 | #define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ | ||
35 | #define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ | ||
36 | #define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ | ||
37 | #define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ | ||
38 | #define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ | ||
39 | #define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ | ||
40 | #define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ | ||
41 | #define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ | ||
42 | |||
43 | /* | ||
44 | * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the | ||
45 | * host_interest structure. It must match the address of the _host_interest | ||
46 | * symbol (see linker script). | ||
47 | * | ||
48 | * Host Interest is shared between Host and Target in order to coordinate | ||
49 | * between the two, and is intended to remain constant (with additions only | ||
50 | * at the end) across software releases. | ||
51 | * | ||
52 | * All addresses are available here so that it's possible to | ||
53 | * write a single binary that works with all Target Types. | ||
54 | * May be used in assembler code as well as C. | ||
55 | */ | ||
56 | #define AR6002_HOST_INTEREST_ADDRESS 0x00500400 | ||
57 | #define AR6003_HOST_INTEREST_ADDRESS 0x00540600 | ||
58 | |||
59 | |||
60 | #define HOST_INTEREST_MAX_SIZE 0x100 | ||
61 | |||
62 | #if !defined(__ASSEMBLER__) | ||
63 | struct register_dump_s; | ||
64 | struct dbglog_hdr_s; | ||
65 | |||
66 | /* | ||
67 | * These are items that the Host may need to access | ||
68 | * via BMI or via the Diagnostic Window. The position | ||
69 | * of items in this structure must remain constant | ||
70 | * across firmware revisions! | ||
71 | * | ||
72 | * Types for each item must be fixed size across | ||
73 | * target and host platforms. | ||
74 | * | ||
75 | * More items may be added at the end. | ||
76 | */ | ||
77 | PREPACK struct host_interest_s { | ||
78 | /* | ||
79 | * Pointer to application-defined area, if any. | ||
80 | * Set by Target application during startup. | ||
81 | */ | ||
82 | u32 hi_app_host_interest; /* 0x00 */ | ||
83 | |||
84 | /* Pointer to register dump area, valid after Target crash. */ | ||
85 | u32 hi_failure_state; /* 0x04 */ | ||
86 | |||
87 | /* Pointer to debug logging header */ | ||
88 | u32 hi_dbglog_hdr; /* 0x08 */ | ||
89 | |||
90 | u32 hi_unused1; /* 0x0c */ | ||
91 | |||
92 | /* | ||
93 | * General-purpose flag bits, similar to AR6000_OPTION_* flags. | ||
94 | * Can be used by application rather than by OS. | ||
95 | */ | ||
96 | u32 hi_option_flag; /* 0x10 */ | ||
97 | |||
98 | /* | ||
99 | * Boolean that determines whether or not to | ||
100 | * display messages on the serial port. | ||
101 | */ | ||
102 | u32 hi_serial_enable; /* 0x14 */ | ||
103 | |||
104 | /* Start address of DataSet index, if any */ | ||
105 | u32 hi_dset_list_head; /* 0x18 */ | ||
106 | |||
107 | /* Override Target application start address */ | ||
108 | u32 hi_app_start; /* 0x1c */ | ||
109 | |||
110 | /* Clock and voltage tuning */ | ||
111 | u32 hi_skip_clock_init; /* 0x20 */ | ||
112 | u32 hi_core_clock_setting; /* 0x24 */ | ||
113 | u32 hi_cpu_clock_setting; /* 0x28 */ | ||
114 | u32 hi_system_sleep_setting; /* 0x2c */ | ||
115 | u32 hi_xtal_control_setting; /* 0x30 */ | ||
116 | u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ | ||
117 | u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ | ||
118 | u32 hi_ref_voltage_trim_setting; /* 0x3c */ | ||
119 | u32 hi_clock_info; /* 0x40 */ | ||
120 | |||
121 | /* | ||
122 | * Flash configuration overrides, used only | ||
123 | * when firmware is not executing from flash. | ||
124 | * (When using flash, modify the global variables | ||
125 | * with equivalent names.) | ||
126 | */ | ||
127 | u32 hi_bank0_addr_value; /* 0x44 */ | ||
128 | u32 hi_bank0_read_value; /* 0x48 */ | ||
129 | u32 hi_bank0_write_value; /* 0x4c */ | ||
130 | u32 hi_bank0_config_value; /* 0x50 */ | ||
131 | |||
132 | /* Pointer to Board Data */ | ||
133 | u32 hi_board_data; /* 0x54 */ | ||
134 | u32 hi_board_data_initialized; /* 0x58 */ | ||
135 | |||
136 | u32 hi_dset_RAM_index_table; /* 0x5c */ | ||
137 | |||
138 | u32 hi_desired_baud_rate; /* 0x60 */ | ||
139 | u32 hi_dbglog_config; /* 0x64 */ | ||
140 | u32 hi_end_RAM_reserve_sz; /* 0x68 */ | ||
141 | u32 hi_mbox_io_block_sz; /* 0x6c */ | ||
142 | |||
143 | u32 hi_num_bpatch_streams; /* 0x70 -- unused */ | ||
144 | u32 hi_mbox_isr_yield_limit; /* 0x74 */ | ||
145 | |||
146 | u32 hi_refclk_hz; /* 0x78 */ | ||
147 | u32 hi_ext_clk_detected; /* 0x7c */ | ||
148 | u32 hi_dbg_uart_txpin; /* 0x80 */ | ||
149 | u32 hi_dbg_uart_rxpin; /* 0x84 */ | ||
150 | u32 hi_hci_uart_baud; /* 0x88 */ | ||
151 | u32 hi_hci_uart_pin_assignments; /* 0x8C */ | ||
152 | /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ | ||
153 | u32 hi_hci_uart_baud_scale_val; /* 0x90 */ | ||
154 | u32 hi_hci_uart_baud_step_val; /* 0x94 */ | ||
155 | |||
156 | u32 hi_allocram_start; /* 0x98 */ | ||
157 | u32 hi_allocram_sz; /* 0x9c */ | ||
158 | u32 hi_hci_bridge_flags; /* 0xa0 */ | ||
159 | u32 hi_hci_uart_support_pins; /* 0xa4 */ | ||
160 | /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ | ||
161 | u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ | ||
162 | /* | ||
163 | * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high | ||
164 | * [31:16]: wakeup timeout in ms | ||
165 | */ | ||
166 | |||
167 | /* Pointer to extended board data */ | ||
168 | u32 hi_board_ext_data; /* 0xac */ | ||
169 | u32 hi_board_ext_data_config; /* 0xb0 */ | ||
170 | |||
171 | /* | ||
172 | * Bit [0] : valid | ||
173 | * Bit[31:16: size | ||
174 | */ | ||
175 | /* | ||
176 | * hi_reset_flag is used to do some stuff when target reset. | ||
177 | * such as restore app_start after warm reset or | ||
178 | * preserve host Interest area, or preserve ROM data, literals etc. | ||
179 | */ | ||
180 | u32 hi_reset_flag; /* 0xb4 */ | ||
181 | /* indicate hi_reset_flag is valid */ | ||
182 | u32 hi_reset_flag_valid; /* 0xb8 */ | ||
183 | u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ | ||
184 | /* | ||
185 | * 0xbc - [31:0]: idle timeout in ms | ||
186 | */ | ||
187 | /* ACS flags */ | ||
188 | u32 hi_acs_flags; /* 0xc0 */ | ||
189 | u32 hi_console_flags; /* 0xc4 */ | ||
190 | u32 hi_nvram_state; /* 0xc8 */ | ||
191 | u32 hi_option_flag2; /* 0xcc */ | ||
192 | |||
193 | /* If non-zero, override values sent to Host in WMI_READY event. */ | ||
194 | u32 hi_sw_version_override; /* 0xd0 */ | ||
195 | u32 hi_abi_version_override; /* 0xd4 */ | ||
196 | |||
197 | /* | ||
198 | * Percentage of high priority RX traffic to total expected RX traffic - | ||
199 | * applicable only to ar6004 | ||
200 | */ | ||
201 | u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ | ||
202 | |||
203 | /* test applications flags */ | ||
204 | u32 hi_test_apps_related ; /* 0xdc */ | ||
205 | /* location of test script */ | ||
206 | u32 hi_ota_testscript; /* 0xe0 */ | ||
207 | /* location of CAL data */ | ||
208 | u32 hi_cal_data; /* 0xe4 */ | ||
209 | /* Number of packet log buffers */ | ||
210 | u32 hi_pktlog_num_buffers; /* 0xe8 */ | ||
211 | |||
212 | } POSTPACK; | ||
213 | |||
214 | /* Bits defined in hi_option_flag */ | ||
215 | #define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ | ||
216 | #define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ | ||
217 | #define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ | ||
218 | /* MAC addr method 0-locally administred 1-globally unique addrs */ | ||
219 | #define HI_OPTION_MAC_ADDR_METHOD 0x08 | ||
220 | #define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */ | ||
221 | #define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ | ||
222 | #define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ | ||
223 | #define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ | ||
224 | #define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ | ||
225 | #define HI_OPTION_NUM_DEV_LSB 0x200 | ||
226 | #define HI_OPTION_NUM_DEV_MSB 0x800 | ||
227 | #define HI_OPTION_DEV_MODE_LSB 0x1000 | ||
228 | #define HI_OPTION_DEV_MODE_MSB 0x8000000 | ||
229 | /* Disable LowFreq Timer Stabilization */ | ||
230 | #define HI_OPTION_NO_LFT_STBL 0x10000000 | ||
231 | #define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */ | ||
232 | /* Do regulatory scan during init beforesending WMI ready event to host */ | ||
233 | #define HI_OPTION_INIT_REG_SCAN 0x40000000 | ||
234 | #define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory | ||
235 | map */ | ||
236 | |||
237 | /* hi_option_flag2 options */ | ||
238 | #define HI_OPTION_OFFLOAD_AMSDU 0x01 | ||
239 | #define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ | ||
240 | |||
241 | #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 | ||
242 | |||
243 | /* 2 bits of hi_option_flag are used to represent 3 modes */ | ||
244 | #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ | ||
245 | #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ | ||
246 | #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ | ||
247 | |||
248 | /* 2 bits of hi_option flag are usedto represent 4 submodes */ | ||
249 | #define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ | ||
250 | #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ | ||
251 | #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ | ||
252 | #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ | ||
253 | |||
254 | /* Num dev Mask */ | ||
255 | #define HI_OPTION_NUM_DEV_MASK 0x7 | ||
256 | #define HI_OPTION_NUM_DEV_SHIFT 0x9 | ||
257 | |||
258 | /* firmware bridging */ | ||
259 | #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 | ||
260 | |||
261 | /* Fw Mode/SubMode Mask | ||
262 | |------------------------------------------------------------------------------| | ||
263 | | SUB | SUB | SUB | SUB | | | | | ||
264 | | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| | ||
265 | | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | ||
266 | |------------------------------------------------------------------------------| | ||
267 | */ | ||
268 | #define HI_OPTION_FW_MODE_BITS 0x2 | ||
269 | #define HI_OPTION_FW_MODE_MASK 0x3 | ||
270 | #define HI_OPTION_FW_MODE_SHIFT 0xC | ||
271 | #define HI_OPTION_ALL_FW_MODE_MASK 0xFF | ||
272 | |||
273 | #define HI_OPTION_FW_SUBMODE_BITS 0x2 | ||
274 | #define HI_OPTION_FW_SUBMODE_MASK 0x3 | ||
275 | #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 | ||
276 | #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 | ||
277 | #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 | ||
278 | |||
279 | /* hi_reset_flag */ | ||
280 | |||
281 | /* preserve App Start address */ | ||
282 | #define HI_RESET_FLAG_PRESERVE_APP_START 0x01 | ||
283 | /* preserve host interest */ | ||
284 | #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 | ||
285 | #define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */ | ||
286 | #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 | ||
287 | #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 | ||
288 | |||
289 | #define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is | ||
290 | valid */ | ||
291 | |||
292 | #define ON_RESET_FLAGS_VALID() \ | ||
293 | (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID) | ||
294 | |||
295 | #define RESET_FLAGS_VALIDATE() \ | ||
296 | (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID) | ||
297 | |||
298 | #define RESET_FLAGS_INVALIDATE() \ | ||
299 | (HOST_INTEREST->hi_reset_flag_valid = 0) | ||
300 | |||
301 | #define ON_RESET_PRESERVE_APP_START() \ | ||
302 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START) | ||
303 | |||
304 | #define ON_RESET_PRESERVE_NVRAM_STATE() \ | ||
305 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE) | ||
306 | |||
307 | #define ON_RESET_PRESERVE_HOST_INTEREST() \ | ||
308 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST) | ||
309 | |||
310 | #define ON_RESET_PRESERVE_ROMDATA() \ | ||
311 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA) | ||
312 | |||
313 | #define ON_RESET_PRESERVE_BOOT_INFO() \ | ||
314 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO) | ||
315 | |||
316 | #define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */ | ||
317 | #define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */ | ||
318 | #define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */ | ||
319 | |||
320 | /* CONSOLE FLAGS | ||
321 | * | ||
322 | * Bit Range Meaning | ||
323 | * --------- -------------------------------- | ||
324 | * 2..0 UART ID (0 = Default) | ||
325 | * 3 Baud Select (0 = 9600, 1 = 115200) | ||
326 | * 30..4 Reserved | ||
327 | * 31 Enable Console | ||
328 | * | ||
329 | */ | ||
330 | |||
331 | #define HI_CONSOLE_FLAGS_ENABLE (1 << 31) | ||
332 | #define HI_CONSOLE_FLAGS_UART_MASK (0x7) | ||
333 | #define HI_CONSOLE_FLAGS_UART_SHIFT 0 | ||
334 | #define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3) | ||
335 | |||
336 | /* | ||
337 | * Intended for use by Host software, this macro returns the Target RAM | ||
338 | * address of any item in the host_interest structure. | ||
339 | * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); | ||
340 | */ | ||
341 | #define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ | ||
342 | (u32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) | ||
343 | |||
344 | #define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ | ||
345 | (u32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) | ||
346 | |||
347 | #define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \ | ||
348 | ((u32)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item))) | ||
349 | |||
350 | |||
351 | #define HOST_INTEREST_DBGLOG_IS_ENABLED() \ | ||
352 | (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) | ||
353 | |||
354 | #define HOST_INTEREST_PKTLOG_IS_ENABLED() \ | ||
355 | ((HOST_INTEREST->hi_pktlog_num_buffers)) | ||
356 | |||
357 | |||
358 | #define HOST_INTEREST_PROFILE_IS_ENABLED() \ | ||
359 | (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) | ||
360 | |||
361 | #define LF_TIMER_STABILIZATION_IS_ENABLED() \ | ||
362 | (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL)) | ||
363 | |||
364 | #define IS_AMSDU_OFFLAOD_ENABLED() \ | ||
365 | ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU)) | ||
366 | |||
367 | #define HOST_INTEREST_DFS_IS_ENABLED() \ | ||
368 | ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT)) | ||
369 | |||
370 | /* Convert a Target virtual address into a Target physical address */ | ||
371 | #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) | ||
372 | #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) | ||
373 | #define TARG_VTOP(TargetType, vaddr) \ | ||
374 | (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr)) | ||
375 | |||
376 | #define AR6003_REV2_APP_START_OVERRIDE 0x944C00 | ||
377 | #define AR6003_REV2_APP_LOAD_ADDRESS 0x543180 | ||
378 | #define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500 | ||
379 | #define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884 | ||
380 | #define AR6003_REV2_RAM_RESERVE_SIZE 6912 | ||
381 | |||
382 | #define AR6003_REV3_APP_START_OVERRIDE 0x945d00 | ||
383 | #define AR6003_REV3_APP_LOAD_ADDRESS 0x545000 | ||
384 | #define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330 | ||
385 | #define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74 | ||
386 | #define AR6003_REV3_RAM_RESERVE_SIZE 512 | ||
387 | |||
388 | #define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600 | ||
389 | |||
390 | /* # of u32 entries in targregs, used by DIAG_FETCH_TARG_REGS */ | ||
391 | #define AR6003_FETCH_TARG_REGS_COUNT 64 | ||
392 | |||
393 | #endif /* !__ASSEMBLER__ */ | ||
394 | |||
395 | #endif /* __TARGADDRS_H__ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/testcmd.h b/drivers/staging/ath6kl/include/common/testcmd.h new file mode 100644 index 00000000000..7d94aee508b --- /dev/null +++ b/drivers/staging/ath6kl/include/common/testcmd.h | |||
@@ -0,0 +1,185 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="testcmd.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | #ifndef TESTCMD_H_ | ||
25 | #define TESTCMD_H_ | ||
26 | |||
27 | #ifdef __cplusplus | ||
28 | extern "C" { | ||
29 | #endif | ||
30 | |||
31 | #ifdef AR6002_REV2 | ||
32 | #define TCMD_MAX_RATES 12 | ||
33 | #else | ||
34 | #define TCMD_MAX_RATES 28 | ||
35 | #endif | ||
36 | |||
37 | typedef enum { | ||
38 | ZEROES_PATTERN = 0, | ||
39 | ONES_PATTERN, | ||
40 | REPEATING_10, | ||
41 | PN7_PATTERN, | ||
42 | PN9_PATTERN, | ||
43 | PN15_PATTERN | ||
44 | }TX_DATA_PATTERN; | ||
45 | |||
46 | /* Continuous tx | ||
47 | mode : TCMD_CONT_TX_OFF - Disabling continuous tx | ||
48 | TCMD_CONT_TX_SINE - Enable continuous unmodulated tx | ||
49 | TCMD_CONT_TX_FRAME- Enable continuous modulated tx | ||
50 | freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g) | ||
51 | dataRate: 0 - 1 Mbps | ||
52 | 1 - 2 Mbps | ||
53 | 2 - 5.5 Mbps | ||
54 | 3 - 11 Mbps | ||
55 | 4 - 6 Mbps | ||
56 | 5 - 9 Mbps | ||
57 | 6 - 12 Mbps | ||
58 | 7 - 18 Mbps | ||
59 | 8 - 24 Mbps | ||
60 | 9 - 36 Mbps | ||
61 | 10 - 28 Mbps | ||
62 | 11 - 54 Mbps | ||
63 | txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx | ||
64 | antenna: 1 - one antenna | ||
65 | 2 - two antenna | ||
66 | Note : Enable/disable continuous tx test cmd works only when target is awake. | ||
67 | */ | ||
68 | |||
69 | typedef enum { | ||
70 | TCMD_CONT_TX_OFF = 0, | ||
71 | TCMD_CONT_TX_SINE, | ||
72 | TCMD_CONT_TX_FRAME, | ||
73 | TCMD_CONT_TX_TX99, | ||
74 | TCMD_CONT_TX_TX100 | ||
75 | } TCMD_CONT_TX_MODE; | ||
76 | |||
77 | typedef enum { | ||
78 | TCMD_WLAN_MODE_NOHT = 0, | ||
79 | TCMD_WLAN_MODE_HT20 = 1, | ||
80 | TCMD_WLAN_MODE_HT40PLUS = 2, | ||
81 | TCMD_WLAN_MODE_HT40MINUS = 3, | ||
82 | } TCMD_WLAN_MODE; | ||
83 | |||
84 | typedef PREPACK struct { | ||
85 | u32 testCmdId; | ||
86 | u32 mode; | ||
87 | u32 freq; | ||
88 | u32 dataRate; | ||
89 | s32 txPwr; | ||
90 | u32 antenna; | ||
91 | u32 enANI; | ||
92 | u32 scramblerOff; | ||
93 | u32 aifsn; | ||
94 | u16 pktSz; | ||
95 | u16 txPattern; | ||
96 | u32 shortGuard; | ||
97 | u32 numPackets; | ||
98 | u32 wlanMode; | ||
99 | } POSTPACK TCMD_CONT_TX; | ||
100 | |||
101 | #define TCMD_TXPATTERN_ZERONE 0x1 | ||
102 | #define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2 | ||
103 | |||
104 | /* Continuous Rx | ||
105 | act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) | ||
106 | TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest | ||
107 | address equal specified | ||
108 | mac address (set via act =3) | ||
109 | TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the | ||
110 | report from the last cont | ||
111 | Rx test) | ||
112 | |||
113 | TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the | ||
114 | target. This Overrides | ||
115 | the default MAC address.) | ||
116 | |||
117 | */ | ||
118 | typedef enum { | ||
119 | TCMD_CONT_RX_PROMIS =0, | ||
120 | TCMD_CONT_RX_FILTER, | ||
121 | TCMD_CONT_RX_REPORT, | ||
122 | TCMD_CONT_RX_SETMAC, | ||
123 | TCMD_CONT_RX_SET_ANT_SWITCH_TABLE | ||
124 | } TCMD_CONT_RX_ACT; | ||
125 | |||
126 | typedef PREPACK struct { | ||
127 | u32 testCmdId; | ||
128 | u32 act; | ||
129 | u32 enANI; | ||
130 | PREPACK union { | ||
131 | struct PREPACK TCMD_CONT_RX_PARA { | ||
132 | u32 freq; | ||
133 | u32 antenna; | ||
134 | u32 wlanMode; | ||
135 | } POSTPACK para; | ||
136 | struct PREPACK TCMD_CONT_RX_REPORT { | ||
137 | u32 totalPkt; | ||
138 | s32 rssiInDBm; | ||
139 | u32 crcErrPkt; | ||
140 | u32 secErrPkt; | ||
141 | u16 rateCnt[TCMD_MAX_RATES]; | ||
142 | u16 rateCntShortGuard[TCMD_MAX_RATES]; | ||
143 | } POSTPACK report; | ||
144 | struct PREPACK TCMD_CONT_RX_MAC { | ||
145 | u8 addr[ATH_MAC_LEN]; | ||
146 | } POSTPACK mac; | ||
147 | struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { | ||
148 | u32 antswitch1; | ||
149 | u32 antswitch2; | ||
150 | }POSTPACK antswitchtable; | ||
151 | } POSTPACK u; | ||
152 | } POSTPACK TCMD_CONT_RX; | ||
153 | |||
154 | /* Force sleep/wake test cmd | ||
155 | mode: TCMD_PM_WAKEUP - Wakeup the target | ||
156 | TCMD_PM_SLEEP - Force the target to sleep. | ||
157 | */ | ||
158 | typedef enum { | ||
159 | TCMD_PM_WAKEUP = 1, /* be consistent with target */ | ||
160 | TCMD_PM_SLEEP, | ||
161 | TCMD_PM_DEEPSLEEP | ||
162 | } TCMD_PM_MODE; | ||
163 | |||
164 | typedef PREPACK struct { | ||
165 | u32 testCmdId; | ||
166 | u32 mode; | ||
167 | } POSTPACK TCMD_PM; | ||
168 | |||
169 | typedef enum { | ||
170 | TCMD_CONT_TX_ID, | ||
171 | TCMD_CONT_RX_ID, | ||
172 | TCMD_PM_ID | ||
173 | } TCMD_ID; | ||
174 | |||
175 | typedef PREPACK union { | ||
176 | TCMD_CONT_TX contTx; | ||
177 | TCMD_CONT_RX contRx; | ||
178 | TCMD_PM pm; | ||
179 | } POSTPACK TEST_CMD; | ||
180 | |||
181 | #ifdef __cplusplus | ||
182 | } | ||
183 | #endif | ||
184 | |||
185 | #endif /* TESTCMD_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/tlpm.h b/drivers/staging/ath6kl/include/common/tlpm.h new file mode 100644 index 00000000000..659b1c07ba9 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/tlpm.h | |||
@@ -0,0 +1,38 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | //------------------------------------------------------------------------------ | ||
19 | //============================================================================== | ||
20 | // Author(s): ="Atheros" | ||
21 | //============================================================================== | ||
22 | |||
23 | #ifndef __TLPM_H__ | ||
24 | #define __TLPM_H__ | ||
25 | |||
26 | /* idle timeout in 16-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */ | ||
27 | #define TLPM_DEFAULT_IDLE_TIMEOUT_MS 1000 | ||
28 | /* hex in LSB and MSB for HCI command */ | ||
29 | #define TLPM_DEFAULT_IDLE_TIMEOUT_LSB 0xE8 | ||
30 | #define TLPM_DEFAULT_IDLE_TIMEOUT_MSB 0x3 | ||
31 | |||
32 | /* wakeup timeout in 8-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */ | ||
33 | #define TLPM_DEFAULT_WAKEUP_TIMEOUT_MS 10 | ||
34 | |||
35 | /* default UART FC polarity is low */ | ||
36 | #define TLPM_DEFAULT_UART_FC_POLARITY 0 | ||
37 | |||
38 | #endif | ||
diff --git a/drivers/staging/ath6kl/include/common/wlan_defs.h b/drivers/staging/ath6kl/include/common/wlan_defs.h new file mode 100644 index 00000000000..03e4d23788c --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wlan_defs.h | |||
@@ -0,0 +1,79 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="wlan_defs.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | #ifndef __WLAN_DEFS_H__ | ||
24 | #define __WLAN_DEFS_H__ | ||
25 | |||
26 | /* | ||
27 | * This file contains WLAN definitions that may be used across both | ||
28 | * Host and Target software. | ||
29 | */ | ||
30 | |||
31 | typedef enum { | ||
32 | MODE_11A = 0, /* 11a Mode */ | ||
33 | MODE_11G = 1, /* 11b/g Mode */ | ||
34 | MODE_11B = 2, /* 11b Mode */ | ||
35 | MODE_11GONLY = 3, /* 11g only Mode */ | ||
36 | #ifdef SUPPORT_11N | ||
37 | MODE_11NA_HT20 = 4, /* 11a HT20 mode */ | ||
38 | MODE_11NG_HT20 = 5, /* 11g HT20 mode */ | ||
39 | MODE_11NA_HT40 = 6, /* 11a HT40 mode */ | ||
40 | MODE_11NG_HT40 = 7, /* 11g HT40 mode */ | ||
41 | MODE_UNKNOWN = 8, | ||
42 | MODE_MAX = 8 | ||
43 | #else | ||
44 | MODE_UNKNOWN = 4, | ||
45 | MODE_MAX = 4 | ||
46 | #endif | ||
47 | } WLAN_PHY_MODE; | ||
48 | |||
49 | typedef enum { | ||
50 | WLAN_11A_CAPABILITY = 1, | ||
51 | WLAN_11G_CAPABILITY = 2, | ||
52 | WLAN_11AG_CAPABILITY = 3, | ||
53 | }WLAN_CAPABILITY; | ||
54 | |||
55 | #ifdef SUPPORT_11N | ||
56 | typedef unsigned long A_RATEMASK; | ||
57 | #else | ||
58 | typedef unsigned short A_RATEMASK; | ||
59 | #endif | ||
60 | |||
61 | #ifdef SUPPORT_11N | ||
62 | #define IS_MODE_11A(mode) (((mode) == MODE_11A) || \ | ||
63 | ((mode) == MODE_11NA_HT20) || \ | ||
64 | ((mode) == MODE_11NA_HT40)) | ||
65 | #define IS_MODE_11B(mode) ((mode) == MODE_11B) | ||
66 | #define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ | ||
67 | ((mode) == MODE_11GONLY) || \ | ||
68 | ((mode) == MODE_11NG_HT20) || \ | ||
69 | ((mode) == MODE_11NG_HT40)) | ||
70 | #define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) | ||
71 | #else | ||
72 | #define IS_MODE_11A(mode) ((mode) == MODE_11A) | ||
73 | #define IS_MODE_11B(mode) ((mode) == MODE_11B) | ||
74 | #define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ | ||
75 | ((mode) == MODE_11GONLY)) | ||
76 | #define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) | ||
77 | #endif /* SUPPORT_11N */ | ||
78 | |||
79 | #endif /* __WLANDEFS_H__ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/wmi.h b/drivers/staging/ath6kl/include/common/wmi.h new file mode 100644 index 00000000000..d9687443d32 --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wmi.h | |||
@@ -0,0 +1,3220 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
3 | // | ||
4 | // | ||
5 | // Permission to use, copy, modify, and/or distribute this software for any | ||
6 | // purpose with or without fee is hereby granted, provided that the above | ||
7 | // copyright notice and this permission notice appear in all copies. | ||
8 | // | ||
9 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
10 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
11 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
12 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
13 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
14 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
15 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
16 | // | ||
17 | // | ||
18 | // | ||
19 | // Author(s): ="Atheros" | ||
20 | //------------------------------------------------------------------------------ | ||
21 | |||
22 | /* | ||
23 | * This file contains the definitions of the WMI protocol specified in the | ||
24 | * Wireless Module Interface (WMI). It includes definitions of all the | ||
25 | * commands and events. Commands are messages from the host to the WM. | ||
26 | * Events and Replies are messages from the WM to the host. | ||
27 | * | ||
28 | * Ownership of correctness in regards to commands | ||
29 | * belongs to the host driver and the WMI is not required to validate | ||
30 | * parameters for value, proper range, or any other checking. | ||
31 | * | ||
32 | */ | ||
33 | |||
34 | #ifndef _WMI_H_ | ||
35 | #define _WMI_H_ | ||
36 | |||
37 | #include "wmix.h" | ||
38 | #include "wlan_defs.h" | ||
39 | |||
40 | #ifdef __cplusplus | ||
41 | extern "C" { | ||
42 | #endif | ||
43 | |||
44 | #define HTC_PROTOCOL_VERSION 0x0002 | ||
45 | #define HTC_PROTOCOL_REVISION 0x0000 | ||
46 | |||
47 | #define WMI_PROTOCOL_VERSION 0x0002 | ||
48 | #define WMI_PROTOCOL_REVISION 0x0000 | ||
49 | |||
50 | #define ATH_MAC_LEN 6 /* length of mac in bytes */ | ||
51 | #define WMI_CMD_MAX_LEN 100 | ||
52 | #define WMI_CONTROL_MSG_MAX_LEN 256 | ||
53 | #define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 | ||
54 | #define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) | ||
55 | #define RFC1042OUI {0x00, 0x00, 0x00} | ||
56 | |||
57 | #define IP_ETHERTYPE 0x0800 | ||
58 | |||
59 | #define WMI_IMPLICIT_PSTREAM 0xFF | ||
60 | #define WMI_MAX_THINSTREAM 15 | ||
61 | |||
62 | #ifdef AR6002_REV2 | ||
63 | #define IBSS_MAX_NUM_STA 4 | ||
64 | #else | ||
65 | #define IBSS_MAX_NUM_STA 8 | ||
66 | #endif | ||
67 | |||
68 | PREPACK struct host_app_area_s { | ||
69 | u32 wmi_protocol_ver; | ||
70 | } POSTPACK; | ||
71 | |||
72 | /* | ||
73 | * Data Path | ||
74 | */ | ||
75 | typedef PREPACK struct { | ||
76 | u8 dstMac[ATH_MAC_LEN]; | ||
77 | u8 srcMac[ATH_MAC_LEN]; | ||
78 | u16 typeOrLen; | ||
79 | } POSTPACK ATH_MAC_HDR; | ||
80 | |||
81 | typedef PREPACK struct { | ||
82 | u8 dsap; | ||
83 | u8 ssap; | ||
84 | u8 cntl; | ||
85 | u8 orgCode[3]; | ||
86 | u16 etherType; | ||
87 | } POSTPACK ATH_LLC_SNAP_HDR; | ||
88 | |||
89 | typedef enum { | ||
90 | DATA_MSGTYPE = 0x0, | ||
91 | CNTL_MSGTYPE, | ||
92 | SYNC_MSGTYPE, | ||
93 | OPT_MSGTYPE, | ||
94 | } WMI_MSG_TYPE; | ||
95 | |||
96 | |||
97 | /* | ||
98 | * Macros for operating on WMI_DATA_HDR (info) field | ||
99 | */ | ||
100 | |||
101 | #define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 | ||
102 | #define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 | ||
103 | #define WMI_DATA_HDR_UP_MASK 0x07 | ||
104 | #define WMI_DATA_HDR_UP_SHIFT 2 | ||
105 | /* In AP mode, the same bit (b5) is used to indicate Power save state in | ||
106 | * the Rx dir and More data bit state in the tx direction. | ||
107 | */ | ||
108 | #define WMI_DATA_HDR_PS_MASK 0x1 | ||
109 | #define WMI_DATA_HDR_PS_SHIFT 5 | ||
110 | |||
111 | #define WMI_DATA_HDR_MORE_MASK 0x1 | ||
112 | #define WMI_DATA_HDR_MORE_SHIFT 5 | ||
113 | |||
114 | typedef enum { | ||
115 | WMI_DATA_HDR_DATA_TYPE_802_3 = 0, | ||
116 | WMI_DATA_HDR_DATA_TYPE_802_11, | ||
117 | WMI_DATA_HDR_DATA_TYPE_ACL, /* used to be used for the PAL */ | ||
118 | } WMI_DATA_HDR_DATA_TYPE; | ||
119 | |||
120 | #define WMI_DATA_HDR_DATA_TYPE_MASK 0x3 | ||
121 | #define WMI_DATA_HDR_DATA_TYPE_SHIFT 6 | ||
122 | |||
123 | #define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT)) | ||
124 | |||
125 | #define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) | ||
126 | #define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | ||
127 | #define WMI_DATA_HDR_GET_UP(h) (((h)->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK) | ||
128 | #define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) | ||
129 | |||
130 | #define WMI_DATA_HDR_GET_DATA_TYPE(h) (((h)->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) & WMI_DATA_HDR_DATA_TYPE_MASK) | ||
131 | #define WMI_DATA_HDR_SET_DATA_TYPE(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_DATA_TYPE_MASK << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | ((p) << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | ||
132 | |||
133 | #define WMI_DATA_HDR_GET_DOT11(h) (WMI_DATA_HDR_GET_DATA_TYPE((h)) == WMI_DATA_HDR_DATA_TYPE_802_11) | ||
134 | #define WMI_DATA_HDR_SET_DOT11(h, p) WMI_DATA_HDR_SET_DATA_TYPE((h), (p)) | ||
135 | |||
136 | /* Macros for operating on WMI_DATA_HDR (info2) field */ | ||
137 | #define WMI_DATA_HDR_SEQNO_MASK 0xFFF | ||
138 | #define WMI_DATA_HDR_SEQNO_SHIFT 0 | ||
139 | |||
140 | #define WMI_DATA_HDR_AMSDU_MASK 0x1 | ||
141 | #define WMI_DATA_HDR_AMSDU_SHIFT 12 | ||
142 | |||
143 | #define WMI_DATA_HDR_META_MASK 0x7 | ||
144 | #define WMI_DATA_HDR_META_SHIFT 13 | ||
145 | |||
146 | #define GET_SEQ_NO(_v) ((_v) & WMI_DATA_HDR_SEQNO_MASK) | ||
147 | #define GET_ISMSDU(_v) ((_v) & WMI_DATA_HDR_AMSDU_MASK) | ||
148 | |||
149 | #define WMI_DATA_HDR_GET_SEQNO(h) GET_SEQ_NO((h)->info2 >> WMI_DATA_HDR_SEQNO_SHIFT) | ||
150 | #define WMI_DATA_HDR_SET_SEQNO(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_SEQNO_MASK << WMI_DATA_HDR_SEQNO_SHIFT)) | (GET_SEQ_NO(_v) << WMI_DATA_HDR_SEQNO_SHIFT)) | ||
151 | |||
152 | #define WMI_DATA_HDR_IS_AMSDU(h) GET_ISMSDU((h)->info2 >> WMI_DATA_HDR_AMSDU_SHIFT) | ||
153 | #define WMI_DATA_HDR_SET_AMSDU(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_AMSDU_MASK << WMI_DATA_HDR_AMSDU_SHIFT)) | (GET_ISMSDU(_v) << WMI_DATA_HDR_AMSDU_SHIFT)) | ||
154 | |||
155 | #define WMI_DATA_HDR_GET_META(h) (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK) | ||
156 | #define WMI_DATA_HDR_SET_META(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT)) | ||
157 | |||
158 | /* Macros for operating on WMI_DATA_HDR (info3) field */ | ||
159 | #define WMI_DATA_HDR_DEVID_MASK 0xF | ||
160 | #define WMI_DATA_HDR_DEVID_SHIFT 0 | ||
161 | #define GET_DEVID(_v) ((_v) & WMI_DATA_HDR_DEVID_MASK) | ||
162 | |||
163 | #define WMI_DATA_HDR_GET_DEVID(h) \ | ||
164 | (((h)->info3 >> WMI_DATA_HDR_DEVID_SHIFT) & WMI_DATA_HDR_DEVID_MASK) | ||
165 | #define WMI_DATA_HDR_SET_DEVID(h, _v) \ | ||
166 | ((h)->info3 = ((h)->info3 & ~(WMI_DATA_HDR_DEVID_MASK << WMI_DATA_HDR_DEVID_SHIFT)) | (GET_DEVID(_v) << WMI_DATA_HDR_DEVID_SHIFT)) | ||
167 | |||
168 | typedef PREPACK struct { | ||
169 | s8 rssi; | ||
170 | u8 info; /* usage of 'info' field(8-bit): | ||
171 | * b1:b0 - WMI_MSG_TYPE | ||
172 | * b4:b3:b2 - UP(tid) | ||
173 | * b5 - Used in AP mode. More-data in tx dir, PS in rx. | ||
174 | * b7:b6 - Dot3 header(0), | ||
175 | * Dot11 Header(1), | ||
176 | * ACL data(2) | ||
177 | */ | ||
178 | |||
179 | u16 info2; /* usage of 'info2' field(16-bit): | ||
180 | * b11:b0 - seq_no | ||
181 | * b12 - A-MSDU? | ||
182 | * b15:b13 - META_DATA_VERSION 0 - 7 | ||
183 | */ | ||
184 | u16 info3; | ||
185 | } POSTPACK WMI_DATA_HDR; | ||
186 | |||
187 | /* | ||
188 | * TX META VERSION DEFINITIONS | ||
189 | */ | ||
190 | #define WMI_MAX_TX_META_SZ (12) | ||
191 | #define WMI_MAX_TX_META_VERSION (7) | ||
192 | #define WMI_META_VERSION_1 (0x01) | ||
193 | #define WMI_META_VERSION_2 (0X02) | ||
194 | |||
195 | #define WMI_ACL_TO_DOT11_HEADROOM 36 | ||
196 | |||
197 | #if 0 /* removed to prevent compile errors for WM.. */ | ||
198 | typedef PREPACK struct { | ||
199 | /* intentionally empty. Default version is no meta data. */ | ||
200 | } POSTPACK WMI_TX_META_V0; | ||
201 | #endif | ||
202 | |||
203 | typedef PREPACK struct { | ||
204 | u8 pktID; /* The packet ID to identify the tx request */ | ||
205 | u8 ratePolicyID; /* The rate policy to be used for the tx of this frame */ | ||
206 | } POSTPACK WMI_TX_META_V1; | ||
207 | |||
208 | |||
209 | #define WMI_CSUM_DIR_TX (0x1) | ||
210 | #define TX_CSUM_CALC_FILL (0x1) | ||
211 | typedef PREPACK struct { | ||
212 | u8 csumStart; /*Offset from start of the WMI header for csum calculation to begin */ | ||
213 | u8 csumDest; /*Offset from start of WMI header where final csum goes*/ | ||
214 | u8 csumFlags; /*number of bytes over which csum is calculated*/ | ||
215 | } POSTPACK WMI_TX_META_V2; | ||
216 | |||
217 | |||
218 | /* | ||
219 | * RX META VERSION DEFINITIONS | ||
220 | */ | ||
221 | /* if RX meta data is present at all then the meta data field | ||
222 | * will consume WMI_MAX_RX_META_SZ bytes of space between the | ||
223 | * WMI_DATA_HDR and the payload. How much of the available | ||
224 | * Meta data is actually used depends on which meta data | ||
225 | * version is active. */ | ||
226 | #define WMI_MAX_RX_META_SZ (12) | ||
227 | #define WMI_MAX_RX_META_VERSION (7) | ||
228 | |||
229 | #define WMI_RX_STATUS_OK 0 /* success */ | ||
230 | #define WMI_RX_STATUS_DECRYPT_ERR 1 /* decrypt error */ | ||
231 | #define WMI_RX_STATUS_MIC_ERR 2 /* tkip MIC error */ | ||
232 | #define WMI_RX_STATUS_ERR 3 /* undefined error */ | ||
233 | |||
234 | #define WMI_RX_FLAGS_AGGR 0x0001 /* part of AGGR */ | ||
235 | #define WMI_RX_FlAGS_STBC 0x0002 /* used STBC */ | ||
236 | #define WMI_RX_FLAGS_SGI 0x0004 /* used SGI */ | ||
237 | #define WMI_RX_FLAGS_HT 0x0008 /* is HT packet */ | ||
238 | /* the flags field is also used to store the CRYPTO_TYPE of the frame | ||
239 | * that value is shifted by WMI_RX_FLAGS_CRYPTO_SHIFT */ | ||
240 | #define WMI_RX_FLAGS_CRYPTO_SHIFT 4 | ||
241 | #define WMI_RX_FLAGS_CRYPTO_MASK 0x1f | ||
242 | #define WMI_RX_META_GET_CRYPTO(flags) (((flags) >> WMI_RX_FLAGS_CRYPTO_SHIFT) & WMI_RX_FLAGS_CRYPTO_MASK) | ||
243 | |||
244 | #if 0 /* removed to prevent compile errors for WM.. */ | ||
245 | typedef PREPACK struct { | ||
246 | /* intentionally empty. Default version is no meta data. */ | ||
247 | } POSTPACK WMI_RX_META_VERSION_0; | ||
248 | #endif | ||
249 | |||
250 | typedef PREPACK struct { | ||
251 | u8 status; /* one of WMI_RX_STATUS_... */ | ||
252 | u8 rix; /* rate index mapped to rate at which this packet was received. */ | ||
253 | u8 rssi; /* rssi of packet */ | ||
254 | u8 channel;/* rf channel during packet reception */ | ||
255 | u16 flags; /* a combination of WMI_RX_FLAGS_... */ | ||
256 | } POSTPACK WMI_RX_META_V1; | ||
257 | |||
258 | #define RX_CSUM_VALID_FLAG (0x1) | ||
259 | typedef PREPACK struct { | ||
260 | u16 csum; | ||
261 | u8 csumFlags;/* bit 0 set -partial csum valid | ||
262 | bit 1 set -test mode */ | ||
263 | } POSTPACK WMI_RX_META_V2; | ||
264 | |||
265 | |||
266 | |||
267 | #define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF) | ||
268 | /* Macros for operating on WMI_CMD_HDR (info1) field */ | ||
269 | #define WMI_CMD_HDR_DEVID_MASK 0xF | ||
270 | #define WMI_CMD_HDR_DEVID_SHIFT 0 | ||
271 | #define GET_CMD_DEVID(_v) ((_v) & WMI_CMD_HDR_DEVID_MASK) | ||
272 | |||
273 | #define WMI_CMD_HDR_GET_DEVID(h) \ | ||
274 | (((h)->info1 >> WMI_CMD_HDR_DEVID_SHIFT) & WMI_CMD_HDR_DEVID_MASK) | ||
275 | #define WMI_CMD_HDR_SET_DEVID(h, _v) \ | ||
276 | ((h)->info1 = ((h)->info1 & \ | ||
277 | ~(WMI_CMD_HDR_DEVID_MASK << WMI_CMD_HDR_DEVID_SHIFT)) | \ | ||
278 | (GET_CMD_DEVID(_v) << WMI_CMD_HDR_DEVID_SHIFT)) | ||
279 | |||
280 | /* | ||
281 | * Control Path | ||
282 | */ | ||
283 | typedef PREPACK struct { | ||
284 | u16 commandId; | ||
285 | /* | ||
286 | * info1 - 16 bits | ||
287 | * b03:b00 - id | ||
288 | * b15:b04 - unused | ||
289 | */ | ||
290 | u16 info1; | ||
291 | |||
292 | u16 reserved; /* For alignment */ | ||
293 | } POSTPACK WMI_CMD_HDR; /* used for commands and events */ | ||
294 | |||
295 | /* | ||
296 | * List of Commnands | ||
297 | */ | ||
298 | typedef enum { | ||
299 | WMI_CONNECT_CMDID = 0x0001, | ||
300 | WMI_RECONNECT_CMDID, | ||
301 | WMI_DISCONNECT_CMDID, | ||
302 | WMI_SYNCHRONIZE_CMDID, | ||
303 | WMI_CREATE_PSTREAM_CMDID, | ||
304 | WMI_DELETE_PSTREAM_CMDID, | ||
305 | WMI_START_SCAN_CMDID, | ||
306 | WMI_SET_SCAN_PARAMS_CMDID, | ||
307 | WMI_SET_BSS_FILTER_CMDID, | ||
308 | WMI_SET_PROBED_SSID_CMDID, /* 10 */ | ||
309 | WMI_SET_LISTEN_INT_CMDID, | ||
310 | WMI_SET_BMISS_TIME_CMDID, | ||
311 | WMI_SET_DISC_TIMEOUT_CMDID, | ||
312 | WMI_GET_CHANNEL_LIST_CMDID, | ||
313 | WMI_SET_BEACON_INT_CMDID, | ||
314 | WMI_GET_STATISTICS_CMDID, | ||
315 | WMI_SET_CHANNEL_PARAMS_CMDID, | ||
316 | WMI_SET_POWER_MODE_CMDID, | ||
317 | WMI_SET_IBSS_PM_CAPS_CMDID, | ||
318 | WMI_SET_POWER_PARAMS_CMDID, /* 20 */ | ||
319 | WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, | ||
320 | WMI_ADD_CIPHER_KEY_CMDID, | ||
321 | WMI_DELETE_CIPHER_KEY_CMDID, | ||
322 | WMI_ADD_KRK_CMDID, | ||
323 | WMI_DELETE_KRK_CMDID, | ||
324 | WMI_SET_PMKID_CMDID, | ||
325 | WMI_SET_TX_PWR_CMDID, | ||
326 | WMI_GET_TX_PWR_CMDID, | ||
327 | WMI_SET_ASSOC_INFO_CMDID, | ||
328 | WMI_ADD_BAD_AP_CMDID, /* 30 */ | ||
329 | WMI_DELETE_BAD_AP_CMDID, | ||
330 | WMI_SET_TKIP_COUNTERMEASURES_CMDID, | ||
331 | WMI_RSSI_THRESHOLD_PARAMS_CMDID, | ||
332 | WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, | ||
333 | WMI_SET_ACCESS_PARAMS_CMDID, | ||
334 | WMI_SET_RETRY_LIMITS_CMDID, | ||
335 | WMI_SET_OPT_MODE_CMDID, | ||
336 | WMI_OPT_TX_FRAME_CMDID, | ||
337 | WMI_SET_VOICE_PKT_SIZE_CMDID, | ||
338 | WMI_SET_MAX_SP_LEN_CMDID, /* 40 */ | ||
339 | WMI_SET_ROAM_CTRL_CMDID, | ||
340 | WMI_GET_ROAM_TBL_CMDID, | ||
341 | WMI_GET_ROAM_DATA_CMDID, | ||
342 | WMI_ENABLE_RM_CMDID, | ||
343 | WMI_SET_MAX_OFFHOME_DURATION_CMDID, | ||
344 | WMI_EXTENSION_CMDID, /* Non-wireless extensions */ | ||
345 | WMI_SNR_THRESHOLD_PARAMS_CMDID, | ||
346 | WMI_LQ_THRESHOLD_PARAMS_CMDID, | ||
347 | WMI_SET_LPREAMBLE_CMDID, | ||
348 | WMI_SET_RTS_CMDID, /* 50 */ | ||
349 | WMI_CLR_RSSI_SNR_CMDID, | ||
350 | WMI_SET_FIXRATES_CMDID, | ||
351 | WMI_GET_FIXRATES_CMDID, | ||
352 | WMI_SET_AUTH_MODE_CMDID, | ||
353 | WMI_SET_REASSOC_MODE_CMDID, | ||
354 | WMI_SET_WMM_CMDID, | ||
355 | WMI_SET_WMM_TXOP_CMDID, | ||
356 | WMI_TEST_CMDID, | ||
357 | /* COEX AR6002 only*/ | ||
358 | WMI_SET_BT_STATUS_CMDID, | ||
359 | WMI_SET_BT_PARAMS_CMDID, /* 60 */ | ||
360 | |||
361 | WMI_SET_KEEPALIVE_CMDID, | ||
362 | WMI_GET_KEEPALIVE_CMDID, | ||
363 | WMI_SET_APPIE_CMDID, | ||
364 | WMI_GET_APPIE_CMDID, | ||
365 | WMI_SET_WSC_STATUS_CMDID, | ||
366 | |||
367 | /* Wake on Wireless */ | ||
368 | WMI_SET_HOST_SLEEP_MODE_CMDID, | ||
369 | WMI_SET_WOW_MODE_CMDID, | ||
370 | WMI_GET_WOW_LIST_CMDID, | ||
371 | WMI_ADD_WOW_PATTERN_CMDID, | ||
372 | WMI_DEL_WOW_PATTERN_CMDID, /* 70 */ | ||
373 | |||
374 | WMI_SET_FRAMERATES_CMDID, | ||
375 | WMI_SET_AP_PS_CMDID, | ||
376 | WMI_SET_QOS_SUPP_CMDID, | ||
377 | /* WMI_THIN_RESERVED_... mark the start and end | ||
378 | * values for WMI_THIN_RESERVED command IDs. These | ||
379 | * command IDs can be found in wmi_thin.h */ | ||
380 | WMI_THIN_RESERVED_START = 0x8000, | ||
381 | WMI_THIN_RESERVED_END = 0x8fff, | ||
382 | /* | ||
383 | * Developer commands starts at 0xF000 | ||
384 | */ | ||
385 | WMI_SET_BITRATE_CMDID = 0xF000, | ||
386 | WMI_GET_BITRATE_CMDID, | ||
387 | WMI_SET_WHALPARAM_CMDID, | ||
388 | |||
389 | |||
390 | /*Should add the new command to the tail for compatible with | ||
391 | * etna. | ||
392 | */ | ||
393 | WMI_SET_MAC_ADDRESS_CMDID, | ||
394 | WMI_SET_AKMP_PARAMS_CMDID, | ||
395 | WMI_SET_PMKID_LIST_CMDID, | ||
396 | WMI_GET_PMKID_LIST_CMDID, | ||
397 | WMI_ABORT_SCAN_CMDID, | ||
398 | WMI_SET_TARGET_EVENT_REPORT_CMDID, | ||
399 | |||
400 | // Unused | ||
401 | WMI_UNUSED1, | ||
402 | WMI_UNUSED2, | ||
403 | |||
404 | /* | ||
405 | * AP mode commands | ||
406 | */ | ||
407 | WMI_AP_HIDDEN_SSID_CMDID, | ||
408 | WMI_AP_SET_NUM_STA_CMDID, | ||
409 | WMI_AP_ACL_POLICY_CMDID, | ||
410 | WMI_AP_ACL_MAC_LIST_CMDID, | ||
411 | WMI_AP_CONFIG_COMMIT_CMDID, | ||
412 | WMI_AP_SET_MLME_CMDID, | ||
413 | WMI_AP_SET_PVB_CMDID, | ||
414 | WMI_AP_CONN_INACT_CMDID, | ||
415 | WMI_AP_PROT_SCAN_TIME_CMDID, | ||
416 | WMI_AP_SET_COUNTRY_CMDID, | ||
417 | WMI_AP_SET_DTIM_CMDID, | ||
418 | WMI_AP_MODE_STAT_CMDID, | ||
419 | |||
420 | WMI_SET_IP_CMDID, | ||
421 | WMI_SET_PARAMS_CMDID, | ||
422 | WMI_SET_MCAST_FILTER_CMDID, | ||
423 | WMI_DEL_MCAST_FILTER_CMDID, | ||
424 | |||
425 | WMI_ALLOW_AGGR_CMDID, | ||
426 | WMI_ADDBA_REQ_CMDID, | ||
427 | WMI_DELBA_REQ_CMDID, | ||
428 | WMI_SET_HT_CAP_CMDID, | ||
429 | WMI_SET_HT_OP_CMDID, | ||
430 | WMI_SET_TX_SELECT_RATES_CMDID, | ||
431 | WMI_SET_TX_SGI_PARAM_CMDID, | ||
432 | WMI_SET_RATE_POLICY_CMDID, | ||
433 | |||
434 | WMI_HCI_CMD_CMDID, | ||
435 | WMI_RX_FRAME_FORMAT_CMDID, | ||
436 | WMI_SET_THIN_MODE_CMDID, | ||
437 | WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID, | ||
438 | |||
439 | WMI_AP_SET_11BG_RATESET_CMDID, | ||
440 | WMI_SET_PMK_CMDID, | ||
441 | WMI_MCAST_FILTER_CMDID, | ||
442 | /* COEX CMDID AR6003*/ | ||
443 | WMI_SET_BTCOEX_FE_ANT_CMDID, | ||
444 | WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID, | ||
445 | WMI_SET_BTCOEX_SCO_CONFIG_CMDID, | ||
446 | WMI_SET_BTCOEX_A2DP_CONFIG_CMDID, | ||
447 | WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID, | ||
448 | WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID, | ||
449 | WMI_SET_BTCOEX_DEBUG_CMDID, | ||
450 | WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID, | ||
451 | WMI_GET_BTCOEX_STATS_CMDID, | ||
452 | WMI_GET_BTCOEX_CONFIG_CMDID, | ||
453 | |||
454 | WMI_SET_DFS_ENABLE_CMDID, /* F034 */ | ||
455 | WMI_SET_DFS_MINRSSITHRESH_CMDID, | ||
456 | WMI_SET_DFS_MAXPULSEDUR_CMDID, | ||
457 | WMI_DFS_RADAR_DETECTED_CMDID, | ||
458 | |||
459 | /* P2P CMDS */ | ||
460 | WMI_P2P_SET_CONFIG_CMDID, /* F038 */ | ||
461 | WMI_WPS_SET_CONFIG_CMDID, | ||
462 | WMI_SET_REQ_DEV_ATTR_CMDID, | ||
463 | WMI_P2P_FIND_CMDID, | ||
464 | WMI_P2P_STOP_FIND_CMDID, | ||
465 | WMI_P2P_GO_NEG_START_CMDID, | ||
466 | WMI_P2P_LISTEN_CMDID, | ||
467 | |||
468 | WMI_CONFIG_TX_MAC_RULES_CMDID, /* F040 */ | ||
469 | WMI_SET_PROMISCUOUS_MODE_CMDID, | ||
470 | WMI_RX_FRAME_FILTER_CMDID, | ||
471 | WMI_SET_CHANNEL_CMDID, | ||
472 | |||
473 | /* WAC commands */ | ||
474 | WMI_ENABLE_WAC_CMDID, | ||
475 | WMI_WAC_SCAN_REPLY_CMDID, | ||
476 | WMI_WAC_CTRL_REQ_CMDID, | ||
477 | WMI_SET_DIV_PARAMS_CMDID, | ||
478 | |||
479 | WMI_GET_PMK_CMDID, | ||
480 | WMI_SET_PASSPHRASE_CMDID, | ||
481 | WMI_SEND_ASSOC_RES_CMDID, | ||
482 | WMI_SET_ASSOC_REQ_RELAY_CMDID, | ||
483 | WMI_GET_RFKILL_MODE_CMDID, | ||
484 | |||
485 | /* ACS command, consists of sub-commands */ | ||
486 | WMI_ACS_CTRL_CMDID, | ||
487 | |||
488 | /* Ultra low power store / recall commands */ | ||
489 | WMI_STORERECALL_CONFIGURE_CMDID, | ||
490 | WMI_STORERECALL_RECALL_CMDID, | ||
491 | WMI_STORERECALL_HOST_READY_CMDID, | ||
492 | WMI_FORCE_TARGET_ASSERT_CMDID, | ||
493 | WMI_SET_EXCESS_TX_RETRY_THRES_CMDID, | ||
494 | } WMI_COMMAND_ID; | ||
495 | |||
496 | /* | ||
497 | * Frame Types | ||
498 | */ | ||
499 | typedef enum { | ||
500 | WMI_FRAME_BEACON = 0, | ||
501 | WMI_FRAME_PROBE_REQ, | ||
502 | WMI_FRAME_PROBE_RESP, | ||
503 | WMI_FRAME_ASSOC_REQ, | ||
504 | WMI_FRAME_ASSOC_RESP, | ||
505 | WMI_NUM_MGMT_FRAME | ||
506 | } WMI_MGMT_FRAME_TYPE; | ||
507 | |||
508 | /* | ||
509 | * Connect Command | ||
510 | */ | ||
511 | typedef enum { | ||
512 | INFRA_NETWORK = 0x01, | ||
513 | ADHOC_NETWORK = 0x02, | ||
514 | ADHOC_CREATOR = 0x04, | ||
515 | AP_NETWORK = 0x10, | ||
516 | } NETWORK_TYPE; | ||
517 | |||
518 | typedef enum { | ||
519 | OPEN_AUTH = 0x01, | ||
520 | SHARED_AUTH = 0x02, | ||
521 | LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ | ||
522 | } DOT11_AUTH_MODE; | ||
523 | |||
524 | enum { | ||
525 | AUTH_IDLE, | ||
526 | AUTH_OPEN_IN_PROGRESS, | ||
527 | }; | ||
528 | |||
529 | typedef enum { | ||
530 | NONE_AUTH = 0x01, | ||
531 | WPA_AUTH = 0x02, | ||
532 | WPA2_AUTH = 0x04, | ||
533 | WPA_PSK_AUTH = 0x08, | ||
534 | WPA2_PSK_AUTH = 0x10, | ||
535 | WPA_AUTH_CCKM = 0x20, | ||
536 | WPA2_AUTH_CCKM = 0x40, | ||
537 | } AUTH_MODE; | ||
538 | |||
539 | typedef enum { | ||
540 | NONE_CRYPT = 0x01, | ||
541 | WEP_CRYPT = 0x02, | ||
542 | TKIP_CRYPT = 0x04, | ||
543 | AES_CRYPT = 0x08, | ||
544 | #ifdef WAPI_ENABLE | ||
545 | WAPI_CRYPT = 0x10, | ||
546 | #endif /*WAPI_ENABLE*/ | ||
547 | } CRYPTO_TYPE; | ||
548 | |||
549 | #define WMI_MIN_CRYPTO_TYPE NONE_CRYPT | ||
550 | #define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) | ||
551 | |||
552 | #ifdef WAPI_ENABLE | ||
553 | #undef WMI_MAX_CRYPTO_TYPE | ||
554 | #define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) | ||
555 | #endif /* WAPI_ENABLE */ | ||
556 | |||
557 | #ifdef WAPI_ENABLE | ||
558 | #define IW_ENCODE_ALG_SM4 0x20 | ||
559 | #define IW_AUTH_WAPI_ENABLED 0x20 | ||
560 | #endif | ||
561 | |||
562 | #define WMI_MIN_KEY_INDEX 0 | ||
563 | #define WMI_MAX_KEY_INDEX 3 | ||
564 | |||
565 | #ifdef WAPI_ENABLE | ||
566 | #undef WMI_MAX_KEY_INDEX | ||
567 | #define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ | ||
568 | #endif /* WAPI_ENABLE */ | ||
569 | |||
570 | #define WMI_MAX_KEY_LEN 32 | ||
571 | |||
572 | #define WMI_MAX_SSID_LEN 32 | ||
573 | |||
574 | typedef enum { | ||
575 | CONNECT_ASSOC_POLICY_USER = 0x0001, | ||
576 | CONNECT_SEND_REASSOC = 0x0002, | ||
577 | CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, | ||
578 | CONNECT_PROFILE_MATCH_DONE = 0x0008, | ||
579 | CONNECT_IGNORE_AAC_BEACON = 0x0010, | ||
580 | CONNECT_CSA_FOLLOW_BSS = 0x0020, | ||
581 | CONNECT_DO_WPA_OFFLOAD = 0x0040, | ||
582 | CONNECT_DO_NOT_DEAUTH = 0x0080, | ||
583 | } WMI_CONNECT_CTRL_FLAGS_BITS; | ||
584 | |||
585 | #define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) | ||
586 | |||
587 | typedef PREPACK struct { | ||
588 | u8 networkType; | ||
589 | u8 dot11AuthMode; | ||
590 | u8 authMode; | ||
591 | u8 pairwiseCryptoType; | ||
592 | u8 pairwiseCryptoLen; | ||
593 | u8 groupCryptoType; | ||
594 | u8 groupCryptoLen; | ||
595 | u8 ssidLength; | ||
596 | u8 ssid[WMI_MAX_SSID_LEN]; | ||
597 | u16 channel; | ||
598 | u8 bssid[ATH_MAC_LEN]; | ||
599 | u32 ctrl_flags; | ||
600 | } POSTPACK WMI_CONNECT_CMD; | ||
601 | |||
602 | /* | ||
603 | * WMI_RECONNECT_CMDID | ||
604 | */ | ||
605 | typedef PREPACK struct { | ||
606 | u16 channel; /* hint */ | ||
607 | u8 bssid[ATH_MAC_LEN]; /* mandatory if set */ | ||
608 | } POSTPACK WMI_RECONNECT_CMD; | ||
609 | |||
610 | #define WMI_PMK_LEN 32 | ||
611 | typedef PREPACK struct { | ||
612 | u8 pmk[WMI_PMK_LEN]; | ||
613 | } POSTPACK WMI_SET_PMK_CMD; | ||
614 | |||
615 | /* | ||
616 | * WMI_SET_EXCESS_TX_RETRY_THRES_CMDID | ||
617 | */ | ||
618 | typedef PREPACK struct { | ||
619 | u32 threshold; | ||
620 | } POSTPACK WMI_SET_EXCESS_TX_RETRY_THRES_CMD; | ||
621 | |||
622 | /* | ||
623 | * WMI_ADD_CIPHER_KEY_CMDID | ||
624 | */ | ||
625 | typedef enum { | ||
626 | PAIRWISE_USAGE = 0x00, | ||
627 | GROUP_USAGE = 0x01, | ||
628 | TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ | ||
629 | } KEY_USAGE; | ||
630 | |||
631 | /* | ||
632 | * Bit Flag | ||
633 | * Bit 0 - Initialise TSC - default is Initialize | ||
634 | */ | ||
635 | #define KEY_OP_INIT_TSC 0x01 | ||
636 | #define KEY_OP_INIT_RSC 0x02 | ||
637 | #ifdef WAPI_ENABLE | ||
638 | #define KEY_OP_INIT_WAPIPN 0x10 | ||
639 | #endif /* WAPI_ENABLE */ | ||
640 | |||
641 | #define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ | ||
642 | #define KEY_OP_VALID_MASK 0x03 | ||
643 | |||
644 | typedef PREPACK struct { | ||
645 | u8 keyIndex; | ||
646 | u8 keyType; | ||
647 | u8 keyUsage; /* KEY_USAGE */ | ||
648 | u8 keyLength; | ||
649 | u8 keyRSC[8]; /* key replay sequence counter */ | ||
650 | u8 key[WMI_MAX_KEY_LEN]; | ||
651 | u8 key_op_ctrl; /* Additional Key Control information */ | ||
652 | u8 key_macaddr[ATH_MAC_LEN]; | ||
653 | } POSTPACK WMI_ADD_CIPHER_KEY_CMD; | ||
654 | |||
655 | /* | ||
656 | * WMI_DELETE_CIPHER_KEY_CMDID | ||
657 | */ | ||
658 | typedef PREPACK struct { | ||
659 | u8 keyIndex; | ||
660 | } POSTPACK WMI_DELETE_CIPHER_KEY_CMD; | ||
661 | |||
662 | #define WMI_KRK_LEN 16 | ||
663 | /* | ||
664 | * WMI_ADD_KRK_CMDID | ||
665 | */ | ||
666 | typedef PREPACK struct { | ||
667 | u8 krk[WMI_KRK_LEN]; | ||
668 | } POSTPACK WMI_ADD_KRK_CMD; | ||
669 | |||
670 | /* | ||
671 | * WMI_SET_TKIP_COUNTERMEASURES_CMDID | ||
672 | */ | ||
673 | typedef enum { | ||
674 | WMI_TKIP_CM_DISABLE = 0x0, | ||
675 | WMI_TKIP_CM_ENABLE = 0x1, | ||
676 | } WMI_TKIP_CM_CONTROL; | ||
677 | |||
678 | typedef PREPACK struct { | ||
679 | u8 cm_en; /* WMI_TKIP_CM_CONTROL */ | ||
680 | } POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD; | ||
681 | |||
682 | /* | ||
683 | * WMI_SET_PMKID_CMDID | ||
684 | */ | ||
685 | |||
686 | #define WMI_PMKID_LEN 16 | ||
687 | |||
688 | typedef enum { | ||
689 | PMKID_DISABLE = 0, | ||
690 | PMKID_ENABLE = 1, | ||
691 | } PMKID_ENABLE_FLG; | ||
692 | |||
693 | typedef PREPACK struct { | ||
694 | u8 bssid[ATH_MAC_LEN]; | ||
695 | u8 enable; /* PMKID_ENABLE_FLG */ | ||
696 | u8 pmkid[WMI_PMKID_LEN]; | ||
697 | } POSTPACK WMI_SET_PMKID_CMD; | ||
698 | |||
699 | /* | ||
700 | * WMI_START_SCAN_CMD | ||
701 | */ | ||
702 | typedef enum { | ||
703 | WMI_LONG_SCAN = 0, | ||
704 | WMI_SHORT_SCAN = 1, | ||
705 | } WMI_SCAN_TYPE; | ||
706 | |||
707 | typedef PREPACK struct { | ||
708 | u32 forceFgScan; | ||
709 | u32 isLegacy; /* For Legacy Cisco AP compatibility */ | ||
710 | u32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */ | ||
711 | u32 forceScanInterval; /* Time interval between scans (milliseconds)*/ | ||
712 | u8 scanType; /* WMI_SCAN_TYPE */ | ||
713 | u8 numChannels; /* how many channels follow */ | ||
714 | u16 channelList[1]; /* channels in Mhz */ | ||
715 | } POSTPACK WMI_START_SCAN_CMD; | ||
716 | |||
717 | /* | ||
718 | * WMI_SET_SCAN_PARAMS_CMDID | ||
719 | */ | ||
720 | #define WMI_SHORTSCANRATIO_DEFAULT 3 | ||
721 | /* | ||
722 | * Warning: ScanCtrlFlag value of 0xFF is used to disable all flags in WMI_SCAN_PARAMS_CMD | ||
723 | * Do not add any more flags to WMI_SCAN_CTRL_FLAG_BITS | ||
724 | */ | ||
725 | typedef enum { | ||
726 | CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ | ||
727 | SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ | ||
728 | /* already connected to */ | ||
729 | ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ | ||
730 | ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ | ||
731 | REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ | ||
732 | ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't | ||
733 | scan after a disconnect event */ | ||
734 | ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */ | ||
735 | } WMI_SCAN_CTRL_FLAGS_BITS; | ||
736 | |||
737 | #define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) | ||
738 | #define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) | ||
739 | #define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) | ||
740 | #define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) | ||
741 | #define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) | ||
742 | #define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) | ||
743 | #define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) | ||
744 | |||
745 | #define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS) | ||
746 | |||
747 | |||
748 | typedef PREPACK struct { | ||
749 | u16 fg_start_period; /* seconds */ | ||
750 | u16 fg_end_period; /* seconds */ | ||
751 | u16 bg_period; /* seconds */ | ||
752 | u16 maxact_chdwell_time; /* msec */ | ||
753 | u16 pas_chdwell_time; /* msec */ | ||
754 | u8 shortScanRatio; /* how many shorts scan for one long */ | ||
755 | u8 scanCtrlFlags; | ||
756 | u16 minact_chdwell_time; /* msec */ | ||
757 | u16 maxact_scan_per_ssid; /* max active scans per ssid */ | ||
758 | u32 max_dfsch_act_time; /* msecs */ | ||
759 | } POSTPACK WMI_SCAN_PARAMS_CMD; | ||
760 | |||
761 | /* | ||
762 | * WMI_SET_BSS_FILTER_CMDID | ||
763 | */ | ||
764 | typedef enum { | ||
765 | NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ | ||
766 | ALL_BSS_FILTER, /* all beacons forwarded */ | ||
767 | PROFILE_FILTER, /* only beacons matching profile */ | ||
768 | ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ | ||
769 | CURRENT_BSS_FILTER, /* only beacons matching current BSS */ | ||
770 | ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ | ||
771 | PROBED_SSID_FILTER, /* beacons matching probed ssid */ | ||
772 | LAST_BSS_FILTER, /* marker only */ | ||
773 | } WMI_BSS_FILTER; | ||
774 | |||
775 | typedef PREPACK struct { | ||
776 | u8 bssFilter; /* see WMI_BSS_FILTER */ | ||
777 | u8 reserved1; /* For alignment */ | ||
778 | u16 reserved2; /* For alignment */ | ||
779 | u32 ieMask; | ||
780 | } POSTPACK WMI_BSS_FILTER_CMD; | ||
781 | |||
782 | /* | ||
783 | * WMI_SET_PROBED_SSID_CMDID | ||
784 | */ | ||
785 | #define MAX_PROBED_SSID_INDEX 9 | ||
786 | |||
787 | typedef enum { | ||
788 | DISABLE_SSID_FLAG = 0, /* disables entry */ | ||
789 | SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ | ||
790 | ANY_SSID_FLAG = 0x02, /* probes for any ssid */ | ||
791 | } WMI_SSID_FLAG; | ||
792 | |||
793 | typedef PREPACK struct { | ||
794 | u8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */ | ||
795 | u8 flag; /* WMI_SSID_FLG */ | ||
796 | u8 ssidLength; | ||
797 | u8 ssid[32]; | ||
798 | } POSTPACK WMI_PROBED_SSID_CMD; | ||
799 | |||
800 | /* | ||
801 | * WMI_SET_LISTEN_INT_CMDID | ||
802 | * The Listen interval is between 15 and 3000 TUs | ||
803 | */ | ||
804 | #define MIN_LISTEN_INTERVAL 15 | ||
805 | #define MAX_LISTEN_INTERVAL 5000 | ||
806 | #define MIN_LISTEN_BEACONS 1 | ||
807 | #define MAX_LISTEN_BEACONS 50 | ||
808 | |||
809 | typedef PREPACK struct { | ||
810 | u16 listenInterval; | ||
811 | u16 numBeacons; | ||
812 | } POSTPACK WMI_LISTEN_INT_CMD; | ||
813 | |||
814 | /* | ||
815 | * WMI_SET_BEACON_INT_CMDID | ||
816 | */ | ||
817 | typedef PREPACK struct { | ||
818 | u16 beaconInterval; | ||
819 | } POSTPACK WMI_BEACON_INT_CMD; | ||
820 | |||
821 | /* | ||
822 | * WMI_SET_BMISS_TIME_CMDID | ||
823 | * valid values are between 1000 and 5000 TUs | ||
824 | */ | ||
825 | |||
826 | #define MIN_BMISS_TIME 1000 | ||
827 | #define MAX_BMISS_TIME 5000 | ||
828 | #define MIN_BMISS_BEACONS 1 | ||
829 | #define MAX_BMISS_BEACONS 50 | ||
830 | |||
831 | typedef PREPACK struct { | ||
832 | u16 bmissTime; | ||
833 | u16 numBeacons; | ||
834 | } POSTPACK WMI_BMISS_TIME_CMD; | ||
835 | |||
836 | /* | ||
837 | * WMI_SET_POWER_MODE_CMDID | ||
838 | */ | ||
839 | typedef enum { | ||
840 | REC_POWER = 0x01, | ||
841 | MAX_PERF_POWER, | ||
842 | } WMI_POWER_MODE; | ||
843 | |||
844 | typedef PREPACK struct { | ||
845 | u8 powerMode; /* WMI_POWER_MODE */ | ||
846 | } POSTPACK WMI_POWER_MODE_CMD; | ||
847 | |||
848 | typedef PREPACK struct { | ||
849 | s8 status; /* WMI_SET_PARAMS_REPLY */ | ||
850 | } POSTPACK WMI_SET_PARAMS_REPLY; | ||
851 | |||
852 | typedef PREPACK struct { | ||
853 | u32 opcode; | ||
854 | u32 length; | ||
855 | char buffer[1]; /* WMI_SET_PARAMS */ | ||
856 | } POSTPACK WMI_SET_PARAMS_CMD; | ||
857 | |||
858 | typedef PREPACK struct { | ||
859 | u8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */ | ||
860 | } POSTPACK WMI_SET_MCAST_FILTER_CMD; | ||
861 | |||
862 | typedef PREPACK struct { | ||
863 | u8 enable; /* WMI_MCAST_FILTER */ | ||
864 | } POSTPACK WMI_MCAST_FILTER_CMD; | ||
865 | |||
866 | /* | ||
867 | * WMI_SET_POWER_PARAMS_CMDID | ||
868 | */ | ||
869 | typedef enum { | ||
870 | IGNORE_DTIM = 0x01, | ||
871 | NORMAL_DTIM = 0x02, | ||
872 | STICK_DTIM = 0x03, | ||
873 | AUTO_DTIM = 0x04, | ||
874 | } WMI_DTIM_POLICY; | ||
875 | |||
876 | /* Policy to determnine whether TX should wakeup WLAN if sleeping */ | ||
877 | typedef enum { | ||
878 | TX_WAKEUP_UPON_SLEEP = 1, | ||
879 | TX_DONT_WAKEUP_UPON_SLEEP = 2 | ||
880 | } WMI_TX_WAKEUP_POLICY_UPON_SLEEP; | ||
881 | |||
882 | /* | ||
883 | * Policy to determnine whether power save failure event should be sent to | ||
884 | * host during scanning | ||
885 | */ | ||
886 | typedef enum { | ||
887 | SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1, | ||
888 | IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2, | ||
889 | } POWER_SAVE_FAIL_EVENT_POLICY; | ||
890 | |||
891 | typedef PREPACK struct { | ||
892 | u16 idle_period; /* msec */ | ||
893 | u16 pspoll_number; | ||
894 | u16 dtim_policy; | ||
895 | u16 tx_wakeup_policy; | ||
896 | u16 num_tx_to_wakeup; | ||
897 | u16 ps_fail_event_policy; | ||
898 | } POSTPACK WMI_POWER_PARAMS_CMD; | ||
899 | |||
900 | /* Adhoc power save types */ | ||
901 | typedef enum { | ||
902 | ADHOC_PS_DISABLE=1, | ||
903 | ADHOC_PS_ATH=2, | ||
904 | ADHOC_PS_IEEE=3, | ||
905 | ADHOC_PS_OTHER=4, | ||
906 | } WMI_ADHOC_PS_TYPE; | ||
907 | |||
908 | typedef PREPACK struct { | ||
909 | u8 power_saving; | ||
910 | u8 ttl; /* number of beacon periods */ | ||
911 | u16 atim_windows; /* msec */ | ||
912 | u16 timeout_value; /* msec */ | ||
913 | } POSTPACK WMI_IBSS_PM_CAPS_CMD; | ||
914 | |||
915 | /* AP power save types */ | ||
916 | typedef enum { | ||
917 | AP_PS_DISABLE=1, | ||
918 | AP_PS_ATH=2, | ||
919 | } WMI_AP_PS_TYPE; | ||
920 | |||
921 | typedef PREPACK struct { | ||
922 | u32 idle_time; /* in msec */ | ||
923 | u32 ps_period; /* in usec */ | ||
924 | u8 sleep_period; /* in ps periods */ | ||
925 | u8 psType; | ||
926 | } POSTPACK WMI_AP_PS_CMD; | ||
927 | |||
928 | /* | ||
929 | * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID | ||
930 | */ | ||
931 | typedef enum { | ||
932 | IGNORE_TIM_ALL_QUEUES_APSD = 0, | ||
933 | PROCESS_TIM_ALL_QUEUES_APSD = 1, | ||
934 | IGNORE_TIM_SIMULATED_APSD = 2, | ||
935 | PROCESS_TIM_SIMULATED_APSD = 3, | ||
936 | } APSD_TIM_POLICY; | ||
937 | |||
938 | typedef PREPACK struct { | ||
939 | u16 psPollTimeout; /* msec */ | ||
940 | u16 triggerTimeout; /* msec */ | ||
941 | u32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */ | ||
942 | u32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */ | ||
943 | } POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD; | ||
944 | |||
945 | /* | ||
946 | * WMI_SET_VOICE_PKT_SIZE_CMDID | ||
947 | */ | ||
948 | typedef PREPACK struct { | ||
949 | u16 voicePktSize; | ||
950 | } POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD; | ||
951 | |||
952 | /* | ||
953 | * WMI_SET_MAX_SP_LEN_CMDID | ||
954 | */ | ||
955 | typedef enum { | ||
956 | DELIVER_ALL_PKT = 0x0, | ||
957 | DELIVER_2_PKT = 0x1, | ||
958 | DELIVER_4_PKT = 0x2, | ||
959 | DELIVER_6_PKT = 0x3, | ||
960 | } APSD_SP_LEN_TYPE; | ||
961 | |||
962 | typedef PREPACK struct { | ||
963 | u8 maxSPLen; | ||
964 | } POSTPACK WMI_SET_MAX_SP_LEN_CMD; | ||
965 | |||
966 | /* | ||
967 | * WMI_SET_DISC_TIMEOUT_CMDID | ||
968 | */ | ||
969 | typedef PREPACK struct { | ||
970 | u8 disconnectTimeout; /* seconds */ | ||
971 | } POSTPACK WMI_DISC_TIMEOUT_CMD; | ||
972 | |||
973 | typedef enum { | ||
974 | UPLINK_TRAFFIC = 0, | ||
975 | DNLINK_TRAFFIC = 1, | ||
976 | BIDIR_TRAFFIC = 2, | ||
977 | } DIR_TYPE; | ||
978 | |||
979 | typedef enum { | ||
980 | DISABLE_FOR_THIS_AC = 0, | ||
981 | ENABLE_FOR_THIS_AC = 1, | ||
982 | ENABLE_FOR_ALL_AC = 2, | ||
983 | } VOICEPS_CAP_TYPE; | ||
984 | |||
985 | typedef enum { | ||
986 | TRAFFIC_TYPE_APERIODIC = 0, | ||
987 | TRAFFIC_TYPE_PERIODIC = 1, | ||
988 | }TRAFFIC_TYPE; | ||
989 | |||
990 | /* | ||
991 | * WMI_SYNCHRONIZE_CMDID | ||
992 | */ | ||
993 | typedef PREPACK struct { | ||
994 | u8 dataSyncMap; | ||
995 | } POSTPACK WMI_SYNC_CMD; | ||
996 | |||
997 | /* | ||
998 | * WMI_CREATE_PSTREAM_CMDID | ||
999 | */ | ||
1000 | typedef PREPACK struct { | ||
1001 | u32 minServiceInt; /* in milli-sec */ | ||
1002 | u32 maxServiceInt; /* in milli-sec */ | ||
1003 | u32 inactivityInt; /* in milli-sec */ | ||
1004 | u32 suspensionInt; /* in milli-sec */ | ||
1005 | u32 serviceStartTime; | ||
1006 | u32 minDataRate; /* in bps */ | ||
1007 | u32 meanDataRate; /* in bps */ | ||
1008 | u32 peakDataRate; /* in bps */ | ||
1009 | u32 maxBurstSize; | ||
1010 | u32 delayBound; | ||
1011 | u32 minPhyRate; /* in bps */ | ||
1012 | u32 sba; | ||
1013 | u32 mediumTime; | ||
1014 | u16 nominalMSDU; /* in octects */ | ||
1015 | u16 maxMSDU; /* in octects */ | ||
1016 | u8 trafficClass; | ||
1017 | u8 trafficDirection; /* DIR_TYPE */ | ||
1018 | u8 rxQueueNum; | ||
1019 | u8 trafficType; /* TRAFFIC_TYPE */ | ||
1020 | u8 voicePSCapability; /* VOICEPS_CAP_TYPE */ | ||
1021 | u8 tsid; | ||
1022 | u8 userPriority; /* 802.1D user priority */ | ||
1023 | u8 nominalPHY; /* nominal phy rate */ | ||
1024 | } POSTPACK WMI_CREATE_PSTREAM_CMD; | ||
1025 | |||
1026 | /* | ||
1027 | * WMI_DELETE_PSTREAM_CMDID | ||
1028 | */ | ||
1029 | typedef PREPACK struct { | ||
1030 | u8 txQueueNumber; | ||
1031 | u8 rxQueueNumber; | ||
1032 | u8 trafficDirection; | ||
1033 | u8 trafficClass; | ||
1034 | u8 tsid; | ||
1035 | } POSTPACK WMI_DELETE_PSTREAM_CMD; | ||
1036 | |||
1037 | /* | ||
1038 | * WMI_SET_CHANNEL_PARAMS_CMDID | ||
1039 | */ | ||
1040 | typedef enum { | ||
1041 | WMI_11A_MODE = 0x1, | ||
1042 | WMI_11G_MODE = 0x2, | ||
1043 | WMI_11AG_MODE = 0x3, | ||
1044 | WMI_11B_MODE = 0x4, | ||
1045 | WMI_11GONLY_MODE = 0x5, | ||
1046 | } WMI_PHY_MODE; | ||
1047 | |||
1048 | #define WMI_MAX_CHANNELS 32 | ||
1049 | |||
1050 | typedef PREPACK struct { | ||
1051 | u8 reserved1; | ||
1052 | u8 scanParam; /* set if enable scan */ | ||
1053 | u8 phyMode; /* see WMI_PHY_MODE */ | ||
1054 | u8 numChannels; /* how many channels follow */ | ||
1055 | u16 channelList[1]; /* channels in Mhz */ | ||
1056 | } POSTPACK WMI_CHANNEL_PARAMS_CMD; | ||
1057 | |||
1058 | |||
1059 | /* | ||
1060 | * WMI_RSSI_THRESHOLD_PARAMS_CMDID | ||
1061 | * Setting the polltime to 0 would disable polling. | ||
1062 | * Threshold values are in the ascending order, and should agree to: | ||
1063 | * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal | ||
1064 | * < highThreshold_upperVal) | ||
1065 | */ | ||
1066 | |||
1067 | typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{ | ||
1068 | u32 pollTime; /* Polling time as a factor of LI */ | ||
1069 | s16 thresholdAbove1_Val; /* lowest of upper */ | ||
1070 | s16 thresholdAbove2_Val; | ||
1071 | s16 thresholdAbove3_Val; | ||
1072 | s16 thresholdAbove4_Val; | ||
1073 | s16 thresholdAbove5_Val; | ||
1074 | s16 thresholdAbove6_Val; /* highest of upper */ | ||
1075 | s16 thresholdBelow1_Val; /* lowest of bellow */ | ||
1076 | s16 thresholdBelow2_Val; | ||
1077 | s16 thresholdBelow3_Val; | ||
1078 | s16 thresholdBelow4_Val; | ||
1079 | s16 thresholdBelow5_Val; | ||
1080 | s16 thresholdBelow6_Val; /* highest of bellow */ | ||
1081 | u8 weight; /* "alpha" */ | ||
1082 | u8 reserved[3]; | ||
1083 | } POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD; | ||
1084 | |||
1085 | /* | ||
1086 | * WMI_SNR_THRESHOLD_PARAMS_CMDID | ||
1087 | * Setting the polltime to 0 would disable polling. | ||
1088 | */ | ||
1089 | |||
1090 | typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{ | ||
1091 | u32 pollTime; /* Polling time as a factor of LI */ | ||
1092 | u8 weight; /* "alpha" */ | ||
1093 | u8 thresholdAbove1_Val; /* lowest of uppper*/ | ||
1094 | u8 thresholdAbove2_Val; | ||
1095 | u8 thresholdAbove3_Val; | ||
1096 | u8 thresholdAbove4_Val; /* highest of upper */ | ||
1097 | u8 thresholdBelow1_Val; /* lowest of bellow */ | ||
1098 | u8 thresholdBelow2_Val; | ||
1099 | u8 thresholdBelow3_Val; | ||
1100 | u8 thresholdBelow4_Val; /* highest of bellow */ | ||
1101 | u8 reserved[3]; | ||
1102 | } POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD; | ||
1103 | |||
1104 | /* | ||
1105 | * WMI_LQ_THRESHOLD_PARAMS_CMDID | ||
1106 | */ | ||
1107 | typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS { | ||
1108 | u8 enable; | ||
1109 | u8 thresholdAbove1_Val; | ||
1110 | u8 thresholdAbove2_Val; | ||
1111 | u8 thresholdAbove3_Val; | ||
1112 | u8 thresholdAbove4_Val; | ||
1113 | u8 thresholdBelow1_Val; | ||
1114 | u8 thresholdBelow2_Val; | ||
1115 | u8 thresholdBelow3_Val; | ||
1116 | u8 thresholdBelow4_Val; | ||
1117 | u8 reserved[3]; | ||
1118 | } POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD; | ||
1119 | |||
1120 | typedef enum { | ||
1121 | WMI_LPREAMBLE_DISABLED = 0, | ||
1122 | WMI_LPREAMBLE_ENABLED | ||
1123 | } WMI_LPREAMBLE_STATUS; | ||
1124 | |||
1125 | typedef enum { | ||
1126 | WMI_IGNORE_BARKER_IN_ERP = 0, | ||
1127 | WMI_DONOT_IGNORE_BARKER_IN_ERP | ||
1128 | } WMI_PREAMBLE_POLICY; | ||
1129 | |||
1130 | typedef PREPACK struct { | ||
1131 | u8 status; | ||
1132 | u8 preamblePolicy; | ||
1133 | }POSTPACK WMI_SET_LPREAMBLE_CMD; | ||
1134 | |||
1135 | typedef PREPACK struct { | ||
1136 | u16 threshold; | ||
1137 | }POSTPACK WMI_SET_RTS_CMD; | ||
1138 | |||
1139 | /* | ||
1140 | * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID | ||
1141 | * Sets the error reporting event bitmask in target. Target clears it | ||
1142 | * upon an error. Subsequent errors are counted, but not reported | ||
1143 | * via event, unless the bitmask is set again. | ||
1144 | */ | ||
1145 | typedef PREPACK struct { | ||
1146 | u32 bitmask; | ||
1147 | } POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; | ||
1148 | |||
1149 | /* | ||
1150 | * WMI_SET_TX_PWR_CMDID | ||
1151 | */ | ||
1152 | typedef PREPACK struct { | ||
1153 | u8 dbM; /* in dbM units */ | ||
1154 | } POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; | ||
1155 | |||
1156 | /* | ||
1157 | * WMI_SET_ASSOC_INFO_CMDID | ||
1158 | * | ||
1159 | * A maximum of 2 private IEs can be sent in the [Re]Assoc request. | ||
1160 | * A 3rd one, the CCX version IE can also be set from the host. | ||
1161 | */ | ||
1162 | #define WMI_MAX_ASSOC_INFO_TYPE 2 | ||
1163 | #define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */ | ||
1164 | |||
1165 | #define WMI_MAX_ASSOC_INFO_LEN 240 | ||
1166 | |||
1167 | typedef PREPACK struct { | ||
1168 | u8 ieType; | ||
1169 | u8 bufferSize; | ||
1170 | u8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */ | ||
1171 | } POSTPACK WMI_SET_ASSOC_INFO_CMD; | ||
1172 | |||
1173 | |||
1174 | /* | ||
1175 | * WMI_GET_TX_PWR_CMDID does not take any parameters | ||
1176 | */ | ||
1177 | |||
1178 | /* | ||
1179 | * WMI_ADD_BAD_AP_CMDID | ||
1180 | */ | ||
1181 | #define WMI_MAX_BAD_AP_INDEX 1 | ||
1182 | |||
1183 | typedef PREPACK struct { | ||
1184 | u8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ | ||
1185 | u8 bssid[ATH_MAC_LEN]; | ||
1186 | } POSTPACK WMI_ADD_BAD_AP_CMD; | ||
1187 | |||
1188 | /* | ||
1189 | * WMI_DELETE_BAD_AP_CMDID | ||
1190 | */ | ||
1191 | typedef PREPACK struct { | ||
1192 | u8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ | ||
1193 | } POSTPACK WMI_DELETE_BAD_AP_CMD; | ||
1194 | |||
1195 | /* | ||
1196 | * WMI_SET_ACCESS_PARAMS_CMDID | ||
1197 | */ | ||
1198 | #define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ | ||
1199 | #define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ | ||
1200 | #define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ | ||
1201 | #define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ | ||
1202 | #define WMI_DEFAULT_AIFSN_ACPARAM 2 | ||
1203 | #define WMI_MAX_AIFSN_ACPARAM 15 | ||
1204 | typedef PREPACK struct { | ||
1205 | u16 txop; /* in units of 32 usec */ | ||
1206 | u8 eCWmin; | ||
1207 | u8 eCWmax; | ||
1208 | u8 aifsn; | ||
1209 | u8 ac; | ||
1210 | } POSTPACK WMI_SET_ACCESS_PARAMS_CMD; | ||
1211 | |||
1212 | |||
1213 | /* | ||
1214 | * WMI_SET_RETRY_LIMITS_CMDID | ||
1215 | * | ||
1216 | * This command is used to customize the number of retries the | ||
1217 | * wlan device will perform on a given frame. | ||
1218 | */ | ||
1219 | #define WMI_MIN_RETRIES 2 | ||
1220 | #define WMI_MAX_RETRIES 13 | ||
1221 | typedef enum { | ||
1222 | MGMT_FRAMETYPE = 0, | ||
1223 | CONTROL_FRAMETYPE = 1, | ||
1224 | DATA_FRAMETYPE = 2 | ||
1225 | } WMI_FRAMETYPE; | ||
1226 | |||
1227 | typedef PREPACK struct { | ||
1228 | u8 frameType; /* WMI_FRAMETYPE */ | ||
1229 | u8 trafficClass; /* applies only to DATA_FRAMETYPE */ | ||
1230 | u8 maxRetries; | ||
1231 | u8 enableNotify; | ||
1232 | } POSTPACK WMI_SET_RETRY_LIMITS_CMD; | ||
1233 | |||
1234 | /* | ||
1235 | * WMI_SET_ROAM_CTRL_CMDID | ||
1236 | * | ||
1237 | * This command is used to influence the Roaming behaviour | ||
1238 | * Set the host biases of the BSSs before setting the roam mode as bias | ||
1239 | * based. | ||
1240 | */ | ||
1241 | |||
1242 | /* | ||
1243 | * Different types of Roam Control | ||
1244 | */ | ||
1245 | |||
1246 | typedef enum { | ||
1247 | WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */ | ||
1248 | WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */ | ||
1249 | WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */ | ||
1250 | WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */ | ||
1251 | } WMI_ROAM_CTRL_TYPE; | ||
1252 | |||
1253 | #define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM | ||
1254 | #define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS | ||
1255 | |||
1256 | /* | ||
1257 | * ROAM MODES | ||
1258 | */ | ||
1259 | |||
1260 | typedef enum { | ||
1261 | WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */ | ||
1262 | WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */ | ||
1263 | WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */ | ||
1264 | } WMI_ROAM_MODE; | ||
1265 | |||
1266 | /* | ||
1267 | * BSS HOST BIAS INFO | ||
1268 | */ | ||
1269 | |||
1270 | typedef PREPACK struct { | ||
1271 | u8 bssid[ATH_MAC_LEN]; | ||
1272 | s8 bias; | ||
1273 | } POSTPACK WMI_BSS_BIAS; | ||
1274 | |||
1275 | typedef PREPACK struct { | ||
1276 | u8 numBss; | ||
1277 | WMI_BSS_BIAS bssBias[1]; | ||
1278 | } POSTPACK WMI_BSS_BIAS_INFO; | ||
1279 | |||
1280 | typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS { | ||
1281 | u16 lowrssi_scan_period; | ||
1282 | s16 lowrssi_scan_threshold; | ||
1283 | s16 lowrssi_roam_threshold; | ||
1284 | u8 roam_rssi_floor; | ||
1285 | u8 reserved[1]; /* For alignment */ | ||
1286 | } POSTPACK WMI_LOWRSSI_SCAN_PARAMS; | ||
1287 | |||
1288 | typedef PREPACK struct { | ||
1289 | PREPACK union { | ||
1290 | u8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ | ||
1291 | u8 roamMode; /* WMI_SET_ROAM_MODE */ | ||
1292 | WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ | ||
1293 | WMI_LOWRSSI_SCAN_PARAMS lrScanParams; | ||
1294 | } POSTPACK info; | ||
1295 | u8 roamCtrlType ; | ||
1296 | } POSTPACK WMI_SET_ROAM_CTRL_CMD; | ||
1297 | |||
1298 | /* | ||
1299 | * WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID | ||
1300 | */ | ||
1301 | typedef enum { | ||
1302 | BT_WLAN_CONN_PRECDENCE_WLAN=0, /* Default */ | ||
1303 | BT_WLAN_CONN_PRECDENCE_PAL, | ||
1304 | } BT_WLAN_CONN_PRECEDENCE; | ||
1305 | |||
1306 | typedef PREPACK struct { | ||
1307 | u8 precedence; | ||
1308 | } POSTPACK WMI_SET_BT_WLAN_CONN_PRECEDENCE; | ||
1309 | |||
1310 | /* | ||
1311 | * WMI_ENABLE_RM_CMDID | ||
1312 | */ | ||
1313 | typedef PREPACK struct { | ||
1314 | u32 enable_radio_measurements; | ||
1315 | } POSTPACK WMI_ENABLE_RM_CMD; | ||
1316 | |||
1317 | /* | ||
1318 | * WMI_SET_MAX_OFFHOME_DURATION_CMDID | ||
1319 | */ | ||
1320 | typedef PREPACK struct { | ||
1321 | u8 max_offhome_duration; | ||
1322 | } POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD; | ||
1323 | |||
1324 | typedef PREPACK struct { | ||
1325 | u32 frequency; | ||
1326 | u8 threshold; | ||
1327 | } POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD; | ||
1328 | /*---------------------- BTCOEX RELATED -------------------------------------*/ | ||
1329 | /*----------------------COMMON to AR6002 and AR6003 -------------------------*/ | ||
1330 | typedef enum { | ||
1331 | BT_STREAM_UNDEF = 0, | ||
1332 | BT_STREAM_SCO, /* SCO stream */ | ||
1333 | BT_STREAM_A2DP, /* A2DP stream */ | ||
1334 | BT_STREAM_SCAN, /* BT Discovery or Page */ | ||
1335 | BT_STREAM_ESCO, | ||
1336 | BT_STREAM_MAX | ||
1337 | } BT_STREAM_TYPE; | ||
1338 | |||
1339 | typedef enum { | ||
1340 | BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1, | ||
1341 | BT_PARAM_SCO_PSPOLL_LATENCY_HALF, | ||
1342 | BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH, | ||
1343 | } BT_PARAMS_SCO_PSPOLL_LATENCY; | ||
1344 | |||
1345 | typedef enum { | ||
1346 | BT_PARAMS_SCO_STOMP_SCO_NEVER =1, | ||
1347 | BT_PARAMS_SCO_STOMP_SCO_ALWAYS, | ||
1348 | BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI, | ||
1349 | } BT_PARAMS_SCO_STOMP_RULES; | ||
1350 | |||
1351 | typedef enum { | ||
1352 | BT_STATUS_UNDEF = 0, | ||
1353 | BT_STATUS_ON, | ||
1354 | BT_STATUS_OFF, | ||
1355 | BT_STATUS_MAX | ||
1356 | } BT_STREAM_STATUS; | ||
1357 | |||
1358 | typedef PREPACK struct { | ||
1359 | u8 streamType; | ||
1360 | u8 status; | ||
1361 | } POSTPACK WMI_SET_BT_STATUS_CMD; | ||
1362 | |||
1363 | typedef enum { | ||
1364 | BT_ANT_TYPE_UNDEF=0, | ||
1365 | BT_ANT_TYPE_DUAL, | ||
1366 | BT_ANT_TYPE_SPLITTER, | ||
1367 | BT_ANT_TYPE_SWITCH, | ||
1368 | BT_ANT_TYPE_HIGH_ISO_DUAL | ||
1369 | } BT_ANT_FRONTEND_CONFIG; | ||
1370 | |||
1371 | typedef enum { | ||
1372 | BT_COLOCATED_DEV_BTS4020=0, | ||
1373 | BT_COLCATED_DEV_CSR , | ||
1374 | BT_COLOCATED_DEV_VALKYRIE | ||
1375 | } BT_COLOCATED_DEV_TYPE; | ||
1376 | |||
1377 | /*********************** Applicable to AR6002 ONLY ******************************/ | ||
1378 | |||
1379 | typedef enum { | ||
1380 | BT_PARAM_SCO = 1, /* SCO stream parameters */ | ||
1381 | BT_PARAM_A2DP , | ||
1382 | BT_PARAM_ANTENNA_CONFIG, | ||
1383 | BT_PARAM_COLOCATED_BT_DEVICE, | ||
1384 | BT_PARAM_ACLCOEX, | ||
1385 | BT_PARAM_11A_SEPARATE_ANT, | ||
1386 | BT_PARAM_MAX | ||
1387 | } BT_PARAM_TYPE; | ||
1388 | |||
1389 | |||
1390 | #define BT_SCO_ALLOW_CLOSE_RANGE_OPT (1 << 0) | ||
1391 | #define BT_SCO_FORCE_AWAKE_OPT (1 << 1) | ||
1392 | #define BT_SCO_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) | ||
1393 | #define BT_SCO_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) | ||
1394 | #define BT_SCO_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) | ||
1395 | #define BT_SCO_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) | ||
1396 | #define BT_SCO_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) | ||
1397 | #define BT_SCO_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) | ||
1398 | #define BT_SCO_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) | ||
1399 | #define BT_SCO_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) | ||
1400 | |||
1401 | typedef PREPACK struct { | ||
1402 | u32 numScoCyclesForceTrigger; /* Number SCO cycles after which | ||
1403 | force a pspoll. default = 10 */ | ||
1404 | u32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt | ||
1405 | in response for ps-poll, | ||
1406 | default = 10 msecs */ | ||
1407 | u32 stompScoRules; | ||
1408 | u32 scoOptFlags; /* SCO Options Flags : | ||
1409 | bits: meaning: | ||
1410 | 0 Allow Close Range Optimization | ||
1411 | 1 Force awake during close range | ||
1412 | 2 If set use host supplied RSSI for OPT | ||
1413 | 3 If set use host supplied RTS COUNT for OPT | ||
1414 | 4..7 Unused | ||
1415 | 8..15 Low Data Rate Min Cnt | ||
1416 | 16..23 Low Data Rate Max Cnt | ||
1417 | */ | ||
1418 | |||
1419 | u8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing | ||
1420 | if stomped */ | ||
1421 | u8 stompDutyCyleMaxVal; /*firm ware increases stomp duty cycle | ||
1422 | gradually uptill this value on need basis*/ | ||
1423 | u8 psPollLatencyFraction; /* Fraction of idle | ||
1424 | period, within which | ||
1425 | additional ps-polls | ||
1426 | can be queued */ | ||
1427 | u8 noSCOSlots; /* Number of SCO Tx/Rx slots. | ||
1428 | HVx, EV3, 2EV3 = 2 */ | ||
1429 | u8 noIdleSlots; /* Number of Bluetooth idle slots between | ||
1430 | consecutive SCO Tx/Rx slots | ||
1431 | HVx, EV3 = 4 | ||
1432 | 2EV3 = 10 */ | ||
1433 | u8 scoOptOffRssi;/*RSSI value below which we go to ps poll*/ | ||
1434 | u8 scoOptOnRssi; /*RSSI value above which we reenter opt mode*/ | ||
1435 | u8 scoOptRtsCount; | ||
1436 | } POSTPACK BT_PARAMS_SCO; | ||
1437 | |||
1438 | #define BT_A2DP_ALLOW_CLOSE_RANGE_OPT (1 << 0) | ||
1439 | #define BT_A2DP_FORCE_AWAKE_OPT (1 << 1) | ||
1440 | #define BT_A2DP_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) | ||
1441 | #define BT_A2DP_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) | ||
1442 | #define BT_A2DP_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) | ||
1443 | #define BT_A2DP_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) | ||
1444 | #define BT_A2DP_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) | ||
1445 | #define BT_A2DP_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) | ||
1446 | #define BT_A2DP_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) | ||
1447 | #define BT_A2DP_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) | ||
1448 | |||
1449 | typedef PREPACK struct { | ||
1450 | u32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for | ||
1451 | wlan, after it identifies the idle time | ||
1452 | default (30 msecs) */ | ||
1453 | u32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames | ||
1454 | to replenish Wlan Usage limit (default 3) */ | ||
1455 | u32 a2dpDataRespTimeout; | ||
1456 | u32 a2dpOptFlags; /* A2DP Option flags: | ||
1457 | bits: meaning: | ||
1458 | 0 Allow Close Range Optimization | ||
1459 | 1 Force awake during close range | ||
1460 | 2 If set use host supplied RSSI for OPT | ||
1461 | 3 If set use host supplied RTS COUNT for OPT | ||
1462 | 4..7 Unused | ||
1463 | 8..15 Low Data Rate Min Cnt | ||
1464 | 16..23 Low Data Rate Max Cnt | ||
1465 | */ | ||
1466 | u8 isCoLocatedBtRoleMaster; | ||
1467 | u8 a2dpOptOffRssi;/*RSSI value below which we go to ps poll*/ | ||
1468 | u8 a2dpOptOnRssi; /*RSSI value above which we reenter opt mode*/ | ||
1469 | u8 a2dpOptRtsCount; | ||
1470 | }POSTPACK BT_PARAMS_A2DP; | ||
1471 | |||
1472 | /* During BT ftp/ BT OPP or any another data based acl profile on bluetooth | ||
1473 | (non a2dp).*/ | ||
1474 | typedef PREPACK struct { | ||
1475 | u32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp) | ||
1476 | coexistence (default 30 msecs) */ | ||
1477 | u32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence | ||
1478 | (default 30 msecs)*/ | ||
1479 | u32 aclDataRespTimeout; | ||
1480 | u32 aclDetectTimeout; /* ACL coexistence enabled if we get | ||
1481 | 10 Pkts in X msec(default 100 msecs) */ | ||
1482 | u32 aclmaxPktCnt; /* No of ACL pkts to receive before | ||
1483 | enabling ACL coex */ | ||
1484 | |||
1485 | }POSTPACK BT_PARAMS_ACLCOEX; | ||
1486 | |||
1487 | typedef PREPACK struct { | ||
1488 | PREPACK union { | ||
1489 | BT_PARAMS_SCO scoParams; | ||
1490 | BT_PARAMS_A2DP a2dpParams; | ||
1491 | BT_PARAMS_ACLCOEX aclCoexParams; | ||
1492 | u8 antType; /* 0 -Disabled (default) | ||
1493 | 1 - BT_ANT_TYPE_DUAL | ||
1494 | 2 - BT_ANT_TYPE_SPLITTER | ||
1495 | 3 - BT_ANT_TYPE_SWITCH */ | ||
1496 | u8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default) | ||
1497 | 1 - BT_COLCATED_DEV_CSR | ||
1498 | 2 - BT_COLOCATED_DEV_VALKYRIe | ||
1499 | */ | ||
1500 | } POSTPACK info; | ||
1501 | u8 paramType ; | ||
1502 | } POSTPACK WMI_SET_BT_PARAMS_CMD; | ||
1503 | |||
1504 | /************************ END AR6002 BTCOEX *******************************/ | ||
1505 | /*-----------------------AR6003 BTCOEX -----------------------------------*/ | ||
1506 | |||
1507 | /* ---------------WMI_SET_BTCOEX_FE_ANT_CMDID --------------------------*/ | ||
1508 | /* Indicates front end antenna configuration. This command needs to be issued | ||
1509 | * right after initialization and after WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID. | ||
1510 | * AR6003 enables coexistence and antenna switching based on the configuration. | ||
1511 | */ | ||
1512 | typedef enum { | ||
1513 | WMI_BTCOEX_NOT_ENABLED = 0, | ||
1514 | WMI_BTCOEX_FE_ANT_SINGLE =1, | ||
1515 | WMI_BTCOEX_FE_ANT_DUAL=2, | ||
1516 | WMI_BTCOEX_FE_ANT_DUAL_HIGH_ISO=3, | ||
1517 | WMI_BTCOEX_FE_ANT_TYPE_MAX | ||
1518 | }WMI_BTCOEX_FE_ANT_TYPE; | ||
1519 | |||
1520 | typedef PREPACK struct { | ||
1521 | u8 btcoexFeAntType; /* 1 - WMI_BTCOEX_FE_ANT_SINGLE for single antenna front end | ||
1522 | 2 - WMI_BTCOEX_FE_ANT_DUAL for dual antenna front end | ||
1523 | (for isolations less 35dB, for higher isolation there | ||
1524 | is not need to pass this command). | ||
1525 | (not implemented) | ||
1526 | */ | ||
1527 | }POSTPACK WMI_SET_BTCOEX_FE_ANT_CMD; | ||
1528 | |||
1529 | /* -------------WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID ----------------*/ | ||
1530 | /* Indicate the bluetooth chip to the firmware. Firmware can have different algorithm based | ||
1531 | * bluetooth chip type.Based on bluetooth device, different coexistence protocol would be used. | ||
1532 | */ | ||
1533 | typedef PREPACK struct { | ||
1534 | u8 btcoexCoLocatedBTdev; /*1 - Qcom BT (3 -wire PTA) | ||
1535 | 2 - CSR BT (3 wire PTA) | ||
1536 | 3 - Atheros 3001 BT (3 wire PTA) | ||
1537 | 4 - STE bluetooth (4-wire ePTA) | ||
1538 | 5 - Atheros 3002 BT (4-wire MCI) | ||
1539 | defaults= 3 (Atheros 3001 BT ) | ||
1540 | */ | ||
1541 | }POSTPACK WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD; | ||
1542 | |||
1543 | /* -------------WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID ------------*/ | ||
1544 | /* Configuration parameters during bluetooth inquiry and page. Page configuration | ||
1545 | * is applicable only on interfaces which can distinguish page (applicable only for ePTA - | ||
1546 | * STE bluetooth). | ||
1547 | * Bluetooth inquiry start and end is indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID. | ||
1548 | * During this the station will be power-save mode. | ||
1549 | */ | ||
1550 | typedef PREPACK struct { | ||
1551 | u32 btInquiryDataFetchFrequency;/* The frequency of querying the AP for data | ||
1552 | (via pspoll) is configured by this parameter. | ||
1553 | "default = 10 ms" */ | ||
1554 | |||
1555 | u32 protectBmissDurPostBtInquiry;/* The firmware will continue to be in inquiry state | ||
1556 | for configured duration, after inquiry completion | ||
1557 | . This is to ensure other bluetooth transactions | ||
1558 | (RDP, SDP profiles, link key exchange ...etc) | ||
1559 | goes through smoothly without wifi stomping. | ||
1560 | default = 10 secs*/ | ||
1561 | |||
1562 | u32 maxpageStomp; /*Applicable only for STE-BT interface. Currently not | ||
1563 | used */ | ||
1564 | u32 btInquiryPageFlag; /* Not used */ | ||
1565 | }POSTPACK WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD; | ||
1566 | |||
1567 | /*---------------------WMI_SET_BTCOEX_SCO_CONFIG_CMDID ---------------*/ | ||
1568 | /* Configure SCO parameters. These parameters would be used whenever firmware is indicated | ||
1569 | * of (e)SCO profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID). | ||
1570 | * Configration of BTCOEX_SCO_CONFIG data structure are common configuration and applies | ||
1571 | * ps-poll mode and opt mode. | ||
1572 | * Ps-poll Mode - Station is in power-save and retrieves downlink data between sco gaps. | ||
1573 | * Opt Mode - station is in awake state and access point can send data to station any time. | ||
1574 | * BTCOEX_PSPOLLMODE_SCO_CONFIG - Configuration applied only during ps-poll mode. | ||
1575 | * BTCOEX_OPTMODE_SCO_CONFIG - Configuration applied only during opt mode. | ||
1576 | */ | ||
1577 | #define WMI_SCO_CONFIG_FLAG_ALLOW_OPTIMIZATION (1 << 0) | ||
1578 | #define WMI_SCO_CONFIG_FLAG_IS_EDR_CAPABLE (1 << 1) | ||
1579 | #define WMI_SCO_CONFIG_FLAG_IS_BT_MASTER (1 << 2) | ||
1580 | #define WMI_SCO_CONFIG_FLAG_FW_DETECT_OF_PER (1 << 3) | ||
1581 | typedef PREPACK struct { | ||
1582 | u32 scoSlots; /* Number of SCO Tx/Rx slots. | ||
1583 | HVx, EV3, 2EV3 = 2 */ | ||
1584 | u32 scoIdleSlots; /* Number of Bluetooth idle slots between | ||
1585 | consecutive SCO Tx/Rx slots | ||
1586 | HVx, EV3 = 4 | ||
1587 | 2EV3 = 10 | ||
1588 | */ | ||
1589 | u32 scoFlags; /* SCO Options Flags : | ||
1590 | bits: meaning: | ||
1591 | 0 Allow Close Range Optimization | ||
1592 | 1 Is EDR capable or Not | ||
1593 | 2 IS Co-located Bt role Master | ||
1594 | 3 Firmware determines the periodicity of SCO. | ||
1595 | */ | ||
1596 | |||
1597 | u32 linkId; /* applicable to STE-BT - not used */ | ||
1598 | }POSTPACK BTCOEX_SCO_CONFIG; | ||
1599 | |||
1600 | typedef PREPACK struct { | ||
1601 | u32 scoCyclesForceTrigger; /* Number SCO cycles after which | ||
1602 | force a pspoll. default = 10 */ | ||
1603 | u32 scoDataResponseTimeout; /* Timeout Waiting for Downlink pkt | ||
1604 | in response for ps-poll, | ||
1605 | default = 20 msecs */ | ||
1606 | |||
1607 | u32 scoStompDutyCyleVal; /* not implemented */ | ||
1608 | |||
1609 | u32 scoStompDutyCyleMaxVal; /*Not implemented */ | ||
1610 | |||
1611 | u32 scoPsPollLatencyFraction; /* Fraction of idle | ||
1612 | period, within which | ||
1613 | additional ps-polls can be queued | ||
1614 | 1 - 1/4 of idle duration | ||
1615 | 2 - 1/2 of idle duration | ||
1616 | 3 - 3/4 of idle duration | ||
1617 | default =2 (1/2) | ||
1618 | */ | ||
1619 | }POSTPACK BTCOEX_PSPOLLMODE_SCO_CONFIG; | ||
1620 | |||
1621 | typedef PREPACK struct { | ||
1622 | u32 scoStompCntIn100ms;/*max number of SCO stomp in 100ms allowed in | ||
1623 | opt mode. If exceeds the configured value, | ||
1624 | switch to ps-poll mode | ||
1625 | default = 3 */ | ||
1626 | |||
1627 | u32 scoContStompMax; /* max number of continuous stomp allowed in opt mode. | ||
1628 | if exceeded switch to pspoll mode | ||
1629 | default = 3 */ | ||
1630 | |||
1631 | u32 scoMinlowRateMbps; /* Low rate threshold */ | ||
1632 | |||
1633 | u32 scoLowRateCnt; /* number of low rate pkts (< scoMinlowRateMbps) allowed in 100 ms. | ||
1634 | If exceeded switch/stay to ps-poll mode, lower stay in opt mode. | ||
1635 | default = 36 | ||
1636 | */ | ||
1637 | |||
1638 | u32 scoHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/ | ||
1639 | ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms, | ||
1640 | if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode. | ||
1641 | default = 5 (80% of high rates) | ||
1642 | */ | ||
1643 | |||
1644 | u32 scoMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates | ||
1645 | max number of aggregates if it was negogiated to higher value | ||
1646 | default = 1 | ||
1647 | Recommended value Basic rate headsets = 1, EDR (2-EV3) =4. | ||
1648 | */ | ||
1649 | }POSTPACK BTCOEX_OPTMODE_SCO_CONFIG; | ||
1650 | |||
1651 | typedef PREPACK struct { | ||
1652 | u32 scanInterval; | ||
1653 | u32 maxScanStompCnt; | ||
1654 | }POSTPACK BTCOEX_WLANSCAN_SCO_CONFIG; | ||
1655 | |||
1656 | typedef PREPACK struct { | ||
1657 | BTCOEX_SCO_CONFIG scoConfig; | ||
1658 | BTCOEX_PSPOLLMODE_SCO_CONFIG scoPspollConfig; | ||
1659 | BTCOEX_OPTMODE_SCO_CONFIG scoOptModeConfig; | ||
1660 | BTCOEX_WLANSCAN_SCO_CONFIG scoWlanScanConfig; | ||
1661 | }POSTPACK WMI_SET_BTCOEX_SCO_CONFIG_CMD; | ||
1662 | |||
1663 | /* ------------------WMI_SET_BTCOEX_A2DP_CONFIG_CMDID -------------------*/ | ||
1664 | /* Configure A2DP profile parameters. These parameters would be used whenver firmware is indicated | ||
1665 | * of A2DP profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID). | ||
1666 | * Configuration of BTCOEX_A2DP_CONFIG data structure are common configuration and applies to | ||
1667 | * ps-poll mode and opt mode. | ||
1668 | * Ps-poll Mode - Station is in power-save and retrieves downlink data between a2dp data bursts. | ||
1669 | * Opt Mode - station is in power save during a2dp bursts and awake in the gaps. | ||
1670 | * BTCOEX_PSPOLLMODE_A2DP_CONFIG - Configuration applied only during ps-poll mode. | ||
1671 | * BTCOEX_OPTMODE_A2DP_CONFIG - Configuration applied only during opt mode. | ||
1672 | */ | ||
1673 | |||
1674 | #define WMI_A2DP_CONFIG_FLAG_ALLOW_OPTIMIZATION (1 << 0) | ||
1675 | #define WMI_A2DP_CONFIG_FLAG_IS_EDR_CAPABLE (1 << 1) | ||
1676 | #define WMI_A2DP_CONFIG_FLAG_IS_BT_ROLE_MASTER (1 << 2) | ||
1677 | #define WMI_A2DP_CONFIG_FLAG_IS_A2DP_HIGH_PRI (1 << 3) | ||
1678 | #define WMI_A2DP_CONFIG_FLAG_FIND_BT_ROLE (1 << 4) | ||
1679 | |||
1680 | typedef PREPACK struct { | ||
1681 | u32 a2dpFlags; /* A2DP Option flags: | ||
1682 | bits: meaning: | ||
1683 | 0 Allow Close Range Optimization | ||
1684 | 1 IS EDR capable | ||
1685 | 2 IS Co-located Bt role Master | ||
1686 | 3 a2dp traffic is high priority | ||
1687 | 4 Fw detect the role of bluetooth. | ||
1688 | */ | ||
1689 | u32 linkId; /* Applicable only to STE-BT - not used */ | ||
1690 | |||
1691 | }POSTPACK BTCOEX_A2DP_CONFIG; | ||
1692 | |||
1693 | typedef PREPACK struct { | ||
1694 | u32 a2dpWlanMaxDur; /* MAX time firmware uses the medium for | ||
1695 | wlan, after it identifies the idle time | ||
1696 | default (30 msecs) */ | ||
1697 | |||
1698 | u32 a2dpMinBurstCnt; /* Minimum number of bluetooth data frames | ||
1699 | to replenish Wlan Usage limit (default 3) */ | ||
1700 | |||
1701 | u32 a2dpDataRespTimeout; /* Max duration firmware waits for downlink | ||
1702 | by stomping on bluetooth | ||
1703 | after ps-poll is acknowledged. | ||
1704 | default = 20 ms | ||
1705 | */ | ||
1706 | }POSTPACK BTCOEX_PSPOLLMODE_A2DP_CONFIG; | ||
1707 | |||
1708 | typedef PREPACK struct { | ||
1709 | u32 a2dpMinlowRateMbps; /* Low rate threshold */ | ||
1710 | |||
1711 | u32 a2dpLowRateCnt; /* number of low rate pkts (< a2dpMinlowRateMbps) allowed in 100 ms. | ||
1712 | If exceeded switch/stay to ps-poll mode, lower stay in opt mode. | ||
1713 | default = 36 | ||
1714 | */ | ||
1715 | |||
1716 | u32 a2dpHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/ | ||
1717 | ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms, | ||
1718 | if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode. | ||
1719 | default = 5 (80% of high rates) | ||
1720 | */ | ||
1721 | |||
1722 | u32 a2dpMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates | ||
1723 | max number of aggregates if it was negogiated to higher value | ||
1724 | default = 1 | ||
1725 | Recommended value Basic rate headsets = 1, EDR (2-EV3) =8. | ||
1726 | */ | ||
1727 | u32 a2dpPktStompCnt; /*number of a2dp pkts that can be stomped per burst. | ||
1728 | default = 6*/ | ||
1729 | |||
1730 | }POSTPACK BTCOEX_OPTMODE_A2DP_CONFIG; | ||
1731 | |||
1732 | typedef PREPACK struct { | ||
1733 | BTCOEX_A2DP_CONFIG a2dpConfig; | ||
1734 | BTCOEX_PSPOLLMODE_A2DP_CONFIG a2dppspollConfig; | ||
1735 | BTCOEX_OPTMODE_A2DP_CONFIG a2dpOptConfig; | ||
1736 | }POSTPACK WMI_SET_BTCOEX_A2DP_CONFIG_CMD; | ||
1737 | |||
1738 | /*------------ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID---------------------*/ | ||
1739 | /* Configure non-A2dp ACL profile parameters.The starts of ACL profile can either be | ||
1740 | * indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID orenabled via firmware detection | ||
1741 | * which is configured via "aclCoexFlags". | ||
1742 | * Configration of BTCOEX_ACLCOEX_CONFIG data structure are common configuration and applies | ||
1743 | * ps-poll mode and opt mode. | ||
1744 | * Ps-poll Mode - Station is in power-save and retrieves downlink data during wlan medium. | ||
1745 | * Opt Mode - station is in power save during bluetooth medium time and awake during wlan duration. | ||
1746 | * (Not implemented yet) | ||
1747 | * | ||
1748 | * BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG - Configuration applied only during ps-poll mode. | ||
1749 | * BTCOEX_OPTMODE_ACLCOEX_CONFIG - Configuration applied only during opt mode. | ||
1750 | */ | ||
1751 | |||
1752 | #define WMI_ACLCOEX_FLAGS_ALLOW_OPTIMIZATION (1 << 0) | ||
1753 | #define WMI_ACLCOEX_FLAGS_DISABLE_FW_DETECTION (1 << 1) | ||
1754 | |||
1755 | typedef PREPACK struct { | ||
1756 | u32 aclWlanMediumDur; /* Wlan usage time during Acl (non-a2dp) | ||
1757 | coexistence (default 30 msecs) | ||
1758 | */ | ||
1759 | |||
1760 | u32 aclBtMediumDur; /* Bt usage time during acl coexistence | ||
1761 | (default 30 msecs) | ||
1762 | */ | ||
1763 | |||
1764 | u32 aclDetectTimeout; /* BT activity observation time limit. | ||
1765 | In this time duration, number of bt pkts are counted. | ||
1766 | If the Cnt reaches "aclPktCntLowerLimit" value | ||
1767 | for "aclIterToEnableCoex" iteration continuously, | ||
1768 | firmware gets into ACL coexistence mode. | ||
1769 | Similarly, if bt traffic count during ACL coexistence | ||
1770 | has not reached "aclPktCntLowerLimit" continuously | ||
1771 | for "aclIterToEnableCoex", then ACL coexistence is | ||
1772 | disabled. | ||
1773 | -default 100 msecs | ||
1774 | */ | ||
1775 | |||
1776 | u32 aclPktCntLowerLimit; /* Acl Pkt Cnt to be received in duration of | ||
1777 | "aclDetectTimeout" for | ||
1778 | "aclIterForEnDis" times to enabling ACL coex. | ||
1779 | Similar logic is used to disable acl coexistence. | ||
1780 | (If "aclPktCntLowerLimit" cnt of acl pkts | ||
1781 | are not seen by the for "aclIterForEnDis" | ||
1782 | then acl coexistence is disabled). | ||
1783 | default = 10 | ||
1784 | */ | ||
1785 | |||
1786 | u32 aclIterForEnDis; /* number of Iteration of "aclPktCntLowerLimit" for Enabling and | ||
1787 | Disabling Acl Coexistence. | ||
1788 | default = 3 | ||
1789 | */ | ||
1790 | |||
1791 | u32 aclPktCntUpperLimit; /* This is upperBound limit, if there is more than | ||
1792 | "aclPktCntUpperLimit" seen in "aclDetectTimeout", | ||
1793 | ACL coexistence is enabled right away. | ||
1794 | - default 15*/ | ||
1795 | |||
1796 | u32 aclCoexFlags; /* A2DP Option flags: | ||
1797 | bits: meaning: | ||
1798 | 0 Allow Close Range Optimization | ||
1799 | 1 disable Firmware detection | ||
1800 | (Currently supported configuration is aclCoexFlags =0) | ||
1801 | */ | ||
1802 | u32 linkId; /* Applicable only for STE-BT - not used */ | ||
1803 | |||
1804 | }POSTPACK BTCOEX_ACLCOEX_CONFIG; | ||
1805 | |||
1806 | typedef PREPACK struct { | ||
1807 | u32 aclDataRespTimeout; /* Max duration firmware waits for downlink | ||
1808 | by stomping on bluetooth | ||
1809 | after ps-poll is acknowledged. | ||
1810 | default = 20 ms */ | ||
1811 | |||
1812 | }POSTPACK BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG; | ||
1813 | |||
1814 | |||
1815 | /* Not implemented yet*/ | ||
1816 | typedef PREPACK struct { | ||
1817 | u32 aclCoexMinlowRateMbps; | ||
1818 | u32 aclCoexLowRateCnt; | ||
1819 | u32 aclCoexHighPktRatio; | ||
1820 | u32 aclCoexMaxAggrSize; | ||
1821 | u32 aclPktStompCnt; | ||
1822 | }POSTPACK BTCOEX_OPTMODE_ACLCOEX_CONFIG; | ||
1823 | |||
1824 | typedef PREPACK struct { | ||
1825 | BTCOEX_ACLCOEX_CONFIG aclCoexConfig; | ||
1826 | BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG aclCoexPspollConfig; | ||
1827 | BTCOEX_OPTMODE_ACLCOEX_CONFIG aclCoexOptConfig; | ||
1828 | }POSTPACK WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD; | ||
1829 | |||
1830 | /* -----------WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ------------------*/ | ||
1831 | typedef enum { | ||
1832 | WMI_BTCOEX_BT_PROFILE_SCO =1, | ||
1833 | WMI_BTCOEX_BT_PROFILE_A2DP, | ||
1834 | WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE, | ||
1835 | WMI_BTCOEX_BT_PROFILE_ACLCOEX, | ||
1836 | }WMI_BTCOEX_BT_PROFILE; | ||
1837 | |||
1838 | typedef PREPACK struct { | ||
1839 | u32 btProfileType; | ||
1840 | u32 btOperatingStatus; | ||
1841 | u32 btLinkId; | ||
1842 | }WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD; | ||
1843 | |||
1844 | /*--------------------- WMI_SET_BTCOEX_DEBUG_CMDID ---------------------*/ | ||
1845 | /* Used for firmware development and debugging */ | ||
1846 | typedef PREPACK struct { | ||
1847 | u32 btcoexDbgParam1; | ||
1848 | u32 btcoexDbgParam2; | ||
1849 | u32 btcoexDbgParam3; | ||
1850 | u32 btcoexDbgParam4; | ||
1851 | u32 btcoexDbgParam5; | ||
1852 | }WMI_SET_BTCOEX_DEBUG_CMD; | ||
1853 | |||
1854 | /*---------------------WMI_GET_BTCOEX_CONFIG_CMDID --------------------- */ | ||
1855 | /* Command to firmware to get configuration parameters of the bt profile | ||
1856 | * reported via WMI_BTCOEX_CONFIG_EVENTID */ | ||
1857 | typedef PREPACK struct { | ||
1858 | u32 btProfileType; /* 1 - SCO | ||
1859 | 2 - A2DP | ||
1860 | 3 - INQUIRY_PAGE | ||
1861 | 4 - ACLCOEX | ||
1862 | */ | ||
1863 | u32 linkId; /* not used */ | ||
1864 | }WMI_GET_BTCOEX_CONFIG_CMD; | ||
1865 | |||
1866 | /*------------------WMI_REPORT_BTCOEX_CONFIG_EVENTID------------------- */ | ||
1867 | /* Event from firmware to host, sent in response to WMI_GET_BTCOEX_CONFIG_CMDID | ||
1868 | * */ | ||
1869 | typedef PREPACK struct { | ||
1870 | u32 btProfileType; | ||
1871 | u32 linkId; /* not used */ | ||
1872 | PREPACK union { | ||
1873 | WMI_SET_BTCOEX_SCO_CONFIG_CMD scoConfigCmd; | ||
1874 | WMI_SET_BTCOEX_A2DP_CONFIG_CMD a2dpConfigCmd; | ||
1875 | WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD aclcoexConfig; | ||
1876 | WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD btinquiryPageConfigCmd; | ||
1877 | } POSTPACK info; | ||
1878 | } POSTPACK WMI_BTCOEX_CONFIG_EVENT; | ||
1879 | |||
1880 | /*------------- WMI_REPORT_BTCOEX_BTCOEX_STATS_EVENTID--------------------*/ | ||
1881 | /* Used for firmware development and debugging*/ | ||
1882 | typedef PREPACK struct { | ||
1883 | u32 highRatePktCnt; | ||
1884 | u32 firstBmissCnt; | ||
1885 | u32 psPollFailureCnt; | ||
1886 | u32 nullFrameFailureCnt; | ||
1887 | u32 optModeTransitionCnt; | ||
1888 | }BTCOEX_GENERAL_STATS; | ||
1889 | |||
1890 | typedef PREPACK struct { | ||
1891 | u32 scoStompCntAvg; | ||
1892 | u32 scoStompIn100ms; | ||
1893 | u32 scoMaxContStomp; | ||
1894 | u32 scoAvgNoRetries; | ||
1895 | u32 scoMaxNoRetriesIn100ms; | ||
1896 | }BTCOEX_SCO_STATS; | ||
1897 | |||
1898 | typedef PREPACK struct { | ||
1899 | u32 a2dpBurstCnt; | ||
1900 | u32 a2dpMaxBurstCnt; | ||
1901 | u32 a2dpAvgIdletimeIn100ms; | ||
1902 | u32 a2dpAvgStompCnt; | ||
1903 | }BTCOEX_A2DP_STATS; | ||
1904 | |||
1905 | typedef PREPACK struct { | ||
1906 | u32 aclPktCntInBtTime; | ||
1907 | u32 aclStompCntInWlanTime; | ||
1908 | u32 aclPktCntIn100ms; | ||
1909 | }BTCOEX_ACLCOEX_STATS; | ||
1910 | |||
1911 | typedef PREPACK struct { | ||
1912 | BTCOEX_GENERAL_STATS coexStats; | ||
1913 | BTCOEX_SCO_STATS scoStats; | ||
1914 | BTCOEX_A2DP_STATS a2dpStats; | ||
1915 | BTCOEX_ACLCOEX_STATS aclCoexStats; | ||
1916 | }WMI_BTCOEX_STATS_EVENT; | ||
1917 | |||
1918 | |||
1919 | /*--------------------------END OF BTCOEX -------------------------------------*/ | ||
1920 | typedef PREPACK struct { | ||
1921 | u32 sleepState; | ||
1922 | }WMI_REPORT_SLEEP_STATE_EVENT; | ||
1923 | |||
1924 | typedef enum { | ||
1925 | WMI_REPORT_SLEEP_STATUS_IS_DEEP_SLEEP =0, | ||
1926 | WMI_REPORT_SLEEP_STATUS_IS_AWAKE | ||
1927 | } WMI_REPORT_SLEEP_STATUS; | ||
1928 | typedef enum { | ||
1929 | DISCONN_EVT_IN_RECONN = 0, /* default */ | ||
1930 | NO_DISCONN_EVT_IN_RECONN | ||
1931 | } TARGET_EVENT_REPORT_CONFIG; | ||
1932 | |||
1933 | typedef PREPACK struct { | ||
1934 | u32 evtConfig; | ||
1935 | } POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD; | ||
1936 | |||
1937 | |||
1938 | typedef PREPACK struct { | ||
1939 | u16 cmd_buf_sz; /* HCI cmd buffer size */ | ||
1940 | u8 buf[1]; /* Absolute HCI cmd */ | ||
1941 | } POSTPACK WMI_HCI_CMD; | ||
1942 | |||
1943 | /* | ||
1944 | * Command Replies | ||
1945 | */ | ||
1946 | |||
1947 | /* | ||
1948 | * WMI_GET_CHANNEL_LIST_CMDID reply | ||
1949 | */ | ||
1950 | typedef PREPACK struct { | ||
1951 | u8 reserved1; | ||
1952 | u8 numChannels; /* number of channels in reply */ | ||
1953 | u16 channelList[1]; /* channel in Mhz */ | ||
1954 | } POSTPACK WMI_CHANNEL_LIST_REPLY; | ||
1955 | |||
1956 | typedef enum { | ||
1957 | A_SUCCEEDED = 0, | ||
1958 | A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250, | ||
1959 | A_SUCCEEDED_MODIFY_STREAM=251, | ||
1960 | A_FAILED_INVALID_STREAM = 252, | ||
1961 | A_FAILED_MAX_THINSTREAMS = 253, | ||
1962 | A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254, | ||
1963 | } PSTREAM_REPLY_STATUS; | ||
1964 | |||
1965 | typedef PREPACK struct { | ||
1966 | u8 status; /* PSTREAM_REPLY_STATUS */ | ||
1967 | u8 txQueueNumber; | ||
1968 | u8 rxQueueNumber; | ||
1969 | u8 trafficClass; | ||
1970 | u8 trafficDirection; /* DIR_TYPE */ | ||
1971 | } POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; | ||
1972 | |||
1973 | typedef PREPACK struct { | ||
1974 | u8 status; /* PSTREAM_REPLY_STATUS */ | ||
1975 | u8 txQueueNumber; | ||
1976 | u8 rxQueueNumber; | ||
1977 | u8 trafficDirection; /* DIR_TYPE */ | ||
1978 | u8 trafficClass; | ||
1979 | } POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; | ||
1980 | |||
1981 | /* | ||
1982 | * List of Events (target to host) | ||
1983 | */ | ||
1984 | typedef enum { | ||
1985 | WMI_READY_EVENTID = 0x1001, | ||
1986 | WMI_CONNECT_EVENTID, | ||
1987 | WMI_DISCONNECT_EVENTID, | ||
1988 | WMI_BSSINFO_EVENTID, | ||
1989 | WMI_CMDERROR_EVENTID, | ||
1990 | WMI_REGDOMAIN_EVENTID, | ||
1991 | WMI_PSTREAM_TIMEOUT_EVENTID, | ||
1992 | WMI_NEIGHBOR_REPORT_EVENTID, | ||
1993 | WMI_TKIP_MICERR_EVENTID, | ||
1994 | WMI_SCAN_COMPLETE_EVENTID, /* 0x100a */ | ||
1995 | WMI_REPORT_STATISTICS_EVENTID, | ||
1996 | WMI_RSSI_THRESHOLD_EVENTID, | ||
1997 | WMI_ERROR_REPORT_EVENTID, | ||
1998 | WMI_OPT_RX_FRAME_EVENTID, | ||
1999 | WMI_REPORT_ROAM_TBL_EVENTID, | ||
2000 | WMI_EXTENSION_EVENTID, | ||
2001 | WMI_CAC_EVENTID, | ||
2002 | WMI_SNR_THRESHOLD_EVENTID, | ||
2003 | WMI_LQ_THRESHOLD_EVENTID, | ||
2004 | WMI_TX_RETRY_ERR_EVENTID, /* 0x1014 */ | ||
2005 | WMI_REPORT_ROAM_DATA_EVENTID, | ||
2006 | WMI_TEST_EVENTID, | ||
2007 | WMI_APLIST_EVENTID, | ||
2008 | WMI_GET_WOW_LIST_EVENTID, | ||
2009 | WMI_GET_PMKID_LIST_EVENTID, | ||
2010 | WMI_CHANNEL_CHANGE_EVENTID, | ||
2011 | WMI_PEER_NODE_EVENTID, | ||
2012 | WMI_PSPOLL_EVENTID, | ||
2013 | WMI_DTIMEXPIRY_EVENTID, | ||
2014 | WMI_WLAN_VERSION_EVENTID, | ||
2015 | WMI_SET_PARAMS_REPLY_EVENTID, | ||
2016 | WMI_ADDBA_REQ_EVENTID, /*0x1020 */ | ||
2017 | WMI_ADDBA_RESP_EVENTID, | ||
2018 | WMI_DELBA_REQ_EVENTID, | ||
2019 | WMI_TX_COMPLETE_EVENTID, | ||
2020 | WMI_HCI_EVENT_EVENTID, | ||
2021 | WMI_ACL_DATA_EVENTID, | ||
2022 | WMI_REPORT_SLEEP_STATE_EVENTID, | ||
2023 | #ifdef WAPI_ENABLE | ||
2024 | WMI_WAPI_REKEY_EVENTID, | ||
2025 | #endif | ||
2026 | WMI_REPORT_BTCOEX_STATS_EVENTID, | ||
2027 | WMI_REPORT_BTCOEX_CONFIG_EVENTID, | ||
2028 | WMI_GET_PMK_EVENTID, | ||
2029 | |||
2030 | /* DFS Events */ | ||
2031 | WMI_DFS_HOST_ATTACH_EVENTID, | ||
2032 | WMI_DFS_HOST_INIT_EVENTID, | ||
2033 | WMI_DFS_RESET_DELAYLINES_EVENTID, | ||
2034 | WMI_DFS_RESET_RADARQ_EVENTID, | ||
2035 | WMI_DFS_RESET_AR_EVENTID, | ||
2036 | WMI_DFS_RESET_ARQ_EVENTID, | ||
2037 | WMI_DFS_SET_DUR_MULTIPLIER_EVENTID, | ||
2038 | WMI_DFS_SET_BANGRADAR_EVENTID, | ||
2039 | WMI_DFS_SET_DEBUGLEVEL_EVENTID, | ||
2040 | WMI_DFS_PHYERR_EVENTID, | ||
2041 | /* CCX Evants */ | ||
2042 | WMI_CCX_RM_STATUS_EVENTID, | ||
2043 | |||
2044 | /* P2P Events */ | ||
2045 | WMI_P2P_GO_NEG_RESULT_EVENTID, | ||
2046 | |||
2047 | WMI_WAC_SCAN_DONE_EVENTID, | ||
2048 | WMI_WAC_REPORT_BSS_EVENTID, | ||
2049 | WMI_WAC_START_WPS_EVENTID, | ||
2050 | WMI_WAC_CTRL_REQ_REPLY_EVENTID, | ||
2051 | |||
2052 | /* RFKILL Events */ | ||
2053 | WMI_RFKILL_STATE_CHANGE_EVENTID, | ||
2054 | WMI_RFKILL_GET_MODE_CMD_EVENTID, | ||
2055 | WMI_THIN_RESERVED_START_EVENTID = 0x8000, | ||
2056 | |||
2057 | /* | ||
2058 | * Events in this range are reserved for thinmode | ||
2059 | * See wmi_thin.h for actual definitions | ||
2060 | */ | ||
2061 | WMI_THIN_RESERVED_END_EVENTID = 0x8fff, | ||
2062 | |||
2063 | WMI_SET_CHANNEL_EVENTID, | ||
2064 | WMI_ASSOC_REQ_EVENTID, | ||
2065 | |||
2066 | /* generic ACS event */ | ||
2067 | WMI_ACS_EVENTID, | ||
2068 | WMI_REPORT_WMM_PARAMS_EVENTID | ||
2069 | } WMI_EVENT_ID; | ||
2070 | |||
2071 | |||
2072 | typedef enum { | ||
2073 | WMI_11A_CAPABILITY = 1, | ||
2074 | WMI_11G_CAPABILITY = 2, | ||
2075 | WMI_11AG_CAPABILITY = 3, | ||
2076 | WMI_11NA_CAPABILITY = 4, | ||
2077 | WMI_11NG_CAPABILITY = 5, | ||
2078 | WMI_11NAG_CAPABILITY = 6, | ||
2079 | // END CAPABILITY | ||
2080 | WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY), | ||
2081 | } WMI_PHY_CAPABILITY; | ||
2082 | |||
2083 | typedef PREPACK struct { | ||
2084 | u8 macaddr[ATH_MAC_LEN]; | ||
2085 | u8 phyCapability; /* WMI_PHY_CAPABILITY */ | ||
2086 | } POSTPACK WMI_READY_EVENT_1; | ||
2087 | |||
2088 | typedef PREPACK struct { | ||
2089 | u32 sw_version; | ||
2090 | u32 abi_version; | ||
2091 | u8 macaddr[ATH_MAC_LEN]; | ||
2092 | u8 phyCapability; /* WMI_PHY_CAPABILITY */ | ||
2093 | } POSTPACK WMI_READY_EVENT_2; | ||
2094 | |||
2095 | #if defined(ATH_TARGET) | ||
2096 | #ifdef AR6002_REV2 | ||
2097 | #define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */ | ||
2098 | #else | ||
2099 | #define WMI_READY_EVENT WMI_READY_EVENT_2 /* AR6001, AR6002_REV4, AR6002_REV5 */ | ||
2100 | #endif | ||
2101 | #else | ||
2102 | #define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ | ||
2103 | #endif | ||
2104 | |||
2105 | |||
2106 | /* | ||
2107 | * Connect Event | ||
2108 | */ | ||
2109 | typedef PREPACK struct { | ||
2110 | u16 channel; | ||
2111 | u8 bssid[ATH_MAC_LEN]; | ||
2112 | u16 listenInterval; | ||
2113 | u16 beaconInterval; | ||
2114 | u32 networkType; | ||
2115 | u8 beaconIeLen; | ||
2116 | u8 assocReqLen; | ||
2117 | u8 assocRespLen; | ||
2118 | u8 assocInfo[1]; | ||
2119 | } POSTPACK WMI_CONNECT_EVENT; | ||
2120 | |||
2121 | /* | ||
2122 | * Disconnect Event | ||
2123 | */ | ||
2124 | typedef enum { | ||
2125 | NO_NETWORK_AVAIL = 0x01, | ||
2126 | LOST_LINK = 0x02, /* bmiss */ | ||
2127 | DISCONNECT_CMD = 0x03, | ||
2128 | BSS_DISCONNECTED = 0x04, | ||
2129 | AUTH_FAILED = 0x05, | ||
2130 | ASSOC_FAILED = 0x06, | ||
2131 | NO_RESOURCES_AVAIL = 0x07, | ||
2132 | CSERV_DISCONNECT = 0x08, | ||
2133 | INVALID_PROFILE = 0x0a, | ||
2134 | DOT11H_CHANNEL_SWITCH = 0x0b, | ||
2135 | PROFILE_MISMATCH = 0x0c, | ||
2136 | CONNECTION_EVICTED = 0x0d, | ||
2137 | IBSS_MERGE = 0xe, | ||
2138 | } WMI_DISCONNECT_REASON; | ||
2139 | |||
2140 | typedef PREPACK struct { | ||
2141 | u16 protocolReasonStatus; /* reason code, see 802.11 spec. */ | ||
2142 | u8 bssid[ATH_MAC_LEN]; /* set if known */ | ||
2143 | u8 disconnectReason ; /* see WMI_DISCONNECT_REASON */ | ||
2144 | u8 assocRespLen; | ||
2145 | u8 assocInfo[1]; | ||
2146 | } POSTPACK WMI_DISCONNECT_EVENT; | ||
2147 | |||
2148 | /* | ||
2149 | * BSS Info Event. | ||
2150 | * Mechanism used to inform host of the presence and characteristic of | ||
2151 | * wireless networks present. Consists of bss info header followed by | ||
2152 | * the beacon or probe-response frame body. The 802.11 header is not included. | ||
2153 | */ | ||
2154 | typedef enum { | ||
2155 | BEACON_FTYPE = 0x1, | ||
2156 | PROBERESP_FTYPE, | ||
2157 | ACTION_MGMT_FTYPE, | ||
2158 | PROBEREQ_FTYPE, | ||
2159 | } WMI_BI_FTYPE; | ||
2160 | |||
2161 | enum { | ||
2162 | BSS_ELEMID_CHANSWITCH = 0x01, | ||
2163 | BSS_ELEMID_ATHEROS = 0x02, | ||
2164 | }; | ||
2165 | |||
2166 | typedef PREPACK struct { | ||
2167 | u16 channel; | ||
2168 | u8 frameType; /* see WMI_BI_FTYPE */ | ||
2169 | u8 snr; | ||
2170 | s16 rssi; | ||
2171 | u8 bssid[ATH_MAC_LEN]; | ||
2172 | u32 ieMask; | ||
2173 | } POSTPACK WMI_BSS_INFO_HDR; | ||
2174 | |||
2175 | /* | ||
2176 | * BSS INFO HDR version 2.0 | ||
2177 | * With 6 bytes HTC header and 6 bytes of WMI header | ||
2178 | * WMI_BSS_INFO_HDR cannot be accommodated in the removed 802.11 management | ||
2179 | * header space. | ||
2180 | * - Reduce the ieMask to 2 bytes as only two bit flags are used | ||
2181 | * - Remove rssi and compute it on the host. rssi = snr - 95 | ||
2182 | */ | ||
2183 | typedef PREPACK struct { | ||
2184 | u16 channel; | ||
2185 | u8 frameType; /* see WMI_BI_FTYPE */ | ||
2186 | u8 snr; | ||
2187 | u8 bssid[ATH_MAC_LEN]; | ||
2188 | u16 ieMask; | ||
2189 | } POSTPACK WMI_BSS_INFO_HDR2; | ||
2190 | |||
2191 | /* | ||
2192 | * Command Error Event | ||
2193 | */ | ||
2194 | typedef enum { | ||
2195 | INVALID_PARAM = 0x01, | ||
2196 | ILLEGAL_STATE = 0x02, | ||
2197 | INTERNAL_ERROR = 0x03, | ||
2198 | } WMI_ERROR_CODE; | ||
2199 | |||
2200 | typedef PREPACK struct { | ||
2201 | u16 commandId; | ||
2202 | u8 errorCode; | ||
2203 | } POSTPACK WMI_CMD_ERROR_EVENT; | ||
2204 | |||
2205 | /* | ||
2206 | * New Regulatory Domain Event | ||
2207 | */ | ||
2208 | typedef PREPACK struct { | ||
2209 | u32 regDomain; | ||
2210 | } POSTPACK WMI_REG_DOMAIN_EVENT; | ||
2211 | |||
2212 | typedef PREPACK struct { | ||
2213 | u8 txQueueNumber; | ||
2214 | u8 rxQueueNumber; | ||
2215 | u8 trafficDirection; | ||
2216 | u8 trafficClass; | ||
2217 | } POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; | ||
2218 | |||
2219 | typedef PREPACK struct { | ||
2220 | u8 reserve1; | ||
2221 | u8 reserve2; | ||
2222 | u8 reserve3; | ||
2223 | u8 trafficClass; | ||
2224 | } POSTPACK WMI_ACM_REJECT_EVENT; | ||
2225 | |||
2226 | /* | ||
2227 | * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform | ||
2228 | * the host of BSS's it has found that matches the current profile. | ||
2229 | * It can be used by the host to cache PMKs and/to initiate pre-authentication | ||
2230 | * if the BSS supports it. The first bssid is always the current associated | ||
2231 | * BSS. | ||
2232 | * The bssid and bssFlags information repeats according to the number | ||
2233 | * or APs reported. | ||
2234 | */ | ||
2235 | typedef enum { | ||
2236 | WMI_DEFAULT_BSS_FLAGS = 0x00, | ||
2237 | WMI_PREAUTH_CAPABLE_BSS = 0x01, | ||
2238 | WMI_PMKID_VALID_BSS = 0x02, | ||
2239 | } WMI_BSS_FLAGS; | ||
2240 | |||
2241 | typedef PREPACK struct { | ||
2242 | u8 bssid[ATH_MAC_LEN]; | ||
2243 | u8 bssFlags; /* see WMI_BSS_FLAGS */ | ||
2244 | } POSTPACK WMI_NEIGHBOR_INFO; | ||
2245 | |||
2246 | typedef PREPACK struct { | ||
2247 | s8 numberOfAps; | ||
2248 | WMI_NEIGHBOR_INFO neighbor[1]; | ||
2249 | } POSTPACK WMI_NEIGHBOR_REPORT_EVENT; | ||
2250 | |||
2251 | /* | ||
2252 | * TKIP MIC Error Event | ||
2253 | */ | ||
2254 | typedef PREPACK struct { | ||
2255 | u8 keyid; | ||
2256 | u8 ismcast; | ||
2257 | } POSTPACK WMI_TKIP_MICERR_EVENT; | ||
2258 | |||
2259 | /* | ||
2260 | * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) | ||
2261 | */ | ||
2262 | typedef PREPACK struct { | ||
2263 | s32 status; | ||
2264 | } POSTPACK WMI_SCAN_COMPLETE_EVENT; | ||
2265 | |||
2266 | #define MAX_OPT_DATA_LEN 1400 | ||
2267 | |||
2268 | /* | ||
2269 | * WMI_SET_ADHOC_BSSID_CMDID | ||
2270 | */ | ||
2271 | typedef PREPACK struct { | ||
2272 | u8 bssid[ATH_MAC_LEN]; | ||
2273 | } POSTPACK WMI_SET_ADHOC_BSSID_CMD; | ||
2274 | |||
2275 | /* | ||
2276 | * WMI_SET_OPT_MODE_CMDID | ||
2277 | */ | ||
2278 | typedef enum { | ||
2279 | SPECIAL_OFF, | ||
2280 | SPECIAL_ON, | ||
2281 | } OPT_MODE_TYPE; | ||
2282 | |||
2283 | typedef PREPACK struct { | ||
2284 | u8 optMode; | ||
2285 | } POSTPACK WMI_SET_OPT_MODE_CMD; | ||
2286 | |||
2287 | /* | ||
2288 | * WMI_TX_OPT_FRAME_CMDID | ||
2289 | */ | ||
2290 | typedef enum { | ||
2291 | OPT_PROBE_REQ = 0x01, | ||
2292 | OPT_PROBE_RESP = 0x02, | ||
2293 | OPT_CPPP_START = 0x03, | ||
2294 | OPT_CPPP_STOP = 0x04, | ||
2295 | } WMI_OPT_FTYPE; | ||
2296 | |||
2297 | typedef PREPACK struct { | ||
2298 | u16 optIEDataLen; | ||
2299 | u8 frmType; | ||
2300 | u8 dstAddr[ATH_MAC_LEN]; | ||
2301 | u8 bssid[ATH_MAC_LEN]; | ||
2302 | u8 reserved; /* For alignment */ | ||
2303 | u8 optIEData[1]; | ||
2304 | } POSTPACK WMI_OPT_TX_FRAME_CMD; | ||
2305 | |||
2306 | /* | ||
2307 | * Special frame receive Event. | ||
2308 | * Mechanism used to inform host of the receiption of the special frames. | ||
2309 | * Consists of special frame info header followed by special frame body. | ||
2310 | * The 802.11 header is not included. | ||
2311 | */ | ||
2312 | typedef PREPACK struct { | ||
2313 | u16 channel; | ||
2314 | u8 frameType; /* see WMI_OPT_FTYPE */ | ||
2315 | s8 snr; | ||
2316 | u8 srcAddr[ATH_MAC_LEN]; | ||
2317 | u8 bssid[ATH_MAC_LEN]; | ||
2318 | } POSTPACK WMI_OPT_RX_INFO_HDR; | ||
2319 | |||
2320 | /* | ||
2321 | * Reporting statistics. | ||
2322 | */ | ||
2323 | typedef PREPACK struct { | ||
2324 | u32 tx_packets; | ||
2325 | u32 tx_bytes; | ||
2326 | u32 tx_unicast_pkts; | ||
2327 | u32 tx_unicast_bytes; | ||
2328 | u32 tx_multicast_pkts; | ||
2329 | u32 tx_multicast_bytes; | ||
2330 | u32 tx_broadcast_pkts; | ||
2331 | u32 tx_broadcast_bytes; | ||
2332 | u32 tx_rts_success_cnt; | ||
2333 | u32 tx_packet_per_ac[4]; | ||
2334 | u32 tx_errors_per_ac[4]; | ||
2335 | |||
2336 | u32 tx_errors; | ||
2337 | u32 tx_failed_cnt; | ||
2338 | u32 tx_retry_cnt; | ||
2339 | u32 tx_mult_retry_cnt; | ||
2340 | u32 tx_rts_fail_cnt; | ||
2341 | s32 tx_unicast_rate; | ||
2342 | }POSTPACK tx_stats_t; | ||
2343 | |||
2344 | typedef PREPACK struct { | ||
2345 | u32 rx_packets; | ||
2346 | u32 rx_bytes; | ||
2347 | u32 rx_unicast_pkts; | ||
2348 | u32 rx_unicast_bytes; | ||
2349 | u32 rx_multicast_pkts; | ||
2350 | u32 rx_multicast_bytes; | ||
2351 | u32 rx_broadcast_pkts; | ||
2352 | u32 rx_broadcast_bytes; | ||
2353 | u32 rx_fragment_pkt; | ||
2354 | |||
2355 | u32 rx_errors; | ||
2356 | u32 rx_crcerr; | ||
2357 | u32 rx_key_cache_miss; | ||
2358 | u32 rx_decrypt_err; | ||
2359 | u32 rx_duplicate_frames; | ||
2360 | s32 rx_unicast_rate; | ||
2361 | }POSTPACK rx_stats_t; | ||
2362 | |||
2363 | typedef PREPACK struct { | ||
2364 | u32 tkip_local_mic_failure; | ||
2365 | u32 tkip_counter_measures_invoked; | ||
2366 | u32 tkip_replays; | ||
2367 | u32 tkip_format_errors; | ||
2368 | u32 ccmp_format_errors; | ||
2369 | u32 ccmp_replays; | ||
2370 | }POSTPACK tkip_ccmp_stats_t; | ||
2371 | |||
2372 | typedef PREPACK struct { | ||
2373 | u32 power_save_failure_cnt; | ||
2374 | u16 stop_tx_failure_cnt; | ||
2375 | u16 atim_tx_failure_cnt; | ||
2376 | u16 atim_rx_failure_cnt; | ||
2377 | u16 bcn_rx_failure_cnt; | ||
2378 | }POSTPACK pm_stats_t; | ||
2379 | |||
2380 | typedef PREPACK struct { | ||
2381 | u32 cs_bmiss_cnt; | ||
2382 | u32 cs_lowRssi_cnt; | ||
2383 | u16 cs_connect_cnt; | ||
2384 | u16 cs_disconnect_cnt; | ||
2385 | s16 cs_aveBeacon_rssi; | ||
2386 | u16 cs_roam_count; | ||
2387 | s16 cs_rssi; | ||
2388 | u8 cs_snr; | ||
2389 | u8 cs_aveBeacon_snr; | ||
2390 | u8 cs_lastRoam_msec; | ||
2391 | } POSTPACK cserv_stats_t; | ||
2392 | |||
2393 | typedef PREPACK struct { | ||
2394 | tx_stats_t tx_stats; | ||
2395 | rx_stats_t rx_stats; | ||
2396 | tkip_ccmp_stats_t tkipCcmpStats; | ||
2397 | }POSTPACK wlan_net_stats_t; | ||
2398 | |||
2399 | typedef PREPACK struct { | ||
2400 | u32 arp_received; | ||
2401 | u32 arp_matched; | ||
2402 | u32 arp_replied; | ||
2403 | } POSTPACK arp_stats_t; | ||
2404 | |||
2405 | typedef PREPACK struct { | ||
2406 | u32 wow_num_pkts_dropped; | ||
2407 | u16 wow_num_events_discarded; | ||
2408 | u8 wow_num_host_pkt_wakeups; | ||
2409 | u8 wow_num_host_event_wakeups; | ||
2410 | } POSTPACK wlan_wow_stats_t; | ||
2411 | |||
2412 | typedef PREPACK struct { | ||
2413 | u32 lqVal; | ||
2414 | s32 noise_floor_calibation; | ||
2415 | pm_stats_t pmStats; | ||
2416 | wlan_net_stats_t txrxStats; | ||
2417 | wlan_wow_stats_t wowStats; | ||
2418 | arp_stats_t arpStats; | ||
2419 | cserv_stats_t cservStats; | ||
2420 | } POSTPACK WMI_TARGET_STATS; | ||
2421 | |||
2422 | /* | ||
2423 | * WMI_RSSI_THRESHOLD_EVENTID. | ||
2424 | * Indicate the RSSI events to host. Events are indicated when we breach a | ||
2425 | * thresold value. | ||
2426 | */ | ||
2427 | typedef enum{ | ||
2428 | WMI_RSSI_THRESHOLD1_ABOVE = 0, | ||
2429 | WMI_RSSI_THRESHOLD2_ABOVE, | ||
2430 | WMI_RSSI_THRESHOLD3_ABOVE, | ||
2431 | WMI_RSSI_THRESHOLD4_ABOVE, | ||
2432 | WMI_RSSI_THRESHOLD5_ABOVE, | ||
2433 | WMI_RSSI_THRESHOLD6_ABOVE, | ||
2434 | WMI_RSSI_THRESHOLD1_BELOW, | ||
2435 | WMI_RSSI_THRESHOLD2_BELOW, | ||
2436 | WMI_RSSI_THRESHOLD3_BELOW, | ||
2437 | WMI_RSSI_THRESHOLD4_BELOW, | ||
2438 | WMI_RSSI_THRESHOLD5_BELOW, | ||
2439 | WMI_RSSI_THRESHOLD6_BELOW | ||
2440 | }WMI_RSSI_THRESHOLD_VAL; | ||
2441 | |||
2442 | typedef PREPACK struct { | ||
2443 | s16 rssi; | ||
2444 | u8 range; | ||
2445 | }POSTPACK WMI_RSSI_THRESHOLD_EVENT; | ||
2446 | |||
2447 | /* | ||
2448 | * WMI_ERROR_REPORT_EVENTID | ||
2449 | */ | ||
2450 | typedef enum{ | ||
2451 | WMI_TARGET_PM_ERR_FAIL = 0x00000001, | ||
2452 | WMI_TARGET_KEY_NOT_FOUND = 0x00000002, | ||
2453 | WMI_TARGET_DECRYPTION_ERR = 0x00000004, | ||
2454 | WMI_TARGET_BMISS = 0x00000008, | ||
2455 | WMI_PSDISABLE_NODE_JOIN = 0x00000010, | ||
2456 | WMI_TARGET_COM_ERR = 0x00000020, | ||
2457 | WMI_TARGET_FATAL_ERR = 0x00000040 | ||
2458 | } WMI_TARGET_ERROR_VAL; | ||
2459 | |||
2460 | typedef PREPACK struct { | ||
2461 | u32 errorVal; | ||
2462 | }POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; | ||
2463 | |||
2464 | typedef PREPACK struct { | ||
2465 | u8 retrys; | ||
2466 | }POSTPACK WMI_TX_RETRY_ERR_EVENT; | ||
2467 | |||
2468 | typedef enum{ | ||
2469 | WMI_SNR_THRESHOLD1_ABOVE = 1, | ||
2470 | WMI_SNR_THRESHOLD1_BELOW, | ||
2471 | WMI_SNR_THRESHOLD2_ABOVE, | ||
2472 | WMI_SNR_THRESHOLD2_BELOW, | ||
2473 | WMI_SNR_THRESHOLD3_ABOVE, | ||
2474 | WMI_SNR_THRESHOLD3_BELOW, | ||
2475 | WMI_SNR_THRESHOLD4_ABOVE, | ||
2476 | WMI_SNR_THRESHOLD4_BELOW | ||
2477 | } WMI_SNR_THRESHOLD_VAL; | ||
2478 | |||
2479 | typedef PREPACK struct { | ||
2480 | u8 range; /* WMI_SNR_THRESHOLD_VAL */ | ||
2481 | u8 snr; | ||
2482 | }POSTPACK WMI_SNR_THRESHOLD_EVENT; | ||
2483 | |||
2484 | typedef enum{ | ||
2485 | WMI_LQ_THRESHOLD1_ABOVE = 1, | ||
2486 | WMI_LQ_THRESHOLD1_BELOW, | ||
2487 | WMI_LQ_THRESHOLD2_ABOVE, | ||
2488 | WMI_LQ_THRESHOLD2_BELOW, | ||
2489 | WMI_LQ_THRESHOLD3_ABOVE, | ||
2490 | WMI_LQ_THRESHOLD3_BELOW, | ||
2491 | WMI_LQ_THRESHOLD4_ABOVE, | ||
2492 | WMI_LQ_THRESHOLD4_BELOW | ||
2493 | } WMI_LQ_THRESHOLD_VAL; | ||
2494 | |||
2495 | typedef PREPACK struct { | ||
2496 | s32 lq; | ||
2497 | u8 range; /* WMI_LQ_THRESHOLD_VAL */ | ||
2498 | }POSTPACK WMI_LQ_THRESHOLD_EVENT; | ||
2499 | /* | ||
2500 | * WMI_REPORT_ROAM_TBL_EVENTID | ||
2501 | */ | ||
2502 | #define MAX_ROAM_TBL_CAND 5 | ||
2503 | |||
2504 | typedef PREPACK struct { | ||
2505 | s32 roam_util; | ||
2506 | u8 bssid[ATH_MAC_LEN]; | ||
2507 | s8 rssi; | ||
2508 | s8 rssidt; | ||
2509 | s8 last_rssi; | ||
2510 | s8 util; | ||
2511 | s8 bias; | ||
2512 | u8 reserved; /* For alignment */ | ||
2513 | } POSTPACK WMI_BSS_ROAM_INFO; | ||
2514 | |||
2515 | |||
2516 | typedef PREPACK struct { | ||
2517 | u16 roamMode; | ||
2518 | u16 numEntries; | ||
2519 | WMI_BSS_ROAM_INFO bssRoamInfo[1]; | ||
2520 | } POSTPACK WMI_TARGET_ROAM_TBL; | ||
2521 | |||
2522 | /* | ||
2523 | * WMI_HCI_EVENT_EVENTID | ||
2524 | */ | ||
2525 | typedef PREPACK struct { | ||
2526 | u16 evt_buf_sz; /* HCI event buffer size */ | ||
2527 | u8 buf[1]; /* HCI event */ | ||
2528 | } POSTPACK WMI_HCI_EVENT; | ||
2529 | |||
2530 | /* | ||
2531 | * WMI_CAC_EVENTID | ||
2532 | */ | ||
2533 | typedef enum { | ||
2534 | CAC_INDICATION_ADMISSION = 0x00, | ||
2535 | CAC_INDICATION_ADMISSION_RESP = 0x01, | ||
2536 | CAC_INDICATION_DELETE = 0x02, | ||
2537 | CAC_INDICATION_NO_RESP = 0x03, | ||
2538 | }CAC_INDICATION; | ||
2539 | |||
2540 | #define WMM_TSPEC_IE_LEN 63 | ||
2541 | |||
2542 | typedef PREPACK struct { | ||
2543 | u8 ac; | ||
2544 | u8 cac_indication; | ||
2545 | u8 statusCode; | ||
2546 | u8 tspecSuggestion[WMM_TSPEC_IE_LEN]; | ||
2547 | }POSTPACK WMI_CAC_EVENT; | ||
2548 | |||
2549 | /* | ||
2550 | * WMI_APLIST_EVENTID | ||
2551 | */ | ||
2552 | |||
2553 | typedef enum { | ||
2554 | APLIST_VER1 = 1, | ||
2555 | } APLIST_VER; | ||
2556 | |||
2557 | typedef PREPACK struct { | ||
2558 | u8 bssid[ATH_MAC_LEN]; | ||
2559 | u16 channel; | ||
2560 | } POSTPACK WMI_AP_INFO_V1; | ||
2561 | |||
2562 | typedef PREPACK union { | ||
2563 | WMI_AP_INFO_V1 apInfoV1; | ||
2564 | } POSTPACK WMI_AP_INFO; | ||
2565 | |||
2566 | typedef PREPACK struct { | ||
2567 | u8 apListVer; | ||
2568 | u8 numAP; | ||
2569 | WMI_AP_INFO apList[1]; | ||
2570 | } POSTPACK WMI_APLIST_EVENT; | ||
2571 | |||
2572 | /* | ||
2573 | * developer commands | ||
2574 | */ | ||
2575 | |||
2576 | /* | ||
2577 | * WMI_SET_BITRATE_CMDID | ||
2578 | * | ||
2579 | * Get bit rate cmd uses same definition as set bit rate cmd | ||
2580 | */ | ||
2581 | typedef enum { | ||
2582 | RATE_AUTO = -1, | ||
2583 | RATE_1Mb = 0, | ||
2584 | RATE_2Mb = 1, | ||
2585 | RATE_5_5Mb = 2, | ||
2586 | RATE_11Mb = 3, | ||
2587 | RATE_6Mb = 4, | ||
2588 | RATE_9Mb = 5, | ||
2589 | RATE_12Mb = 6, | ||
2590 | RATE_18Mb = 7, | ||
2591 | RATE_24Mb = 8, | ||
2592 | RATE_36Mb = 9, | ||
2593 | RATE_48Mb = 10, | ||
2594 | RATE_54Mb = 11, | ||
2595 | RATE_MCS_0_20 = 12, | ||
2596 | RATE_MCS_1_20 = 13, | ||
2597 | RATE_MCS_2_20 = 14, | ||
2598 | RATE_MCS_3_20 = 15, | ||
2599 | RATE_MCS_4_20 = 16, | ||
2600 | RATE_MCS_5_20 = 17, | ||
2601 | RATE_MCS_6_20 = 18, | ||
2602 | RATE_MCS_7_20 = 19, | ||
2603 | RATE_MCS_0_40 = 20, | ||
2604 | RATE_MCS_1_40 = 21, | ||
2605 | RATE_MCS_2_40 = 22, | ||
2606 | RATE_MCS_3_40 = 23, | ||
2607 | RATE_MCS_4_40 = 24, | ||
2608 | RATE_MCS_5_40 = 25, | ||
2609 | RATE_MCS_6_40 = 26, | ||
2610 | RATE_MCS_7_40 = 27, | ||
2611 | } WMI_BIT_RATE; | ||
2612 | |||
2613 | typedef PREPACK struct { | ||
2614 | s8 rateIndex; /* see WMI_BIT_RATE */ | ||
2615 | s8 mgmtRateIndex; | ||
2616 | s8 ctlRateIndex; | ||
2617 | } POSTPACK WMI_BIT_RATE_CMD; | ||
2618 | |||
2619 | |||
2620 | typedef PREPACK struct { | ||
2621 | s8 rateIndex; /* see WMI_BIT_RATE */ | ||
2622 | } POSTPACK WMI_BIT_RATE_REPLY; | ||
2623 | |||
2624 | |||
2625 | /* | ||
2626 | * WMI_SET_FIXRATES_CMDID | ||
2627 | * | ||
2628 | * Get fix rates cmd uses same definition as set fix rates cmd | ||
2629 | */ | ||
2630 | #define FIX_RATE_1Mb ((u32)0x1) | ||
2631 | #define FIX_RATE_2Mb ((u32)0x2) | ||
2632 | #define FIX_RATE_5_5Mb ((u32)0x4) | ||
2633 | #define FIX_RATE_11Mb ((u32)0x8) | ||
2634 | #define FIX_RATE_6Mb ((u32)0x10) | ||
2635 | #define FIX_RATE_9Mb ((u32)0x20) | ||
2636 | #define FIX_RATE_12Mb ((u32)0x40) | ||
2637 | #define FIX_RATE_18Mb ((u32)0x80) | ||
2638 | #define FIX_RATE_24Mb ((u32)0x100) | ||
2639 | #define FIX_RATE_36Mb ((u32)0x200) | ||
2640 | #define FIX_RATE_48Mb ((u32)0x400) | ||
2641 | #define FIX_RATE_54Mb ((u32)0x800) | ||
2642 | #define FIX_RATE_MCS_0_20 ((u32)0x1000) | ||
2643 | #define FIX_RATE_MCS_1_20 ((u32)0x2000) | ||
2644 | #define FIX_RATE_MCS_2_20 ((u32)0x4000) | ||
2645 | #define FIX_RATE_MCS_3_20 ((u32)0x8000) | ||
2646 | #define FIX_RATE_MCS_4_20 ((u32)0x10000) | ||
2647 | #define FIX_RATE_MCS_5_20 ((u32)0x20000) | ||
2648 | #define FIX_RATE_MCS_6_20 ((u32)0x40000) | ||
2649 | #define FIX_RATE_MCS_7_20 ((u32)0x80000) | ||
2650 | #define FIX_RATE_MCS_0_40 ((u32)0x100000) | ||
2651 | #define FIX_RATE_MCS_1_40 ((u32)0x200000) | ||
2652 | #define FIX_RATE_MCS_2_40 ((u32)0x400000) | ||
2653 | #define FIX_RATE_MCS_3_40 ((u32)0x800000) | ||
2654 | #define FIX_RATE_MCS_4_40 ((u32)0x1000000) | ||
2655 | #define FIX_RATE_MCS_5_40 ((u32)0x2000000) | ||
2656 | #define FIX_RATE_MCS_6_40 ((u32)0x4000000) | ||
2657 | #define FIX_RATE_MCS_7_40 ((u32)0x8000000) | ||
2658 | |||
2659 | typedef PREPACK struct { | ||
2660 | u32 fixRateMask; /* see WMI_BIT_RATE */ | ||
2661 | } POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY; | ||
2662 | |||
2663 | typedef PREPACK struct { | ||
2664 | u8 bEnableMask; | ||
2665 | u8 frameType; /*type and subtype*/ | ||
2666 | u32 frameRateMask; /* see WMI_BIT_RATE */ | ||
2667 | } POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY; | ||
2668 | |||
2669 | /* | ||
2670 | * WMI_SET_RECONNECT_AUTH_MODE_CMDID | ||
2671 | * | ||
2672 | * Set authentication mode | ||
2673 | */ | ||
2674 | typedef enum { | ||
2675 | RECONN_DO_AUTH = 0x00, | ||
2676 | RECONN_NOT_AUTH = 0x01 | ||
2677 | } WMI_AUTH_MODE; | ||
2678 | |||
2679 | typedef PREPACK struct { | ||
2680 | u8 mode; | ||
2681 | } POSTPACK WMI_SET_AUTH_MODE_CMD; | ||
2682 | |||
2683 | /* | ||
2684 | * WMI_SET_REASSOC_MODE_CMDID | ||
2685 | * | ||
2686 | * Set authentication mode | ||
2687 | */ | ||
2688 | typedef enum { | ||
2689 | REASSOC_DO_DISASSOC = 0x00, | ||
2690 | REASSOC_DONOT_DISASSOC = 0x01 | ||
2691 | } WMI_REASSOC_MODE; | ||
2692 | |||
2693 | typedef PREPACK struct { | ||
2694 | u8 mode; | ||
2695 | }POSTPACK WMI_SET_REASSOC_MODE_CMD; | ||
2696 | |||
2697 | typedef enum { | ||
2698 | ROAM_DATA_TIME = 1, /* Get The Roam Time Data */ | ||
2699 | } ROAM_DATA_TYPE; | ||
2700 | |||
2701 | typedef PREPACK struct { | ||
2702 | u32 disassoc_time; | ||
2703 | u32 no_txrx_time; | ||
2704 | u32 assoc_time; | ||
2705 | u32 allow_txrx_time; | ||
2706 | u8 disassoc_bssid[ATH_MAC_LEN]; | ||
2707 | s8 disassoc_bss_rssi; | ||
2708 | u8 assoc_bssid[ATH_MAC_LEN]; | ||
2709 | s8 assoc_bss_rssi; | ||
2710 | } POSTPACK WMI_TARGET_ROAM_TIME; | ||
2711 | |||
2712 | typedef PREPACK struct { | ||
2713 | PREPACK union { | ||
2714 | WMI_TARGET_ROAM_TIME roamTime; | ||
2715 | } POSTPACK u; | ||
2716 | u8 roamDataType ; | ||
2717 | } POSTPACK WMI_TARGET_ROAM_DATA; | ||
2718 | |||
2719 | typedef enum { | ||
2720 | WMI_WMM_DISABLED = 0, | ||
2721 | WMI_WMM_ENABLED | ||
2722 | } WMI_WMM_STATUS; | ||
2723 | |||
2724 | typedef PREPACK struct { | ||
2725 | u8 status; | ||
2726 | }POSTPACK WMI_SET_WMM_CMD; | ||
2727 | |||
2728 | typedef PREPACK struct { | ||
2729 | u8 status; | ||
2730 | }POSTPACK WMI_SET_QOS_SUPP_CMD; | ||
2731 | |||
2732 | typedef enum { | ||
2733 | WMI_TXOP_DISABLED = 0, | ||
2734 | WMI_TXOP_ENABLED | ||
2735 | } WMI_TXOP_CFG; | ||
2736 | |||
2737 | typedef PREPACK struct { | ||
2738 | u8 txopEnable; | ||
2739 | }POSTPACK WMI_SET_WMM_TXOP_CMD; | ||
2740 | |||
2741 | typedef PREPACK struct { | ||
2742 | u8 keepaliveInterval; | ||
2743 | } POSTPACK WMI_SET_KEEPALIVE_CMD; | ||
2744 | |||
2745 | typedef PREPACK struct { | ||
2746 | u32 configured; | ||
2747 | u8 keepaliveInterval; | ||
2748 | } POSTPACK WMI_GET_KEEPALIVE_CMD; | ||
2749 | |||
2750 | /* | ||
2751 | * Add Application specified IE to a management frame | ||
2752 | */ | ||
2753 | #define WMI_MAX_IE_LEN 255 | ||
2754 | |||
2755 | typedef PREPACK struct { | ||
2756 | u8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ | ||
2757 | u8 ieLen; /* Length of the IE that should be added to the MGMT frame */ | ||
2758 | u8 ieInfo[1]; | ||
2759 | } POSTPACK WMI_SET_APPIE_CMD; | ||
2760 | |||
2761 | /* | ||
2762 | * Notify the WSC registration status to the target | ||
2763 | */ | ||
2764 | #define WSC_REG_ACTIVE 1 | ||
2765 | #define WSC_REG_INACTIVE 0 | ||
2766 | /* Generic Hal Interface for setting hal paramters. */ | ||
2767 | /* Add new Set HAL Param cmdIds here for newer params */ | ||
2768 | typedef enum { | ||
2769 | WHAL_SETCABTO_CMDID = 1, | ||
2770 | }WHAL_CMDID; | ||
2771 | |||
2772 | typedef PREPACK struct { | ||
2773 | u8 cabTimeOut; | ||
2774 | } POSTPACK WHAL_SETCABTO_PARAM; | ||
2775 | |||
2776 | typedef PREPACK struct { | ||
2777 | u8 whalCmdId; | ||
2778 | u8 data[1]; | ||
2779 | } POSTPACK WHAL_PARAMCMD; | ||
2780 | |||
2781 | |||
2782 | #define WOW_MAX_FILTER_LISTS 1 /*4*/ | ||
2783 | #define WOW_MAX_FILTERS_PER_LIST 4 | ||
2784 | #define WOW_PATTERN_SIZE 64 | ||
2785 | #define WOW_MASK_SIZE 64 | ||
2786 | |||
2787 | #define MAC_MAX_FILTERS_PER_LIST 4 | ||
2788 | |||
2789 | typedef PREPACK struct { | ||
2790 | u8 wow_valid_filter; | ||
2791 | u8 wow_filter_id; | ||
2792 | u8 wow_filter_size; | ||
2793 | u8 wow_filter_offset; | ||
2794 | u8 wow_filter_mask[WOW_MASK_SIZE]; | ||
2795 | u8 wow_filter_pattern[WOW_PATTERN_SIZE]; | ||
2796 | } POSTPACK WOW_FILTER; | ||
2797 | |||
2798 | |||
2799 | typedef PREPACK struct { | ||
2800 | u8 wow_valid_list; | ||
2801 | u8 wow_list_id; | ||
2802 | u8 wow_num_filters; | ||
2803 | u8 wow_total_list_size; | ||
2804 | WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST]; | ||
2805 | } POSTPACK WOW_FILTER_LIST; | ||
2806 | |||
2807 | typedef PREPACK struct { | ||
2808 | u8 valid_filter; | ||
2809 | u8 mac_addr[ATH_MAC_LEN]; | ||
2810 | } POSTPACK MAC_FILTER; | ||
2811 | |||
2812 | |||
2813 | typedef PREPACK struct { | ||
2814 | u8 total_list_size; | ||
2815 | u8 enable; | ||
2816 | MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST]; | ||
2817 | } POSTPACK MAC_FILTER_LIST; | ||
2818 | |||
2819 | #define MAX_IP_ADDRS 2 | ||
2820 | typedef PREPACK struct { | ||
2821 | u32 ips[MAX_IP_ADDRS]; /* IP in Network Byte Order */ | ||
2822 | } POSTPACK WMI_SET_IP_CMD; | ||
2823 | |||
2824 | typedef PREPACK struct { | ||
2825 | u32 awake; | ||
2826 | u32 asleep; | ||
2827 | } POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD; | ||
2828 | |||
2829 | typedef enum { | ||
2830 | WOW_FILTER_SSID = 0x1 | ||
2831 | } WMI_WOW_FILTER; | ||
2832 | |||
2833 | typedef PREPACK struct { | ||
2834 | u32 enable_wow; | ||
2835 | WMI_WOW_FILTER filter; | ||
2836 | u16 hostReqDelay; | ||
2837 | } POSTPACK WMI_SET_WOW_MODE_CMD; | ||
2838 | |||
2839 | typedef PREPACK struct { | ||
2840 | u8 filter_list_id; | ||
2841 | } POSTPACK WMI_GET_WOW_LIST_CMD; | ||
2842 | |||
2843 | /* | ||
2844 | * WMI_GET_WOW_LIST_CMD reply | ||
2845 | */ | ||
2846 | typedef PREPACK struct { | ||
2847 | u8 num_filters; /* number of patterns in reply */ | ||
2848 | u8 this_filter_num; /* this is filter # x of total num_filters */ | ||
2849 | u8 wow_mode; | ||
2850 | u8 host_mode; | ||
2851 | WOW_FILTER wow_filters[1]; | ||
2852 | } POSTPACK WMI_GET_WOW_LIST_REPLY; | ||
2853 | |||
2854 | typedef PREPACK struct { | ||
2855 | u8 filter_list_id; | ||
2856 | u8 filter_size; | ||
2857 | u8 filter_offset; | ||
2858 | u8 filter[1]; | ||
2859 | } POSTPACK WMI_ADD_WOW_PATTERN_CMD; | ||
2860 | |||
2861 | typedef PREPACK struct { | ||
2862 | u16 filter_list_id; | ||
2863 | u16 filter_id; | ||
2864 | } POSTPACK WMI_DEL_WOW_PATTERN_CMD; | ||
2865 | |||
2866 | typedef PREPACK struct { | ||
2867 | u8 macaddr[ATH_MAC_LEN]; | ||
2868 | } POSTPACK WMI_SET_MAC_ADDRESS_CMD; | ||
2869 | |||
2870 | /* | ||
2871 | * WMI_SET_AKMP_PARAMS_CMD | ||
2872 | */ | ||
2873 | |||
2874 | #define WMI_AKMP_MULTI_PMKID_EN 0x000001 | ||
2875 | |||
2876 | typedef PREPACK struct { | ||
2877 | u32 akmpInfo; | ||
2878 | } POSTPACK WMI_SET_AKMP_PARAMS_CMD; | ||
2879 | |||
2880 | typedef PREPACK struct { | ||
2881 | u8 pmkid[WMI_PMKID_LEN]; | ||
2882 | } POSTPACK WMI_PMKID; | ||
2883 | |||
2884 | /* | ||
2885 | * WMI_SET_PMKID_LIST_CMD | ||
2886 | */ | ||
2887 | #define WMI_MAX_PMKID_CACHE 8 | ||
2888 | |||
2889 | typedef PREPACK struct { | ||
2890 | u32 numPMKID; | ||
2891 | WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; | ||
2892 | } POSTPACK WMI_SET_PMKID_LIST_CMD; | ||
2893 | |||
2894 | /* | ||
2895 | * WMI_GET_PMKID_LIST_CMD Reply | ||
2896 | * Following the Number of PMKIDs is the list of PMKIDs | ||
2897 | */ | ||
2898 | typedef PREPACK struct { | ||
2899 | u32 numPMKID; | ||
2900 | u8 bssidList[ATH_MAC_LEN][1]; | ||
2901 | WMI_PMKID pmkidList[1]; | ||
2902 | } POSTPACK WMI_PMKID_LIST_REPLY; | ||
2903 | |||
2904 | typedef PREPACK struct { | ||
2905 | u16 oldChannel; | ||
2906 | u32 newChannel; | ||
2907 | } POSTPACK WMI_CHANNEL_CHANGE_EVENT; | ||
2908 | |||
2909 | typedef PREPACK struct { | ||
2910 | u32 version; | ||
2911 | } POSTPACK WMI_WLAN_VERSION_EVENT; | ||
2912 | |||
2913 | |||
2914 | /* WMI_ADDBA_REQ_EVENTID */ | ||
2915 | typedef PREPACK struct { | ||
2916 | u8 tid; | ||
2917 | u8 win_sz; | ||
2918 | u16 st_seq_no; | ||
2919 | u8 status; /* f/w response for ADDBA Req; OK(0) or failure(!=0) */ | ||
2920 | } POSTPACK WMI_ADDBA_REQ_EVENT; | ||
2921 | |||
2922 | /* WMI_ADDBA_RESP_EVENTID */ | ||
2923 | typedef PREPACK struct { | ||
2924 | u8 tid; | ||
2925 | u8 status; /* OK(0), failure (!=0) */ | ||
2926 | u16 amsdu_sz; /* Three values: Not supported(0), 3839, 8k */ | ||
2927 | } POSTPACK WMI_ADDBA_RESP_EVENT; | ||
2928 | |||
2929 | /* WMI_DELBA_EVENTID | ||
2930 | * f/w received a DELBA for peer and processed it. | ||
2931 | * Host is notified of this | ||
2932 | */ | ||
2933 | typedef PREPACK struct { | ||
2934 | u8 tid; | ||
2935 | u8 is_peer_initiator; | ||
2936 | u16 reason_code; | ||
2937 | } POSTPACK WMI_DELBA_EVENT; | ||
2938 | |||
2939 | |||
2940 | #ifdef WAPI_ENABLE | ||
2941 | #define WAPI_REKEY_UCAST 1 | ||
2942 | #define WAPI_REKEY_MCAST 2 | ||
2943 | typedef PREPACK struct { | ||
2944 | u8 type; | ||
2945 | u8 macAddr[ATH_MAC_LEN]; | ||
2946 | } POSTPACK WMI_WAPIREKEY_EVENT; | ||
2947 | #endif | ||
2948 | |||
2949 | |||
2950 | /* WMI_ALLOW_AGGR_CMDID | ||
2951 | * Configures tid's to allow ADDBA negotiations | ||
2952 | * on each tid, in each direction | ||
2953 | */ | ||
2954 | typedef PREPACK struct { | ||
2955 | u16 tx_allow_aggr; /* 16-bit mask to allow uplink ADDBA negotiation - bit position indicates tid*/ | ||
2956 | u16 rx_allow_aggr; /* 16-bit mask to allow donwlink ADDBA negotiation - bit position indicates tid*/ | ||
2957 | } POSTPACK WMI_ALLOW_AGGR_CMD; | ||
2958 | |||
2959 | /* WMI_ADDBA_REQ_CMDID | ||
2960 | * f/w starts performing ADDBA negotiations with peer | ||
2961 | * on the given tid | ||
2962 | */ | ||
2963 | typedef PREPACK struct { | ||
2964 | u8 tid; | ||
2965 | } POSTPACK WMI_ADDBA_REQ_CMD; | ||
2966 | |||
2967 | /* WMI_DELBA_REQ_CMDID | ||
2968 | * f/w would teardown BA with peer. | ||
2969 | * is_send_initiator indicates if it's or tx or rx side | ||
2970 | */ | ||
2971 | typedef PREPACK struct { | ||
2972 | u8 tid; | ||
2973 | u8 is_sender_initiator; | ||
2974 | |||
2975 | } POSTPACK WMI_DELBA_REQ_CMD; | ||
2976 | |||
2977 | #define PEER_NODE_JOIN_EVENT 0x00 | ||
2978 | #define PEER_NODE_LEAVE_EVENT 0x01 | ||
2979 | #define PEER_FIRST_NODE_JOIN_EVENT 0x10 | ||
2980 | #define PEER_LAST_NODE_LEAVE_EVENT 0x11 | ||
2981 | typedef PREPACK struct { | ||
2982 | u8 eventCode; | ||
2983 | u8 peerMacAddr[ATH_MAC_LEN]; | ||
2984 | } POSTPACK WMI_PEER_NODE_EVENT; | ||
2985 | |||
2986 | #define IEEE80211_FRAME_TYPE_MGT 0x00 | ||
2987 | #define IEEE80211_FRAME_TYPE_CTL 0x04 | ||
2988 | |||
2989 | /* | ||
2990 | * Transmit complete event data structure(s) | ||
2991 | */ | ||
2992 | |||
2993 | |||
2994 | typedef PREPACK struct { | ||
2995 | #define TX_COMPLETE_STATUS_SUCCESS 0 | ||
2996 | #define TX_COMPLETE_STATUS_RETRIES 1 | ||
2997 | #define TX_COMPLETE_STATUS_NOLINK 2 | ||
2998 | #define TX_COMPLETE_STATUS_TIMEOUT 3 | ||
2999 | #define TX_COMPLETE_STATUS_OTHER 4 | ||
3000 | |||
3001 | u8 status; /* one of TX_COMPLETE_STATUS_... */ | ||
3002 | u8 pktID; /* packet ID to identify parent packet */ | ||
3003 | u8 rateIdx; /* rate index on successful transmission */ | ||
3004 | u8 ackFailures; /* number of ACK failures in tx attempt */ | ||
3005 | #if 0 /* optional params currently omitted. */ | ||
3006 | u32 queueDelay; // usec delay measured Tx Start time - host delivery time | ||
3007 | u32 mediaDelay; // usec delay measured ACK rx time - host delivery time | ||
3008 | #endif | ||
3009 | } POSTPACK TX_COMPLETE_MSG_V1; /* version 1 of tx complete msg */ | ||
3010 | |||
3011 | typedef PREPACK struct { | ||
3012 | u8 numMessages; /* number of tx comp msgs following this struct */ | ||
3013 | u8 msgLen; /* length in bytes for each individual msg following this struct */ | ||
3014 | u8 msgType; /* version of tx complete msg data following this struct */ | ||
3015 | u8 reserved; /* individual messages follow this header */ | ||
3016 | } POSTPACK WMI_TX_COMPLETE_EVENT; | ||
3017 | |||
3018 | #define WMI_TXCOMPLETE_VERSION_1 (0x01) | ||
3019 | |||
3020 | |||
3021 | /* | ||
3022 | * ------- AP Mode definitions -------------- | ||
3023 | */ | ||
3024 | |||
3025 | /* | ||
3026 | * !!! Warning !!! | ||
3027 | * -Changing the following values needs compilation of both driver and firmware | ||
3028 | */ | ||
3029 | #ifdef AR6002_REV2 | ||
3030 | #define AP_MAX_NUM_STA 4 | ||
3031 | #else | ||
3032 | #define AP_MAX_NUM_STA 8 | ||
3033 | #endif | ||
3034 | #define AP_ACL_SIZE 10 | ||
3035 | #define IEEE80211_MAX_IE 256 | ||
3036 | #define MCAST_AID 0xFF /* Spl. AID used to set DTIM flag in the beacons */ | ||
3037 | #define DEF_AP_COUNTRY_CODE "US " | ||
3038 | #define DEF_AP_WMODE_G WMI_11G_MODE | ||
3039 | #define DEF_AP_WMODE_AG WMI_11AG_MODE | ||
3040 | #define DEF_AP_DTIM 5 | ||
3041 | #define DEF_BEACON_INTERVAL 100 | ||
3042 | |||
3043 | /* AP mode disconnect reasons */ | ||
3044 | #define AP_DISCONNECT_STA_LEFT 101 | ||
3045 | #define AP_DISCONNECT_FROM_HOST 102 | ||
3046 | #define AP_DISCONNECT_COMM_TIMEOUT 103 | ||
3047 | |||
3048 | /* | ||
3049 | * Used with WMI_AP_HIDDEN_SSID_CMDID | ||
3050 | */ | ||
3051 | #define HIDDEN_SSID_FALSE 0 | ||
3052 | #define HIDDEN_SSID_TRUE 1 | ||
3053 | typedef PREPACK struct { | ||
3054 | u8 hidden_ssid; | ||
3055 | } POSTPACK WMI_AP_HIDDEN_SSID_CMD; | ||
3056 | |||
3057 | /* | ||
3058 | * Used with WMI_AP_ACL_POLICY_CMDID | ||
3059 | */ | ||
3060 | #define AP_ACL_DISABLE 0x00 | ||
3061 | #define AP_ACL_ALLOW_MAC 0x01 | ||
3062 | #define AP_ACL_DENY_MAC 0x02 | ||
3063 | #define AP_ACL_RETAIN_LIST_MASK 0x80 | ||
3064 | typedef PREPACK struct { | ||
3065 | u8 policy; | ||
3066 | } POSTPACK WMI_AP_ACL_POLICY_CMD; | ||
3067 | |||
3068 | /* | ||
3069 | * Used with WMI_AP_ACL_MAC_LIST_CMDID | ||
3070 | */ | ||
3071 | #define ADD_MAC_ADDR 1 | ||
3072 | #define DEL_MAC_ADDR 2 | ||
3073 | typedef PREPACK struct { | ||
3074 | u8 action; | ||
3075 | u8 index; | ||
3076 | u8 mac[ATH_MAC_LEN]; | ||
3077 | u8 wildcard; | ||
3078 | } POSTPACK WMI_AP_ACL_MAC_CMD; | ||
3079 | |||
3080 | typedef PREPACK struct { | ||
3081 | u16 index; | ||
3082 | u8 acl_mac[AP_ACL_SIZE][ATH_MAC_LEN]; | ||
3083 | u8 wildcard[AP_ACL_SIZE]; | ||
3084 | u8 policy; | ||
3085 | } POSTPACK WMI_AP_ACL; | ||
3086 | |||
3087 | /* | ||
3088 | * Used with WMI_AP_SET_NUM_STA_CMDID | ||
3089 | */ | ||
3090 | typedef PREPACK struct { | ||
3091 | u8 num_sta; | ||
3092 | } POSTPACK WMI_AP_SET_NUM_STA_CMD; | ||
3093 | |||
3094 | /* | ||
3095 | * Used with WMI_AP_SET_MLME_CMDID | ||
3096 | */ | ||
3097 | typedef PREPACK struct { | ||
3098 | u8 mac[ATH_MAC_LEN]; | ||
3099 | u16 reason; /* 802.11 reason code */ | ||
3100 | u8 cmd; /* operation to perform */ | ||
3101 | #define WMI_AP_MLME_ASSOC 1 /* associate station */ | ||
3102 | #define WMI_AP_DISASSOC 2 /* disassociate station */ | ||
3103 | #define WMI_AP_DEAUTH 3 /* deauthenticate station */ | ||
3104 | #define WMI_AP_MLME_AUTHORIZE 4 /* authorize station */ | ||
3105 | #define WMI_AP_MLME_UNAUTHORIZE 5 /* unauthorize station */ | ||
3106 | } POSTPACK WMI_AP_SET_MLME_CMD; | ||
3107 | |||
3108 | typedef PREPACK struct { | ||
3109 | u32 period; | ||
3110 | } POSTPACK WMI_AP_CONN_INACT_CMD; | ||
3111 | |||
3112 | typedef PREPACK struct { | ||
3113 | u32 period_min; | ||
3114 | u32 dwell_ms; | ||
3115 | } POSTPACK WMI_AP_PROT_SCAN_TIME_CMD; | ||
3116 | |||
3117 | typedef PREPACK struct { | ||
3118 | u32 flag; | ||
3119 | u16 aid; | ||
3120 | } POSTPACK WMI_AP_SET_PVB_CMD; | ||
3121 | |||
3122 | #define WMI_DISABLE_REGULATORY_CODE "FF" | ||
3123 | |||
3124 | typedef PREPACK struct { | ||
3125 | u8 countryCode[3]; | ||
3126 | } POSTPACK WMI_AP_SET_COUNTRY_CMD; | ||
3127 | |||
3128 | typedef PREPACK struct { | ||
3129 | u8 dtim; | ||
3130 | } POSTPACK WMI_AP_SET_DTIM_CMD; | ||
3131 | |||
3132 | typedef PREPACK struct { | ||
3133 | u8 band; /* specifies which band to apply these values */ | ||
3134 | u8 enable; /* allows 11n to be disabled on a per band basis */ | ||
3135 | u8 chan_width_40M_supported; | ||
3136 | u8 short_GI_20MHz; | ||
3137 | u8 short_GI_40MHz; | ||
3138 | u8 intolerance_40MHz; | ||
3139 | u8 max_ampdu_len_exp; | ||
3140 | } POSTPACK WMI_SET_HT_CAP_CMD; | ||
3141 | |||
3142 | typedef PREPACK struct { | ||
3143 | u8 sta_chan_width; | ||
3144 | } POSTPACK WMI_SET_HT_OP_CMD; | ||
3145 | |||
3146 | typedef PREPACK struct { | ||
3147 | u32 rateMasks[8]; | ||
3148 | } POSTPACK WMI_SET_TX_SELECT_RATES_CMD; | ||
3149 | |||
3150 | typedef PREPACK struct { | ||
3151 | u32 sgiMask; | ||
3152 | u8 sgiPERThreshold; | ||
3153 | } POSTPACK WMI_SET_TX_SGI_PARAM_CMD; | ||
3154 | |||
3155 | #define DEFAULT_SGI_MASK 0x08080000 | ||
3156 | #define DEFAULT_SGI_PER 10 | ||
3157 | |||
3158 | typedef PREPACK struct { | ||
3159 | u32 rateField; /* 1 bit per rate corresponding to index */ | ||
3160 | u8 id; | ||
3161 | u8 shortTrys; | ||
3162 | u8 longTrys; | ||
3163 | u8 reserved; /* padding */ | ||
3164 | } POSTPACK WMI_SET_RATE_POLICY_CMD; | ||
3165 | |||
3166 | typedef PREPACK struct { | ||
3167 | u8 metaVersion; /* version of meta data for rx packets <0 = default> (0-7 = valid) */ | ||
3168 | u8 dot11Hdr; /* 1 == leave .11 header intact , 0 == replace .11 header with .3 <default> */ | ||
3169 | u8 defragOnHost; /* 1 == defragmentation is performed by host, 0 == performed by target <default> */ | ||
3170 | u8 reserved[1]; /* alignment */ | ||
3171 | } POSTPACK WMI_RX_FRAME_FORMAT_CMD; | ||
3172 | |||
3173 | |||
3174 | typedef PREPACK struct { | ||
3175 | u8 enable; /* 1 == device operates in thin mode , 0 == normal mode <default> */ | ||
3176 | u8 reserved[3]; | ||
3177 | } POSTPACK WMI_SET_THIN_MODE_CMD; | ||
3178 | |||
3179 | /* AP mode events */ | ||
3180 | /* WMI_PS_POLL_EVENT */ | ||
3181 | typedef PREPACK struct { | ||
3182 | u16 aid; | ||
3183 | } POSTPACK WMI_PSPOLL_EVENT; | ||
3184 | |||
3185 | typedef PREPACK struct { | ||
3186 | u32 tx_bytes; | ||
3187 | u32 tx_pkts; | ||
3188 | u32 tx_error; | ||
3189 | u32 tx_discard; | ||
3190 | u32 rx_bytes; | ||
3191 | u32 rx_pkts; | ||
3192 | u32 rx_error; | ||
3193 | u32 rx_discard; | ||
3194 | u32 aid; | ||
3195 | } POSTPACK WMI_PER_STA_STAT; | ||
3196 | |||
3197 | #define AP_GET_STATS 0 | ||
3198 | #define AP_CLEAR_STATS 1 | ||
3199 | |||
3200 | typedef PREPACK struct { | ||
3201 | u32 action; | ||
3202 | WMI_PER_STA_STAT sta[AP_MAX_NUM_STA+1]; | ||
3203 | } POSTPACK WMI_AP_MODE_STAT; | ||
3204 | #define WMI_AP_MODE_STAT_SIZE(numSta) (sizeof(u32) + ((numSta + 1) * sizeof(WMI_PER_STA_STAT))) | ||
3205 | |||
3206 | #define AP_11BG_RATESET1 1 | ||
3207 | #define AP_11BG_RATESET2 2 | ||
3208 | #define DEF_AP_11BG_RATESET AP_11BG_RATESET1 | ||
3209 | typedef PREPACK struct { | ||
3210 | u8 rateset; | ||
3211 | } POSTPACK WMI_AP_SET_11BG_RATESET_CMD; | ||
3212 | /* | ||
3213 | * End of AP mode definitions | ||
3214 | */ | ||
3215 | |||
3216 | #ifdef __cplusplus | ||
3217 | } | ||
3218 | #endif | ||
3219 | |||
3220 | #endif /* _WMI_H_ */ | ||
diff --git a/drivers/staging/ath6kl/include/common/wmix.h b/drivers/staging/ath6kl/include/common/wmix.h new file mode 100644 index 00000000000..9435eab1b7f --- /dev/null +++ b/drivers/staging/ath6kl/include/common/wmix.h | |||
@@ -0,0 +1,271 @@ | |||
1 | //------------------------------------------------------------------------------ | ||
2 | // <copyright file="wmix.h" company="Atheros"> | ||
3 | // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. | ||
4 | // | ||
5 | // | ||
6 | // Permission to use, copy, modify, and/or distribute this software for any | ||
7 | // purpose with or without fee is hereby granted, provided that the above | ||
8 | // copyright notice and this permission notice appear in all copies. | ||
9 | // | ||
10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
11 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
12 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
13 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
14 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
15 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
16 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
17 | // | ||
18 | // | ||
19 | //------------------------------------------------------------------------------ | ||
20 | //============================================================================== | ||
21 | // Author(s): ="Atheros" | ||
22 | //============================================================================== | ||
23 | |||
24 | /* | ||
25 | * This file contains extensions of the WMI protocol specified in the | ||
26 | * Wireless Module Interface (WMI). It includes definitions of all | ||
27 | * extended commands and events. Extensions include useful commands | ||
28 | * that are not directly related to wireless activities. They may | ||
29 | * be hardware-specific, and they might not be supported on all | ||
30 | * implementations. | ||
31 | * | ||
32 | * Extended WMIX commands are encapsulated in a WMI message with | ||
33 | * cmd=WMI_EXTENSION_CMD. | ||
34 | */ | ||
35 | |||
36 | #ifndef _WMIX_H_ | ||
37 | #define _WMIX_H_ | ||
38 | |||
39 | #ifdef __cplusplus | ||
40 | extern "C" { | ||
41 | #endif | ||
42 | |||
43 | #include "dbglog.h" | ||
44 | |||
45 | /* | ||
46 | * Extended WMI commands are those that are needed during wireless | ||
47 | * operation, but which are not really wireless commands. This allows, | ||
48 | * for instance, platform-specific commands. Extended WMI commands are | ||
49 | * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. | ||
50 | * Extended WMI events are similarly embedded in a WMI event message with | ||
51 | * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. | ||
52 | */ | ||
53 | typedef PREPACK struct { | ||
54 | u32 commandId; | ||
55 | } POSTPACK WMIX_CMD_HDR; | ||
56 | |||
57 | typedef enum { | ||
58 | WMIX_DSETOPEN_REPLY_CMDID = 0x2001, | ||
59 | WMIX_DSETDATA_REPLY_CMDID, | ||
60 | WMIX_GPIO_OUTPUT_SET_CMDID, | ||
61 | WMIX_GPIO_INPUT_GET_CMDID, | ||
62 | WMIX_GPIO_REGISTER_SET_CMDID, | ||
63 | WMIX_GPIO_REGISTER_GET_CMDID, | ||
64 | WMIX_GPIO_INTR_ACK_CMDID, | ||
65 | WMIX_HB_CHALLENGE_RESP_CMDID, | ||
66 | WMIX_DBGLOG_CFG_MODULE_CMDID, | ||
67 | WMIX_PROF_CFG_CMDID, /* 0x200a */ | ||
68 | WMIX_PROF_ADDR_SET_CMDID, | ||
69 | WMIX_PROF_START_CMDID, | ||
70 | WMIX_PROF_STOP_CMDID, | ||
71 | WMIX_PROF_COUNT_GET_CMDID, | ||
72 | } WMIX_COMMAND_ID; | ||
73 | |||
74 | typedef enum { | ||
75 | WMIX_DSETOPENREQ_EVENTID = 0x3001, | ||
76 | WMIX_DSETCLOSE_EVENTID, | ||
77 | WMIX_DSETDATAREQ_EVENTID, | ||
78 | WMIX_GPIO_INTR_EVENTID, | ||
79 | WMIX_GPIO_DATA_EVENTID, | ||
80 | WMIX_GPIO_ACK_EVENTID, | ||
81 | WMIX_HB_CHALLENGE_RESP_EVENTID, | ||
82 | WMIX_DBGLOG_EVENTID, | ||
83 | WMIX_PROF_COUNT_EVENTID, | ||
84 | } WMIX_EVENT_ID; | ||
85 | |||
86 | /* | ||
87 | * =============DataSet support================= | ||
88 | */ | ||
89 | |||
90 | /* | ||
91 | * WMIX_DSETOPENREQ_EVENTID | ||
92 | * DataSet Open Request Event | ||
93 | */ | ||
94 | typedef PREPACK struct { | ||
95 | u32 dset_id; | ||
96 | u32 targ_dset_handle; /* echo'ed, not used by Host, */ | ||
97 | u32 targ_reply_fn; /* echo'ed, not used by Host, */ | ||
98 | u32 targ_reply_arg; /* echo'ed, not used by Host, */ | ||
99 | } POSTPACK WMIX_DSETOPENREQ_EVENT; | ||
100 | |||
101 | /* | ||
102 | * WMIX_DSETCLOSE_EVENTID | ||
103 | * DataSet Close Event | ||
104 | */ | ||
105 | typedef PREPACK struct { | ||
106 | u32 access_cookie; | ||
107 | } POSTPACK WMIX_DSETCLOSE_EVENT; | ||
108 | |||
109 | /* | ||
110 | * WMIX_DSETDATAREQ_EVENTID | ||
111 | * DataSet Data Request Event | ||
112 | */ | ||
113 | typedef PREPACK struct { | ||
114 | u32 access_cookie; | ||
115 | u32 offset; | ||
116 | u32 length; | ||
117 | u32 targ_buf; /* echo'ed, not used by Host, */ | ||
118 | u32 targ_reply_fn; /* echo'ed, not used by Host, */ | ||
119 | u32 targ_reply_arg; /* echo'ed, not used by Host, */ | ||
120 | } POSTPACK WMIX_DSETDATAREQ_EVENT; | ||
121 | |||
122 | typedef PREPACK struct { | ||
123 | u32 status; | ||
124 | u32 targ_dset_handle; | ||
125 | u32 targ_reply_fn; | ||
126 | u32 targ_reply_arg; | ||
127 | u32 access_cookie; | ||
128 | u32 size; | ||
129 | u32 version; | ||
130 | } POSTPACK WMIX_DSETOPEN_REPLY_CMD; | ||
131 | |||
132 | typedef PREPACK struct { | ||
133 | u32 status; | ||
134 | u32 targ_buf; | ||
135 | u32 targ_reply_fn; | ||
136 | u32 targ_reply_arg; | ||
137 | u32 length; | ||
138 | u8 buf[1]; | ||
139 | } POSTPACK WMIX_DSETDATA_REPLY_CMD; | ||
140 | |||
141 | |||
142 | /* | ||
143 | * =============GPIO support================= | ||
144 | * All masks are 18-bit masks with bit N operating on GPIO pin N. | ||
145 | */ | ||
146 | |||
147 | |||
148 | /* | ||
149 | * Set GPIO pin output state. | ||
150 | * In order for output to be driven, a pin must be enabled for output. | ||
151 | * This can be done during initialization through the GPIO Configuration | ||
152 | * DataSet, or during operation with the enable_mask. | ||
153 | * | ||
154 | * If a request is made to simultaneously set/clear or set/disable or | ||
155 | * clear/disable or disable/enable, results are undefined. | ||
156 | */ | ||
157 | typedef PREPACK struct { | ||
158 | u32 set_mask; /* pins to set */ | ||
159 | u32 clear_mask; /* pins to clear */ | ||
160 | u32 enable_mask; /* pins to enable for output */ | ||
161 | u32 disable_mask; /* pins to disable/tristate */ | ||
162 | } POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; | ||
163 | |||
164 | /* | ||
165 | * Set a GPIO register. For debug/exceptional cases. | ||
166 | * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a | ||
167 | * platform-dependent header. | ||
168 | */ | ||
169 | typedef PREPACK struct { | ||
170 | u32 gpioreg_id; /* GPIO register ID */ | ||
171 | u32 value; /* value to write */ | ||
172 | } POSTPACK WMIX_GPIO_REGISTER_SET_CMD; | ||
173 | |||
174 | /* Get a GPIO register. For debug/exceptional cases. */ | ||
175 | typedef PREPACK struct { | ||
176 | u32 gpioreg_id; /* GPIO register to read */ | ||
177 | } POSTPACK WMIX_GPIO_REGISTER_GET_CMD; | ||
178 | |||
179 | /* | ||
180 | * Host acknowledges and re-arms GPIO interrupts. A single | ||
181 | * message should be used to acknowledge all interrupts that | ||
182 | * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. | ||
183 | */ | ||
184 | typedef PREPACK struct { | ||
185 | u32 ack_mask; /* interrupts to acknowledge */ | ||
186 | } POSTPACK WMIX_GPIO_INTR_ACK_CMD; | ||
187 | |||
188 | /* | ||
189 | * Target informs Host of GPIO interrupts that have occurred since the | ||
190 | * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- | ||
191 | * the current GPIO input values is provided -- in order to support | ||
192 | * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. | ||
193 | */ | ||
194 | typedef PREPACK struct { | ||
195 | u32 intr_mask; /* pending GPIO interrupts */ | ||
196 | u32 input_values; /* recent GPIO input values */ | ||
197 | } POSTPACK WMIX_GPIO_INTR_EVENT; | ||
198 | |||
199 | /* | ||
200 | * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request | ||
201 | * using a GPIO_DATA_EVENT with | ||
202 | * value set to the mask of GPIO pin inputs and | ||
203 | * reg_id set to GPIO_ID_NONE | ||
204 | * | ||
205 | * | ||
206 | * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request | ||
207 | * using a GPIO_DATA_EVENT with | ||
208 | * value set to the value of the requested register and | ||
209 | * reg_id identifying the register (reflects the original request) | ||
210 | * NB: reg_id supports the future possibility of unsolicited | ||
211 | * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may | ||
212 | * simplify Host GPIO support. | ||
213 | */ | ||
214 | typedef PREPACK struct { | ||
215 | u32 value; | ||
216 | u32 reg_id; | ||
217 | } POSTPACK WMIX_GPIO_DATA_EVENT; | ||
218 | |||
219 | /* | ||
220 | * =============Error Detection support================= | ||
221 | */ | ||
222 | |||
223 | /* | ||
224 | * WMIX_HB_CHALLENGE_RESP_CMDID | ||
225 | * Heartbeat Challenge Response command | ||
226 | */ | ||
227 | typedef PREPACK struct { | ||
228 | u32 cookie; | ||
229 | u32 source; | ||
230 | } POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; | ||
231 | |||
232 | /* | ||
233 | * WMIX_HB_CHALLENGE_RESP_EVENTID | ||
234 | * Heartbeat Challenge Response Event | ||
235 | */ | ||
236 | #define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD | ||
237 | |||
238 | typedef PREPACK struct { | ||
239 | struct dbglog_config_s config; | ||
240 | } POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD; | ||
241 | |||
242 | /* | ||
243 | * =============Target Profiling support================= | ||
244 | */ | ||
245 | |||
246 | typedef PREPACK struct { | ||
247 | u32 period; /* Time (in 30.5us ticks) between samples */ | ||
248 | u32 nbins; | ||
249 | } POSTPACK WMIX_PROF_CFG_CMD; | ||
250 | |||
251 | typedef PREPACK struct { | ||
252 | u32 addr; | ||
253 | } POSTPACK WMIX_PROF_ADDR_SET_CMD; | ||
254 | |||
255 | /* | ||
256 | * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request | ||
257 | * using a WMIX_PROF_COUNT_EVENT with | ||
258 | * addr set to the next address | ||
259 | * count set to the corresponding count | ||
260 | */ | ||
261 | typedef PREPACK struct { | ||
262 | u32 addr; | ||
263 | u32 count; | ||
264 | } POSTPACK WMIX_PROF_COUNT_EVENT; | ||
265 | |||
266 | |||
267 | #ifdef __cplusplus | ||
268 | } | ||
269 | #endif | ||
270 | |||
271 | #endif /* _WMIX_H_ */ | ||