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-rw-r--r--drivers/spi/Kconfig2
-rw-r--r--drivers/spi/spi-omap-uwire.c5
-rw-r--r--drivers/spi/spi-omap2-mcspi.c2
-rw-r--r--drivers/spi/spi-tegra.c55
4 files changed, 6 insertions, 58 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5f84b5563c2..2d198a01a41 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -366,7 +366,7 @@ config SPI_STMP3XXX
366 366
367config SPI_TEGRA 367config SPI_TEGRA
368 tristate "Nvidia Tegra SPI controller" 368 tristate "Nvidia Tegra SPI controller"
369 depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA) 369 depends on ARCH_TEGRA && TEGRA20_APB_DMA
370 help 370 help
371 SPI driver for NVidia Tegra SoCs 371 SPI driver for NVidia Tegra SoCs
372 372
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 9b0d7169603..0a94d9dc9c3 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -52,8 +52,9 @@
52#include <asm/io.h> 52#include <asm/io.h>
53#include <asm/mach-types.h> 53#include <asm/mach-types.h>
54 54
55#include <plat/mux.h> 55#include <mach/mux.h>
56#include <plat/omap7xx.h> /* OMAP7XX_IO_CONF registers */ 56
57#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
57 58
58 59
59/* FIXME address is now a platform device resource, 60/* FIXME address is now a platform device resource,
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 569714ebffe..5d59a69a906 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -42,7 +42,7 @@
42#include <linux/spi/spi.h> 42#include <linux/spi/spi.h>
43 43
44#include <plat/clock.h> 44#include <plat/clock.h>
45#include <plat/mcspi.h> 45#include <linux/platform_data/spi-omap2-mcspi.h>
46 46
47#define OMAP2_MCSPI_MAX_FREQ 48000000 47#define OMAP2_MCSPI_MAX_FREQ 48000000
48#define SPI_AUTOSUSPEND_TIMEOUT 2000 48#define SPI_AUTOSUSPEND_TIMEOUT 2000
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index ef52c1c6f5c..488d9b6e9cb 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -164,23 +164,15 @@ struct spi_tegra_data {
164 * for the generic case. 164 * for the generic case.
165 */ 165 */
166 int dma_req_len; 166 int dma_req_len;
167#if defined(CONFIG_TEGRA_SYSTEM_DMA)
168 struct tegra_dma_req rx_dma_req;
169 struct tegra_dma_channel *rx_dma;
170#else
171 struct dma_chan *rx_dma; 167 struct dma_chan *rx_dma;
172 struct dma_slave_config sconfig; 168 struct dma_slave_config sconfig;
173 struct dma_async_tx_descriptor *rx_dma_desc; 169 struct dma_async_tx_descriptor *rx_dma_desc;
174 dma_cookie_t rx_cookie; 170 dma_cookie_t rx_cookie;
175#endif
176 u32 *rx_bb; 171 u32 *rx_bb;
177 dma_addr_t rx_bb_phys; 172 dma_addr_t rx_bb_phys;
178}; 173};
179 174
180#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
181static void tegra_spi_rx_dma_complete(void *args); 175static void tegra_spi_rx_dma_complete(void *args);
182#endif
183
184static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi, 176static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
185 unsigned long reg) 177 unsigned long reg)
186{ 178{
@@ -204,10 +196,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
204 val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN; 196 val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
205 val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1); 197 val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
206 spi_tegra_writel(tspi, val, SLINK_DMA_CTL); 198 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
207#if defined(CONFIG_TEGRA_SYSTEM_DMA)
208 tspi->rx_dma_req.size = tspi->dma_req_len;
209 tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
210#else
211 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma, 199 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
212 tspi->rx_bb_phys, tspi->dma_req_len, 200 tspi->rx_bb_phys, tspi->dma_req_len,
213 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 201 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
@@ -219,7 +207,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
219 tspi->rx_dma_desc->callback_param = tspi; 207 tspi->rx_dma_desc->callback_param = tspi;
220 tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc); 208 tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
221 dma_async_issue_pending(tspi->rx_dma); 209 dma_async_issue_pending(tspi->rx_dma);
222#endif
223 210
224 val |= SLINK_DMA_EN; 211 val |= SLINK_DMA_EN;
225 spi_tegra_writel(tspi, val, SLINK_DMA_CTL); 212 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
@@ -405,19 +392,12 @@ static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
405 392
406 spin_unlock_irqrestore(&tspi->lock, flags); 393 spin_unlock_irqrestore(&tspi->lock, flags);
407} 394}
408#if defined(CONFIG_TEGRA_SYSTEM_DMA) 395
409static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
410{
411 struct spi_tegra_data *tspi = req->dev;
412 handle_spi_rx_dma_complete(tspi);
413}
414#else
415static void tegra_spi_rx_dma_complete(void *args) 396static void tegra_spi_rx_dma_complete(void *args)
416{ 397{
417 struct spi_tegra_data *tspi = args; 398 struct spi_tegra_data *tspi = args;
418 handle_spi_rx_dma_complete(tspi); 399 handle_spi_rx_dma_complete(tspi);
419} 400}
420#endif
421 401
422static int spi_tegra_setup(struct spi_device *spi) 402static int spi_tegra_setup(struct spi_device *spi)
423{ 403{
@@ -509,9 +489,7 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
509 struct spi_tegra_data *tspi; 489 struct spi_tegra_data *tspi;
510 struct resource *r; 490 struct resource *r;
511 int ret; 491 int ret;
512#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
513 dma_cap_mask_t mask; 492 dma_cap_mask_t mask;
514#endif
515 493
516 master = spi_alloc_master(&pdev->dev, sizeof *tspi); 494 master = spi_alloc_master(&pdev->dev, sizeof *tspi);
517 if (master == NULL) { 495 if (master == NULL) {
@@ -563,14 +541,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
563 541
564 INIT_LIST_HEAD(&tspi->queue); 542 INIT_LIST_HEAD(&tspi->queue);
565 543
566#if defined(CONFIG_TEGRA_SYSTEM_DMA)
567 tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
568 if (!tspi->rx_dma) {
569 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
570 ret = -ENODEV;
571 goto err3;
572 }
573#else
574 dma_cap_zero(mask); 544 dma_cap_zero(mask);
575 dma_cap_set(DMA_SLAVE, mask); 545 dma_cap_set(DMA_SLAVE, mask);
576 tspi->rx_dma = dma_request_channel(mask, NULL, NULL); 546 tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
@@ -580,8 +550,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
580 goto err3; 550 goto err3;
581 } 551 }
582 552
583#endif
584
585 tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN, 553 tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
586 &tspi->rx_bb_phys, GFP_KERNEL); 554 &tspi->rx_bb_phys, GFP_KERNEL);
587 if (!tspi->rx_bb) { 555 if (!tspi->rx_bb) {
@@ -590,17 +558,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
590 goto err4; 558 goto err4;
591 } 559 }
592 560
593#if defined(CONFIG_TEGRA_SYSTEM_DMA)
594 tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
595 tspi->rx_dma_req.to_memory = 1;
596 tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
597 tspi->rx_dma_req.dest_bus_width = 32;
598 tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
599 tspi->rx_dma_req.source_bus_width = 32;
600 tspi->rx_dma_req.source_wrap = 4;
601 tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
602 tspi->rx_dma_req.dev = tspi;
603#else
604 /* Dmaengine Dma slave config */ 561 /* Dmaengine Dma slave config */
605 tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; 562 tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
606 tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO; 563 tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
@@ -616,7 +573,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
616 ret); 573 ret);
617 goto err4; 574 goto err4;
618 } 575 }
619#endif
620 576
621 master->dev.of_node = pdev->dev.of_node; 577 master->dev.of_node = pdev->dev.of_node;
622 ret = spi_register_master(master); 578 ret = spi_register_master(master);
@@ -630,11 +586,7 @@ err5:
630 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, 586 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
631 tspi->rx_bb, tspi->rx_bb_phys); 587 tspi->rx_bb, tspi->rx_bb_phys);
632err4: 588err4:
633#if defined(CONFIG_TEGRA_SYSTEM_DMA)
634 tegra_dma_free_channel(tspi->rx_dma);
635#else
636 dma_release_channel(tspi->rx_dma); 589 dma_release_channel(tspi->rx_dma);
637#endif
638err3: 590err3:
639 clk_put(tspi->clk); 591 clk_put(tspi->clk);
640err2: 592err2:
@@ -656,12 +608,7 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev)
656 tspi = spi_master_get_devdata(master); 608 tspi = spi_master_get_devdata(master);
657 609
658 spi_unregister_master(master); 610 spi_unregister_master(master);
659#if defined(CONFIG_TEGRA_SYSTEM_DMA)
660 tegra_dma_free_channel(tspi->rx_dma);
661#else
662 dma_release_channel(tspi->rx_dma); 611 dma_release_channel(tspi->rx_dma);
663#endif
664
665 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, 612 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
666 tspi->rx_bb, tspi->rx_bb_phys); 613 tspi->rx_bb, tspi->rx_bb_phys);
667 614