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path: root/drivers/sh/pfc.c
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-rw-r--r--drivers/sh/pfc.c577
1 files changed, 577 insertions, 0 deletions
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
new file mode 100644
index 00000000000..841ed5030c8
--- /dev/null
+++ b/drivers/sh/pfc.c
@@ -0,0 +1,577 @@
1/*
2 * Pinmuxed GPIO support for SuperH.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/bitops.h>
19#include <linux/gpio.h>
20
21static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
22{
23 if (enum_id < r->begin)
24 return 0;
25
26 if (enum_id > r->end)
27 return 0;
28
29 return 1;
30}
31
32static unsigned long gpio_read_raw_reg(unsigned long reg,
33 unsigned long reg_width)
34{
35 switch (reg_width) {
36 case 8:
37 return __raw_readb(reg);
38 case 16:
39 return __raw_readw(reg);
40 case 32:
41 return __raw_readl(reg);
42 }
43
44 BUG();
45 return 0;
46}
47
48static void gpio_write_raw_reg(unsigned long reg,
49 unsigned long reg_width,
50 unsigned long data)
51{
52 switch (reg_width) {
53 case 8:
54 __raw_writeb(data, reg);
55 return;
56 case 16:
57 __raw_writew(data, reg);
58 return;
59 case 32:
60 __raw_writel(data, reg);
61 return;
62 }
63
64 BUG();
65}
66
67static void gpio_write_bit(struct pinmux_data_reg *dr,
68 unsigned long in_pos, unsigned long value)
69{
70 unsigned long pos;
71
72 pos = dr->reg_width - (in_pos + 1);
73
74 pr_debug("write_bit addr = %lx, value = %ld, pos = %ld, "
75 "r_width = %ld\n",
76 dr->reg, !!value, pos, dr->reg_width);
77
78 if (value)
79 set_bit(pos, &dr->reg_shadow);
80 else
81 clear_bit(pos, &dr->reg_shadow);
82
83 gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
84}
85
86static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
87 unsigned long field_width, unsigned long in_pos)
88{
89 unsigned long data, mask, pos;
90
91 data = 0;
92 mask = (1 << field_width) - 1;
93 pos = reg_width - ((in_pos + 1) * field_width);
94
95 pr_debug("read_reg: addr = %lx, pos = %ld, "
96 "r_width = %ld, f_width = %ld\n",
97 reg, pos, reg_width, field_width);
98
99 data = gpio_read_raw_reg(reg, reg_width);
100 return (data >> pos) & mask;
101}
102
103static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
104 unsigned long field_width, unsigned long in_pos,
105 unsigned long value)
106{
107 unsigned long mask, pos;
108
109 mask = (1 << field_width) - 1;
110 pos = reg_width - ((in_pos + 1) * field_width);
111
112 pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
113 "r_width = %ld, f_width = %ld\n",
114 reg, value, pos, reg_width, field_width);
115
116 mask = ~(mask << pos);
117 value = value << pos;
118
119 switch (reg_width) {
120 case 8:
121 __raw_writeb((__raw_readb(reg) & mask) | value, reg);
122 break;
123 case 16:
124 __raw_writew((__raw_readw(reg) & mask) | value, reg);
125 break;
126 case 32:
127 __raw_writel((__raw_readl(reg) & mask) | value, reg);
128 break;
129 }
130}
131
132static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
133{
134 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
135 struct pinmux_data_reg *data_reg;
136 int k, n;
137
138 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
139 return -1;
140
141 k = 0;
142 while (1) {
143 data_reg = gpioc->data_regs + k;
144
145 if (!data_reg->reg_width)
146 break;
147
148 for (n = 0; n < data_reg->reg_width; n++) {
149 if (data_reg->enum_ids[n] == gpiop->enum_id) {
150 gpiop->flags &= ~PINMUX_FLAG_DREG;
151 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
152 gpiop->flags &= ~PINMUX_FLAG_DBIT;
153 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
154 return 0;
155 }
156 }
157 k++;
158 }
159
160 BUG();
161
162 return -1;
163}
164
165static void setup_data_regs(struct pinmux_info *gpioc)
166{
167 struct pinmux_data_reg *drp;
168 int k;
169
170 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
171 setup_data_reg(gpioc, k);
172
173 k = 0;
174 while (1) {
175 drp = gpioc->data_regs + k;
176
177 if (!drp->reg_width)
178 break;
179
180 drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
181 k++;
182 }
183}
184
185static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
186 struct pinmux_data_reg **drp, int *bitp)
187{
188 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
189 int k, n;
190
191 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
192 return -1;
193
194 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
195 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
196 *drp = gpioc->data_regs + k;
197 *bitp = n;
198 return 0;
199}
200
201static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
202 struct pinmux_cfg_reg **crp, int *indexp,
203 unsigned long **cntp)
204{
205 struct pinmux_cfg_reg *config_reg;
206 unsigned long r_width, f_width;
207 int k, n;
208
209 k = 0;
210 while (1) {
211 config_reg = gpioc->cfg_regs + k;
212
213 r_width = config_reg->reg_width;
214 f_width = config_reg->field_width;
215
216 if (!r_width)
217 break;
218 for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
219 if (config_reg->enum_ids[n] == enum_id) {
220 *crp = config_reg;
221 *indexp = n;
222 *cntp = &config_reg->cnt[n / (1 << f_width)];
223 return 0;
224 }
225 }
226 k++;
227 }
228
229 return -1;
230}
231
232static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
233 int pos, pinmux_enum_t *enum_idp)
234{
235 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
236 pinmux_enum_t *data = gpioc->gpio_data;
237 int k;
238
239 if (!enum_in_range(enum_id, &gpioc->data)) {
240 if (!enum_in_range(enum_id, &gpioc->mark)) {
241 pr_err("non data/mark enum_id for gpio %d\n", gpio);
242 return -1;
243 }
244 }
245
246 if (pos) {
247 *enum_idp = data[pos + 1];
248 return pos + 1;
249 }
250
251 for (k = 0; k < gpioc->gpio_data_size; k++) {
252 if (data[k] == enum_id) {
253 *enum_idp = data[k + 1];
254 return k + 1;
255 }
256 }
257
258 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
259 return -1;
260}
261
262static void write_config_reg(struct pinmux_info *gpioc,
263 struct pinmux_cfg_reg *crp,
264 int index)
265{
266 unsigned long ncomb, pos, value;
267
268 ncomb = 1 << crp->field_width;
269 pos = index / ncomb;
270 value = index % ncomb;
271
272 gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
273}
274
275static int check_config_reg(struct pinmux_info *gpioc,
276 struct pinmux_cfg_reg *crp,
277 int index)
278{
279 unsigned long ncomb, pos, value;
280
281 ncomb = 1 << crp->field_width;
282 pos = index / ncomb;
283 value = index % ncomb;
284
285 if (gpio_read_reg(crp->reg, crp->reg_width,
286 crp->field_width, pos) == value)
287 return 0;
288
289 return -1;
290}
291
292enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
293
294static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
295 int pinmux_type, int cfg_mode)
296{
297 struct pinmux_cfg_reg *cr = NULL;
298 pinmux_enum_t enum_id;
299 struct pinmux_range *range;
300 int in_range, pos, index;
301 unsigned long *cntp;
302
303 switch (pinmux_type) {
304
305 case PINMUX_TYPE_FUNCTION:
306 range = NULL;
307 break;
308
309 case PINMUX_TYPE_OUTPUT:
310 range = &gpioc->output;
311 break;
312
313 case PINMUX_TYPE_INPUT:
314 range = &gpioc->input;
315 break;
316
317 case PINMUX_TYPE_INPUT_PULLUP:
318 range = &gpioc->input_pu;
319 break;
320
321 case PINMUX_TYPE_INPUT_PULLDOWN:
322 range = &gpioc->input_pd;
323 break;
324
325 default:
326 goto out_err;
327 }
328
329 pos = 0;
330 enum_id = 0;
331 index = 0;
332 while (1) {
333 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
334 if (pos <= 0)
335 goto out_err;
336
337 if (!enum_id)
338 break;
339
340 in_range = enum_in_range(enum_id, &gpioc->function);
341 if (!in_range && range) {
342 in_range = enum_in_range(enum_id, range);
343
344 if (in_range && enum_id == range->force)
345 continue;
346 }
347
348 if (!in_range)
349 continue;
350
351 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
352 goto out_err;
353
354 switch (cfg_mode) {
355 case GPIO_CFG_DRYRUN:
356 if (!*cntp || !check_config_reg(gpioc, cr, index))
357 continue;
358 break;
359
360 case GPIO_CFG_REQ:
361 write_config_reg(gpioc, cr, index);
362 *cntp = *cntp + 1;
363 break;
364
365 case GPIO_CFG_FREE:
366 *cntp = *cntp - 1;
367 break;
368 }
369 }
370
371 return 0;
372 out_err:
373 return -1;
374}
375
376static DEFINE_SPINLOCK(gpio_lock);
377
378static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
379{
380 return container_of(chip, struct pinmux_info, chip);
381}
382
383static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
384{
385 struct pinmux_info *gpioc = chip_to_pinmux(chip);
386 struct pinmux_data_reg *dummy;
387 unsigned long flags;
388 int i, ret, pinmux_type;
389
390 ret = -EINVAL;
391
392 if (!gpioc)
393 goto err_out;
394
395 spin_lock_irqsave(&gpio_lock, flags);
396
397 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
398 goto err_unlock;
399
400 /* setup pin function here if no data is associated with pin */
401
402 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
403 pinmux_type = PINMUX_TYPE_FUNCTION;
404 else
405 pinmux_type = PINMUX_TYPE_GPIO;
406
407 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
408 if (pinmux_config_gpio(gpioc, offset,
409 pinmux_type,
410 GPIO_CFG_DRYRUN) != 0)
411 goto err_unlock;
412
413 if (pinmux_config_gpio(gpioc, offset,
414 pinmux_type,
415 GPIO_CFG_REQ) != 0)
416 BUG();
417 }
418
419 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
420 gpioc->gpios[offset].flags |= pinmux_type;
421
422 ret = 0;
423 err_unlock:
424 spin_unlock_irqrestore(&gpio_lock, flags);
425 err_out:
426 return ret;
427}
428
429static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
430{
431 struct pinmux_info *gpioc = chip_to_pinmux(chip);
432 unsigned long flags;
433 int pinmux_type;
434
435 if (!gpioc)
436 return;
437
438 spin_lock_irqsave(&gpio_lock, flags);
439
440 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
441 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
442 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
443 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
444
445 spin_unlock_irqrestore(&gpio_lock, flags);
446}
447
448static int pinmux_direction(struct pinmux_info *gpioc,
449 unsigned gpio, int new_pinmux_type)
450{
451 int pinmux_type;
452 int ret = -EINVAL;
453
454 if (!gpioc)
455 goto err_out;
456
457 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
458
459 switch (pinmux_type) {
460 case PINMUX_TYPE_GPIO:
461 break;
462 case PINMUX_TYPE_OUTPUT:
463 case PINMUX_TYPE_INPUT:
464 case PINMUX_TYPE_INPUT_PULLUP:
465 case PINMUX_TYPE_INPUT_PULLDOWN:
466 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
467 break;
468 default:
469 goto err_out;
470 }
471
472 if (pinmux_config_gpio(gpioc, gpio,
473 new_pinmux_type,
474 GPIO_CFG_DRYRUN) != 0)
475 goto err_out;
476
477 if (pinmux_config_gpio(gpioc, gpio,
478 new_pinmux_type,
479 GPIO_CFG_REQ) != 0)
480 BUG();
481
482 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
483 gpioc->gpios[gpio].flags |= new_pinmux_type;
484
485 ret = 0;
486 err_out:
487 return ret;
488}
489
490static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
491{
492 struct pinmux_info *gpioc = chip_to_pinmux(chip);
493 unsigned long flags;
494 int ret;
495
496 spin_lock_irqsave(&gpio_lock, flags);
497 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
498 spin_unlock_irqrestore(&gpio_lock, flags);
499
500 return ret;
501}
502
503static void sh_gpio_set_value(struct pinmux_info *gpioc,
504 unsigned gpio, int value)
505{
506 struct pinmux_data_reg *dr = NULL;
507 int bit = 0;
508
509 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
510 BUG();
511 else
512 gpio_write_bit(dr, bit, value);
513}
514
515static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
516 int value)
517{
518 struct pinmux_info *gpioc = chip_to_pinmux(chip);
519 unsigned long flags;
520 int ret;
521
522 sh_gpio_set_value(gpioc, offset, value);
523 spin_lock_irqsave(&gpio_lock, flags);
524 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
525 spin_unlock_irqrestore(&gpio_lock, flags);
526
527 return ret;
528}
529
530static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
531{
532 struct pinmux_data_reg *dr = NULL;
533 int bit = 0;
534
535 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) {
536 BUG();
537 return 0;
538 }
539
540 return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
541}
542
543static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
544{
545 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
546}
547
548static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
549{
550 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
551}
552
553int register_pinmux(struct pinmux_info *pip)
554{
555 struct gpio_chip *chip = &pip->chip;
556
557 pr_info("sh pinmux: %s handling gpio %d -> %d\n",
558 pip->name, pip->first_gpio, pip->last_gpio);
559
560 setup_data_regs(pip);
561
562 chip->request = sh_gpio_request;
563 chip->free = sh_gpio_free;
564 chip->direction_input = sh_gpio_direction_input;
565 chip->get = sh_gpio_get;
566 chip->direction_output = sh_gpio_direction_output;
567 chip->set = sh_gpio_set;
568
569 WARN_ON(pip->first_gpio != 0); /* needs testing */
570
571 chip->label = pip->name;
572 chip->owner = THIS_MODULE;
573 chip->base = pip->first_gpio;
574 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
575
576 return gpiochip_add(chip);
577}
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