diff options
Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_fw.h')
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_fw.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_fw.h b/drivers/scsi/qla4xxx/ql4_fw.h index 037d38016c0..3f36950ec86 100644 --- a/drivers/scsi/qla4xxx/ql4_fw.h +++ b/drivers/scsi/qla4xxx/ql4_fw.h | |||
@@ -65,6 +65,40 @@ struct device_reg_82xx { | |||
65 | #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ | 65 | #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ |
66 | }; | 66 | }; |
67 | 67 | ||
68 | /* ISP 83xx I/O Register Set structure */ | ||
69 | struct device_reg_83xx { | ||
70 | __le32 mailbox_in[16]; /* 0x0000 */ | ||
71 | __le32 reserve1[496]; /* 0x0040 */ | ||
72 | __le32 mailbox_out[16]; /* 0x0800 */ | ||
73 | __le32 reserve2[496]; | ||
74 | __le32 mbox_int; /* 0x1000 */ | ||
75 | __le32 reserve3[63]; | ||
76 | __le32 req_q_out; /* 0x1100 */ | ||
77 | __le32 reserve4[63]; | ||
78 | |||
79 | __le32 rsp_q_in; /* 0x1200 */ | ||
80 | __le32 reserve5[1919]; | ||
81 | |||
82 | __le32 req_q_in; /* 0x3000 */ | ||
83 | __le32 reserve6[3]; | ||
84 | __le32 iocb_int_mask; /* 0x3010 */ | ||
85 | __le32 reserve7[3]; | ||
86 | __le32 rsp_q_out; /* 0x3020 */ | ||
87 | __le32 reserve8[3]; | ||
88 | __le32 anonymousbuff; /* 0x3030 */ | ||
89 | __le32 mb_int_mask; /* 0x3034 */ | ||
90 | |||
91 | __le32 host_intr; /* 0x3038 - Host Interrupt Register */ | ||
92 | __le32 risc_intr; /* 0x303C - RISC Interrupt Register */ | ||
93 | __le32 reserve9[544]; | ||
94 | __le32 leg_int_ptr; /* 0x38C0 - Legacy Interrupt Pointer Register */ | ||
95 | __le32 leg_int_trig; /* 0x38C4 - Legacy Interrupt Trigger Control */ | ||
96 | __le32 leg_int_mask; /* 0x38C8 - Legacy Interrupt Mask Register */ | ||
97 | }; | ||
98 | |||
99 | #define INT_ENABLE_FW_MB (1 << 2) | ||
100 | #define INT_MASK_FW_MB (1 << 2) | ||
101 | |||
68 | /* remote register set (access via PCI memory read/write) */ | 102 | /* remote register set (access via PCI memory read/write) */ |
69 | struct isp_reg { | 103 | struct isp_reg { |
70 | #define MBOX_REG_COUNT 8 | 104 | #define MBOX_REG_COUNT 8 |
@@ -1198,6 +1232,9 @@ struct ql_iscsi_stats { | |||
1198 | #define QLA8XXX_DBG_STATE_ARRAY_LEN 16 | 1232 | #define QLA8XXX_DBG_STATE_ARRAY_LEN 16 |
1199 | #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8 | 1233 | #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8 |
1200 | #define QLA8XXX_DBG_RSVD_ARRAY_LEN 8 | 1234 | #define QLA8XXX_DBG_RSVD_ARRAY_LEN 8 |
1235 | #define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN 16 | ||
1236 | #define QLA83XX_SS_OCM_WNDREG_INDEX 3 | ||
1237 | #define QLA83XX_SS_PCI_INDEX 0 | ||
1201 | 1238 | ||
1202 | struct qla4_8xxx_minidump_template_hdr { | 1239 | struct qla4_8xxx_minidump_template_hdr { |
1203 | uint32_t entry_type; | 1240 | uint32_t entry_type; |
@@ -1216,6 +1253,7 @@ struct qla4_8xxx_minidump_template_hdr { | |||
1216 | 1253 | ||
1217 | uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN]; | 1254 | uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN]; |
1218 | uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN]; | 1255 | uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN]; |
1256 | uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN]; | ||
1219 | }; | 1257 | }; |
1220 | 1258 | ||
1221 | #endif /* _QLA4X_FW_H */ | 1259 | #endif /* _QLA4X_FW_H */ |