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-rw-r--r--drivers/pci/pcie/aer/aerdrv_errprint.c46
1 files changed, 21 insertions, 25 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv_errprint.c b/drivers/pci/pcie/aer/aerdrv_errprint.c
index 7fb5a2c71c6..48f70fa7f68 100644
--- a/drivers/pci/pcie/aer/aerdrv_errprint.c
+++ b/drivers/pci/pcie/aer/aerdrv_errprint.c
@@ -27,39 +27,35 @@
27#define AER_AGENT_COMPLETER 2 27#define AER_AGENT_COMPLETER 2
28#define AER_AGENT_TRANSMITTER 3 28#define AER_AGENT_TRANSMITTER 3
29 29
30#define AER_AGENT_REQUESTER_MASK (PCI_ERR_UNC_COMP_TIME| \ 30#define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
31 PCI_ERR_UNC_UNSUP) 31 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
32 32#define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
33#define AER_AGENT_COMPLETER_MASK PCI_ERR_UNC_COMP_ABORT 33 0 : PCI_ERR_UNC_COMP_ABORT)
34 34#define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
35#define AER_AGENT_TRANSMITTER_MASK(t, e) (e & (PCI_ERR_COR_REP_ROLL| \ 35 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
36 ((t == AER_CORRECTABLE) ? PCI_ERR_COR_REP_TIMER : 0)))
37 36
38#define AER_GET_AGENT(t, e) \ 37#define AER_GET_AGENT(t, e) \
39 ((e & AER_AGENT_COMPLETER_MASK) ? AER_AGENT_COMPLETER : \ 38 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
40 (e & AER_AGENT_REQUESTER_MASK) ? AER_AGENT_REQUESTER : \ 39 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
41 (AER_AGENT_TRANSMITTER_MASK(t, e)) ? AER_AGENT_TRANSMITTER : \ 40 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
42 AER_AGENT_RECEIVER) 41 AER_AGENT_RECEIVER)
43 42
44#define AER_PHYSICAL_LAYER_ERROR_MASK PCI_ERR_COR_RCVR
45#define AER_DATA_LINK_LAYER_ERROR_MASK(t, e) \
46 (PCI_ERR_UNC_DLP| \
47 PCI_ERR_COR_BAD_TLP| \
48 PCI_ERR_COR_BAD_DLLP| \
49 PCI_ERR_COR_REP_ROLL| \
50 ((t == AER_CORRECTABLE) ? \
51 PCI_ERR_COR_REP_TIMER : 0))
52
53#define AER_PHYSICAL_LAYER_ERROR 0 43#define AER_PHYSICAL_LAYER_ERROR 0
54#define AER_DATA_LINK_LAYER_ERROR 1 44#define AER_DATA_LINK_LAYER_ERROR 1
55#define AER_TRANSACTION_LAYER_ERROR 2 45#define AER_TRANSACTION_LAYER_ERROR 2
56 46
57#define AER_GET_LAYER_ERROR(t, e) \ 47#define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
58 ((e & AER_PHYSICAL_LAYER_ERROR_MASK) ? \ 48 PCI_ERR_COR_RCVR : 0)
59 AER_PHYSICAL_LAYER_ERROR : \ 49#define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
60 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t, e)) ? \ 50 (PCI_ERR_COR_BAD_TLP| \
61 AER_DATA_LINK_LAYER_ERROR : \ 51 PCI_ERR_COR_BAD_DLLP| \
62 AER_TRANSACTION_LAYER_ERROR) 52 PCI_ERR_COR_REP_ROLL| \
53 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
54
55#define AER_GET_LAYER_ERROR(t, e) \
56 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
57 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
58 AER_TRANSACTION_LAYER_ERROR)
63 59
64#define AER_PR(info, fmt, args...) \ 60#define AER_PR(info, fmt, args...) \
65 printk("%s" fmt, (info->severity == AER_CORRECTABLE) ? \ 61 printk("%s" fmt, (info->severity == AER_CORRECTABLE) ? \