diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800.h')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2800.h | 55 |
1 files changed, 53 insertions, 2 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h index 74c0433dba3..455dc3ffb25 100644 --- a/drivers/net/wireless/rt2x00/rt2800.h +++ b/drivers/net/wireless/rt2x00/rt2800.h | |||
@@ -56,6 +56,7 @@ | |||
56 | #define RF3021 0x0007 | 56 | #define RF3021 0x0007 |
57 | #define RF3022 0x0008 | 57 | #define RF3022 0x0008 |
58 | #define RF3052 0x0009 | 58 | #define RF3052 0x0009 |
59 | #define RF3320 0x000b | ||
59 | 60 | ||
60 | /* | 61 | /* |
61 | * Chipset version. | 62 | * Chipset version. |
@@ -90,10 +91,16 @@ | |||
90 | #define NUM_TX_QUEUES 4 | 91 | #define NUM_TX_QUEUES 4 |
91 | 92 | ||
92 | /* | 93 | /* |
93 | * USB registers. | 94 | * Registers. |
94 | */ | 95 | */ |
95 | 96 | ||
96 | /* | 97 | /* |
98 | * OPT_14: Unknown register used by rt3xxx devices. | ||
99 | */ | ||
100 | #define OPT_14_CSR 0x0114 | ||
101 | #define OPT_14_CSR_BIT0 FIELD32(0x00000001) | ||
102 | |||
103 | /* | ||
97 | * INT_SOURCE_CSR: Interrupt source register. | 104 | * INT_SOURCE_CSR: Interrupt source register. |
98 | * Write one to clear corresponding bit. | 105 | * Write one to clear corresponding bit. |
99 | * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c | 106 | * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c |
@@ -398,6 +405,31 @@ | |||
398 | #define EFUSE_DATA3 0x059c | 405 | #define EFUSE_DATA3 0x059c |
399 | 406 | ||
400 | /* | 407 | /* |
408 | * LDO_CFG0 | ||
409 | */ | ||
410 | #define LDO_CFG0 0x05d4 | ||
411 | #define LDO_CFG0_DELAY3 FIELD32(0x000000ff) | ||
412 | #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) | ||
413 | #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) | ||
414 | #define LDO_CFG0_BGSEL FIELD32(0x03000000) | ||
415 | #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) | ||
416 | #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) | ||
417 | #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) | ||
418 | |||
419 | /* | ||
420 | * GPIO_SWITCH | ||
421 | */ | ||
422 | #define GPIO_SWITCH 0x05dc | ||
423 | #define GPIO_SWITCH_0 FIELD32(0x00000001) | ||
424 | #define GPIO_SWITCH_1 FIELD32(0x00000002) | ||
425 | #define GPIO_SWITCH_2 FIELD32(0x00000004) | ||
426 | #define GPIO_SWITCH_3 FIELD32(0x00000008) | ||
427 | #define GPIO_SWITCH_4 FIELD32(0x00000010) | ||
428 | #define GPIO_SWITCH_5 FIELD32(0x00000020) | ||
429 | #define GPIO_SWITCH_6 FIELD32(0x00000040) | ||
430 | #define GPIO_SWITCH_7 FIELD32(0x00000080) | ||
431 | |||
432 | /* | ||
401 | * MAC Control/Status Registers(CSR). | 433 | * MAC Control/Status Registers(CSR). |
402 | * Some values are set in TU, whereas 1 TU == 1024 us. | 434 | * Some values are set in TU, whereas 1 TU == 1024 us. |
403 | */ | 435 | */ |
@@ -1492,6 +1524,14 @@ struct mac_iveiv_entry { | |||
1492 | #define BBP4_BANDWIDTH FIELD8(0x18) | 1524 | #define BBP4_BANDWIDTH FIELD8(0x18) |
1493 | 1525 | ||
1494 | /* | 1526 | /* |
1527 | * BBP 138: Unknown | ||
1528 | */ | ||
1529 | #define BBP138_RX_ADC1 FIELD8(0x02) | ||
1530 | #define BBP138_RX_ADC2 FIELD8(0x04) | ||
1531 | #define BBP138_TX_DAC1 FIELD8(0x20) | ||
1532 | #define BBP138_TX_DAC2 FIELD8(0x40) | ||
1533 | |||
1534 | /* | ||
1495 | * RFCSR registers | 1535 | * RFCSR registers |
1496 | * The wordsize of the RFCSR is 8 bits. | 1536 | * The wordsize of the RFCSR is 8 bits. |
1497 | */ | 1537 | */ |
@@ -1499,7 +1539,8 @@ struct mac_iveiv_entry { | |||
1499 | /* | 1539 | /* |
1500 | * RFCSR 6: | 1540 | * RFCSR 6: |
1501 | */ | 1541 | */ |
1502 | #define RFCSR6_R FIELD8(0x03) | 1542 | #define RFCSR6_R1 FIELD8(0x03) |
1543 | #define RFCSR6_R2 FIELD8(0x40) | ||
1503 | 1544 | ||
1504 | /* | 1545 | /* |
1505 | * RFCSR 7: | 1546 | * RFCSR 7: |
@@ -1512,6 +1553,14 @@ struct mac_iveiv_entry { | |||
1512 | #define RFCSR12_TX_POWER FIELD8(0x1f) | 1553 | #define RFCSR12_TX_POWER FIELD8(0x1f) |
1513 | 1554 | ||
1514 | /* | 1555 | /* |
1556 | * RFCSR 17: | ||
1557 | */ | ||
1558 | #define RFCSR17_R1 FIELD8(0x07) | ||
1559 | #define RFCSR17_R2 FIELD8(0x08) | ||
1560 | #define RFCSR17_R3 FIELD8(0x20) | ||
1561 | |||
1562 | |||
1563 | /* | ||
1515 | * RFCSR 22: | 1564 | * RFCSR 22: |
1516 | */ | 1565 | */ |
1517 | #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) | 1566 | #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) |
@@ -1603,6 +1652,8 @@ struct mac_iveiv_entry { | |||
1603 | #define EEPROM_NIC_WPS_PBC FIELD16(0x0080) | 1652 | #define EEPROM_NIC_WPS_PBC FIELD16(0x0080) |
1604 | #define EEPROM_NIC_BW40M_BG FIELD16(0x0100) | 1653 | #define EEPROM_NIC_BW40M_BG FIELD16(0x0100) |
1605 | #define EEPROM_NIC_BW40M_A FIELD16(0x0200) | 1654 | #define EEPROM_NIC_BW40M_A FIELD16(0x0200) |
1655 | #define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800) | ||
1656 | #define EEPROM_NIC_DAC_TEST FIELD16(0x8000) | ||
1606 | 1657 | ||
1607 | /* | 1658 | /* |
1608 | * EEPROM frequency | 1659 | * EEPROM frequency |