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path: root/drivers/net/wireless/rt2x00/rt2400pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c56
1 files changed, 30 insertions, 26 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 5f5204b8289..4ba7b038928 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -526,6 +526,10 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
526 526
527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); 527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
528 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 528 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
529 } else {
530 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
531 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
532 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
529 } 533 }
530 534
531 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 535 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
@@ -1003,19 +1007,19 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1003{ 1007{
1004 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1008 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1005 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1009 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1006 __le32 *txd = skbdesc->desc; 1010 __le32 *txd = entry_priv->desc;
1007 u32 word; 1011 u32 word;
1008 1012
1009 /* 1013 /*
1010 * Start writing the descriptor words. 1014 * Start writing the descriptor words.
1011 */ 1015 */
1012 rt2x00_desc_read(entry_priv->desc, 1, &word); 1016 rt2x00_desc_read(txd, 1, &word);
1013 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1017 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1014 rt2x00_desc_write(entry_priv->desc, 1, word); 1018 rt2x00_desc_write(txd, 1, word);
1015 1019
1016 rt2x00_desc_read(txd, 2, &word); 1020 rt2x00_desc_read(txd, 2, &word);
1017 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len); 1021 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1018 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len); 1022 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1019 rt2x00_desc_write(txd, 2, word); 1023 rt2x00_desc_write(txd, 2, word);
1020 1024
1021 rt2x00_desc_read(txd, 3, &word); 1025 rt2x00_desc_read(txd, 3, &word);
@@ -1036,6 +1040,11 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1036 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); 1040 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1037 rt2x00_desc_write(txd, 4, word); 1041 rt2x00_desc_write(txd, 4, word);
1038 1042
1043 /*
1044 * Writing TXD word 0 must the last to prevent a race condition with
1045 * the device, whereby the device may take hold of the TXD before we
1046 * finished updating it.
1047 */
1039 rt2x00_desc_read(txd, 0, &word); 1048 rt2x00_desc_read(txd, 0, &word);
1040 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1049 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1041 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1050 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
@@ -1051,12 +1060,19 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1051 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1060 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1052 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1061 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1053 rt2x00_desc_write(txd, 0, word); 1062 rt2x00_desc_write(txd, 0, word);
1063
1064 /*
1065 * Register descriptor details in skb frame descriptor.
1066 */
1067 skbdesc->desc = txd;
1068 skbdesc->desc_len = TXD_DESC_SIZE;
1054} 1069}
1055 1070
1056/* 1071/*
1057 * TX data initialization 1072 * TX data initialization
1058 */ 1073 */
1059static void rt2400pci_write_beacon(struct queue_entry *entry) 1074static void rt2400pci_write_beacon(struct queue_entry *entry,
1075 struct txentry_desc *txdesc)
1060{ 1076{
1061 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1077 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1062 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1078 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
@@ -1072,20 +1088,19 @@ static void rt2400pci_write_beacon(struct queue_entry *entry)
1072 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 1088 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1073 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1089 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1074 1090
1075 /*
1076 * Replace rt2x00lib allocated descriptor with the
1077 * pointer to the _real_ hardware descriptor.
1078 * After that, map the beacon to DMA and update the
1079 * descriptor.
1080 */
1081 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1082 skbdesc->desc = entry_priv->desc;
1083
1084 rt2x00queue_map_txskb(rt2x00dev, entry->skb); 1091 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1085 1092
1086 rt2x00_desc_read(entry_priv->desc, 1, &word); 1093 rt2x00_desc_read(entry_priv->desc, 1, &word);
1087 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1094 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1088 rt2x00_desc_write(entry_priv->desc, 1, word); 1095 rt2x00_desc_write(entry_priv->desc, 1, word);
1096
1097 /*
1098 * Enable beaconing again.
1099 */
1100 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1101 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1102 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1103 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1089} 1104}
1090 1105
1091static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1106static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
@@ -1093,17 +1108,6 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1093{ 1108{
1094 u32 reg; 1109 u32 reg;
1095 1110
1096 if (queue == QID_BEACON) {
1097 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1098 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1099 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1100 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1101 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1102 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1103 }
1104 return;
1105 }
1106
1107 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1111 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1108 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE)); 1112 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1109 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK)); 1113 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));