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path: root/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-agn-ucode.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-ucode.c580
1 files changed, 580 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
new file mode 100644
index 00000000000..a5c5a0accd5
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
@@ -0,0 +1,580 @@
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-io.h"
38#include "iwl-helpers.h"
39#include "iwl-agn-hw.h"
40#include "iwl-agn.h"
41#include "iwl-agn-calib.h"
42#include "iwl-trans.h"
43
44static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
45 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
46 0, COEX_UNASSOC_IDLE_FLAGS},
47 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
48 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
49 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
50 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
51 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
52 0, COEX_CALIBRATION_FLAGS},
53 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
54 0, COEX_PERIODIC_CALIBRATION_FLAGS},
55 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
56 0, COEX_CONNECTION_ESTAB_FLAGS},
57 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
58 0, COEX_ASSOCIATED_IDLE_FLAGS},
59 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
60 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
61 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
62 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
63 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
64 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
65 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
66 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
67 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
68 0, COEX_STAND_ALONE_DEBUG_FLAGS},
69 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
70 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
71 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
72 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
73};
74
75/*
76 * ucode
77 */
78static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
79 struct fw_desc *image, u32 dst_addr)
80{
81 dma_addr_t phy_addr = image->p_addr;
82 u32 byte_cnt = image->len;
83 int ret;
84
85 priv->ucode_write_complete = 0;
86
87 iwl_write_direct32(priv,
88 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
89 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
90
91 iwl_write_direct32(priv,
92 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
93
94 iwl_write_direct32(priv,
95 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
96 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
97
98 iwl_write_direct32(priv,
99 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
100 (iwl_get_dma_hi_addr(phy_addr)
101 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
102
103 iwl_write_direct32(priv,
104 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
105 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
106 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
107 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
108
109 iwl_write_direct32(priv,
110 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
111 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
112 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
113 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
114
115 IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
116 ret = wait_event_timeout(priv->wait_command_queue,
117 priv->ucode_write_complete, 5 * HZ);
118 if (!ret) {
119 IWL_ERR(priv, "Could not load the %s uCode section\n",
120 name);
121 return -ETIMEDOUT;
122 }
123
124 return 0;
125}
126
127static int iwlagn_load_given_ucode(struct iwl_priv *priv,
128 struct fw_img *image)
129{
130 int ret = 0;
131
132 ret = iwlagn_load_section(priv, "INST", &image->code,
133 IWLAGN_RTC_INST_LOWER_BOUND);
134 if (ret)
135 return ret;
136
137 return iwlagn_load_section(priv, "DATA", &image->data,
138 IWLAGN_RTC_DATA_LOWER_BOUND);
139}
140
141/*
142 * Calibration
143 */
144static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
145{
146 struct iwl_calib_xtal_freq_cmd cmd;
147 __le16 *xtal_calib =
148 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
149
150 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
151 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
152 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
153 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
154 (u8 *)&cmd, sizeof(cmd));
155}
156
157static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
158{
159 struct iwl_calib_temperature_offset_cmd cmd;
160 __le16 *offset_calib =
161 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
162
163 memset(&cmd, 0, sizeof(cmd));
164 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
165 memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib));
166 if (!(cmd.radio_sensor_offset))
167 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
168
169 IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
170 le16_to_cpu(cmd.radio_sensor_offset));
171 return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
172 (u8 *)&cmd, sizeof(cmd));
173}
174
175static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
176{
177 struct iwl_calib_cfg_cmd calib_cfg_cmd;
178 struct iwl_host_cmd cmd = {
179 .id = CALIBRATION_CFG_CMD,
180 .len = { sizeof(struct iwl_calib_cfg_cmd), },
181 .data = { &calib_cfg_cmd, },
182 };
183
184 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
185 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
186 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
187 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
188 calib_cfg_cmd.ucd_calib_cfg.flags =
189 IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
190
191 return trans_send_cmd(&priv->trans, &cmd);
192}
193
194void iwlagn_rx_calib_result(struct iwl_priv *priv,
195 struct iwl_rx_mem_buffer *rxb)
196{
197 struct iwl_rx_packet *pkt = rxb_addr(rxb);
198 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
199 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
200 int index;
201
202 /* reduce the size of the length field itself */
203 len -= 4;
204
205 /* Define the order in which the results will be sent to the runtime
206 * uCode. iwl_send_calib_results sends them in a row according to
207 * their index. We sort them here
208 */
209 switch (hdr->op_code) {
210 case IWL_PHY_CALIBRATE_DC_CMD:
211 index = IWL_CALIB_DC;
212 break;
213 case IWL_PHY_CALIBRATE_LO_CMD:
214 index = IWL_CALIB_LO;
215 break;
216 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
217 index = IWL_CALIB_TX_IQ;
218 break;
219 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
220 index = IWL_CALIB_TX_IQ_PERD;
221 break;
222 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
223 index = IWL_CALIB_BASE_BAND;
224 break;
225 default:
226 IWL_ERR(priv, "Unknown calibration notification %d\n",
227 hdr->op_code);
228 return;
229 }
230 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
231}
232
233int iwlagn_init_alive_start(struct iwl_priv *priv)
234{
235 int ret;
236
237 if (priv->cfg->bt_params &&
238 priv->cfg->bt_params->advanced_bt_coexist) {
239 /*
240 * Tell uCode we are ready to perform calibration
241 * need to perform this before any calibration
242 * no need to close the envlope since we are going
243 * to load the runtime uCode later.
244 */
245 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
246 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
247 if (ret)
248 return ret;
249
250 }
251
252 ret = iwlagn_send_calib_cfg(priv);
253 if (ret)
254 return ret;
255
256 /**
257 * temperature offset calibration is only needed for runtime ucode,
258 * so prepare the value now.
259 */
260 if (priv->cfg->need_temp_offset_calib)
261 return iwlagn_set_temperature_offset_calib(priv);
262
263 return 0;
264}
265
266static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
267{
268 struct iwl_wimax_coex_cmd coex_cmd;
269
270 if (priv->cfg->base_params->support_wimax_coexist) {
271 /* UnMask wake up src at associated sleep */
272 coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
273
274 /* UnMask wake up src at unassociated sleep */
275 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
276 memcpy(coex_cmd.sta_prio, cu_priorities,
277 sizeof(struct iwl_wimax_coex_event_entry) *
278 COEX_NUM_OF_EVENTS);
279
280 /* enabling the coexistence feature */
281 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
282
283 /* enabling the priorities tables */
284 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
285 } else {
286 /* coexistence is disabled */
287 memset(&coex_cmd, 0, sizeof(coex_cmd));
288 }
289 return trans_send_cmd_pdu(&priv->trans,
290 COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
291 sizeof(coex_cmd), &coex_cmd);
292}
293
294static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
295 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
296 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
297 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
298 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
299 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
300 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
301 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
302 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
303 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
304 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
305 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
306 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
307 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
308 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
309 ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
310 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
311 ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
312 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
313 0, 0, 0, 0, 0, 0, 0
314};
315
316void iwlagn_send_prio_tbl(struct iwl_priv *priv)
317{
318 struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
319
320 memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
321 sizeof(iwlagn_bt_prio_tbl));
322 if (trans_send_cmd_pdu(&priv->trans,
323 REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
324 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
325 IWL_ERR(priv, "failed to send BT prio tbl command\n");
326}
327
328int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
329{
330 struct iwl_bt_coex_prot_env_cmd env_cmd;
331 int ret;
332
333 env_cmd.action = action;
334 env_cmd.type = type;
335 ret = trans_send_cmd_pdu(&priv->trans,
336 REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
337 sizeof(env_cmd), &env_cmd);
338 if (ret)
339 IWL_ERR(priv, "failed to send BT env command\n");
340 return ret;
341}
342
343
344static int iwlagn_alive_notify(struct iwl_priv *priv)
345{
346 int ret;
347
348 trans_tx_start(&priv->trans);
349
350 ret = iwlagn_send_wimax_coex(priv);
351 if (ret)
352 return ret;
353
354 ret = iwlagn_set_Xtal_calib(priv);
355 if (ret)
356 return ret;
357
358 return iwl_send_calib_results(priv);
359}
360
361
362/**
363 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
364 * using sample data 100 bytes apart. If these sample points are good,
365 * it's a pretty good bet that everything between them is good, too.
366 */
367static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
368 struct fw_desc *fw_desc)
369{
370 __le32 *image = (__le32 *)fw_desc->v_addr;
371 u32 len = fw_desc->len;
372 u32 val;
373 u32 i;
374
375 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
376
377 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
378 /* read data comes through single port, auto-incr addr */
379 /* NOTE: Use the debugless read so we don't flood kernel log
380 * if IWL_DL_IO is set */
381 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
382 i + IWLAGN_RTC_INST_LOWER_BOUND);
383 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
384 if (val != le32_to_cpu(*image))
385 return -EIO;
386 }
387
388 return 0;
389}
390
391static void iwl_print_mismatch_inst(struct iwl_priv *priv,
392 struct fw_desc *fw_desc)
393{
394 __le32 *image = (__le32 *)fw_desc->v_addr;
395 u32 len = fw_desc->len;
396 u32 val;
397 u32 offs;
398 int errors = 0;
399
400 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
401
402 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
403 IWLAGN_RTC_INST_LOWER_BOUND);
404
405 for (offs = 0;
406 offs < len && errors < 20;
407 offs += sizeof(u32), image++) {
408 /* read data comes through single port, auto-incr addr */
409 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
410 if (val != le32_to_cpu(*image)) {
411 IWL_ERR(priv, "uCode INST section at "
412 "offset 0x%x, is 0x%x, s/b 0x%x\n",
413 offs, val, le32_to_cpu(*image));
414 errors++;
415 }
416 }
417}
418
419/**
420 * iwl_verify_ucode - determine which instruction image is in SRAM,
421 * and verify its contents
422 */
423static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
424{
425 if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
426 IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
427 return 0;
428 }
429
430 IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
431
432 iwl_print_mismatch_inst(priv, &img->code);
433 return -EIO;
434}
435
436struct iwlagn_alive_data {
437 bool valid;
438 u8 subtype;
439};
440
441static void iwlagn_alive_fn(struct iwl_priv *priv,
442 struct iwl_rx_packet *pkt,
443 void *data)
444{
445 struct iwlagn_alive_data *alive_data = data;
446 struct iwl_alive_resp *palive;
447
448 palive = &pkt->u.alive_frame;
449
450 IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
451 "0x%01X 0x%01X\n",
452 palive->is_valid, palive->ver_type,
453 palive->ver_subtype);
454
455 priv->device_pointers.error_event_table =
456 le32_to_cpu(palive->error_event_table_ptr);
457 priv->device_pointers.log_event_table =
458 le32_to_cpu(palive->log_event_table_ptr);
459
460 alive_data->subtype = palive->ver_subtype;
461 alive_data->valid = palive->is_valid == UCODE_VALID_OK;
462}
463
464#define UCODE_ALIVE_TIMEOUT HZ
465#define UCODE_CALIB_TIMEOUT (2*HZ)
466
467int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
468 struct fw_img *image,
469 enum iwlagn_ucode_type ucode_type)
470{
471 struct iwl_notification_wait alive_wait;
472 struct iwlagn_alive_data alive_data;
473 int ret;
474 enum iwlagn_ucode_type old_type;
475
476 ret = trans_start_device(&priv->trans);
477 if (ret)
478 return ret;
479
480 iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
481 iwlagn_alive_fn, &alive_data);
482
483 old_type = priv->ucode_type;
484 priv->ucode_type = ucode_type;
485
486 ret = iwlagn_load_given_ucode(priv, image);
487 if (ret) {
488 priv->ucode_type = old_type;
489 iwlagn_remove_notification(priv, &alive_wait);
490 return ret;
491 }
492
493 trans_kick_nic(&priv->trans);
494
495 /*
496 * Some things may run in the background now, but we
497 * just wait for the ALIVE notification here.
498 */
499 ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
500 if (ret) {
501 priv->ucode_type = old_type;
502 return ret;
503 }
504
505 if (!alive_data.valid) {
506 IWL_ERR(priv, "Loaded ucode is not valid!\n");
507 priv->ucode_type = old_type;
508 return -EIO;
509 }
510
511 /*
512 * This step takes a long time (60-80ms!!) and
513 * WoWLAN image should be loaded quickly, so
514 * skip it for WoWLAN.
515 */
516 if (ucode_type != IWL_UCODE_WOWLAN) {
517 ret = iwl_verify_ucode(priv, image);
518 if (ret) {
519 priv->ucode_type = old_type;
520 return ret;
521 }
522
523 /* delay a bit to give rfkill time to run */
524 msleep(5);
525 }
526
527 ret = iwlagn_alive_notify(priv);
528 if (ret) {
529 IWL_WARN(priv,
530 "Could not complete ALIVE transition: %d\n", ret);
531 priv->ucode_type = old_type;
532 return ret;
533 }
534
535 return 0;
536}
537
538int iwlagn_run_init_ucode(struct iwl_priv *priv)
539{
540 struct iwl_notification_wait calib_wait;
541 int ret;
542
543 lockdep_assert_held(&priv->mutex);
544
545 /* No init ucode required? Curious, but maybe ok */
546 if (!priv->ucode_init.code.len)
547 return 0;
548
549 if (priv->ucode_type != IWL_UCODE_NONE)
550 return 0;
551
552 iwlagn_init_notification_wait(priv, &calib_wait,
553 CALIBRATION_COMPLETE_NOTIFICATION,
554 NULL, NULL);
555
556 /* Will also start the device */
557 ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
558 IWL_UCODE_INIT);
559 if (ret)
560 goto error;
561
562 ret = iwlagn_init_alive_start(priv);
563 if (ret)
564 goto error;
565
566 /*
567 * Some things may run in the background now, but we
568 * just wait for the calibration complete notification.
569 */
570 ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
571
572 goto out;
573
574 error:
575 iwlagn_remove_notification(priv, &calib_wait);
576 out:
577 /* Whatever happened, stop the device */
578 trans_stop_device(&priv->trans);
579 return ret;
580}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-28 11:28:44 -0400