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-rw-r--r--drivers/net/wireless/iwlegacy/4965-mac.c3245
1 files changed, 3245 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlegacy/4965-mac.c b/drivers/net/wireless/iwlegacy/4965-mac.c
new file mode 100644
index 00000000000..df86431d3ba
--- /dev/null
+++ b/drivers/net/wireless/iwlegacy/4965-mac.c
@@ -0,0 +1,3245 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/mac80211.h>
48
49#include <asm/div64.h>
50
51#define DRV_NAME "iwl4965"
52
53#include "iwl-eeprom.h"
54#include "iwl-dev.h"
55#include "iwl-core.h"
56#include "iwl-io.h"
57#include "iwl-helpers.h"
58#include "iwl-sta.h"
59#include "iwl-4965-calib.h"
60#include "iwl-4965.h"
61#include "iwl-4965-led.h"
62
63
64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
70/*
71 * module name, copyright, version, etc.
72 */
73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
74
75#ifdef CONFIG_IWLEGACY_DEBUG
76#define VD "d"
77#else
78#define VD
79#endif
80
81#define DRV_VERSION IWLWIFI_VERSION VD
82
83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87MODULE_LICENSE("GPL");
88MODULE_ALIAS("iwl4965");
89
90void il4965_update_chain_flags(struct il_priv *il)
91{
92 if (il->cfg->ops->hcmd->set_rxon_chain) {
93 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
94 if (il->ctx.active.rx_chain != il->ctx.staging.rx_chain)
95 il_commit_rxon(il, &il->ctx);
96 }
97}
98
99static void il4965_clear_free_frames(struct il_priv *il)
100{
101 struct list_head *element;
102
103 D_INFO("%d frames on pre-allocated heap on clear.\n",
104 il->frames_count);
105
106 while (!list_empty(&il->free_frames)) {
107 element = il->free_frames.next;
108 list_del(element);
109 kfree(list_entry(element, struct il_frame, list));
110 il->frames_count--;
111 }
112
113 if (il->frames_count) {
114 IL_WARN("%d frames still in use. Did we lose one?\n",
115 il->frames_count);
116 il->frames_count = 0;
117 }
118}
119
120static struct il_frame *il4965_get_free_frame(struct il_priv *il)
121{
122 struct il_frame *frame;
123 struct list_head *element;
124 if (list_empty(&il->free_frames)) {
125 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
126 if (!frame) {
127 IL_ERR("Could not allocate frame!\n");
128 return NULL;
129 }
130
131 il->frames_count++;
132 return frame;
133 }
134
135 element = il->free_frames.next;
136 list_del(element);
137 return list_entry(element, struct il_frame, list);
138}
139
140static void il4965_free_frame(struct il_priv *il, struct il_frame *frame)
141{
142 memset(frame, 0, sizeof(*frame));
143 list_add(&frame->list, &il->free_frames);
144}
145
146static u32 il4965_fill_beacon_frame(struct il_priv *il,
147 struct ieee80211_hdr *hdr,
148 int left)
149{
150 lockdep_assert_held(&il->mutex);
151
152 if (!il->beacon_skb)
153 return 0;
154
155 if (il->beacon_skb->len > left)
156 return 0;
157
158 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
159
160 return il->beacon_skb->len;
161}
162
163/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
164static void il4965_set_beacon_tim(struct il_priv *il,
165 struct il_tx_beacon_cmd *tx_beacon_cmd,
166 u8 *beacon, u32 frame_size)
167{
168 u16 tim_idx;
169 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
170
171 /*
172 * The idx is relative to frame start but we start looking at the
173 * variable-length part of the beacon.
174 */
175 tim_idx = mgmt->u.beacon.variable - beacon;
176
177 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
178 while ((tim_idx < (frame_size - 2)) &&
179 (beacon[tim_idx] != WLAN_EID_TIM))
180 tim_idx += beacon[tim_idx+1] + 2;
181
182 /* If TIM field was found, set variables */
183 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
184 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
185 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
186 } else
187 IL_WARN("Unable to find TIM Element in beacon\n");
188}
189
190static unsigned int il4965_hw_get_beacon_cmd(struct il_priv *il,
191 struct il_frame *frame)
192{
193 struct il_tx_beacon_cmd *tx_beacon_cmd;
194 u32 frame_size;
195 u32 rate_flags;
196 u32 rate;
197 /*
198 * We have to set up the TX command, the TX Beacon command, and the
199 * beacon contents.
200 */
201
202 lockdep_assert_held(&il->mutex);
203
204 if (!il->beacon_ctx) {
205 IL_ERR("trying to build beacon w/o beacon context!\n");
206 return 0;
207 }
208
209 /* Initialize memory */
210 tx_beacon_cmd = &frame->u.beacon;
211 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
212
213 /* Set up TX beacon contents */
214 frame_size = il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
215 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
216 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
217 return 0;
218 if (!frame_size)
219 return 0;
220
221 /* Set up TX command fields */
222 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
223 tx_beacon_cmd->tx.sta_id = il->beacon_ctx->bcast_sta_id;
224 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
225 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
226 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
227
228 /* Set up TX beacon command fields */
229 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
230 frame_size);
231
232 /* Set up packet rate and flags */
233 rate = il_get_lowest_plcp(il, il->beacon_ctx);
234 il->mgmt_tx_ant = il4965_toggle_tx_ant(il, il->mgmt_tx_ant,
235 il->hw_params.valid_tx_ant);
236 rate_flags = il4965_ant_idx_to_flags(il->mgmt_tx_ant);
237 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
238 rate_flags |= RATE_MCS_CCK_MSK;
239 tx_beacon_cmd->tx.rate_n_flags = il4965_hw_set_rate_n_flags(rate,
240 rate_flags);
241
242 return sizeof(*tx_beacon_cmd) + frame_size;
243}
244
245int il4965_send_beacon_cmd(struct il_priv *il)
246{
247 struct il_frame *frame;
248 unsigned int frame_size;
249 int rc;
250
251 frame = il4965_get_free_frame(il);
252 if (!frame) {
253 IL_ERR("Could not obtain free frame buffer for beacon "
254 "command.\n");
255 return -ENOMEM;
256 }
257
258 frame_size = il4965_hw_get_beacon_cmd(il, frame);
259 if (!frame_size) {
260 IL_ERR("Error configuring the beacon command\n");
261 il4965_free_frame(il, frame);
262 return -EINVAL;
263 }
264
265 rc = il_send_cmd_pdu(il, REPLY_TX_BEACON, frame_size,
266 &frame->u.cmd[0]);
267
268 il4965_free_frame(il, frame);
269
270 return rc;
271}
272
273static inline dma_addr_t il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
274{
275 struct il_tfd_tb *tb = &tfd->tbs[idx];
276
277 dma_addr_t addr = get_unaligned_le32(&tb->lo);
278 if (sizeof(dma_addr_t) > sizeof(u32))
279 addr |=
280 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
281
282 return addr;
283}
284
285static inline u16 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
286{
287 struct il_tfd_tb *tb = &tfd->tbs[idx];
288
289 return le16_to_cpu(tb->hi_n_len) >> 4;
290}
291
292static inline void il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx,
293 dma_addr_t addr, u16 len)
294{
295 struct il_tfd_tb *tb = &tfd->tbs[idx];
296 u16 hi_n_len = len << 4;
297
298 put_unaligned_le32(addr, &tb->lo);
299 if (sizeof(dma_addr_t) > sizeof(u32))
300 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
301
302 tb->hi_n_len = cpu_to_le16(hi_n_len);
303
304 tfd->num_tbs = idx + 1;
305}
306
307static inline u8 il4965_tfd_get_num_tbs(struct il_tfd *tfd)
308{
309 return tfd->num_tbs & 0x1f;
310}
311
312/**
313 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
314 * @il - driver ilate data
315 * @txq - tx queue
316 *
317 * Does NOT advance any TFD circular buffer read/write idxes
318 * Does NOT free the TFD itself (which is within circular buffer)
319 */
320void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
321{
322 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
323 struct il_tfd *tfd;
324 struct pci_dev *dev = il->pci_dev;
325 int idx = txq->q.read_ptr;
326 int i;
327 int num_tbs;
328
329 tfd = &tfd_tmp[idx];
330
331 /* Sanity check on number of chunks */
332 num_tbs = il4965_tfd_get_num_tbs(tfd);
333
334 if (num_tbs >= IL_NUM_OF_TBS) {
335 IL_ERR("Too many chunks: %i\n", num_tbs);
336 /* @todo issue fatal error, it is quite serious situation */
337 return;
338 }
339
340 /* Unmap tx_cmd */
341 if (num_tbs)
342 pci_unmap_single(dev,
343 dma_unmap_addr(&txq->meta[idx], mapping),
344 dma_unmap_len(&txq->meta[idx], len),
345 PCI_DMA_BIDIRECTIONAL);
346
347 /* Unmap chunks, if any. */
348 for (i = 1; i < num_tbs; i++)
349 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
350 il4965_tfd_tb_get_len(tfd, i),
351 PCI_DMA_TODEVICE);
352
353 /* free SKB */
354 if (txq->txb) {
355 struct sk_buff *skb;
356
357 skb = txq->txb[txq->q.read_ptr].skb;
358
359 /* can be called from irqs-disabled context */
360 if (skb) {
361 dev_kfree_skb_any(skb);
362 txq->txb[txq->q.read_ptr].skb = NULL;
363 }
364 }
365}
366
367int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il,
368 struct il_tx_queue *txq,
369 dma_addr_t addr, u16 len,
370 u8 reset, u8 pad)
371{
372 struct il_queue *q;
373 struct il_tfd *tfd, *tfd_tmp;
374 u32 num_tbs;
375
376 q = &txq->q;
377 tfd_tmp = (struct il_tfd *)txq->tfds;
378 tfd = &tfd_tmp[q->write_ptr];
379
380 if (reset)
381 memset(tfd, 0, sizeof(*tfd));
382
383 num_tbs = il4965_tfd_get_num_tbs(tfd);
384
385 /* Each TFD can point to a maximum 20 Tx buffers */
386 if (num_tbs >= IL_NUM_OF_TBS) {
387 IL_ERR("Error can not send more than %d chunks\n",
388 IL_NUM_OF_TBS);
389 return -EINVAL;
390 }
391
392 BUG_ON(addr & ~DMA_BIT_MASK(36));
393 if (unlikely(addr & ~IL_TX_DMA_MASK))
394 IL_ERR("Unaligned address = %llx\n",
395 (unsigned long long)addr);
396
397 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
398
399 return 0;
400}
401
402/*
403 * Tell nic where to find circular buffer of Tx Frame Descriptors for
404 * given Tx queue, and enable the DMA channel used for that queue.
405 *
406 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
407 * channels supported in hardware.
408 */
409int il4965_hw_tx_queue_init(struct il_priv *il,
410 struct il_tx_queue *txq)
411{
412 int txq_id = txq->q.id;
413
414 /* Circular buffer (TFD queue in DRAM) physical base address */
415 il_wr(il, FH_MEM_CBBC_QUEUE(txq_id),
416 txq->q.dma_addr >> 8);
417
418 return 0;
419}
420
421/******************************************************************************
422 *
423 * Generic RX handler implementations
424 *
425 ******************************************************************************/
426static void il4965_rx_reply_alive(struct il_priv *il,
427 struct il_rx_buf *rxb)
428{
429 struct il_rx_pkt *pkt = rxb_addr(rxb);
430 struct il_alive_resp *palive;
431 struct delayed_work *pwork;
432
433 palive = &pkt->u.alive_frame;
434
435 D_INFO("Alive ucode status 0x%08X revision "
436 "0x%01X 0x%01X\n",
437 palive->is_valid, palive->ver_type,
438 palive->ver_subtype);
439
440 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
441 D_INFO("Initialization Alive received.\n");
442 memcpy(&il->card_alive_init,
443 &pkt->u.alive_frame,
444 sizeof(struct il_init_alive_resp));
445 pwork = &il->init_alive_start;
446 } else {
447 D_INFO("Runtime Alive received.\n");
448 memcpy(&il->card_alive, &pkt->u.alive_frame,
449 sizeof(struct il_alive_resp));
450 pwork = &il->alive_start;
451 }
452
453 /* We delay the ALIVE response by 5ms to
454 * give the HW RF Kill time to activate... */
455 if (palive->is_valid == UCODE_VALID_OK)
456 queue_delayed_work(il->workqueue, pwork,
457 msecs_to_jiffies(5));
458 else
459 IL_WARN("uCode did not respond OK.\n");
460}
461
462/**
463 * il4965_bg_stats_periodic - Timer callback to queue stats
464 *
465 * This callback is provided in order to send a stats request.
466 *
467 * This timer function is continually reset to execute within
468 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
469 * was received. We need to ensure we receive the stats in order
470 * to update the temperature used for calibrating the TXPOWER.
471 */
472static void il4965_bg_stats_periodic(unsigned long data)
473{
474 struct il_priv *il = (struct il_priv *)data;
475
476 if (test_bit(STATUS_EXIT_PENDING, &il->status))
477 return;
478
479 /* dont send host command if rf-kill is on */
480 if (!il_is_ready_rf(il))
481 return;
482
483 il_send_stats_request(il, CMD_ASYNC, false);
484}
485
486static void il4965_rx_beacon_notif(struct il_priv *il,
487 struct il_rx_buf *rxb)
488{
489 struct il_rx_pkt *pkt = rxb_addr(rxb);
490 struct il4965_beacon_notif *beacon =
491 (struct il4965_beacon_notif *)pkt->u.raw;
492#ifdef CONFIG_IWLEGACY_DEBUG
493 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
494
495 D_RX("beacon status %x retries %d iss %d "
496 "tsf %d %d rate %d\n",
497 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
498 beacon->beacon_notify_hdr.failure_frame,
499 le32_to_cpu(beacon->ibss_mgr_status),
500 le32_to_cpu(beacon->high_tsf),
501 le32_to_cpu(beacon->low_tsf), rate);
502#endif
503
504 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
505}
506
507static void il4965_perform_ct_kill_task(struct il_priv *il)
508{
509 unsigned long flags;
510
511 D_POWER("Stop all queues\n");
512
513 if (il->mac80211_registered)
514 ieee80211_stop_queues(il->hw);
515
516 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
517 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
518 _il_rd(il, CSR_UCODE_DRV_GP1);
519
520 spin_lock_irqsave(&il->reg_lock, flags);
521 if (!_il_grab_nic_access(il))
522 _il_release_nic_access(il);
523 spin_unlock_irqrestore(&il->reg_lock, flags);
524}
525
526/* Handle notification from uCode that card's power state is changing
527 * due to software, hardware, or critical temperature RFKILL */
528static void il4965_rx_card_state_notif(struct il_priv *il,
529 struct il_rx_buf *rxb)
530{
531 struct il_rx_pkt *pkt = rxb_addr(rxb);
532 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
533 unsigned long status = il->status;
534
535 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
536 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
537 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
538 (flags & CT_CARD_DISABLED) ?
539 "Reached" : "Not reached");
540
541 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
542 CT_CARD_DISABLED)) {
543
544 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
545 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
546
547 il_wr(il, HBUS_TARG_MBX_C,
548 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
549
550 if (!(flags & RXON_CARD_DISABLED)) {
551 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
552 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
553 il_wr(il, HBUS_TARG_MBX_C,
554 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
555 }
556 }
557
558 if (flags & CT_CARD_DISABLED)
559 il4965_perform_ct_kill_task(il);
560
561 if (flags & HW_CARD_DISABLED)
562 set_bit(STATUS_RF_KILL_HW, &il->status);
563 else
564 clear_bit(STATUS_RF_KILL_HW, &il->status);
565
566 if (!(flags & RXON_CARD_DISABLED))
567 il_scan_cancel(il);
568
569 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
570 test_bit(STATUS_RF_KILL_HW, &il->status)))
571 wiphy_rfkill_set_hw_state(il->hw->wiphy,
572 test_bit(STATUS_RF_KILL_HW, &il->status));
573 else
574 wake_up(&il->wait_command_queue);
575}
576
577/**
578 * il4965_setup_rx_handlers - Initialize Rx handler callbacks
579 *
580 * Setup the RX handlers for each of the reply types sent from the uCode
581 * to the host.
582 *
583 * This function chains into the hardware specific files for them to setup
584 * any hardware specific handlers as well.
585 */
586static void il4965_setup_rx_handlers(struct il_priv *il)
587{
588 il->rx_handlers[REPLY_ALIVE] = il4965_rx_reply_alive;
589 il->rx_handlers[REPLY_ERROR] = il_rx_reply_error;
590 il->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = il_rx_csa;
591 il->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
592 il_rx_spectrum_measure_notif;
593 il->rx_handlers[PM_SLEEP_NOTIFICATION] = il_rx_pm_sleep_notif;
594 il->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
595 il_rx_pm_debug_stats_notif;
596 il->rx_handlers[BEACON_NOTIFICATION] = il4965_rx_beacon_notif;
597
598 /*
599 * The same handler is used for both the REPLY to a discrete
600 * stats request from the host as well as for the periodic
601 * stats notifications (after received beacons) from the uCode.
602 */
603 il->rx_handlers[REPLY_STATISTICS_CMD] = il4965_reply_stats;
604 il->rx_handlers[STATISTICS_NOTIFICATION] = il4965_rx_stats;
605
606 il_setup_rx_scan_handlers(il);
607
608 /* status change handler */
609 il->rx_handlers[CARD_STATE_NOTIFICATION] =
610 il4965_rx_card_state_notif;
611
612 il->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
613 il4965_rx_missed_beacon_notif;
614 /* Rx handlers */
615 il->rx_handlers[REPLY_RX_PHY_CMD] = il4965_rx_reply_rx_phy;
616 il->rx_handlers[REPLY_RX_MPDU_CMD] = il4965_rx_reply_rx;
617 /* block ack */
618 il->rx_handlers[REPLY_COMPRESSED_BA] = il4965_rx_reply_compressed_ba;
619 /* Set up hardware specific Rx handlers */
620 il->cfg->ops->lib->rx_handler_setup(il);
621}
622
623/**
624 * il4965_rx_handle - Main entry function for receiving responses from uCode
625 *
626 * Uses the il->rx_handlers callback function array to invoke
627 * the appropriate handlers, including command responses,
628 * frame-received notifications, and other notifications.
629 */
630void il4965_rx_handle(struct il_priv *il)
631{
632 struct il_rx_buf *rxb;
633 struct il_rx_pkt *pkt;
634 struct il_rx_queue *rxq = &il->rxq;
635 u32 r, i;
636 int reclaim;
637 unsigned long flags;
638 u8 fill_rx = 0;
639 u32 count = 8;
640 int total_empty;
641
642 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
643 * buffer that the driver may process (last buffer filled by ucode). */
644 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
645 i = rxq->read;
646
647 /* Rx interrupt, but nothing sent from uCode */
648 if (i == r)
649 D_RX("r = %d, i = %d\n", r, i);
650
651 /* calculate total frames need to be restock after handling RX */
652 total_empty = r - rxq->write_actual;
653 if (total_empty < 0)
654 total_empty += RX_QUEUE_SIZE;
655
656 if (total_empty > (RX_QUEUE_SIZE / 2))
657 fill_rx = 1;
658
659 while (i != r) {
660 int len;
661
662 rxb = rxq->queue[i];
663
664 /* If an RXB doesn't have a Rx queue slot associated with it,
665 * then a bug has been introduced in the queue refilling
666 * routines -- catch it here */
667 BUG_ON(rxb == NULL);
668
669 rxq->queue[i] = NULL;
670
671 pci_unmap_page(il->pci_dev, rxb->page_dma,
672 PAGE_SIZE << il->hw_params.rx_page_order,
673 PCI_DMA_FROMDEVICE);
674 pkt = rxb_addr(rxb);
675
676 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
677 len += sizeof(u32); /* account for status word */
678
679 /* Reclaim a command buffer only if this packet is a response
680 * to a (driver-originated) command.
681 * If the packet (e.g. Rx frame) originated from uCode,
682 * there is no command buffer to reclaim.
683 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
684 * but apparently a few don't get set; catch them here. */
685 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
686 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
687 (pkt->hdr.cmd != REPLY_RX) &&
688 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
689 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
690 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
691 (pkt->hdr.cmd != REPLY_TX);
692
693 /* Based on type of command response or notification,
694 * handle those that need handling via function in
695 * rx_handlers table. See il4965_setup_rx_handlers() */
696 if (il->rx_handlers[pkt->hdr.cmd]) {
697 D_RX("r = %d, i = %d, %s, 0x%02x\n", r,
698 i, il_get_cmd_string(pkt->hdr.cmd),
699 pkt->hdr.cmd);
700 il->isr_stats.rx_handlers[pkt->hdr.cmd]++;
701 il->rx_handlers[pkt->hdr.cmd] (il, rxb);
702 } else {
703 /* No handling needed */
704 D_RX(
705 "r %d i %d No handler needed for %s, 0x%02x\n",
706 r, i, il_get_cmd_string(pkt->hdr.cmd),
707 pkt->hdr.cmd);
708 }
709
710 /*
711 * XXX: After here, we should always check rxb->page
712 * against NULL before touching it or its virtual
713 * memory (pkt). Because some rx_handler might have
714 * already taken or freed the pages.
715 */
716
717 if (reclaim) {
718 /* Invoke any callbacks, transfer the buffer to caller,
719 * and fire off the (possibly) blocking il_send_cmd()
720 * as we reclaim the driver command queue */
721 if (rxb->page)
722 il_tx_cmd_complete(il, rxb);
723 else
724 IL_WARN("Claim null rxb?\n");
725 }
726
727 /* Reuse the page if possible. For notification packets and
728 * SKBs that fail to Rx correctly, add them back into the
729 * rx_free list for reuse later. */
730 spin_lock_irqsave(&rxq->lock, flags);
731 if (rxb->page != NULL) {
732 rxb->page_dma = pci_map_page(il->pci_dev, rxb->page,
733 0, PAGE_SIZE << il->hw_params.rx_page_order,
734 PCI_DMA_FROMDEVICE);
735 list_add_tail(&rxb->list, &rxq->rx_free);
736 rxq->free_count++;
737 } else
738 list_add_tail(&rxb->list, &rxq->rx_used);
739
740 spin_unlock_irqrestore(&rxq->lock, flags);
741
742 i = (i + 1) & RX_QUEUE_MASK;
743 /* If there are a lot of unused frames,
744 * restock the Rx queue so ucode wont assert. */
745 if (fill_rx) {
746 count++;
747 if (count >= 8) {
748 rxq->read = i;
749 il4965_rx_replenish_now(il);
750 count = 0;
751 }
752 }
753 }
754
755 /* Backtrack one entry */
756 rxq->read = i;
757 if (fill_rx)
758 il4965_rx_replenish_now(il);
759 else
760 il4965_rx_queue_restock(il);
761}
762
763/* call this function to flush any scheduled tasklet */
764static inline void il4965_synchronize_irq(struct il_priv *il)
765{
766 /* wait to make sure we flush pending tasklet*/
767 synchronize_irq(il->pci_dev->irq);
768 tasklet_kill(&il->irq_tasklet);
769}
770
771static void il4965_irq_tasklet(struct il_priv *il)
772{
773 u32 inta, handled = 0;
774 u32 inta_fh;
775 unsigned long flags;
776 u32 i;
777#ifdef CONFIG_IWLEGACY_DEBUG
778 u32 inta_mask;
779#endif
780
781 spin_lock_irqsave(&il->lock, flags);
782
783 /* Ack/clear/reset pending uCode interrupts.
784 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
785 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
786 inta = _il_rd(il, CSR_INT);
787 _il_wr(il, CSR_INT, inta);
788
789 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
790 * Any new interrupts that happen after this, either while we're
791 * in this tasklet, or later, will show up in next ISR/tasklet. */
792 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
793 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
794
795#ifdef CONFIG_IWLEGACY_DEBUG
796 if (il_get_debug_level(il) & IL_DL_ISR) {
797 /* just for debug */
798 inta_mask = _il_rd(il, CSR_INT_MASK);
799 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
800 inta, inta_mask, inta_fh);
801 }
802#endif
803
804 spin_unlock_irqrestore(&il->lock, flags);
805
806 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
807 * atomic, make sure that inta covers all the interrupts that
808 * we've discovered, even if FH interrupt came in just after
809 * reading CSR_INT. */
810 if (inta_fh & CSR49_FH_INT_RX_MASK)
811 inta |= CSR_INT_BIT_FH_RX;
812 if (inta_fh & CSR49_FH_INT_TX_MASK)
813 inta |= CSR_INT_BIT_FH_TX;
814
815 /* Now service all interrupt bits discovered above. */
816 if (inta & CSR_INT_BIT_HW_ERR) {
817 IL_ERR("Hardware error detected. Restarting.\n");
818
819 /* Tell the device to stop sending interrupts */
820 il_disable_interrupts(il);
821
822 il->isr_stats.hw++;
823 il_irq_handle_error(il);
824
825 handled |= CSR_INT_BIT_HW_ERR;
826
827 return;
828 }
829
830#ifdef CONFIG_IWLEGACY_DEBUG
831 if (il_get_debug_level(il) & (IL_DL_ISR)) {
832 /* NIC fires this, but we don't use it, redundant with WAKEUP */
833 if (inta & CSR_INT_BIT_SCD) {
834 D_ISR("Scheduler finished to transmit "
835 "the frame/frames.\n");
836 il->isr_stats.sch++;
837 }
838
839 /* Alive notification via Rx interrupt will do the real work */
840 if (inta & CSR_INT_BIT_ALIVE) {
841 D_ISR("Alive interrupt\n");
842 il->isr_stats.alive++;
843 }
844 }
845#endif
846 /* Safely ignore these bits for debug checks below */
847 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
848
849 /* HW RF KILL switch toggled */
850 if (inta & CSR_INT_BIT_RF_KILL) {
851 int hw_rf_kill = 0;
852 if (!(_il_rd(il, CSR_GP_CNTRL) &
853 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
854 hw_rf_kill = 1;
855
856 IL_WARN("RF_KILL bit toggled to %s.\n",
857 hw_rf_kill ? "disable radio" : "enable radio");
858
859 il->isr_stats.rfkill++;
860
861 /* driver only loads ucode once setting the interface up.
862 * the driver allows loading the ucode even if the radio
863 * is killed. Hence update the killswitch state here. The
864 * rfkill handler will care about restarting if needed.
865 */
866 if (!test_bit(STATUS_ALIVE, &il->status)) {
867 if (hw_rf_kill)
868 set_bit(STATUS_RF_KILL_HW, &il->status);
869 else
870 clear_bit(STATUS_RF_KILL_HW, &il->status);
871 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
872 }
873
874 handled |= CSR_INT_BIT_RF_KILL;
875 }
876
877 /* Chip got too hot and stopped itself */
878 if (inta & CSR_INT_BIT_CT_KILL) {
879 IL_ERR("Microcode CT kill error detected.\n");
880 il->isr_stats.ctkill++;
881 handled |= CSR_INT_BIT_CT_KILL;
882 }
883
884 /* Error detected by uCode */
885 if (inta & CSR_INT_BIT_SW_ERR) {
886 IL_ERR("Microcode SW error detected. "
887 " Restarting 0x%X.\n", inta);
888 il->isr_stats.sw++;
889 il_irq_handle_error(il);
890 handled |= CSR_INT_BIT_SW_ERR;
891 }
892
893 /*
894 * uCode wakes up after power-down sleep.
895 * Tell device about any new tx or host commands enqueued,
896 * and about any Rx buffers made available while asleep.
897 */
898 if (inta & CSR_INT_BIT_WAKEUP) {
899 D_ISR("Wakeup interrupt\n");
900 il_rx_queue_update_write_ptr(il, &il->rxq);
901 for (i = 0; i < il->hw_params.max_txq_num; i++)
902 il_txq_update_write_ptr(il, &il->txq[i]);
903 il->isr_stats.wakeup++;
904 handled |= CSR_INT_BIT_WAKEUP;
905 }
906
907 /* All uCode command responses, including Tx command responses,
908 * Rx "responses" (frame-received notification), and other
909 * notifications from uCode come through here*/
910 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
911 il4965_rx_handle(il);
912 il->isr_stats.rx++;
913 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
914 }
915
916 /* This "Tx" DMA channel is used only for loading uCode */
917 if (inta & CSR_INT_BIT_FH_TX) {
918 D_ISR("uCode load interrupt\n");
919 il->isr_stats.tx++;
920 handled |= CSR_INT_BIT_FH_TX;
921 /* Wake up uCode load routine, now that load is complete */
922 il->ucode_write_complete = 1;
923 wake_up(&il->wait_command_queue);
924 }
925
926 if (inta & ~handled) {
927 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
928 il->isr_stats.unhandled++;
929 }
930
931 if (inta & ~(il->inta_mask)) {
932 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
933 inta & ~il->inta_mask);
934 IL_WARN(" with FH_INT = 0x%08x\n", inta_fh);
935 }
936
937 /* Re-enable all interrupts */
938 /* only Re-enable if disabled by irq */
939 if (test_bit(STATUS_INT_ENABLED, &il->status))
940 il_enable_interrupts(il);
941 /* Re-enable RF_KILL if it occurred */
942 else if (handled & CSR_INT_BIT_RF_KILL)
943 il_enable_rfkill_int(il);
944
945#ifdef CONFIG_IWLEGACY_DEBUG
946 if (il_get_debug_level(il) & (IL_DL_ISR)) {
947 inta = _il_rd(il, CSR_INT);
948 inta_mask = _il_rd(il, CSR_INT_MASK);
949 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
950 D_ISR(
951 "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
952 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
953 }
954#endif
955}
956
957/*****************************************************************************
958 *
959 * sysfs attributes
960 *
961 *****************************************************************************/
962
963#ifdef CONFIG_IWLEGACY_DEBUG
964
965/*
966 * The following adds a new attribute to the sysfs representation
967 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
968 * used for controlling the debug level.
969 *
970 * See the level definitions in iwl for details.
971 *
972 * The debug_level being managed using sysfs below is a per device debug
973 * level that is used instead of the global debug level if it (the per
974 * device debug level) is set.
975 */
976static ssize_t il4965_show_debug_level(struct device *d,
977 struct device_attribute *attr, char *buf)
978{
979 struct il_priv *il = dev_get_drvdata(d);
980 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
981}
982static ssize_t il4965_store_debug_level(struct device *d,
983 struct device_attribute *attr,
984 const char *buf, size_t count)
985{
986 struct il_priv *il = dev_get_drvdata(d);
987 unsigned long val;
988 int ret;
989
990 ret = strict_strtoul(buf, 0, &val);
991 if (ret)
992 IL_ERR("%s is not in hex or decimal form.\n", buf);
993 else {
994 il->debug_level = val;
995 if (il_alloc_traffic_mem(il))
996 IL_ERR(
997 "Not enough memory to generate traffic log\n");
998 }
999 return strnlen(buf, count);
1000}
1001
1002static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1003 il4965_show_debug_level, il4965_store_debug_level);
1004
1005
1006#endif /* CONFIG_IWLEGACY_DEBUG */
1007
1008
1009static ssize_t il4965_show_temperature(struct device *d,
1010 struct device_attribute *attr, char *buf)
1011{
1012 struct il_priv *il = dev_get_drvdata(d);
1013
1014 if (!il_is_alive(il))
1015 return -EAGAIN;
1016
1017 return sprintf(buf, "%d\n", il->temperature);
1018}
1019
1020static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
1021
1022static ssize_t il4965_show_tx_power(struct device *d,
1023 struct device_attribute *attr, char *buf)
1024{
1025 struct il_priv *il = dev_get_drvdata(d);
1026
1027 if (!il_is_ready_rf(il))
1028 return sprintf(buf, "off\n");
1029 else
1030 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
1031}
1032
1033static ssize_t il4965_store_tx_power(struct device *d,
1034 struct device_attribute *attr,
1035 const char *buf, size_t count)
1036{
1037 struct il_priv *il = dev_get_drvdata(d);
1038 unsigned long val;
1039 int ret;
1040
1041 ret = strict_strtoul(buf, 10, &val);
1042 if (ret)
1043 IL_INFO("%s is not in decimal form.\n", buf);
1044 else {
1045 ret = il_set_tx_power(il, val, false);
1046 if (ret)
1047 IL_ERR("failed setting tx power (0x%d).\n",
1048 ret);
1049 else
1050 ret = count;
1051 }
1052 return ret;
1053}
1054
1055static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO,
1056 il4965_show_tx_power, il4965_store_tx_power);
1057
1058static struct attribute *il_sysfs_entries[] = {
1059 &dev_attr_temperature.attr,
1060 &dev_attr_tx_power.attr,
1061#ifdef CONFIG_IWLEGACY_DEBUG
1062 &dev_attr_debug_level.attr,
1063#endif
1064 NULL
1065};
1066
1067static struct attribute_group il_attribute_group = {
1068 .name = NULL, /* put in device directory */
1069 .attrs = il_sysfs_entries,
1070};
1071
1072/******************************************************************************
1073 *
1074 * uCode download functions
1075 *
1076 ******************************************************************************/
1077
1078static void il4965_dealloc_ucode_pci(struct il_priv *il)
1079{
1080 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1081 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1082 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1083 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1084 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1085 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1086}
1087
1088static void il4965_nic_start(struct il_priv *il)
1089{
1090 /* Remove all resets to allow NIC to operate */
1091 _il_wr(il, CSR_RESET, 0);
1092}
1093
1094static void il4965_ucode_callback(const struct firmware *ucode_raw,
1095 void *context);
1096static int il4965_mac_setup_register(struct il_priv *il,
1097 u32 max_probe_length);
1098
1099static int __must_check il4965_request_firmware(struct il_priv *il, bool first)
1100{
1101 const char *name_pre = il->cfg->fw_name_pre;
1102 char tag[8];
1103
1104 if (first) {
1105 il->fw_idx = il->cfg->ucode_api_max;
1106 sprintf(tag, "%d", il->fw_idx);
1107 } else {
1108 il->fw_idx--;
1109 sprintf(tag, "%d", il->fw_idx);
1110 }
1111
1112 if (il->fw_idx < il->cfg->ucode_api_min) {
1113 IL_ERR("no suitable firmware found!\n");
1114 return -ENOENT;
1115 }
1116
1117 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1118
1119 D_INFO("attempting to load firmware '%s'\n",
1120 il->firmware_name);
1121
1122 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
1123 &il->pci_dev->dev, GFP_KERNEL, il,
1124 il4965_ucode_callback);
1125}
1126
1127struct il4965_firmware_pieces {
1128 const void *inst, *data, *init, *init_data, *boot;
1129 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1130};
1131
1132static int il4965_load_firmware(struct il_priv *il,
1133 const struct firmware *ucode_raw,
1134 struct il4965_firmware_pieces *pieces)
1135{
1136 struct il_ucode_header *ucode = (void *)ucode_raw->data;
1137 u32 api_ver, hdr_size;
1138 const u8 *src;
1139
1140 il->ucode_ver = le32_to_cpu(ucode->ver);
1141 api_ver = IL_UCODE_API(il->ucode_ver);
1142
1143 switch (api_ver) {
1144 default:
1145 case 0:
1146 case 1:
1147 case 2:
1148 hdr_size = 24;
1149 if (ucode_raw->size < hdr_size) {
1150 IL_ERR("File size too small!\n");
1151 return -EINVAL;
1152 }
1153 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
1154 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
1155 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
1156 pieces->init_data_size =
1157 le32_to_cpu(ucode->v1.init_data_size);
1158 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
1159 src = ucode->v1.data;
1160 break;
1161 }
1162
1163 /* Verify size of file vs. image size info in file's header */
1164 if (ucode_raw->size != hdr_size + pieces->inst_size +
1165 pieces->data_size + pieces->init_size +
1166 pieces->init_data_size + pieces->boot_size) {
1167
1168 IL_ERR(
1169 "uCode file size %d does not match expected size\n",
1170 (int)ucode_raw->size);
1171 return -EINVAL;
1172 }
1173
1174 pieces->inst = src;
1175 src += pieces->inst_size;
1176 pieces->data = src;
1177 src += pieces->data_size;
1178 pieces->init = src;
1179 src += pieces->init_size;
1180 pieces->init_data = src;
1181 src += pieces->init_data_size;
1182 pieces->boot = src;
1183 src += pieces->boot_size;
1184
1185 return 0;
1186}
1187
1188/**
1189 * il4965_ucode_callback - callback when firmware was loaded
1190 *
1191 * If loaded successfully, copies the firmware into buffers
1192 * for the card to fetch (via DMA).
1193 */
1194static void
1195il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
1196{
1197 struct il_priv *il = context;
1198 struct il_ucode_header *ucode;
1199 int err;
1200 struct il4965_firmware_pieces pieces;
1201 const unsigned int api_max = il->cfg->ucode_api_max;
1202 const unsigned int api_min = il->cfg->ucode_api_min;
1203 u32 api_ver;
1204
1205 u32 max_probe_length = 200;
1206 u32 standard_phy_calibration_size =
1207 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1208
1209 memset(&pieces, 0, sizeof(pieces));
1210
1211 if (!ucode_raw) {
1212 if (il->fw_idx <= il->cfg->ucode_api_max)
1213 IL_ERR(
1214 "request for firmware file '%s' failed.\n",
1215 il->firmware_name);
1216 goto try_again;
1217 }
1218
1219 D_INFO("Loaded firmware file '%s' (%zd bytes).\n",
1220 il->firmware_name, ucode_raw->size);
1221
1222 /* Make sure that we got at least the API version number */
1223 if (ucode_raw->size < 4) {
1224 IL_ERR("File size way too small!\n");
1225 goto try_again;
1226 }
1227
1228 /* Data from ucode file: header followed by uCode images */
1229 ucode = (struct il_ucode_header *)ucode_raw->data;
1230
1231 err = il4965_load_firmware(il, ucode_raw, &pieces);
1232
1233 if (err)
1234 goto try_again;
1235
1236 api_ver = IL_UCODE_API(il->ucode_ver);
1237
1238 /*
1239 * api_ver should match the api version forming part of the
1240 * firmware filename ... but we don't check for that and only rely
1241 * on the API version read from firmware header from here on forward
1242 */
1243 if (api_ver < api_min || api_ver > api_max) {
1244 IL_ERR(
1245 "Driver unable to support your firmware API. "
1246 "Driver supports v%u, firmware is v%u.\n",
1247 api_max, api_ver);
1248 goto try_again;
1249 }
1250
1251 if (api_ver != api_max)
1252 IL_ERR(
1253 "Firmware has old API version. Expected v%u, "
1254 "got v%u. New firmware can be obtained "
1255 "from http://www.intellinuxwireless.org.\n",
1256 api_max, api_ver);
1257
1258 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
1259 IL_UCODE_MAJOR(il->ucode_ver),
1260 IL_UCODE_MINOR(il->ucode_ver),
1261 IL_UCODE_API(il->ucode_ver),
1262 IL_UCODE_SERIAL(il->ucode_ver));
1263
1264 snprintf(il->hw->wiphy->fw_version,
1265 sizeof(il->hw->wiphy->fw_version),
1266 "%u.%u.%u.%u",
1267 IL_UCODE_MAJOR(il->ucode_ver),
1268 IL_UCODE_MINOR(il->ucode_ver),
1269 IL_UCODE_API(il->ucode_ver),
1270 IL_UCODE_SERIAL(il->ucode_ver));
1271
1272 /*
1273 * For any of the failures below (before allocating pci memory)
1274 * we will try to load a version with a smaller API -- maybe the
1275 * user just got a corrupted version of the latest API.
1276 */
1277
1278 D_INFO("f/w package hdr ucode version raw = 0x%x\n",
1279 il->ucode_ver);
1280 D_INFO("f/w package hdr runtime inst size = %Zd\n",
1281 pieces.inst_size);
1282 D_INFO("f/w package hdr runtime data size = %Zd\n",
1283 pieces.data_size);
1284 D_INFO("f/w package hdr init inst size = %Zd\n",
1285 pieces.init_size);
1286 D_INFO("f/w package hdr init data size = %Zd\n",
1287 pieces.init_data_size);
1288 D_INFO("f/w package hdr boot inst size = %Zd\n",
1289 pieces.boot_size);
1290
1291 /* Verify that uCode images will fit in card's SRAM */
1292 if (pieces.inst_size > il->hw_params.max_inst_size) {
1293 IL_ERR("uCode instr len %Zd too large to fit in\n",
1294 pieces.inst_size);
1295 goto try_again;
1296 }
1297
1298 if (pieces.data_size > il->hw_params.max_data_size) {
1299 IL_ERR("uCode data len %Zd too large to fit in\n",
1300 pieces.data_size);
1301 goto try_again;
1302 }
1303
1304 if (pieces.init_size > il->hw_params.max_inst_size) {
1305 IL_ERR("uCode init instr len %Zd too large to fit in\n",
1306 pieces.init_size);
1307 goto try_again;
1308 }
1309
1310 if (pieces.init_data_size > il->hw_params.max_data_size) {
1311 IL_ERR("uCode init data len %Zd too large to fit in\n",
1312 pieces.init_data_size);
1313 goto try_again;
1314 }
1315
1316 if (pieces.boot_size > il->hw_params.max_bsm_size) {
1317 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
1318 pieces.boot_size);
1319 goto try_again;
1320 }
1321
1322 /* Allocate ucode buffers for card's bus-master loading ... */
1323
1324 /* Runtime instructions and 2 copies of data:
1325 * 1) unmodified from disk
1326 * 2) backup cache for save/restore during power-downs */
1327 il->ucode_code.len = pieces.inst_size;
1328 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1329
1330 il->ucode_data.len = pieces.data_size;
1331 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1332
1333 il->ucode_data_backup.len = pieces.data_size;
1334 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1335
1336 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1337 !il->ucode_data_backup.v_addr)
1338 goto err_pci_alloc;
1339
1340 /* Initialization instructions and data */
1341 if (pieces.init_size && pieces.init_data_size) {
1342 il->ucode_init.len = pieces.init_size;
1343 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
1344
1345 il->ucode_init_data.len = pieces.init_data_size;
1346 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
1347
1348 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
1349 goto err_pci_alloc;
1350 }
1351
1352 /* Bootstrap (instructions only, no data) */
1353 if (pieces.boot_size) {
1354 il->ucode_boot.len = pieces.boot_size;
1355 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
1356
1357 if (!il->ucode_boot.v_addr)
1358 goto err_pci_alloc;
1359 }
1360
1361 /* Now that we can no longer fail, copy information */
1362
1363 il->sta_key_max_num = STA_KEY_MAX_NUM;
1364
1365 /* Copy images into buffers for card's bus-master reads ... */
1366
1367 /* Runtime instructions (first block of data in file) */
1368 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
1369 pieces.inst_size);
1370 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1371
1372 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1373 il->ucode_code.v_addr, (u32)il->ucode_code.p_addr);
1374
1375 /*
1376 * Runtime data
1377 * NOTE: Copy into backup buffer will be done in il_up()
1378 */
1379 D_INFO("Copying (but not loading) uCode data len %Zd\n",
1380 pieces.data_size);
1381 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
1382 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1383
1384 /* Initialization instructions */
1385 if (pieces.init_size) {
1386 D_INFO(
1387 "Copying (but not loading) init instr len %Zd\n",
1388 pieces.init_size);
1389 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
1390 }
1391
1392 /* Initialization data */
1393 if (pieces.init_data_size) {
1394 D_INFO(
1395 "Copying (but not loading) init data len %Zd\n",
1396 pieces.init_data_size);
1397 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
1398 pieces.init_data_size);
1399 }
1400
1401 /* Bootstrap instructions */
1402 D_INFO("Copying (but not loading) boot instr len %Zd\n",
1403 pieces.boot_size);
1404 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1405
1406 /*
1407 * figure out the offset of chain noise reset and gain commands
1408 * base on the size of standard phy calibration commands table size
1409 */
1410 il->_4965.phy_calib_chain_noise_reset_cmd =
1411 standard_phy_calibration_size;
1412 il->_4965.phy_calib_chain_noise_gain_cmd =
1413 standard_phy_calibration_size + 1;
1414
1415 /**************************************************
1416 * This is still part of probe() in a sense...
1417 *
1418 * 9. Setup and register with mac80211 and debugfs
1419 **************************************************/
1420 err = il4965_mac_setup_register(il, max_probe_length);
1421 if (err)
1422 goto out_unbind;
1423
1424 err = il_dbgfs_register(il, DRV_NAME);
1425 if (err)
1426 IL_ERR(
1427 "failed to create debugfs files. Ignoring error: %d\n", err);
1428
1429 err = sysfs_create_group(&il->pci_dev->dev.kobj,
1430 &il_attribute_group);
1431 if (err) {
1432 IL_ERR("failed to create sysfs device attributes\n");
1433 goto out_unbind;
1434 }
1435
1436 /* We have our copies now, allow OS release its copies */
1437 release_firmware(ucode_raw);
1438 complete(&il->_4965.firmware_loading_complete);
1439 return;
1440
1441 try_again:
1442 /* try next, if any */
1443 if (il4965_request_firmware(il, false))
1444 goto out_unbind;
1445 release_firmware(ucode_raw);
1446 return;
1447
1448 err_pci_alloc:
1449 IL_ERR("failed to allocate pci memory\n");
1450 il4965_dealloc_ucode_pci(il);
1451 out_unbind:
1452 complete(&il->_4965.firmware_loading_complete);
1453 device_release_driver(&il->pci_dev->dev);
1454 release_firmware(ucode_raw);
1455}
1456
1457static const char * const desc_lookup_text[] = {
1458 "OK",
1459 "FAIL",
1460 "BAD_PARAM",
1461 "BAD_CHECKSUM",
1462 "NMI_INTERRUPT_WDG",
1463 "SYSASSERT",
1464 "FATAL_ERROR",
1465 "BAD_COMMAND",
1466 "HW_ERROR_TUNE_LOCK",
1467 "HW_ERROR_TEMPERATURE",
1468 "ILLEGAL_CHAN_FREQ",
1469 "VCC_NOT_STBL",
1470 "FH_ERROR",
1471 "NMI_INTERRUPT_HOST",
1472 "NMI_INTERRUPT_ACTION_PT",
1473 "NMI_INTERRUPT_UNKNOWN",
1474 "UCODE_VERSION_MISMATCH",
1475 "HW_ERROR_ABS_LOCK",
1476 "HW_ERROR_CAL_LOCK_FAIL",
1477 "NMI_INTERRUPT_INST_ACTION_PT",
1478 "NMI_INTERRUPT_DATA_ACTION_PT",
1479 "NMI_TRM_HW_ER",
1480 "NMI_INTERRUPT_TRM",
1481 "NMI_INTERRUPT_BREAK_POINT",
1482 "DEBUG_0",
1483 "DEBUG_1",
1484 "DEBUG_2",
1485 "DEBUG_3",
1486};
1487
1488static struct { char *name; u8 num; } advanced_lookup[] = {
1489 { "NMI_INTERRUPT_WDG", 0x34 },
1490 { "SYSASSERT", 0x35 },
1491 { "UCODE_VERSION_MISMATCH", 0x37 },
1492 { "BAD_COMMAND", 0x38 },
1493 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1494 { "FATAL_ERROR", 0x3D },
1495 { "NMI_TRM_HW_ERR", 0x46 },
1496 { "NMI_INTERRUPT_TRM", 0x4C },
1497 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1498 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1499 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1500 { "NMI_INTERRUPT_HOST", 0x66 },
1501 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1502 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1503 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1504 { "ADVANCED_SYSASSERT", 0 },
1505};
1506
1507static const char *il4965_desc_lookup(u32 num)
1508{
1509 int i;
1510 int max = ARRAY_SIZE(desc_lookup_text);
1511
1512 if (num < max)
1513 return desc_lookup_text[num];
1514
1515 max = ARRAY_SIZE(advanced_lookup) - 1;
1516 for (i = 0; i < max; i++) {
1517 if (advanced_lookup[i].num == num)
1518 break;
1519 }
1520 return advanced_lookup[i].name;
1521}
1522
1523#define ERROR_START_OFFSET (1 * sizeof(u32))
1524#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1525
1526void il4965_dump_nic_error_log(struct il_priv *il)
1527{
1528 u32 data2, line;
1529 u32 desc, time, count, base, data1;
1530 u32 blink1, blink2, ilink1, ilink2;
1531 u32 pc, hcmd;
1532
1533 if (il->ucode_type == UCODE_INIT) {
1534 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
1535 } else {
1536 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1537 }
1538
1539 if (!il->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1540 IL_ERR(
1541 "Not valid error log pointer 0x%08X for %s uCode\n",
1542 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
1543 return;
1544 }
1545
1546 count = il_read_targ_mem(il, base);
1547
1548 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1549 IL_ERR("Start IWL Error Log Dump:\n");
1550 IL_ERR("Status: 0x%08lX, count: %d\n",
1551 il->status, count);
1552 }
1553
1554 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
1555 il->isr_stats.err_code = desc;
1556 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
1557 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
1558 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
1559 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
1560 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
1561 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
1562 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
1563 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
1564 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
1565 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
1566
1567 IL_ERR("Desc Time "
1568 "data1 data2 line\n");
1569 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1570 il4965_desc_lookup(desc), desc, time, data1, data2, line);
1571 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
1572 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1573 pc, blink1, blink2, ilink1, ilink2, hcmd);
1574}
1575
1576static void il4965_rf_kill_ct_config(struct il_priv *il)
1577{
1578 struct il_ct_kill_config cmd;
1579 unsigned long flags;
1580 int ret = 0;
1581
1582 spin_lock_irqsave(&il->lock, flags);
1583 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
1584 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1585 spin_unlock_irqrestore(&il->lock, flags);
1586
1587 cmd.critical_temperature_R =
1588 cpu_to_le32(il->hw_params.ct_kill_threshold);
1589
1590 ret = il_send_cmd_pdu(il, REPLY_CT_KILL_CONFIG_CMD,
1591 sizeof(cmd), &cmd);
1592 if (ret)
1593 IL_ERR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1594 else
1595 D_INFO("REPLY_CT_KILL_CONFIG_CMD "
1596 "succeeded, "
1597 "critical temperature is %d\n",
1598 il->hw_params.ct_kill_threshold);
1599}
1600
1601static const s8 default_queue_to_tx_fifo[] = {
1602 IL_TX_FIFO_VO,
1603 IL_TX_FIFO_VI,
1604 IL_TX_FIFO_BE,
1605 IL_TX_FIFO_BK,
1606 IL49_CMD_FIFO_NUM,
1607 IL_TX_FIFO_UNUSED,
1608 IL_TX_FIFO_UNUSED,
1609};
1610
1611static int il4965_alive_notify(struct il_priv *il)
1612{
1613 u32 a;
1614 unsigned long flags;
1615 int i, chan;
1616 u32 reg_val;
1617
1618 spin_lock_irqsave(&il->lock, flags);
1619
1620 /* Clear 4965's internal Tx Scheduler data base */
1621 il->scd_base_addr = il_rd_prph(il,
1622 IL49_SCD_SRAM_BASE_ADDR);
1623 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
1624 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1625 il_write_targ_mem(il, a, 0);
1626 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
1627 il_write_targ_mem(il, a, 0);
1628 for (; a < il->scd_base_addr +
1629 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); a += 4)
1630 il_write_targ_mem(il, a, 0);
1631
1632 /* Tel 4965 where to find Tx byte count tables */
1633 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR,
1634 il->scd_bc_tbls.dma >> 10);
1635
1636 /* Enable DMA channel */
1637 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
1638 il_wr(il,
1639 FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1640 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1641 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1642
1643 /* Update FH chicken bits */
1644 reg_val = il_rd(il, FH_TX_CHICKEN_BITS_REG);
1645 il_wr(il, FH_TX_CHICKEN_BITS_REG,
1646 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1647
1648 /* Disable chain mode for all queues */
1649 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
1650
1651 /* Initialize each Tx queue (including the command queue) */
1652 for (i = 0; i < il->hw_params.max_txq_num; i++) {
1653
1654 /* TFD circular buffer read/write idxes */
1655 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
1656 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
1657
1658 /* Max Tx Window size for Scheduler-ACK mode */
1659 il_write_targ_mem(il, il->scd_base_addr +
1660 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
1661 (SCD_WIN_SIZE <<
1662 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1663 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1664
1665 /* Frame limit */
1666 il_write_targ_mem(il, il->scd_base_addr +
1667 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
1668 sizeof(u32),
1669 (SCD_FRAME_LIMIT <<
1670 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1671 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1672
1673 }
1674 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
1675 (1 << il->hw_params.max_txq_num) - 1);
1676
1677 /* Activate all Tx DMA/FIFO channels */
1678 il4965_txq_set_sched(il, IL_MASK(0, 6));
1679
1680 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
1681
1682 /* make sure all queue are not stopped */
1683 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
1684 for (i = 0; i < 4; i++)
1685 atomic_set(&il->queue_stop_count[i], 0);
1686
1687 /* reset to 0 to enable all the queue first */
1688 il->txq_ctx_active_msk = 0;
1689 /* Map each Tx/cmd queue to its corresponding fifo */
1690 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
1691
1692 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1693 int ac = default_queue_to_tx_fifo[i];
1694
1695 il_txq_ctx_activate(il, i);
1696
1697 if (ac == IL_TX_FIFO_UNUSED)
1698 continue;
1699
1700 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
1701 }
1702
1703 spin_unlock_irqrestore(&il->lock, flags);
1704
1705 return 0;
1706}
1707
1708/**
1709 * il4965_alive_start - called after REPLY_ALIVE notification received
1710 * from protocol/runtime uCode (initialization uCode's
1711 * Alive gets handled by il_init_alive_start()).
1712 */
1713static void il4965_alive_start(struct il_priv *il)
1714{
1715 int ret = 0;
1716 struct il_rxon_context *ctx = &il->ctx;
1717
1718 D_INFO("Runtime Alive received.\n");
1719
1720 if (il->card_alive.is_valid != UCODE_VALID_OK) {
1721 /* We had an error bringing up the hardware, so take it
1722 * all the way back down so we can try again */
1723 D_INFO("Alive failed.\n");
1724 goto restart;
1725 }
1726
1727 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1728 * This is a paranoid check, because we would not have gotten the
1729 * "runtime" alive if code weren't properly loaded. */
1730 if (il4965_verify_ucode(il)) {
1731 /* Runtime instruction load was bad;
1732 * take it all the way back down so we can try again */
1733 D_INFO("Bad runtime uCode load.\n");
1734 goto restart;
1735 }
1736
1737 ret = il4965_alive_notify(il);
1738 if (ret) {
1739 IL_WARN(
1740 "Could not complete ALIVE transition [ntf]: %d\n", ret);
1741 goto restart;
1742 }
1743
1744
1745 /* After the ALIVE response, we can send host commands to the uCode */
1746 set_bit(STATUS_ALIVE, &il->status);
1747
1748 /* Enable watchdog to monitor the driver tx queues */
1749 il_setup_watchdog(il);
1750
1751 if (il_is_rfkill(il))
1752 return;
1753
1754 ieee80211_wake_queues(il->hw);
1755
1756 il->active_rate = RATES_MASK;
1757
1758 if (il_is_associated_ctx(ctx)) {
1759 struct il_rxon_cmd *active_rxon =
1760 (struct il_rxon_cmd *)&ctx->active;
1761 /* apply any changes in staging */
1762 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
1763 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1764 } else {
1765 /* Initialize our rx_config data */
1766 il_connection_init_rx_config(il, &il->ctx);
1767
1768 if (il->cfg->ops->hcmd->set_rxon_chain)
1769 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
1770 }
1771
1772 /* Configure bluetooth coexistence if enabled */
1773 il_send_bt_config(il);
1774
1775 il4965_reset_run_time_calib(il);
1776
1777 set_bit(STATUS_READY, &il->status);
1778
1779 /* Configure the adapter for unassociated operation */
1780 il_commit_rxon(il, ctx);
1781
1782 /* At this point, the NIC is initialized and operational */
1783 il4965_rf_kill_ct_config(il);
1784
1785 D_INFO("ALIVE processing complete.\n");
1786 wake_up(&il->wait_command_queue);
1787
1788 il_power_update_mode(il, true);
1789 D_INFO("Updated power mode\n");
1790
1791 return;
1792
1793 restart:
1794 queue_work(il->workqueue, &il->restart);
1795}
1796
1797static void il4965_cancel_deferred_work(struct il_priv *il);
1798
1799static void __il4965_down(struct il_priv *il)
1800{
1801 unsigned long flags;
1802 int exit_pending;
1803
1804 D_INFO(DRV_NAME " is going down\n");
1805
1806 il_scan_cancel_timeout(il, 200);
1807
1808 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &il->status);
1809
1810 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
1811 * to prevent rearm timer */
1812 del_timer_sync(&il->watchdog);
1813
1814 il_clear_ucode_stations(il, NULL);
1815 il_dealloc_bcast_stations(il);
1816 il_clear_driver_stations(il);
1817
1818 /* Unblock any waiting calls */
1819 wake_up_all(&il->wait_command_queue);
1820
1821 /* Wipe out the EXIT_PENDING status bit if we are not actually
1822 * exiting the module */
1823 if (!exit_pending)
1824 clear_bit(STATUS_EXIT_PENDING, &il->status);
1825
1826 /* stop and reset the on-board processor */
1827 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1828
1829 /* tell the device to stop sending interrupts */
1830 spin_lock_irqsave(&il->lock, flags);
1831 il_disable_interrupts(il);
1832 spin_unlock_irqrestore(&il->lock, flags);
1833 il4965_synchronize_irq(il);
1834
1835 if (il->mac80211_registered)
1836 ieee80211_stop_queues(il->hw);
1837
1838 /* If we have not previously called il_init() then
1839 * clear all bits but the RF Kill bit and return */
1840 if (!il_is_init(il)) {
1841 il->status = test_bit(STATUS_RF_KILL_HW, &il->status) <<
1842 STATUS_RF_KILL_HW |
1843 test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
1844 STATUS_GEO_CONFIGURED |
1845 test_bit(STATUS_EXIT_PENDING, &il->status) <<
1846 STATUS_EXIT_PENDING;
1847 goto exit;
1848 }
1849
1850 /* ...otherwise clear out all the status bits but the RF Kill
1851 * bit and continue taking the NIC down. */
1852 il->status &= test_bit(STATUS_RF_KILL_HW, &il->status) <<
1853 STATUS_RF_KILL_HW |
1854 test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
1855 STATUS_GEO_CONFIGURED |
1856 test_bit(STATUS_FW_ERROR, &il->status) <<
1857 STATUS_FW_ERROR |
1858 test_bit(STATUS_EXIT_PENDING, &il->status) <<
1859 STATUS_EXIT_PENDING;
1860
1861 il4965_txq_ctx_stop(il);
1862 il4965_rxq_stop(il);
1863
1864 /* Power-down device's busmaster DMA clocks */
1865 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
1866 udelay(5);
1867
1868 /* Make sure (redundant) we've released our request to stay awake */
1869 il_clear_bit(il, CSR_GP_CNTRL,
1870 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1871
1872 /* Stop the device, and put it in low power state */
1873 il_apm_stop(il);
1874
1875 exit:
1876 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
1877
1878 dev_kfree_skb(il->beacon_skb);
1879 il->beacon_skb = NULL;
1880
1881 /* clear out any free frames */
1882 il4965_clear_free_frames(il);
1883}
1884
1885static void il4965_down(struct il_priv *il)
1886{
1887 mutex_lock(&il->mutex);
1888 __il4965_down(il);
1889 mutex_unlock(&il->mutex);
1890
1891 il4965_cancel_deferred_work(il);
1892}
1893
1894#define HW_READY_TIMEOUT (50)
1895
1896static int il4965_set_hw_ready(struct il_priv *il)
1897{
1898 int ret = 0;
1899
1900 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
1901 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1902
1903 /* See if we got it */
1904 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
1905 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1906 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1907 HW_READY_TIMEOUT);
1908 if (ret != -ETIMEDOUT)
1909 il->hw_ready = true;
1910 else
1911 il->hw_ready = false;
1912
1913 D_INFO("hardware %s\n",
1914 (il->hw_ready == 1) ? "ready" : "not ready");
1915 return ret;
1916}
1917
1918static int il4965_prepare_card_hw(struct il_priv *il)
1919{
1920 int ret = 0;
1921
1922 D_INFO("il4965_prepare_card_hw enter\n");
1923
1924 ret = il4965_set_hw_ready(il);
1925 if (il->hw_ready)
1926 return ret;
1927
1928 /* If HW is not ready, prepare the conditions to check again */
1929 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
1930 CSR_HW_IF_CONFIG_REG_PREPARE);
1931
1932 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
1933 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1934 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1935
1936 /* HW should be ready by now, check again. */
1937 if (ret != -ETIMEDOUT)
1938 il4965_set_hw_ready(il);
1939
1940 return ret;
1941}
1942
1943#define MAX_HW_RESTARTS 5
1944
1945static int __il4965_up(struct il_priv *il)
1946{
1947 int i;
1948 int ret;
1949
1950 if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
1951 IL_WARN("Exit pending; will not bring the NIC up\n");
1952 return -EIO;
1953 }
1954
1955 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
1956 IL_ERR("ucode not available for device bringup\n");
1957 return -EIO;
1958 }
1959
1960 ret = il4965_alloc_bcast_station(il, &il->ctx);
1961 if (ret) {
1962 il_dealloc_bcast_stations(il);
1963 return ret;
1964 }
1965
1966 il4965_prepare_card_hw(il);
1967
1968 if (!il->hw_ready) {
1969 IL_WARN("Exit HW not ready\n");
1970 return -EIO;
1971 }
1972
1973 /* If platform's RF_KILL switch is NOT set to KILL */
1974 if (_il_rd(il,
1975 CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1976 clear_bit(STATUS_RF_KILL_HW, &il->status);
1977 else
1978 set_bit(STATUS_RF_KILL_HW, &il->status);
1979
1980 if (il_is_rfkill(il)) {
1981 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
1982
1983 il_enable_interrupts(il);
1984 IL_WARN("Radio disabled by HW RF Kill switch\n");
1985 return 0;
1986 }
1987
1988 _il_wr(il, CSR_INT, 0xFFFFFFFF);
1989
1990 /* must be initialised before il_hw_nic_init */
1991 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
1992
1993 ret = il4965_hw_nic_init(il);
1994 if (ret) {
1995 IL_ERR("Unable to init nic\n");
1996 return ret;
1997 }
1998
1999 /* make sure rfkill handshake bits are cleared */
2000 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2001 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
2002 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2003
2004 /* clear (again), then enable host interrupts */
2005 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2006 il_enable_interrupts(il);
2007
2008 /* really make sure rfkill handshake bits are cleared */
2009 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2010 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2011
2012 /* Copy original ucode data image from disk into backup cache.
2013 * This will be used to initialize the on-board processor's
2014 * data SRAM for a clean start when the runtime program first loads. */
2015 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2016 il->ucode_data.len);
2017
2018 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2019
2020 /* load bootstrap state machine,
2021 * load bootstrap program into processor's memory,
2022 * prepare to load the "initialize" uCode */
2023 ret = il->cfg->ops->lib->load_ucode(il);
2024
2025 if (ret) {
2026 IL_ERR("Unable to set up bootstrap uCode: %d\n",
2027 ret);
2028 continue;
2029 }
2030
2031 /* start card; "initialize" will load runtime ucode */
2032 il4965_nic_start(il);
2033
2034 D_INFO(DRV_NAME " is coming up\n");
2035
2036 return 0;
2037 }
2038
2039 set_bit(STATUS_EXIT_PENDING, &il->status);
2040 __il4965_down(il);
2041 clear_bit(STATUS_EXIT_PENDING, &il->status);
2042
2043 /* tried to restart and config the device for as long as our
2044 * patience could withstand */
2045 IL_ERR("Unable to initialize device after %d attempts.\n", i);
2046 return -EIO;
2047}
2048
2049
2050/*****************************************************************************
2051 *
2052 * Workqueue callbacks
2053 *
2054 *****************************************************************************/
2055
2056static void il4965_bg_init_alive_start(struct work_struct *data)
2057{
2058 struct il_priv *il =
2059 container_of(data, struct il_priv, init_alive_start.work);
2060
2061 mutex_lock(&il->mutex);
2062 if (test_bit(STATUS_EXIT_PENDING, &il->status))
2063 goto out;
2064
2065 il->cfg->ops->lib->init_alive_start(il);
2066out:
2067 mutex_unlock(&il->mutex);
2068}
2069
2070static void il4965_bg_alive_start(struct work_struct *data)
2071{
2072 struct il_priv *il =
2073 container_of(data, struct il_priv, alive_start.work);
2074
2075 mutex_lock(&il->mutex);
2076 if (test_bit(STATUS_EXIT_PENDING, &il->status))
2077 goto out;
2078
2079 il4965_alive_start(il);
2080out:
2081 mutex_unlock(&il->mutex);
2082}
2083
2084static void il4965_bg_run_time_calib_work(struct work_struct *work)
2085{
2086 struct il_priv *il = container_of(work, struct il_priv,
2087 run_time_calib_work);
2088
2089 mutex_lock(&il->mutex);
2090
2091 if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
2092 test_bit(STATUS_SCANNING, &il->status)) {
2093 mutex_unlock(&il->mutex);
2094 return;
2095 }
2096
2097 if (il->start_calib) {
2098 il4965_chain_noise_calibration(il,
2099 (void *)&il->_4965.stats);
2100 il4965_sensitivity_calibration(il,
2101 (void *)&il->_4965.stats);
2102 }
2103
2104 mutex_unlock(&il->mutex);
2105}
2106
2107static void il4965_bg_restart(struct work_struct *data)
2108{
2109 struct il_priv *il = container_of(data, struct il_priv, restart);
2110
2111 if (test_bit(STATUS_EXIT_PENDING, &il->status))
2112 return;
2113
2114 if (test_and_clear_bit(STATUS_FW_ERROR, &il->status)) {
2115 mutex_lock(&il->mutex);
2116 il->ctx.vif = NULL;
2117 il->is_open = 0;
2118
2119 __il4965_down(il);
2120
2121 mutex_unlock(&il->mutex);
2122 il4965_cancel_deferred_work(il);
2123 ieee80211_restart_hw(il->hw);
2124 } else {
2125 il4965_down(il);
2126
2127 mutex_lock(&il->mutex);
2128 if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
2129 mutex_unlock(&il->mutex);
2130 return;
2131 }
2132
2133 __il4965_up(il);
2134 mutex_unlock(&il->mutex);
2135 }
2136}
2137
2138static void il4965_bg_rx_replenish(struct work_struct *data)
2139{
2140 struct il_priv *il =
2141 container_of(data, struct il_priv, rx_replenish);
2142
2143 if (test_bit(STATUS_EXIT_PENDING, &il->status))
2144 return;
2145
2146 mutex_lock(&il->mutex);
2147 il4965_rx_replenish(il);
2148 mutex_unlock(&il->mutex);
2149}
2150
2151/*****************************************************************************
2152 *
2153 * mac80211 entry point functions
2154 *
2155 *****************************************************************************/
2156
2157#define UCODE_READY_TIMEOUT (4 * HZ)
2158
2159/*
2160 * Not a mac80211 entry point function, but it fits in with all the
2161 * other mac80211 functions grouped here.
2162 */
2163static int il4965_mac_setup_register(struct il_priv *il,
2164 u32 max_probe_length)
2165{
2166 int ret;
2167 struct ieee80211_hw *hw = il->hw;
2168
2169 hw->rate_control_algorithm = "iwl-4965-rs";
2170
2171 /* Tell mac80211 our characteristics */
2172 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2173 IEEE80211_HW_AMPDU_AGGREGATION |
2174 IEEE80211_HW_NEED_DTIM_PERIOD |
2175 IEEE80211_HW_SPECTRUM_MGMT |
2176 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2177
2178 if (il->cfg->sku & IL_SKU_N)
2179 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2180 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2181
2182 hw->sta_data_size = sizeof(struct il_station_priv);
2183 hw->vif_data_size = sizeof(struct il_vif_priv);
2184
2185 hw->wiphy->interface_modes |= il->ctx.interface_modes;
2186 hw->wiphy->interface_modes |= il->ctx.exclusive_interface_modes;
2187
2188 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2189 WIPHY_FLAG_DISABLE_BEACON_HINTS;
2190
2191 /*
2192 * For now, disable PS by default because it affects
2193 * RX performance significantly.
2194 */
2195 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2196
2197 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2198 /* we create the 802.11 header and a zero-length SSID element */
2199 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
2200
2201 /* Default value; 4 EDCA QOS priorities */
2202 hw->queues = 4;
2203
2204 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
2205
2206 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
2207 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2208 &il->bands[IEEE80211_BAND_2GHZ];
2209 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
2210 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2211 &il->bands[IEEE80211_BAND_5GHZ];
2212
2213 il_leds_init(il);
2214
2215 ret = ieee80211_register_hw(il->hw);
2216 if (ret) {
2217 IL_ERR("Failed to register hw (error %d)\n", ret);
2218 return ret;
2219 }
2220 il->mac80211_registered = 1;
2221
2222 return 0;
2223}
2224
2225
2226int il4965_mac_start(struct ieee80211_hw *hw)
2227{
2228 struct il_priv *il = hw->priv;
2229 int ret;
2230
2231 D_MAC80211("enter\n");
2232
2233 /* we should be verifying the device is ready to be opened */
2234 mutex_lock(&il->mutex);
2235 ret = __il4965_up(il);
2236 mutex_unlock(&il->mutex);
2237
2238 if (ret)
2239 return ret;
2240
2241 if (il_is_rfkill(il))
2242 goto out;
2243
2244 D_INFO("Start UP work done.\n");
2245
2246 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2247 * mac80211 will not be run successfully. */
2248 ret = wait_event_timeout(il->wait_command_queue,
2249 test_bit(STATUS_READY, &il->status),
2250 UCODE_READY_TIMEOUT);
2251 if (!ret) {
2252 if (!test_bit(STATUS_READY, &il->status)) {
2253 IL_ERR("START_ALIVE timeout after %dms.\n",
2254 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2255 return -ETIMEDOUT;
2256 }
2257 }
2258
2259 il4965_led_enable(il);
2260
2261out:
2262 il->is_open = 1;
2263 D_MAC80211("leave\n");
2264 return 0;
2265}
2266
2267void il4965_mac_stop(struct ieee80211_hw *hw)
2268{
2269 struct il_priv *il = hw->priv;
2270
2271 D_MAC80211("enter\n");
2272
2273 if (!il->is_open)
2274 return;
2275
2276 il->is_open = 0;
2277
2278 il4965_down(il);
2279
2280 flush_workqueue(il->workqueue);
2281
2282 /* User space software may expect getting rfkill changes
2283 * even if interface is down */
2284 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2285 il_enable_rfkill_int(il);
2286
2287 D_MAC80211("leave\n");
2288}
2289
2290void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2291{
2292 struct il_priv *il = hw->priv;
2293
2294 D_MACDUMP("enter\n");
2295
2296 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2297 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2298
2299 if (il4965_tx_skb(il, skb))
2300 dev_kfree_skb_any(skb);
2301
2302 D_MACDUMP("leave\n");
2303}
2304
2305void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
2306 struct ieee80211_vif *vif,
2307 struct ieee80211_key_conf *keyconf,
2308 struct ieee80211_sta *sta,
2309 u32 iv32, u16 *phase1key)
2310{
2311 struct il_priv *il = hw->priv;
2312 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2313
2314 D_MAC80211("enter\n");
2315
2316 il4965_update_tkip_key(il, vif_priv->ctx, keyconf, sta,
2317 iv32, phase1key);
2318
2319 D_MAC80211("leave\n");
2320}
2321
2322int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2323 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2324 struct ieee80211_key_conf *key)
2325{
2326 struct il_priv *il = hw->priv;
2327 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2328 struct il_rxon_context *ctx = vif_priv->ctx;
2329 int ret;
2330 u8 sta_id;
2331 bool is_default_wep_key = false;
2332
2333 D_MAC80211("enter\n");
2334
2335 if (il->cfg->mod_params->sw_crypto) {
2336 D_MAC80211("leave - hwcrypto disabled\n");
2337 return -EOPNOTSUPP;
2338 }
2339
2340 sta_id = il_sta_id_or_broadcast(il, vif_priv->ctx, sta);
2341 if (sta_id == IL_INVALID_STATION)
2342 return -EINVAL;
2343
2344 mutex_lock(&il->mutex);
2345 il_scan_cancel_timeout(il, 100);
2346
2347 /*
2348 * If we are getting WEP group key and we didn't receive any key mapping
2349 * so far, we are in legacy wep mode (group key only), otherwise we are
2350 * in 1X mode.
2351 * In legacy wep mode, we use another host command to the uCode.
2352 */
2353 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2354 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2355 !sta) {
2356 if (cmd == SET_KEY)
2357 is_default_wep_key = !ctx->key_mapping_keys;
2358 else
2359 is_default_wep_key =
2360 (key->hw_key_idx == HW_KEY_DEFAULT);
2361 }
2362
2363 switch (cmd) {
2364 case SET_KEY:
2365 if (is_default_wep_key)
2366 ret = il4965_set_default_wep_key(il,
2367 vif_priv->ctx, key);
2368 else
2369 ret = il4965_set_dynamic_key(il, vif_priv->ctx,
2370 key, sta_id);
2371
2372 D_MAC80211("enable hwcrypto key\n");
2373 break;
2374 case DISABLE_KEY:
2375 if (is_default_wep_key)
2376 ret = il4965_remove_default_wep_key(il, ctx, key);
2377 else
2378 ret = il4965_remove_dynamic_key(il, ctx,
2379 key, sta_id);
2380
2381 D_MAC80211("disable hwcrypto key\n");
2382 break;
2383 default:
2384 ret = -EINVAL;
2385 }
2386
2387 mutex_unlock(&il->mutex);
2388 D_MAC80211("leave\n");
2389
2390 return ret;
2391}
2392
2393int il4965_mac_ampdu_action(struct ieee80211_hw *hw,
2394 struct ieee80211_vif *vif,
2395 enum ieee80211_ampdu_mlme_action action,
2396 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2397 u8 buf_size)
2398{
2399 struct il_priv *il = hw->priv;
2400 int ret = -EINVAL;
2401
2402 D_HT("A-MPDU action on addr %pM tid %d\n",
2403 sta->addr, tid);
2404
2405 if (!(il->cfg->sku & IL_SKU_N))
2406 return -EACCES;
2407
2408 mutex_lock(&il->mutex);
2409
2410 switch (action) {
2411 case IEEE80211_AMPDU_RX_START:
2412 D_HT("start Rx\n");
2413 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
2414 break;
2415 case IEEE80211_AMPDU_RX_STOP:
2416 D_HT("stop Rx\n");
2417 ret = il4965_sta_rx_agg_stop(il, sta, tid);
2418 if (test_bit(STATUS_EXIT_PENDING, &il->status))
2419 ret = 0;
2420 break;
2421 case IEEE80211_AMPDU_TX_START:
2422 D_HT("start Tx\n");
2423 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
2424 break;
2425 case IEEE80211_AMPDU_TX_STOP:
2426 D_HT("stop Tx\n");
2427 ret = il4965_tx_agg_stop(il, vif, sta, tid);
2428 if (test_bit(STATUS_EXIT_PENDING, &il->status))
2429 ret = 0;
2430 break;
2431 case IEEE80211_AMPDU_TX_OPERATIONAL:
2432 ret = 0;
2433 break;
2434 }
2435 mutex_unlock(&il->mutex);
2436
2437 return ret;
2438}
2439
2440int il4965_mac_sta_add(struct ieee80211_hw *hw,
2441 struct ieee80211_vif *vif,
2442 struct ieee80211_sta *sta)
2443{
2444 struct il_priv *il = hw->priv;
2445 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
2446 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2447 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2448 int ret;
2449 u8 sta_id;
2450
2451 D_INFO("received request to add station %pM\n",
2452 sta->addr);
2453 mutex_lock(&il->mutex);
2454 D_INFO("proceeding to add station %pM\n",
2455 sta->addr);
2456 sta_priv->common.sta_id = IL_INVALID_STATION;
2457
2458 atomic_set(&sta_priv->pending_frames, 0);
2459
2460 ret = il_add_station_common(il, vif_priv->ctx, sta->addr,
2461 is_ap, sta, &sta_id);
2462 if (ret) {
2463 IL_ERR("Unable to add station %pM (%d)\n",
2464 sta->addr, ret);
2465 /* Should we return success if return code is EEXIST ? */
2466 mutex_unlock(&il->mutex);
2467 return ret;
2468 }
2469
2470 sta_priv->common.sta_id = sta_id;
2471
2472 /* Initialize rate scaling */
2473 D_INFO("Initializing rate scaling for station %pM\n",
2474 sta->addr);
2475 il4965_rs_rate_init(il, sta, sta_id);
2476 mutex_unlock(&il->mutex);
2477
2478 return 0;
2479}
2480
2481void il4965_mac_channel_switch(struct ieee80211_hw *hw,
2482 struct ieee80211_channel_switch *ch_switch)
2483{
2484 struct il_priv *il = hw->priv;
2485 const struct il_channel_info *ch_info;
2486 struct ieee80211_conf *conf = &hw->conf;
2487 struct ieee80211_channel *channel = ch_switch->channel;
2488 struct il_ht_config *ht_conf = &il->current_ht_config;
2489
2490 struct il_rxon_context *ctx = &il->ctx;
2491 u16 ch;
2492
2493 D_MAC80211("enter\n");
2494
2495 mutex_lock(&il->mutex);
2496
2497 if (il_is_rfkill(il))
2498 goto out;
2499
2500 if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
2501 test_bit(STATUS_SCANNING, &il->status) ||
2502 test_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status))
2503 goto out;
2504
2505 if (!il_is_associated_ctx(ctx))
2506 goto out;
2507
2508 if (!il->cfg->ops->lib->set_channel_switch)
2509 goto out;
2510
2511 ch = channel->hw_value;
2512 if (le16_to_cpu(ctx->active.channel) == ch)
2513 goto out;
2514
2515 ch_info = il_get_channel_info(il, channel->band, ch);
2516 if (!il_is_channel_valid(ch_info)) {
2517 D_MAC80211("invalid channel\n");
2518 goto out;
2519 }
2520
2521 spin_lock_irq(&il->lock);
2522
2523 il->current_ht_config.smps = conf->smps_mode;
2524
2525 /* Configure HT40 channels */
2526 ctx->ht.enabled = conf_is_ht(conf);
2527 if (ctx->ht.enabled) {
2528 if (conf_is_ht40_minus(conf)) {
2529 ctx->ht.extension_chan_offset =
2530 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2531 ctx->ht.is_40mhz = true;
2532 } else if (conf_is_ht40_plus(conf)) {
2533 ctx->ht.extension_chan_offset =
2534 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2535 ctx->ht.is_40mhz = true;
2536 } else {
2537 ctx->ht.extension_chan_offset =
2538 IEEE80211_HT_PARAM_CHA_SEC_NONE;
2539 ctx->ht.is_40mhz = false;
2540 }
2541 } else
2542 ctx->ht.is_40mhz = false;
2543
2544 if ((le16_to_cpu(ctx->staging.channel) != ch))
2545 ctx->staging.flags = 0;
2546
2547 il_set_rxon_channel(il, channel, ctx);
2548 il_set_rxon_ht(il, ht_conf);
2549 il_set_flags_for_band(il, ctx, channel->band, ctx->vif);
2550
2551 spin_unlock_irq(&il->lock);
2552
2553 il_set_rate(il);
2554 /*
2555 * at this point, staging_rxon has the
2556 * configuration for channel switch
2557 */
2558 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status);
2559 il->switch_channel = cpu_to_le16(ch);
2560 if (il->cfg->ops->lib->set_channel_switch(il, ch_switch)) {
2561 clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status);
2562 il->switch_channel = 0;
2563 ieee80211_chswitch_done(ctx->vif, false);
2564 }
2565
2566out:
2567 mutex_unlock(&il->mutex);
2568 D_MAC80211("leave\n");
2569}
2570
2571void il4965_configure_filter(struct ieee80211_hw *hw,
2572 unsigned int changed_flags,
2573 unsigned int *total_flags,
2574 u64 multicast)
2575{
2576 struct il_priv *il = hw->priv;
2577 __le32 filter_or = 0, filter_nand = 0;
2578
2579#define CHK(test, flag) do { \
2580 if (*total_flags & (test)) \
2581 filter_or |= (flag); \
2582 else \
2583 filter_nand |= (flag); \
2584 } while (0)
2585
2586 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
2587 changed_flags, *total_flags);
2588
2589 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
2590 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
2591 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
2592 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
2593
2594#undef CHK
2595
2596 mutex_lock(&il->mutex);
2597
2598 il->ctx.staging.filter_flags &= ~filter_nand;
2599 il->ctx.staging.filter_flags |= filter_or;
2600
2601 /*
2602 * Not committing directly because hardware can perform a scan,
2603 * but we'll eventually commit the filter flags change anyway.
2604 */
2605
2606 mutex_unlock(&il->mutex);
2607
2608 /*
2609 * Receiving all multicast frames is always enabled by the
2610 * default flags setup in il_connection_init_rx_config()
2611 * since we currently do not support programming multicast
2612 * filters into the device.
2613 */
2614 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
2615 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
2616}
2617
2618/*****************************************************************************
2619 *
2620 * driver setup and teardown
2621 *
2622 *****************************************************************************/
2623
2624static void il4965_bg_txpower_work(struct work_struct *work)
2625{
2626 struct il_priv *il = container_of(work, struct il_priv,
2627 txpower_work);
2628
2629 mutex_lock(&il->mutex);
2630
2631 /* If a scan happened to start before we got here
2632 * then just return; the stats notification will
2633 * kick off another scheduled work to compensate for
2634 * any temperature delta we missed here. */
2635 if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
2636 test_bit(STATUS_SCANNING, &il->status))
2637 goto out;
2638
2639 /* Regardless of if we are associated, we must reconfigure the
2640 * TX power since frames can be sent on non-radar channels while
2641 * not associated */
2642 il->cfg->ops->lib->send_tx_power(il);
2643
2644 /* Update last_temperature to keep is_calib_needed from running
2645 * when it isn't needed... */
2646 il->last_temperature = il->temperature;
2647out:
2648 mutex_unlock(&il->mutex);
2649}
2650
2651static void il4965_setup_deferred_work(struct il_priv *il)
2652{
2653 il->workqueue = create_singlethread_workqueue(DRV_NAME);
2654
2655 init_waitqueue_head(&il->wait_command_queue);
2656
2657 INIT_WORK(&il->restart, il4965_bg_restart);
2658 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
2659 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
2660 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
2661 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
2662
2663 il_setup_scan_deferred_work(il);
2664
2665 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
2666
2667 init_timer(&il->stats_periodic);
2668 il->stats_periodic.data = (unsigned long)il;
2669 il->stats_periodic.function = il4965_bg_stats_periodic;
2670
2671 init_timer(&il->watchdog);
2672 il->watchdog.data = (unsigned long)il;
2673 il->watchdog.function = il_bg_watchdog;
2674
2675 tasklet_init(&il->irq_tasklet, (void (*)(unsigned long))
2676 il4965_irq_tasklet, (unsigned long)il);
2677}
2678
2679static void il4965_cancel_deferred_work(struct il_priv *il)
2680{
2681 cancel_work_sync(&il->txpower_work);
2682 cancel_delayed_work_sync(&il->init_alive_start);
2683 cancel_delayed_work(&il->alive_start);
2684 cancel_work_sync(&il->run_time_calib_work);
2685
2686 il_cancel_scan_deferred_work(il);
2687
2688 del_timer_sync(&il->stats_periodic);
2689}
2690
2691static void il4965_init_hw_rates(struct il_priv *il,
2692 struct ieee80211_rate *rates)
2693{
2694 int i;
2695
2696 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
2697 rates[i].bitrate = il_rates[i].ieee * 5;
2698 rates[i].hw_value = i; /* Rate scaling will work on idxes */
2699 rates[i].hw_value_short = i;
2700 rates[i].flags = 0;
2701 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
2702 /*
2703 * If CCK != 1M then set short preamble rate flag.
2704 */
2705 rates[i].flags |=
2706 (il_rates[i].plcp == RATE_1M_PLCP) ?
2707 0 : IEEE80211_RATE_SHORT_PREAMBLE;
2708 }
2709 }
2710}
2711/*
2712 * Acquire il->lock before calling this function !
2713 */
2714void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
2715{
2716 il_wr(il, HBUS_TARG_WRPTR,
2717 (idx & 0xff) | (txq_id << 8));
2718 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
2719}
2720
2721void il4965_tx_queue_set_status(struct il_priv *il,
2722 struct il_tx_queue *txq,
2723 int tx_fifo_id, int scd_retry)
2724{
2725 int txq_id = txq->q.id;
2726
2727 /* Find out whether to activate Tx queue */
2728 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
2729
2730 /* Set up and activate */
2731 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2732 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2733 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
2734 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
2735 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
2736 IL49_SCD_QUEUE_STTS_REG_MSK);
2737
2738 txq->sched_retry = scd_retry;
2739
2740 D_INFO("%s %s Queue %d on AC %d\n",
2741 active ? "Activate" : "Deactivate",
2742 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
2743}
2744
2745
2746static int il4965_init_drv(struct il_priv *il)
2747{
2748 int ret;
2749
2750 spin_lock_init(&il->sta_lock);
2751 spin_lock_init(&il->hcmd_lock);
2752
2753 INIT_LIST_HEAD(&il->free_frames);
2754
2755 mutex_init(&il->mutex);
2756
2757 il->ieee_channels = NULL;
2758 il->ieee_rates = NULL;
2759 il->band = IEEE80211_BAND_2GHZ;
2760
2761 il->iw_mode = NL80211_IFTYPE_STATION;
2762 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
2763 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
2764
2765 /* initialize force reset */
2766 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
2767
2768 /* Choose which receivers/antennas to use */
2769 if (il->cfg->ops->hcmd->set_rxon_chain)
2770 il->cfg->ops->hcmd->set_rxon_chain(il,
2771 &il->ctx);
2772
2773 il_init_scan_params(il);
2774
2775 ret = il_init_channel_map(il);
2776 if (ret) {
2777 IL_ERR("initializing regulatory failed: %d\n", ret);
2778 goto err;
2779 }
2780
2781 ret = il_init_geos(il);
2782 if (ret) {
2783 IL_ERR("initializing geos failed: %d\n", ret);
2784 goto err_free_channel_map;
2785 }
2786 il4965_init_hw_rates(il, il->ieee_rates);
2787
2788 return 0;
2789
2790err_free_channel_map:
2791 il_free_channel_map(il);
2792err:
2793 return ret;
2794}
2795
2796static void il4965_uninit_drv(struct il_priv *il)
2797{
2798 il4965_calib_free_results(il);
2799 il_free_geos(il);
2800 il_free_channel_map(il);
2801 kfree(il->scan_cmd);
2802}
2803
2804static void il4965_hw_detect(struct il_priv *il)
2805{
2806 il->hw_rev = _il_rd(il, CSR_HW_REV);
2807 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
2808 il->rev_id = il->pci_dev->revision;
2809 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
2810}
2811
2812static int il4965_set_hw_params(struct il_priv *il)
2813{
2814 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2815 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2816 if (il->cfg->mod_params->amsdu_size_8K)
2817 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
2818 else
2819 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
2820
2821 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
2822
2823 if (il->cfg->mod_params->disable_11n)
2824 il->cfg->sku &= ~IL_SKU_N;
2825
2826 /* Device-specific setup */
2827 return il->cfg->ops->lib->set_hw_params(il);
2828}
2829
2830static const u8 il4965_bss_ac_to_fifo[] = {
2831 IL_TX_FIFO_VO,
2832 IL_TX_FIFO_VI,
2833 IL_TX_FIFO_BE,
2834 IL_TX_FIFO_BK,
2835};
2836
2837static const u8 il4965_bss_ac_to_queue[] = {
2838 0, 1, 2, 3,
2839};
2840
2841static int
2842il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2843{
2844 int err = 0;
2845 struct il_priv *il;
2846 struct ieee80211_hw *hw;
2847 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
2848 unsigned long flags;
2849 u16 pci_cmd;
2850
2851 /************************
2852 * 1. Allocating HW data
2853 ************************/
2854
2855 hw = il_alloc_all(cfg);
2856 if (!hw) {
2857 err = -ENOMEM;
2858 goto out;
2859 }
2860 il = hw->priv;
2861 /* At this point both hw and il are allocated. */
2862
2863 il->ctx.ctxid = 0;
2864
2865 il->ctx.always_active = true;
2866 il->ctx.is_active = true;
2867 il->ctx.rxon_cmd = REPLY_RXON;
2868 il->ctx.rxon_timing_cmd = REPLY_RXON_TIMING;
2869 il->ctx.rxon_assoc_cmd = REPLY_RXON_ASSOC;
2870 il->ctx.qos_cmd = REPLY_QOS_PARAM;
2871 il->ctx.ap_sta_id = IL_AP_ID;
2872 il->ctx.wep_key_cmd = REPLY_WEPKEY;
2873 il->ctx.ac_to_fifo = il4965_bss_ac_to_fifo;
2874 il->ctx.ac_to_queue = il4965_bss_ac_to_queue;
2875 il->ctx.exclusive_interface_modes =
2876 BIT(NL80211_IFTYPE_ADHOC);
2877 il->ctx.interface_modes =
2878 BIT(NL80211_IFTYPE_STATION);
2879 il->ctx.ap_devtype = RXON_DEV_TYPE_AP;
2880 il->ctx.ibss_devtype = RXON_DEV_TYPE_IBSS;
2881 il->ctx.station_devtype = RXON_DEV_TYPE_ESS;
2882 il->ctx.unused_devtype = RXON_DEV_TYPE_ESS;
2883
2884 SET_IEEE80211_DEV(hw, &pdev->dev);
2885
2886 D_INFO("*** LOAD DRIVER ***\n");
2887 il->cfg = cfg;
2888 il->pci_dev = pdev;
2889 il->inta_mask = CSR_INI_SET_MASK;
2890
2891 if (il_alloc_traffic_mem(il))
2892 IL_ERR("Not enough memory to generate traffic log\n");
2893
2894 /**************************
2895 * 2. Initializing PCI bus
2896 **************************/
2897 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2898 PCIE_LINK_STATE_CLKPM);
2899
2900 if (pci_enable_device(pdev)) {
2901 err = -ENODEV;
2902 goto out_ieee80211_free_hw;
2903 }
2904
2905 pci_set_master(pdev);
2906
2907 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2908 if (!err)
2909 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2910 if (err) {
2911 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2912 if (!err)
2913 err = pci_set_consistent_dma_mask(pdev,
2914 DMA_BIT_MASK(32));
2915 /* both attempts failed: */
2916 if (err) {
2917 IL_WARN("No suitable DMA available.\n");
2918 goto out_pci_disable_device;
2919 }
2920 }
2921
2922 err = pci_request_regions(pdev, DRV_NAME);
2923 if (err)
2924 goto out_pci_disable_device;
2925
2926 pci_set_drvdata(pdev, il);
2927
2928
2929 /***********************
2930 * 3. Read REV register
2931 ***********************/
2932 il->hw_base = pci_iomap(pdev, 0, 0);
2933 if (!il->hw_base) {
2934 err = -ENODEV;
2935 goto out_pci_release_regions;
2936 }
2937
2938 D_INFO("pci_resource_len = 0x%08llx\n",
2939 (unsigned long long) pci_resource_len(pdev, 0));
2940 D_INFO("pci_resource_base = %p\n", il->hw_base);
2941
2942 /* these spin locks will be used in apm_ops.init and EEPROM access
2943 * we should init now
2944 */
2945 spin_lock_init(&il->reg_lock);
2946 spin_lock_init(&il->lock);
2947
2948 /*
2949 * stop and reset the on-board processor just in case it is in a
2950 * strange state ... like being left stranded by a primary kernel
2951 * and this is now the kdump kernel trying to start up
2952 */
2953 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2954
2955 il4965_hw_detect(il);
2956 IL_INFO("Detected %s, REV=0x%X\n",
2957 il->cfg->name, il->hw_rev);
2958
2959 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2960 * PCI Tx retries from interfering with C3 CPU state */
2961 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2962
2963 il4965_prepare_card_hw(il);
2964 if (!il->hw_ready) {
2965 IL_WARN("Failed, HW not ready\n");
2966 goto out_iounmap;
2967 }
2968
2969 /*****************
2970 * 4. Read EEPROM
2971 *****************/
2972 /* Read the EEPROM */
2973 err = il_eeprom_init(il);
2974 if (err) {
2975 IL_ERR("Unable to init EEPROM\n");
2976 goto out_iounmap;
2977 }
2978 err = il4965_eeprom_check_version(il);
2979 if (err)
2980 goto out_free_eeprom;
2981
2982 if (err)
2983 goto out_free_eeprom;
2984
2985 /* extract MAC Address */
2986 il4965_eeprom_get_mac(il, il->addresses[0].addr);
2987 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
2988 il->hw->wiphy->addresses = il->addresses;
2989 il->hw->wiphy->n_addresses = 1;
2990
2991 /************************
2992 * 5. Setup HW constants
2993 ************************/
2994 if (il4965_set_hw_params(il)) {
2995 IL_ERR("failed to set hw parameters\n");
2996 goto out_free_eeprom;
2997 }
2998
2999 /*******************
3000 * 6. Setup il
3001 *******************/
3002
3003 err = il4965_init_drv(il);
3004 if (err)
3005 goto out_free_eeprom;
3006 /* At this point both hw and il are initialized. */
3007
3008 /********************
3009 * 7. Setup services
3010 ********************/
3011 spin_lock_irqsave(&il->lock, flags);
3012 il_disable_interrupts(il);
3013 spin_unlock_irqrestore(&il->lock, flags);
3014
3015 pci_enable_msi(il->pci_dev);
3016
3017 err = request_irq(il->pci_dev->irq, il_isr,
3018 IRQF_SHARED, DRV_NAME, il);
3019 if (err) {
3020 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3021 goto out_disable_msi;
3022 }
3023
3024 il4965_setup_deferred_work(il);
3025 il4965_setup_rx_handlers(il);
3026
3027 /*********************************************
3028 * 8. Enable interrupts and read RFKILL state
3029 *********************************************/
3030
3031 /* enable rfkill interrupt: hw bug w/a */
3032 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
3033 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3034 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3035 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
3036 }
3037
3038 il_enable_rfkill_int(il);
3039
3040 /* If platform's RF_KILL switch is NOT set to KILL */
3041 if (_il_rd(il, CSR_GP_CNTRL) &
3042 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3043 clear_bit(STATUS_RF_KILL_HW, &il->status);
3044 else
3045 set_bit(STATUS_RF_KILL_HW, &il->status);
3046
3047 wiphy_rfkill_set_hw_state(il->hw->wiphy,
3048 test_bit(STATUS_RF_KILL_HW, &il->status));
3049
3050 il_power_initialize(il);
3051
3052 init_completion(&il->_4965.firmware_loading_complete);
3053
3054 err = il4965_request_firmware(il, true);
3055 if (err)
3056 goto out_destroy_workqueue;
3057
3058 return 0;
3059
3060 out_destroy_workqueue:
3061 destroy_workqueue(il->workqueue);
3062 il->workqueue = NULL;
3063 free_irq(il->pci_dev->irq, il);
3064 out_disable_msi:
3065 pci_disable_msi(il->pci_dev);
3066 il4965_uninit_drv(il);
3067 out_free_eeprom:
3068 il_eeprom_free(il);
3069 out_iounmap:
3070 pci_iounmap(pdev, il->hw_base);
3071 out_pci_release_regions:
3072 pci_set_drvdata(pdev, NULL);
3073 pci_release_regions(pdev);
3074 out_pci_disable_device:
3075 pci_disable_device(pdev);
3076 out_ieee80211_free_hw:
3077 il_free_traffic_mem(il);
3078 ieee80211_free_hw(il->hw);
3079 out:
3080 return err;
3081}
3082
3083static void __devexit il4965_pci_remove(struct pci_dev *pdev)
3084{
3085 struct il_priv *il = pci_get_drvdata(pdev);
3086 unsigned long flags;
3087
3088 if (!il)
3089 return;
3090
3091 wait_for_completion(&il->_4965.firmware_loading_complete);
3092
3093 D_INFO("*** UNLOAD DRIVER ***\n");
3094
3095 il_dbgfs_unregister(il);
3096 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
3097
3098 /* ieee80211_unregister_hw call wil cause il_mac_stop to
3099 * to be called and il4965_down since we are removing the device
3100 * we need to set STATUS_EXIT_PENDING bit.
3101 */
3102 set_bit(STATUS_EXIT_PENDING, &il->status);
3103
3104 il_leds_exit(il);
3105
3106 if (il->mac80211_registered) {
3107 ieee80211_unregister_hw(il->hw);
3108 il->mac80211_registered = 0;
3109 } else {
3110 il4965_down(il);
3111 }
3112
3113 /*
3114 * Make sure device is reset to low power before unloading driver.
3115 * This may be redundant with il4965_down(), but there are paths to
3116 * run il4965_down() without calling apm_ops.stop(), and there are
3117 * paths to avoid running il4965_down() at all before leaving driver.
3118 * This (inexpensive) call *makes sure* device is reset.
3119 */
3120 il_apm_stop(il);
3121
3122 /* make sure we flush any pending irq or
3123 * tasklet for the driver
3124 */
3125 spin_lock_irqsave(&il->lock, flags);
3126 il_disable_interrupts(il);
3127 spin_unlock_irqrestore(&il->lock, flags);
3128
3129 il4965_synchronize_irq(il);
3130
3131 il4965_dealloc_ucode_pci(il);
3132
3133 if (il->rxq.bd)
3134 il4965_rx_queue_free(il, &il->rxq);
3135 il4965_hw_txq_ctx_free(il);
3136
3137 il_eeprom_free(il);
3138
3139
3140 /*netif_stop_queue(dev); */
3141 flush_workqueue(il->workqueue);
3142
3143 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
3144 * il->workqueue... so we can't take down the workqueue
3145 * until now... */
3146 destroy_workqueue(il->workqueue);
3147 il->workqueue = NULL;
3148 il_free_traffic_mem(il);
3149
3150 free_irq(il->pci_dev->irq, il);
3151 pci_disable_msi(il->pci_dev);
3152 pci_iounmap(pdev, il->hw_base);
3153 pci_release_regions(pdev);
3154 pci_disable_device(pdev);
3155 pci_set_drvdata(pdev, NULL);
3156
3157 il4965_uninit_drv(il);
3158
3159 dev_kfree_skb(il->beacon_skb);
3160
3161 ieee80211_free_hw(il->hw);
3162}
3163
3164/*
3165 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
3166 * must be called under il->lock and mac access
3167 */
3168void il4965_txq_set_sched(struct il_priv *il, u32 mask)
3169{
3170 il_wr_prph(il, IL49_SCD_TXFACT, mask);
3171}
3172
3173/*****************************************************************************
3174 *
3175 * driver and module entry point
3176 *
3177 *****************************************************************************/
3178
3179/* Hardware specific file defines the PCI IDs table for that hardware module */
3180static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
3181 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
3182 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
3183 {0}
3184};
3185MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
3186
3187static struct pci_driver il4965_driver = {
3188 .name = DRV_NAME,
3189 .id_table = il4965_hw_card_ids,
3190 .probe = il4965_pci_probe,
3191 .remove = __devexit_p(il4965_pci_remove),
3192 .driver.pm = IL_LEGACY_PM_OPS,
3193};
3194
3195static int __init il4965_init(void)
3196{
3197
3198 int ret;
3199 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3200 pr_info(DRV_COPYRIGHT "\n");
3201
3202 ret = il4965_rate_control_register();
3203 if (ret) {
3204 pr_err("Unable to register rate control algorithm: %d\n", ret);
3205 return ret;
3206 }
3207
3208 ret = pci_register_driver(&il4965_driver);
3209 if (ret) {
3210 pr_err("Unable to initialize PCI module\n");
3211 goto error_register;
3212 }
3213
3214 return ret;
3215
3216error_register:
3217 il4965_rate_control_unregister();
3218 return ret;
3219}
3220
3221static void __exit il4965_exit(void)
3222{
3223 pci_unregister_driver(&il4965_driver);
3224 il4965_rate_control_unregister();
3225}
3226
3227module_exit(il4965_exit);
3228module_init(il4965_init);
3229
3230#ifdef CONFIG_IWLEGACY_DEBUG
3231module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
3232MODULE_PARM_DESC(debug, "debug output mask");
3233#endif
3234
3235module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
3236MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
3237module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
3238MODULE_PARM_DESC(queues_num, "number of hw queues.");
3239module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
3240MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
3241module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K,
3242 int, S_IRUGO);
3243MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3244module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
3245MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 07:30:57 -0400