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diff --git a/drivers/net/wireless/bcm4329/siutils_priv.h b/drivers/net/wireless/bcm4329/siutils_priv.h
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1/*
2 * Include file private to the SOC Interconnect support files.
3 *
4 * Copyright (C) 1999-2010, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 * $Id: siutils_priv.h,v 1.3.10.5.4.2 2009/09/22 13:28:16 Exp $
25 */
26
27#ifndef _siutils_priv_h_
28#define _siutils_priv_h_
29
30/* debug/trace */
31#define SI_ERROR(args)
32
33#define SI_MSG(args)
34
35#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
36
37typedef uint32 (*si_intrsoff_t)(void *intr_arg);
38typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
39typedef bool (*si_intrsenabled_t)(void *intr_arg);
40
41typedef struct gpioh_item {
42 void *arg;
43 bool level;
44 gpio_handler_t handler;
45 uint32 event;
46 struct gpioh_item *next;
47} gpioh_item_t;
48
49/* misc si info needed by some of the routines */
50typedef struct si_common_info {
51 void *regs[SI_MAXCORES]; /* other regs va */
52 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
53 uint coreid[SI_MAXCORES]; /* id of each core */
54 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
55 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
56 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
57 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
58 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
59 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
60 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
61 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
62 uint32 oob_router; /* oob router registers for axi */
63 uint8 attach_count;
64} si_common_info_t;
65
66typedef struct si_info {
67 struct si_pub pub; /* back plane public state (must be first field) */
68
69 void *osh; /* osl os handle */
70 void *sdh; /* bcmsdh handle */
71 void *pch; /* PCI/E core handle */
72 uint dev_coreid; /* the core provides driver functions */
73 void *intr_arg; /* interrupt callback function arg */
74 si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
75 si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
76 si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
77
78
79 gpioh_item_t *gpioh_head; /* GPIO event handlers list */
80
81 bool memseg; /* flag to toggle MEM_SEG register */
82
83 char *vars;
84 uint varsz;
85
86 void *curmap; /* current regs va */
87
88 uint curidx; /* current core index */
89 uint numcores; /* # discovered cores */
90 void *curwrap; /* current wrapper va */
91 si_common_info_t *common_info; /* Common information for all the cores in a chip */
92} si_info_t;
93
94#define SI_INFO(sih) (si_info_t *)(uintptr)sih
95
96#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
97 ISALIGNED((x), SI_CORE_SIZE))
98#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
99#define BADCOREADDR 0
100#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
101#define BADIDX (SI_MAXCORES + 1)
102#define NOREV -1 /* Invalid rev */
103
104#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
105 ((si)->pub.buscoretype == PCI_CORE_ID))
106#define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
107 ((si)->pub.buscoretype == PCIE_CORE_ID))
108#define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
109
110/* Newer chips can access PCI/PCIE and CC core without requiring to change
111 * PCI BAR0 WIN
112 */
113#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
114 (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
115
116#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
117#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
118
119/*
120 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
121 * after core switching to avoid invalid register accesss inside ISR.
122 */
123#define INTR_OFF(si, intr_val) \
124 if ((si)->intrsoff_fn && (si)->common_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
125 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
126#define INTR_RESTORE(si, intr_val) \
127 if ((si)->intrsrestore_fn && (si)->common_info->coreid[(si)->curidx] == (si)->dev_coreid) {\
128 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
129
130/* dynamic clock control defines */
131#define LPOMINFREQ 25000 /* low power oscillator min */
132#define LPOMAXFREQ 43000 /* low power oscillator max */
133#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
134#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
135#define PCIMINFREQ 25000000 /* 25 MHz */
136#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
137
138#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
139#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
140
141#define PCI_FORCEHT(si) \
142 (((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
143 ((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)))
144
145/* GPIO Based LED powersave defines */
146#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
147#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
148
149#ifndef DEFAULT_GPIOTIMERVAL
150#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
151#endif
152
153/* Silicon Backplane externs */
154extern void sb_scan(si_t *sih, void *regs, uint devid);
155extern uint sb_coreid(si_t *sih);
156extern uint sb_flag(si_t *sih);
157extern void sb_setint(si_t *sih, int siflag);
158extern uint sb_corevendor(si_t *sih);
159extern uint sb_corerev(si_t *sih);
160extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
161extern bool sb_iscoreup(si_t *sih);
162extern void *sb_setcoreidx(si_t *sih, uint coreidx);
163extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
164extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
165extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
166extern void sb_commit(si_t *sih);
167extern uint32 sb_base(uint32 admatch);
168extern uint32 sb_size(uint32 admatch);
169extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
170extern void sb_core_tofixup(si_t *sih);
171extern void sb_core_disable(si_t *sih, uint32 bits);
172extern uint32 sb_addrspace(si_t *sih, uint asidx);
173extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
174extern int sb_numaddrspaces(si_t *sih);
175
176extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
177
178
179
180/* Wake-on-wireless-LAN (WOWL) */
181extern bool sb_pci_pmecap(si_t *sih);
182struct osl_info;
183extern bool sb_pci_fastpmecap(struct osl_info *osh);
184extern bool sb_pci_pmeclr(si_t *sih);
185extern void sb_pci_pmeen(si_t *sih);
186extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
187
188/* AMBA Interconnect exported externs */
189extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
190 void *sdh, char **vars, uint *varsz);
191extern si_t *ai_kattach(osl_t *osh);
192extern void ai_scan(si_t *sih, void *regs, uint devid);
193
194extern uint ai_flag(si_t *sih);
195extern void ai_setint(si_t *sih, int siflag);
196extern uint ai_coreidx(si_t *sih);
197extern uint ai_corevendor(si_t *sih);
198extern uint ai_corerev(si_t *sih);
199extern bool ai_iscoreup(si_t *sih);
200extern void *ai_setcoreidx(si_t *sih, uint coreidx);
201extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
202extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
203extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
204extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
205extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
206extern void ai_core_disable(si_t *sih, uint32 bits);
207extern int ai_numaddrspaces(si_t *sih);
208extern uint32 ai_addrspace(si_t *sih, uint asidx);
209extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
210extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val);
211
212
213#endif /* _siutils_priv_h_ */
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