aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/bcm4329/include/sbsdpcmdev.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/bcm4329/include/sbsdpcmdev.h')
-rw-r--r--drivers/net/wireless/bcm4329/include/sbsdpcmdev.h288
1 files changed, 288 insertions, 0 deletions
diff --git a/drivers/net/wireless/bcm4329/include/sbsdpcmdev.h b/drivers/net/wireless/bcm4329/include/sbsdpcmdev.h
new file mode 100644
index 00000000000..7c7c7e4de0f
--- /dev/null
+++ b/drivers/net/wireless/bcm4329/include/sbsdpcmdev.h
@@ -0,0 +1,288 @@
1/*
2 * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific device core support
3 *
4 * Copyright (C) 1999-2010, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 * $Id: sbsdpcmdev.h,v 13.29.4.1.4.6.6.2 2008/12/31 21:16:51 Exp $
25 */
26
27#ifndef _sbsdpcmdev_h_
28#define _sbsdpcmdev_h_
29
30/* cpp contortions to concatenate w/arg prescan */
31#ifndef PAD
32#define _PADLINE(line) pad ## line
33#define _XSTR(line) _PADLINE(line)
34#define PAD _XSTR(__LINE__)
35#endif /* PAD */
36
37
38typedef volatile struct {
39 dma64regs_t xmt; /* dma tx */
40 uint32 PAD[2];
41 dma64regs_t rcv; /* dma rx */
42 uint32 PAD[2];
43} dma64p_t;
44
45/* dma64 sdiod corerev >= 1 */
46typedef volatile struct {
47 dma64p_t dma64regs[2];
48 dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */
49 uint32 PAD[92];
50} sdiodma64_t;
51
52/* dma32 sdiod corerev == 0 */
53typedef volatile struct {
54 dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */
55 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */
56 uint32 PAD[108];
57} sdiodma32_t;
58
59/* dma32 regs for pcmcia core */
60typedef volatile struct {
61 dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */
62 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */
63 uint32 PAD[116];
64} pcmdma32_t;
65
66/* core registers */
67typedef volatile struct {
68 uint32 corecontrol; /* CoreControl, 0x000, rev8 */
69 uint32 corestatus; /* CoreStatus, 0x004, rev8 */
70 uint32 PAD[1];
71 uint32 biststatus; /* BistStatus, 0x00c, rev8 */
72
73 /* PCMCIA access */
74 uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */
75 uint16 PAD[1];
76 uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */
77 uint16 PAD[1];
78 uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */
79 uint16 PAD[1];
80 uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */
81 uint16 PAD[1];
82
83 /* interrupt */
84 uint32 intstatus; /* IntStatus, 0x020, rev8 */
85 uint32 hostintmask; /* IntHostMask, 0x024, rev8 */
86 uint32 intmask; /* IntSbMask, 0x028, rev8 */
87 uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */
88 uint32 sbintmask; /* SBIntMask, 0x030, rev8 */
89 uint32 PAD[3];
90 uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */
91 uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */
92 uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */
93 uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */
94
95 /* synchronized access to registers in SDIO clock domain */
96 uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */
97 uint32 PAD[3];
98
99 /* PCMCIA frame control */
100 uint8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */
101 uint8 PAD[3];
102 uint8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */
103 uint8 PAD[155];
104
105 /* interrupt batching control */
106 uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */
107 uint32 PAD[3];
108
109 /* counters */
110 uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
111 uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
112 uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
113 uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
114 uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
115 uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
116 uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
117 uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
118 uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
119 uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
120 uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
121 uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
122 uint32 PAD[40];
123 uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */
124 uint32 PAD[7];
125
126 /* DMA engines */
127 volatile union {
128 pcmdma32_t pcm32;
129 sdiodma32_t sdiod32;
130 sdiodma64_t sdiod64;
131 } dma;
132
133 /* SDIO/PCMCIA CIS region */
134 char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */
135
136 /* PCMCIA function control registers */
137 char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */
138 uint16 PAD[55];
139
140 /* PCMCIA backplane access */
141 uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */
142 uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */
143 uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */
144 uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */
145 uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */
146 uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */
147 uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */
148 uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */
149 uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */
150 uint16 PAD[31];
151
152 /* sprom "size" & "blank" info */
153 uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */
154 uint32 PAD[464];
155
156 /* Sonics SiliconBackplane registers */
157 sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */
158} sdpcmd_regs_t;
159
160/* corecontrol */
161#define CC_CISRDY (1 << 0) /* CIS Ready */
162#define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */
163#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
164#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */
165
166/* corestatus */
167#define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
168#define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
169#define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
170
171#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
172#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
173#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
174#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
175
176/* intstatus */
177#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
178#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
179#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
180#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
181#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
182#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
183#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
184#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
185#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
186#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
187#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
188#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
189#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
190#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
191#define I_PC (1 << 10) /* descriptor error */
192#define I_PD (1 << 11) /* data error */
193#define I_DE (1 << 12) /* Descriptor protocol Error */
194#define I_RU (1 << 13) /* Receive descriptor Underflow */
195#define I_RO (1 << 14) /* Receive fifo Overflow */
196#define I_XU (1 << 15) /* Transmit fifo Underflow */
197#define I_RI (1 << 16) /* Receive Interrupt */
198#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
199#define I_XI (1 << 24) /* Transmit Interrupt */
200#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
201#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
202#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
203#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
204#define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */
205#define I_SRESET (1 << 30) /* CCCR RES interrupt */
206#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
207#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */
208#define I_DMA (I_RI | I_XI | I_ERRORS)
209
210/* sbintstatus */
211#define I_SB_SERR (1 << 8) /* Backplane SError (write) */
212#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
213#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
214
215/* sdioaccess */
216#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
217#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
218#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
219#define SDA_WRITE 0x01000000 /* Write bit */
220#define SDA_READ 0x00000000 /* Write bit cleared for Read */
221#define SDA_BUSY 0x80000000 /* Busy bit */
222
223/* sdioaccess-accessible register address spaces */
224#define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */
225#define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */
226#define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */
227#define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */
228
229/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
230#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
231#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
232#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
233#define SDA_DEVICECONTROL 0x009 /* DeviceControl */
234#define SDA_SBADDRLOW 0x00a /* SbAddrLow */
235#define SDA_SBADDRMID 0x00b /* SbAddrMid */
236#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
237#define SDA_FRAMECTRL 0x00d /* FrameCtrl */
238#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
239#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
240#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
241#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
242#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
243#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
244
245/* SDA_F2WATERMARK */
246#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
247
248/* SDA_SBADDRLOW */
249#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
250
251/* SDA_SBADDRMID */
252#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
253
254/* SDA_SBADDRHIGH */
255#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
256
257/* SDA_FRAMECTRL */
258#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
259#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
260#define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */
261#define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */
262
263/* pcmciaframectrl */
264#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
265#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
266
267/* intrcvlazy */
268#define IRL_TO_MASK 0x00ffffff /* timeout */
269#define IRL_FC_MASK 0xff000000 /* frame count */
270#define IRL_FC_SHIFT 24 /* frame count */
271
272/* rx header */
273typedef volatile struct {
274 uint16 len;
275 uint16 flags;
276} sdpcmd_rxh_t;
277
278/* rx header flags */
279#define RXF_CRC 0x0001 /* CRC error detected */
280#define RXF_WOOS 0x0002 /* write frame out of sync */
281#define RXF_WF_TERM 0x0004 /* write frame terminated */
282#define RXF_ABORT 0x0008 /* write frame aborted */
283#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */
284
285/* HW frame tag */
286#define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */
287
288#endif /* _sbsdpcmdev_h_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-28 11:40:44 -0400