aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/bcm4329/bcmsdspi.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/bcm4329/bcmsdspi.c')
-rw-r--r--drivers/net/wireless/bcm4329/bcmsdspi.c1596
1 files changed, 1596 insertions, 0 deletions
diff --git a/drivers/net/wireless/bcm4329/bcmsdspi.c b/drivers/net/wireless/bcm4329/bcmsdspi.c
new file mode 100644
index 00000000000..636539be5ea
--- /dev/null
+++ b/drivers/net/wireless/bcm4329/bcmsdspi.c
@@ -0,0 +1,1596 @@
1/*
2 * Broadcom BCMSDH to SPI Protocol Conversion Layer
3 *
4 * Copyright (C) 1999-2010, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 * $Id: bcmsdspi.c,v 1.14.4.2.4.4.6.5 2010/03/10 03:09:48 Exp $
25 */
26
27#include <typedefs.h>
28
29#include <bcmdevs.h>
30#include <bcmendian.h>
31#include <bcmutils.h>
32#include <osl.h>
33#include <siutils.h>
34#include <sdio.h> /* SDIO Device and Protocol Specs */
35#include <sdioh.h> /* SDIO Host Controller Specification */
36#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
37#include <sdiovar.h> /* ioctl/iovars */
38
39#include <pcicfg.h>
40
41
42#include <bcmsdspi.h>
43#include <bcmspi.h>
44
45#include <proto/sdspi.h>
46
47#define SD_PAGE 4096
48
49/* Globals */
50
51uint sd_msglevel = SDH_ERROR_VAL;
52uint sd_hiok = FALSE; /* Use hi-speed mode if available? */
53uint sd_sdmode = SDIOH_MODE_SPI; /* Use SD4 mode by default */
54uint sd_f2_blocksize = 512; /* Default blocksize */
55
56uint sd_divisor = 2; /* Default 33MHz/2 = 16MHz for dongle */
57uint sd_power = 1; /* Default to SD Slot powered ON */
58uint sd_clock = 1; /* Default to SD Clock turned ON */
59uint sd_crc = 0; /* Default to SPI CRC Check turned OFF */
60uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
61
62uint sd_toctl = 7;
63
64/* Prototypes */
65static bool sdspi_start_power(sdioh_info_t *sd);
66static int sdspi_set_highspeed_mode(sdioh_info_t *sd, bool HSMode);
67static int sdspi_card_enablefuncs(sdioh_info_t *sd);
68static void sdspi_cmd_getrsp(sdioh_info_t *sd, uint32 *rsp_buffer, int count);
69static int sdspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd, uint32 arg,
70 uint32 *data, uint32 datalen);
71static int sdspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
72 int regsize, uint32 *data);
73static int sdspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
74 int regsize, uint32 data);
75static int sdspi_driver_init(sdioh_info_t *sd);
76static bool sdspi_reset(sdioh_info_t *sd, bool host_reset, bool client_reset);
77static int sdspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
78 uint32 addr, int nbytes, uint32 *data);
79static int sdspi_abort(sdioh_info_t *sd, uint func);
80
81static int set_client_block_size(sdioh_info_t *sd, int func, int blocksize);
82
83static uint8 sdspi_crc7(unsigned char* p, uint32 len);
84static uint16 sdspi_crc16(unsigned char* p, uint32 len);
85static int sdspi_crc_onoff(sdioh_info_t *sd, bool use_crc);
86
87/*
88 * Public entry points & extern's
89 */
90extern sdioh_info_t *
91sdioh_attach(osl_t *osh, void *bar0, uint irq)
92{
93 sdioh_info_t *sd;
94
95 sd_trace(("%s\n", __FUNCTION__));
96 if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
97 sd_err(("sdioh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
98 return NULL;
99 }
100 bzero((char *)sd, sizeof(sdioh_info_t));
101 sd->osh = osh;
102
103 if (spi_osinit(sd) != 0) {
104 sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
105 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
106 return NULL;
107 }
108
109 sd->bar0 = (uintptr)bar0;
110 sd->irq = irq;
111 sd->intr_handler = NULL;
112 sd->intr_handler_arg = NULL;
113 sd->intr_handler_valid = FALSE;
114
115 /* Set defaults */
116 sd->sd_blockmode = FALSE;
117 sd->use_client_ints = TRUE;
118 sd->sd_use_dma = FALSE; /* DMA Not supported */
119
120 /* Haven't figured out how to make bytemode work with dma */
121 if (!sd->sd_blockmode)
122 sd->sd_use_dma = 0;
123
124 if (!spi_hw_attach(sd)) {
125 sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
126 spi_osfree(sd);
127 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
128 return NULL;
129 }
130
131 if (sdspi_driver_init(sd) != SUCCESS) {
132 if (sdspi_driver_init(sd) != SUCCESS) {
133 sd_err(("%s:sdspi_driver_init() failed()\n", __FUNCTION__));
134 spi_hw_detach(sd);
135 spi_osfree(sd);
136 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
137 return (NULL);
138 }
139 }
140
141 if (spi_register_irq(sd, irq) != SUCCESS) {
142 sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
143 spi_hw_detach(sd);
144 spi_osfree(sd);
145 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
146 return (NULL);
147 }
148
149 sd_trace(("%s: Done\n", __FUNCTION__));
150 return sd;
151}
152
153extern SDIOH_API_RC
154sdioh_detach(osl_t *osh, sdioh_info_t *sd)
155{
156 sd_trace(("%s\n", __FUNCTION__));
157
158 if (sd) {
159 if (sd->card_init_done)
160 sdspi_reset(sd, 1, 1);
161
162 sd_info(("%s: detaching from hardware\n", __FUNCTION__));
163 spi_free_irq(sd->irq, sd);
164 spi_hw_detach(sd);
165 spi_osfree(sd);
166 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
167 }
168
169 return SDIOH_API_RC_SUCCESS;
170}
171
172/* Configure callback to client when we recieve client interrupt */
173extern SDIOH_API_RC
174sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
175{
176 sd_trace(("%s: Entering\n", __FUNCTION__));
177
178 sd->intr_handler = fn;
179 sd->intr_handler_arg = argh;
180 sd->intr_handler_valid = TRUE;
181
182 return SDIOH_API_RC_SUCCESS;
183}
184
185extern SDIOH_API_RC
186sdioh_interrupt_deregister(sdioh_info_t *sd)
187{
188 sd_trace(("%s: Entering\n", __FUNCTION__));
189
190 sd->intr_handler_valid = FALSE;
191 sd->intr_handler = NULL;
192 sd->intr_handler_arg = NULL;
193
194 return SDIOH_API_RC_SUCCESS;
195}
196
197extern SDIOH_API_RC
198sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
199{
200 sd_trace(("%s: Entering\n", __FUNCTION__));
201
202 *onoff = sd->client_intr_enabled;
203
204 return SDIOH_API_RC_SUCCESS;
205}
206
207#if defined(DHD_DEBUG)
208extern bool
209sdioh_interrupt_pending(sdioh_info_t *sd)
210{
211 return 0;
212}
213#endif
214
215uint
216sdioh_query_iofnum(sdioh_info_t *sd)
217{
218 return sd->num_funcs;
219}
220
221/* IOVar table */
222enum {
223 IOV_MSGLEVEL = 1,
224 IOV_BLOCKMODE,
225 IOV_BLOCKSIZE,
226 IOV_DMA,
227 IOV_USEINTS,
228 IOV_NUMINTS,
229 IOV_NUMLOCALINTS,
230 IOV_HOSTREG,
231 IOV_DEVREG,
232 IOV_DIVISOR,
233 IOV_SDMODE,
234 IOV_HISPEED,
235 IOV_HCIREGS,
236 IOV_POWER,
237 IOV_CLOCK,
238 IOV_CRC
239};
240
241const bcm_iovar_t sdioh_iovars[] = {
242 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0 },
243 {"sd_blockmode", IOV_BLOCKMODE, 0, IOVT_BOOL, 0 },
244 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0 }, /* ((fn << 16) | size) */
245 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0 },
246 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0 },
247 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0 },
248 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0 },
249 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
250 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
251 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0 },
252 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0 },
253 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0 },
254 {"sd_crc", IOV_CRC, 0, IOVT_UINT32, 0 },
255 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100},
256 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0},
257 {NULL, 0, 0, 0, 0 }
258};
259
260int
261sdioh_iovar_op(sdioh_info_t *si, const char *name,
262 void *params, int plen, void *arg, int len, bool set)
263{
264 const bcm_iovar_t *vi = NULL;
265 int bcmerror = 0;
266 int val_size;
267 int32 int_val = 0;
268 bool bool_val;
269 uint32 actionid;
270
271 ASSERT(name);
272 ASSERT(len >= 0);
273
274 /* Get must have return space; Set does not take qualifiers */
275 ASSERT(set || (arg && len));
276 ASSERT(!set || (!params && !plen));
277
278 sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
279
280 if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
281 bcmerror = BCME_UNSUPPORTED;
282 goto exit;
283 }
284
285 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
286 goto exit;
287
288 /* Set up params so get and set can share the convenience variables */
289 if (params == NULL) {
290 params = arg;
291 plen = len;
292 }
293
294 if (vi->type == IOVT_VOID)
295 val_size = 0;
296 else if (vi->type == IOVT_BUFFER)
297 val_size = len;
298 else
299 val_size = sizeof(int);
300
301 if (plen >= (int)sizeof(int_val))
302 bcopy(params, &int_val, sizeof(int_val));
303
304 bool_val = (int_val != 0) ? TRUE : FALSE;
305
306 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
307 switch (actionid) {
308 case IOV_GVAL(IOV_MSGLEVEL):
309 int_val = (int32)sd_msglevel;
310 bcopy(&int_val, arg, val_size);
311 break;
312
313 case IOV_SVAL(IOV_MSGLEVEL):
314 sd_msglevel = int_val;
315 break;
316
317 case IOV_GVAL(IOV_BLOCKMODE):
318 int_val = (int32)si->sd_blockmode;
319 bcopy(&int_val, arg, val_size);
320 break;
321
322 case IOV_SVAL(IOV_BLOCKMODE):
323 si->sd_blockmode = (bool)int_val;
324 /* Haven't figured out how to make non-block mode with DMA */
325 if (!si->sd_blockmode)
326 si->sd_use_dma = 0;
327 break;
328
329 case IOV_GVAL(IOV_BLOCKSIZE):
330 if ((uint32)int_val > si->num_funcs) {
331 bcmerror = BCME_BADARG;
332 break;
333 }
334 int_val = (int32)si->client_block_size[int_val];
335 bcopy(&int_val, arg, val_size);
336 break;
337
338 case IOV_SVAL(IOV_BLOCKSIZE):
339 {
340 uint func = ((uint32)int_val >> 16);
341 uint blksize = (uint16)int_val;
342 uint maxsize;
343
344 if (func > si->num_funcs) {
345 bcmerror = BCME_BADARG;
346 break;
347 }
348
349 switch (func) {
350 case 0: maxsize = 32; break;
351 case 1: maxsize = BLOCK_SIZE_4318; break;
352 case 2: maxsize = BLOCK_SIZE_4328; break;
353 default: maxsize = 0;
354 }
355 if (blksize > maxsize) {
356 bcmerror = BCME_BADARG;
357 break;
358 }
359 if (!blksize) {
360 blksize = maxsize;
361 }
362
363 /* Now set it */
364 spi_lock(si);
365 bcmerror = set_client_block_size(si, func, blksize);
366 spi_unlock(si);
367 break;
368 }
369
370 case IOV_GVAL(IOV_DMA):
371 int_val = (int32)si->sd_use_dma;
372 bcopy(&int_val, arg, val_size);
373 break;
374
375 case IOV_SVAL(IOV_DMA):
376 si->sd_use_dma = (bool)int_val;
377 break;
378
379 case IOV_GVAL(IOV_USEINTS):
380 int_val = (int32)si->use_client_ints;
381 bcopy(&int_val, arg, val_size);
382 break;
383
384 case IOV_SVAL(IOV_USEINTS):
385 break;
386
387 case IOV_GVAL(IOV_DIVISOR):
388 int_val = (uint32)sd_divisor;
389 bcopy(&int_val, arg, val_size);
390 break;
391
392 case IOV_SVAL(IOV_DIVISOR):
393 sd_divisor = int_val;
394 if (!spi_start_clock(si, (uint16)sd_divisor)) {
395 sd_err(("set clock failed!\n"));
396 bcmerror = BCME_ERROR;
397 }
398 break;
399
400 case IOV_GVAL(IOV_POWER):
401 int_val = (uint32)sd_power;
402 bcopy(&int_val, arg, val_size);
403 break;
404
405 case IOV_SVAL(IOV_POWER):
406 sd_power = int_val;
407 break;
408
409 case IOV_GVAL(IOV_CLOCK):
410 int_val = (uint32)sd_clock;
411 bcopy(&int_val, arg, val_size);
412 break;
413
414 case IOV_SVAL(IOV_CLOCK):
415 sd_clock = int_val;
416 break;
417
418 case IOV_GVAL(IOV_CRC):
419 int_val = (uint32)sd_crc;
420 bcopy(&int_val, arg, val_size);
421 break;
422
423 case IOV_SVAL(IOV_CRC):
424 /* Apply new setting, but don't change sd_crc until
425 * after the CRC-mode is selected in the device. This
426 * is required because the software must generate a
427 * correct CRC for the CMD59 in order to be able to
428 * turn OFF the CRC.
429 */
430 sdspi_crc_onoff(si, int_val ? 1 : 0);
431 sd_crc = int_val;
432 break;
433
434 case IOV_GVAL(IOV_SDMODE):
435 int_val = (uint32)sd_sdmode;
436 bcopy(&int_val, arg, val_size);
437 break;
438
439 case IOV_SVAL(IOV_SDMODE):
440 sd_sdmode = int_val;
441 break;
442
443 case IOV_GVAL(IOV_HISPEED):
444 int_val = (uint32)sd_hiok;
445 bcopy(&int_val, arg, val_size);
446 break;
447
448 case IOV_SVAL(IOV_HISPEED):
449 sd_hiok = int_val;
450
451 if (!sdspi_set_highspeed_mode(si, (bool)sd_hiok)) {
452 sd_err(("Failed changing highspeed mode to %d.\n", sd_hiok));
453 bcmerror = BCME_ERROR;
454 return ERROR;
455 }
456 break;
457
458 case IOV_GVAL(IOV_NUMINTS):
459 int_val = (int32)si->intrcount;
460 bcopy(&int_val, arg, val_size);
461 break;
462
463 case IOV_GVAL(IOV_NUMLOCALINTS):
464 int_val = (int32)si->local_intrcount;
465 bcopy(&int_val, arg, val_size);
466 break;
467
468 case IOV_GVAL(IOV_HOSTREG):
469 {
470 break;
471 }
472
473 case IOV_SVAL(IOV_HOSTREG):
474 {
475 sd_err(("IOV_HOSTREG unsupported\n"));
476 break;
477 }
478
479 case IOV_GVAL(IOV_DEVREG):
480 {
481 sdreg_t *sd_ptr = (sdreg_t *)params;
482 uint8 data;
483
484 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
485 bcmerror = BCME_SDIO_ERROR;
486 break;
487 }
488
489 int_val = (int)data;
490 bcopy(&int_val, arg, sizeof(int_val));
491 break;
492 }
493
494 case IOV_SVAL(IOV_DEVREG):
495 {
496 sdreg_t *sd_ptr = (sdreg_t *)params;
497 uint8 data = (uint8)sd_ptr->value;
498
499 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
500 bcmerror = BCME_SDIO_ERROR;
501 break;
502 }
503 break;
504 }
505
506
507 default:
508 bcmerror = BCME_UNSUPPORTED;
509 break;
510 }
511exit:
512
513 return bcmerror;
514}
515
516extern SDIOH_API_RC
517sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
518{
519 SDIOH_API_RC status;
520 /* No lock needed since sdioh_request_byte does locking */
521 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
522 return status;
523}
524
525extern SDIOH_API_RC
526sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
527{
528 /* No lock needed since sdioh_request_byte does locking */
529 SDIOH_API_RC status;
530 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
531 return status;
532}
533
534extern SDIOH_API_RC
535sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
536{
537 uint32 count;
538 int offset;
539 uint32 foo;
540 uint8 *cis = cisd;
541
542 sd_trace(("%s: Func = %d\n", __FUNCTION__, func));
543
544 if (!sd->func_cis_ptr[func]) {
545 bzero(cis, length);
546 return SDIOH_API_RC_FAIL;
547 }
548
549 spi_lock(sd);
550 *cis = 0;
551 for (count = 0; count < length; count++) {
552 offset = sd->func_cis_ptr[func] + count;
553 if (sdspi_card_regread (sd, 0, offset, 1, &foo) < 0) {
554 sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
555 spi_unlock(sd);
556 return SDIOH_API_RC_FAIL;
557 }
558 *cis = (uint8)(foo & 0xff);
559 cis++;
560 }
561 spi_unlock(sd);
562 return SDIOH_API_RC_SUCCESS;
563}
564
565extern SDIOH_API_RC
566sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
567{
568 int status;
569 uint32 cmd_arg;
570 uint32 rsp5;
571
572 spi_lock(sd);
573
574 cmd_arg = 0;
575 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
576 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
577 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
578 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
579 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, rw == SDIOH_READ ? 0 : *byte);
580
581 sd_trace(("%s: rw=%d, func=%d, regaddr=0x%08x\n", __FUNCTION__, rw, func, regaddr));
582
583 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
584 SDIOH_CMD_52, cmd_arg, NULL, 0)) != SUCCESS) {
585 spi_unlock(sd);
586 return status;
587 }
588
589 sdspi_cmd_getrsp(sd, &rsp5, 1);
590 if (rsp5 != 0x00) {
591 sd_err(("%s: rsp5 flags is 0x%x func=%d\n",
592 __FUNCTION__, rsp5, func));
593 /* ASSERT(0); */
594 spi_unlock(sd);
595 return SDIOH_API_RC_FAIL;
596 }
597
598 if (rw == SDIOH_READ)
599 *byte = sd->card_rsp_data >> 24;
600
601 spi_unlock(sd);
602 return SDIOH_API_RC_SUCCESS;
603}
604
605extern SDIOH_API_RC
606sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
607 uint32 *word, uint nbytes)
608{
609 int status;
610
611 spi_lock(sd);
612
613 if (rw == SDIOH_READ)
614 status = sdspi_card_regread(sd, func, addr, nbytes, word);
615 else
616 status = sdspi_card_regwrite(sd, func, addr, nbytes, *word);
617
618 spi_unlock(sd);
619 return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
620}
621
622extern SDIOH_API_RC
623sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
624 uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
625{
626 int len;
627 int buflen = (int)buflen_u;
628 bool fifo = (fix_inc == SDIOH_DATA_FIX);
629
630 spi_lock(sd);
631
632 ASSERT(reg_width == 4);
633 ASSERT(buflen_u < (1 << 30));
634 ASSERT(sd->client_block_size[func]);
635
636 sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
637 __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
638 buflen_u, sd->r_cnt, sd->t_cnt, pkt));
639
640 /* Break buffer down into blocksize chunks:
641 * Bytemode: 1 block at a time.
642 */
643 while (buflen > 0) {
644 if (sd->sd_blockmode) {
645 /* Max xfer is Page size */
646 len = MIN(SD_PAGE, buflen);
647
648 /* Round down to a block boundry */
649 if (buflen > sd->client_block_size[func])
650 len = (len/sd->client_block_size[func]) *
651 sd->client_block_size[func];
652 } else {
653 /* Byte mode: One block at a time */
654 len = MIN(sd->client_block_size[func], buflen);
655 }
656
657 if (sdspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
658 spi_unlock(sd);
659 return SDIOH_API_RC_FAIL;
660 }
661 buffer += len;
662 buflen -= len;
663 if (!fifo)
664 addr += len;
665 }
666 spi_unlock(sd);
667 return SDIOH_API_RC_SUCCESS;
668}
669
670static int
671sdspi_abort(sdioh_info_t *sd, uint func)
672{
673 uint8 spi_databuf[] = { 0x74, 0x80, 0x00, 0x0C, 0xFF, 0x95, 0xFF, 0xFF,
674 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
675 uint8 spi_rspbuf[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
676 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
677 int err = 0;
678
679 sd_err(("Sending SPI Abort to F%d\n", func));
680 spi_databuf[4] = func & 0x7;
681 /* write to function 0, addr 6 (IOABORT) func # in 3 LSBs. */
682 spi_sendrecv(sd, spi_databuf, spi_rspbuf, sizeof(spi_databuf));
683
684 return err;
685}
686
687extern int
688sdioh_abort(sdioh_info_t *sd, uint fnum)
689{
690 int ret;
691
692 spi_lock(sd);
693 ret = sdspi_abort(sd, fnum);
694 spi_unlock(sd);
695
696 return ret;
697}
698
699int
700sdioh_start(sdioh_info_t *sd, int stage)
701{
702 return SUCCESS;
703}
704
705int
706sdioh_stop(sdioh_info_t *sd)
707{
708 return SUCCESS;
709}
710
711
712/*
713 * Private/Static work routines
714 */
715static bool
716sdspi_reset(sdioh_info_t *sd, bool host_reset, bool client_reset)
717{
718 if (!sd)
719 return TRUE;
720
721 spi_lock(sd);
722 /* Reset client card */
723 if (client_reset && (sd->adapter_slot != -1)) {
724 if (sdspi_card_regwrite(sd, 0, SDIOD_CCCR_IOABORT, 1, 0x8) != SUCCESS)
725 sd_err(("%s: Cannot write to card reg 0x%x\n",
726 __FUNCTION__, SDIOD_CCCR_IOABORT));
727 else
728 sd->card_rca = 0;
729 }
730
731 /* The host reset is a NOP in the sd-spi case. */
732 if (host_reset) {
733 sd->sd_mode = SDIOH_MODE_SPI;
734 }
735 spi_unlock(sd);
736 return TRUE;
737}
738
739static int
740sdspi_host_init(sdioh_info_t *sd)
741{
742 sdspi_reset(sd, 1, 0);
743
744 /* Default power on mode is SD1 */
745 sd->sd_mode = SDIOH_MODE_SPI;
746 sd->polled_mode = TRUE;
747 sd->host_init_done = TRUE;
748 sd->card_init_done = FALSE;
749 sd->adapter_slot = 1;
750
751 return (SUCCESS);
752}
753
754#define CMD0_RETRIES 3
755#define CMD5_RETRIES 10
756
757static int
758get_ocr(sdioh_info_t *sd, uint32 *cmd_arg, uint32 *cmd_rsp)
759{
760 uint32 rsp5;
761 int retries, status;
762
763 /* First issue a CMD0 to get the card into SPI mode. */
764 for (retries = 0; retries <= CMD0_RETRIES; retries++) {
765 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
766 SDIOH_CMD_0, *cmd_arg, NULL, 0)) != SUCCESS) {
767 sd_err(("%s: No response to CMD0\n", __FUNCTION__));
768 continue;
769 }
770
771 sdspi_cmd_getrsp(sd, &rsp5, 1);
772
773 if (GFIELD(rsp5, SPI_RSP_ILL_CMD)) {
774 printf("%s: Card already initialized (continuing)\n", __FUNCTION__);
775 break;
776 }
777
778 if (GFIELD(rsp5, SPI_RSP_IDLE)) {
779 printf("%s: Card in SPI mode\n", __FUNCTION__);
780 break;
781 }
782 }
783
784 if (retries > CMD0_RETRIES) {
785 sd_err(("%s: Too many retries for CMD0\n", __FUNCTION__));
786 return ERROR;
787 }
788
789 /* Get the Card's Operation Condition. */
790 /* Occasionally the board takes a while to become ready. */
791 for (retries = 0; retries <= CMD5_RETRIES; retries++) {
792 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
793 SDIOH_CMD_5, *cmd_arg, NULL, 0)) != SUCCESS) {
794 sd_err(("%s: No response to CMD5\n", __FUNCTION__));
795 continue;
796 }
797
798 printf("CMD5 response data was: 0x%08x\n", sd->card_rsp_data);
799
800 if (GFIELD(sd->card_rsp_data, RSP4_CARD_READY)) {
801 printf("%s: Card ready\n", __FUNCTION__);
802 break;
803 }
804 }
805
806 if (retries > CMD5_RETRIES) {
807 sd_err(("%s: Too many retries for CMD5\n", __FUNCTION__));
808 return ERROR;
809 }
810
811 *cmd_rsp = sd->card_rsp_data;
812
813 sdspi_crc_onoff(sd, sd_crc ? 1 : 0);
814
815 return (SUCCESS);
816}
817
818static int
819sdspi_crc_onoff(sdioh_info_t *sd, bool use_crc)
820{
821 uint32 args;
822 int status;
823
824 args = use_crc ? 1 : 0;
825 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma,
826 SDIOH_CMD_59, args, NULL, 0)) != SUCCESS) {
827 sd_err(("%s: No response to CMD59\n", __FUNCTION__));
828 }
829
830 sd_info(("CMD59 response data was: 0x%08x\n", sd->card_rsp_data));
831
832 sd_err(("SD-SPI CRC turned %s\n", use_crc ? "ON" : "OFF"));
833 return (SUCCESS);
834}
835
836static int
837sdspi_client_init(sdioh_info_t *sd)
838{
839 uint8 fn_ints;
840
841 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
842
843 /* Start at ~400KHz clock rate for initialization */
844 if (!spi_start_clock(sd, 128)) {
845 sd_err(("spi_start_clock failed\n"));
846 return ERROR;
847 }
848
849 if (!sdspi_start_power(sd)) {
850 sd_err(("sdspi_start_power failed\n"));
851 return ERROR;
852 }
853
854 if (sd->num_funcs == 0) {
855 sd_err(("%s: No IO funcs!\n", __FUNCTION__));
856 return ERROR;
857 }
858
859 sdspi_card_enablefuncs(sd);
860
861 set_client_block_size(sd, 1, BLOCK_SIZE_4318);
862 fn_ints = INTR_CTL_FUNC1_EN;
863
864 if (sd->num_funcs >= 2) {
865 set_client_block_size(sd, 2, sd_f2_blocksize /* BLOCK_SIZE_4328 */);
866 fn_ints |= INTR_CTL_FUNC2_EN;
867 }
868
869 /* Enable/Disable Client interrupts */
870 /* Turn on here but disable at host controller */
871 if (sdspi_card_regwrite(sd, 0, SDIOD_CCCR_INTEN, 1,
872 (fn_ints | INTR_CTL_MASTER_EN)) != SUCCESS) {
873 sd_err(("%s: Could not enable ints in CCCR\n", __FUNCTION__));
874 return ERROR;
875 }
876
877 /* Switch to High-speed clocking mode if both host and device support it */
878 sdspi_set_highspeed_mode(sd, (bool)sd_hiok);
879
880 /* After configuring for High-Speed mode, set the desired clock rate. */
881 if (!spi_start_clock(sd, (uint16)sd_divisor)) {
882 sd_err(("spi_start_clock failed\n"));
883 return ERROR;
884 }
885
886 sd->card_init_done = TRUE;
887
888 return SUCCESS;
889}
890
891static int
892sdspi_set_highspeed_mode(sdioh_info_t *sd, bool HSMode)
893{
894 uint32 regdata;
895 int status;
896 bool hsmode;
897
898 if (HSMode == TRUE) {
899
900 sd_err(("Attempting to enable High-Speed mode.\n"));
901
902 if ((status = sdspi_card_regread(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
903 1, &regdata)) != SUCCESS) {
904 return status;
905 }
906 if (regdata & SDIO_SPEED_SHS) {
907 sd_err(("Device supports High-Speed mode.\n"));
908
909 regdata |= SDIO_SPEED_EHS;
910
911 sd_err(("Writing %08x to Card at %08x\n",
912 regdata, SDIOD_CCCR_SPEED_CONTROL));
913 if ((status = sdspi_card_regwrite(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
914 1, regdata)) != BCME_OK) {
915 return status;
916 }
917
918 hsmode = 1;
919
920 sd_err(("High-speed clocking mode enabled.\n"));
921 }
922 else {
923 sd_err(("Device does not support High-Speed Mode.\n"));
924 hsmode = 0;
925 }
926 } else {
927 if ((status = sdspi_card_regread(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
928 1, &regdata)) != SUCCESS) {
929 return status;
930 }
931
932 regdata = ~SDIO_SPEED_EHS;
933
934 sd_err(("Writing %08x to Card at %08x\n",
935 regdata, SDIOD_CCCR_SPEED_CONTROL));
936 if ((status = sdspi_card_regwrite(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
937 1, regdata)) != BCME_OK) {
938 return status;
939 }
940
941 sd_err(("Low-speed clocking mode enabled.\n"));
942 hsmode = 0;
943 }
944
945 spi_controller_highspeed_mode(sd, hsmode);
946
947 return TRUE;
948}
949
950bool
951sdspi_start_power(sdioh_info_t *sd)
952{
953 uint32 cmd_arg;
954 uint32 cmd_rsp;
955
956 sd_trace(("%s\n", __FUNCTION__));
957
958 /* Get the Card's Operation Condition. Occasionally the board
959 * takes a while to become ready
960 */
961
962 cmd_arg = 0;
963 if (get_ocr(sd, &cmd_arg, &cmd_rsp) != SUCCESS) {
964 sd_err(("%s: Failed to get OCR; bailing\n", __FUNCTION__));
965 return FALSE;
966 }
967
968 sd_err(("mem_present = %d\n", GFIELD(cmd_rsp, RSP4_MEM_PRESENT)));
969 sd_err(("num_funcs = %d\n", GFIELD(cmd_rsp, RSP4_NUM_FUNCS)));
970 sd_err(("card_ready = %d\n", GFIELD(cmd_rsp, RSP4_CARD_READY)));
971 sd_err(("OCR = 0x%x\n", GFIELD(cmd_rsp, RSP4_IO_OCR)));
972
973 /* Verify that the card supports I/O mode */
974 if (GFIELD(cmd_rsp, RSP4_NUM_FUNCS) == 0) {
975 sd_err(("%s: Card does not support I/O\n", __FUNCTION__));
976 return ERROR;
977 }
978
979 sd->num_funcs = GFIELD(cmd_rsp, RSP4_NUM_FUNCS);
980
981 /* Examine voltage: Arasan only supports 3.3 volts,
982 * so look for 3.2-3.3 Volts and also 3.3-3.4 volts.
983 */
984
985 if ((GFIELD(cmd_rsp, RSP4_IO_OCR) & (0x3 << 20)) == 0) {
986 sd_err(("This client does not support 3.3 volts!\n"));
987 return ERROR;
988 }
989
990
991 return TRUE;
992}
993
994static int
995sdspi_driver_init(sdioh_info_t *sd)
996{
997 sd_trace(("%s\n", __FUNCTION__));
998
999 if ((sdspi_host_init(sd)) != SUCCESS) {
1000 return ERROR;
1001 }
1002
1003 if (sdspi_client_init(sd) != SUCCESS) {
1004 return ERROR;
1005 }
1006
1007 return SUCCESS;
1008}
1009
1010static int
1011sdspi_card_enablefuncs(sdioh_info_t *sd)
1012{
1013 int status;
1014 uint32 regdata;
1015 uint32 regaddr, fbraddr;
1016 uint8 func;
1017 uint8 *ptr;
1018
1019 sd_trace(("%s\n", __FUNCTION__));
1020 /* Get the Card's common CIS address */
1021 ptr = (uint8 *) &sd->com_cis_ptr;
1022 for (regaddr = SDIOD_CCCR_CISPTR_0; regaddr <= SDIOD_CCCR_CISPTR_2; regaddr++) {
1023 if ((status = sdspi_card_regread (sd, 0, regaddr, 1, &regdata)) != SUCCESS)
1024 return status;
1025
1026 *ptr++ = (uint8) regdata;
1027 }
1028
1029 /* Only the lower 17-bits are valid */
1030 sd->com_cis_ptr &= 0x0001FFFF;
1031 sd->func_cis_ptr[0] = sd->com_cis_ptr;
1032 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr));
1033
1034 /* Get the Card's function CIS (for each function) */
1035 for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
1036 func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
1037 ptr = (uint8 *) &sd->func_cis_ptr[func];
1038 for (regaddr = SDIOD_FBR_CISPTR_0; regaddr <= SDIOD_FBR_CISPTR_2; regaddr++) {
1039 if ((status = sdspi_card_regread (sd, 0, regaddr + fbraddr, 1, &regdata))
1040 != SUCCESS)
1041 return status;
1042
1043 *ptr++ = (uint8) regdata;
1044 }
1045
1046 /* Only the lower 17-bits are valid */
1047 sd->func_cis_ptr[func] &= 0x0001FFFF;
1048 sd_info(("%s: Function %d CIS Ptr = 0x%x\n",
1049 __FUNCTION__, func, sd->func_cis_ptr[func]));
1050 }
1051
1052 sd_info(("%s: write ESCI bit\n", __FUNCTION__));
1053 /* Enable continuous SPI interrupt (ESCI bit) */
1054 sdspi_card_regwrite(sd, 0, SDIOD_CCCR_BICTRL, 1, 0x60);
1055
1056 sd_info(("%s: enable f1\n", __FUNCTION__));
1057 /* Enable function 1 on the card */
1058 regdata = SDIO_FUNC_ENABLE_1;
1059 if ((status = sdspi_card_regwrite(sd, 0, SDIOD_CCCR_IOEN, 1, regdata)) != SUCCESS)
1060 return status;
1061
1062 sd_info(("%s: done\n", __FUNCTION__));
1063 return SUCCESS;
1064}
1065
1066/* Read client card reg */
1067static int
1068sdspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1069{
1070 int status;
1071 uint32 cmd_arg;
1072 uint32 rsp5;
1073
1074 cmd_arg = 0;
1075
1076 if ((func == 0) || (regsize == 1)) {
1077 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
1078 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
1079 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, SDIOH_XFER_TYPE_READ);
1080 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
1081 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, 0);
1082
1083 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_52, cmd_arg, NULL, 0))
1084 != SUCCESS)
1085 return status;
1086
1087 sdspi_cmd_getrsp(sd, &rsp5, 1);
1088
1089 if (rsp5 != 0x00)
1090 sd_err(("%s: rsp5 flags is 0x%x\t %d\n",
1091 __FUNCTION__, rsp5, func));
1092
1093 *data = sd->card_rsp_data >> 24;
1094 } else {
1095 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, regsize);
1096 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
1097 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
1098 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
1099 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, regaddr);
1100 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_READ);
1101
1102 sd->data_xfer_count = regsize;
1103
1104 /* sdspi_cmd_issue() returns with the command complete bit
1105 * in the ISR already cleared
1106 */
1107 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_53, cmd_arg, NULL, 0))
1108 != SUCCESS)
1109 return status;
1110
1111 sdspi_cmd_getrsp(sd, &rsp5, 1);
1112
1113 if (rsp5 != 0x00)
1114 sd_err(("%s: rsp5 flags is 0x%x\t %d\n",
1115 __FUNCTION__, rsp5, func));
1116
1117 *data = sd->card_rsp_data;
1118 if (regsize == 2) {
1119 *data &= 0xffff;
1120 }
1121
1122 sd_info(("%s: CMD53 func %d, addr 0x%x, size %d, data 0x%08x\n",
1123 __FUNCTION__, func, regaddr, regsize, *data));
1124
1125
1126 }
1127
1128 return SUCCESS;
1129}
1130
1131/* write a client register */
1132static int
1133sdspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
1134{
1135 int status;
1136 uint32 cmd_arg, rsp5, flags;
1137
1138 cmd_arg = 0;
1139
1140 if ((func == 0) || (regsize == 1)) {
1141 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
1142 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
1143 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
1144 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
1145 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, data & 0xff);
1146 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_52, cmd_arg, NULL, 0))
1147 != SUCCESS)
1148 return status;
1149
1150 sdspi_cmd_getrsp(sd, &rsp5, 1);
1151 flags = GFIELD(rsp5, RSP5_FLAGS);
1152 if (flags && (flags != 0x10))
1153 sd_err(("%s: rsp5.rsp5.flags = 0x%x, expecting 0x10\n",
1154 __FUNCTION__, flags));
1155 }
1156 else {
1157 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, regsize);
1158 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
1159 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
1160 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
1161 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, regaddr);
1162 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
1163
1164 sd->data_xfer_count = regsize;
1165 sd->cmd53_wr_data = data;
1166
1167 sd_info(("%s: CMD53 func %d, addr 0x%x, size %d, data 0x%08x\n",
1168 __FUNCTION__, func, regaddr, regsize, data));
1169
1170 /* sdspi_cmd_issue() returns with the command complete bit
1171 * in the ISR already cleared
1172 */
1173 if ((status = sdspi_cmd_issue(sd, sd->sd_use_dma, SDIOH_CMD_53, cmd_arg, NULL, 0))
1174 != SUCCESS)
1175 return status;
1176
1177 sdspi_cmd_getrsp(sd, &rsp5, 1);
1178
1179 if (rsp5 != 0x00)
1180 sd_err(("%s: rsp5 flags = 0x%x, expecting 0x00\n",
1181 __FUNCTION__, rsp5));
1182
1183 }
1184 return SUCCESS;
1185}
1186
1187void
1188sdspi_cmd_getrsp(sdioh_info_t *sd, uint32 *rsp_buffer, int count /* num 32 bit words */)
1189{
1190 *rsp_buffer = sd->card_response;
1191}
1192
1193int max_errors = 0;
1194
1195#define SPI_MAX_PKT_LEN 768
1196uint8 spi_databuf[SPI_MAX_PKT_LEN];
1197uint8 spi_rspbuf[SPI_MAX_PKT_LEN];
1198
1199/* datalen is used for CMD53 length only (0 for sd->data_xfer_count) */
1200static int
1201sdspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd, uint32 arg,
1202 uint32 *data, uint32 datalen)
1203{
1204 uint32 cmd_reg;
1205 uint32 cmd_arg = arg;
1206 uint8 cmd_crc = 0x95; /* correct CRC for CMD0 and don't care for others. */
1207 uint16 dat_crc;
1208 uint8 cmd52data = 0;
1209 uint32 i, j;
1210 uint32 spi_datalen = 0;
1211 uint32 spi_pre_cmd_pad = 0;
1212 uint32 spi_max_response_pad = 128;
1213
1214 cmd_reg = 0;
1215 cmd_reg = SFIELD(cmd_reg, SPI_DIR, 1);
1216 cmd_reg = SFIELD(cmd_reg, SPI_CMD_INDEX, cmd);
1217
1218 if (GFIELD(cmd_arg, CMD52_RW_FLAG) == 1) { /* Same for CMD52 and CMD53 */
1219 cmd_reg = SFIELD(cmd_reg, SPI_RW, 1);
1220 }
1221
1222 switch (cmd) {
1223 case SDIOH_CMD_59: /* CRC_ON_OFF (SPI Mode Only) - Response R1 */
1224 cmd52data = arg & 0x1;
1225 case SDIOH_CMD_0: /* Set Card to Idle State - No Response */
1226 case SDIOH_CMD_5: /* Send Operation condition - Response R4 */
1227 sd_trace(("%s: CMD%d\n", __FUNCTION__, cmd));
1228 spi_datalen = 44;
1229 spi_pre_cmd_pad = 12;
1230 spi_max_response_pad = 28;
1231 break;
1232
1233 case SDIOH_CMD_3: /* Ask card to send RCA - Response R6 */
1234 case SDIOH_CMD_7: /* Select card - Response R1 */
1235 case SDIOH_CMD_15: /* Set card to inactive state - Response None */
1236 sd_err(("%s: CMD%d is invalid for SPI Mode.\n", __FUNCTION__, cmd));
1237 return ERROR;
1238 break;
1239
1240 case SDIOH_CMD_52: /* IO R/W Direct (single byte) - Response R5 */
1241 cmd52data = GFIELD(cmd_arg, CMD52_DATA);
1242 cmd_arg = arg;
1243 cmd_reg = SFIELD(cmd_reg, SPI_FUNC, GFIELD(cmd_arg, CMD52_FUNCTION));
1244 cmd_reg = SFIELD(cmd_reg, SPI_ADDR, GFIELD(cmd_arg, CMD52_REG_ADDR));
1245 /* Display trace for byte write */
1246 if (GFIELD(cmd_arg, CMD52_RW_FLAG) == 1) {
1247 sd_trace(("%s: CMD52: Wr F:%d @0x%04x=%02x\n",
1248 __FUNCTION__,
1249 GFIELD(cmd_arg, CMD52_FUNCTION),
1250 GFIELD(cmd_arg, CMD52_REG_ADDR),
1251 cmd52data));
1252 }
1253
1254 spi_datalen = 32;
1255 spi_max_response_pad = 28;
1256
1257 break;
1258 case SDIOH_CMD_53: /* IO R/W Extended (multiple bytes/blocks) */
1259 cmd_arg = arg;
1260 cmd_reg = SFIELD(cmd_reg, SPI_FUNC, GFIELD(cmd_arg, CMD53_FUNCTION));
1261 cmd_reg = SFIELD(cmd_reg, SPI_ADDR, GFIELD(cmd_arg, CMD53_REG_ADDR));
1262 cmd_reg = SFIELD(cmd_reg, SPI_BLKMODE, 0);
1263 cmd_reg = SFIELD(cmd_reg, SPI_OPCODE, GFIELD(cmd_arg, CMD53_OP_CODE));
1264 cmd_reg = SFIELD(cmd_reg, SPI_STUFF0, (sd->data_xfer_count>>8));
1265 cmd52data = (uint8)sd->data_xfer_count;
1266
1267 /* Set upper bit in byte count if necessary, but don't set it for 512 bytes. */
1268 if ((sd->data_xfer_count > 255) && (sd->data_xfer_count < 512)) {
1269 cmd_reg |= 1;
1270 }
1271
1272 if (GFIELD(cmd_reg, SPI_RW) == 1) { /* Write */
1273 spi_max_response_pad = 32;
1274 spi_datalen = (sd->data_xfer_count + spi_max_response_pad) & 0xFFFC;
1275 } else { /* Read */
1276
1277 spi_max_response_pad = 32;
1278 spi_datalen = (sd->data_xfer_count + spi_max_response_pad) & 0xFFFC;
1279 }
1280 sd_trace(("%s: CMD53: %s F:%d @0x%04x len=0x%02x\n",
1281 __FUNCTION__,
1282 (GFIELD(cmd_reg, SPI_RW) == 1 ? "Wr" : "Rd"),
1283 GFIELD(cmd_arg, CMD53_FUNCTION),
1284 GFIELD(cmd_arg, CMD53_REG_ADDR),
1285 cmd52data));
1286 break;
1287
1288 default:
1289 sd_err(("%s: Unknown command %d\n", __FUNCTION__, cmd));
1290 return ERROR;
1291 }
1292
1293 /* Set up and issue the SDIO command */
1294 memset(spi_databuf, SDSPI_IDLE_PAD, spi_datalen);
1295 spi_databuf[spi_pre_cmd_pad + 0] = (cmd_reg & 0xFF000000) >> 24;
1296 spi_databuf[spi_pre_cmd_pad + 1] = (cmd_reg & 0x00FF0000) >> 16;
1297 spi_databuf[spi_pre_cmd_pad + 2] = (cmd_reg & 0x0000FF00) >> 8;
1298 spi_databuf[spi_pre_cmd_pad + 3] = (cmd_reg & 0x000000FF);
1299 spi_databuf[spi_pre_cmd_pad + 4] = cmd52data;
1300
1301 /* Generate CRC7 for command, if CRC is enabled, otherwise, a
1302 * default CRC7 of 0x95, which is correct for CMD0, is used.
1303 */
1304 if (sd_crc) {
1305 cmd_crc = sdspi_crc7(&spi_databuf[spi_pre_cmd_pad], 5);
1306 }
1307 spi_databuf[spi_pre_cmd_pad + 5] = cmd_crc;
1308#define SPI_STOP_TRAN 0xFD
1309
1310 /* for CMD53 Write, put the data into the output buffer */
1311 if ((cmd == SDIOH_CMD_53) && (GFIELD(cmd_arg, CMD53_RW_FLAG) == 1)) {
1312 if (datalen != 0) {
1313 spi_databuf[spi_pre_cmd_pad + 9] = SDSPI_IDLE_PAD;
1314 spi_databuf[spi_pre_cmd_pad + 10] = SDSPI_START_BLOCK;
1315
1316 for (i = 0; i < sd->data_xfer_count; i++) {
1317 spi_databuf[i + 11 + spi_pre_cmd_pad] = ((uint8 *)data)[i];
1318 }
1319 if (sd_crc) {
1320 dat_crc = sdspi_crc16(&spi_databuf[spi_pre_cmd_pad+11], i);
1321 } else {
1322 dat_crc = 0xAAAA;
1323 }
1324 spi_databuf[i + 11 + spi_pre_cmd_pad] = (dat_crc >> 8) & 0xFF;
1325 spi_databuf[i + 12 + spi_pre_cmd_pad] = dat_crc & 0xFF;
1326 } else if (sd->data_xfer_count == 2) {
1327 spi_databuf[spi_pre_cmd_pad + 9] = SDSPI_IDLE_PAD;
1328 spi_databuf[spi_pre_cmd_pad + 10] = SDSPI_START_BLOCK;
1329 spi_databuf[spi_pre_cmd_pad + 11] = sd->cmd53_wr_data & 0xFF;
1330 spi_databuf[spi_pre_cmd_pad + 12] = (sd->cmd53_wr_data & 0x0000FF00) >> 8;
1331 if (sd_crc) {
1332 dat_crc = sdspi_crc16(&spi_databuf[spi_pre_cmd_pad+11], 2);
1333 } else {
1334 dat_crc = 0x22AA;
1335 }
1336 spi_databuf[spi_pre_cmd_pad + 13] = (dat_crc >> 8) & 0xFF;
1337 spi_databuf[spi_pre_cmd_pad + 14] = (dat_crc & 0xFF);
1338 } else if (sd->data_xfer_count == 4) {
1339 spi_databuf[spi_pre_cmd_pad + 9] = SDSPI_IDLE_PAD;
1340 spi_databuf[spi_pre_cmd_pad + 10] = SDSPI_START_BLOCK;
1341 spi_databuf[spi_pre_cmd_pad + 11] = sd->cmd53_wr_data & 0xFF;
1342 spi_databuf[spi_pre_cmd_pad + 12] = (sd->cmd53_wr_data & 0x0000FF00) >> 8;
1343 spi_databuf[spi_pre_cmd_pad + 13] = (sd->cmd53_wr_data & 0x00FF0000) >> 16;
1344 spi_databuf[spi_pre_cmd_pad + 14] = (sd->cmd53_wr_data & 0xFF000000) >> 24;
1345 if (sd_crc) {
1346 dat_crc = sdspi_crc16(&spi_databuf[spi_pre_cmd_pad+11], 4);
1347 } else {
1348 dat_crc = 0x44AA;
1349 }
1350 spi_databuf[spi_pre_cmd_pad + 15] = (dat_crc >> 8) & 0xFF;
1351 spi_databuf[spi_pre_cmd_pad + 16] = (dat_crc & 0xFF);
1352 } else {
1353 printf("CMD53 Write: size %d unsupported\n", sd->data_xfer_count);
1354 }
1355 }
1356
1357 spi_sendrecv(sd, spi_databuf, spi_rspbuf, spi_datalen);
1358
1359 for (i = spi_pre_cmd_pad + SDSPI_COMMAND_LEN; i < spi_max_response_pad; i++) {
1360 if ((spi_rspbuf[i] & SDSPI_START_BIT_MASK) == 0) {
1361 break;
1362 }
1363 }
1364
1365 if (i == spi_max_response_pad) {
1366 sd_err(("%s: Did not get a response for CMD%d\n", __FUNCTION__, cmd));
1367 return ERROR;
1368 }
1369
1370 /* Extract the response. */
1371 sd->card_response = spi_rspbuf[i];
1372
1373 /* for CMD53 Read, find the start of the response data... */
1374 if ((cmd == SDIOH_CMD_53) && (GFIELD(cmd_arg, CMD52_RW_FLAG) == 0)) {
1375 for (; i < spi_max_response_pad; i++) {
1376 if (spi_rspbuf[i] == SDSPI_START_BLOCK) {
1377 break;
1378 }
1379 }
1380
1381 if (i == spi_max_response_pad) {
1382 printf("Did not get a start of data phase for CMD%d\n", cmd);
1383 max_errors++;
1384 sdspi_abort(sd, GFIELD(cmd_arg, CMD53_FUNCTION));
1385 }
1386 sd->card_rsp_data = spi_rspbuf[i+1];
1387 sd->card_rsp_data |= spi_rspbuf[i+2] << 8;
1388 sd->card_rsp_data |= spi_rspbuf[i+3] << 16;
1389 sd->card_rsp_data |= spi_rspbuf[i+4] << 24;
1390
1391 if (datalen != 0) {
1392 i++;
1393 for (j = 0; j < sd->data_xfer_count; j++) {
1394 ((uint8 *)data)[j] = spi_rspbuf[i+j];
1395 }
1396 if (sd_crc) {
1397 uint16 recv_crc;
1398
1399 recv_crc = spi_rspbuf[i+j] << 8 | spi_rspbuf[i+j+1];
1400 dat_crc = sdspi_crc16((uint8 *)data, datalen);
1401 if (dat_crc != recv_crc) {
1402 sd_err(("%s: Incorrect data CRC: expected 0x%04x, "
1403 "received 0x%04x\n",
1404 __FUNCTION__, dat_crc, recv_crc));
1405 }
1406 }
1407 }
1408 return SUCCESS;
1409 }
1410
1411 sd->card_rsp_data = spi_rspbuf[i+4];
1412 sd->card_rsp_data |= spi_rspbuf[i+3] << 8;
1413 sd->card_rsp_data |= spi_rspbuf[i+2] << 16;
1414 sd->card_rsp_data |= spi_rspbuf[i+1] << 24;
1415
1416 /* Display trace for byte read */
1417 if ((cmd == SDIOH_CMD_52) && (GFIELD(cmd_arg, CMD52_RW_FLAG) == 0)) {
1418 sd_trace(("%s: CMD52: Rd F:%d @0x%04x=%02x\n",
1419 __FUNCTION__,
1420 GFIELD(cmd_arg, CMD53_FUNCTION),
1421 GFIELD(cmd_arg, CMD53_REG_ADDR),
1422 sd->card_rsp_data >> 24));
1423 }
1424
1425 return SUCCESS;
1426}
1427
1428/*
1429 * On entry: if single-block or non-block, buffer size <= block size.
1430 * If multi-block, buffer size is unlimited.
1431 * Question is how to handle the left-overs in either single- or multi-block.
1432 * I think the caller should break the buffer up so this routine will always
1433 * use block size == buffer size to handle the end piece of the buffer
1434 */
1435
1436static int
1437sdspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo, uint32 addr, int nbytes, uint32 *data)
1438{
1439 int status;
1440 uint32 cmd_arg;
1441 uint32 rsp5;
1442 int num_blocks, blocksize;
1443 bool local_blockmode, local_dma;
1444 bool read = rw == SDIOH_READ ? 1 : 0;
1445
1446 ASSERT(nbytes);
1447
1448 cmd_arg = 0;
1449 sd_data(("%s: %s 53 func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1450 __FUNCTION__, read ? "Rd" : "Wr", func, fifo ? "FIXED" : "INCR",
1451 addr, nbytes, sd->r_cnt, sd->t_cnt));
1452
1453 if (read) sd->r_cnt++; else sd->t_cnt++;
1454
1455 local_blockmode = sd->sd_blockmode;
1456 local_dma = sd->sd_use_dma;
1457
1458 /* Don't bother with block mode on small xfers */
1459 if (nbytes < sd->client_block_size[func]) {
1460 sd_info(("setting local blockmode to false: nbytes (%d) != block_size (%d)\n",
1461 nbytes, sd->client_block_size[func]));
1462 local_blockmode = FALSE;
1463 local_dma = FALSE;
1464 }
1465
1466 if (local_blockmode) {
1467 blocksize = MIN(sd->client_block_size[func], nbytes);
1468 num_blocks = nbytes/blocksize;
1469 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, num_blocks);
1470 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 1);
1471 } else {
1472 num_blocks = 1;
1473 blocksize = nbytes;
1474 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, nbytes);
1475 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
1476 }
1477
1478 if (fifo)
1479 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 0);
1480 else
1481 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
1482
1483 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
1484 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, addr);
1485 if (read)
1486 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_READ);
1487 else
1488 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
1489
1490 sd->data_xfer_count = nbytes;
1491 if ((func == 2) && (fifo == 1)) {
1492 sd_data(("%s: %s 53 func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1493 __FUNCTION__, read ? "Rd" : "Wr", func, fifo ? "FIXED" : "INCR",
1494 addr, nbytes, sd->r_cnt, sd->t_cnt));
1495 }
1496
1497 /* sdspi_cmd_issue() returns with the command complete bit
1498 * in the ISR already cleared
1499 */
1500 if ((status = sdspi_cmd_issue(sd, local_dma,
1501 SDIOH_CMD_53, cmd_arg,
1502 data, nbytes)) != SUCCESS) {
1503 sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__, (read ? "read" : "write")));
1504 return status;
1505 }
1506
1507 sdspi_cmd_getrsp(sd, &rsp5, 1);
1508
1509 if (rsp5 != 0x00) {
1510 sd_err(("%s: rsp5 flags = 0x%x, expecting 0x00\n",
1511 __FUNCTION__, rsp5));
1512 return ERROR;
1513 }
1514
1515 return SUCCESS;
1516}
1517
1518static int
1519set_client_block_size(sdioh_info_t *sd, int func, int block_size)
1520{
1521 int base;
1522 int err = 0;
1523
1524 sd_err(("%s: Setting block size %d, func %d\n", __FUNCTION__, block_size, func));
1525 sd->client_block_size[func] = block_size;
1526
1527 /* Set the block size in the SDIO Card register */
1528 base = func * SDIOD_FBR_SIZE;
1529 err = sdspi_card_regwrite(sd, 0, base + SDIOD_CCCR_BLKSIZE_0, 1, block_size & 0xff);
1530 if (!err) {
1531 err = sdspi_card_regwrite(sd, 0, base + SDIOD_CCCR_BLKSIZE_1, 1,
1532 (block_size >> 8) & 0xff);
1533 }
1534
1535 /*
1536 * Do not set the block size in the SDIO Host register; that
1537 * is func dependent and will get done on an individual
1538 * transaction basis.
1539 */
1540
1541 return (err ? BCME_SDIO_ERROR : 0);
1542}
1543
1544/* Reset and re-initialize the device */
1545int
1546sdioh_sdio_reset(sdioh_info_t *si)
1547{
1548 si->card_init_done = FALSE;
1549 return sdspi_client_init(si);
1550}
1551
1552#define CRC7_POLYNOM 0x09
1553#define CRC7_CRCHIGHBIT 0x40
1554
1555static uint8 sdspi_crc7(unsigned char* p, uint32 len)
1556{
1557 uint8 c, j, bit, crc = 0;
1558 uint32 i;
1559
1560 for (i = 0; i < len; i++) {
1561 c = *p++;
1562 for (j = 0x80; j; j >>= 1) {
1563 bit = crc & CRC7_CRCHIGHBIT;
1564 crc <<= 1;
1565 if (c & j) bit ^= CRC7_CRCHIGHBIT;
1566 if (bit) crc ^= CRC7_POLYNOM;
1567 }
1568 }
1569
1570 /* Convert the CRC7 to an 8-bit SD CRC */
1571 crc = (crc << 1) | 1;
1572
1573 return (crc);
1574}
1575
1576#define CRC16_POLYNOM 0x1021
1577#define CRC16_CRCHIGHBIT 0x8000
1578
1579static uint16 sdspi_crc16(unsigned char* p, uint32 len)
1580{
1581 uint32 i;
1582 uint16 j, c, bit;
1583 uint16 crc = 0;
1584
1585 for (i = 0; i < len; i++) {
1586 c = *p++;
1587 for (j = 0x80; j; j >>= 1) {
1588 bit = crc & CRC16_CRCHIGHBIT;
1589 crc <<= 1;
1590 if (c & j) bit ^= CRC16_CRCHIGHBIT;
1591 if (bit) crc ^= CRC16_POLYNOM;
1592 }
1593 }
1594
1595 return (crc);
1596}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 17:40:07 -0400