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path: root/drivers/net/wireless/ath/ath9k/init.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/init.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c16
1 files changed, 4 insertions, 12 deletions
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 944e9b518f1..60159f4ee53 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -172,7 +172,7 @@ static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
172 struct ath_common *common = ath9k_hw_common(ah); 172 struct ath_common *common = ath9k_hw_common(ah);
173 struct ath_softc *sc = (struct ath_softc *) common->priv; 173 struct ath_softc *sc = (struct ath_softc *) common->priv;
174 174
175 if (ah->config.serialize_regmode == SER_REG_MODE_ON) { 175 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
176 unsigned long flags; 176 unsigned long flags;
177 spin_lock_irqsave(&sc->sc_serial_rw, flags); 177 spin_lock_irqsave(&sc->sc_serial_rw, flags);
178 iowrite32(val, sc->mem + reg_offset); 178 iowrite32(val, sc->mem + reg_offset);
@@ -188,7 +188,7 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
188 struct ath_softc *sc = (struct ath_softc *) common->priv; 188 struct ath_softc *sc = (struct ath_softc *) common->priv;
189 u32 val; 189 u32 val;
190 190
191 if (ah->config.serialize_regmode == SER_REG_MODE_ON) { 191 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
192 unsigned long flags; 192 unsigned long flags;
193 spin_lock_irqsave(&sc->sc_serial_rw, flags); 193 spin_lock_irqsave(&sc->sc_serial_rw, flags);
194 val = ioread32(sc->mem + reg_offset); 194 val = ioread32(sc->mem + reg_offset);
@@ -219,7 +219,7 @@ static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 cl
219 unsigned long uninitialized_var(flags); 219 unsigned long uninitialized_var(flags);
220 u32 val; 220 u32 val;
221 221
222 if (ah->config.serialize_regmode == SER_REG_MODE_ON) { 222 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
223 spin_lock_irqsave(&sc->sc_serial_rw, flags); 223 spin_lock_irqsave(&sc->sc_serial_rw, flags);
224 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 224 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
225 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 225 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
@@ -484,19 +484,11 @@ static void ath9k_init_misc(struct ath_softc *sc)
484{ 484{
485 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 485 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
486 int i = 0; 486 int i = 0;
487
487 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 488 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
488 489
489 sc->config.txpowlimit = ATH_TXPOWER_MAX; 490 sc->config.txpowlimit = ATH_TXPOWER_MAX;
490
491 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
492 sc->sc_flags |= SC_OP_TXAGGR;
493 sc->sc_flags |= SC_OP_RXAGGR;
494 }
495
496 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
497
498 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 491 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
499
500 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 492 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
501 493
502 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 494 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)