diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.h | 63 |
1 files changed, 48 insertions, 15 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index b8923457182..cdaec526db3 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h | |||
@@ -27,17 +27,24 @@ | |||
27 | #include "calib.h" | 27 | #include "calib.h" |
28 | #include "reg.h" | 28 | #include "reg.h" |
29 | #include "phy.h" | 29 | #include "phy.h" |
30 | #include "btcoex.h" | ||
30 | 31 | ||
31 | #include "../regd.h" | 32 | #include "../regd.h" |
33 | #include "../debug.h" | ||
32 | 34 | ||
33 | #define ATHEROS_VENDOR_ID 0x168c | 35 | #define ATHEROS_VENDOR_ID 0x168c |
36 | |||
34 | #define AR5416_DEVID_PCI 0x0023 | 37 | #define AR5416_DEVID_PCI 0x0023 |
35 | #define AR5416_DEVID_PCIE 0x0024 | 38 | #define AR5416_DEVID_PCIE 0x0024 |
36 | #define AR9160_DEVID_PCI 0x0027 | 39 | #define AR9160_DEVID_PCI 0x0027 |
37 | #define AR9280_DEVID_PCI 0x0029 | 40 | #define AR9280_DEVID_PCI 0x0029 |
38 | #define AR9280_DEVID_PCIE 0x002a | 41 | #define AR9280_DEVID_PCIE 0x002a |
39 | #define AR9285_DEVID_PCIE 0x002b | 42 | #define AR9285_DEVID_PCIE 0x002b |
43 | |||
40 | #define AR5416_AR9100_DEVID 0x000b | 44 | #define AR5416_AR9100_DEVID 0x000b |
45 | |||
46 | #define AR9271_USB 0x9271 | ||
47 | |||
41 | #define AR_SUBVENDOR_ID_NOG 0x0e11 | 48 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
42 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | 49 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 |
43 | #define AR5416_MAGIC 0x19641014 | 50 | #define AR5416_MAGIC 0x19641014 |
@@ -49,9 +56,18 @@ | |||
49 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | 56 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa |
50 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | 57 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab |
51 | 58 | ||
59 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) | ||
60 | |||
61 | #define ATH_DEFAULT_NOISE_FLOOR -95 | ||
62 | |||
63 | #define ATH9K_RSSI_BAD 0x80 | ||
64 | |||
52 | /* Register read/write primitives */ | 65 | /* Register read/write primitives */ |
53 | #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val)) | 66 | #define REG_WRITE(_ah, _reg, _val) \ |
54 | #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg)) | 67 | ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) |
68 | |||
69 | #define REG_READ(_ah, _reg) \ | ||
70 | ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) | ||
55 | 71 | ||
56 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | 72 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
57 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | 73 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) |
@@ -91,7 +107,7 @@ | |||
91 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | 107 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) |
92 | 108 | ||
93 | #define BASE_ACTIVATE_DELAY 100 | 109 | #define BASE_ACTIVATE_DELAY 100 |
94 | #define RTC_PLL_SETTLE_DELAY 1000 | 110 | #define RTC_PLL_SETTLE_DELAY 100 |
95 | #define COEF_SCALE_S 24 | 111 | #define COEF_SCALE_S 24 |
96 | #define HT40_CHANNEL_CENTER_SHIFT 10 | 112 | #define HT40_CHANNEL_CENTER_SHIFT 10 |
97 | 113 | ||
@@ -433,7 +449,8 @@ struct ath_gen_timer_table { | |||
433 | }; | 449 | }; |
434 | 450 | ||
435 | struct ath_hw { | 451 | struct ath_hw { |
436 | struct ath_softc *ah_sc; | 452 | struct ieee80211_hw *hw; |
453 | struct ath_common common; | ||
437 | struct ath9k_hw_version hw_version; | 454 | struct ath9k_hw_version hw_version; |
438 | struct ath9k_ops_config config; | 455 | struct ath9k_ops_config config; |
439 | struct ath9k_hw_capabilities caps; | 456 | struct ath9k_hw_capabilities caps; |
@@ -450,7 +467,6 @@ struct ath_hw { | |||
450 | 467 | ||
451 | bool sw_mgmt_crypto; | 468 | bool sw_mgmt_crypto; |
452 | bool is_pciexpress; | 469 | bool is_pciexpress; |
453 | u8 macaddr[ETH_ALEN]; | ||
454 | u16 tx_trig_level; | 470 | u16 tx_trig_level; |
455 | u16 rfsilent; | 471 | u16 rfsilent; |
456 | u32 rfkill_gpio; | 472 | u32 rfkill_gpio; |
@@ -553,8 +569,10 @@ struct ath_hw { | |||
553 | int firpwr[5]; | 569 | int firpwr[5]; |
554 | enum ath9k_ani_cmd ani_function; | 570 | enum ath9k_ani_cmd ani_function; |
555 | 571 | ||
572 | /* Bluetooth coexistance */ | ||
573 | struct ath_btcoex_hw btcoex_hw; | ||
574 | |||
556 | u32 intr_txqs; | 575 | u32 intr_txqs; |
557 | enum ath9k_ht_extprotspacing extprotspacing; | ||
558 | u8 txchainmask; | 576 | u8 txchainmask; |
559 | u8 rxchainmask; | 577 | u8 rxchainmask; |
560 | 578 | ||
@@ -578,12 +596,24 @@ struct ath_hw { | |||
578 | struct ar5416IniArray iniModesAdditional; | 596 | struct ar5416IniArray iniModesAdditional; |
579 | struct ar5416IniArray iniModesRxGain; | 597 | struct ar5416IniArray iniModesRxGain; |
580 | struct ar5416IniArray iniModesTxGain; | 598 | struct ar5416IniArray iniModesTxGain; |
599 | struct ar5416IniArray iniCckfirNormal; | ||
600 | struct ar5416IniArray iniCckfirJapan2484; | ||
581 | 601 | ||
582 | u32 intr_gen_timer_trigger; | 602 | u32 intr_gen_timer_trigger; |
583 | u32 intr_gen_timer_thresh; | 603 | u32 intr_gen_timer_thresh; |
584 | struct ath_gen_timer_table hw_gen_timers; | 604 | struct ath_gen_timer_table hw_gen_timers; |
585 | }; | 605 | }; |
586 | 606 | ||
607 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) | ||
608 | { | ||
609 | return &ah->common; | ||
610 | } | ||
611 | |||
612 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | ||
613 | { | ||
614 | return &(ath9k_hw_common(ah)->regulatory); | ||
615 | } | ||
616 | |||
587 | /* Initialization, Detach, Reset */ | 617 | /* Initialization, Detach, Reset */ |
588 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); | 618 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
589 | void ath9k_hw_detach(struct ath_hw *ah); | 619 | void ath9k_hw_detach(struct ath_hw *ah); |
@@ -637,19 +667,20 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); | |||
637 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); | 667 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); |
638 | void ath9k_hw_setopmode(struct ath_hw *ah); | 668 | void ath9k_hw_setopmode(struct ath_hw *ah); |
639 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | 669 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); |
640 | void ath9k_hw_setbssidmask(struct ath_softc *sc); | 670 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
641 | void ath9k_hw_write_associd(struct ath_softc *sc); | 671 | void ath9k_hw_write_associd(struct ath_hw *ah); |
642 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); | 672 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
643 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | 673 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); |
644 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | 674 | void ath9k_hw_reset_tsf(struct ath_hw *ah); |
645 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); | 675 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
646 | bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); | 676 | bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); |
647 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); | 677 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
648 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); | 678 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
649 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | 679 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
650 | const struct ath9k_beacon_state *bs); | 680 | const struct ath9k_beacon_state *bs); |
651 | bool ath9k_hw_setpower(struct ath_hw *ah, | 681 | |
652 | enum ath9k_power_mode mode); | 682 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
683 | |||
653 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off); | 684 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off); |
654 | 685 | ||
655 | /* Interrupt Handling */ | 686 | /* Interrupt Handling */ |
@@ -663,9 +694,12 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |||
663 | void (*overflow)(void *), | 694 | void (*overflow)(void *), |
664 | void *arg, | 695 | void *arg, |
665 | u8 timer_index); | 696 | u8 timer_index); |
666 | void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer, | 697 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
667 | u32 timer_next, u32 timer_period); | 698 | struct ath_gen_timer *timer, |
668 | void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | 699 | u32 timer_next, |
700 | u32 timer_period); | ||
701 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | ||
702 | |||
669 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); | 703 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
670 | void ath_gen_timer_isr(struct ath_hw *hw); | 704 | void ath_gen_timer_isr(struct ath_hw *hw); |
671 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); | 705 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
@@ -674,5 +708,4 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah); | |||
674 | #define ATH_PCIE_CAP_LINK_L0S 1 | 708 | #define ATH_PCIE_CAP_LINK_L0S 1 |
675 | #define ATH_PCIE_CAP_LINK_L1 2 | 709 | #define ATH_PCIE_CAP_LINK_L1 2 |
676 | 710 | ||
677 | void ath_pcie_aspm_disable(struct ath_softc *sc); | ||
678 | #endif | 711 | #endif |