aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/ath/ath9k/hw.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c1913
1 files changed, 437 insertions, 1476 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 78b571129c9..c33f17dbe6f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -19,18 +19,16 @@
19#include <asm/unaligned.h> 19#include <asm/unaligned.h>
20 20
21#include "hw.h" 21#include "hw.h"
22#include "hw-ops.h"
22#include "rc.h" 23#include "rc.h"
23#include "initvals.h" 24#include "ar9003_mac.h"
24 25
25#define ATH9K_CLOCK_RATE_CCK 22 26#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 27#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 28#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
29#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
28 30
29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
30static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
31static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
32 struct ar5416_eeprom_def *pEepData,
33 u32 reg, u32 value);
34 32
35MODULE_AUTHOR("Atheros Communications"); 33MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -49,6 +47,39 @@ static void __exit ath9k_exit(void)
49} 47}
50module_exit(ath9k_exit); 48module_exit(ath9k_exit);
51 49
50/* Private hardware callbacks */
51
52static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55}
56
57static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
58{
59 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
60}
61
62static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
63{
64 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
65
66 return priv_ops->macversion_supported(ah->hw_version.macVersion);
67}
68
69static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
70 struct ath9k_channel *chan)
71{
72 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
73}
74
75static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
76{
77 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
78 return;
79
80 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
81}
82
52/********************/ 83/********************/
53/* Helper Functions */ 84/* Helper Functions */
54/********************/ 85/********************/
@@ -61,7 +92,11 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
61 return usecs *ATH9K_CLOCK_RATE_CCK; 92 return usecs *ATH9K_CLOCK_RATE_CCK;
62 if (conf->channel->band == IEEE80211_BAND_2GHZ) 93 if (conf->channel->band == IEEE80211_BAND_2GHZ)
63 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 94 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
64 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; 95
96 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
97 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
98 else
99 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
65} 100}
66 101
67static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 102static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
@@ -236,21 +271,6 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
236 } 271 }
237} 272}
238 273
239static int ath9k_hw_get_radiorev(struct ath_hw *ah)
240{
241 u32 val;
242 int i;
243
244 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
245
246 for (i = 0; i < 8; i++)
247 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
248 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
249 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
250
251 return ath9k_hw_reverse_bits(val, 8);
252}
253
254/************************************/ 274/************************************/
255/* HW Attach, Detach, Init Routines */ 275/* HW Attach, Detach, Init Routines */
256/************************************/ 276/************************************/
@@ -260,6 +280,8 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
260 if (AR_SREV_9100(ah)) 280 if (AR_SREV_9100(ah))
261 return; 281 return;
262 282
283 ENABLE_REGWRITE_BUFFER(ah);
284
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -271,20 +293,30 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
271 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
272 294
273 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 295 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
296
297 REGWRITE_BUFFER_FLUSH(ah);
298 DISABLE_REGWRITE_BUFFER(ah);
274} 299}
275 300
301/* This should work for all families including legacy */
276static bool ath9k_hw_chip_test(struct ath_hw *ah) 302static bool ath9k_hw_chip_test(struct ath_hw *ah)
277{ 303{
278 struct ath_common *common = ath9k_hw_common(ah); 304 struct ath_common *common = ath9k_hw_common(ah);
279 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 305 u32 regAddr[2] = { AR_STA_ID0 };
280 u32 regHold[2]; 306 u32 regHold[2];
281 u32 patternData[4] = { 0x55555555, 307 u32 patternData[4] = { 0x55555555,
282 0xaaaaaaaa, 308 0xaaaaaaaa,
283 0x66666666, 309 0x66666666,
284 0x99999999 }; 310 0x99999999 };
285 int i, j; 311 int i, j, loop_max;
312
313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
314 loop_max = 2;
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
316 } else
317 loop_max = 1;
286 318
287 for (i = 0; i < 2; i++) { 319 for (i = 0; i < loop_max; i++) {
288 u32 addr = regAddr[i]; 320 u32 addr = regAddr[i];
289 u32 wrData, rdData; 321 u32 wrData, rdData;
290 322
@@ -339,7 +371,13 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
339 ah->config.ofdm_trig_high = 500; 371 ah->config.ofdm_trig_high = 500;
340 ah->config.cck_trig_high = 200; 372 ah->config.cck_trig_high = 200;
341 ah->config.cck_trig_low = 100; 373 ah->config.cck_trig_low = 100;
342 ah->config.enable_ani = 1; 374
375 /*
376 * For now ANI is disabled for AR9003, it is still
377 * being tested.
378 */
379 if (!AR_SREV_9300_20_OR_LATER(ah))
380 ah->config.enable_ani = 1;
343 381
344 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 382 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
345 ah->config.spurchans[i][0] = AR_NO_SPUR; 383 ah->config.spurchans[i][0] = AR_NO_SPUR;
@@ -354,6 +392,12 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
354 ah->config.rx_intr_mitigation = true; 392 ah->config.rx_intr_mitigation = true;
355 393
356 /* 394 /*
395 * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
396 * used by AR9003, but it is showing reliability issues.
397 * It will take a while to fix so this is currently disabled.
398 */
399
400 /*
357 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 401 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
358 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 402 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
359 * This means we use it for all AR5416 devices, and the few 403 * This means we use it for all AR5416 devices, and the few
@@ -372,7 +416,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
372 if (num_possible_cpus() > 1) 416 if (num_possible_cpus() > 1)
373 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 417 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
374} 418}
375EXPORT_SYMBOL(ath9k_hw_init);
376 419
377static void ath9k_hw_init_defaults(struct ath_hw *ah) 420static void ath9k_hw_init_defaults(struct ath_hw *ah)
378{ 421{
@@ -386,8 +429,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
386 ah->hw_version.subvendorid = 0; 429 ah->hw_version.subvendorid = 0;
387 430
388 ah->ah_flags = 0; 431 ah->ah_flags = 0;
389 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
390 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
391 if (!AR_SREV_9100(ah)) 432 if (!AR_SREV_9100(ah))
392 ah->ah_flags = AH_USE_EEPROM; 433 ah->ah_flags = AH_USE_EEPROM;
393 434
@@ -400,44 +441,17 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
400 ah->power_mode = ATH9K_PM_UNDEFINED; 441 ah->power_mode = ATH9K_PM_UNDEFINED;
401} 442}
402 443
403static int ath9k_hw_rf_claim(struct ath_hw *ah)
404{
405 u32 val;
406
407 REG_WRITE(ah, AR_PHY(0), 0x00000007);
408
409 val = ath9k_hw_get_radiorev(ah);
410 switch (val & AR_RADIO_SREV_MAJOR) {
411 case 0:
412 val = AR_RAD5133_SREV_MAJOR;
413 break;
414 case AR_RAD5133_SREV_MAJOR:
415 case AR_RAD5122_SREV_MAJOR:
416 case AR_RAD2133_SREV_MAJOR:
417 case AR_RAD2122_SREV_MAJOR:
418 break;
419 default:
420 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
421 "Radio Chip Rev 0x%02X not supported\n",
422 val & AR_RADIO_SREV_MAJOR);
423 return -EOPNOTSUPP;
424 }
425
426 ah->hw_version.analog5GhzRev = val;
427
428 return 0;
429}
430
431static int ath9k_hw_init_macaddr(struct ath_hw *ah) 444static int ath9k_hw_init_macaddr(struct ath_hw *ah)
432{ 445{
433 struct ath_common *common = ath9k_hw_common(ah); 446 struct ath_common *common = ath9k_hw_common(ah);
434 u32 sum; 447 u32 sum;
435 int i; 448 int i;
436 u16 eeval; 449 u16 eeval;
450 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
437 451
438 sum = 0; 452 sum = 0;
439 for (i = 0; i < 3; i++) { 453 for (i = 0; i < 3; i++) {
440 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 454 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
441 sum += eeval; 455 sum += eeval;
442 common->macaddr[2 * i] = eeval >> 8; 456 common->macaddr[2 * i] = eeval >> 8;
443 common->macaddr[2 * i + 1] = eeval & 0xff; 457 common->macaddr[2 * i + 1] = eeval & 0xff;
@@ -448,64 +462,20 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
448 return 0; 462 return 0;
449} 463}
450 464
451static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
452{
453 u32 rxgain_type;
454
455 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
456 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
457
458 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
459 INIT_INI_ARRAY(&ah->iniModesRxGain,
460 ar9280Modes_backoff_13db_rxgain_9280_2,
461 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
462 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
463 INIT_INI_ARRAY(&ah->iniModesRxGain,
464 ar9280Modes_backoff_23db_rxgain_9280_2,
465 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
466 else
467 INIT_INI_ARRAY(&ah->iniModesRxGain,
468 ar9280Modes_original_rxgain_9280_2,
469 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
470 } else {
471 INIT_INI_ARRAY(&ah->iniModesRxGain,
472 ar9280Modes_original_rxgain_9280_2,
473 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
474 }
475}
476
477static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
478{
479 u32 txgain_type;
480
481 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
482 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
483
484 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
485 INIT_INI_ARRAY(&ah->iniModesTxGain,
486 ar9280Modes_high_power_tx_gain_9280_2,
487 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
488 else
489 INIT_INI_ARRAY(&ah->iniModesTxGain,
490 ar9280Modes_original_tx_gain_9280_2,
491 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
492 } else {
493 INIT_INI_ARRAY(&ah->iniModesTxGain,
494 ar9280Modes_original_tx_gain_9280_2,
495 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
496 }
497}
498
499static int ath9k_hw_post_init(struct ath_hw *ah) 465static int ath9k_hw_post_init(struct ath_hw *ah)
500{ 466{
501 int ecode; 467 int ecode;
502 468
503 if (!ath9k_hw_chip_test(ah)) 469 if (!AR_SREV_9271(ah)) {
504 return -ENODEV; 470 if (!ath9k_hw_chip_test(ah))
471 return -ENODEV;
472 }
505 473
506 ecode = ath9k_hw_rf_claim(ah); 474 if (!AR_SREV_9300_20_OR_LATER(ah)) {
507 if (ecode != 0) 475 ecode = ar9002_hw_rf_claim(ah);
508 return ecode; 476 if (ecode != 0)
477 return ecode;
478 }
509 479
510 ecode = ath9k_hw_eeprom_init(ah); 480 ecode = ath9k_hw_eeprom_init(ah);
511 if (ecode != 0) 481 if (ecode != 0)
@@ -516,14 +486,12 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
516 ah->eep_ops->get_eeprom_ver(ah), 486 ah->eep_ops->get_eeprom_ver(ah),
517 ah->eep_ops->get_eeprom_rev(ah)); 487 ah->eep_ops->get_eeprom_rev(ah));
518 488
519 if (!AR_SREV_9280_10_OR_LATER(ah)) { 489 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
520 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 490 if (ecode) {
521 if (ecode) { 491 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
522 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 492 "Failed allocating banks for "
523 "Failed allocating banks for " 493 "external radio\n");
524 "external radio\n"); 494 return ecode;
525 return ecode;
526 }
527 } 495 }
528 496
529 if (!AR_SREV_9100(ah)) { 497 if (!AR_SREV_9100(ah)) {
@@ -534,321 +502,22 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
534 return 0; 502 return 0;
535} 503}
536 504
537static bool ath9k_hw_devid_supported(u16 devid) 505static void ath9k_hw_attach_ops(struct ath_hw *ah)
538{ 506{
539 switch (devid) { 507 if (AR_SREV_9300_20_OR_LATER(ah))
540 case AR5416_DEVID_PCI: 508 ar9003_hw_attach_ops(ah);
541 case AR5416_DEVID_PCIE: 509 else
542 case AR5416_AR9100_DEVID: 510 ar9002_hw_attach_ops(ah);
543 case AR9160_DEVID_PCI:
544 case AR9280_DEVID_PCI:
545 case AR9280_DEVID_PCIE:
546 case AR9285_DEVID_PCIE:
547 case AR5416_DEVID_AR9287_PCI:
548 case AR5416_DEVID_AR9287_PCIE:
549 case AR9271_USB:
550 case AR2427_DEVID_PCIE:
551 return true;
552 default:
553 break;
554 }
555 return false;
556}
557
558static bool ath9k_hw_macversion_supported(u32 macversion)
559{
560 switch (macversion) {
561 case AR_SREV_VERSION_5416_PCI:
562 case AR_SREV_VERSION_5416_PCIE:
563 case AR_SREV_VERSION_9160:
564 case AR_SREV_VERSION_9100:
565 case AR_SREV_VERSION_9280:
566 case AR_SREV_VERSION_9285:
567 case AR_SREV_VERSION_9287:
568 case AR_SREV_VERSION_9271:
569 return true;
570 default:
571 break;
572 }
573 return false;
574}
575
576static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
577{
578 if (AR_SREV_9160_10_OR_LATER(ah)) {
579 if (AR_SREV_9280_10_OR_LATER(ah)) {
580 ah->iq_caldata.calData = &iq_cal_single_sample;
581 ah->adcgain_caldata.calData =
582 &adc_gain_cal_single_sample;
583 ah->adcdc_caldata.calData =
584 &adc_dc_cal_single_sample;
585 ah->adcdc_calinitdata.calData =
586 &adc_init_dc_cal;
587 } else {
588 ah->iq_caldata.calData = &iq_cal_multi_sample;
589 ah->adcgain_caldata.calData =
590 &adc_gain_cal_multi_sample;
591 ah->adcdc_caldata.calData =
592 &adc_dc_cal_multi_sample;
593 ah->adcdc_calinitdata.calData =
594 &adc_init_dc_cal;
595 }
596 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
597 }
598}
599
600static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
601{
602 if (AR_SREV_9271(ah)) {
603 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
604 ARRAY_SIZE(ar9271Modes_9271), 6);
605 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
606 ARRAY_SIZE(ar9271Common_9271), 2);
607 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
608 ar9271Modes_9271_1_0_only,
609 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
610 return;
611 }
612
613 if (AR_SREV_9287_11_OR_LATER(ah)) {
614 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
615 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
616 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
617 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
618 if (ah->config.pcie_clock_req)
619 INIT_INI_ARRAY(&ah->iniPcieSerdes,
620 ar9287PciePhy_clkreq_off_L1_9287_1_1,
621 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
622 else
623 INIT_INI_ARRAY(&ah->iniPcieSerdes,
624 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
625 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
626 2);
627 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
628 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
629 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
630 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
631 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
632
633 if (ah->config.pcie_clock_req)
634 INIT_INI_ARRAY(&ah->iniPcieSerdes,
635 ar9287PciePhy_clkreq_off_L1_9287_1_0,
636 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
637 else
638 INIT_INI_ARRAY(&ah->iniPcieSerdes,
639 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
640 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
641 2);
642 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
643
644
645 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
646 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
647 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
648 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
649
650 if (ah->config.pcie_clock_req) {
651 INIT_INI_ARRAY(&ah->iniPcieSerdes,
652 ar9285PciePhy_clkreq_off_L1_9285_1_2,
653 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
654 } else {
655 INIT_INI_ARRAY(&ah->iniPcieSerdes,
656 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
657 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
658 2);
659 }
660 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
661 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
662 ARRAY_SIZE(ar9285Modes_9285), 6);
663 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
664 ARRAY_SIZE(ar9285Common_9285), 2);
665
666 if (ah->config.pcie_clock_req) {
667 INIT_INI_ARRAY(&ah->iniPcieSerdes,
668 ar9285PciePhy_clkreq_off_L1_9285,
669 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
670 } else {
671 INIT_INI_ARRAY(&ah->iniPcieSerdes,
672 ar9285PciePhy_clkreq_always_on_L1_9285,
673 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
674 }
675 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
676 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
677 ARRAY_SIZE(ar9280Modes_9280_2), 6);
678 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
679 ARRAY_SIZE(ar9280Common_9280_2), 2);
680
681 if (ah->config.pcie_clock_req) {
682 INIT_INI_ARRAY(&ah->iniPcieSerdes,
683 ar9280PciePhy_clkreq_off_L1_9280,
684 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
685 } else {
686 INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 ar9280PciePhy_clkreq_always_on_L1_9280,
688 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
689 }
690 INIT_INI_ARRAY(&ah->iniModesAdditional,
691 ar9280Modes_fast_clock_9280_2,
692 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
693 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
694 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
695 ARRAY_SIZE(ar9280Modes_9280), 6);
696 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
697 ARRAY_SIZE(ar9280Common_9280), 2);
698 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
699 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
700 ARRAY_SIZE(ar5416Modes_9160), 6);
701 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
702 ARRAY_SIZE(ar5416Common_9160), 2);
703 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
704 ARRAY_SIZE(ar5416Bank0_9160), 2);
705 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
706 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
707 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
708 ARRAY_SIZE(ar5416Bank1_9160), 2);
709 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
710 ARRAY_SIZE(ar5416Bank2_9160), 2);
711 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
712 ARRAY_SIZE(ar5416Bank3_9160), 3);
713 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
714 ARRAY_SIZE(ar5416Bank6_9160), 3);
715 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
716 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
717 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
718 ARRAY_SIZE(ar5416Bank7_9160), 2);
719 if (AR_SREV_9160_11(ah)) {
720 INIT_INI_ARRAY(&ah->iniAddac,
721 ar5416Addac_91601_1,
722 ARRAY_SIZE(ar5416Addac_91601_1), 2);
723 } else {
724 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
725 ARRAY_SIZE(ar5416Addac_9160), 2);
726 }
727 } else if (AR_SREV_9100_OR_LATER(ah)) {
728 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
729 ARRAY_SIZE(ar5416Modes_9100), 6);
730 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
731 ARRAY_SIZE(ar5416Common_9100), 2);
732 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
733 ARRAY_SIZE(ar5416Bank0_9100), 2);
734 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
735 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
736 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
737 ARRAY_SIZE(ar5416Bank1_9100), 2);
738 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
739 ARRAY_SIZE(ar5416Bank2_9100), 2);
740 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
741 ARRAY_SIZE(ar5416Bank3_9100), 3);
742 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
743 ARRAY_SIZE(ar5416Bank6_9100), 3);
744 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
745 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
746 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
747 ARRAY_SIZE(ar5416Bank7_9100), 2);
748 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
749 ARRAY_SIZE(ar5416Addac_9100), 2);
750 } else {
751 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
752 ARRAY_SIZE(ar5416Modes), 6);
753 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
754 ARRAY_SIZE(ar5416Common), 2);
755 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
756 ARRAY_SIZE(ar5416Bank0), 2);
757 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
758 ARRAY_SIZE(ar5416BB_RfGain), 3);
759 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
760 ARRAY_SIZE(ar5416Bank1), 2);
761 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
762 ARRAY_SIZE(ar5416Bank2), 2);
763 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
764 ARRAY_SIZE(ar5416Bank3), 3);
765 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
766 ARRAY_SIZE(ar5416Bank6), 3);
767 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
768 ARRAY_SIZE(ar5416Bank6TPC), 3);
769 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
770 ARRAY_SIZE(ar5416Bank7), 2);
771 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
772 ARRAY_SIZE(ar5416Addac), 2);
773 }
774}
775
776static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
777{
778 if (AR_SREV_9287_11_OR_LATER(ah))
779 INIT_INI_ARRAY(&ah->iniModesRxGain,
780 ar9287Modes_rx_gain_9287_1_1,
781 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
782 else if (AR_SREV_9287_10(ah))
783 INIT_INI_ARRAY(&ah->iniModesRxGain,
784 ar9287Modes_rx_gain_9287_1_0,
785 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
786 else if (AR_SREV_9280_20(ah))
787 ath9k_hw_init_rxgain_ini(ah);
788
789 if (AR_SREV_9287_11_OR_LATER(ah)) {
790 INIT_INI_ARRAY(&ah->iniModesTxGain,
791 ar9287Modes_tx_gain_9287_1_1,
792 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
793 } else if (AR_SREV_9287_10(ah)) {
794 INIT_INI_ARRAY(&ah->iniModesTxGain,
795 ar9287Modes_tx_gain_9287_1_0,
796 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
797 } else if (AR_SREV_9280_20(ah)) {
798 ath9k_hw_init_txgain_ini(ah);
799 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
800 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
801
802 /* txgain table */
803 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
804 INIT_INI_ARRAY(&ah->iniModesTxGain,
805 ar9285Modes_high_power_tx_gain_9285_1_2,
806 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
807 } else {
808 INIT_INI_ARRAY(&ah->iniModesTxGain,
809 ar9285Modes_original_tx_gain_9285_1_2,
810 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
811 }
812
813 }
814}
815
816static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
817{
818 u32 i, j;
819
820 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
821
822 /* EEPROM Fixup */
823 for (i = 0; i < ah->iniModes.ia_rows; i++) {
824 u32 reg = INI_RA(&ah->iniModes, i, 0);
825
826 for (j = 1; j < ah->iniModes.ia_columns; j++) {
827 u32 val = INI_RA(&ah->iniModes, i, j);
828
829 INI_RA(&ah->iniModes, i, j) =
830 ath9k_hw_ini_fixup(ah,
831 &ah->eeprom.def,
832 reg, val);
833 }
834 }
835 }
836} 511}
837 512
838int ath9k_hw_init(struct ath_hw *ah) 513/* Called for all hardware families */
514static int __ath9k_hw_init(struct ath_hw *ah)
839{ 515{
840 struct ath_common *common = ath9k_hw_common(ah); 516 struct ath_common *common = ath9k_hw_common(ah);
841 int r = 0; 517 int r = 0;
842 518
843 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) { 519 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
844 ath_print(common, ATH_DBG_FATAL, 520 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
845 "Unsupported device ID: 0x%0x\n",
846 ah->hw_version.devid);
847 return -EOPNOTSUPP;
848 }
849
850 ath9k_hw_init_defaults(ah);
851 ath9k_hw_init_config(ah);
852 521
853 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 522 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
854 ath_print(common, ATH_DBG_FATAL, 523 ath_print(common, ATH_DBG_FATAL,
@@ -856,6 +525,11 @@ int ath9k_hw_init(struct ath_hw *ah)
856 return -EIO; 525 return -EIO;
857 } 526 }
858 527
528 ath9k_hw_init_defaults(ah);
529 ath9k_hw_init_config(ah);
530
531 ath9k_hw_attach_ops(ah);
532
859 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 533 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
860 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 534 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
861 return -EIO; 535 return -EIO;
@@ -880,7 +554,7 @@ int ath9k_hw_init(struct ath_hw *ah)
880 else 554 else
881 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 555 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
882 556
883 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 557 if (!ath9k_hw_macversion_supported(ah)) {
884 ath_print(common, ATH_DBG_FATAL, 558 ath_print(common, ATH_DBG_FATAL,
885 "Mac Chip Rev 0x%02x.%x is not supported by " 559 "Mac Chip Rev 0x%02x.%x is not supported by "
886 "this driver\n", ah->hw_version.macVersion, 560 "this driver\n", ah->hw_version.macVersion,
@@ -888,45 +562,45 @@ int ath9k_hw_init(struct ath_hw *ah)
888 return -EOPNOTSUPP; 562 return -EOPNOTSUPP;
889 } 563 }
890 564
891 if (AR_SREV_9100(ah)) { 565 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
892 ah->iq_caldata.calData = &iq_cal_multi_sample;
893 ah->supp_cals = IQ_MISMATCH_CAL;
894 ah->is_pciexpress = false;
895 }
896
897 if (AR_SREV_9271(ah))
898 ah->is_pciexpress = false; 566 ah->is_pciexpress = false;
899 567
900 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 568 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
901
902 ath9k_hw_init_cal_settings(ah); 569 ath9k_hw_init_cal_settings(ah);
903 570
904 ah->ani_function = ATH9K_ANI_ALL; 571 ah->ani_function = ATH9K_ANI_ALL;
905 if (AR_SREV_9280_10_OR_LATER(ah)) { 572 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
906 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 573 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
907 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
908 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
909 } else {
910 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
911 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
912 }
913 574
914 ath9k_hw_init_mode_regs(ah); 575 ath9k_hw_init_mode_regs(ah);
915 576
577 /*
578 * Configire PCIE after Ini init. SERDES values now come from ini file
579 * This enables PCIe low power mode.
580 */
581 if (AR_SREV_9300_20_OR_LATER(ah)) {
582 u32 regval;
583 unsigned int i;
584
585 /* Set Bits 16 and 17 in the AR_WA register. */
586 regval = REG_READ(ah, AR_WA);
587 regval |= 0x00030000;
588 REG_WRITE(ah, AR_WA, regval);
589
590 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
591 REG_WRITE(ah,
592 INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
593 INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
594 }
595 }
596
916 if (ah->is_pciexpress) 597 if (ah->is_pciexpress)
917 ath9k_hw_configpcipowersave(ah, 0, 0); 598 ath9k_hw_configpcipowersave(ah, 0, 0);
918 else 599 else
919 ath9k_hw_disablepcie(ah); 600 ath9k_hw_disablepcie(ah);
920 601
921 /* Support for Japan ch.14 (2484) spread */ 602 if (!AR_SREV_9300_20_OR_LATER(ah))
922 if (AR_SREV_9287_11_OR_LATER(ah)) { 603 ar9002_hw_cck_chan14_spread(ah);
923 INIT_INI_ARRAY(&ah->iniCckfirNormal,
924 ar9287Common_normal_cck_fir_coeff_92871_1,
925 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
926 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
927 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
928 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
929 }
930 604
931 r = ath9k_hw_post_init(ah); 605 r = ath9k_hw_post_init(ah);
932 if (r) 606 if (r)
@@ -937,8 +611,6 @@ int ath9k_hw_init(struct ath_hw *ah)
937 if (r) 611 if (r)
938 return r; 612 return r;
939 613
940 ath9k_hw_init_eeprom_fix(ah);
941
942 r = ath9k_hw_init_macaddr(ah); 614 r = ath9k_hw_init_macaddr(ah);
943 if (r) { 615 if (r) {
944 ath_print(common, ATH_DBG_FATAL, 616 ath_print(common, ATH_DBG_FATAL,
@@ -951,6 +623,9 @@ int ath9k_hw_init(struct ath_hw *ah)
951 else 623 else
952 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 624 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
953 625
626 if (AR_SREV_9300_20_OR_LATER(ah))
627 ar9003_hw_set_nf_limits(ah);
628
954 ath9k_init_nfcal_hist_buffer(ah); 629 ath9k_init_nfcal_hist_buffer(ah);
955 630
956 common->state = ATH_HW_INITIALIZED; 631 common->state = ATH_HW_INITIALIZED;
@@ -958,24 +633,50 @@ int ath9k_hw_init(struct ath_hw *ah)
958 return 0; 633 return 0;
959} 634}
960 635
961static void ath9k_hw_init_bb(struct ath_hw *ah, 636int ath9k_hw_init(struct ath_hw *ah)
962 struct ath9k_channel *chan)
963{ 637{
964 u32 synthDelay; 638 int ret;
639 struct ath_common *common = ath9k_hw_common(ah);
965 640
966 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 641 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
967 if (IS_CHAN_B(chan)) 642 switch (ah->hw_version.devid) {
968 synthDelay = (4 * synthDelay) / 22; 643 case AR5416_DEVID_PCI:
969 else 644 case AR5416_DEVID_PCIE:
970 synthDelay /= 10; 645 case AR5416_AR9100_DEVID:
646 case AR9160_DEVID_PCI:
647 case AR9280_DEVID_PCI:
648 case AR9280_DEVID_PCIE:
649 case AR9285_DEVID_PCIE:
650 case AR9287_DEVID_PCI:
651 case AR9287_DEVID_PCIE:
652 case AR2427_DEVID_PCIE:
653 case AR9300_DEVID_PCIE:
654 break;
655 default:
656 if (common->bus_ops->ath_bus_type == ATH_USB)
657 break;
658 ath_print(common, ATH_DBG_FATAL,
659 "Hardware device ID 0x%04x not supported\n",
660 ah->hw_version.devid);
661 return -EOPNOTSUPP;
662 }
971 663
972 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 664 ret = __ath9k_hw_init(ah);
665 if (ret) {
666 ath_print(common, ATH_DBG_FATAL,
667 "Unable to initialize hardware; "
668 "initialization status: %d\n", ret);
669 return ret;
670 }
973 671
974 udelay(synthDelay + BASE_ACTIVATE_DELAY); 672 return 0;
975} 673}
674EXPORT_SYMBOL(ath9k_hw_init);
976 675
977static void ath9k_hw_init_qos(struct ath_hw *ah) 676static void ath9k_hw_init_qos(struct ath_hw *ah)
978{ 677{
678 ENABLE_REGWRITE_BUFFER(ah);
679
979 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 680 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
980 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 681 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
981 682
@@ -989,105 +690,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
989 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 690 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
990 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 691 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
991 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 692 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
992}
993
994static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
995{
996 u32 lcr;
997 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
998
999 lcr = REG_READ(ah , 0x5100c);
1000 lcr |= 0x80;
1001 693
1002 REG_WRITE(ah, 0x5100c, lcr); 694 REGWRITE_BUFFER_FLUSH(ah);
1003 REG_WRITE(ah, 0x51004, (baud_divider >> 8)); 695 DISABLE_REGWRITE_BUFFER(ah);
1004 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1005
1006 lcr &= ~0x80;
1007 REG_WRITE(ah, 0x5100c, lcr);
1008} 696}
1009 697
1010static void ath9k_hw_init_pll(struct ath_hw *ah, 698static void ath9k_hw_init_pll(struct ath_hw *ah,
1011 struct ath9k_channel *chan) 699 struct ath9k_channel *chan)
1012{ 700{
1013 u32 pll; 701 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
1014
1015 if (AR_SREV_9100(ah)) {
1016 if (chan && IS_CHAN_5GHZ(chan))
1017 pll = 0x1450;
1018 else
1019 pll = 0x1458;
1020 } else {
1021 if (AR_SREV_9280_10_OR_LATER(ah)) {
1022 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1023
1024 if (chan && IS_CHAN_HALF_RATE(chan))
1025 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1026 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1027 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1028
1029 if (chan && IS_CHAN_5GHZ(chan)) {
1030 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1031
1032
1033 if (AR_SREV_9280_20(ah)) {
1034 if (((chan->channel % 20) == 0)
1035 || ((chan->channel % 10) == 0))
1036 pll = 0x2850;
1037 else
1038 pll = 0x142c;
1039 }
1040 } else {
1041 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1042 }
1043
1044 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1045
1046 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1047
1048 if (chan && IS_CHAN_HALF_RATE(chan))
1049 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1050 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1051 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1052
1053 if (chan && IS_CHAN_5GHZ(chan))
1054 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1055 else
1056 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1057 } else {
1058 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1059
1060 if (chan && IS_CHAN_HALF_RATE(chan))
1061 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1062 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1063 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1064 702
1065 if (chan && IS_CHAN_5GHZ(chan))
1066 pll |= SM(0xa, AR_RTC_PLL_DIV);
1067 else
1068 pll |= SM(0xb, AR_RTC_PLL_DIV);
1069 }
1070 }
1071 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 703 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1072 704
1073 /* Switch the core clock for ar9271 to 117Mhz */ 705 /* Switch the core clock for ar9271 to 117Mhz */
1074 if (AR_SREV_9271(ah)) { 706 if (AR_SREV_9271(ah)) {
1075 if ((pll == 0x142c) || (pll == 0x2850) ) { 707 udelay(500);
1076 udelay(500); 708 REG_WRITE(ah, 0x50040, 0x304);
1077 /* set CLKOBS to output AHB clock */
1078 REG_WRITE(ah, 0x7020, 0xe);
1079 /*
1080 * 0x304: 117Mhz, ahb_ratio: 1x1
1081 * 0x306: 40Mhz, ahb_ratio: 1x1
1082 */
1083 REG_WRITE(ah, 0x50040, 0x304);
1084 /*
1085 * makes adjustments for the baud dividor to keep the
1086 * targetted baud rate based on the used core clock.
1087 */
1088 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1089 AR9271_TARGET_BAUD_RATE);
1090 }
1091 } 709 }
1092 710
1093 udelay(RTC_PLL_SETTLE_DELAY); 711 udelay(RTC_PLL_SETTLE_DELAY);
@@ -1095,70 +713,58 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1095 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 713 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1096} 714}
1097 715
1098static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1099{
1100 int rx_chainmask, tx_chainmask;
1101
1102 rx_chainmask = ah->rxchainmask;
1103 tx_chainmask = ah->txchainmask;
1104
1105 switch (rx_chainmask) {
1106 case 0x5:
1107 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108 AR_PHY_SWAP_ALT_CHAIN);
1109 case 0x3:
1110 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113 break;
1114 }
1115 case 0x1:
1116 case 0x2:
1117 case 0x7:
1118 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1119 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1120 break;
1121 default:
1122 break;
1123 }
1124
1125 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1126 if (tx_chainmask == 0x5) {
1127 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1128 AR_PHY_SWAP_ALT_CHAIN);
1129 }
1130 if (AR_SREV_9100(ah))
1131 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1132 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1133}
1134
1135static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 716static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1136 enum nl80211_iftype opmode) 717 enum nl80211_iftype opmode)
1137{ 718{
1138 ah->mask_reg = AR_IMR_TXERR | 719 u32 imr_reg = AR_IMR_TXERR |
1139 AR_IMR_TXURN | 720 AR_IMR_TXURN |
1140 AR_IMR_RXERR | 721 AR_IMR_RXERR |
1141 AR_IMR_RXORN | 722 AR_IMR_RXORN |
1142 AR_IMR_BCNMISC; 723 AR_IMR_BCNMISC;
1143 724
1144 if (ah->config.rx_intr_mitigation) 725 if (AR_SREV_9300_20_OR_LATER(ah)) {
1145 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 726 imr_reg |= AR_IMR_RXOK_HP;
1146 else 727 if (ah->config.rx_intr_mitigation)
1147 ah->mask_reg |= AR_IMR_RXOK; 728 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
729 else
730 imr_reg |= AR_IMR_RXOK_LP;
1148 731
1149 ah->mask_reg |= AR_IMR_TXOK; 732 } else {
733 if (ah->config.rx_intr_mitigation)
734 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
735 else
736 imr_reg |= AR_IMR_RXOK;
737 }
738
739 if (ah->config.tx_intr_mitigation)
740 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
741 else
742 imr_reg |= AR_IMR_TXOK;
1150 743
1151 if (opmode == NL80211_IFTYPE_AP) 744 if (opmode == NL80211_IFTYPE_AP)
1152 ah->mask_reg |= AR_IMR_MIB; 745 imr_reg |= AR_IMR_MIB;
746
747 ENABLE_REGWRITE_BUFFER(ah);
1153 748
1154 REG_WRITE(ah, AR_IMR, ah->mask_reg); 749 REG_WRITE(ah, AR_IMR, imr_reg);
1155 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); 750 ah->imrs2_reg |= AR_IMR_S2_GTT;
751 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1156 752
1157 if (!AR_SREV_9100(ah)) { 753 if (!AR_SREV_9100(ah)) {
1158 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 754 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1159 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 755 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1160 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 756 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1161 } 757 }
758
759 REGWRITE_BUFFER_FLUSH(ah);
760 DISABLE_REGWRITE_BUFFER(ah);
761
762 if (AR_SREV_9300_20_OR_LATER(ah)) {
763 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
764 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
765 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
766 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
767 }
1162} 768}
1163 769
1164static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 770static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
@@ -1241,19 +847,13 @@ void ath9k_hw_deinit(struct ath_hw *ah)
1241{ 847{
1242 struct ath_common *common = ath9k_hw_common(ah); 848 struct ath_common *common = ath9k_hw_common(ah);
1243 849
1244 if (common->state <= ATH_HW_INITIALIZED) 850 if (common->state < ATH_HW_INITIALIZED)
1245 goto free_hw; 851 goto free_hw;
1246 852
1247 if (!AR_SREV_9100(ah))
1248 ath9k_hw_ani_disable(ah);
1249
1250 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 853 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1251 854
1252free_hw: 855free_hw:
1253 if (!AR_SREV_9280_10_OR_LATER(ah)) 856 ath9k_hw_rf_free_ext_banks(ah);
1254 ath9k_hw_rf_free_ext_banks(ah);
1255 kfree(ah);
1256 ah = NULL;
1257} 857}
1258EXPORT_SYMBOL(ath9k_hw_deinit); 858EXPORT_SYMBOL(ath9k_hw_deinit);
1259 859
@@ -1261,136 +861,7 @@ EXPORT_SYMBOL(ath9k_hw_deinit);
1261/* INI */ 861/* INI */
1262/*******/ 862/*******/
1263 863
1264static void ath9k_hw_override_ini(struct ath_hw *ah, 864u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1265 struct ath9k_channel *chan)
1266{
1267 u32 val;
1268
1269 if (AR_SREV_9271(ah)) {
1270 /*
1271 * Enable spectral scan to solution for issues with stuck
1272 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1273 * AR9271 1.1
1274 */
1275 if (AR_SREV_9271_10(ah)) {
1276 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1277 AR_PHY_SPECTRAL_SCAN_ENABLE;
1278 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1279 }
1280 else if (AR_SREV_9271_11(ah))
1281 /*
1282 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1283 * present on AR9271 1.1
1284 */
1285 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1286 return;
1287 }
1288
1289 /*
1290 * Set the RX_ABORT and RX_DIS and clear if off only after
1291 * RXE is set for MAC. This prevents frames with corrupted
1292 * descriptor status.
1293 */
1294 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1295
1296 if (AR_SREV_9280_10_OR_LATER(ah)) {
1297 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1298 (~AR_PCU_MISC_MODE2_HWWAR1);
1299
1300 if (AR_SREV_9287_10_OR_LATER(ah))
1301 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1302
1303 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1304 }
1305
1306 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1307 AR_SREV_9280_10_OR_LATER(ah))
1308 return;
1309 /*
1310 * Disable BB clock gating
1311 * Necessary to avoid issues on AR5416 2.0
1312 */
1313 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1314
1315 /*
1316 * Disable RIFS search on some chips to avoid baseband
1317 * hang issues.
1318 */
1319 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1320 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1321 val &= ~AR_PHY_RIFS_INIT_DELAY;
1322 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1323 }
1324}
1325
1326static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1327 struct ar5416_eeprom_def *pEepData,
1328 u32 reg, u32 value)
1329{
1330 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1331 struct ath_common *common = ath9k_hw_common(ah);
1332
1333 switch (ah->hw_version.devid) {
1334 case AR9280_DEVID_PCI:
1335 if (reg == 0x7894) {
1336 ath_print(common, ATH_DBG_EEPROM,
1337 "ini VAL: %x EEPROM: %x\n", value,
1338 (pBase->version & 0xff));
1339
1340 if ((pBase->version & 0xff) > 0x0a) {
1341 ath_print(common, ATH_DBG_EEPROM,
1342 "PWDCLKIND: %d\n",
1343 pBase->pwdclkind);
1344 value &= ~AR_AN_TOP2_PWDCLKIND;
1345 value |= AR_AN_TOP2_PWDCLKIND &
1346 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1347 } else {
1348 ath_print(common, ATH_DBG_EEPROM,
1349 "PWDCLKIND Earlier Rev\n");
1350 }
1351
1352 ath_print(common, ATH_DBG_EEPROM,
1353 "final ini VAL: %x\n", value);
1354 }
1355 break;
1356 }
1357
1358 return value;
1359}
1360
1361static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1362 struct ar5416_eeprom_def *pEepData,
1363 u32 reg, u32 value)
1364{
1365 if (ah->eep_map == EEP_MAP_4KBITS)
1366 return value;
1367 else
1368 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1369}
1370
1371static void ath9k_olc_init(struct ath_hw *ah)
1372{
1373 u32 i;
1374
1375 if (OLC_FOR_AR9287_10_LATER) {
1376 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1377 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1378 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1379 AR9287_AN_TXPC0_TXPCMODE,
1380 AR9287_AN_TXPC0_TXPCMODE_S,
1381 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1382 udelay(100);
1383 } else {
1384 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1385 ah->originalGain[i] =
1386 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1387 AR_PHY_TX_GAIN);
1388 ah->PDADCdelta = 0;
1389 }
1390}
1391
1392static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1393 struct ath9k_channel *chan)
1394{ 865{
1395 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 866 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1396 867
@@ -1404,173 +875,24 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1404 return ctl; 875 return ctl;
1405} 876}
1406 877
1407static int ath9k_hw_process_ini(struct ath_hw *ah,
1408 struct ath9k_channel *chan)
1409{
1410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1411 int i, regWrites = 0;
1412 struct ieee80211_channel *channel = chan->chan;
1413 u32 modesIndex, freqIndex;
1414
1415 switch (chan->chanmode) {
1416 case CHANNEL_A:
1417 case CHANNEL_A_HT20:
1418 modesIndex = 1;
1419 freqIndex = 1;
1420 break;
1421 case CHANNEL_A_HT40PLUS:
1422 case CHANNEL_A_HT40MINUS:
1423 modesIndex = 2;
1424 freqIndex = 1;
1425 break;
1426 case CHANNEL_G:
1427 case CHANNEL_G_HT20:
1428 case CHANNEL_B:
1429 modesIndex = 4;
1430 freqIndex = 2;
1431 break;
1432 case CHANNEL_G_HT40PLUS:
1433 case CHANNEL_G_HT40MINUS:
1434 modesIndex = 3;
1435 freqIndex = 2;
1436 break;
1437
1438 default:
1439 return -EINVAL;
1440 }
1441
1442 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1443 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1444 ah->eep_ops->set_addac(ah, chan);
1445
1446 if (AR_SREV_5416_22_OR_LATER(ah)) {
1447 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1448 } else {
1449 struct ar5416IniArray temp;
1450 u32 addacSize =
1451 sizeof(u32) * ah->iniAddac.ia_rows *
1452 ah->iniAddac.ia_columns;
1453
1454 memcpy(ah->addac5416_21,
1455 ah->iniAddac.ia_array, addacSize);
1456
1457 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1458
1459 temp.ia_array = ah->addac5416_21;
1460 temp.ia_columns = ah->iniAddac.ia_columns;
1461 temp.ia_rows = ah->iniAddac.ia_rows;
1462 REG_WRITE_ARRAY(&temp, 1, regWrites);
1463 }
1464
1465 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1466
1467 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1468 u32 reg = INI_RA(&ah->iniModes, i, 0);
1469 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1470
1471 REG_WRITE(ah, reg, val);
1472
1473 if (reg >= 0x7800 && reg < 0x78a0
1474 && ah->config.analog_shiftreg) {
1475 udelay(100);
1476 }
1477
1478 DO_DELAY(regWrites);
1479 }
1480
1481 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1482 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1483
1484 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1485 AR_SREV_9287_10_OR_LATER(ah))
1486 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1487
1488 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1489 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1490 u32 val = INI_RA(&ah->iniCommon, i, 1);
1491
1492 REG_WRITE(ah, reg, val);
1493
1494 if (reg >= 0x7800 && reg < 0x78a0
1495 && ah->config.analog_shiftreg) {
1496 udelay(100);
1497 }
1498
1499 DO_DELAY(regWrites);
1500 }
1501
1502 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1503
1504 if (AR_SREV_9271_10(ah))
1505 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1506 modesIndex, regWrites);
1507
1508 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1509 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1510 regWrites);
1511 }
1512
1513 ath9k_hw_override_ini(ah, chan);
1514 ath9k_hw_set_regs(ah, chan);
1515 ath9k_hw_init_chain_masks(ah);
1516
1517 if (OLC_FOR_AR9280_20_LATER)
1518 ath9k_olc_init(ah);
1519
1520 ah->eep_ops->set_txpower(ah, chan,
1521 ath9k_regd_get_ctl(regulatory, chan),
1522 channel->max_antenna_gain * 2,
1523 channel->max_power * 2,
1524 min((u32) MAX_RATE_POWER,
1525 (u32) regulatory->power_limit));
1526
1527 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1528 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1529 "ar5416SetRfRegs failed\n");
1530 return -EIO;
1531 }
1532
1533 return 0;
1534}
1535
1536/****************************************/ 878/****************************************/
1537/* Reset and Channel Switching Routines */ 879/* Reset and Channel Switching Routines */
1538/****************************************/ 880/****************************************/
1539 881
1540static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1541{
1542 u32 rfMode = 0;
1543
1544 if (chan == NULL)
1545 return;
1546
1547 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1548 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1549
1550 if (!AR_SREV_9280_10_OR_LATER(ah))
1551 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1552 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1553
1554 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1555 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1556
1557 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1558}
1559
1560static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1561{
1562 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1563}
1564
1565static inline void ath9k_hw_set_dma(struct ath_hw *ah) 882static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1566{ 883{
884 struct ath_common *common = ath9k_hw_common(ah);
1567 u32 regval; 885 u32 regval;
1568 886
887 ENABLE_REGWRITE_BUFFER(ah);
888
1569 /* 889 /*
1570 * set AHB_MODE not to do cacheline prefetches 890 * set AHB_MODE not to do cacheline prefetches
1571 */ 891 */
1572 regval = REG_READ(ah, AR_AHB_MODE); 892 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1573 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 893 regval = REG_READ(ah, AR_AHB_MODE);
894 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
895 }
1574 896
1575 /* 897 /*
1576 * let mac dma reads be in 128 byte chunks 898 * let mac dma reads be in 128 byte chunks
@@ -1578,12 +900,18 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1578 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 900 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1579 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 901 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1580 902
903 REGWRITE_BUFFER_FLUSH(ah);
904 DISABLE_REGWRITE_BUFFER(ah);
905
1581 /* 906 /*
1582 * Restore TX Trigger Level to its pre-reset value. 907 * Restore TX Trigger Level to its pre-reset value.
1583 * The initial value depends on whether aggregation is enabled, and is 908 * The initial value depends on whether aggregation is enabled, and is
1584 * adjusted whenever underruns are detected. 909 * adjusted whenever underruns are detected.
1585 */ 910 */
1586 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 911 if (!AR_SREV_9300_20_OR_LATER(ah))
912 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
913
914 ENABLE_REGWRITE_BUFFER(ah);
1587 915
1588 /* 916 /*
1589 * let mac dma writes be in 128 byte chunks 917 * let mac dma writes be in 128 byte chunks
@@ -1596,6 +924,14 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1596 */ 924 */
1597 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 925 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1598 926
927 if (AR_SREV_9300_20_OR_LATER(ah)) {
928 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
929 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
930
931 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
932 ah->caps.rx_status_len);
933 }
934
1599 /* 935 /*
1600 * reduce the number of usable entries in PCU TXBUF to avoid 936 * reduce the number of usable entries in PCU TXBUF to avoid
1601 * wrap around issues. 937 * wrap around issues.
@@ -1611,6 +947,12 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1611 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 947 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1612 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 948 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1613 } 949 }
950
951 REGWRITE_BUFFER_FLUSH(ah);
952 DISABLE_REGWRITE_BUFFER(ah);
953
954 if (AR_SREV_9300_20_OR_LATER(ah))
955 ath9k_hw_reset_txstatus_ring(ah);
1614} 956}
1615 957
1616static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 958static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
@@ -1638,10 +980,8 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1638 } 980 }
1639} 981}
1640 982
1641static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, 983void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1642 u32 coef_scaled, 984 u32 *coef_mantissa, u32 *coef_exponent)
1643 u32 *coef_mantissa,
1644 u32 *coef_exponent)
1645{ 985{
1646 u32 coef_exp, coef_man; 986 u32 coef_exp, coef_man;
1647 987
@@ -1657,40 +997,6 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1657 *coef_exponent = coef_exp - 16; 997 *coef_exponent = coef_exp - 16;
1658} 998}
1659 999
1660static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1661 struct ath9k_channel *chan)
1662{
1663 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1664 u32 clockMhzScaled = 0x64000000;
1665 struct chan_centers centers;
1666
1667 if (IS_CHAN_HALF_RATE(chan))
1668 clockMhzScaled = clockMhzScaled >> 1;
1669 else if (IS_CHAN_QUARTER_RATE(chan))
1670 clockMhzScaled = clockMhzScaled >> 2;
1671
1672 ath9k_hw_get_channel_centers(ah, chan, &centers);
1673 coef_scaled = clockMhzScaled / centers.synth_center;
1674
1675 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1676 &ds_coef_exp);
1677
1678 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1679 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1680 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1681 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1682
1683 coef_scaled = (9 * coef_scaled) / 10;
1684
1685 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1686 &ds_coef_exp);
1687
1688 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1689 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1690 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1691 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1692}
1693
1694static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1000static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1695{ 1001{
1696 u32 rst_flags; 1002 u32 rst_flags;
@@ -1704,6 +1010,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1704 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1010 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1705 } 1011 }
1706 1012
1013 ENABLE_REGWRITE_BUFFER(ah);
1014
1707 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1015 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1708 AR_RTC_FORCE_WAKE_ON_INT); 1016 AR_RTC_FORCE_WAKE_ON_INT);
1709 1017
@@ -1715,11 +1023,16 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1715 if (tmpReg & 1023 if (tmpReg &
1716 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1024 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1717 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1025 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1026 u32 val;
1718 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1027 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1719 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1028
1720 } else { 1029 val = AR_RC_HOSTIF;
1030 if (!AR_SREV_9300_20_OR_LATER(ah))
1031 val |= AR_RC_AHB;
1032 REG_WRITE(ah, AR_RC, val);
1033
1034 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1721 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1035 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1722 }
1723 1036
1724 rst_flags = AR_RTC_RC_MAC_WARM; 1037 rst_flags = AR_RTC_RC_MAC_WARM;
1725 if (type == ATH9K_RESET_COLD) 1038 if (type == ATH9K_RESET_COLD)
@@ -1727,6 +1040,10 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1727 } 1040 }
1728 1041
1729 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1042 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1043
1044 REGWRITE_BUFFER_FLUSH(ah);
1045 DISABLE_REGWRITE_BUFFER(ah);
1046
1730 udelay(50); 1047 udelay(50);
1731 1048
1732 REG_WRITE(ah, AR_RTC_RC, 0); 1049 REG_WRITE(ah, AR_RTC_RC, 0);
@@ -1747,16 +1064,23 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1747 1064
1748static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1065static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1749{ 1066{
1067 ENABLE_REGWRITE_BUFFER(ah);
1068
1750 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1069 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1751 AR_RTC_FORCE_WAKE_ON_INT); 1070 AR_RTC_FORCE_WAKE_ON_INT);
1752 1071
1753 if (!AR_SREV_9100(ah)) 1072 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1754 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1073 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1755 1074
1756 REG_WRITE(ah, AR_RTC_RESET, 0); 1075 REG_WRITE(ah, AR_RTC_RESET, 0);
1757 udelay(2);
1758 1076
1759 if (!AR_SREV_9100(ah)) 1077 REGWRITE_BUFFER_FLUSH(ah);
1078 DISABLE_REGWRITE_BUFFER(ah);
1079
1080 if (!AR_SREV_9300_20_OR_LATER(ah))
1081 udelay(2);
1082
1083 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1760 REG_WRITE(ah, AR_RC, 0); 1084 REG_WRITE(ah, AR_RC, 0);
1761 1085
1762 REG_WRITE(ah, AR_RTC_RESET, 1); 1086 REG_WRITE(ah, AR_RTC_RESET, 1);
@@ -1792,34 +1116,6 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1792 } 1116 }
1793} 1117}
1794 1118
1795static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1796{
1797 u32 phymode;
1798 u32 enableDacFifo = 0;
1799
1800 if (AR_SREV_9285_10_OR_LATER(ah))
1801 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1802 AR_PHY_FC_ENABLE_DAC_FIFO);
1803
1804 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1805 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1806
1807 if (IS_CHAN_HT40(chan)) {
1808 phymode |= AR_PHY_FC_DYN2040_EN;
1809
1810 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1811 (chan->chanmode == CHANNEL_G_HT40PLUS))
1812 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1813
1814 }
1815 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1816
1817 ath9k_hw_set11nmac2040(ah);
1818
1819 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1820 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1821}
1822
1823static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1119static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1824 struct ath9k_channel *chan) 1120 struct ath9k_channel *chan)
1825{ 1121{
@@ -1845,7 +1141,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1845 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1141 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1846 struct ath_common *common = ath9k_hw_common(ah); 1142 struct ath_common *common = ath9k_hw_common(ah);
1847 struct ieee80211_channel *channel = chan->chan; 1143 struct ieee80211_channel *channel = chan->chan;
1848 u32 synthDelay, qnum; 1144 u32 qnum;
1849 int r; 1145 int r;
1850 1146
1851 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1147 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -1857,17 +1153,15 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1857 } 1153 }
1858 } 1154 }
1859 1155
1860 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1156 if (!ath9k_hw_rfbus_req(ah)) {
1861 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1862 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1863 ath_print(common, ATH_DBG_FATAL, 1157 ath_print(common, ATH_DBG_FATAL,
1864 "Could not kill baseband RX\n"); 1158 "Could not kill baseband RX\n");
1865 return false; 1159 return false;
1866 } 1160 }
1867 1161
1868 ath9k_hw_set_regs(ah, chan); 1162 ath9k_hw_set_channel_regs(ah, chan);
1869 1163
1870 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1164 r = ath9k_hw_rf_set_freq(ah, chan);
1871 if (r) { 1165 if (r) {
1872 ath_print(common, ATH_DBG_FATAL, 1166 ath_print(common, ATH_DBG_FATAL,
1873 "Failed to set channel\n"); 1167 "Failed to set channel\n");
@@ -1881,20 +1175,12 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1881 min((u32) MAX_RATE_POWER, 1175 min((u32) MAX_RATE_POWER,
1882 (u32) regulatory->power_limit)); 1176 (u32) regulatory->power_limit));
1883 1177
1884 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1178 ath9k_hw_rfbus_done(ah);
1885 if (IS_CHAN_B(chan))
1886 synthDelay = (4 * synthDelay) / 22;
1887 else
1888 synthDelay /= 10;
1889
1890 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1891
1892 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1893 1179
1894 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1180 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1895 ath9k_hw_set_delta_slope(ah, chan); 1181 ath9k_hw_set_delta_slope(ah, chan);
1896 1182
1897 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1183 ath9k_hw_spur_mitigate_freq(ah, chan);
1898 1184
1899 if (!chan->oneTimeCalsDone) 1185 if (!chan->oneTimeCalsDone)
1900 chan->oneTimeCalsDone = true; 1186 chan->oneTimeCalsDone = true;
@@ -1902,17 +1188,33 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1902 return true; 1188 return true;
1903} 1189}
1904 1190
1905static void ath9k_enable_rfkill(struct ath_hw *ah) 1191bool ath9k_hw_check_alive(struct ath_hw *ah)
1906{ 1192{
1907 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1193 int count = 50;
1908 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 1194 u32 reg;
1195
1196 if (AR_SREV_9285_10_OR_LATER(ah))
1197 return true;
1198
1199 do {
1200 reg = REG_READ(ah, AR_OBS_BUS_1);
1909 1201
1910 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 1202 if ((reg & 0x7E7FFFEF) == 0x00702400)
1911 AR_GPIO_INPUT_MUX2_RFSILENT); 1203 continue;
1912 1204
1913 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1205 switch (reg & 0x7E000B00) {
1914 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 1206 case 0x1E000000:
1207 case 0x52000B00:
1208 case 0x18000B00:
1209 continue;
1210 default:
1211 return true;
1212 }
1213 } while (count-- > 0);
1214
1215 return false;
1915} 1216}
1217EXPORT_SYMBOL(ath9k_hw_check_alive);
1916 1218
1917int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1219int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1918 bool bChannelChange) 1220 bool bChannelChange)
@@ -1923,11 +1225,18 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1923 u32 saveDefAntenna; 1225 u32 saveDefAntenna;
1924 u32 macStaId1; 1226 u32 macStaId1;
1925 u64 tsf = 0; 1227 u64 tsf = 0;
1926 int i, rx_chainmask, r; 1228 int i, r;
1927 1229
1928 ah->txchainmask = common->tx_chainmask; 1230 ah->txchainmask = common->tx_chainmask;
1929 ah->rxchainmask = common->rx_chainmask; 1231 ah->rxchainmask = common->rx_chainmask;
1930 1232
1233 if (!ah->chip_fullsleep) {
1234 ath9k_hw_abortpcurecv(ah);
1235 if (!ath9k_hw_stopdmarecv(ah))
1236 ath_print(common, ATH_DBG_XMIT,
1237 "Failed to stop receive dma\n");
1238 }
1239
1931 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1240 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1932 return -EIO; 1241 return -EIO;
1933 1242
@@ -1940,8 +1249,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1940 (chan->channel != ah->curchan->channel) && 1249 (chan->channel != ah->curchan->channel) &&
1941 ((chan->channelFlags & CHANNEL_ALL) == 1250 ((chan->channelFlags & CHANNEL_ALL) ==
1942 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1251 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1943 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || 1252 !AR_SREV_9280(ah)) {
1944 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1945 1253
1946 if (ath9k_hw_channel_change(ah, chan)) { 1254 if (ath9k_hw_channel_change(ah, chan)) {
1947 ath9k_hw_loadnf(ah, ah->curchan); 1255 ath9k_hw_loadnf(ah, ah->curchan);
@@ -1966,6 +1274,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1966 1274
1967 ath9k_hw_mark_phy_inactive(ah); 1275 ath9k_hw_mark_phy_inactive(ah);
1968 1276
1277 /* Only required on the first reset */
1969 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1278 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1970 REG_WRITE(ah, 1279 REG_WRITE(ah,
1971 AR9271_RESET_POWER_DOWN_CONTROL, 1280 AR9271_RESET_POWER_DOWN_CONTROL,
@@ -1978,6 +1287,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1978 return -EINVAL; 1287 return -EINVAL;
1979 } 1288 }
1980 1289
1290 /* Only required on the first reset */
1981 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1291 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1982 ah->htc_reset_init = false; 1292 ah->htc_reset_init = false;
1983 REG_WRITE(ah, 1293 REG_WRITE(ah,
@@ -1993,16 +1303,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1993 if (AR_SREV_9280_10_OR_LATER(ah)) 1303 if (AR_SREV_9280_10_OR_LATER(ah))
1994 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1304 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1995 1305
1996 if (AR_SREV_9287_12_OR_LATER(ah)) {
1997 /* Enable ASYNC FIFO */
1998 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1999 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2000 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2001 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2002 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2003 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2004 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2005 }
2006 r = ath9k_hw_process_ini(ah, chan); 1306 r = ath9k_hw_process_ini(ah, chan);
2007 if (r) 1307 if (r)
2008 return r; 1308 return r;
@@ -2027,9 +1327,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2027 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1327 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2028 ath9k_hw_set_delta_slope(ah, chan); 1328 ath9k_hw_set_delta_slope(ah, chan);
2029 1329
2030 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1330 ath9k_hw_spur_mitigate_freq(ah, chan);
2031 ah->eep_ops->set_board_values(ah, chan); 1331 ah->eep_ops->set_board_values(ah, chan);
2032 1332
1333 ath9k_hw_set_operating_mode(ah, ah->opmode);
1334
1335 ENABLE_REGWRITE_BUFFER(ah);
1336
2033 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1337 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2034 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1338 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2035 | macStaId1 1339 | macStaId1
@@ -2037,25 +1341,27 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2037 | (ah->config. 1341 | (ah->config.
2038 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1342 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2039 | ah->sta_id1_defaults); 1343 | ah->sta_id1_defaults);
2040 ath9k_hw_set_operating_mode(ah, ah->opmode);
2041
2042 ath_hw_setbssidmask(common); 1344 ath_hw_setbssidmask(common);
2043
2044 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1345 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2045
2046 ath9k_hw_write_associd(ah); 1346 ath9k_hw_write_associd(ah);
2047
2048 REG_WRITE(ah, AR_ISR, ~0); 1347 REG_WRITE(ah, AR_ISR, ~0);
2049
2050 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1348 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2051 1349
2052 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1350 REGWRITE_BUFFER_FLUSH(ah);
1351 DISABLE_REGWRITE_BUFFER(ah);
1352
1353 r = ath9k_hw_rf_set_freq(ah, chan);
2053 if (r) 1354 if (r)
2054 return r; 1355 return r;
2055 1356
1357 ENABLE_REGWRITE_BUFFER(ah);
1358
2056 for (i = 0; i < AR_NUM_DCU; i++) 1359 for (i = 0; i < AR_NUM_DCU; i++)
2057 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1360 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2058 1361
1362 REGWRITE_BUFFER_FLUSH(ah);
1363 DISABLE_REGWRITE_BUFFER(ah);
1364
2059 ah->intr_txqs = 0; 1365 ah->intr_txqs = 0;
2060 for (i = 0; i < ah->caps.total_queues; i++) 1366 for (i = 0; i < ah->caps.total_queues; i++)
2061 ath9k_hw_resettxqueue(ah, i); 1367 ath9k_hw_resettxqueue(ah, i);
@@ -2068,25 +1374,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2068 1374
2069 ath9k_hw_init_global_settings(ah); 1375 ath9k_hw_init_global_settings(ah);
2070 1376
2071 if (AR_SREV_9287_12_OR_LATER(ah)) { 1377 if (!AR_SREV_9300_20_OR_LATER(ah)) {
2072 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 1378 ar9002_hw_enable_async_fifo(ah);
2073 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 1379 ar9002_hw_enable_wep_aggregation(ah);
2074 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2075 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2076 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2077 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2078
2079 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2080 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2081
2082 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2083 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2084 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2085 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2086 }
2087 if (AR_SREV_9287_12_OR_LATER(ah)) {
2088 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2089 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2090 } 1380 }
2091 1381
2092 REG_WRITE(ah, AR_STA_ID1, 1382 REG_WRITE(ah, AR_STA_ID1,
@@ -2101,19 +1391,24 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2101 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1391 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2102 } 1392 }
2103 1393
1394 if (ah->config.tx_intr_mitigation) {
1395 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1396 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1397 }
1398
2104 ath9k_hw_init_bb(ah, chan); 1399 ath9k_hw_init_bb(ah, chan);
2105 1400
2106 if (!ath9k_hw_init_cal(ah, chan)) 1401 if (!ath9k_hw_init_cal(ah, chan))
2107 return -EIO; 1402 return -EIO;
2108 1403
2109 rx_chainmask = ah->rxchainmask; 1404 ENABLE_REGWRITE_BUFFER(ah);
2110 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2113 }
2114 1405
1406 ath9k_hw_restore_chainmask(ah);
2115 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1407 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2116 1408
1409 REGWRITE_BUFFER_FLUSH(ah);
1410 DISABLE_REGWRITE_BUFFER(ah);
1411
2117 /* 1412 /*
2118 * For big endian systems turn on swapping for descriptors 1413 * For big endian systems turn on swapping for descriptors
2119 */ 1414 */
@@ -2143,6 +1438,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2143 if (ah->btcoex_hw.enabled) 1438 if (ah->btcoex_hw.enabled)
2144 ath9k_hw_btcoex_enable(ah); 1439 ath9k_hw_btcoex_enable(ah);
2145 1440
1441 if (AR_SREV_9300_20_OR_LATER(ah)) {
1442 ath9k_hw_loadnf(ah, curchan);
1443 ath9k_hw_start_nfcal(ah);
1444 }
1445
2146 return 0; 1446 return 0;
2147} 1447}
2148EXPORT_SYMBOL(ath9k_hw_reset); 1448EXPORT_SYMBOL(ath9k_hw_reset);
@@ -2429,21 +1729,35 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2429/* Power Management (Chipset) */ 1729/* Power Management (Chipset) */
2430/******************************/ 1730/******************************/
2431 1731
1732/*
1733 * Notify Power Mgt is disabled in self-generated frames.
1734 * If requested, force chip to sleep.
1735 */
2432static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1736static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2433{ 1737{
2434 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1738 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2435 if (setChip) { 1739 if (setChip) {
1740 /*
1741 * Clear the RTC force wake bit to allow the
1742 * mac to go to sleep.
1743 */
2436 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1744 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2437 AR_RTC_FORCE_WAKE_EN); 1745 AR_RTC_FORCE_WAKE_EN);
2438 if (!AR_SREV_9100(ah)) 1746 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2439 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1747 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2440 1748
2441 if(!AR_SREV_5416(ah)) 1749 /* Shutdown chip. Active low */
1750 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2442 REG_CLR_BIT(ah, (AR_RTC_RESET), 1751 REG_CLR_BIT(ah, (AR_RTC_RESET),
2443 AR_RTC_RESET_EN); 1752 AR_RTC_RESET_EN);
2444 } 1753 }
2445} 1754}
2446 1755
1756/*
1757 * Notify Power Management is enabled in self-generating
1758 * frames. If request, set power mode of chip to
1759 * auto/normal. Duration in units of 128us (1/8 TU).
1760 */
2447static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1761static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2448{ 1762{
2449 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1763 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
@@ -2451,9 +1765,14 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2451 struct ath9k_hw_capabilities *pCap = &ah->caps; 1765 struct ath9k_hw_capabilities *pCap = &ah->caps;
2452 1766
2453 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1767 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1768 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2454 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1769 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2455 AR_RTC_FORCE_WAKE_ON_INT); 1770 AR_RTC_FORCE_WAKE_ON_INT);
2456 } else { 1771 } else {
1772 /*
1773 * Clear the RTC force wake bit to allow the
1774 * mac to go to sleep.
1775 */
2457 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1776 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2458 AR_RTC_FORCE_WAKE_EN); 1777 AR_RTC_FORCE_WAKE_EN);
2459 } 1778 }
@@ -2472,7 +1791,8 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2472 ATH9K_RESET_POWER_ON) != true) { 1791 ATH9K_RESET_POWER_ON) != true) {
2473 return false; 1792 return false;
2474 } 1793 }
2475 ath9k_hw_init_pll(ah, NULL); 1794 if (!AR_SREV_9300_20_OR_LATER(ah))
1795 ath9k_hw_init_pll(ah, NULL);
2476 } 1796 }
2477 if (AR_SREV_9100(ah)) 1797 if (AR_SREV_9100(ah))
2478 REG_SET_BIT(ah, AR_RTC_RESET, 1798 REG_SET_BIT(ah, AR_RTC_RESET,
@@ -2542,424 +1862,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2542} 1862}
2543EXPORT_SYMBOL(ath9k_hw_setpower); 1863EXPORT_SYMBOL(ath9k_hw_setpower);
2544 1864
2545/*
2546 * Helper for ASPM support.
2547 *
2548 * Disable PLL when in L0s as well as receiver clock when in L1.
2549 * This power saving option must be enabled through the SerDes.
2550 *
2551 * Programming the SerDes must go through the same 288 bit serial shift
2552 * register as the other analog registers. Hence the 9 writes.
2553 */
2554void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2555{
2556 u8 i;
2557 u32 val;
2558
2559 if (ah->is_pciexpress != true)
2560 return;
2561
2562 /* Do not touch SerDes registers */
2563 if (ah->config.pcie_powersave_enable == 2)
2564 return;
2565
2566 /* Nothing to do on restore for 11N */
2567 if (!restore) {
2568 if (AR_SREV_9280_20_OR_LATER(ah)) {
2569 /*
2570 * AR9280 2.0 or later chips use SerDes values from the
2571 * initvals.h initialized depending on chipset during
2572 * ath9k_hw_init()
2573 */
2574 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2575 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2576 INI_RA(&ah->iniPcieSerdes, i, 1));
2577 }
2578 } else if (AR_SREV_9280(ah) &&
2579 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2580 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2581 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2582
2583 /* RX shut off when elecidle is asserted */
2584 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2585 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2586 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2587
2588 /* Shut off CLKREQ active in L1 */
2589 if (ah->config.pcie_clock_req)
2590 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2591 else
2592 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2593
2594 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2595 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2596 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2597
2598 /* Load the new settings */
2599 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2600
2601 } else {
2602 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2604
2605 /* RX shut off when elecidle is asserted */
2606 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2607 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2608 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2609
2610 /*
2611 * Ignore ah->ah_config.pcie_clock_req setting for
2612 * pre-AR9280 11n
2613 */
2614 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2615
2616 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2617 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2618 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2619
2620 /* Load the new settings */
2621 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2622 }
2623
2624 udelay(1000);
2625
2626 /* set bit 19 to allow forcing of pcie core into L1 state */
2627 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2628
2629 /* Several PCIe massages to ensure proper behaviour */
2630 if (ah->config.pcie_waen) {
2631 val = ah->config.pcie_waen;
2632 if (!power_off)
2633 val &= (~AR_WA_D3_L1_DISABLE);
2634 } else {
2635 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2636 AR_SREV_9287(ah)) {
2637 val = AR9285_WA_DEFAULT;
2638 if (!power_off)
2639 val &= (~AR_WA_D3_L1_DISABLE);
2640 } else if (AR_SREV_9280(ah)) {
2641 /*
2642 * On AR9280 chips bit 22 of 0x4004 needs to be
2643 * set otherwise card may disappear.
2644 */
2645 val = AR9280_WA_DEFAULT;
2646 if (!power_off)
2647 val &= (~AR_WA_D3_L1_DISABLE);
2648 } else
2649 val = AR_WA_DEFAULT;
2650 }
2651
2652 REG_WRITE(ah, AR_WA, val);
2653 }
2654
2655 if (power_off) {
2656 /*
2657 * Set PCIe workaround bits
2658 * bit 14 in WA register (disable L1) should only
2659 * be set when device enters D3 and be cleared
2660 * when device comes back to D0.
2661 */
2662 if (ah->config.pcie_waen) {
2663 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2664 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2665 } else {
2666 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2667 AR_SREV_9287(ah)) &&
2668 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2669 (AR_SREV_9280(ah) &&
2670 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2671 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2672 }
2673 }
2674 }
2675}
2676EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2677
2678/**********************/
2679/* Interrupt Handling */
2680/**********************/
2681
2682bool ath9k_hw_intrpend(struct ath_hw *ah)
2683{
2684 u32 host_isr;
2685
2686 if (AR_SREV_9100(ah))
2687 return true;
2688
2689 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2690 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2691 return true;
2692
2693 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2694 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2695 && (host_isr != AR_INTR_SPURIOUS))
2696 return true;
2697
2698 return false;
2699}
2700EXPORT_SYMBOL(ath9k_hw_intrpend);
2701
2702bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2703{
2704 u32 isr = 0;
2705 u32 mask2 = 0;
2706 struct ath9k_hw_capabilities *pCap = &ah->caps;
2707 u32 sync_cause = 0;
2708 bool fatal_int = false;
2709 struct ath_common *common = ath9k_hw_common(ah);
2710
2711 if (!AR_SREV_9100(ah)) {
2712 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2713 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2714 == AR_RTC_STATUS_ON) {
2715 isr = REG_READ(ah, AR_ISR);
2716 }
2717 }
2718
2719 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2720 AR_INTR_SYNC_DEFAULT;
2721
2722 *masked = 0;
2723
2724 if (!isr && !sync_cause)
2725 return false;
2726 } else {
2727 *masked = 0;
2728 isr = REG_READ(ah, AR_ISR);
2729 }
2730
2731 if (isr) {
2732 if (isr & AR_ISR_BCNMISC) {
2733 u32 isr2;
2734 isr2 = REG_READ(ah, AR_ISR_S2);
2735 if (isr2 & AR_ISR_S2_TIM)
2736 mask2 |= ATH9K_INT_TIM;
2737 if (isr2 & AR_ISR_S2_DTIM)
2738 mask2 |= ATH9K_INT_DTIM;
2739 if (isr2 & AR_ISR_S2_DTIMSYNC)
2740 mask2 |= ATH9K_INT_DTIMSYNC;
2741 if (isr2 & (AR_ISR_S2_CABEND))
2742 mask2 |= ATH9K_INT_CABEND;
2743 if (isr2 & AR_ISR_S2_GTT)
2744 mask2 |= ATH9K_INT_GTT;
2745 if (isr2 & AR_ISR_S2_CST)
2746 mask2 |= ATH9K_INT_CST;
2747 if (isr2 & AR_ISR_S2_TSFOOR)
2748 mask2 |= ATH9K_INT_TSFOOR;
2749 }
2750
2751 isr = REG_READ(ah, AR_ISR_RAC);
2752 if (isr == 0xffffffff) {
2753 *masked = 0;
2754 return false;
2755 }
2756
2757 *masked = isr & ATH9K_INT_COMMON;
2758
2759 if (ah->config.rx_intr_mitigation) {
2760 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2761 *masked |= ATH9K_INT_RX;
2762 }
2763
2764 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2765 *masked |= ATH9K_INT_RX;
2766 if (isr &
2767 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2768 AR_ISR_TXEOL)) {
2769 u32 s0_s, s1_s;
2770
2771 *masked |= ATH9K_INT_TX;
2772
2773 s0_s = REG_READ(ah, AR_ISR_S0_S);
2774 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2775 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2776
2777 s1_s = REG_READ(ah, AR_ISR_S1_S);
2778 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2779 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2780 }
2781
2782 if (isr & AR_ISR_RXORN) {
2783 ath_print(common, ATH_DBG_INTERRUPT,
2784 "receive FIFO overrun interrupt\n");
2785 }
2786
2787 if (!AR_SREV_9100(ah)) {
2788 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2789 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2790 if (isr5 & AR_ISR_S5_TIM_TIMER)
2791 *masked |= ATH9K_INT_TIM_TIMER;
2792 }
2793 }
2794
2795 *masked |= mask2;
2796 }
2797
2798 if (AR_SREV_9100(ah))
2799 return true;
2800
2801 if (isr & AR_ISR_GENTMR) {
2802 u32 s5_s;
2803
2804 s5_s = REG_READ(ah, AR_ISR_S5_S);
2805 if (isr & AR_ISR_GENTMR) {
2806 ah->intr_gen_timer_trigger =
2807 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2808
2809 ah->intr_gen_timer_thresh =
2810 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2811
2812 if (ah->intr_gen_timer_trigger)
2813 *masked |= ATH9K_INT_GENTIMER;
2814
2815 }
2816 }
2817
2818 if (sync_cause) {
2819 fatal_int =
2820 (sync_cause &
2821 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2822 ? true : false;
2823
2824 if (fatal_int) {
2825 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2826 ath_print(common, ATH_DBG_ANY,
2827 "received PCI FATAL interrupt\n");
2828 }
2829 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2830 ath_print(common, ATH_DBG_ANY,
2831 "received PCI PERR interrupt\n");
2832 }
2833 *masked |= ATH9K_INT_FATAL;
2834 }
2835 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2836 ath_print(common, ATH_DBG_INTERRUPT,
2837 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2838 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2839 REG_WRITE(ah, AR_RC, 0);
2840 *masked |= ATH9K_INT_FATAL;
2841 }
2842 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2843 ath_print(common, ATH_DBG_INTERRUPT,
2844 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2845 }
2846
2847 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2848 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2849 }
2850
2851 return true;
2852}
2853EXPORT_SYMBOL(ath9k_hw_getisr);
2854
2855enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2856{
2857 u32 omask = ah->mask_reg;
2858 u32 mask, mask2;
2859 struct ath9k_hw_capabilities *pCap = &ah->caps;
2860 struct ath_common *common = ath9k_hw_common(ah);
2861
2862 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2863
2864 if (omask & ATH9K_INT_GLOBAL) {
2865 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2866 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2867 (void) REG_READ(ah, AR_IER);
2868 if (!AR_SREV_9100(ah)) {
2869 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2870 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2871
2872 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2873 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2874 }
2875 }
2876
2877 mask = ints & ATH9K_INT_COMMON;
2878 mask2 = 0;
2879
2880 if (ints & ATH9K_INT_TX) {
2881 if (ah->txok_interrupt_mask)
2882 mask |= AR_IMR_TXOK;
2883 if (ah->txdesc_interrupt_mask)
2884 mask |= AR_IMR_TXDESC;
2885 if (ah->txerr_interrupt_mask)
2886 mask |= AR_IMR_TXERR;
2887 if (ah->txeol_interrupt_mask)
2888 mask |= AR_IMR_TXEOL;
2889 }
2890 if (ints & ATH9K_INT_RX) {
2891 mask |= AR_IMR_RXERR;
2892 if (ah->config.rx_intr_mitigation)
2893 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2894 else
2895 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2896 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2897 mask |= AR_IMR_GENTMR;
2898 }
2899
2900 if (ints & (ATH9K_INT_BMISC)) {
2901 mask |= AR_IMR_BCNMISC;
2902 if (ints & ATH9K_INT_TIM)
2903 mask2 |= AR_IMR_S2_TIM;
2904 if (ints & ATH9K_INT_DTIM)
2905 mask2 |= AR_IMR_S2_DTIM;
2906 if (ints & ATH9K_INT_DTIMSYNC)
2907 mask2 |= AR_IMR_S2_DTIMSYNC;
2908 if (ints & ATH9K_INT_CABEND)
2909 mask2 |= AR_IMR_S2_CABEND;
2910 if (ints & ATH9K_INT_TSFOOR)
2911 mask2 |= AR_IMR_S2_TSFOOR;
2912 }
2913
2914 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2915 mask |= AR_IMR_BCNMISC;
2916 if (ints & ATH9K_INT_GTT)
2917 mask2 |= AR_IMR_S2_GTT;
2918 if (ints & ATH9K_INT_CST)
2919 mask2 |= AR_IMR_S2_CST;
2920 }
2921
2922 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2923 REG_WRITE(ah, AR_IMR, mask);
2924 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2925 AR_IMR_S2_DTIM |
2926 AR_IMR_S2_DTIMSYNC |
2927 AR_IMR_S2_CABEND |
2928 AR_IMR_S2_CABTO |
2929 AR_IMR_S2_TSFOOR |
2930 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2931 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2932 ah->mask_reg = ints;
2933
2934 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2935 if (ints & ATH9K_INT_TIM_TIMER)
2936 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2937 else
2938 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2939 }
2940
2941 if (ints & ATH9K_INT_GLOBAL) {
2942 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2943 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2944 if (!AR_SREV_9100(ah)) {
2945 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2946 AR_INTR_MAC_IRQ);
2947 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2948
2949
2950 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2951 AR_INTR_SYNC_DEFAULT);
2952 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2953 AR_INTR_SYNC_DEFAULT);
2954 }
2955 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2956 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2957 }
2958
2959 return omask;
2960}
2961EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2962
2963/*******************/ 1865/*******************/
2964/* Beacon Handling */ 1866/* Beacon Handling */
2965/*******************/ 1867/*******************/
@@ -2970,6 +1872,8 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2970 1872
2971 ah->beacon_interval = beacon_period; 1873 ah->beacon_interval = beacon_period;
2972 1874
1875 ENABLE_REGWRITE_BUFFER(ah);
1876
2973 switch (ah->opmode) { 1877 switch (ah->opmode) {
2974 case NL80211_IFTYPE_STATION: 1878 case NL80211_IFTYPE_STATION:
2975 case NL80211_IFTYPE_MONITOR: 1879 case NL80211_IFTYPE_MONITOR:
@@ -3013,6 +1917,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3013 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1917 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3014 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1918 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3015 1919
1920 REGWRITE_BUFFER_FLUSH(ah);
1921 DISABLE_REGWRITE_BUFFER(ah);
1922
3016 beacon_period &= ~ATH9K_BEACON_ENA; 1923 beacon_period &= ~ATH9K_BEACON_ENA;
3017 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1924 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3018 ath9k_hw_reset_tsf(ah); 1925 ath9k_hw_reset_tsf(ah);
@@ -3029,6 +1936,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3029 struct ath9k_hw_capabilities *pCap = &ah->caps; 1936 struct ath9k_hw_capabilities *pCap = &ah->caps;
3030 struct ath_common *common = ath9k_hw_common(ah); 1937 struct ath_common *common = ath9k_hw_common(ah);
3031 1938
1939 ENABLE_REGWRITE_BUFFER(ah);
1940
3032 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1941 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3033 1942
3034 REG_WRITE(ah, AR_BEACON_PERIOD, 1943 REG_WRITE(ah, AR_BEACON_PERIOD,
@@ -3036,6 +1945,9 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3036 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1945 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3037 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1946 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3038 1947
1948 REGWRITE_BUFFER_FLUSH(ah);
1949 DISABLE_REGWRITE_BUFFER(ah);
1950
3039 REG_RMW_FIELD(ah, AR_RSSI_THR, 1951 REG_RMW_FIELD(ah, AR_RSSI_THR,
3040 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1952 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3041 1953
@@ -3058,6 +1970,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3058 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1970 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3059 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1971 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3060 1972
1973 ENABLE_REGWRITE_BUFFER(ah);
1974
3061 REG_WRITE(ah, AR_NEXT_DTIM, 1975 REG_WRITE(ah, AR_NEXT_DTIM,
3062 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1976 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3063 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1977 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
@@ -3077,6 +1991,9 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3077 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1991 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3078 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1992 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3079 1993
1994 REGWRITE_BUFFER_FLUSH(ah);
1995 DISABLE_REGWRITE_BUFFER(ah);
1996
3080 REG_SET_BIT(ah, AR_TIMER_MODE, 1997 REG_SET_BIT(ah, AR_TIMER_MODE,
3081 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1998 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3082 AR_DTIM_TIMER_EN); 1999 AR_DTIM_TIMER_EN);
@@ -3219,7 +2136,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3219 else 2136 else
3220 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 2137 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3221 2138
3222 if (AR_SREV_9285_10_OR_LATER(ah)) 2139 if (AR_SREV_9271(ah))
2140 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2141 else if (AR_SREV_9285_10_OR_LATER(ah))
3223 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2142 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3224 else if (AR_SREV_9280_10_OR_LATER(ah)) 2143 else if (AR_SREV_9280_10_OR_LATER(ah))
3225 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2144 pCap->num_gpio_pins = AR928X_NUM_GPIO;
@@ -3246,8 +2165,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3246 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2165 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3247 } 2166 }
3248#endif 2167#endif
3249 2168 if (AR_SREV_9271(ah))
3250 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2169 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2170 else
2171 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3251 2172
3252 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2173 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3253 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2174 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
@@ -3291,6 +2212,26 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3291 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2212 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3292 } 2213 }
3293 2214
2215 if (AR_SREV_9300_20_OR_LATER(ah)) {
2216 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2217 ATH9K_HW_CAP_FASTCLOCK;
2218 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2219 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2220 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2221 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2222 pCap->txs_len = sizeof(struct ar9003_txs);
2223 } else {
2224 pCap->tx_desc_len = sizeof(struct ath_desc);
2225 if (AR_SREV_9280_20(ah) &&
2226 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2227 AR5416_EEP_MINOR_VER_16) ||
2228 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2229 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2230 }
2231
2232 if (AR_SREV_9300_20_OR_LATER(ah))
2233 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2234
3294 return 0; 2235 return 0;
3295} 2236}
3296 2237
@@ -3323,10 +2264,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3323 case ATH9K_CAP_TKIP_SPLIT: 2264 case ATH9K_CAP_TKIP_SPLIT:
3324 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 2265 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3325 false : true; 2266 false : true;
3326 case ATH9K_CAP_DIVERSITY:
3327 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3328 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3329 true : false;
3330 case ATH9K_CAP_MCAST_KEYSRCH: 2267 case ATH9K_CAP_MCAST_KEYSRCH:
3331 switch (capability) { 2268 switch (capability) {
3332 case 0: 2269 case 0:
@@ -3369,8 +2306,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
3369bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 2306bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3370 u32 capability, u32 setting, int *status) 2307 u32 capability, u32 setting, int *status)
3371{ 2308{
3372 u32 v;
3373
3374 switch (type) { 2309 switch (type) {
3375 case ATH9K_CAP_TKIP_MIC: 2310 case ATH9K_CAP_TKIP_MIC:
3376 if (setting) 2311 if (setting)
@@ -3380,14 +2315,6 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3380 ah->sta_id1_defaults &= 2315 ah->sta_id1_defaults &=
3381 ~AR_STA_ID1_CRPT_MIC_ENABLE; 2316 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3382 return true; 2317 return true;
3383 case ATH9K_CAP_DIVERSITY:
3384 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3385 if (setting)
3386 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3387 else
3388 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3389 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3390 return true;
3391 case ATH9K_CAP_MCAST_KEYSRCH: 2318 case ATH9K_CAP_MCAST_KEYSRCH:
3392 if (setting) 2319 if (setting)
3393 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 2320 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
@@ -3455,7 +2382,11 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3455 if (gpio >= ah->caps.num_gpio_pins) 2382 if (gpio >= ah->caps.num_gpio_pins)
3456 return 0xffffffff; 2383 return 0xffffffff;
3457 2384
3458 if (AR_SREV_9287_10_OR_LATER(ah)) 2385 if (AR_SREV_9300_20_OR_LATER(ah))
2386 return MS_REG_READ(AR9300, gpio) != 0;
2387 else if (AR_SREV_9271(ah))
2388 return MS_REG_READ(AR9271, gpio) != 0;
2389 else if (AR_SREV_9287_10_OR_LATER(ah))
3459 return MS_REG_READ(AR9287, gpio) != 0; 2390 return MS_REG_READ(AR9287, gpio) != 0;
3460 else if (AR_SREV_9285_10_OR_LATER(ah)) 2391 else if (AR_SREV_9285_10_OR_LATER(ah))
3461 return MS_REG_READ(AR9285, gpio) != 0; 2392 return MS_REG_READ(AR9285, gpio) != 0;
@@ -3484,6 +2415,9 @@ EXPORT_SYMBOL(ath9k_hw_cfg_output);
3484 2415
3485void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2416void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3486{ 2417{
2418 if (AR_SREV_9271(ah))
2419 val = ~val;
2420
3487 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2421 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3488 AR_GPIO_BIT(gpio)); 2422 AR_GPIO_BIT(gpio));
3489} 2423}
@@ -3523,6 +2457,8 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3523{ 2457{
3524 u32 phybits; 2458 u32 phybits;
3525 2459
2460 ENABLE_REGWRITE_BUFFER(ah);
2461
3526 REG_WRITE(ah, AR_RX_FILTER, bits); 2462 REG_WRITE(ah, AR_RX_FILTER, bits);
3527 2463
3528 phybits = 0; 2464 phybits = 0;
@@ -3538,6 +2474,9 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3538 else 2474 else
3539 REG_WRITE(ah, AR_RXCFG, 2475 REG_WRITE(ah, AR_RXCFG,
3540 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2476 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2477
2478 REGWRITE_BUFFER_FLUSH(ah);
2479 DISABLE_REGWRITE_BUFFER(ah);
3541} 2480}
3542EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2481EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3543 2482
@@ -3610,14 +2549,25 @@ void ath9k_hw_write_associd(struct ath_hw *ah)
3610} 2549}
3611EXPORT_SYMBOL(ath9k_hw_write_associd); 2550EXPORT_SYMBOL(ath9k_hw_write_associd);
3612 2551
2552#define ATH9K_MAX_TSF_READ 10
2553
3613u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2554u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3614{ 2555{
3615 u64 tsf; 2556 u32 tsf_lower, tsf_upper1, tsf_upper2;
2557 int i;
2558
2559 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2560 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2561 tsf_lower = REG_READ(ah, AR_TSF_L32);
2562 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2563 if (tsf_upper2 == tsf_upper1)
2564 break;
2565 tsf_upper1 = tsf_upper2;
2566 }
3616 2567
3617 tsf = REG_READ(ah, AR_TSF_U32); 2568 WARN_ON( i == ATH9K_MAX_TSF_READ );
3618 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3619 2569
3620 return tsf; 2570 return (((u64)tsf_upper1 << 32) | tsf_lower);
3621} 2571}
3622EXPORT_SYMBOL(ath9k_hw_gettsf64); 2572EXPORT_SYMBOL(ath9k_hw_gettsf64);
3623 2573
@@ -3868,6 +2818,16 @@ void ath_gen_timer_isr(struct ath_hw *ah)
3868} 2818}
3869EXPORT_SYMBOL(ath_gen_timer_isr); 2819EXPORT_SYMBOL(ath_gen_timer_isr);
3870 2820
2821/********/
2822/* HTC */
2823/********/
2824
2825void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2826{
2827 ah->htc_reset_init = true;
2828}
2829EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2830
3871static struct { 2831static struct {
3872 u32 version; 2832 u32 version;
3873 const char * name; 2833 const char * name;
@@ -3882,6 +2842,7 @@ static struct {
3882 { AR_SREV_VERSION_9285, "9285" }, 2842 { AR_SREV_VERSION_9285, "9285" },
3883 { AR_SREV_VERSION_9287, "9287" }, 2843 { AR_SREV_VERSION_9287, "9287" },
3884 { AR_SREV_VERSION_9271, "9271" }, 2844 { AR_SREV_VERSION_9271, "9271" },
2845 { AR_SREV_VERSION_9300, "9300" },
3885}; 2846};
3886 2847
3887/* For devices with external radios */ 2848/* For devices with external radios */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 19:47:53 -0400