1 files changed, 121 insertions, 81 deletions

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index b6c6cca0781..ca7694caf36 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -842,7 +842,7 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 
 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 {
-        if (AR_SREV_9287_11(ah))
+        if (AR_SREV_9287_11_OR_LATER(ah))
                 INIT_INI_ARRAY(&ah->iniModesRxGain,
                 ar9287Modes_rx_gain_9287_1_1,
                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
@@ -853,7 +853,7 @@ static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
         else if (AR_SREV_9280_20(ah))
                 ath9k_hw_init_rxgain_ini(ah);
 
-        if (AR_SREV_9287_11(ah)) {
+        if (AR_SREV_9287_11_OR_LATER(ah)) {
                 INIT_INI_ARRAY(&ah->iniModesTxGain,
                 ar9287Modes_tx_gain_9287_1_1,
                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
@@ -965,7 +965,7 @@ int ath9k_hw_init(struct ath_hw *ah)
         ath9k_hw_init_mode_regs(ah);
 
         if (ah->is_pciexpress)
-                ath9k_hw_configpcipowersave(ah, 0);
+                ath9k_hw_configpcipowersave(ah, 0, 0);
         else
                 ath9k_hw_disablepcie(ah);
 
@@ -1273,6 +1273,15 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
          */
         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 
+        if (AR_SREV_9280_10_OR_LATER(ah)) {
+                val = REG_READ(ah, AR_PCU_MISC_MODE2) &
+                               (~AR_PCU_MISC_MODE2_HWWAR1);
+
+                if (AR_SREV_9287_10_OR_LATER(ah))
+                        val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
+
+                REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
+        }
 
         if (!AR_SREV_5416_20_OR_LATER(ah) ||
             AR_SREV_9280_10_OR_LATER(ah))
@@ -1784,7 +1793,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
                                 struct ath9k_channel *chan)
 {
-        if (OLC_FOR_AR9280_20_LATER) {
+        if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
                         return false;
         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
@@ -2338,6 +2347,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         struct ath9k_channel *curchan = ah->curchan;
         u32 saveDefAntenna;
         u32 macStaId1;
+        u64 tsf = 0;
         int i, rx_chainmask, r;
 
         ah->extprotspacing = sc->ht_extprotspacing;
@@ -2347,7 +2357,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                 return -EIO;
 
-        if (curchan)
+        if (curchan && !ah->chip_fullsleep)
                 ath9k_hw_getnf(ah, curchan);
 
         if (bChannelChange &&
@@ -2356,8 +2366,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
             (chan->channel != ah->curchan->channel) &&
             ((chan->channelFlags & CHANNEL_ALL) ==
              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
-            (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
-                                   !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
+             !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
+             IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
 
                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
                         ath9k_hw_loadnf(ah, ah->curchan);
@@ -2372,6 +2382,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 
         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
 
+        /* For chips on which RTC reset is done, save TSF before it gets cleared */
+        if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
+                tsf = ath9k_hw_gettsf64(ah);
+
         saveLedState = REG_READ(ah, AR_CFG_LED) &
                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
@@ -2398,6 +2412,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 udelay(50);
         }
 
+        /* Restore TSF */
+        if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
+                ath9k_hw_settsf64(ah, tsf);
+
         if (AR_SREV_9280_10_OR_LATER(ah))
                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
 
@@ -3005,9 +3023,10 @@ void ath9k_ps_restore(struct ath_softc *sc)
  * Programming the SerDes must go through the same 288 bit serial shift
  * register as the other analog registers.  Hence the 9 writes.
  */
-void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
+void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
 {
         u8 i;
+        u32 val;
 
         if (ah->is_pciexpress != true)
                 return;
@@ -3017,84 +3036,113 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
                 return;
 
         /* Nothing to do on restore for 11N */
-        if (restore)
-                return;
+        if (!restore) {
+                if (AR_SREV_9280_20_OR_LATER(ah)) {
+                        /*
+                         * AR9280 2.0 or later chips use SerDes values from the
+                         * initvals.h initialized depending on chipset during
+                         * ath9k_hw_init()
+                         */
+                        for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
+                                REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
+                                          INI_RA(&ah->iniPcieSerdes, i, 1));
+                        }
+                } else if (AR_SREV_9280(ah) &&
+                           (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+
+                        /* RX shut off when elecidle is asserted */
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
+
+                        /* Shut off CLKREQ active in L1 */
+                        if (ah->config.pcie_clock_req)
+                                REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
+                        else
+                                REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
 
-        if (AR_SREV_9280_20_OR_LATER(ah)) {
-                /*
-                 * AR9280 2.0 or later chips use SerDes values from the
-                 * initvals.h initialized depending on chipset during
-                 * ath9k_hw_init()
-                 */
-                for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
-                        REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
-                                  INI_RA(&ah->iniPcieSerdes, i, 1));
-                }
-        } else if (AR_SREV_9280(ah) &&
-                   (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
 
-                /* RX shut off when elecidle is asserted */
-                REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
+                        /* Load the new settings */
+                        REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 
-                /* Shut off CLKREQ active in L1 */
-                if (ah->config.pcie_clock_req)
-                        REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
-                else
-                        REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
-
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
+                } else {
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 
-                /* Load the new settings */
-                REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
+                        /* RX shut off when elecidle is asserted */
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 
-        } else {
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+                        /*
+                         * Ignore ah->ah_config.pcie_clock_req setting for
+                         * pre-AR9280 11n
+                         */
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 
-                /* RX shut off when elecidle is asserted */
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
+                        REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 
-                /*
-                 * Ignore ah->ah_config.pcie_clock_req setting for
-                 * pre-AR9280 11n
-                 */
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
+                        /* Load the new settings */
+                        REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
+                }
 
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
-                REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
+                udelay(1000);
 
-                /* Load the new settings */
-                REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
-        }
+                /* set bit 19 to allow forcing of pcie core into L1 state */
+                REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 
-        udelay(1000);
+                /* Several PCIe massages to ensure proper behaviour */
+                if (ah->config.pcie_waen) {
+                        val = ah->config.pcie_waen;
+                        if (!power_off)
+                                val &= (~AR_WA_D3_L1_DISABLE);
+                } else {
+                        if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
+                            AR_SREV_9287(ah)) {
+                                val = AR9285_WA_DEFAULT;
+                                if (!power_off)
+                                        val &= (~AR_WA_D3_L1_DISABLE);
+                        } else if (AR_SREV_9280(ah)) {
+                                /*
+                                 * On AR9280 chips bit 22 of 0x4004 needs to be
+                                 * set otherwise card may disappear.
+                                 */
+                                val = AR9280_WA_DEFAULT;
+                                if (!power_off)
+                                        val &= (~AR_WA_D3_L1_DISABLE);
+                        } else
+                                val = AR_WA_DEFAULT;
+                }
 
-        /* set bit 19 to allow forcing of pcie core into L1 state */
-        REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+                REG_WRITE(ah, AR_WA, val);
+        }
 
-        /* Several PCIe massages to ensure proper behaviour */
-        if (ah->config.pcie_waen) {
-                REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
-        } else {
-                if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah))
-                        REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
+        if (power_off) {
                 /*
-                 * On AR9280 chips bit 22 of 0x4004 needs to be set to
-                 * otherwise card may disappear.
+                 * Set PCIe workaround bits
+                 * bit 14 in WA register (disable L1) should only
+                 * be set when device enters D3 and be cleared
+                 * when device comes back to D0.
                  */
-                else if (AR_SREV_9280(ah))
-                        REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
-                else
-                        REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
+                if (ah->config.pcie_waen) {
+                        if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
+                                REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
+                } else {
+                        if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
+                              AR_SREV_9287(ah)) &&
+                             (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
+                            (AR_SREV_9280(ah) &&
+                             (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
+                                REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
+                        }
+                }
         }
 }
 
@@ -3652,15 +3700,7 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
         }
 #endif
 
-        if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
-            (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
-            (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
-            (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
-            (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
-            (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
-                pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
-        else
-                pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
+        pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
 
         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;