diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/calib.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/calib.c | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c index 085e1264fbe..6982577043b 100644 --- a/drivers/net/wireless/ath/ath9k/calib.c +++ b/drivers/net/wireless/ath/ath9k/calib.c | |||
@@ -16,7 +16,6 @@ | |||
16 | 16 | ||
17 | #include "hw.h" | 17 | #include "hw.h" |
18 | #include "hw-ops.h" | 18 | #include "hw-ops.h" |
19 | #include "ar9002_phy.h" | ||
20 | 19 | ||
21 | /* Common calibration code */ | 20 | /* Common calibration code */ |
22 | 21 | ||
@@ -174,72 +173,6 @@ void ath9k_hw_start_nfcal(struct ath_hw *ah) | |||
174 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | 173 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); |
175 | } | 174 | } |
176 | 175 | ||
177 | void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) | ||
178 | { | ||
179 | struct ath9k_nfcal_hist *h; | ||
180 | int i, j; | ||
181 | int32_t val; | ||
182 | const u32 ar5416_cca_regs[6] = { | ||
183 | AR_PHY_CCA, | ||
184 | AR_PHY_CH1_CCA, | ||
185 | AR_PHY_CH2_CCA, | ||
186 | AR_PHY_EXT_CCA, | ||
187 | AR_PHY_CH1_EXT_CCA, | ||
188 | AR_PHY_CH2_EXT_CCA | ||
189 | }; | ||
190 | u8 chainmask, rx_chain_status; | ||
191 | |||
192 | rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK); | ||
193 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | ||
194 | chainmask = 0x9; | ||
195 | else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) { | ||
196 | if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4)) | ||
197 | chainmask = 0x1B; | ||
198 | else | ||
199 | chainmask = 0x09; | ||
200 | } else { | ||
201 | if (rx_chain_status & 0x4) | ||
202 | chainmask = 0x3F; | ||
203 | else if (rx_chain_status & 0x2) | ||
204 | chainmask = 0x1B; | ||
205 | else | ||
206 | chainmask = 0x09; | ||
207 | } | ||
208 | |||
209 | h = ah->nfCalHist; | ||
210 | |||
211 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
212 | if (chainmask & (1 << i)) { | ||
213 | val = REG_READ(ah, ar5416_cca_regs[i]); | ||
214 | val &= 0xFFFFFE00; | ||
215 | val |= (((u32) (h[i].privNF) << 1) & 0x1ff); | ||
216 | REG_WRITE(ah, ar5416_cca_regs[i], val); | ||
217 | } | ||
218 | } | ||
219 | |||
220 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | ||
221 | AR_PHY_AGC_CONTROL_ENABLE_NF); | ||
222 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | ||
223 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | ||
224 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | ||
225 | |||
226 | for (j = 0; j < 5; j++) { | ||
227 | if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & | ||
228 | AR_PHY_AGC_CONTROL_NF) == 0) | ||
229 | break; | ||
230 | udelay(50); | ||
231 | } | ||
232 | |||
233 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
234 | if (chainmask & (1 << i)) { | ||
235 | val = REG_READ(ah, ar5416_cca_regs[i]); | ||
236 | val &= 0xFFFFFE00; | ||
237 | val |= (((u32) (-50) << 1) & 0x1ff); | ||
238 | REG_WRITE(ah, ar5416_cca_regs[i], val); | ||
239 | } | ||
240 | } | ||
241 | } | ||
242 | |||
243 | int16_t ath9k_hw_getnf(struct ath_hw *ah, | 176 | int16_t ath9k_hw_getnf(struct ath_hw *ah, |
244 | struct ath9k_channel *chan) | 177 | struct ath9k_channel *chan) |
245 | { | 178 | { |