diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_phy.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.c | 1134 |
1 files changed, 1134 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c new file mode 100644 index 00000000000..80431a2f6dc --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
@@ -0,0 +1,1134 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2010 Atheros Communications Inc. | ||
3 | * | ||
4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
5 | * purpose with or without fee is hereby granted, provided that the above | ||
6 | * copyright notice and this permission notice appear in all copies. | ||
7 | * | ||
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
15 | */ | ||
16 | |||
17 | #include "hw.h" | ||
18 | #include "ar9003_phy.h" | ||
19 | |||
20 | /** | ||
21 | * ar9003_hw_set_channel - set channel on single-chip device | ||
22 | * @ah: atheros hardware structure | ||
23 | * @chan: | ||
24 | * | ||
25 | * This is the function to change channel on single-chip devices, that is | ||
26 | * all devices after ar9280. | ||
27 | * | ||
28 | * This function takes the channel value in MHz and sets | ||
29 | * hardware channel value. Assumes writes have been enabled to analog bus. | ||
30 | * | ||
31 | * Actual Expression, | ||
32 | * | ||
33 | * For 2GHz channel, | ||
34 | * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | ||
35 | * (freq_ref = 40MHz) | ||
36 | * | ||
37 | * For 5GHz channel, | ||
38 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) | ||
39 | * (freq_ref = 40MHz/(24>>amodeRefSel)) | ||
40 | * | ||
41 | * For 5GHz channels which are 5MHz spaced, | ||
42 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | ||
43 | * (freq_ref = 40MHz) | ||
44 | */ | ||
45 | static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | ||
46 | { | ||
47 | u16 bMode, fracMode = 0, aModeRefSel = 0; | ||
48 | u32 freq, channelSel = 0, reg32 = 0; | ||
49 | struct chan_centers centers; | ||
50 | int loadSynthChannel; | ||
51 | |||
52 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
53 | freq = centers.synth_center; | ||
54 | |||
55 | if (freq < 4800) { /* 2 GHz, fractional mode */ | ||
56 | channelSel = CHANSEL_2G(freq); | ||
57 | /* Set to 2G mode */ | ||
58 | bMode = 1; | ||
59 | } else { | ||
60 | channelSel = CHANSEL_5G(freq); | ||
61 | /* Doubler is ON, so, divide channelSel by 2. */ | ||
62 | channelSel >>= 1; | ||
63 | /* Set to 5G mode */ | ||
64 | bMode = 0; | ||
65 | } | ||
66 | |||
67 | /* Enable fractional mode for all channels */ | ||
68 | fracMode = 1; | ||
69 | aModeRefSel = 0; | ||
70 | loadSynthChannel = 0; | ||
71 | |||
72 | reg32 = (bMode << 29); | ||
73 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); | ||
74 | |||
75 | /* Enable Long shift Select for Synthesizer */ | ||
76 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, | ||
77 | AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); | ||
78 | |||
79 | /* Program Synth. setting */ | ||
80 | reg32 = (channelSel << 2) | (fracMode << 30) | | ||
81 | (aModeRefSel << 28) | (loadSynthChannel << 31); | ||
82 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | ||
83 | |||
84 | /* Toggle Load Synth channel bit */ | ||
85 | loadSynthChannel = 1; | ||
86 | reg32 = (channelSel << 2) | (fracMode << 30) | | ||
87 | (aModeRefSel << 28) | (loadSynthChannel << 31); | ||
88 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | ||
89 | |||
90 | ah->curchan = chan; | ||
91 | ah->curchan_rad_index = -1; | ||
92 | |||
93 | return 0; | ||
94 | } | ||
95 | |||
96 | /** | ||
97 | * ar9003_hw_spur_mitigate - convert baseband spur frequency | ||
98 | * @ah: atheros hardware structure | ||
99 | * @chan: | ||
100 | * | ||
101 | * For single-chip solutions. Converts to baseband spur frequency given the | ||
102 | * input channel frequency and compute register settings below. | ||
103 | * | ||
104 | * Spur mitigation for MRC CCK | ||
105 | */ | ||
106 | static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, | ||
107 | struct ath9k_channel *chan) | ||
108 | { | ||
109 | u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; | ||
110 | int cur_bb_spur, negative = 0, cck_spur_freq; | ||
111 | int i; | ||
112 | |||
113 | /* | ||
114 | * Need to verify range +/- 10 MHz in control channel, otherwise spur | ||
115 | * is out-of-band and can be ignored. | ||
116 | */ | ||
117 | |||
118 | for (i = 0; i < 4; i++) { | ||
119 | negative = 0; | ||
120 | cur_bb_spur = spur_freq[i] - chan->channel; | ||
121 | |||
122 | if (cur_bb_spur < 0) { | ||
123 | negative = 1; | ||
124 | cur_bb_spur = -cur_bb_spur; | ||
125 | } | ||
126 | if (cur_bb_spur < 10) { | ||
127 | cck_spur_freq = (int)((cur_bb_spur << 19) / 11); | ||
128 | |||
129 | if (negative == 1) | ||
130 | cck_spur_freq = -cck_spur_freq; | ||
131 | |||
132 | cck_spur_freq = cck_spur_freq & 0xfffff; | ||
133 | |||
134 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | ||
135 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); | ||
136 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | ||
137 | AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); | ||
138 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | ||
139 | AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, | ||
140 | 0x2); | ||
141 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | ||
142 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, | ||
143 | 0x1); | ||
144 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | ||
145 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, | ||
146 | cck_spur_freq); | ||
147 | |||
148 | return; | ||
149 | } | ||
150 | } | ||
151 | |||
152 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | ||
153 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); | ||
154 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | ||
155 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); | ||
156 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | ||
157 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); | ||
158 | } | ||
159 | |||
160 | /* Clean all spur register fields */ | ||
161 | static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) | ||
162 | { | ||
163 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
164 | AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); | ||
165 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
166 | AR_PHY_TIMING11_SPUR_FREQ_SD, 0); | ||
167 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
168 | AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); | ||
169 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
170 | AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); | ||
171 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
172 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); | ||
173 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
174 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); | ||
175 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
176 | AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); | ||
177 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
178 | AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); | ||
179 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
180 | AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); | ||
181 | |||
182 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
183 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); | ||
184 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
185 | AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); | ||
186 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
187 | AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); | ||
188 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | ||
189 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); | ||
190 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | ||
191 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); | ||
192 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | ||
193 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); | ||
194 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | ||
195 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); | ||
196 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | ||
197 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); | ||
198 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | ||
199 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); | ||
200 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
201 | AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); | ||
202 | } | ||
203 | |||
204 | static void ar9003_hw_spur_ofdm(struct ath_hw *ah, | ||
205 | int freq_offset, | ||
206 | int spur_freq_sd, | ||
207 | int spur_delta_phase, | ||
208 | int spur_subchannel_sd) | ||
209 | { | ||
210 | int mask_index = 0; | ||
211 | |||
212 | /* OFDM Spur mitigation */ | ||
213 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
214 | AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); | ||
215 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
216 | AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); | ||
217 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
218 | AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); | ||
219 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
220 | AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); | ||
221 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
222 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); | ||
223 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | ||
224 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); | ||
225 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
226 | AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); | ||
227 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
228 | AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); | ||
229 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
230 | AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); | ||
231 | |||
232 | if (REG_READ_FIELD(ah, AR_PHY_MODE, | ||
233 | AR_PHY_MODE_DYNAMIC) == 0x1) | ||
234 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
235 | AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); | ||
236 | |||
237 | mask_index = (freq_offset << 4) / 5; | ||
238 | if (mask_index < 0) | ||
239 | mask_index = mask_index - 1; | ||
240 | |||
241 | mask_index = mask_index & 0x7f; | ||
242 | |||
243 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
244 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); | ||
245 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
246 | AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); | ||
247 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | ||
248 | AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); | ||
249 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | ||
250 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); | ||
251 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | ||
252 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); | ||
253 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | ||
254 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); | ||
255 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | ||
256 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); | ||
257 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | ||
258 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); | ||
259 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | ||
260 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); | ||
261 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | ||
262 | AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); | ||
263 | } | ||
264 | |||
265 | static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, | ||
266 | struct ath9k_channel *chan, | ||
267 | int freq_offset) | ||
268 | { | ||
269 | int spur_freq_sd = 0; | ||
270 | int spur_subchannel_sd = 0; | ||
271 | int spur_delta_phase = 0; | ||
272 | |||
273 | if (IS_CHAN_HT40(chan)) { | ||
274 | if (freq_offset < 0) { | ||
275 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, | ||
276 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) | ||
277 | spur_subchannel_sd = 1; | ||
278 | else | ||
279 | spur_subchannel_sd = 0; | ||
280 | |||
281 | spur_freq_sd = ((freq_offset + 10) << 9) / 11; | ||
282 | |||
283 | } else { | ||
284 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, | ||
285 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) | ||
286 | spur_subchannel_sd = 0; | ||
287 | else | ||
288 | spur_subchannel_sd = 1; | ||
289 | |||
290 | spur_freq_sd = ((freq_offset - 10) << 9) / 11; | ||
291 | |||
292 | } | ||
293 | |||
294 | spur_delta_phase = (freq_offset << 17) / 5; | ||
295 | |||
296 | } else { | ||
297 | spur_subchannel_sd = 0; | ||
298 | spur_freq_sd = (freq_offset << 9) /11; | ||
299 | spur_delta_phase = (freq_offset << 18) / 5; | ||
300 | } | ||
301 | |||
302 | spur_freq_sd = spur_freq_sd & 0x3ff; | ||
303 | spur_delta_phase = spur_delta_phase & 0xfffff; | ||
304 | |||
305 | ar9003_hw_spur_ofdm(ah, | ||
306 | freq_offset, | ||
307 | spur_freq_sd, | ||
308 | spur_delta_phase, | ||
309 | spur_subchannel_sd); | ||
310 | } | ||
311 | |||
312 | /* Spur mitigation for OFDM */ | ||
313 | static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, | ||
314 | struct ath9k_channel *chan) | ||
315 | { | ||
316 | int synth_freq; | ||
317 | int range = 10; | ||
318 | int freq_offset = 0; | ||
319 | int mode; | ||
320 | u8* spurChansPtr; | ||
321 | unsigned int i; | ||
322 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | ||
323 | |||
324 | if (IS_CHAN_5GHZ(chan)) { | ||
325 | spurChansPtr = &(eep->modalHeader5G.spurChans[0]); | ||
326 | mode = 0; | ||
327 | } | ||
328 | else { | ||
329 | spurChansPtr = &(eep->modalHeader2G.spurChans[0]); | ||
330 | mode = 1; | ||
331 | } | ||
332 | |||
333 | if (spurChansPtr[0] == 0) | ||
334 | return; /* No spur in the mode */ | ||
335 | |||
336 | if (IS_CHAN_HT40(chan)) { | ||
337 | range = 19; | ||
338 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, | ||
339 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) | ||
340 | synth_freq = chan->channel - 10; | ||
341 | else | ||
342 | synth_freq = chan->channel + 10; | ||
343 | } else { | ||
344 | range = 10; | ||
345 | synth_freq = chan->channel; | ||
346 | } | ||
347 | |||
348 | ar9003_hw_spur_ofdm_clear(ah); | ||
349 | |||
350 | for (i = 0; spurChansPtr[i] && i < 5; i++) { | ||
351 | freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq; | ||
352 | if (abs(freq_offset) < range) { | ||
353 | ar9003_hw_spur_ofdm_work(ah, chan, freq_offset); | ||
354 | break; | ||
355 | } | ||
356 | } | ||
357 | } | ||
358 | |||
359 | static void ar9003_hw_spur_mitigate(struct ath_hw *ah, | ||
360 | struct ath9k_channel *chan) | ||
361 | { | ||
362 | ar9003_hw_spur_mitigate_mrc_cck(ah, chan); | ||
363 | ar9003_hw_spur_mitigate_ofdm(ah, chan); | ||
364 | } | ||
365 | |||
366 | static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, | ||
367 | struct ath9k_channel *chan) | ||
368 | { | ||
369 | u32 pll; | ||
370 | |||
371 | pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); | ||
372 | |||
373 | if (chan && IS_CHAN_HALF_RATE(chan)) | ||
374 | pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); | ||
375 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | ||
376 | pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); | ||
377 | |||
378 | pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); | ||
379 | |||
380 | return pll; | ||
381 | } | ||
382 | |||
383 | static void ar9003_hw_set_channel_regs(struct ath_hw *ah, | ||
384 | struct ath9k_channel *chan) | ||
385 | { | ||
386 | u32 phymode; | ||
387 | u32 enableDacFifo = 0; | ||
388 | |||
389 | enableDacFifo = | ||
390 | (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); | ||
391 | |||
392 | /* Enable 11n HT, 20 MHz */ | ||
393 | phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH | | ||
394 | AR_PHY_GC_SHORT_GI_40 | enableDacFifo; | ||
395 | |||
396 | /* Configure baseband for dynamic 20/40 operation */ | ||
397 | if (IS_CHAN_HT40(chan)) { | ||
398 | phymode |= AR_PHY_GC_DYN2040_EN; | ||
399 | /* Configure control (primary) channel at +-10MHz */ | ||
400 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || | ||
401 | (chan->chanmode == CHANNEL_G_HT40PLUS)) | ||
402 | phymode |= AR_PHY_GC_DYN2040_PRI_CH; | ||
403 | |||
404 | } | ||
405 | |||
406 | /* make sure we preserve INI settings */ | ||
407 | phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); | ||
408 | /* turn off Green Field detection for STA for now */ | ||
409 | phymode &= ~AR_PHY_GC_GF_DETECT_EN; | ||
410 | |||
411 | REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); | ||
412 | |||
413 | /* Configure MAC for 20/40 operation */ | ||
414 | ath9k_hw_set11nmac2040(ah); | ||
415 | |||
416 | /* global transmit timeout (25 TUs default)*/ | ||
417 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); | ||
418 | /* carrier sense timeout */ | ||
419 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | ||
420 | } | ||
421 | |||
422 | static void ar9003_hw_init_bb(struct ath_hw *ah, | ||
423 | struct ath9k_channel *chan) | ||
424 | { | ||
425 | u32 synthDelay; | ||
426 | |||
427 | /* | ||
428 | * Wait for the frequency synth to settle (synth goes on | ||
429 | * via AR_PHY_ACTIVE_EN). Read the phy active delay register. | ||
430 | * Value is in 100ns increments. | ||
431 | */ | ||
432 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | ||
433 | if (IS_CHAN_B(chan)) | ||
434 | synthDelay = (4 * synthDelay) / 22; | ||
435 | else | ||
436 | synthDelay /= 10; | ||
437 | |||
438 | /* Activate the PHY (includes baseband activate + synthesizer on) */ | ||
439 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); | ||
440 | |||
441 | /* | ||
442 | * There is an issue if the AP starts the calibration before | ||
443 | * the base band timeout completes. This could result in the | ||
444 | * rx_clear false triggering. As a workaround we add delay an | ||
445 | * extra BASE_ACTIVATE_DELAY usecs to ensure this condition | ||
446 | * does not happen. | ||
447 | */ | ||
448 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | ||
449 | } | ||
450 | |||
451 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) | ||
452 | { | ||
453 | switch (rx) { | ||
454 | case 0x5: | ||
455 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | ||
456 | AR_PHY_SWAP_ALT_CHAIN); | ||
457 | case 0x3: | ||
458 | case 0x1: | ||
459 | case 0x2: | ||
460 | case 0x7: | ||
461 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); | ||
462 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); | ||
463 | break; | ||
464 | default: | ||
465 | break; | ||
466 | } | ||
467 | |||
468 | REG_WRITE(ah, AR_SELFGEN_MASK, tx); | ||
469 | if (tx == 0x5) { | ||
470 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | ||
471 | AR_PHY_SWAP_ALT_CHAIN); | ||
472 | } | ||
473 | } | ||
474 | |||
475 | /* | ||
476 | * Override INI values with chip specific configuration. | ||
477 | */ | ||
478 | static void ar9003_hw_override_ini(struct ath_hw *ah) | ||
479 | { | ||
480 | u32 val; | ||
481 | |||
482 | /* | ||
483 | * Set the RX_ABORT and RX_DIS and clear it only after | ||
484 | * RXE is set for MAC. This prevents frames with | ||
485 | * corrupted descriptor status. | ||
486 | */ | ||
487 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | ||
488 | |||
489 | /* | ||
490 | * For AR9280 and above, there is a new feature that allows | ||
491 | * Multicast search based on both MAC Address and Key ID. By default, | ||
492 | * this feature is enabled. But since the driver is not using this | ||
493 | * feature, we switch it off; otherwise multicast search based on | ||
494 | * MAC addr only will fail. | ||
495 | */ | ||
496 | val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); | ||
497 | REG_WRITE(ah, AR_PCU_MISC_MODE2, | ||
498 | val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); | ||
499 | } | ||
500 | |||
501 | static void ar9003_hw_prog_ini(struct ath_hw *ah, | ||
502 | struct ar5416IniArray *iniArr, | ||
503 | int column) | ||
504 | { | ||
505 | unsigned int i, regWrites = 0; | ||
506 | |||
507 | /* New INI format: Array may be undefined (pre, core, post arrays) */ | ||
508 | if (!iniArr->ia_array) | ||
509 | return; | ||
510 | |||
511 | /* | ||
512 | * New INI format: Pre, core, and post arrays for a given subsystem | ||
513 | * may be modal (> 2 columns) or non-modal (2 columns). Determine if | ||
514 | * the array is non-modal and force the column to 1. | ||
515 | */ | ||
516 | if (column >= iniArr->ia_columns) | ||
517 | column = 1; | ||
518 | |||
519 | for (i = 0; i < iniArr->ia_rows; i++) { | ||
520 | u32 reg = INI_RA(iniArr, i, 0); | ||
521 | u32 val = INI_RA(iniArr, i, column); | ||
522 | |||
523 | REG_WRITE(ah, reg, val); | ||
524 | |||
525 | /* | ||
526 | * Determine if this is a shift register value, and insert the | ||
527 | * configured delay if so. | ||
528 | */ | ||
529 | if (reg >= 0x16000 && reg < 0x17000 | ||
530 | && ah->config.analog_shiftreg) | ||
531 | udelay(100); | ||
532 | |||
533 | DO_DELAY(regWrites); | ||
534 | } | ||
535 | } | ||
536 | |||
537 | static int ar9003_hw_process_ini(struct ath_hw *ah, | ||
538 | struct ath9k_channel *chan) | ||
539 | { | ||
540 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); | ||
541 | unsigned int regWrites = 0, i; | ||
542 | struct ieee80211_channel *channel = chan->chan; | ||
543 | u32 modesIndex, freqIndex; | ||
544 | |||
545 | switch (chan->chanmode) { | ||
546 | case CHANNEL_A: | ||
547 | case CHANNEL_A_HT20: | ||
548 | modesIndex = 1; | ||
549 | freqIndex = 1; | ||
550 | break; | ||
551 | case CHANNEL_A_HT40PLUS: | ||
552 | case CHANNEL_A_HT40MINUS: | ||
553 | modesIndex = 2; | ||
554 | freqIndex = 1; | ||
555 | break; | ||
556 | case CHANNEL_G: | ||
557 | case CHANNEL_G_HT20: | ||
558 | case CHANNEL_B: | ||
559 | modesIndex = 4; | ||
560 | freqIndex = 2; | ||
561 | break; | ||
562 | case CHANNEL_G_HT40PLUS: | ||
563 | case CHANNEL_G_HT40MINUS: | ||
564 | modesIndex = 3; | ||
565 | freqIndex = 2; | ||
566 | break; | ||
567 | |||
568 | default: | ||
569 | return -EINVAL; | ||
570 | } | ||
571 | |||
572 | for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { | ||
573 | ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); | ||
574 | ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); | ||
575 | ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); | ||
576 | ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); | ||
577 | } | ||
578 | |||
579 | REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); | ||
580 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); | ||
581 | |||
582 | /* | ||
583 | * For 5GHz channels requiring Fast Clock, apply | ||
584 | * different modal values. | ||
585 | */ | ||
586 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | ||
587 | REG_WRITE_ARRAY(&ah->iniModesAdditional, | ||
588 | modesIndex, regWrites); | ||
589 | |||
590 | ar9003_hw_override_ini(ah); | ||
591 | ar9003_hw_set_channel_regs(ah, chan); | ||
592 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); | ||
593 | |||
594 | /* Set TX power */ | ||
595 | ah->eep_ops->set_txpower(ah, chan, | ||
596 | ath9k_regd_get_ctl(regulatory, chan), | ||
597 | channel->max_antenna_gain * 2, | ||
598 | channel->max_power * 2, | ||
599 | min((u32) MAX_RATE_POWER, | ||
600 | (u32) regulatory->power_limit)); | ||
601 | |||
602 | return 0; | ||
603 | } | ||
604 | |||
605 | static void ar9003_hw_set_rfmode(struct ath_hw *ah, | ||
606 | struct ath9k_channel *chan) | ||
607 | { | ||
608 | u32 rfMode = 0; | ||
609 | |||
610 | if (chan == NULL) | ||
611 | return; | ||
612 | |||
613 | rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) | ||
614 | ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; | ||
615 | |||
616 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | ||
617 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); | ||
618 | |||
619 | REG_WRITE(ah, AR_PHY_MODE, rfMode); | ||
620 | } | ||
621 | |||
622 | static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) | ||
623 | { | ||
624 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); | ||
625 | } | ||
626 | |||
627 | static void ar9003_hw_set_delta_slope(struct ath_hw *ah, | ||
628 | struct ath9k_channel *chan) | ||
629 | { | ||
630 | u32 coef_scaled, ds_coef_exp, ds_coef_man; | ||
631 | u32 clockMhzScaled = 0x64000000; | ||
632 | struct chan_centers centers; | ||
633 | |||
634 | /* | ||
635 | * half and quarter rate can divide the scaled clock by 2 or 4 | ||
636 | * scale for selected channel bandwidth | ||
637 | */ | ||
638 | if (IS_CHAN_HALF_RATE(chan)) | ||
639 | clockMhzScaled = clockMhzScaled >> 1; | ||
640 | else if (IS_CHAN_QUARTER_RATE(chan)) | ||
641 | clockMhzScaled = clockMhzScaled >> 2; | ||
642 | |||
643 | /* | ||
644 | * ALGO -> coef = 1e8/fcarrier*fclock/40; | ||
645 | * scaled coef to provide precision for this floating calculation | ||
646 | */ | ||
647 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | ||
648 | coef_scaled = clockMhzScaled / centers.synth_center; | ||
649 | |||
650 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | ||
651 | &ds_coef_exp); | ||
652 | |||
653 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | ||
654 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); | ||
655 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | ||
656 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); | ||
657 | |||
658 | /* | ||
659 | * For Short GI, | ||
660 | * scaled coeff is 9/10 that of normal coeff | ||
661 | */ | ||
662 | coef_scaled = (9 * coef_scaled) / 10; | ||
663 | |||
664 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | ||
665 | &ds_coef_exp); | ||
666 | |||
667 | /* for short gi */ | ||
668 | REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, | ||
669 | AR_PHY_SGI_DSC_MAN, ds_coef_man); | ||
670 | REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, | ||
671 | AR_PHY_SGI_DSC_EXP, ds_coef_exp); | ||
672 | } | ||
673 | |||
674 | static bool ar9003_hw_rfbus_req(struct ath_hw *ah) | ||
675 | { | ||
676 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); | ||
677 | return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, | ||
678 | AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); | ||
679 | } | ||
680 | |||
681 | /* | ||
682 | * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). | ||
683 | * Read the phy active delay register. Value is in 100ns increments. | ||
684 | */ | ||
685 | static void ar9003_hw_rfbus_done(struct ath_hw *ah) | ||
686 | { | ||
687 | u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | ||
688 | if (IS_CHAN_B(ah->curchan)) | ||
689 | synthDelay = (4 * synthDelay) / 22; | ||
690 | else | ||
691 | synthDelay /= 10; | ||
692 | |||
693 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | ||
694 | |||
695 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); | ||
696 | } | ||
697 | |||
698 | /* | ||
699 | * Set the interrupt and GPIO values so the ISR can disable RF | ||
700 | * on a switch signal. Assumes GPIO port and interrupt polarity | ||
701 | * are set prior to call. | ||
702 | */ | ||
703 | static void ar9003_hw_enable_rfkill(struct ath_hw *ah) | ||
704 | { | ||
705 | /* Connect rfsilent_bb_l to baseband */ | ||
706 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | ||
707 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); | ||
708 | /* Set input mux for rfsilent_bb_l to GPIO #0 */ | ||
709 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, | ||
710 | AR_GPIO_INPUT_MUX2_RFSILENT); | ||
711 | |||
712 | /* | ||
713 | * Configure the desired GPIO port for input and | ||
714 | * enable baseband rf silence. | ||
715 | */ | ||
716 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); | ||
717 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); | ||
718 | } | ||
719 | |||
720 | static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value) | ||
721 | { | ||
722 | u32 v = REG_READ(ah, AR_PHY_CCK_DETECT); | ||
723 | if (value) | ||
724 | v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | ||
725 | else | ||
726 | v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | ||
727 | REG_WRITE(ah, AR_PHY_CCK_DETECT, v); | ||
728 | } | ||
729 | |||
730 | static bool ar9003_hw_ani_control(struct ath_hw *ah, | ||
731 | enum ath9k_ani_cmd cmd, int param) | ||
732 | { | ||
733 | struct ar5416AniState *aniState = ah->curani; | ||
734 | struct ath_common *common = ath9k_hw_common(ah); | ||
735 | |||
736 | switch (cmd & ah->ani_function) { | ||
737 | case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ | ||
738 | u32 level = param; | ||
739 | |||
740 | if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { | ||
741 | ath_print(common, ATH_DBG_ANI, | ||
742 | "level out of range (%u > %u)\n", | ||
743 | level, | ||
744 | (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); | ||
745 | return false; | ||
746 | } | ||
747 | |||
748 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, | ||
749 | AR_PHY_DESIRED_SZ_TOT_DES, | ||
750 | ah->totalSizeDesired[level]); | ||
751 | REG_RMW_FIELD(ah, AR_PHY_AGC, | ||
752 | AR_PHY_AGC_COARSE_LOW, | ||
753 | ah->coarse_low[level]); | ||
754 | REG_RMW_FIELD(ah, AR_PHY_AGC, | ||
755 | AR_PHY_AGC_COARSE_HIGH, | ||
756 | ah->coarse_high[level]); | ||
757 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | ||
758 | AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]); | ||
759 | |||
760 | if (level > aniState->noiseImmunityLevel) | ||
761 | ah->stats.ast_ani_niup++; | ||
762 | else if (level < aniState->noiseImmunityLevel) | ||
763 | ah->stats.ast_ani_nidown++; | ||
764 | aniState->noiseImmunityLevel = level; | ||
765 | break; | ||
766 | } | ||
767 | case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ | ||
768 | const int m1ThreshLow[] = { 127, 50 }; | ||
769 | const int m2ThreshLow[] = { 127, 40 }; | ||
770 | const int m1Thresh[] = { 127, 0x4d }; | ||
771 | const int m2Thresh[] = { 127, 0x40 }; | ||
772 | const int m2CountThr[] = { 31, 16 }; | ||
773 | const int m2CountThrLow[] = { 63, 48 }; | ||
774 | u32 on = param ? 1 : 0; | ||
775 | |||
776 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | ||
777 | AR_PHY_SFCORR_LOW_M1_THRESH_LOW, | ||
778 | m1ThreshLow[on]); | ||
779 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | ||
780 | AR_PHY_SFCORR_LOW_M2_THRESH_LOW, | ||
781 | m2ThreshLow[on]); | ||
782 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | ||
783 | AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]); | ||
784 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | ||
785 | AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]); | ||
786 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, | ||
787 | AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]); | ||
788 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | ||
789 | AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, | ||
790 | m2CountThrLow[on]); | ||
791 | |||
792 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
793 | AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]); | ||
794 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
795 | AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]); | ||
796 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
797 | AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]); | ||
798 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | ||
799 | AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]); | ||
800 | |||
801 | if (on) | ||
802 | REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, | ||
803 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | ||
804 | else | ||
805 | REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, | ||
806 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | ||
807 | |||
808 | if (!on != aniState->ofdmWeakSigDetectOff) { | ||
809 | if (on) | ||
810 | ah->stats.ast_ani_ofdmon++; | ||
811 | else | ||
812 | ah->stats.ast_ani_ofdmoff++; | ||
813 | aniState->ofdmWeakSigDetectOff = !on; | ||
814 | } | ||
815 | break; | ||
816 | } | ||
817 | case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{ | ||
818 | const int weakSigThrCck[] = { 8, 6 }; | ||
819 | u32 high = param ? 1 : 0; | ||
820 | |||
821 | REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, | ||
822 | AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, | ||
823 | weakSigThrCck[high]); | ||
824 | if (high != aniState->cckWeakSigThreshold) { | ||
825 | if (high) | ||
826 | ah->stats.ast_ani_cckhigh++; | ||
827 | else | ||
828 | ah->stats.ast_ani_ccklow++; | ||
829 | aniState->cckWeakSigThreshold = high; | ||
830 | } | ||
831 | break; | ||
832 | } | ||
833 | case ATH9K_ANI_FIRSTEP_LEVEL:{ | ||
834 | const int firstep[] = { 0, 4, 8 }; | ||
835 | u32 level = param; | ||
836 | |||
837 | if (level >= ARRAY_SIZE(firstep)) { | ||
838 | ath_print(common, ATH_DBG_ANI, | ||
839 | "level out of range (%u > %u)\n", | ||
840 | level, | ||
841 | (unsigned) ARRAY_SIZE(firstep)); | ||
842 | return false; | ||
843 | } | ||
844 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | ||
845 | AR_PHY_FIND_SIG_FIRSTEP, | ||
846 | firstep[level]); | ||
847 | if (level > aniState->firstepLevel) | ||
848 | ah->stats.ast_ani_stepup++; | ||
849 | else if (level < aniState->firstepLevel) | ||
850 | ah->stats.ast_ani_stepdown++; | ||
851 | aniState->firstepLevel = level; | ||
852 | break; | ||
853 | } | ||
854 | case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ | ||
855 | const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; | ||
856 | u32 level = param; | ||
857 | |||
858 | if (level >= ARRAY_SIZE(cycpwrThr1)) { | ||
859 | ath_print(common, ATH_DBG_ANI, | ||
860 | "level out of range (%u > %u)\n", | ||
861 | level, | ||
862 | (unsigned) ARRAY_SIZE(cycpwrThr1)); | ||
863 | return false; | ||
864 | } | ||
865 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, | ||
866 | AR_PHY_TIMING5_CYCPWR_THR1, | ||
867 | cycpwrThr1[level]); | ||
868 | if (level > aniState->spurImmunityLevel) | ||
869 | ah->stats.ast_ani_spurup++; | ||
870 | else if (level < aniState->spurImmunityLevel) | ||
871 | ah->stats.ast_ani_spurdown++; | ||
872 | aniState->spurImmunityLevel = level; | ||
873 | break; | ||
874 | } | ||
875 | case ATH9K_ANI_PRESENT: | ||
876 | break; | ||
877 | default: | ||
878 | ath_print(common, ATH_DBG_ANI, | ||
879 | "invalid cmd %u\n", cmd); | ||
880 | return false; | ||
881 | } | ||
882 | |||
883 | ath_print(common, ATH_DBG_ANI, "ANI parameters:\n"); | ||
884 | ath_print(common, ATH_DBG_ANI, | ||
885 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, " | ||
886 | "ofdmWeakSigDetectOff=%d\n", | ||
887 | aniState->noiseImmunityLevel, | ||
888 | aniState->spurImmunityLevel, | ||
889 | !aniState->ofdmWeakSigDetectOff); | ||
890 | ath_print(common, ATH_DBG_ANI, | ||
891 | "cckWeakSigThreshold=%d, " | ||
892 | "firstepLevel=%d, listenTime=%d\n", | ||
893 | aniState->cckWeakSigThreshold, | ||
894 | aniState->firstepLevel, | ||
895 | aniState->listenTime); | ||
896 | ath_print(common, ATH_DBG_ANI, | ||
897 | "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", | ||
898 | aniState->cycleCount, | ||
899 | aniState->ofdmPhyErrCount, | ||
900 | aniState->cckPhyErrCount); | ||
901 | |||
902 | return true; | ||
903 | } | ||
904 | |||
905 | static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf) | ||
906 | { | ||
907 | struct ath_common *common = ath9k_hw_common(ah); | ||
908 | |||
909 | if (*nf > ah->nf_2g_max) { | ||
910 | ath_print(common, ATH_DBG_CALIBRATE, | ||
911 | "2 GHz NF (%d) > MAX (%d), " | ||
912 | "correcting to MAX", | ||
913 | *nf, ah->nf_2g_max); | ||
914 | *nf = ah->nf_2g_max; | ||
915 | } else if (*nf < ah->nf_2g_min) { | ||
916 | ath_print(common, ATH_DBG_CALIBRATE, | ||
917 | "2 GHz NF (%d) < MIN (%d), " | ||
918 | "correcting to MIN", | ||
919 | *nf, ah->nf_2g_min); | ||
920 | *nf = ah->nf_2g_min; | ||
921 | } | ||
922 | } | ||
923 | |||
924 | static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf) | ||
925 | { | ||
926 | struct ath_common *common = ath9k_hw_common(ah); | ||
927 | |||
928 | if (*nf > ah->nf_5g_max) { | ||
929 | ath_print(common, ATH_DBG_CALIBRATE, | ||
930 | "5 GHz NF (%d) > MAX (%d), " | ||
931 | "correcting to MAX", | ||
932 | *nf, ah->nf_5g_max); | ||
933 | *nf = ah->nf_5g_max; | ||
934 | } else if (*nf < ah->nf_5g_min) { | ||
935 | ath_print(common, ATH_DBG_CALIBRATE, | ||
936 | "5 GHz NF (%d) < MIN (%d), " | ||
937 | "correcting to MIN", | ||
938 | *nf, ah->nf_5g_min); | ||
939 | *nf = ah->nf_5g_min; | ||
940 | } | ||
941 | } | ||
942 | |||
943 | static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf) | ||
944 | { | ||
945 | if (IS_CHAN_2GHZ(ah->curchan)) | ||
946 | ar9003_hw_nf_sanitize_2g(ah, nf); | ||
947 | else | ||
948 | ar9003_hw_nf_sanitize_5g(ah, nf); | ||
949 | } | ||
950 | |||
951 | static void ar9003_hw_do_getnf(struct ath_hw *ah, | ||
952 | int16_t nfarray[NUM_NF_READINGS]) | ||
953 | { | ||
954 | struct ath_common *common = ath9k_hw_common(ah); | ||
955 | int16_t nf; | ||
956 | |||
957 | nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR); | ||
958 | if (nf & 0x100) | ||
959 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
960 | ar9003_hw_nf_sanitize(ah, &nf); | ||
961 | ath_print(common, ATH_DBG_CALIBRATE, | ||
962 | "NF calibrated [ctl] [chain 0] is %d\n", nf); | ||
963 | nfarray[0] = nf; | ||
964 | |||
965 | nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR); | ||
966 | if (nf & 0x100) | ||
967 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
968 | ar9003_hw_nf_sanitize(ah, &nf); | ||
969 | ath_print(common, ATH_DBG_CALIBRATE, | ||
970 | "NF calibrated [ctl] [chain 1] is %d\n", nf); | ||
971 | nfarray[1] = nf; | ||
972 | |||
973 | nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR); | ||
974 | if (nf & 0x100) | ||
975 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
976 | ar9003_hw_nf_sanitize(ah, &nf); | ||
977 | ath_print(common, ATH_DBG_CALIBRATE, | ||
978 | "NF calibrated [ctl] [chain 2] is %d\n", nf); | ||
979 | nfarray[2] = nf; | ||
980 | |||
981 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); | ||
982 | if (nf & 0x100) | ||
983 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
984 | ar9003_hw_nf_sanitize(ah, &nf); | ||
985 | ath_print(common, ATH_DBG_CALIBRATE, | ||
986 | "NF calibrated [ext] [chain 0] is %d\n", nf); | ||
987 | nfarray[3] = nf; | ||
988 | |||
989 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR); | ||
990 | if (nf & 0x100) | ||
991 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
992 | ar9003_hw_nf_sanitize(ah, &nf); | ||
993 | ath_print(common, ATH_DBG_CALIBRATE, | ||
994 | "NF calibrated [ext] [chain 1] is %d\n", nf); | ||
995 | nfarray[4] = nf; | ||
996 | |||
997 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR); | ||
998 | if (nf & 0x100) | ||
999 | nf = 0 - ((nf ^ 0x1ff) + 1); | ||
1000 | ar9003_hw_nf_sanitize(ah, &nf); | ||
1001 | ath_print(common, ATH_DBG_CALIBRATE, | ||
1002 | "NF calibrated [ext] [chain 2] is %d\n", nf); | ||
1003 | nfarray[5] = nf; | ||
1004 | } | ||
1005 | |||
1006 | void ar9003_hw_set_nf_limits(struct ath_hw *ah) | ||
1007 | { | ||
1008 | ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; | ||
1009 | ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; | ||
1010 | ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; | ||
1011 | ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; | ||
1012 | } | ||
1013 | |||
1014 | /* | ||
1015 | * Find out which of the RX chains are enabled | ||
1016 | */ | ||
1017 | static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah) | ||
1018 | { | ||
1019 | u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK); | ||
1020 | /* | ||
1021 | * The bits [2:0] indicate the rx chain mask and are to be | ||
1022 | * interpreted as follows: | ||
1023 | * 00x => Only chain 0 is enabled | ||
1024 | * 01x => Chain 1 and 0 enabled | ||
1025 | * 1xx => Chain 2,1 and 0 enabled | ||
1026 | */ | ||
1027 | return chain & 0x7; | ||
1028 | } | ||
1029 | |||
1030 | static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) | ||
1031 | { | ||
1032 | struct ath9k_nfcal_hist *h; | ||
1033 | unsigned i, j; | ||
1034 | int32_t val; | ||
1035 | const u32 ar9300_cca_regs[6] = { | ||
1036 | AR_PHY_CCA_0, | ||
1037 | AR_PHY_CCA_1, | ||
1038 | AR_PHY_CCA_2, | ||
1039 | AR_PHY_EXT_CCA, | ||
1040 | AR_PHY_EXT_CCA_1, | ||
1041 | AR_PHY_EXT_CCA_2, | ||
1042 | }; | ||
1043 | u8 chainmask, rx_chain_status; | ||
1044 | struct ath_common *common = ath9k_hw_common(ah); | ||
1045 | |||
1046 | rx_chain_status = ar9003_hw_get_rx_chainmask(ah); | ||
1047 | |||
1048 | chainmask = 0x3F; | ||
1049 | h = ah->nfCalHist; | ||
1050 | |||
1051 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
1052 | if (chainmask & (1 << i)) { | ||
1053 | val = REG_READ(ah, ar9300_cca_regs[i]); | ||
1054 | val &= 0xFFFFFE00; | ||
1055 | val |= (((u32) (h[i].privNF) << 1) & 0x1ff); | ||
1056 | REG_WRITE(ah, ar9300_cca_regs[i], val); | ||
1057 | } | ||
1058 | } | ||
1059 | |||
1060 | /* | ||
1061 | * Load software filtered NF value into baseband internal minCCApwr | ||
1062 | * variable. | ||
1063 | */ | ||
1064 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | ||
1065 | AR_PHY_AGC_CONTROL_ENABLE_NF); | ||
1066 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | ||
1067 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | ||
1068 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | ||
1069 | |||
1070 | /* | ||
1071 | * Wait for load to complete, should be fast, a few 10s of us. | ||
1072 | * The max delay was changed from an original 250us to 10000us | ||
1073 | * since 250us often results in NF load timeout and causes deaf | ||
1074 | * condition during stress testing 12/12/2009 | ||
1075 | */ | ||
1076 | for (j = 0; j < 1000; j++) { | ||
1077 | if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & | ||
1078 | AR_PHY_AGC_CONTROL_NF) == 0) | ||
1079 | break; | ||
1080 | udelay(10); | ||
1081 | } | ||
1082 | |||
1083 | /* | ||
1084 | * We timed out waiting for the noisefloor to load, probably due to an | ||
1085 | * in-progress rx. Simply return here and allow the load plenty of time | ||
1086 | * to complete before the next calibration interval. We need to avoid | ||
1087 | * trying to load -50 (which happens below) while the previous load is | ||
1088 | * still in progress as this can cause rx deafness. Instead by returning | ||
1089 | * here, the baseband nf cal will just be capped by our present | ||
1090 | * noisefloor until the next calibration timer. | ||
1091 | */ | ||
1092 | if (j == 1000) { | ||
1093 | ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf " | ||
1094 | "to load: AR_PHY_AGC_CONTROL=0x%x\n", | ||
1095 | REG_READ(ah, AR_PHY_AGC_CONTROL)); | ||
1096 | return; | ||
1097 | } | ||
1098 | |||
1099 | /* | ||
1100 | * Restore maxCCAPower register parameter again so that we're not capped | ||
1101 | * by the median we just loaded. This will be initial (and max) value | ||
1102 | * of next noise floor calibration the baseband does. | ||
1103 | */ | ||
1104 | for (i = 0; i < NUM_NF_READINGS; i++) { | ||
1105 | if (chainmask & (1 << i)) { | ||
1106 | val = REG_READ(ah, ar9300_cca_regs[i]); | ||
1107 | val &= 0xFFFFFE00; | ||
1108 | val |= (((u32) (-50) << 1) & 0x1ff); | ||
1109 | REG_WRITE(ah, ar9300_cca_regs[i], val); | ||
1110 | } | ||
1111 | } | ||
1112 | } | ||
1113 | |||
1114 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah) | ||
1115 | { | ||
1116 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | ||
1117 | |||
1118 | priv_ops->rf_set_freq = ar9003_hw_set_channel; | ||
1119 | priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; | ||
1120 | priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; | ||
1121 | priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; | ||
1122 | priv_ops->init_bb = ar9003_hw_init_bb; | ||
1123 | priv_ops->process_ini = ar9003_hw_process_ini; | ||
1124 | priv_ops->set_rfmode = ar9003_hw_set_rfmode; | ||
1125 | priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; | ||
1126 | priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; | ||
1127 | priv_ops->rfbus_req = ar9003_hw_rfbus_req; | ||
1128 | priv_ops->rfbus_done = ar9003_hw_rfbus_done; | ||
1129 | priv_ops->enable_rfkill = ar9003_hw_enable_rfkill; | ||
1130 | priv_ops->set_diversity = ar9003_hw_set_diversity; | ||
1131 | priv_ops->ani_control = ar9003_hw_ani_control; | ||
1132 | priv_ops->do_getnf = ar9003_hw_do_getnf; | ||
1133 | priv_ops->loadnf = ar9003_hw_loadnf; | ||
1134 | } | ||