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Diffstat (limited to 'drivers/net/wireless/ath/ath6kl/init.c')
-rw-r--r--drivers/net/wireless/ath/ath6kl/init.c210
1 files changed, 81 insertions, 129 deletions
diff --git a/drivers/net/wireless/ath/ath6kl/init.c b/drivers/net/wireless/ath/ath6kl/init.c
index 0d76c377810..03cae142f17 100644
--- a/drivers/net/wireless/ath/ath6kl/init.c
+++ b/drivers/net/wireless/ath/ath6kl/init.c
@@ -1,6 +1,7 @@
1 1
2/* 2/*
3 * Copyright (c) 2011 Atheros Communications Inc. 3 * Copyright (c) 2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4 * 5 *
5 * Permission to use, copy, modify, and/or distribute this software for any 6 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above 7 * purpose with or without fee is hereby granted, provided that the above
@@ -74,7 +75,7 @@ static const struct ath6kl_hw hw_list[] = {
74 }, 75 },
75 76
76 .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 77 .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
77 .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 78 .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
78 }, 79 },
79 { 80 {
80 .id = AR6004_HW_1_0_VERSION, 81 .id = AR6004_HW_1_0_VERSION,
@@ -351,11 +352,7 @@ static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
351 blk_size |= ((u32)htc_ctrl_buf) << 16; 352 blk_size |= ((u32)htc_ctrl_buf) << 16;
352 353
353 /* set the host interest area for the block size */ 354 /* set the host interest area for the block size */
354 status = ath6kl_bmi_write(ar, 355 status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
355 ath6kl_get_hi_item_addr(ar,
356 HI_ITEM(hi_mbox_io_block_sz)),
357 (u8 *)&blk_size,
358 4);
359 if (status) { 356 if (status) {
360 ath6kl_err("bmi_write_memory for IO block size failed\n"); 357 ath6kl_err("bmi_write_memory for IO block size failed\n");
361 goto out; 358 goto out;
@@ -367,11 +364,8 @@ static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
367 364
368 if (mbox_isr_yield_val) { 365 if (mbox_isr_yield_val) {
369 /* set the host interest area for the mbox ISR yield limit */ 366 /* set the host interest area for the mbox ISR yield limit */
370 status = ath6kl_bmi_write(ar, 367 status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
371 ath6kl_get_hi_item_addr(ar, 368 mbox_isr_yield_val);
372 HI_ITEM(hi_mbox_isr_yield_limit)),
373 (u8 *)&mbox_isr_yield_val,
374 4);
375 if (status) { 369 if (status) {
376 ath6kl_err("bmi_write_memory for yield limit failed\n"); 370 ath6kl_err("bmi_write_memory for yield limit failed\n");
377 goto out; 371 goto out;
@@ -384,7 +378,6 @@ out:
384 378
385static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 379static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
386{ 380{
387 int status = 0;
388 int ret; 381 int ret;
389 382
390 /* 383 /*
@@ -392,43 +385,54 @@ static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
392 * default values. Required if checksum offload is needed. Set 385 * default values. Required if checksum offload is needed. Set
393 * RxMetaVersion to 2. 386 * RxMetaVersion to 2.
394 */ 387 */
395 if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 388 ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
396 ar->rx_meta_ver, 0, 0)) { 389 ar->rx_meta_ver, 0, 0);
397 ath6kl_err("unable to set the rx frame format\n"); 390 if (ret) {
398 status = -EIO; 391 ath6kl_err("unable to set the rx frame format: %d\n", ret);
392 return ret;
399 } 393 }
400 394
401 if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) 395 if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) {
402 if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 396 ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
403 IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) { 397 IGNORE_PS_FAIL_DURING_SCAN);
404 ath6kl_err("unable to set power save fail event policy\n"); 398 if (ret) {
405 status = -EIO; 399 ath6kl_err("unable to set power save fail event policy: %d\n",
400 ret);
401 return ret;
406 } 402 }
403 }
407 404
408 if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) 405 if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) {
409 if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 406 ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
410 WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) { 407 WMI_FOLLOW_BARKER_IN_ERP);
411 ath6kl_err("unable to set barker preamble policy\n"); 408 if (ret) {
412 status = -EIO; 409 ath6kl_err("unable to set barker preamble policy: %d\n",
410 ret);
411 return ret;
413 } 412 }
413 }
414 414
415 if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 415 ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
416 WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) { 416 WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
417 ath6kl_err("unable to set keep alive interval\n"); 417 if (ret) {
418 status = -EIO; 418 ath6kl_err("unable to set keep alive interval: %d\n", ret);
419 return ret;
419 } 420 }
420 421
421 if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 422 ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
422 WLAN_CONFIG_DISCONNECT_TIMEOUT)) { 423 WLAN_CONFIG_DISCONNECT_TIMEOUT);
423 ath6kl_err("unable to set disconnect timeout\n"); 424 if (ret) {
424 status = -EIO; 425 ath6kl_err("unable to set disconnect timeout: %d\n", ret);
426 return ret;
425 } 427 }
426 428
427 if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) 429 if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) {
428 if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) { 430 ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED);
429 ath6kl_err("unable to set txop bursting\n"); 431 if (ret) {
430 status = -EIO; 432 ath6kl_err("unable to set txop bursting: %d\n", ret);
433 return ret;
431 } 434 }
435 }
432 436
433 if (ar->p2p && (ar->vif_max == 1 || idx)) { 437 if (ar->p2p && (ar->vif_max == 1 || idx)) {
434 ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 438 ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
@@ -452,7 +456,7 @@ static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
452 } 456 }
453 } 457 }
454 458
455 return status; 459 return ret;
456} 460}
457 461
458int ath6kl_configure_target(struct ath6kl *ar) 462int ath6kl_configure_target(struct ath6kl *ar)
@@ -462,8 +466,7 @@ int ath6kl_configure_target(struct ath6kl *ar)
462 int i, status; 466 int i, status;
463 467
464 param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); 468 param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
465 if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 469 if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
466 HI_ITEM(hi_serial_enable)), (u8 *)&param, 4)) {
467 ath6kl_err("bmi_write_memory for uart debug failed\n"); 470 ath6kl_err("bmi_write_memory for uart debug failed\n");
468 return -EIO; 471 return -EIO;
469 } 472 }
@@ -499,11 +502,8 @@ int ath6kl_configure_target(struct ath6kl *ar)
499 if (ar->p2p && ar->vif_max == 1) 502 if (ar->p2p && ar->vif_max == 1)
500 fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 503 fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
501 504
502 param = HTC_PROTOCOL_VERSION; 505 if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
503 if (ath6kl_bmi_write(ar, 506 HTC_PROTOCOL_VERSION) != 0) {
504 ath6kl_get_hi_item_addr(ar,
505 HI_ITEM(hi_app_host_interest)),
506 (u8 *)&param, 4) != 0) {
507 ath6kl_err("bmi_write_memory for htc version failed\n"); 507 ath6kl_err("bmi_write_memory for htc version failed\n");
508 return -EIO; 508 return -EIO;
509 } 509 }
@@ -511,10 +511,7 @@ int ath6kl_configure_target(struct ath6kl *ar)
511 /* set the firmware mode to STA/IBSS/AP */ 511 /* set the firmware mode to STA/IBSS/AP */
512 param = 0; 512 param = 0;
513 513
514 if (ath6kl_bmi_read(ar, 514 if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
515 ath6kl_get_hi_item_addr(ar,
516 HI_ITEM(hi_option_flag)),
517 (u8 *)&param, 4) != 0) {
518 ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 515 ath6kl_err("bmi_read_memory for setting fwmode failed\n");
519 return -EIO; 516 return -EIO;
520 } 517 }
@@ -526,11 +523,7 @@ int ath6kl_configure_target(struct ath6kl *ar)
526 param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 523 param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
527 param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 524 param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
528 525
529 if (ath6kl_bmi_write(ar, 526 if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
530 ath6kl_get_hi_item_addr(ar,
531 HI_ITEM(hi_option_flag)),
532 (u8 *)&param,
533 4) != 0) {
534 ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 527 ath6kl_err("bmi_write_memory for setting fwmode failed\n");
535 return -EIO; 528 return -EIO;
536 } 529 }
@@ -549,16 +542,13 @@ int ath6kl_configure_target(struct ath6kl *ar)
549 param = ar->hw.board_ext_data_addr; 542 param = ar->hw.board_ext_data_addr;
550 ram_reserved_size = ar->hw.reserved_ram_size; 543 ram_reserved_size = ar->hw.reserved_ram_size;
551 544
552 if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 545 if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
553 HI_ITEM(hi_board_ext_data)),
554 (u8 *)&param, 4) != 0) {
555 ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 546 ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
556 return -EIO; 547 return -EIO;
557 } 548 }
558 549
559 if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 550 if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
560 HI_ITEM(hi_end_ram_reserve_sz)), 551 ram_reserved_size) != 0) {
561 (u8 *)&ram_reserved_size, 4) != 0) {
562 ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 552 ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
563 return -EIO; 553 return -EIO;
564 } 554 }
@@ -569,20 +559,13 @@ int ath6kl_configure_target(struct ath6kl *ar)
569 return -EIO; 559 return -EIO;
570 560
571 /* Configure GPIO AR600x UART */ 561 /* Configure GPIO AR600x UART */
572 param = ar->hw.uarttx_pin; 562 status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
573 status = ath6kl_bmi_write(ar, 563 ar->hw.uarttx_pin);
574 ath6kl_get_hi_item_addr(ar,
575 HI_ITEM(hi_dbg_uart_txpin)),
576 (u8 *)&param, 4);
577 if (status) 564 if (status)
578 return status; 565 return status;
579 566
580 /* Configure target refclk_hz */ 567 /* Configure target refclk_hz */
581 param = ar->hw.refclk_hz; 568 status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
582 status = ath6kl_bmi_write(ar,
583 ath6kl_get_hi_item_addr(ar,
584 HI_ITEM(hi_refclk_hz)),
585 (u8 *)&param, 4);
586 if (status) 569 if (status)
587 return status; 570 return status;
588 571
@@ -832,13 +815,13 @@ static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
832 return 0; 815 return 0;
833 816
834 snprintf(filename, sizeof(filename), "%s/%s", 817 snprintf(filename, sizeof(filename), "%s/%s",
835 ar->hw.fw.dir, ar->hw.fw.testscript); 818 ar->hw.fw.dir, ar->hw.fw.testscript);
836 819
837 ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, 820 ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
838 &ar->fw_testscript_len); 821 &ar->fw_testscript_len);
839 if (ret) { 822 if (ret) {
840 ath6kl_err("Failed to get testscript file %s: %d\n", 823 ath6kl_err("Failed to get testscript file %s: %d\n",
841 filename, ret); 824 filename, ret);
842 return ret; 825 return ret;
843 } 826 }
844 827
@@ -922,7 +905,7 @@ static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
922 switch (ie_id) { 905 switch (ie_id) {
923 case ATH6KL_FW_IE_OTP_IMAGE: 906 case ATH6KL_FW_IE_OTP_IMAGE:
924 ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 907 ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
925 ie_len); 908 ie_len);
926 909
927 ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 910 ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
928 911
@@ -935,7 +918,7 @@ static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
935 break; 918 break;
936 case ATH6KL_FW_IE_FW_IMAGE: 919 case ATH6KL_FW_IE_FW_IMAGE:
937 ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 920 ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
938 ie_len); 921 ie_len);
939 922
940 /* in testmode we already might have a fw file */ 923 /* in testmode we already might have a fw file */
941 if (ar->fw != NULL) 924 if (ar->fw != NULL)
@@ -952,7 +935,7 @@ static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
952 break; 935 break;
953 case ATH6KL_FW_IE_PATCH_IMAGE: 936 case ATH6KL_FW_IE_PATCH_IMAGE:
954 ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 937 ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
955 ie_len); 938 ie_len);
956 939
957 ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 940 ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
958 941
@@ -1096,22 +1079,14 @@ static int ath6kl_upload_board_file(struct ath6kl *ar)
1096 */ 1079 */
1097 if (ar->hw.board_addr != 0) { 1080 if (ar->hw.board_addr != 0) {
1098 board_address = ar->hw.board_addr; 1081 board_address = ar->hw.board_addr;
1099 ath6kl_bmi_write(ar, 1082 ath6kl_bmi_write_hi32(ar, hi_board_data,
1100 ath6kl_get_hi_item_addr(ar, 1083 board_address);
1101 HI_ITEM(hi_board_data)),
1102 (u8 *) &board_address, 4);
1103 } else { 1084 } else {
1104 ath6kl_bmi_read(ar, 1085 ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
1105 ath6kl_get_hi_item_addr(ar,
1106 HI_ITEM(hi_board_data)),
1107 (u8 *) &board_address, 4);
1108 } 1086 }
1109 1087
1110 /* determine where in target ram to write extended board data */ 1088 /* determine where in target ram to write extended board data */
1111 ath6kl_bmi_read(ar, 1089 ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
1112 ath6kl_get_hi_item_addr(ar,
1113 HI_ITEM(hi_board_ext_data)),
1114 (u8 *) &board_ext_address, 4);
1115 1090
1116 if (ar->target_type == TARGET_TYPE_AR6003 && 1091 if (ar->target_type == TARGET_TYPE_AR6003 &&
1117 board_ext_address == 0) { 1092 board_ext_address == 0) {
@@ -1123,6 +1098,8 @@ static int ath6kl_upload_board_file(struct ath6kl *ar)
1123 case TARGET_TYPE_AR6003: 1098 case TARGET_TYPE_AR6003:
1124 board_data_size = AR6003_BOARD_DATA_SZ; 1099 board_data_size = AR6003_BOARD_DATA_SZ;
1125 board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 1100 board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
1101 if (ar->fw_board_len > (board_data_size + board_ext_data_size))
1102 board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
1126 break; 1103 break;
1127 case TARGET_TYPE_AR6004: 1104 case TARGET_TYPE_AR6004:
1128 board_data_size = AR6004_BOARD_DATA_SZ; 1105 board_data_size = AR6004_BOARD_DATA_SZ;
@@ -1154,10 +1131,7 @@ static int ath6kl_upload_board_file(struct ath6kl *ar)
1154 /* record that extended board data is initialized */ 1131 /* record that extended board data is initialized */
1155 param = (board_ext_data_size << 16) | 1; 1132 param = (board_ext_data_size << 16) | 1;
1156 1133
1157 ath6kl_bmi_write(ar, 1134 ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
1158 ath6kl_get_hi_item_addr(ar,
1159 HI_ITEM(hi_board_ext_data_config)),
1160 (unsigned char *) &param, 4);
1161 } 1135 }
1162 1136
1163 if (ar->fw_board_len < board_data_size) { 1137 if (ar->fw_board_len < board_data_size) {
@@ -1178,11 +1152,7 @@ static int ath6kl_upload_board_file(struct ath6kl *ar)
1178 } 1152 }
1179 1153
1180 /* record the fact that Board Data IS initialized */ 1154 /* record the fact that Board Data IS initialized */
1181 param = 1; 1155 ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
1182 ath6kl_bmi_write(ar,
1183 ath6kl_get_hi_item_addr(ar,
1184 HI_ITEM(hi_board_data_initialized)),
1185 (u8 *)&param, 4);
1186 1156
1187 return ret; 1157 return ret;
1188} 1158}
@@ -1209,10 +1179,7 @@ static int ath6kl_upload_otp(struct ath6kl *ar)
1209 } 1179 }
1210 1180
1211 /* read firmware start address */ 1181 /* read firmware start address */
1212 ret = ath6kl_bmi_read(ar, 1182 ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
1213 ath6kl_get_hi_item_addr(ar,
1214 HI_ITEM(hi_app_start)),
1215 (u8 *) &address, sizeof(address));
1216 1183
1217 if (ret) { 1184 if (ret) {
1218 ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1185 ath6kl_err("Failed to read hi_app_start: %d\n", ret);
@@ -1270,7 +1237,7 @@ static int ath6kl_upload_firmware(struct ath6kl *ar)
1270 1237
1271static int ath6kl_upload_patch(struct ath6kl *ar) 1238static int ath6kl_upload_patch(struct ath6kl *ar)
1272{ 1239{
1273 u32 address, param; 1240 u32 address;
1274 int ret; 1241 int ret;
1275 1242
1276 if (ar->fw_patch == NULL) 1243 if (ar->fw_patch == NULL)
@@ -1287,18 +1254,14 @@ static int ath6kl_upload_patch(struct ath6kl *ar)
1287 return ret; 1254 return ret;
1288 } 1255 }
1289 1256
1290 param = address; 1257 ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
1291 ath6kl_bmi_write(ar,
1292 ath6kl_get_hi_item_addr(ar,
1293 HI_ITEM(hi_dset_list_head)),
1294 (unsigned char *) &param, 4);
1295 1258
1296 return 0; 1259 return 0;
1297} 1260}
1298 1261
1299static int ath6kl_upload_testscript(struct ath6kl *ar) 1262static int ath6kl_upload_testscript(struct ath6kl *ar)
1300{ 1263{
1301 u32 address, param; 1264 u32 address;
1302 int ret; 1265 int ret;
1303 1266
1304 if (ar->testmode != 2) 1267 if (ar->testmode != 2)
@@ -1310,7 +1273,7 @@ static int ath6kl_upload_testscript(struct ath6kl *ar)
1310 address = ar->hw.testscript_addr; 1273 address = ar->hw.testscript_addr;
1311 1274
1312 ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", 1275 ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
1313 address, ar->fw_testscript_len); 1276 address, ar->fw_testscript_len);
1314 1277
1315 ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, 1278 ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
1316 ar->fw_testscript_len); 1279 ar->fw_testscript_len);
@@ -1319,23 +1282,9 @@ static int ath6kl_upload_testscript(struct ath6kl *ar)
1319 return ret; 1282 return ret;
1320 } 1283 }
1321 1284
1322 param = address; 1285 ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
1323 ath6kl_bmi_write(ar, 1286 ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
1324 ath6kl_get_hi_item_addr(ar, 1287 ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
1325 HI_ITEM(hi_ota_testscript)),
1326 (unsigned char *) &param, 4);
1327
1328 param = 4096;
1329 ath6kl_bmi_write(ar,
1330 ath6kl_get_hi_item_addr(ar,
1331 HI_ITEM(hi_end_ram_reserve_sz)),
1332 (unsigned char *) &param, 4);
1333
1334 param = 1;
1335 ath6kl_bmi_write(ar,
1336 ath6kl_get_hi_item_addr(ar,
1337 HI_ITEM(hi_test_apps_related)),
1338 (unsigned char *) &param, 4);
1339 1288
1340 return 0; 1289 return 0;
1341} 1290}
@@ -1346,7 +1295,7 @@ static int ath6kl_init_upload(struct ath6kl *ar)
1346 int status = 0; 1295 int status = 0;
1347 1296
1348 if (ar->target_type != TARGET_TYPE_AR6003 && 1297 if (ar->target_type != TARGET_TYPE_AR6003 &&
1349 ar->target_type != TARGET_TYPE_AR6004) 1298 ar->target_type != TARGET_TYPE_AR6004)
1350 return -EINVAL; 1299 return -EINVAL;
1351 1300
1352 /* temporarily disable system sleep */ 1301 /* temporarily disable system sleep */
@@ -1403,7 +1352,8 @@ static int ath6kl_init_upload(struct ath6kl *ar)
1403 return status; 1352 return status;
1404 1353
1405 /* WAR to avoid SDIO CRC err */ 1354 /* WAR to avoid SDIO CRC err */
1406 if (ar->version.target_ver == AR6003_HW_2_0_VERSION) { 1355 if (ar->version.target_ver == AR6003_HW_2_0_VERSION ||
1356 ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
1407 ath6kl_err("temporary war to avoid sdio crc error\n"); 1357 ath6kl_err("temporary war to avoid sdio crc error\n");
1408 1358
1409 param = 0x20; 1359 param = 0x20;
@@ -1726,9 +1676,11 @@ void ath6kl_stop_txrx(struct ath6kl *ar)
1726 * configure NOT to reset the target during a debug session. 1676 * configure NOT to reset the target during a debug session.
1727 */ 1677 */
1728 ath6kl_dbg(ATH6KL_DBG_TRC, 1678 ath6kl_dbg(ATH6KL_DBG_TRC,
1729 "attempting to reset target on instance destroy\n"); 1679 "attempting to reset target on instance destroy\n");
1730 ath6kl_reset_device(ar, ar->target_type, true, true); 1680 ath6kl_reset_device(ar, ar->target_type, true, true);
1731 1681
1732 clear_bit(WLAN_ENABLED, &ar->flag); 1682 clear_bit(WLAN_ENABLED, &ar->flag);
1683
1684 up(&ar->sem);
1733} 1685}
1734EXPORT_SYMBOL(ath6kl_stop_txrx); 1686EXPORT_SYMBOL(ath6kl_stop_txrx);