aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/ath/ath5k/base.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/base.h')
-rw-r--r--drivers/net/wireless/ath/ath5k/base.h196
1 files changed, 0 insertions, 196 deletions
diff --git a/drivers/net/wireless/ath/ath5k/base.h b/drivers/net/wireless/ath/ath5k/base.h
index 0a98777b937..aa8aafca906 100644
--- a/drivers/net/wireless/ath/ath5k/base.h
+++ b/drivers/net/wireless/ath/ath5k/base.h
@@ -45,23 +45,13 @@
45#include <linux/list.h> 45#include <linux/list.h>
46#include <linux/wireless.h> 46#include <linux/wireless.h>
47#include <linux/if_ether.h> 47#include <linux/if_ether.h>
48#include <linux/leds.h>
49#include <linux/rfkill.h> 48#include <linux/rfkill.h>
50#include <linux/workqueue.h> 49#include <linux/workqueue.h>
51 50
52#include "ath5k.h" 51#include "ath5k.h"
53#include "debug.h"
54#include "ani.h"
55
56#include "../regd.h" 52#include "../regd.h"
57#include "../ath.h" 53#include "../ath.h"
58 54
59#define ATH_RXBUF 40 /* number of RX buffers */
60#define ATH_TXBUF 200 /* number of TX buffers */
61#define ATH_BCBUF 4 /* number of beacon buffers */
62#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
63#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
64
65struct ath5k_buf { 55struct ath5k_buf {
66 struct list_head list; 56 struct list_head list;
67 struct ath5k_desc *desc; /* virtual addr of desc */ 57 struct ath5k_desc *desc; /* virtual addr of desc */
@@ -70,94 +60,6 @@ struct ath5k_buf {
70 dma_addr_t skbaddr;/* physical addr of skb data */ 60 dma_addr_t skbaddr;/* physical addr of skb data */
71}; 61};
72 62
73/*
74 * Data transmit queue state. One of these exists for each
75 * hardware transmit queue. Packets sent to us from above
76 * are assigned to queues based on their priority. Not all
77 * devices support a complete set of hardware transmit queues.
78 * For those devices the array sc_ac2q will map multiple
79 * priorities to fewer hardware queues (typically all to one
80 * hardware queue).
81 */
82struct ath5k_txq {
83 unsigned int qnum; /* hardware q number */
84 u32 *link; /* link ptr in last TX desc */
85 struct list_head q; /* transmit queue */
86 spinlock_t lock; /* lock on q and link */
87 bool setup;
88 int txq_len; /* number of queued buffers */
89 int txq_max; /* max allowed num of queued buffers */
90 bool txq_poll_mark;
91 unsigned int txq_stuck; /* informational counter */
92};
93
94#define ATH5K_LED_MAX_NAME_LEN 31
95
96/*
97 * State for LED triggers
98 */
99struct ath5k_led {
100 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
101 struct ath5k_softc *sc; /* driver state */
102 struct led_classdev led_dev; /* led classdev */
103};
104
105/* Rfkill */
106struct ath5k_rfkill {
107 /* GPIO PIN for rfkill */
108 u16 gpio;
109 /* polarity of rfkill GPIO PIN */
110 bool polarity;
111 /* RFKILL toggle tasklet */
112 struct tasklet_struct toggleq;
113};
114
115/* statistics */
116struct ath5k_statistics {
117 /* antenna use */
118 unsigned int antenna_rx[5]; /* frames count per antenna RX */
119 unsigned int antenna_tx[5]; /* frames count per antenna TX */
120
121 /* frame errors */
122 unsigned int rx_all_count; /* all RX frames, including errors */
123 unsigned int tx_all_count; /* all TX frames, including errors */
124 unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
125 * and the MAC headers for each packet
126 */
127 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
128 * and the MAC headers and padding for
129 * each packet.
130 */
131 unsigned int rxerr_crc;
132 unsigned int rxerr_phy;
133 unsigned int rxerr_phy_code[32];
134 unsigned int rxerr_fifo;
135 unsigned int rxerr_decrypt;
136 unsigned int rxerr_mic;
137 unsigned int rxerr_proc;
138 unsigned int rxerr_jumbo;
139 unsigned int txerr_retry;
140 unsigned int txerr_fifo;
141 unsigned int txerr_filt;
142
143 /* MIB counters */
144 unsigned int ack_fail;
145 unsigned int rts_fail;
146 unsigned int rts_ok;
147 unsigned int fcs_error;
148 unsigned int beacons;
149
150 unsigned int mib_intr;
151 unsigned int rxorn_intr;
152 unsigned int rxeol_intr;
153};
154
155#if CHAN_DEBUG
156#define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
157#else
158#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
159#endif
160
161struct ath5k_vif { 63struct ath5k_vif {
162 bool assoc; /* are we associated or not */ 64 bool assoc; /* are we associated or not */
163 enum nl80211_iftype opmode; 65 enum nl80211_iftype opmode;
@@ -166,104 +68,6 @@ struct ath5k_vif {
166 u8 lladdr[ETH_ALEN]; 68 u8 lladdr[ETH_ALEN];
167}; 69};
168 70
169/* Software Carrier, keeps track of the driver state
170 * associated with an instance of a device */
171struct ath5k_softc {
172 struct pci_dev *pdev;
173 struct device *dev; /* for dma mapping */
174 int irq;
175 u16 devid;
176 void __iomem *iobase; /* address of the device */
177 struct mutex lock; /* dev-level lock */
178 struct ieee80211_hw *hw; /* IEEE 802.11 common */
179 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
180 struct ieee80211_channel channels[ATH_CHAN_MAX];
181 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
182 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
183 enum nl80211_iftype opmode;
184 struct ath5k_hw *ah; /* Atheros HW */
185
186#ifdef CONFIG_ATH5K_DEBUG
187 struct ath5k_dbg_info debug; /* debug info */
188#endif /* CONFIG_ATH5K_DEBUG */
189
190 struct ath5k_buf *bufptr; /* allocated buffer ptr */
191 struct ath5k_desc *desc; /* TX/RX descriptors */
192 dma_addr_t desc_daddr; /* DMA (physical) address */
193 size_t desc_len; /* size of TX/RX descriptors */
194
195 DECLARE_BITMAP(status, 6);
196#define ATH_STAT_INVALID 0 /* disable hardware accesses */
197#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
198#define ATH_STAT_PROMISC 2
199#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
200#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
201#define ATH_STAT_2G_DISABLED 5 /* multiband radio without 2G */
202
203 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
204 struct ieee80211_channel *curchan; /* current h/w channel */
205
206 u16 nvifs;
207
208 enum ath5k_int imask; /* interrupt mask copy */
209
210 spinlock_t irqlock;
211 bool rx_pending; /* rx tasklet pending */
212 bool tx_pending; /* tx tasklet pending */
213
214 u8 lladdr[ETH_ALEN];
215 u8 bssidmask[ETH_ALEN];
216
217 unsigned int led_pin, /* GPIO pin for driving LED */
218 led_on; /* pin setting for LED on */
219
220 struct work_struct reset_work; /* deferred chip reset */
221
222 unsigned int rxbufsize; /* rx size based on mtu */
223 struct list_head rxbuf; /* receive buffer */
224 spinlock_t rxbuflock;
225 u32 *rxlink; /* link ptr in last RX desc */
226 struct tasklet_struct rxtq; /* rx intr tasklet */
227 struct ath5k_led rx_led; /* rx led */
228
229 struct list_head txbuf; /* transmit buffer */
230 spinlock_t txbuflock;
231 unsigned int txbuf_len; /* buf count in txbuf list */
232 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
233 struct tasklet_struct txtq; /* tx intr tasklet */
234 struct ath5k_led tx_led; /* tx led */
235
236 struct ath5k_rfkill rf_kill;
237
238 struct tasklet_struct calib; /* calibration tasklet */
239
240 spinlock_t block; /* protects beacon */
241 struct tasklet_struct beacontq; /* beacon intr tasklet */
242 struct list_head bcbuf; /* beacon buffer */
243 struct ieee80211_vif *bslot[ATH_BCBUF];
244 u16 num_ap_vifs;
245 u16 num_adhoc_vifs;
246 unsigned int bhalq, /* SW q for outgoing beacons */
247 bmisscount, /* missed beacon transmits */
248 bintval, /* beacon interval in TU */
249 bsent;
250 unsigned int nexttbtt; /* next beacon time in TU */
251 struct ath5k_txq *cabq; /* content after beacon */
252
253 int power_level; /* Requested tx power in dBm */
254 bool assoc; /* associate state */
255 bool enable_beacon; /* true if beacons are on */
256
257 struct ath5k_statistics stats;
258
259 struct ath5k_ani_state ani_state;
260 struct tasklet_struct ani_tasklet; /* ANI calibration */
261
262 struct delayed_work tx_complete_work;
263
264 struct survey_info survey; /* collected survey info */
265};
266
267struct ath5k_vif_iter_data { 71struct ath5k_vif_iter_data {
268 const u8 *hw_macaddr; 72 const u8 *hw_macaddr;
269 u8 mask[ETH_ALEN]; 73 u8 mask[ETH_ALEN];