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-rw-r--r--drivers/net/tulip/tulip_core.c2011
1 files changed, 2011 insertions, 0 deletions
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
new file mode 100644
index 00000000000..1246998a677
--- /dev/null
+++ b/drivers/net/tulip/tulip_core.c
@@ -0,0 +1,2011 @@
1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
2
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
5
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
8
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
10 for more information on this driver.
11
12 Please submit bugs to http://bugzilla.kernel.org/ .
13*/
14
15#define pr_fmt(fmt) "tulip: " fmt
16
17#define DRV_NAME "tulip"
18#ifdef CONFIG_TULIP_NAPI
19#define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
20#else
21#define DRV_VERSION "1.1.15"
22#endif
23#define DRV_RELDATE "Feb 27, 2007"
24
25
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include "tulip.h"
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/etherdevice.h>
33#include <linux/delay.h>
34#include <linux/mii.h>
35#include <linux/crc32.h>
36#include <asm/unaligned.h>
37#include <asm/uaccess.h>
38
39#ifdef CONFIG_SPARC
40#include <asm/prom.h>
41#endif
42
43static char version[] __devinitdata =
44 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
45
46/* A few user-configurable values. */
47
48/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
49static unsigned int max_interrupt_work = 25;
50
51#define MAX_UNITS 8
52/* Used to pass the full-duplex flag, etc. */
53static int full_duplex[MAX_UNITS];
54static int options[MAX_UNITS];
55static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
56
57/* The possible media types that can be set in options[] are: */
58const char * const medianame[32] = {
59 "10baseT", "10base2", "AUI", "100baseTx",
60 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
61 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
62 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
63 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
64 "","","","", "","","","", "","","","Transceiver reset",
65};
66
67/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
68#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
69 defined(CONFIG_SPARC) || defined(__ia64__) || \
70 defined(__sh__) || defined(__mips__)
71static int rx_copybreak = 1518;
72#else
73static int rx_copybreak = 100;
74#endif
75
76/*
77 Set the bus performance register.
78 Typical: Set 16 longword cache alignment, no burst limit.
79 Cache alignment bits 15:14 Burst length 13:8
80 0000 No alignment 0x00000000 unlimited 0800 8 longwords
81 4000 8 longwords 0100 1 longword 1000 16 longwords
82 8000 16 longwords 0200 2 longwords 2000 32 longwords
83 C000 32 longwords 0400 4 longwords
84 Warning: many older 486 systems are broken and require setting 0x00A04800
85 8 longword cache alignment, 8 longword burst.
86 ToDo: Non-Intel setting could be better.
87*/
88
89#if defined(__alpha__) || defined(__ia64__)
90static int csr0 = 0x01A00000 | 0xE000;
91#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
92static int csr0 = 0x01A00000 | 0x8000;
93#elif defined(CONFIG_SPARC) || defined(__hppa__)
94/* The UltraSparc PCI controllers will disconnect at every 64-byte
95 * crossing anyways so it makes no sense to tell Tulip to burst
96 * any more than that.
97 */
98static int csr0 = 0x01A00000 | 0x9000;
99#elif defined(__arm__) || defined(__sh__)
100static int csr0 = 0x01A00000 | 0x4800;
101#elif defined(__mips__)
102static int csr0 = 0x00200000 | 0x4000;
103#else
104#warning Processor architecture undefined!
105static int csr0 = 0x00A00000 | 0x4800;
106#endif
107
108/* Operational parameters that usually are not changed. */
109/* Time in jiffies before concluding the transmitter is hung. */
110#define TX_TIMEOUT (4*HZ)
111
112
113MODULE_AUTHOR("The Linux Kernel Team");
114MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
115MODULE_LICENSE("GPL");
116MODULE_VERSION(DRV_VERSION);
117module_param(tulip_debug, int, 0);
118module_param(max_interrupt_work, int, 0);
119module_param(rx_copybreak, int, 0);
120module_param(csr0, int, 0);
121module_param_array(options, int, NULL, 0);
122module_param_array(full_duplex, int, NULL, 0);
123
124#ifdef TULIP_DEBUG
125int tulip_debug = TULIP_DEBUG;
126#else
127int tulip_debug = 1;
128#endif
129
130static void tulip_timer(unsigned long data)
131{
132 struct net_device *dev = (struct net_device *)data;
133 struct tulip_private *tp = netdev_priv(dev);
134
135 if (netif_running(dev))
136 schedule_work(&tp->media_work);
137}
138
139/*
140 * This table use during operation for capabilities and media timer.
141 *
142 * It is indexed via the values in 'enum chips'
143 */
144
145struct tulip_chip_table tulip_tbl[] = {
146 { }, /* placeholder for array, slot unused currently */
147 { }, /* placeholder for array, slot unused currently */
148
149 /* DC21140 */
150 { "Digital DS21140 Tulip", 128, 0x0001ebef,
151 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
152 tulip_media_task },
153
154 /* DC21142, DC21143 */
155 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
156 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
157 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
158
159 /* LC82C168 */
160 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
161 HAS_MII | HAS_PNICNWAY, pnic_timer, },
162
163 /* MX98713 */
164 { "Macronix 98713 PMAC", 128, 0x0001ebef,
165 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
166
167 /* MX98715 */
168 { "Macronix 98715 PMAC", 256, 0x0001ebef,
169 HAS_MEDIA_TABLE, mxic_timer, },
170
171 /* MX98725 */
172 { "Macronix 98725 PMAC", 256, 0x0001ebef,
173 HAS_MEDIA_TABLE, mxic_timer, },
174
175 /* AX88140 */
176 { "ASIX AX88140", 128, 0x0001fbff,
177 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
178 | IS_ASIX, tulip_timer, tulip_media_task },
179
180 /* PNIC2 */
181 { "Lite-On PNIC-II", 256, 0x0801fbff,
182 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
183
184 /* COMET */
185 { "ADMtek Comet", 256, 0x0001abef,
186 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
187
188 /* COMPEX9881 */
189 { "Compex 9881 PMAC", 128, 0x0001ebef,
190 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
191
192 /* I21145 */
193 { "Intel DS21145 Tulip", 128, 0x0801fbff,
194 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
195 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
196
197 /* DM910X */
198#ifdef CONFIG_TULIP_DM910X
199 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
200 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
201 tulip_timer, tulip_media_task },
202#else
203 { NULL },
204#endif
205
206 /* RS7112 */
207 { "Conexant LANfinity", 256, 0x0001ebef,
208 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
209
210};
211
212
213static DEFINE_PCI_DEVICE_TABLE(tulip_pci_tbl) = {
214 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
215 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
216 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
217 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
218 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
219/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
220 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
221 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
222 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
233 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
234#ifdef CONFIG_TULIP_DM910X
235 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
236 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
237#endif
238 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
240 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
245 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
246 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
247 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
248 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
250 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
251 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
252 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
253 { } /* terminate list */
254};
255MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
256
257
258/* A full-duplex map for media types. */
259const char tulip_media_cap[32] =
260{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
261
262static void tulip_tx_timeout(struct net_device *dev);
263static void tulip_init_ring(struct net_device *dev);
264static void tulip_free_ring(struct net_device *dev);
265static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
266 struct net_device *dev);
267static int tulip_open(struct net_device *dev);
268static int tulip_close(struct net_device *dev);
269static void tulip_up(struct net_device *dev);
270static void tulip_down(struct net_device *dev);
271static struct net_device_stats *tulip_get_stats(struct net_device *dev);
272static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
273static void set_rx_mode(struct net_device *dev);
274static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts);
275#ifdef CONFIG_NET_POLL_CONTROLLER
276static void poll_tulip(struct net_device *dev);
277#endif
278
279static void tulip_set_power_state (struct tulip_private *tp,
280 int sleep, int snooze)
281{
282 if (tp->flags & HAS_ACPI) {
283 u32 tmp, newtmp;
284 pci_read_config_dword (tp->pdev, CFDD, &tmp);
285 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
286 if (sleep)
287 newtmp |= CFDD_Sleep;
288 else if (snooze)
289 newtmp |= CFDD_Snooze;
290 if (tmp != newtmp)
291 pci_write_config_dword (tp->pdev, CFDD, newtmp);
292 }
293
294}
295
296
297static void tulip_up(struct net_device *dev)
298{
299 struct tulip_private *tp = netdev_priv(dev);
300 void __iomem *ioaddr = tp->base_addr;
301 int next_tick = 3*HZ;
302 u32 reg;
303 int i;
304
305#ifdef CONFIG_TULIP_NAPI
306 napi_enable(&tp->napi);
307#endif
308
309 /* Wake the chip from sleep/snooze mode. */
310 tulip_set_power_state (tp, 0, 0);
311
312 /* Disable all WOL events */
313 pci_enable_wake(tp->pdev, PCI_D3hot, 0);
314 pci_enable_wake(tp->pdev, PCI_D3cold, 0);
315 tulip_set_wolopts(tp->pdev, 0);
316
317 /* On some chip revs we must set the MII/SYM port before the reset!? */
318 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
319 iowrite32(0x00040000, ioaddr + CSR6);
320
321 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
322 iowrite32(0x00000001, ioaddr + CSR0);
323 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
324 udelay(100);
325
326 /* Deassert reset.
327 Wait the specified 50 PCI cycles after a reset by initializing
328 Tx and Rx queues and the address filter list. */
329 iowrite32(tp->csr0, ioaddr + CSR0);
330 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
331 udelay(100);
332
333 if (tulip_debug > 1)
334 netdev_dbg(dev, "tulip_up(), irq==%d\n", dev->irq);
335
336 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
337 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
338 tp->cur_rx = tp->cur_tx = 0;
339 tp->dirty_rx = tp->dirty_tx = 0;
340
341 if (tp->flags & MC_HASH_ONLY) {
342 u32 addr_low = get_unaligned_le32(dev->dev_addr);
343 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
344 if (tp->chip_id == AX88140) {
345 iowrite32(0, ioaddr + CSR13);
346 iowrite32(addr_low, ioaddr + CSR14);
347 iowrite32(1, ioaddr + CSR13);
348 iowrite32(addr_high, ioaddr + CSR14);
349 } else if (tp->flags & COMET_MAC_ADDR) {
350 iowrite32(addr_low, ioaddr + 0xA4);
351 iowrite32(addr_high, ioaddr + 0xA8);
352 iowrite32(0, ioaddr + CSR27);
353 iowrite32(0, ioaddr + CSR28);
354 }
355 } else {
356 /* This is set_rx_mode(), but without starting the transmitter. */
357 u16 *eaddrs = (u16 *)dev->dev_addr;
358 u16 *setup_frm = &tp->setup_frame[15*6];
359 dma_addr_t mapping;
360
361 /* 21140 bug: you must add the broadcast address. */
362 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
363 /* Fill the final entry of the table with our physical address. */
364 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
365 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
366 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
367
368 mapping = pci_map_single(tp->pdev, tp->setup_frame,
369 sizeof(tp->setup_frame),
370 PCI_DMA_TODEVICE);
371 tp->tx_buffers[tp->cur_tx].skb = NULL;
372 tp->tx_buffers[tp->cur_tx].mapping = mapping;
373
374 /* Put the setup frame on the Tx list. */
375 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
376 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
377 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
378
379 tp->cur_tx++;
380 }
381
382 tp->saved_if_port = dev->if_port;
383 if (dev->if_port == 0)
384 dev->if_port = tp->default_port;
385
386 /* Allow selecting a default media. */
387 i = 0;
388 if (tp->mtable == NULL)
389 goto media_picked;
390 if (dev->if_port) {
391 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
392 (dev->if_port == 12 ? 0 : dev->if_port);
393 for (i = 0; i < tp->mtable->leafcount; i++)
394 if (tp->mtable->mleaf[i].media == looking_for) {
395 dev_info(&dev->dev,
396 "Using user-specified media %s\n",
397 medianame[dev->if_port]);
398 goto media_picked;
399 }
400 }
401 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
402 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
403 for (i = 0; i < tp->mtable->leafcount; i++)
404 if (tp->mtable->mleaf[i].media == looking_for) {
405 dev_info(&dev->dev,
406 "Using EEPROM-set media %s\n",
407 medianame[looking_for]);
408 goto media_picked;
409 }
410 }
411 /* Start sensing first non-full-duplex media. */
412 for (i = tp->mtable->leafcount - 1;
413 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
414 ;
415media_picked:
416
417 tp->csr6 = 0;
418 tp->cur_index = i;
419 tp->nwayset = 0;
420
421 if (dev->if_port) {
422 if (tp->chip_id == DC21143 &&
423 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
424 /* We must reset the media CSRs when we force-select MII mode. */
425 iowrite32(0x0000, ioaddr + CSR13);
426 iowrite32(0x0000, ioaddr + CSR14);
427 iowrite32(0x0008, ioaddr + CSR15);
428 }
429 tulip_select_media(dev, 1);
430 } else if (tp->chip_id == DC21142) {
431 if (tp->mii_cnt) {
432 tulip_select_media(dev, 1);
433 if (tulip_debug > 1)
434 dev_info(&dev->dev,
435 "Using MII transceiver %d, status %04x\n",
436 tp->phys[0],
437 tulip_mdio_read(dev, tp->phys[0], 1));
438 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
439 tp->csr6 = csr6_mask_hdcap;
440 dev->if_port = 11;
441 iowrite32(0x0000, ioaddr + CSR13);
442 iowrite32(0x0000, ioaddr + CSR14);
443 } else
444 t21142_start_nway(dev);
445 } else if (tp->chip_id == PNIC2) {
446 /* for initial startup advertise 10/100 Full and Half */
447 tp->sym_advertise = 0x01E0;
448 /* enable autonegotiate end interrupt */
449 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
450 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
451 pnic2_start_nway(dev);
452 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
453 if (tp->mii_cnt) {
454 dev->if_port = 11;
455 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
456 iowrite32(0x0001, ioaddr + CSR15);
457 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
458 pnic_do_nway(dev);
459 else {
460 /* Start with 10mbps to do autonegotiation. */
461 iowrite32(0x32, ioaddr + CSR12);
462 tp->csr6 = 0x00420000;
463 iowrite32(0x0001B078, ioaddr + 0xB8);
464 iowrite32(0x0201B078, ioaddr + 0xB8);
465 next_tick = 1*HZ;
466 }
467 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
468 ! tp->medialock) {
469 dev->if_port = 0;
470 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
471 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
472 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
473 /* Provided by BOLO, Macronix - 12/10/1998. */
474 dev->if_port = 0;
475 tp->csr6 = 0x01a80200;
476 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
477 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
478 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
479 /* Enable automatic Tx underrun recovery. */
480 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
481 dev->if_port = tp->mii_cnt ? 11 : 0;
482 tp->csr6 = 0x00040000;
483 } else if (tp->chip_id == AX88140) {
484 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
485 } else
486 tulip_select_media(dev, 1);
487
488 /* Start the chip's Tx to process setup frame. */
489 tulip_stop_rxtx(tp);
490 barrier();
491 udelay(5);
492 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
493
494 /* Enable interrupts by setting the interrupt mask. */
495 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
496 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
497 tulip_start_rxtx(tp);
498 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
499
500 if (tulip_debug > 2) {
501 netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
502 ioread32(ioaddr + CSR0),
503 ioread32(ioaddr + CSR5),
504 ioread32(ioaddr + CSR6));
505 }
506
507 /* Set the timer to switch to check for link beat and perhaps switch
508 to an alternate media type. */
509 tp->timer.expires = RUN_AT(next_tick);
510 add_timer(&tp->timer);
511#ifdef CONFIG_TULIP_NAPI
512 init_timer(&tp->oom_timer);
513 tp->oom_timer.data = (unsigned long)dev;
514 tp->oom_timer.function = oom_timer;
515#endif
516}
517
518static int
519tulip_open(struct net_device *dev)
520{
521 int retval;
522
523 tulip_init_ring (dev);
524
525 retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev);
526 if (retval)
527 goto free_ring;
528
529 tulip_up (dev);
530
531 netif_start_queue (dev);
532
533 return 0;
534
535free_ring:
536 tulip_free_ring (dev);
537 return retval;
538}
539
540
541static void tulip_tx_timeout(struct net_device *dev)
542{
543 struct tulip_private *tp = netdev_priv(dev);
544 void __iomem *ioaddr = tp->base_addr;
545 unsigned long flags;
546
547 spin_lock_irqsave (&tp->lock, flags);
548
549 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
550 /* Do nothing -- the media monitor should handle this. */
551 if (tulip_debug > 1)
552 dev_warn(&dev->dev,
553 "Transmit timeout using MII device\n");
554 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
555 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
556 tp->chip_id == DM910X) {
557 dev_warn(&dev->dev,
558 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
559 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
560 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
561 ioread32(ioaddr + CSR15));
562 tp->timeout_recovery = 1;
563 schedule_work(&tp->media_work);
564 goto out_unlock;
565 } else if (tp->chip_id == PNIC2) {
566 dev_warn(&dev->dev,
567 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
568 (int)ioread32(ioaddr + CSR5),
569 (int)ioread32(ioaddr + CSR6),
570 (int)ioread32(ioaddr + CSR7),
571 (int)ioread32(ioaddr + CSR12));
572 } else {
573 dev_warn(&dev->dev,
574 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
575 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
576 dev->if_port = 0;
577 }
578
579#if defined(way_too_many_messages)
580 if (tulip_debug > 3) {
581 int i;
582 for (i = 0; i < RX_RING_SIZE; i++) {
583 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
584 int j;
585 printk(KERN_DEBUG
586 "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
587 i,
588 (unsigned int)tp->rx_ring[i].status,
589 (unsigned int)tp->rx_ring[i].length,
590 (unsigned int)tp->rx_ring[i].buffer1,
591 (unsigned int)tp->rx_ring[i].buffer2,
592 buf[0], buf[1], buf[2]);
593 for (j = 0; buf[j] != 0xee && j < 1600; j++)
594 if (j < 100)
595 pr_cont(" %02x", buf[j]);
596 pr_cont(" j=%d\n", j);
597 }
598 printk(KERN_DEBUG " Rx ring %p: ", tp->rx_ring);
599 for (i = 0; i < RX_RING_SIZE; i++)
600 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
601 printk(KERN_DEBUG " Tx ring %p: ", tp->tx_ring);
602 for (i = 0; i < TX_RING_SIZE; i++)
603 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
604 pr_cont("\n");
605 }
606#endif
607
608 tulip_tx_timeout_complete(tp, ioaddr);
609
610out_unlock:
611 spin_unlock_irqrestore (&tp->lock, flags);
612 dev->trans_start = jiffies; /* prevent tx timeout */
613 netif_wake_queue (dev);
614}
615
616
617/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
618static void tulip_init_ring(struct net_device *dev)
619{
620 struct tulip_private *tp = netdev_priv(dev);
621 int i;
622
623 tp->susp_rx = 0;
624 tp->ttimer = 0;
625 tp->nir = 0;
626
627 for (i = 0; i < RX_RING_SIZE; i++) {
628 tp->rx_ring[i].status = 0x00000000;
629 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
630 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
631 tp->rx_buffers[i].skb = NULL;
632 tp->rx_buffers[i].mapping = 0;
633 }
634 /* Mark the last entry as wrapping the ring. */
635 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
636 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
637
638 for (i = 0; i < RX_RING_SIZE; i++) {
639 dma_addr_t mapping;
640
641 /* Note the receive buffer must be longword aligned.
642 dev_alloc_skb() provides 16 byte alignment. But do *not*
643 use skb_reserve() to align the IP header! */
644 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
645 tp->rx_buffers[i].skb = skb;
646 if (skb == NULL)
647 break;
648 mapping = pci_map_single(tp->pdev, skb->data,
649 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
650 tp->rx_buffers[i].mapping = mapping;
651 skb->dev = dev; /* Mark as being used by this device. */
652 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
653 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
654 }
655 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
656
657 /* The Tx buffer descriptor is filled in as needed, but we
658 do need to clear the ownership bit. */
659 for (i = 0; i < TX_RING_SIZE; i++) {
660 tp->tx_buffers[i].skb = NULL;
661 tp->tx_buffers[i].mapping = 0;
662 tp->tx_ring[i].status = 0x00000000;
663 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
664 }
665 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
666}
667
668static netdev_tx_t
669tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
670{
671 struct tulip_private *tp = netdev_priv(dev);
672 int entry;
673 u32 flag;
674 dma_addr_t mapping;
675 unsigned long flags;
676
677 spin_lock_irqsave(&tp->lock, flags);
678
679 /* Calculate the next Tx descriptor entry. */
680 entry = tp->cur_tx % TX_RING_SIZE;
681
682 tp->tx_buffers[entry].skb = skb;
683 mapping = pci_map_single(tp->pdev, skb->data,
684 skb->len, PCI_DMA_TODEVICE);
685 tp->tx_buffers[entry].mapping = mapping;
686 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
687
688 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
689 flag = 0x60000000; /* No interrupt */
690 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
691 flag = 0xe0000000; /* Tx-done intr. */
692 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
693 flag = 0x60000000; /* No Tx-done intr. */
694 } else { /* Leave room for set_rx_mode() to fill entries. */
695 flag = 0xe0000000; /* Tx-done intr. */
696 netif_stop_queue(dev);
697 }
698 if (entry == TX_RING_SIZE-1)
699 flag = 0xe0000000 | DESC_RING_WRAP;
700
701 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
702 /* if we were using Transmit Automatic Polling, we would need a
703 * wmb() here. */
704 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
705 wmb();
706
707 tp->cur_tx++;
708
709 /* Trigger an immediate transmit demand. */
710 iowrite32(0, tp->base_addr + CSR1);
711
712 spin_unlock_irqrestore(&tp->lock, flags);
713
714 return NETDEV_TX_OK;
715}
716
717static void tulip_clean_tx_ring(struct tulip_private *tp)
718{
719 unsigned int dirty_tx;
720
721 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
722 dirty_tx++) {
723 int entry = dirty_tx % TX_RING_SIZE;
724 int status = le32_to_cpu(tp->tx_ring[entry].status);
725
726 if (status < 0) {
727 tp->dev->stats.tx_errors++; /* It wasn't Txed */
728 tp->tx_ring[entry].status = 0;
729 }
730
731 /* Check for Tx filter setup frames. */
732 if (tp->tx_buffers[entry].skb == NULL) {
733 /* test because dummy frames not mapped */
734 if (tp->tx_buffers[entry].mapping)
735 pci_unmap_single(tp->pdev,
736 tp->tx_buffers[entry].mapping,
737 sizeof(tp->setup_frame),
738 PCI_DMA_TODEVICE);
739 continue;
740 }
741
742 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
743 tp->tx_buffers[entry].skb->len,
744 PCI_DMA_TODEVICE);
745
746 /* Free the original skb. */
747 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
748 tp->tx_buffers[entry].skb = NULL;
749 tp->tx_buffers[entry].mapping = 0;
750 }
751}
752
753static void tulip_down (struct net_device *dev)
754{
755 struct tulip_private *tp = netdev_priv(dev);
756 void __iomem *ioaddr = tp->base_addr;
757 unsigned long flags;
758
759 cancel_work_sync(&tp->media_work);
760
761#ifdef CONFIG_TULIP_NAPI
762 napi_disable(&tp->napi);
763#endif
764
765 del_timer_sync (&tp->timer);
766#ifdef CONFIG_TULIP_NAPI
767 del_timer_sync (&tp->oom_timer);
768#endif
769 spin_lock_irqsave (&tp->lock, flags);
770
771 /* Disable interrupts by clearing the interrupt mask. */
772 iowrite32 (0x00000000, ioaddr + CSR7);
773
774 /* Stop the Tx and Rx processes. */
775 tulip_stop_rxtx(tp);
776
777 /* prepare receive buffers */
778 tulip_refill_rx(dev);
779
780 /* release any unconsumed transmit buffers */
781 tulip_clean_tx_ring(tp);
782
783 if (ioread32(ioaddr + CSR6) != 0xffffffff)
784 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
785
786 spin_unlock_irqrestore (&tp->lock, flags);
787
788 init_timer(&tp->timer);
789 tp->timer.data = (unsigned long)dev;
790 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
791
792 dev->if_port = tp->saved_if_port;
793
794 /* Leave the driver in snooze, not sleep, mode. */
795 tulip_set_power_state (tp, 0, 1);
796}
797
798static void tulip_free_ring (struct net_device *dev)
799{
800 struct tulip_private *tp = netdev_priv(dev);
801 int i;
802
803 /* Free all the skbuffs in the Rx queue. */
804 for (i = 0; i < RX_RING_SIZE; i++) {
805 struct sk_buff *skb = tp->rx_buffers[i].skb;
806 dma_addr_t mapping = tp->rx_buffers[i].mapping;
807
808 tp->rx_buffers[i].skb = NULL;
809 tp->rx_buffers[i].mapping = 0;
810
811 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
812 tp->rx_ring[i].length = 0;
813 /* An invalid address. */
814 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
815 if (skb) {
816 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
817 PCI_DMA_FROMDEVICE);
818 dev_kfree_skb (skb);
819 }
820 }
821
822 for (i = 0; i < TX_RING_SIZE; i++) {
823 struct sk_buff *skb = tp->tx_buffers[i].skb;
824
825 if (skb != NULL) {
826 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
827 skb->len, PCI_DMA_TODEVICE);
828 dev_kfree_skb (skb);
829 }
830 tp->tx_buffers[i].skb = NULL;
831 tp->tx_buffers[i].mapping = 0;
832 }
833}
834
835static int tulip_close (struct net_device *dev)
836{
837 struct tulip_private *tp = netdev_priv(dev);
838 void __iomem *ioaddr = tp->base_addr;
839
840 netif_stop_queue (dev);
841
842 tulip_down (dev);
843
844 if (tulip_debug > 1)
845 netdev_dbg(dev, "Shutting down ethercard, status was %02x\n",
846 ioread32 (ioaddr + CSR5));
847
848 free_irq (dev->irq, dev);
849
850 tulip_free_ring (dev);
851
852 return 0;
853}
854
855static struct net_device_stats *tulip_get_stats(struct net_device *dev)
856{
857 struct tulip_private *tp = netdev_priv(dev);
858 void __iomem *ioaddr = tp->base_addr;
859
860 if (netif_running(dev)) {
861 unsigned long flags;
862
863 spin_lock_irqsave (&tp->lock, flags);
864
865 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
866
867 spin_unlock_irqrestore(&tp->lock, flags);
868 }
869
870 return &dev->stats;
871}
872
873
874static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
875{
876 struct tulip_private *np = netdev_priv(dev);
877 strcpy(info->driver, DRV_NAME);
878 strcpy(info->version, DRV_VERSION);
879 strcpy(info->bus_info, pci_name(np->pdev));
880}
881
882
883static int tulip_ethtool_set_wol(struct net_device *dev,
884 struct ethtool_wolinfo *wolinfo)
885{
886 struct tulip_private *tp = netdev_priv(dev);
887
888 if (wolinfo->wolopts & (~tp->wolinfo.supported))
889 return -EOPNOTSUPP;
890
891 tp->wolinfo.wolopts = wolinfo->wolopts;
892 device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
893 return 0;
894}
895
896static void tulip_ethtool_get_wol(struct net_device *dev,
897 struct ethtool_wolinfo *wolinfo)
898{
899 struct tulip_private *tp = netdev_priv(dev);
900
901 wolinfo->supported = tp->wolinfo.supported;
902 wolinfo->wolopts = tp->wolinfo.wolopts;
903 return;
904}
905
906
907static const struct ethtool_ops ops = {
908 .get_drvinfo = tulip_get_drvinfo,
909 .set_wol = tulip_ethtool_set_wol,
910 .get_wol = tulip_ethtool_get_wol,
911};
912
913/* Provide ioctl() calls to examine the MII xcvr state. */
914static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
915{
916 struct tulip_private *tp = netdev_priv(dev);
917 void __iomem *ioaddr = tp->base_addr;
918 struct mii_ioctl_data *data = if_mii(rq);
919 const unsigned int phy_idx = 0;
920 int phy = tp->phys[phy_idx] & 0x1f;
921 unsigned int regnum = data->reg_num;
922
923 switch (cmd) {
924 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
925 if (tp->mii_cnt)
926 data->phy_id = phy;
927 else if (tp->flags & HAS_NWAY)
928 data->phy_id = 32;
929 else if (tp->chip_id == COMET)
930 data->phy_id = 1;
931 else
932 return -ENODEV;
933
934 case SIOCGMIIREG: /* Read MII PHY register. */
935 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
936 int csr12 = ioread32 (ioaddr + CSR12);
937 int csr14 = ioread32 (ioaddr + CSR14);
938 switch (regnum) {
939 case 0:
940 if (((csr14<<5) & 0x1000) ||
941 (dev->if_port == 5 && tp->nwayset))
942 data->val_out = 0x1000;
943 else
944 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
945 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
946 break;
947 case 1:
948 data->val_out =
949 0x1848 +
950 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
951 ((csr12&0x06) == 6 ? 0 : 4);
952 data->val_out |= 0x6048;
953 break;
954 case 4:
955 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
956 data->val_out =
957 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
958 ((csr14 >> 1) & 0x20) + 1;
959 data->val_out |= ((csr14 >> 9) & 0x03C0);
960 break;
961 case 5: data->val_out = tp->lpar; break;
962 default: data->val_out = 0; break;
963 }
964 } else {
965 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
966 }
967 return 0;
968
969 case SIOCSMIIREG: /* Write MII PHY register. */
970 if (regnum & ~0x1f)
971 return -EINVAL;
972 if (data->phy_id == phy) {
973 u16 value = data->val_in;
974 switch (regnum) {
975 case 0: /* Check for autonegotiation on or reset. */
976 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
977 if (tp->full_duplex_lock)
978 tp->full_duplex = (value & 0x0100) ? 1 : 0;
979 break;
980 case 4:
981 tp->advertising[phy_idx] =
982 tp->mii_advertise = data->val_in;
983 break;
984 }
985 }
986 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
987 u16 value = data->val_in;
988 if (regnum == 0) {
989 if ((value & 0x1200) == 0x1200) {
990 if (tp->chip_id == PNIC2) {
991 pnic2_start_nway (dev);
992 } else {
993 t21142_start_nway (dev);
994 }
995 }
996 } else if (regnum == 4)
997 tp->sym_advertise = value;
998 } else {
999 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
1000 }
1001 return 0;
1002 default:
1003 return -EOPNOTSUPP;
1004 }
1005
1006 return -EOPNOTSUPP;
1007}
1008
1009
1010/* Set or clear the multicast filter for this adaptor.
1011 Note that we only use exclusion around actually queueing the
1012 new frame, not around filling tp->setup_frame. This is non-deterministic
1013 when re-entered but still correct. */
1014
1015#undef set_bit_le
1016#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
1017
1018static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
1019{
1020 struct tulip_private *tp = netdev_priv(dev);
1021 u16 hash_table[32];
1022 struct netdev_hw_addr *ha;
1023 int i;
1024 u16 *eaddrs;
1025
1026 memset(hash_table, 0, sizeof(hash_table));
1027 set_bit_le(255, hash_table); /* Broadcast entry */
1028 /* This should work on big-endian machines as well. */
1029 netdev_for_each_mc_addr(ha, dev) {
1030 int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff;
1031
1032 set_bit_le(index, hash_table);
1033 }
1034 for (i = 0; i < 32; i++) {
1035 *setup_frm++ = hash_table[i];
1036 *setup_frm++ = hash_table[i];
1037 }
1038 setup_frm = &tp->setup_frame[13*6];
1039
1040 /* Fill the final entry with our physical address. */
1041 eaddrs = (u16 *)dev->dev_addr;
1042 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1043 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1044 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1045}
1046
1047static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1048{
1049 struct tulip_private *tp = netdev_priv(dev);
1050 struct netdev_hw_addr *ha;
1051 u16 *eaddrs;
1052
1053 /* We have <= 14 addresses so we can use the wonderful
1054 16 address perfect filtering of the Tulip. */
1055 netdev_for_each_mc_addr(ha, dev) {
1056 eaddrs = (u16 *) ha->addr;
1057 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1058 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1059 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1060 }
1061 /* Fill the unused entries with the broadcast address. */
1062 memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
1063 setup_frm = &tp->setup_frame[15*6];
1064
1065 /* Fill the final entry with our physical address. */
1066 eaddrs = (u16 *)dev->dev_addr;
1067 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1068 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1069 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1070}
1071
1072
1073static void set_rx_mode(struct net_device *dev)
1074{
1075 struct tulip_private *tp = netdev_priv(dev);
1076 void __iomem *ioaddr = tp->base_addr;
1077 int csr6;
1078
1079 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1080
1081 tp->csr6 &= ~0x00D5;
1082 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1083 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1084 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1085 } else if ((netdev_mc_count(dev) > 1000) ||
1086 (dev->flags & IFF_ALLMULTI)) {
1087 /* Too many to filter well -- accept all multicasts. */
1088 tp->csr6 |= AcceptAllMulticast;
1089 csr6 |= AcceptAllMulticast;
1090 } else if (tp->flags & MC_HASH_ONLY) {
1091 /* Some work-alikes have only a 64-entry hash filter table. */
1092 /* Should verify correctness on big-endian/__powerpc__ */
1093 struct netdev_hw_addr *ha;
1094 if (netdev_mc_count(dev) > 64) {
1095 /* Arbitrary non-effective limit. */
1096 tp->csr6 |= AcceptAllMulticast;
1097 csr6 |= AcceptAllMulticast;
1098 } else {
1099 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1100 int filterbit;
1101 netdev_for_each_mc_addr(ha, dev) {
1102 if (tp->flags & COMET_MAC_ADDR)
1103 filterbit = ether_crc_le(ETH_ALEN,
1104 ha->addr);
1105 else
1106 filterbit = ether_crc(ETH_ALEN,
1107 ha->addr) >> 26;
1108 filterbit &= 0x3f;
1109 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1110 if (tulip_debug > 2)
1111 dev_info(&dev->dev,
1112 "Added filter for %pM %08x bit %d\n",
1113 ha->addr,
1114 ether_crc(ETH_ALEN, ha->addr),
1115 filterbit);
1116 }
1117 if (mc_filter[0] == tp->mc_filter[0] &&
1118 mc_filter[1] == tp->mc_filter[1])
1119 ; /* No change. */
1120 else if (tp->flags & IS_ASIX) {
1121 iowrite32(2, ioaddr + CSR13);
1122 iowrite32(mc_filter[0], ioaddr + CSR14);
1123 iowrite32(3, ioaddr + CSR13);
1124 iowrite32(mc_filter[1], ioaddr + CSR14);
1125 } else if (tp->flags & COMET_MAC_ADDR) {
1126 iowrite32(mc_filter[0], ioaddr + CSR27);
1127 iowrite32(mc_filter[1], ioaddr + CSR28);
1128 }
1129 tp->mc_filter[0] = mc_filter[0];
1130 tp->mc_filter[1] = mc_filter[1];
1131 }
1132 } else {
1133 unsigned long flags;
1134 u32 tx_flags = 0x08000000 | 192;
1135
1136 /* Note that only the low-address shortword of setup_frame is valid!
1137 The values are doubled for big-endian architectures. */
1138 if (netdev_mc_count(dev) > 14) {
1139 /* Must use a multicast hash table. */
1140 build_setup_frame_hash(tp->setup_frame, dev);
1141 tx_flags = 0x08400000 | 192;
1142 } else {
1143 build_setup_frame_perfect(tp->setup_frame, dev);
1144 }
1145
1146 spin_lock_irqsave(&tp->lock, flags);
1147
1148 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1149 /* Same setup recently queued, we need not add it. */
1150 } else {
1151 unsigned int entry;
1152 int dummy = -1;
1153
1154 /* Now add this frame to the Tx list. */
1155
1156 entry = tp->cur_tx++ % TX_RING_SIZE;
1157
1158 if (entry != 0) {
1159 /* Avoid a chip errata by prefixing a dummy entry. */
1160 tp->tx_buffers[entry].skb = NULL;
1161 tp->tx_buffers[entry].mapping = 0;
1162 tp->tx_ring[entry].length =
1163 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1164 tp->tx_ring[entry].buffer1 = 0;
1165 /* Must set DescOwned later to avoid race with chip */
1166 dummy = entry;
1167 entry = tp->cur_tx++ % TX_RING_SIZE;
1168
1169 }
1170
1171 tp->tx_buffers[entry].skb = NULL;
1172 tp->tx_buffers[entry].mapping =
1173 pci_map_single(tp->pdev, tp->setup_frame,
1174 sizeof(tp->setup_frame),
1175 PCI_DMA_TODEVICE);
1176 /* Put the setup frame on the Tx list. */
1177 if (entry == TX_RING_SIZE-1)
1178 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1179 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1180 tp->tx_ring[entry].buffer1 =
1181 cpu_to_le32(tp->tx_buffers[entry].mapping);
1182 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1183 if (dummy >= 0)
1184 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1185 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1186 netif_stop_queue(dev);
1187
1188 /* Trigger an immediate transmit demand. */
1189 iowrite32(0, ioaddr + CSR1);
1190 }
1191
1192 spin_unlock_irqrestore(&tp->lock, flags);
1193 }
1194
1195 iowrite32(csr6, ioaddr + CSR6);
1196}
1197
1198#ifdef CONFIG_TULIP_MWI
1199static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1200 struct net_device *dev)
1201{
1202 struct tulip_private *tp = netdev_priv(dev);
1203 u8 cache;
1204 u16 pci_command;
1205 u32 csr0;
1206
1207 if (tulip_debug > 3)
1208 netdev_dbg(dev, "tulip_mwi_config()\n");
1209
1210 tp->csr0 = csr0 = 0;
1211
1212 /* if we have any cache line size at all, we can do MRM and MWI */
1213 csr0 |= MRM | MWI;
1214
1215 /* Enable MWI in the standard PCI command bit.
1216 * Check for the case where MWI is desired but not available
1217 */
1218 pci_try_set_mwi(pdev);
1219
1220 /* read result from hardware (in case bit refused to enable) */
1221 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1222 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1223 csr0 &= ~MWI;
1224
1225 /* if cache line size hardwired to zero, no MWI */
1226 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1227 if ((csr0 & MWI) && (cache == 0)) {
1228 csr0 &= ~MWI;
1229 pci_clear_mwi(pdev);
1230 }
1231
1232 /* assign per-cacheline-size cache alignment and
1233 * burst length values
1234 */
1235 switch (cache) {
1236 case 8:
1237 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1238 break;
1239 case 16:
1240 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1241 break;
1242 case 32:
1243 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1244 break;
1245 default:
1246 cache = 0;
1247 break;
1248 }
1249
1250 /* if we have a good cache line size, we by now have a good
1251 * csr0, so save it and exit
1252 */
1253 if (cache)
1254 goto out;
1255
1256 /* we don't have a good csr0 or cache line size, disable MWI */
1257 if (csr0 & MWI) {
1258 pci_clear_mwi(pdev);
1259 csr0 &= ~MWI;
1260 }
1261
1262 /* sane defaults for burst length and cache alignment
1263 * originally from de4x5 driver
1264 */
1265 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1266
1267out:
1268 tp->csr0 = csr0;
1269 if (tulip_debug > 2)
1270 netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n",
1271 cache, csr0);
1272}
1273#endif
1274
1275/*
1276 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1277 * is the DM910X and the on chip ULi devices
1278 */
1279
1280static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1281{
1282 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1283 return 1;
1284 return 0;
1285}
1286
1287static const struct net_device_ops tulip_netdev_ops = {
1288 .ndo_open = tulip_open,
1289 .ndo_start_xmit = tulip_start_xmit,
1290 .ndo_tx_timeout = tulip_tx_timeout,
1291 .ndo_stop = tulip_close,
1292 .ndo_get_stats = tulip_get_stats,
1293 .ndo_do_ioctl = private_ioctl,
1294 .ndo_set_multicast_list = set_rx_mode,
1295 .ndo_change_mtu = eth_change_mtu,
1296 .ndo_set_mac_address = eth_mac_addr,
1297 .ndo_validate_addr = eth_validate_addr,
1298#ifdef CONFIG_NET_POLL_CONTROLLER
1299 .ndo_poll_controller = poll_tulip,
1300#endif
1301};
1302
1303DEFINE_PCI_DEVICE_TABLE(early_486_chipsets) = {
1304 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1305 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1306 { },
1307};
1308
1309static int __devinit tulip_init_one (struct pci_dev *pdev,
1310 const struct pci_device_id *ent)
1311{
1312 struct tulip_private *tp;
1313 /* See note below on the multiport cards. */
1314 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1315 static int last_irq;
1316 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1317 int i, irq;
1318 unsigned short sum;
1319 unsigned char *ee_data;
1320 struct net_device *dev;
1321 void __iomem *ioaddr;
1322 static int board_idx = -1;
1323 int chip_idx = ent->driver_data;
1324 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1325 unsigned int eeprom_missing = 0;
1326 unsigned int force_csr0 = 0;
1327
1328#ifndef MODULE
1329 if (tulip_debug > 0)
1330 printk_once(KERN_INFO "%s", version);
1331#endif
1332
1333 board_idx++;
1334
1335 /*
1336 * Lan media wire a tulip chip to a wan interface. Needs a very
1337 * different driver (lmc driver)
1338 */
1339
1340 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1341 pr_err("skipping LMC card\n");
1342 return -ENODEV;
1343 } else if (pdev->subsystem_vendor == PCI_VENDOR_ID_SBE &&
1344 (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_T3E3 ||
1345 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0 ||
1346 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)) {
1347 pr_err("skipping SBE T3E3 port\n");
1348 return -ENODEV;
1349 }
1350
1351 /*
1352 * DM910x chips should be handled by the dmfe driver, except
1353 * on-board chips on SPARC systems. Also, early DM9100s need
1354 * software CRC which only the dmfe driver supports.
1355 */
1356
1357#ifdef CONFIG_TULIP_DM910X
1358 if (chip_idx == DM910X) {
1359 struct device_node *dp;
1360
1361 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1362 pdev->revision < 0x30) {
1363 pr_info("skipping early DM9100 with Crc bug (use dmfe)\n");
1364 return -ENODEV;
1365 }
1366
1367 dp = pci_device_to_OF_node(pdev);
1368 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
1369 pr_info("skipping DM910x expansion card (use dmfe)\n");
1370 return -ENODEV;
1371 }
1372 }
1373#endif
1374
1375 /*
1376 * Looks for early PCI chipsets where people report hangs
1377 * without the workarounds being on.
1378 */
1379
1380 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1381 aligned. Aries might need this too. The Saturn errata are not
1382 pretty reading but thankfully it's an old 486 chipset.
1383
1384 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1385 Saturn.
1386 */
1387
1388 if (pci_dev_present(early_486_chipsets)) {
1389 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1390 force_csr0 = 1;
1391 }
1392
1393 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1394 if (chip_idx == AX88140) {
1395 if ((csr0 & 0x3f00) == 0)
1396 csr0 |= 0x2000;
1397 }
1398
1399 /* PNIC doesn't have MWI/MRL/MRM... */
1400 if (chip_idx == LC82C168)
1401 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1402
1403 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1404 if (tulip_uli_dm_quirk(pdev)) {
1405 csr0 &= ~0x01f100ff;
1406#if defined(CONFIG_SPARC)
1407 csr0 = (csr0 & ~0xff00) | 0xe000;
1408#endif
1409 }
1410 /*
1411 * And back to business
1412 */
1413
1414 i = pci_enable_device(pdev);
1415 if (i) {
1416 pr_err("Cannot enable tulip board #%d, aborting\n", board_idx);
1417 return i;
1418 }
1419
1420 /* The chip will fail to enter a low-power state later unless
1421 * first explicitly commanded into D0 */
1422 if (pci_set_power_state(pdev, PCI_D0)) {
1423 pr_notice("Failed to set power state to D0\n");
1424 }
1425
1426 irq = pdev->irq;
1427
1428 /* alloc_etherdev ensures aligned and zeroed private structures */
1429 dev = alloc_etherdev (sizeof (*tp));
1430 if (!dev) {
1431 pr_err("ether device alloc failed, aborting\n");
1432 return -ENOMEM;
1433 }
1434
1435 SET_NETDEV_DEV(dev, &pdev->dev);
1436 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1437 pr_err("%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
1438 pci_name(pdev),
1439 (unsigned long long)pci_resource_len (pdev, 0),
1440 (unsigned long long)pci_resource_start (pdev, 0));
1441 goto err_out_free_netdev;
1442 }
1443
1444 /* grab all resources from both PIO and MMIO regions, as we
1445 * don't want anyone else messing around with our hardware */
1446 if (pci_request_regions (pdev, DRV_NAME))
1447 goto err_out_free_netdev;
1448
1449 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1450
1451 if (!ioaddr)
1452 goto err_out_free_res;
1453
1454 /*
1455 * initialize private data structure 'tp'
1456 * it is zeroed and aligned in alloc_etherdev
1457 */
1458 tp = netdev_priv(dev);
1459 tp->dev = dev;
1460
1461 tp->rx_ring = pci_alloc_consistent(pdev,
1462 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1463 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1464 &tp->rx_ring_dma);
1465 if (!tp->rx_ring)
1466 goto err_out_mtable;
1467 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1468 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1469
1470 tp->chip_id = chip_idx;
1471 tp->flags = tulip_tbl[chip_idx].flags;
1472
1473 tp->wolinfo.supported = 0;
1474 tp->wolinfo.wolopts = 0;
1475 /* COMET: Enable power management only for AN983B */
1476 if (chip_idx == COMET ) {
1477 u32 sig;
1478 pci_read_config_dword (pdev, 0x80, &sig);
1479 if (sig == 0x09811317) {
1480 tp->flags |= COMET_PM;
1481 tp->wolinfo.supported = WAKE_PHY | WAKE_MAGIC;
1482 pr_info("%s: Enabled WOL support for AN983B\n",
1483 __func__);
1484 }
1485 }
1486 tp->pdev = pdev;
1487 tp->base_addr = ioaddr;
1488 tp->revision = pdev->revision;
1489 tp->csr0 = csr0;
1490 spin_lock_init(&tp->lock);
1491 spin_lock_init(&tp->mii_lock);
1492 init_timer(&tp->timer);
1493 tp->timer.data = (unsigned long)dev;
1494 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1495
1496 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1497
1498 dev->base_addr = (unsigned long)ioaddr;
1499
1500#ifdef CONFIG_TULIP_MWI
1501 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1502 tulip_mwi_config (pdev, dev);
1503#endif
1504
1505 /* Stop the chip's Tx and Rx processes. */
1506 tulip_stop_rxtx(tp);
1507
1508 pci_set_master(pdev);
1509
1510#ifdef CONFIG_GSC
1511 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1512 switch (pdev->subsystem_device) {
1513 default:
1514 break;
1515 case 0x1061:
1516 case 0x1062:
1517 case 0x1063:
1518 case 0x1098:
1519 case 0x1099:
1520 case 0x10EE:
1521 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1522 chip_name = "GSC DS21140 Tulip";
1523 }
1524 }
1525#endif
1526
1527 /* Clear the missed-packet counter. */
1528 ioread32(ioaddr + CSR8);
1529
1530 /* The station address ROM is read byte serially. The register must
1531 be polled, waiting for the value to be read bit serially from the
1532 EEPROM.
1533 */
1534 ee_data = tp->eeprom;
1535 memset(ee_data, 0, sizeof(tp->eeprom));
1536 sum = 0;
1537 if (chip_idx == LC82C168) {
1538 for (i = 0; i < 3; i++) {
1539 int value, boguscnt = 100000;
1540 iowrite32(0x600 | i, ioaddr + 0x98);
1541 do {
1542 value = ioread32(ioaddr + CSR9);
1543 } while (value < 0 && --boguscnt > 0);
1544 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1545 sum += value & 0xffff;
1546 }
1547 } else if (chip_idx == COMET) {
1548 /* No need to read the EEPROM. */
1549 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1550 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1551 for (i = 0; i < 6; i ++)
1552 sum += dev->dev_addr[i];
1553 } else {
1554 /* A serial EEPROM interface, we read now and sort it out later. */
1555 int sa_offset = 0;
1556 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1557 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1558
1559 if (ee_max_addr > sizeof(tp->eeprom))
1560 ee_max_addr = sizeof(tp->eeprom);
1561
1562 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1563 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1564 ee_data[i] = data & 0xff;
1565 ee_data[i + 1] = data >> 8;
1566 }
1567
1568 /* DEC now has a specification (see Notes) but early board makers
1569 just put the address in the first EEPROM locations. */
1570 /* This does memcmp(ee_data, ee_data+16, 8) */
1571 for (i = 0; i < 8; i ++)
1572 if (ee_data[i] != ee_data[16+i])
1573 sa_offset = 20;
1574 if (chip_idx == CONEXANT) {
1575 /* Check that the tuple type and length is correct. */
1576 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1577 sa_offset = 0x19A;
1578 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1579 ee_data[2] == 0) {
1580 sa_offset = 2; /* Grrr, damn Matrox boards. */
1581 multiport_cnt = 4;
1582 }
1583#ifdef CONFIG_MIPS_COBALT
1584 if ((pdev->bus->number == 0) &&
1585 ((PCI_SLOT(pdev->devfn) == 7) ||
1586 (PCI_SLOT(pdev->devfn) == 12))) {
1587 /* Cobalt MAC address in first EEPROM locations. */
1588 sa_offset = 0;
1589 /* Ensure our media table fixup get's applied */
1590 memcpy(ee_data + 16, ee_data, 8);
1591 }
1592#endif
1593#ifdef CONFIG_GSC
1594 /* Check to see if we have a broken srom */
1595 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1596 /* pci_vendor_id and subsystem_id are swapped */
1597 ee_data[0] = ee_data[2];
1598 ee_data[1] = ee_data[3];
1599 ee_data[2] = 0x61;
1600 ee_data[3] = 0x10;
1601
1602 /* HSC-PCI boards need to be byte-swaped and shifted
1603 * up 1 word. This shift needs to happen at the end
1604 * of the MAC first because of the 2 byte overlap.
1605 */
1606 for (i = 4; i >= 0; i -= 2) {
1607 ee_data[17 + i + 3] = ee_data[17 + i];
1608 ee_data[16 + i + 5] = ee_data[16 + i];
1609 }
1610 }
1611#endif
1612
1613 for (i = 0; i < 6; i ++) {
1614 dev->dev_addr[i] = ee_data[i + sa_offset];
1615 sum += ee_data[i + sa_offset];
1616 }
1617 }
1618 /* Lite-On boards have the address byte-swapped. */
1619 if ((dev->dev_addr[0] == 0xA0 ||
1620 dev->dev_addr[0] == 0xC0 ||
1621 dev->dev_addr[0] == 0x02) &&
1622 dev->dev_addr[1] == 0x00)
1623 for (i = 0; i < 6; i+=2) {
1624 char tmp = dev->dev_addr[i];
1625 dev->dev_addr[i] = dev->dev_addr[i+1];
1626 dev->dev_addr[i+1] = tmp;
1627 }
1628 /* On the Zynx 315 Etherarray and other multiport boards only the
1629 first Tulip has an EEPROM.
1630 On Sparc systems the mac address is held in the OBP property
1631 "local-mac-address".
1632 The addresses of the subsequent ports are derived from the first.
1633 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1634 that here as well. */
1635 if (sum == 0 || sum == 6*0xff) {
1636#if defined(CONFIG_SPARC)
1637 struct device_node *dp = pci_device_to_OF_node(pdev);
1638 const unsigned char *addr;
1639 int len;
1640#endif
1641 eeprom_missing = 1;
1642 for (i = 0; i < 5; i++)
1643 dev->dev_addr[i] = last_phys_addr[i];
1644 dev->dev_addr[i] = last_phys_addr[i] + 1;
1645#if defined(CONFIG_SPARC)
1646 addr = of_get_property(dp, "local-mac-address", &len);
1647 if (addr && len == 6)
1648 memcpy(dev->dev_addr, addr, 6);
1649#endif
1650#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1651 if (last_irq)
1652 irq = last_irq;
1653#endif
1654 }
1655
1656 for (i = 0; i < 6; i++)
1657 last_phys_addr[i] = dev->dev_addr[i];
1658 last_irq = irq;
1659 dev->irq = irq;
1660
1661 /* The lower four bits are the media type. */
1662 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1663 if (options[board_idx] & MEDIA_MASK)
1664 tp->default_port = options[board_idx] & MEDIA_MASK;
1665 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1666 tp->full_duplex = 1;
1667 if (mtu[board_idx] > 0)
1668 dev->mtu = mtu[board_idx];
1669 }
1670 if (dev->mem_start & MEDIA_MASK)
1671 tp->default_port = dev->mem_start & MEDIA_MASK;
1672 if (tp->default_port) {
1673 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
1674 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1675 tp->medialock = 1;
1676 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1677 tp->full_duplex = 1;
1678 }
1679 if (tp->full_duplex)
1680 tp->full_duplex_lock = 1;
1681
1682 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1683 static const u16 media2advert[] = {
1684 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200
1685 };
1686 tp->mii_advertise = media2advert[tp->default_port - 9];
1687 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1688 }
1689
1690 if (tp->flags & HAS_MEDIA_TABLE) {
1691 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
1692 tulip_parse_eeprom(dev);
1693 strcpy(dev->name, "eth%d"); /* un-hack */
1694 }
1695
1696 if ((tp->flags & ALWAYS_CHECK_MII) ||
1697 (tp->mtable && tp->mtable->has_mii) ||
1698 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1699 if (tp->mtable && tp->mtable->has_mii) {
1700 for (i = 0; i < tp->mtable->leafcount; i++)
1701 if (tp->mtable->mleaf[i].media == 11) {
1702 tp->cur_index = i;
1703 tp->saved_if_port = dev->if_port;
1704 tulip_select_media(dev, 2);
1705 dev->if_port = tp->saved_if_port;
1706 break;
1707 }
1708 }
1709
1710 /* Find the connected MII xcvrs.
1711 Doing this in open() would allow detecting external xcvrs
1712 later, but takes much time. */
1713 tulip_find_mii (dev, board_idx);
1714 }
1715
1716 /* The Tulip-specific entries in the device structure. */
1717 dev->netdev_ops = &tulip_netdev_ops;
1718 dev->watchdog_timeo = TX_TIMEOUT;
1719#ifdef CONFIG_TULIP_NAPI
1720 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1721#endif
1722 SET_ETHTOOL_OPS(dev, &ops);
1723
1724 if (register_netdev(dev))
1725 goto err_out_free_ring;
1726
1727 pci_set_drvdata(pdev, dev);
1728
1729 dev_info(&dev->dev,
1730#ifdef CONFIG_TULIP_MMIO
1731 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
1732#else
1733 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
1734#endif
1735 chip_name, pdev->revision,
1736 (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
1737 eeprom_missing ? " EEPROM not present," : "",
1738 dev->dev_addr, irq);
1739
1740 if (tp->chip_id == PNIC2)
1741 tp->link_change = pnic2_lnk_change;
1742 else if (tp->flags & HAS_NWAY)
1743 tp->link_change = t21142_lnk_change;
1744 else if (tp->flags & HAS_PNICNWAY)
1745 tp->link_change = pnic_lnk_change;
1746
1747 /* Reset the xcvr interface and turn on heartbeat. */
1748 switch (chip_idx) {
1749 case DC21140:
1750 case DM910X:
1751 default:
1752 if (tp->mtable)
1753 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1754 break;
1755 case DC21142:
1756 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1757 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1758 iowrite32(0x0000, ioaddr + CSR13);
1759 iowrite32(0x0000, ioaddr + CSR14);
1760 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1761 } else
1762 t21142_start_nway(dev);
1763 break;
1764 case PNIC2:
1765 /* just do a reset for sanity sake */
1766 iowrite32(0x0000, ioaddr + CSR13);
1767 iowrite32(0x0000, ioaddr + CSR14);
1768 break;
1769 case LC82C168:
1770 if ( ! tp->mii_cnt) {
1771 tp->nway = 1;
1772 tp->nwayset = 0;
1773 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1774 iowrite32(0x30, ioaddr + CSR12);
1775 iowrite32(0x0001F078, ioaddr + CSR6);
1776 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1777 }
1778 break;
1779 case MX98713:
1780 case COMPEX9881:
1781 iowrite32(0x00000000, ioaddr + CSR6);
1782 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1783 iowrite32(0x00000001, ioaddr + CSR13);
1784 break;
1785 case MX98715:
1786 case MX98725:
1787 iowrite32(0x01a80000, ioaddr + CSR6);
1788 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1789 iowrite32(0x00001000, ioaddr + CSR12);
1790 break;
1791 case COMET:
1792 /* No initialization necessary. */
1793 break;
1794 }
1795
1796 /* put the chip in snooze mode until opened */
1797 tulip_set_power_state (tp, 0, 1);
1798
1799 return 0;
1800
1801err_out_free_ring:
1802 pci_free_consistent (pdev,
1803 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1804 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1805 tp->rx_ring, tp->rx_ring_dma);
1806
1807err_out_mtable:
1808 kfree (tp->mtable);
1809 pci_iounmap(pdev, ioaddr);
1810
1811err_out_free_res:
1812 pci_release_regions (pdev);
1813
1814err_out_free_netdev:
1815 free_netdev (dev);
1816 return -ENODEV;
1817}
1818
1819
1820/* set the registers according to the given wolopts */
1821static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts)
1822{
1823 struct net_device *dev = pci_get_drvdata(pdev);
1824 struct tulip_private *tp = netdev_priv(dev);
1825 void __iomem *ioaddr = tp->base_addr;
1826
1827 if (tp->flags & COMET_PM) {
1828
1829 unsigned int tmp;
1830
1831 tmp = ioread32(ioaddr + CSR18);
1832 tmp &= ~(comet_csr18_pmes_sticky | comet_csr18_apm_mode | comet_csr18_d3a);
1833 tmp |= comet_csr18_pm_mode;
1834 iowrite32(tmp, ioaddr + CSR18);
1835
1836 /* Set the Wake-up Control/Status Register to the given WOL options*/
1837 tmp = ioread32(ioaddr + CSR13);
1838 tmp &= ~(comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_wfre | comet_csr13_lsce | comet_csr13_mpre);
1839 if (wolopts & WAKE_MAGIC)
1840 tmp |= comet_csr13_mpre;
1841 if (wolopts & WAKE_PHY)
1842 tmp |= comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_lsce;
1843 /* Clear the event flags */
1844 tmp |= comet_csr13_wfr | comet_csr13_mpr | comet_csr13_lsc;
1845 iowrite32(tmp, ioaddr + CSR13);
1846 }
1847}
1848
1849#ifdef CONFIG_PM
1850
1851
1852static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1853{
1854 pci_power_t pstate;
1855 struct net_device *dev = pci_get_drvdata(pdev);
1856 struct tulip_private *tp = netdev_priv(dev);
1857
1858 if (!dev)
1859 return -EINVAL;
1860
1861 if (!netif_running(dev))
1862 goto save_state;
1863
1864 tulip_down(dev);
1865
1866 netif_device_detach(dev);
1867 free_irq(dev->irq, dev);
1868
1869save_state:
1870 pci_save_state(pdev);
1871 pci_disable_device(pdev);
1872 pstate = pci_choose_state(pdev, state);
1873 if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) {
1874 int rc;
1875
1876 tulip_set_wolopts(pdev, tp->wolinfo.wolopts);
1877 rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts);
1878 if (rc)
1879 pr_err("pci_enable_wake failed (%d)\n", rc);
1880 }
1881 pci_set_power_state(pdev, pstate);
1882
1883 return 0;
1884}
1885
1886
1887static int tulip_resume(struct pci_dev *pdev)
1888{
1889 struct net_device *dev = pci_get_drvdata(pdev);
1890 struct tulip_private *tp = netdev_priv(dev);
1891 void __iomem *ioaddr = tp->base_addr;
1892 int retval;
1893 unsigned int tmp;
1894
1895 if (!dev)
1896 return -EINVAL;
1897
1898 pci_set_power_state(pdev, PCI_D0);
1899 pci_restore_state(pdev);
1900
1901 if (!netif_running(dev))
1902 return 0;
1903
1904 if ((retval = pci_enable_device(pdev))) {
1905 pr_err("pci_enable_device failed in resume\n");
1906 return retval;
1907 }
1908
1909 if ((retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1910 pr_err("request_irq failed in resume\n");
1911 return retval;
1912 }
1913
1914 if (tp->flags & COMET_PM) {
1915 pci_enable_wake(pdev, PCI_D3hot, 0);
1916 pci_enable_wake(pdev, PCI_D3cold, 0);
1917
1918 /* Clear the PMES flag */
1919 tmp = ioread32(ioaddr + CSR20);
1920 tmp |= comet_csr20_pmes;
1921 iowrite32(tmp, ioaddr + CSR20);
1922
1923 /* Disable all wake-up events */
1924 tulip_set_wolopts(pdev, 0);
1925 }
1926 netif_device_attach(dev);
1927
1928 if (netif_running(dev))
1929 tulip_up(dev);
1930
1931 return 0;
1932}
1933
1934#endif /* CONFIG_PM */
1935
1936
1937static void __devexit tulip_remove_one (struct pci_dev *pdev)
1938{
1939 struct net_device *dev = pci_get_drvdata (pdev);
1940 struct tulip_private *tp;
1941
1942 if (!dev)
1943 return;
1944
1945 tp = netdev_priv(dev);
1946 unregister_netdev(dev);
1947 pci_free_consistent (pdev,
1948 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1949 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1950 tp->rx_ring, tp->rx_ring_dma);
1951 kfree (tp->mtable);
1952 pci_iounmap(pdev, tp->base_addr);
1953 free_netdev (dev);
1954 pci_release_regions (pdev);
1955 pci_set_drvdata (pdev, NULL);
1956
1957 /* pci_power_off (pdev, -1); */
1958}
1959
1960#ifdef CONFIG_NET_POLL_CONTROLLER
1961/*
1962 * Polling 'interrupt' - used by things like netconsole to send skbs
1963 * without having to re-enable interrupts. It's not called while
1964 * the interrupt routine is executing.
1965 */
1966
1967static void poll_tulip (struct net_device *dev)
1968{
1969 /* disable_irq here is not very nice, but with the lockless
1970 interrupt handler we have no other choice. */
1971 disable_irq(dev->irq);
1972 tulip_interrupt (dev->irq, dev);
1973 enable_irq(dev->irq);
1974}
1975#endif
1976
1977static struct pci_driver tulip_driver = {
1978 .name = DRV_NAME,
1979 .id_table = tulip_pci_tbl,
1980 .probe = tulip_init_one,
1981 .remove = __devexit_p(tulip_remove_one),
1982#ifdef CONFIG_PM
1983 .suspend = tulip_suspend,
1984 .resume = tulip_resume,
1985#endif /* CONFIG_PM */
1986};
1987
1988
1989static int __init tulip_init (void)
1990{
1991#ifdef MODULE
1992 pr_info("%s", version);
1993#endif
1994
1995 /* copy module parms into globals */
1996 tulip_rx_copybreak = rx_copybreak;
1997 tulip_max_interrupt_work = max_interrupt_work;
1998
1999 /* probe for and init boards */
2000 return pci_register_driver(&tulip_driver);
2001}
2002
2003
2004static void __exit tulip_cleanup (void)
2005{
2006 pci_unregister_driver (&tulip_driver);
2007}
2008
2009
2010module_init(tulip_init);
2011module_exit(tulip_cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-08 18:55:37 -0400