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-rw-r--r--drivers/net/tg3.c839
1 files changed, 359 insertions, 480 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index ecc41cffb47..573054ae7b5 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -67,8 +67,8 @@
67#include "tg3.h" 67#include "tg3.h"
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define DRV_MODULE_VERSION "3.108" 70#define DRV_MODULE_VERSION "3.110"
71#define DRV_MODULE_RELDATE "February 17, 2010" 71#define DRV_MODULE_RELDATE "April 9, 2010"
72 72
73#define TG3_DEF_MAC_MODE 0 73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0 74#define TG3_DEF_RX_MODE 0
@@ -101,7 +101,7 @@
101#define TG3_DEF_RX_RING_PENDING 200 101#define TG3_DEF_RX_RING_PENDING 200
102#define TG3_RX_JUMBO_RING_SIZE 256 102#define TG3_RX_JUMBO_RING_SIZE 256
103#define TG3_DEF_RX_JUMBO_RING_PENDING 100 103#define TG3_DEF_RX_JUMBO_RING_PENDING 100
104#define TG3_RSS_INDIR_TBL_SIZE 128 104#define TG3_RSS_INDIR_TBL_SIZE 128
105 105
106/* Do not place this n-ring entries value into the tp struct itself, 106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et 107 * we really want to expose these constants to GCC so that modulo et
@@ -126,6 +126,9 @@
126 TG3_TX_RING_SIZE) 126 TG3_TX_RING_SIZE)
127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) 127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 128
129#define TG3_RX_DMA_ALIGN 16
130#define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
131
129#define TG3_DMA_BYTE_ENAB 64 132#define TG3_DMA_BYTE_ENAB 64
130 133
131#define TG3_RX_STD_DMA_SZ 1536 134#define TG3_RX_STD_DMA_SZ 1536
@@ -142,6 +145,26 @@
142#define TG3_RX_JMB_BUFF_RING_SIZE \ 145#define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE) 146 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
144 147
148#define TG3_RSS_MIN_NUM_MSIX_VECS 2
149
150/* Due to a hardware bug, the 5701 can only DMA to memory addresses
151 * that are at least dword aligned when used in PCIX mode. The driver
152 * works around this bug by double copying the packet. This workaround
153 * is built into the normal double copy length check for efficiency.
154 *
155 * However, the double copy is only necessary on those architectures
156 * where unaligned memory accesses are inefficient. For those architectures
157 * where unaligned memory accesses incur little penalty, we can reintegrate
158 * the 5701 in the normal rx path. Doing so saves a device structure
159 * dereference by hardcoding the double copy threshold in place.
160 */
161#define TG3_RX_COPY_THRESHOLD 256
162#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
163 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
164#else
165 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
166#endif
167
145/* minimum number of free TX descriptors required to wake up TX process */ 168/* minimum number of free TX descriptors required to wake up TX process */
146#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) 169#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
147 170
@@ -152,6 +175,8 @@
152 175
153#define TG3_NUM_TEST 6 176#define TG3_NUM_TEST 6
154 177
178#define TG3_FW_UPDATE_TIMEOUT_SEC 5
179
155#define FIRMWARE_TG3 "tigon/tg3.bin" 180#define FIRMWARE_TG3 "tigon/tg3.bin"
156#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" 181#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
157#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" 182#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
@@ -167,8 +192,6 @@ MODULE_FIRMWARE(FIRMWARE_TG3);
167MODULE_FIRMWARE(FIRMWARE_TG3TSO); 192MODULE_FIRMWARE(FIRMWARE_TG3TSO);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO5); 193MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
169 194
170#define TG3_RSS_MIN_NUM_MSIX_VECS 2
171
172static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ 195static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
173module_param(tg3_debug, int, 0); 196module_param(tg3_debug, int, 0);
174MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); 197MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
@@ -360,7 +383,7 @@ static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
360 383
361static u32 tg3_read32(struct tg3 *tp, u32 off) 384static u32 tg3_read32(struct tg3 *tp, u32 off)
362{ 385{
363 return (readl(tp->regs + off)); 386 return readl(tp->regs + off);
364} 387}
365 388
366static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) 389static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
@@ -370,7 +393,7 @@ static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
370 393
371static u32 tg3_ape_read32(struct tg3 *tp, u32 off) 394static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
372{ 395{
373 return (readl(tp->aperegs + off)); 396 return readl(tp->aperegs + off);
374} 397}
375 398
376static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) 399static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
@@ -488,7 +511,7 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
488 511
489static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) 512static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
490{ 513{
491 return (readl(tp->regs + off + GRCMBOX_BASE)); 514 return readl(tp->regs + off + GRCMBOX_BASE);
492} 515}
493 516
494static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) 517static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
@@ -496,16 +519,16 @@ static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
496 writel(val, tp->regs + off + GRCMBOX_BASE); 519 writel(val, tp->regs + off + GRCMBOX_BASE);
497} 520}
498 521
499#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) 522#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
500#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) 523#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
501#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) 524#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
502#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) 525#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
503#define tr32_mailbox(reg) tp->read32_mbox(tp, reg) 526#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
504 527
505#define tw32(reg,val) tp->write32(tp, reg, val) 528#define tw32(reg, val) tp->write32(tp, reg, val)
506#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0) 529#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
507#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us)) 530#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
508#define tr32(reg) tp->read32(tp, reg) 531#define tr32(reg) tp->read32(tp, reg)
509 532
510static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) 533static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
511{ 534{
@@ -579,11 +602,11 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
579 return 0; 602 return 0;
580 603
581 switch (locknum) { 604 switch (locknum) {
582 case TG3_APE_LOCK_GRC: 605 case TG3_APE_LOCK_GRC:
583 case TG3_APE_LOCK_MEM: 606 case TG3_APE_LOCK_MEM:
584 break; 607 break;
585 default: 608 default:
586 return -EINVAL; 609 return -EINVAL;
587 } 610 }
588 611
589 off = 4 * locknum; 612 off = 4 * locknum;
@@ -617,11 +640,11 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
617 return; 640 return;
618 641
619 switch (locknum) { 642 switch (locknum) {
620 case TG3_APE_LOCK_GRC: 643 case TG3_APE_LOCK_GRC:
621 case TG3_APE_LOCK_MEM: 644 case TG3_APE_LOCK_MEM:
622 break; 645 break;
623 default: 646 default:
624 return; 647 return;
625 } 648 }
626 649
627 off = 4 * locknum; 650 off = 4 * locknum;
@@ -651,6 +674,7 @@ static void tg3_enable_ints(struct tg3 *tp)
651 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; 674 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
652 for (i = 0; i < tp->irq_cnt; i++) { 675 for (i = 0; i < tp->irq_cnt; i++) {
653 struct tg3_napi *tnapi = &tp->napi[i]; 676 struct tg3_napi *tnapi = &tp->napi[i];
677
654 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); 678 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
655 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) 679 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
656 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); 680 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
@@ -1098,7 +1122,7 @@ static int tg3_mdio_init(struct tg3 *tp)
1098 1122
1099 i = mdiobus_register(tp->mdio_bus); 1123 i = mdiobus_register(tp->mdio_bus);
1100 if (i) { 1124 if (i) {
1101 netdev_warn(tp->dev, "mdiobus_reg failed (0x%x)\n", i); 1125 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1102 mdiobus_free(tp->mdio_bus); 1126 mdiobus_free(tp->mdio_bus);
1103 return i; 1127 return i;
1104 } 1128 }
@@ -1106,7 +1130,7 @@ static int tg3_mdio_init(struct tg3 *tp)
1106 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; 1130 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1107 1131
1108 if (!phydev || !phydev->drv) { 1132 if (!phydev || !phydev->drv) {
1109 netdev_warn(tp->dev, "No PHY devices\n"); 1133 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1110 mdiobus_unregister(tp->mdio_bus); 1134 mdiobus_unregister(tp->mdio_bus);
1111 mdiobus_free(tp->mdio_bus); 1135 mdiobus_free(tp->mdio_bus);
1112 return -ENODEV; 1136 return -ENODEV;
@@ -1437,7 +1461,7 @@ static void tg3_adjust_link(struct net_device *dev)
1437 phydev->speed != tp->link_config.active_speed || 1461 phydev->speed != tp->link_config.active_speed ||
1438 phydev->duplex != tp->link_config.active_duplex || 1462 phydev->duplex != tp->link_config.active_duplex ||
1439 oldflowctrl != tp->link_config.active_flowctrl) 1463 oldflowctrl != tp->link_config.active_flowctrl)
1440 linkmesg = 1; 1464 linkmesg = 1;
1441 1465
1442 tp->link_config.active_speed = phydev->speed; 1466 tp->link_config.active_speed = phydev->speed;
1443 tp->link_config.active_duplex = phydev->duplex; 1467 tp->link_config.active_duplex = phydev->duplex;
@@ -1464,7 +1488,7 @@ static int tg3_phy_init(struct tg3 *tp)
1464 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, 1488 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1465 phydev->dev_flags, phydev->interface); 1489 phydev->dev_flags, phydev->interface);
1466 if (IS_ERR(phydev)) { 1490 if (IS_ERR(phydev)) {
1467 netdev_err(tp->dev, "Could not attach to PHY\n"); 1491 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1468 return PTR_ERR(phydev); 1492 return PTR_ERR(phydev);
1469 } 1493 }
1470 1494
@@ -1855,8 +1879,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 1879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1856 /* Set Extended packet length bit for jumbo frames */ 1880 /* Set Extended packet length bit for jumbo frames */
1857 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); 1881 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1858 } 1882 } else {
1859 else {
1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1883 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1861 } 1884 }
1862 1885
@@ -1974,8 +1997,7 @@ out:
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f); 1997 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1975 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); 1998 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1999 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1977 } 2000 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1978 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1979 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); 2001 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); 2002 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1981 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) { 2003 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
@@ -2007,8 +2029,8 @@ out:
2007 u32 phy_reg; 2029 u32 phy_reg;
2008 2030
2009 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) 2031 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2010 tg3_writephy(tp, MII_TG3_EXT_CTRL, 2032 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2011 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC); 2033 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2012 } 2034 }
2013 2035
2014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 2036 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
@@ -3425,7 +3447,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3425 ap->rxconfig = rx_cfg_reg; 3447 ap->rxconfig = rx_cfg_reg;
3426 ret = ANEG_OK; 3448 ret = ANEG_OK;
3427 3449
3428 switch(ap->state) { 3450 switch (ap->state) {
3429 case ANEG_STATE_UNKNOWN: 3451 case ANEG_STATE_UNKNOWN:
3430 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) 3452 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3431 ap->state = ANEG_STATE_AN_ENABLE; 3453 ap->state = ANEG_STATE_AN_ENABLE;
@@ -3463,11 +3485,10 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3463 /* fallthru */ 3485 /* fallthru */
3464 case ANEG_STATE_RESTART: 3486 case ANEG_STATE_RESTART:
3465 delta = ap->cur_time - ap->link_time; 3487 delta = ap->cur_time - ap->link_time;
3466 if (delta > ANEG_STATE_SETTLE_TIME) { 3488 if (delta > ANEG_STATE_SETTLE_TIME)
3467 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; 3489 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3468 } else { 3490 else
3469 ret = ANEG_TIMER_ENAB; 3491 ret = ANEG_TIMER_ENAB;
3470 }
3471 break; 3492 break;
3472 3493
3473 case ANEG_STATE_DISABLE_LINK_OK: 3494 case ANEG_STATE_DISABLE_LINK_OK:
@@ -3491,9 +3512,8 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3491 break; 3512 break;
3492 3513
3493 case ANEG_STATE_ABILITY_DETECT: 3514 case ANEG_STATE_ABILITY_DETECT:
3494 if (ap->ability_match != 0 && ap->rxconfig != 0) { 3515 if (ap->ability_match != 0 && ap->rxconfig != 0)
3495 ap->state = ANEG_STATE_ACK_DETECT_INIT; 3516 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3496 }
3497 break; 3517 break;
3498 3518
3499 case ANEG_STATE_ACK_DETECT_INIT: 3519 case ANEG_STATE_ACK_DETECT_INIT:
@@ -4171,9 +4191,9 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4171 current_duplex = DUPLEX_FULL; 4191 current_duplex = DUPLEX_FULL;
4172 else 4192 else
4173 current_duplex = DUPLEX_HALF; 4193 current_duplex = DUPLEX_HALF;
4174 } 4194 } else {
4175 else
4176 current_link_up = 0; 4195 current_link_up = 0;
4196 }
4177 } 4197 }
4178 } 4198 }
4179 4199
@@ -4211,6 +4231,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
4211 tp->serdes_counter--; 4231 tp->serdes_counter--;
4212 return; 4232 return;
4213 } 4233 }
4234
4214 if (!netif_carrier_ok(tp->dev) && 4235 if (!netif_carrier_ok(tp->dev) &&
4215 (tp->link_config.autoneg == AUTONEG_ENABLE)) { 4236 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4216 u32 bmcr; 4237 u32 bmcr;
@@ -4240,10 +4261,9 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
4240 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT; 4261 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4241 } 4262 }
4242 } 4263 }
4243 } 4264 } else if (netif_carrier_ok(tp->dev) &&
4244 else if (netif_carrier_ok(tp->dev) && 4265 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4245 (tp->link_config.autoneg == AUTONEG_ENABLE) && 4266 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4246 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4247 u32 phy2; 4267 u32 phy2;
4248 4268
4249 /* Select expansion interrupt status register */ 4269 /* Select expansion interrupt status register */
@@ -4266,13 +4286,12 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4266{ 4286{
4267 int err; 4287 int err;
4268 4288
4269 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { 4289 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4270 err = tg3_setup_fiber_phy(tp, force_reset); 4290 err = tg3_setup_fiber_phy(tp, force_reset);
4271 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { 4291 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4272 err = tg3_setup_fiber_mii_phy(tp, force_reset); 4292 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4273 } else { 4293 else
4274 err = tg3_setup_copper_phy(tp, force_reset); 4294 err = tg3_setup_copper_phy(tp, force_reset);
4275 }
4276 4295
4277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { 4296 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4278 u32 val, scale; 4297 u32 val, scale;
@@ -4335,8 +4354,11 @@ static void tg3_tx_recover(struct tg3 *tp)
4335 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || 4354 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4336 tp->write32_tx_mbox == tg3_write_indirect_mbox); 4355 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4337 4356
4338 netdev_warn(tp->dev, "The system may be re-ordering memory-mapped I/O cycles to the network device, attempting to recover\n" 4357 netdev_warn(tp->dev,
4339 "Please report the problem to the driver maintainer and include system chipset information.\n"); 4358 "The system may be re-ordering memory-mapped I/O "
4359 "cycles to the network device, attempting to recover. "
4360 "Please report the problem to the driver maintainer "
4361 "and include system chipset information.\n");
4340 4362
4341 spin_lock(&tp->lock); 4363 spin_lock(&tp->lock);
4342 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; 4364 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
@@ -4378,7 +4400,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
4378 } 4400 }
4379 4401
4380 pci_unmap_single(tp->pdev, 4402 pci_unmap_single(tp->pdev,
4381 pci_unmap_addr(ri, mapping), 4403 dma_unmap_addr(ri, mapping),
4382 skb_headlen(skb), 4404 skb_headlen(skb),
4383 PCI_DMA_TODEVICE); 4405 PCI_DMA_TODEVICE);
4384 4406
@@ -4392,7 +4414,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
4392 tx_bug = 1; 4414 tx_bug = 1;
4393 4415
4394 pci_unmap_page(tp->pdev, 4416 pci_unmap_page(tp->pdev,
4395 pci_unmap_addr(ri, mapping), 4417 dma_unmap_addr(ri, mapping),
4396 skb_shinfo(skb)->frags[i].size, 4418 skb_shinfo(skb)->frags[i].size,
4397 PCI_DMA_TODEVICE); 4419 PCI_DMA_TODEVICE);
4398 sw_idx = NEXT_TX(sw_idx); 4420 sw_idx = NEXT_TX(sw_idx);
@@ -4430,7 +4452,7 @@ static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4430 if (!ri->skb) 4452 if (!ri->skb)
4431 return; 4453 return;
4432 4454
4433 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping), 4455 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4434 map_sz, PCI_DMA_FROMDEVICE); 4456 map_sz, PCI_DMA_FROMDEVICE);
4435 dev_kfree_skb_any(ri->skb); 4457 dev_kfree_skb_any(ri->skb);
4436 ri->skb = NULL; 4458 ri->skb = NULL;
@@ -4496,7 +4518,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4496 } 4518 }
4497 4519
4498 map->skb = skb; 4520 map->skb = skb;
4499 pci_unmap_addr_set(map, mapping, mapping); 4521 dma_unmap_addr_set(map, mapping, mapping);
4500 4522
4501 desc->addr_hi = ((u64)mapping >> 32); 4523 desc->addr_hi = ((u64)mapping >> 32);
4502 desc->addr_lo = ((u64)mapping & 0xffffffff); 4524 desc->addr_lo = ((u64)mapping & 0xffffffff);
@@ -4516,8 +4538,8 @@ static void tg3_recycle_rx(struct tg3_napi *tnapi,
4516 struct tg3 *tp = tnapi->tp; 4538 struct tg3 *tp = tnapi->tp;
4517 struct tg3_rx_buffer_desc *src_desc, *dest_desc; 4539 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4518 struct ring_info *src_map, *dest_map; 4540 struct ring_info *src_map, *dest_map;
4519 int dest_idx;
4520 struct tg3_rx_prodring_set *spr = &tp->prodring[0]; 4541 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4542 int dest_idx;
4521 4543
4522 switch (opaque_key) { 4544 switch (opaque_key) {
4523 case RXD_OPAQUE_RING_STD: 4545 case RXD_OPAQUE_RING_STD:
@@ -4541,8 +4563,8 @@ static void tg3_recycle_rx(struct tg3_napi *tnapi,
4541 } 4563 }
4542 4564
4543 dest_map->skb = src_map->skb; 4565 dest_map->skb = src_map->skb;
4544 pci_unmap_addr_set(dest_map, mapping, 4566 dma_unmap_addr_set(dest_map, mapping,
4545 pci_unmap_addr(src_map, mapping)); 4567 dma_unmap_addr(src_map, mapping));
4546 dest_desc->addr_hi = src_desc->addr_hi; 4568 dest_desc->addr_hi = src_desc->addr_hi;
4547 dest_desc->addr_lo = src_desc->addr_lo; 4569 dest_desc->addr_lo = src_desc->addr_lo;
4548 4570
@@ -4605,18 +4627,20 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
4605 struct sk_buff *skb; 4627 struct sk_buff *skb;
4606 dma_addr_t dma_addr; 4628 dma_addr_t dma_addr;
4607 u32 opaque_key, desc_idx, *post_ptr; 4629 u32 opaque_key, desc_idx, *post_ptr;
4630 bool hw_vlan __maybe_unused = false;
4631 u16 vtag __maybe_unused = 0;
4608 4632
4609 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; 4633 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4610 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; 4634 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4611 if (opaque_key == RXD_OPAQUE_RING_STD) { 4635 if (opaque_key == RXD_OPAQUE_RING_STD) {
4612 ri = &tp->prodring[0].rx_std_buffers[desc_idx]; 4636 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4613 dma_addr = pci_unmap_addr(ri, mapping); 4637 dma_addr = dma_unmap_addr(ri, mapping);
4614 skb = ri->skb; 4638 skb = ri->skb;
4615 post_ptr = &std_prod_idx; 4639 post_ptr = &std_prod_idx;
4616 rx_std_posted++; 4640 rx_std_posted++;
4617 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { 4641 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4618 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx]; 4642 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4619 dma_addr = pci_unmap_addr(ri, mapping); 4643 dma_addr = dma_unmap_addr(ri, mapping);
4620 skb = ri->skb; 4644 skb = ri->skb;
4621 post_ptr = &jmb_prod_idx; 4645 post_ptr = &jmb_prod_idx;
4622 } else 4646 } else
@@ -4638,12 +4662,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
4638 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4662 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4639 ETH_FCS_LEN; 4663 ETH_FCS_LEN;
4640 4664
4641 if (len > RX_COPY_THRESHOLD && 4665 if (len > TG3_RX_COPY_THRESH(tp)) {
4642 tp->rx_offset == NET_IP_ALIGN) {
4643 /* rx_offset will likely not equal NET_IP_ALIGN
4644 * if this is a 5701 card running in PCI-X mode
4645 * [see tg3_get_invariants()]
4646 */
4647 int skb_size; 4666 int skb_size;
4648 4667
4649 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, 4668 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
@@ -4668,12 +4687,12 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
4668 tg3_recycle_rx(tnapi, tpr, opaque_key, 4687 tg3_recycle_rx(tnapi, tpr, opaque_key,
4669 desc_idx, *post_ptr); 4688 desc_idx, *post_ptr);
4670 4689
4671 copy_skb = netdev_alloc_skb(tp->dev, 4690 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4672 len + TG3_RAW_IP_ALIGN); 4691 TG3_RAW_IP_ALIGN);
4673 if (copy_skb == NULL) 4692 if (copy_skb == NULL)
4674 goto drop_it_no_recycle; 4693 goto drop_it_no_recycle;
4675 4694
4676 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN); 4695 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4677 skb_put(copy_skb, len); 4696 skb_put(copy_skb, len);
4678 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); 4697 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4679 skb_copy_from_linear_data(skb, copy_skb->data, len); 4698 skb_copy_from_linear_data(skb, copy_skb->data, len);
@@ -4699,12 +4718,29 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
4699 goto next_pkt; 4718 goto next_pkt;
4700 } 4719 }
4701 4720
4721 if (desc->type_flags & RXD_FLAG_VLAN &&
4722 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4723 vtag = desc->err_vlan & RXD_VLAN_MASK;
4702#if TG3_VLAN_TAG_USED 4724#if TG3_VLAN_TAG_USED
4703 if (tp->vlgrp != NULL && 4725 if (tp->vlgrp)
4704 desc->type_flags & RXD_FLAG_VLAN) { 4726 hw_vlan = true;
4705 vlan_gro_receive(&tnapi->napi, tp->vlgrp, 4727 else
4706 desc->err_vlan & RXD_VLAN_MASK, skb); 4728#endif
4707 } else 4729 {
4730 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4731 __skb_push(skb, VLAN_HLEN);
4732
4733 memmove(ve, skb->data + VLAN_HLEN,
4734 ETH_ALEN * 2);
4735 ve->h_vlan_proto = htons(ETH_P_8021Q);
4736 ve->h_vlan_TCI = htons(vtag);
4737 }
4738 }
4739
4740#if TG3_VLAN_TAG_USED
4741 if (hw_vlan)
4742 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4743 else
4708#endif 4744#endif
4709 napi_gro_receive(&tnapi->napi, skb); 4745 napi_gro_receive(&tnapi->napi, skb);
4710 4746
@@ -4978,7 +5014,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
4978 if (unlikely(work_done >= budget)) 5014 if (unlikely(work_done >= budget))
4979 break; 5015 break;
4980 5016
4981 /* tp->last_tag is used in tg3_restart_ints() below 5017 /* tp->last_tag is used in tg3_int_reenable() below
4982 * to tell the hw how much work has been processed, 5018 * to tell the hw how much work has been processed,
4983 * so we must read it before checking for more work. 5019 * so we must read it before checking for more work.
4984 */ 5020 */
@@ -4987,8 +5023,8 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
4987 rmb(); 5023 rmb();
4988 5024
4989 /* check for RX/TX work to do */ 5025 /* check for RX/TX work to do */
4990 if (sblk->idx[0].tx_consumer == tnapi->tx_cons && 5026 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4991 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) { 5027 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4992 napi_complete(napi); 5028 napi_complete(napi);
4993 /* Reenable interrupts. */ 5029 /* Reenable interrupts. */
4994 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); 5030 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
@@ -5260,7 +5296,8 @@ static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5260 5296
5261 err = tg3_init_hw(tp, reset_phy); 5297 err = tg3_init_hw(tp, reset_phy);
5262 if (err) { 5298 if (err) {
5263 netdev_err(tp->dev, "Failed to re-initialize device, aborting\n"); 5299 netdev_err(tp->dev,
5300 "Failed to re-initialize device, aborting\n");
5264 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 5301 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5265 tg3_full_unlock(tp); 5302 tg3_full_unlock(tp);
5266 del_timer_sync(&tp->timer); 5303 del_timer_sync(&tp->timer);
@@ -5437,12 +5474,12 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5437 len = skb_shinfo(skb)->frags[i-1].size; 5474 len = skb_shinfo(skb)->frags[i-1].size;
5438 5475
5439 pci_unmap_single(tp->pdev, 5476 pci_unmap_single(tp->pdev,
5440 pci_unmap_addr(&tnapi->tx_buffers[entry], 5477 dma_unmap_addr(&tnapi->tx_buffers[entry],
5441 mapping), 5478 mapping),
5442 len, PCI_DMA_TODEVICE); 5479 len, PCI_DMA_TODEVICE);
5443 if (i == 0) { 5480 if (i == 0) {
5444 tnapi->tx_buffers[entry].skb = new_skb; 5481 tnapi->tx_buffers[entry].skb = new_skb;
5445 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, 5482 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5446 new_addr); 5483 new_addr);
5447 } else { 5484 } else {
5448 tnapi->tx_buffers[entry].skb = NULL; 5485 tnapi->tx_buffers[entry].skb = NULL;
@@ -5492,7 +5529,6 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5492 struct netdev_queue *txq; 5529 struct netdev_queue *txq;
5493 unsigned int i, last; 5530 unsigned int i, last;
5494 5531
5495
5496 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 5532 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5497 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 5533 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5498 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 5534 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -5508,7 +5544,8 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5508 netif_tx_stop_queue(txq); 5544 netif_tx_stop_queue(txq);
5509 5545
5510 /* This is a hard error, log it. */ 5546 /* This is a hard error, log it. */
5511 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 5547 netdev_err(dev,
5548 "BUG! Tx Ring full when queue awake!\n");
5512 } 5549 }
5513 return NETDEV_TX_BUSY; 5550 return NETDEV_TX_BUSY;
5514 } 5551 }
@@ -5552,9 +5589,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5552 5589
5553 tcp_hdr(skb)->check = 0; 5590 tcp_hdr(skb)->check = 0;
5554 5591
5555 } 5592 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5556 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5557 base_flags |= TXD_FLAG_TCPUDP_CSUM; 5593 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5594 }
5595
5558#if TG3_VLAN_TAG_USED 5596#if TG3_VLAN_TAG_USED
5559 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) 5597 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5560 base_flags |= (TXD_FLAG_VLAN | 5598 base_flags |= (TXD_FLAG_VLAN |
@@ -5571,7 +5609,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5571 } 5609 }
5572 5610
5573 tnapi->tx_buffers[entry].skb = skb; 5611 tnapi->tx_buffers[entry].skb = skb;
5574 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); 5612 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5575 5613
5576 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && 5614 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5577 !mss && skb->len > ETH_DATA_LEN) 5615 !mss && skb->len > ETH_DATA_LEN)
@@ -5597,7 +5635,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5597 goto dma_error; 5635 goto dma_error;
5598 5636
5599 tnapi->tx_buffers[entry].skb = NULL; 5637 tnapi->tx_buffers[entry].skb = NULL;
5600 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, 5638 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5601 mapping); 5639 mapping);
5602 5640
5603 tg3_set_txd(tnapi, entry, mapping, len, 5641 tg3_set_txd(tnapi, entry, mapping, len,
@@ -5627,7 +5665,7 @@ dma_error:
5627 entry = tnapi->tx_prod; 5665 entry = tnapi->tx_prod;
5628 tnapi->tx_buffers[entry].skb = NULL; 5666 tnapi->tx_buffers[entry].skb = NULL;
5629 pci_unmap_single(tp->pdev, 5667 pci_unmap_single(tp->pdev,
5630 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping), 5668 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5631 skb_headlen(skb), 5669 skb_headlen(skb),
5632 PCI_DMA_TODEVICE); 5670 PCI_DMA_TODEVICE);
5633 for (i = 0; i <= last; i++) { 5671 for (i = 0; i <= last; i++) {
@@ -5635,7 +5673,7 @@ dma_error:
5635 entry = NEXT_TX(entry); 5673 entry = NEXT_TX(entry);
5636 5674
5637 pci_unmap_page(tp->pdev, 5675 pci_unmap_page(tp->pdev,
5638 pci_unmap_addr(&tnapi->tx_buffers[entry], 5676 dma_unmap_addr(&tnapi->tx_buffers[entry],
5639 mapping), 5677 mapping),
5640 frag->size, PCI_DMA_TODEVICE); 5678 frag->size, PCI_DMA_TODEVICE);
5641 } 5679 }
@@ -5695,7 +5733,6 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5695 struct netdev_queue *txq; 5733 struct netdev_queue *txq;
5696 unsigned int i, last; 5734 unsigned int i, last;
5697 5735
5698
5699 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 5736 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5700 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; 5737 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5701 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) 5738 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -5711,7 +5748,8 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5711 netif_tx_stop_queue(txq); 5748 netif_tx_stop_queue(txq);
5712 5749
5713 /* This is a hard error, log it. */ 5750 /* This is a hard error, log it. */
5714 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 5751 netdev_err(dev,
5752 "BUG! Tx Ring full when queue awake!\n");
5715 } 5753 }
5716 return NETDEV_TX_BUSY; 5754 return NETDEV_TX_BUSY;
5717 } 5755 }
@@ -5737,7 +5775,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5737 hdr_len = ip_tcp_len + tcp_opt_len; 5775 hdr_len = ip_tcp_len + tcp_opt_len;
5738 if (unlikely((ETH_HLEN + hdr_len) > 80) && 5776 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5739 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) 5777 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5740 return (tg3_tso_bug(tp, skb)); 5778 return tg3_tso_bug(tp, skb);
5741 5779
5742 base_flags |= (TXD_FLAG_CPU_PRE_DMA | 5780 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5743 TXD_FLAG_CPU_POST_DMA); 5781 TXD_FLAG_CPU_POST_DMA);
@@ -5797,7 +5835,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5797 } 5835 }
5798 5836
5799 tnapi->tx_buffers[entry].skb = skb; 5837 tnapi->tx_buffers[entry].skb = skb;
5800 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); 5838 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5801 5839
5802 would_hit_hwbug = 0; 5840 would_hit_hwbug = 0;
5803 5841
@@ -5833,7 +5871,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5833 len, PCI_DMA_TODEVICE); 5871 len, PCI_DMA_TODEVICE);
5834 5872
5835 tnapi->tx_buffers[entry].skb = NULL; 5873 tnapi->tx_buffers[entry].skb = NULL;
5836 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, 5874 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5837 mapping); 5875 mapping);
5838 if (pci_dma_mapping_error(tp->pdev, mapping)) 5876 if (pci_dma_mapping_error(tp->pdev, mapping))
5839 goto dma_error; 5877 goto dma_error;
@@ -5898,7 +5936,7 @@ dma_error:
5898 entry = tnapi->tx_prod; 5936 entry = tnapi->tx_prod;
5899 tnapi->tx_buffers[entry].skb = NULL; 5937 tnapi->tx_buffers[entry].skb = NULL;
5900 pci_unmap_single(tp->pdev, 5938 pci_unmap_single(tp->pdev,
5901 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping), 5939 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5902 skb_headlen(skb), 5940 skb_headlen(skb),
5903 PCI_DMA_TODEVICE); 5941 PCI_DMA_TODEVICE);
5904 for (i = 0; i <= last; i++) { 5942 for (i = 0; i <= last; i++) {
@@ -5906,7 +5944,7 @@ dma_error:
5906 entry = NEXT_TX(entry); 5944 entry = NEXT_TX(entry);
5907 5945
5908 pci_unmap_page(tp->pdev, 5946 pci_unmap_page(tp->pdev,
5909 pci_unmap_addr(&tnapi->tx_buffers[entry], 5947 dma_unmap_addr(&tnapi->tx_buffers[entry],
5910 mapping), 5948 mapping),
5911 frag->size, PCI_DMA_TODEVICE); 5949 frag->size, PCI_DMA_TODEVICE);
5912 } 5950 }
@@ -5924,9 +5962,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5924 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 5962 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5925 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; 5963 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5926 ethtool_op_set_tso(dev, 0); 5964 ethtool_op_set_tso(dev, 0);
5927 } 5965 } else {
5928 else
5929 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; 5966 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5967 }
5930 } else { 5968 } else {
5931 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) 5969 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5932 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; 5970 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
@@ -6007,7 +6045,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
6007 } 6045 }
6008} 6046}
6009 6047
6010/* Initialize tx/rx rings for packet processing. 6048/* Initialize rx rings for packet processing.
6011 * 6049 *
6012 * The chip has been shut down and the driver detached from 6050 * The chip has been shut down and the driver detached from
6013 * the networking, so no interrupts or new tx packets will 6051 * the networking, so no interrupts or new tx packets will
@@ -6058,8 +6096,10 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
6058 /* Now allocate fresh SKBs for each rx ring. */ 6096 /* Now allocate fresh SKBs for each rx ring. */
6059 for (i = 0; i < tp->rx_pending; i++) { 6097 for (i = 0; i < tp->rx_pending; i++) {
6060 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { 6098 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6061 netdev_warn(tp->dev, "Using a smaller RX standard ring, only %d out of %d buffers were allocated successfully\n", 6099 netdev_warn(tp->dev,
6062 i, tp->rx_pending); 6100 "Using a smaller RX standard ring. Only "
6101 "%d out of %d buffers were allocated "
6102 "successfully\n", i, tp->rx_pending);
6063 if (i == 0) 6103 if (i == 0)
6064 goto initfail; 6104 goto initfail;
6065 tp->rx_pending = i; 6105 tp->rx_pending = i;
@@ -6088,8 +6128,10 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
6088 6128
6089 for (i = 0; i < tp->rx_jumbo_pending; i++) { 6129 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6090 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { 6130 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6091 netdev_warn(tp->dev, "Using a smaller RX jumbo ring, only %d out of %d buffers were allocated successfully\n", 6131 netdev_warn(tp->dev,
6092 i, tp->rx_jumbo_pending); 6132 "Using a smaller RX jumbo ring. Only %d "
6133 "out of %d buffers were allocated "
6134 "successfully\n", i, tp->rx_jumbo_pending);
6093 if (i == 0) 6135 if (i == 0)
6094 goto initfail; 6136 goto initfail;
6095 tp->rx_jumbo_pending = i; 6137 tp->rx_jumbo_pending = i;
@@ -6187,7 +6229,7 @@ static void tg3_free_rings(struct tg3 *tp)
6187 } 6229 }
6188 6230
6189 pci_unmap_single(tp->pdev, 6231 pci_unmap_single(tp->pdev,
6190 pci_unmap_addr(txp, mapping), 6232 dma_unmap_addr(txp, mapping),
6191 skb_headlen(skb), 6233 skb_headlen(skb),
6192 PCI_DMA_TODEVICE); 6234 PCI_DMA_TODEVICE);
6193 txp->skb = NULL; 6235 txp->skb = NULL;
@@ -6197,7 +6239,7 @@ static void tg3_free_rings(struct tg3 *tp)
6197 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { 6239 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6198 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; 6240 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6199 pci_unmap_page(tp->pdev, 6241 pci_unmap_page(tp->pdev,
6200 pci_unmap_addr(txp, mapping), 6242 dma_unmap_addr(txp, mapping),
6201 skb_shinfo(skb)->frags[k].size, 6243 skb_shinfo(skb)->frags[k].size,
6202 PCI_DMA_TODEVICE); 6244 PCI_DMA_TODEVICE);
6203 i++; 6245 i++;
@@ -6433,8 +6475,9 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
6433 } 6475 }
6434 6476
6435 if (i == MAX_WAIT_CNT && !silent) { 6477 if (i == MAX_WAIT_CNT && !silent) {
6436 pr_err("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", 6478 dev_err(&tp->pdev->dev,
6437 ofs, enable_bit); 6479 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6480 ofs, enable_bit);
6438 return -ENODEV; 6481 return -ENODEV;
6439 } 6482 }
6440 6483
@@ -6480,8 +6523,9 @@ static int tg3_abort_hw(struct tg3 *tp, int silent)
6480 break; 6523 break;
6481 } 6524 }
6482 if (i >= MAX_WAIT_CNT) { 6525 if (i >= MAX_WAIT_CNT) {
6483 netdev_err(tp->dev, "%s timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n", 6526 dev_err(&tp->pdev->dev,
6484 __func__, tr32(MAC_TX_MODE)); 6527 "%s timed out, TX_MODE_ENABLE will not clear "
6528 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6485 err |= -ENODEV; 6529 err |= -ENODEV;
6486 } 6530 }
6487 6531
@@ -6551,35 +6595,35 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6551 return; 6595 return;
6552 6596
6553 switch (kind) { 6597 switch (kind) {
6554 case RESET_KIND_INIT: 6598 case RESET_KIND_INIT:
6555 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 6599 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6556 APE_HOST_SEG_SIG_MAGIC); 6600 APE_HOST_SEG_SIG_MAGIC);
6557 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, 6601 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6558 APE_HOST_SEG_LEN_MAGIC); 6602 APE_HOST_SEG_LEN_MAGIC);
6559 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); 6603 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6560 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); 6604 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6561 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, 6605 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6562 APE_HOST_DRIVER_ID_MAGIC); 6606 APE_HOST_DRIVER_ID_MAGIC);
6563 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, 6607 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6564 APE_HOST_BEHAV_NO_PHYLOCK); 6608 APE_HOST_BEHAV_NO_PHYLOCK);
6565 6609
6566 event = APE_EVENT_STATUS_STATE_START; 6610 event = APE_EVENT_STATUS_STATE_START;
6567 break; 6611 break;
6568 case RESET_KIND_SHUTDOWN: 6612 case RESET_KIND_SHUTDOWN:
6569 /* With the interface we are currently using, 6613 /* With the interface we are currently using,
6570 * APE does not track driver state. Wiping 6614 * APE does not track driver state. Wiping
6571 * out the HOST SEGMENT SIGNATURE forces 6615 * out the HOST SEGMENT SIGNATURE forces
6572 * the APE to assume OS absent status. 6616 * the APE to assume OS absent status.
6573 */ 6617 */
6574 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); 6618 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6575 6619
6576 event = APE_EVENT_STATUS_STATE_UNLOAD; 6620 event = APE_EVENT_STATUS_STATE_UNLOAD;
6577 break; 6621 break;
6578 case RESET_KIND_SUSPEND: 6622 case RESET_KIND_SUSPEND:
6579 event = APE_EVENT_STATUS_STATE_SUSPEND; 6623 event = APE_EVENT_STATUS_STATE_SUSPEND;
6580 break; 6624 break;
6581 default: 6625 default:
6582 return; 6626 return;
6583 } 6627 }
6584 6628
6585 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; 6629 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
@@ -7156,7 +7200,8 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
7156 7200
7157 if (cpu_base == TX_CPU_BASE && 7201 if (cpu_base == TX_CPU_BASE &&
7158 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 7202 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7159 netdev_err(tp->dev, "%s: Trying to load TX cpu firmware which is 5705\n", 7203 netdev_err(tp->dev,
7204 "%s: Trying to load TX cpu firmware which is 5705\n",
7160 __func__); 7205 __func__);
7161 return -EINVAL; 7206 return -EINVAL;
7162 } 7207 }
@@ -7236,7 +7281,8 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7236 udelay(1000); 7281 udelay(1000);
7237 } 7282 }
7238 if (i >= 5) { 7283 if (i >= 5) {
7239 netdev_err(tp->dev, "tg3_load_firmware fails to set RX CPU PC, is %08x should be %08x\n", 7284 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7285 "should be %08x\n", __func__,
7240 tr32(RX_CPU_BASE + CPU_PC), info.fw_base); 7286 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7241 return -ENODEV; 7287 return -ENODEV;
7242 } 7288 }
@@ -7300,7 +7346,8 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
7300 udelay(1000); 7346 udelay(1000);
7301 } 7347 }
7302 if (i >= 5) { 7348 if (i >= 5) {
7303 netdev_err(tp->dev, "%s fails to set CPU PC, is %08x should be %08x\n", 7349 netdev_err(tp->dev,
7350 "%s fails to set CPU PC, is %08x should be %08x\n",
7304 __func__, tr32(cpu_base + CPU_PC), info.fw_base); 7351 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7305 return -ENODEV; 7352 return -ENODEV;
7306 } 7353 }
@@ -7568,9 +7615,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7568 7615
7569 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); 7616 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7570 7617
7571 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { 7618 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7572 tg3_abort_hw(tp, 1); 7619 tg3_abort_hw(tp, 1);
7573 }
7574 7620
7575 if (reset_phy) 7621 if (reset_phy)
7576 tg3_phy_reset(tp); 7622 tg3_phy_reset(tp);
@@ -7631,6 +7677,25 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7631 tw32(GRC_MODE, grc_mode); 7677 tw32(GRC_MODE, grc_mode);
7632 } 7678 }
7633 7679
7680 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7681 u32 grc_mode = tr32(GRC_MODE);
7682
7683 /* Access the lower 1K of PL PCIE block registers. */
7684 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7685 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7686
7687 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7688 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7689 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7690
7691 tw32(GRC_MODE, grc_mode);
7692
7693 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7694 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7695 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7696 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7697 }
7698
7634 /* This works around an issue with Athlon chipsets on 7699 /* This works around an issue with Athlon chipsets on
7635 * B3 tigon3 silicon. This bit has no effect on any 7700 * B3 tigon3 silicon. This bit has no effect on any
7636 * other revision. But do not set this on PCI Express 7701 * other revision. But do not set this on PCI Express
@@ -7679,6 +7744,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7679 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { 7744 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7680 val = tr32(TG3PCI_DMA_RW_CTRL) & 7745 val = tr32(TG3PCI_DMA_RW_CTRL) &
7681 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; 7746 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7747 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7748 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7682 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); 7749 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7683 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && 7750 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7684 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { 7751 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
@@ -7723,8 +7790,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7723 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); 7790 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7724 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); 7791 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7725 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); 7792 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7726 } 7793 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7727 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7728 int fw_len; 7794 int fw_len;
7729 7795
7730 fw_len = tp->fw_len; 7796 fw_len = tp->fw_len;
@@ -7839,9 +7905,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 7905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 7906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7841 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) | 7907 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7842 (RX_STD_MAX_SIZE << 2); 7908 (TG3_RX_STD_DMA_SZ << 2);
7843 else 7909 else
7844 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT; 7910 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7845 } else 7911 } else
7846 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT; 7912 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7847 7913
@@ -8476,8 +8542,8 @@ static void tg3_timer(unsigned long __opaque)
8476 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, 8542 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8477 FWCMD_NICDRV_ALIVE3); 8543 FWCMD_NICDRV_ALIVE3);
8478 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); 8544 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8479 /* 5 seconds timeout */ 8545 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8480 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); 8546 TG3_FW_UPDATE_TIMEOUT_SEC);
8481 8547
8482 tg3_generate_fw_event(tp); 8548 tg3_generate_fw_event(tp);
8483 } 8549 }
@@ -8625,8 +8691,9 @@ static int tg3_test_msi(struct tg3 *tp)
8625 return err; 8691 return err;
8626 8692
8627 /* MSI test failed, go back to INTx mode */ 8693 /* MSI test failed, go back to INTx mode */
8628 netdev_warn(tp->dev, "No interrupt was generated using MSI, switching to INTx mode\n" 8694 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8629 "Please report this failure to the PCI maintainer and include system chipset information\n"); 8695 "to INTx mode. Please report this failure to the PCI "
8696 "maintainer and include system chipset information\n");
8630 8697
8631 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); 8698 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8632 8699
@@ -8739,7 +8806,8 @@ static void tg3_ints_init(struct tg3 *tp)
8739 /* All MSI supporting chips should support tagged 8806 /* All MSI supporting chips should support tagged
8740 * status. Assert that this is the case. 8807 * status. Assert that this is the case.
8741 */ 8808 */
8742 netdev_warn(tp->dev, "MSI without TAGGED? Not using MSI\n"); 8809 netdev_warn(tp->dev,
8810 "MSI without TAGGED_STATUS? Not using MSI\n");
8743 goto defcfg; 8811 goto defcfg;
8744 } 8812 }
8745 8813
@@ -8914,236 +8982,6 @@ err_out1:
8914 return err; 8982 return err;
8915} 8983}
8916 8984
8917#if 0
8918/*static*/ void tg3_dump_state(struct tg3 *tp)
8919{
8920 u32 val32, val32_2, val32_3, val32_4, val32_5;
8921 u16 val16;
8922 int i;
8923 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8924
8925 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8926 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8927 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8928 val16, val32);
8929
8930 /* MAC block */
8931 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8932 tr32(MAC_MODE), tr32(MAC_STATUS));
8933 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8934 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8935 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8936 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8937 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8938 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8939
8940 /* Send data initiator control block */
8941 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8942 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8943 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8944 tr32(SNDDATAI_STATSCTRL));
8945
8946 /* Send data completion control block */
8947 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8948
8949 /* Send BD ring selector block */
8950 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8951 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8952
8953 /* Send BD initiator control block */
8954 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8955 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8956
8957 /* Send BD completion control block */
8958 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8959
8960 /* Receive list placement control block */
8961 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8962 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8963 printk(" RCVLPC_STATSCTRL[%08x]\n",
8964 tr32(RCVLPC_STATSCTRL));
8965
8966 /* Receive data and receive BD initiator control block */
8967 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8968 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8969
8970 /* Receive data completion control block */
8971 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8972 tr32(RCVDCC_MODE));
8973
8974 /* Receive BD initiator control block */
8975 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8976 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8977
8978 /* Receive BD completion control block */
8979 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8980 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8981
8982 /* Receive list selector control block */
8983 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8984 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8985
8986 /* Mbuf cluster free block */
8987 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8988 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8989
8990 /* Host coalescing control block */
8991 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8992 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8993 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8994 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8995 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8996 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8997 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8998 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8999 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9000 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9001 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9002 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9003
9004 /* Memory arbiter control block */
9005 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9006 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9007
9008 /* Buffer manager control block */
9009 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9010 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9011 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9012 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9013 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9014 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9015 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9016 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9017
9018 /* Read DMA control block */
9019 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9020 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9021
9022 /* Write DMA control block */
9023 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9024 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9025
9026 /* DMA completion block */
9027 printk("DEBUG: DMAC_MODE[%08x]\n",
9028 tr32(DMAC_MODE));
9029
9030 /* GRC block */
9031 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9032 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9033 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9034 tr32(GRC_LOCAL_CTRL));
9035
9036 /* TG3_BDINFOs */
9037 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9038 tr32(RCVDBDI_JUMBO_BD + 0x0),
9039 tr32(RCVDBDI_JUMBO_BD + 0x4),
9040 tr32(RCVDBDI_JUMBO_BD + 0x8),
9041 tr32(RCVDBDI_JUMBO_BD + 0xc));
9042 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9043 tr32(RCVDBDI_STD_BD + 0x0),
9044 tr32(RCVDBDI_STD_BD + 0x4),
9045 tr32(RCVDBDI_STD_BD + 0x8),
9046 tr32(RCVDBDI_STD_BD + 0xc));
9047 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9048 tr32(RCVDBDI_MINI_BD + 0x0),
9049 tr32(RCVDBDI_MINI_BD + 0x4),
9050 tr32(RCVDBDI_MINI_BD + 0x8),
9051 tr32(RCVDBDI_MINI_BD + 0xc));
9052
9053 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9054 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9055 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9056 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9057 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9058 val32, val32_2, val32_3, val32_4);
9059
9060 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9061 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9062 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9063 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9064 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9065 val32, val32_2, val32_3, val32_4);
9066
9067 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9068 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9069 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9070 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9071 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9072 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9073 val32, val32_2, val32_3, val32_4, val32_5);
9074
9075 /* SW status block */
9076 printk(KERN_DEBUG
9077 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9078 sblk->status,
9079 sblk->status_tag,
9080 sblk->rx_jumbo_consumer,
9081 sblk->rx_consumer,
9082 sblk->rx_mini_consumer,
9083 sblk->idx[0].rx_producer,
9084 sblk->idx[0].tx_consumer);
9085
9086 /* SW statistics block */
9087 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9088 ((u32 *)tp->hw_stats)[0],
9089 ((u32 *)tp->hw_stats)[1],
9090 ((u32 *)tp->hw_stats)[2],
9091 ((u32 *)tp->hw_stats)[3]);
9092
9093 /* Mailboxes */
9094 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9095 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9096 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9097 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9098 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9099
9100 /* NIC side send descriptors. */
9101 for (i = 0; i < 6; i++) {
9102 unsigned long txd;
9103
9104 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9105 + (i * sizeof(struct tg3_tx_buffer_desc));
9106 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9107 i,
9108 readl(txd + 0x0), readl(txd + 0x4),
9109 readl(txd + 0x8), readl(txd + 0xc));
9110 }
9111
9112 /* NIC side RX descriptors. */
9113 for (i = 0; i < 6; i++) {
9114 unsigned long rxd;
9115
9116 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9117 + (i * sizeof(struct tg3_rx_buffer_desc));
9118 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9119 i,
9120 readl(rxd + 0x0), readl(rxd + 0x4),
9121 readl(rxd + 0x8), readl(rxd + 0xc));
9122 rxd += (4 * sizeof(u32));
9123 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9124 i,
9125 readl(rxd + 0x0), readl(rxd + 0x4),
9126 readl(rxd + 0x8), readl(rxd + 0xc));
9127 }
9128
9129 for (i = 0; i < 6; i++) {
9130 unsigned long rxd;
9131
9132 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9133 + (i * sizeof(struct tg3_rx_buffer_desc));
9134 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9135 i,
9136 readl(rxd + 0x0), readl(rxd + 0x4),
9137 readl(rxd + 0x8), readl(rxd + 0xc));
9138 rxd += (4 * sizeof(u32));
9139 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9140 i,
9141 readl(rxd + 0x0), readl(rxd + 0x4),
9142 readl(rxd + 0x8), readl(rxd + 0xc));
9143 }
9144}
9145#endif
9146
9147static struct net_device_stats *tg3_get_stats(struct net_device *); 8985static struct net_device_stats *tg3_get_stats(struct net_device *);
9148static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); 8986static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9149 8987
@@ -9162,9 +9000,6 @@ static int tg3_close(struct net_device *dev)
9162 tg3_phy_stop(tp); 9000 tg3_phy_stop(tp);
9163 9001
9164 tg3_full_lock(tp, 1); 9002 tg3_full_lock(tp, 1);
9165#if 0
9166 tg3_dump_state(tp);
9167#endif
9168 9003
9169 tg3_disable_ints(tp); 9004 tg3_disable_ints(tp);
9170 9005
@@ -9406,9 +9241,8 @@ static inline u32 calc_crc(unsigned char *buf, int len)
9406 9241
9407 reg >>= 1; 9242 reg >>= 1;
9408 9243
9409 if (tmp) { 9244 if (tmp)
9410 reg ^= 0xedb88320; 9245 reg ^= 0xedb88320;
9411 }
9412 } 9246 }
9413 } 9247 }
9414 9248
@@ -9452,20 +9286,20 @@ static void __tg3_set_rx_mode(struct net_device *dev)
9452 rx_mode |= RX_MODE_PROMISC; 9286 rx_mode |= RX_MODE_PROMISC;
9453 } else if (dev->flags & IFF_ALLMULTI) { 9287 } else if (dev->flags & IFF_ALLMULTI) {
9454 /* Accept all multicast. */ 9288 /* Accept all multicast. */
9455 tg3_set_multi (tp, 1); 9289 tg3_set_multi(tp, 1);
9456 } else if (netdev_mc_empty(dev)) { 9290 } else if (netdev_mc_empty(dev)) {
9457 /* Reject all multicast. */ 9291 /* Reject all multicast. */
9458 tg3_set_multi (tp, 0); 9292 tg3_set_multi(tp, 0);
9459 } else { 9293 } else {
9460 /* Accept one or more multicast(s). */ 9294 /* Accept one or more multicast(s). */
9461 struct dev_mc_list *mclist; 9295 struct netdev_hw_addr *ha;
9462 u32 mc_filter[4] = { 0, }; 9296 u32 mc_filter[4] = { 0, };
9463 u32 regidx; 9297 u32 regidx;
9464 u32 bit; 9298 u32 bit;
9465 u32 crc; 9299 u32 crc;
9466 9300
9467 netdev_for_each_mc_addr(mclist, dev) { 9301 netdev_for_each_mc_addr(ha, dev) {
9468 crc = calc_crc (mclist->dmi_addr, ETH_ALEN); 9302 crc = calc_crc(ha->addr, ETH_ALEN);
9469 bit = ~crc & 0x7f; 9303 bit = ~crc & 0x7f;
9470 regidx = (bit & 0x60) >> 5; 9304 regidx = (bit & 0x60) >> 5;
9471 bit &= 0x1f; 9305 bit &= 0x1f;
@@ -9618,7 +9452,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
9618 memcpy(data, ((char*)&val) + b_offset, b_count); 9452 memcpy(data, ((char*)&val) + b_offset, b_count);
9619 len -= b_count; 9453 len -= b_count;
9620 offset += b_count; 9454 offset += b_count;
9621 eeprom->len += b_count; 9455 eeprom->len += b_count;
9622 } 9456 }
9623 9457
9624 /* read bytes upto the last 4 byte boundary */ 9458 /* read bytes upto the last 4 byte boundary */
@@ -10166,8 +10000,8 @@ static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10166 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { 10000 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10167 if (data != 0) 10001 if (data != 0)
10168 return -EINVAL; 10002 return -EINVAL;
10169 return 0; 10003 return 0;
10170 } 10004 }
10171 10005
10172 spin_lock_bh(&tp->lock); 10006 spin_lock_bh(&tp->lock);
10173 if (data) 10007 if (data)
@@ -10186,8 +10020,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10186 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { 10020 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10187 if (data != 0) 10021 if (data != 0)
10188 return -EINVAL; 10022 return -EINVAL;
10189 return 0; 10023 return 0;
10190 } 10024 }
10191 10025
10192 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) 10026 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10193 ethtool_op_set_tx_ipv6_csum(dev, data); 10027 ethtool_op_set_tx_ipv6_csum(dev, data);
@@ -10197,7 +10031,7 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10197 return 0; 10031 return 0;
10198} 10032}
10199 10033
10200static int tg3_get_sset_count (struct net_device *dev, int sset) 10034static int tg3_get_sset_count(struct net_device *dev, int sset)
10201{ 10035{
10202 switch (sset) { 10036 switch (sset) {
10203 case ETH_SS_TEST: 10037 case ETH_SS_TEST:
@@ -10209,7 +10043,7 @@ static int tg3_get_sset_count (struct net_device *dev, int sset)
10209 } 10043 }
10210} 10044}
10211 10045
10212static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf) 10046static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10213{ 10047{
10214 switch (stringset) { 10048 switch (stringset) {
10215 case ETH_SS_STATS: 10049 case ETH_SS_STATS:
@@ -10256,7 +10090,7 @@ static int tg3_phys_id(struct net_device *dev, u32 data)
10256 return 0; 10090 return 0;
10257} 10091}
10258 10092
10259static void tg3_get_ethtool_stats (struct net_device *dev, 10093static void tg3_get_ethtool_stats(struct net_device *dev,
10260 struct ethtool_stats *estats, u64 *tmp_stats) 10094 struct ethtool_stats *estats, u64 *tmp_stats)
10261{ 10095{
10262 struct tg3 *tp = netdev_priv(dev); 10096 struct tg3 *tp = netdev_priv(dev);
@@ -10362,8 +10196,7 @@ static int tg3_test_nvram(struct tg3 *tp)
10362 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) 10196 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10363 parity[k++] = buf8[i] & msk; 10197 parity[k++] = buf8[i] & msk;
10364 i++; 10198 i++;
10365 } 10199 } else if (i == 16) {
10366 else if (i == 16) {
10367 int l; 10200 int l;
10368 u8 msk; 10201 u8 msk;
10369 10202
@@ -10461,7 +10294,7 @@ static int tg3_test_registers(struct tg3 *tp)
10461 { MAC_ADDR_0_HIGH, 0x0000, 10294 { MAC_ADDR_0_HIGH, 0x0000,
10462 0x00000000, 0x0000ffff }, 10295 0x00000000, 0x0000ffff },
10463 { MAC_ADDR_0_LOW, 0x0000, 10296 { MAC_ADDR_0_LOW, 0x0000,
10464 0x00000000, 0xffffffff }, 10297 0x00000000, 0xffffffff },
10465 { MAC_RX_MTU_SIZE, 0x0000, 10298 { MAC_RX_MTU_SIZE, 0x0000,
10466 0x00000000, 0x0000ffff }, 10299 0x00000000, 0x0000ffff },
10467 { MAC_TX_MODE, 0x0000, 10300 { MAC_TX_MODE, 0x0000,
@@ -10649,7 +10482,8 @@ static int tg3_test_registers(struct tg3 *tp)
10649 10482
10650out: 10483out:
10651 if (netif_msg_hw(tp)) 10484 if (netif_msg_hw(tp))
10652 pr_err("Register test failed at offset %x\n", offset); 10485 netdev_err(tp->dev,
10486 "Register test failed at offset %x\n", offset);
10653 tw32(offset, save_val); 10487 tw32(offset, save_val);
10654 return -EIO; 10488 return -EIO;
10655} 10489}
@@ -10825,9 +10659,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10825 MII_TG3_EXT_CTRL_LNK3_LED_MODE); 10659 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10826 } 10660 }
10827 tw32(MAC_MODE, mac_mode); 10661 tw32(MAC_MODE, mac_mode);
10828 } 10662 } else {
10829 else
10830 return -EINVAL; 10663 return -EINVAL;
10664 }
10831 10665
10832 err = -EIO; 10666 err = -EIO;
10833 10667
@@ -10909,7 +10743,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10909 10743
10910 rx_skb = tpr->rx_std_buffers[desc_idx].skb; 10744 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10911 10745
10912 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); 10746 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10913 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); 10747 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10914 10748
10915 for (i = 14; i < tx_len; i++) { 10749 for (i = 14; i < tx_len; i++) {
@@ -11083,7 +10917,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11083 return phy_mii_ioctl(phydev, data, cmd); 10917 return phy_mii_ioctl(phydev, data, cmd);
11084 } 10918 }
11085 10919
11086 switch(cmd) { 10920 switch (cmd) {
11087 case SIOCGMIIPHY: 10921 case SIOCGMIIPHY:
11088 data->phy_id = tp->phy_addr; 10922 data->phy_id = tp->phy_addr;
11089 10923
@@ -11776,7 +11610,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
11776 tp->tg3_flags |= TG3_FLAG_NVRAM; 11610 tp->tg3_flags |= TG3_FLAG_NVRAM;
11777 11611
11778 if (tg3_nvram_lock(tp)) { 11612 if (tg3_nvram_lock(tp)) {
11779 netdev_warn(tp->dev, "Cannot get nvram lock, %s failed\n", 11613 netdev_warn(tp->dev,
11614 "Cannot get nvram lock, %s failed\n",
11780 __func__); 11615 __func__);
11781 return; 11616 return;
11782 } 11617 }
@@ -11895,7 +11730,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11895 if (ret) 11730 if (ret)
11896 break; 11731 break;
11897 11732
11898 page_off = offset & pagemask; 11733 page_off = offset & pagemask;
11899 size = pagesize; 11734 size = pagesize;
11900 if (len < size) 11735 if (len < size)
11901 size = len; 11736 size = len;
@@ -11923,7 +11758,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11923 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | 11758 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11924 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; 11759 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11925 11760
11926 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) 11761 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11927 break; 11762 break;
11928 11763
11929 /* Issue another write enable to start the write. */ 11764 /* Issue another write enable to start the write. */
@@ -11977,7 +11812,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11977 memcpy(&data, buf + i, 4); 11812 memcpy(&data, buf + i, 4);
11978 tw32(NVRAM_WRDATA, be32_to_cpu(data)); 11813 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11979 11814
11980 page_off = offset % tp->nvram_pagesize; 11815 page_off = offset % tp->nvram_pagesize;
11981 11816
11982 phy_addr = tg3_nvram_phys_addr(tp, offset); 11817 phy_addr = tg3_nvram_phys_addr(tp, offset);
11983 11818
@@ -11985,7 +11820,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11985 11820
11986 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; 11821 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11987 11822
11988 if ((page_off == 0) || (i == 0)) 11823 if (page_off == 0 || i == 0)
11989 nvram_cmd |= NVRAM_CMD_FIRST; 11824 nvram_cmd |= NVRAM_CMD_FIRST;
11990 if (page_off == (tp->nvram_pagesize - 4)) 11825 if (page_off == (tp->nvram_pagesize - 4))
11991 nvram_cmd |= NVRAM_CMD_LAST; 11826 nvram_cmd |= NVRAM_CMD_LAST;
@@ -12028,8 +11863,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12028 11863
12029 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { 11864 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12030 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); 11865 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12031 } 11866 } else {
12032 else {
12033 u32 grc_mode; 11867 u32 grc_mode;
12034 11868
12035 ret = tg3_nvram_lock(tp); 11869 ret = tg3_nvram_lock(tp);
@@ -12049,8 +11883,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12049 11883
12050 ret = tg3_nvram_write_block_buffered(tp, offset, len, 11884 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12051 buf); 11885 buf);
12052 } 11886 } else {
12053 else {
12054 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, 11887 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12055 buf); 11888 buf);
12056 } 11889 }
@@ -12545,11 +12378,11 @@ skip_phy_reset:
12545 return err; 12378 return err;
12546} 12379}
12547 12380
12548static void __devinit tg3_read_partno(struct tg3 *tp) 12381static void __devinit tg3_read_vpd(struct tg3 *tp)
12549{ 12382{
12550 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */ 12383 u8 vpd_data[TG3_NVM_VPD_LEN];
12551 unsigned int block_end, rosize, len; 12384 unsigned int block_end, rosize, len;
12552 int i = 0; 12385 int j, i = 0;
12553 u32 magic; 12386 u32 magic;
12554 12387
12555 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || 12388 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
@@ -12598,6 +12431,32 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
12598 if (block_end > TG3_NVM_VPD_LEN) 12431 if (block_end > TG3_NVM_VPD_LEN)
12599 goto out_not_found; 12432 goto out_not_found;
12600 12433
12434 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12435 PCI_VPD_RO_KEYWORD_MFR_ID);
12436 if (j > 0) {
12437 len = pci_vpd_info_field_size(&vpd_data[j]);
12438
12439 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12440 if (j + len > block_end || len != 4 ||
12441 memcmp(&vpd_data[j], "1028", 4))
12442 goto partno;
12443
12444 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12445 PCI_VPD_RO_KEYWORD_VENDOR0);
12446 if (j < 0)
12447 goto partno;
12448
12449 len = pci_vpd_info_field_size(&vpd_data[j]);
12450
12451 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12452 if (j + len > block_end)
12453 goto partno;
12454
12455 memcpy(tp->fw_ver, &vpd_data[j], len);
12456 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12457 }
12458
12459partno:
12601 i = pci_vpd_find_info_keyword(vpd_data, i, rosize, 12460 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12602 PCI_VPD_RO_KEYWORD_PARTNO); 12461 PCI_VPD_RO_KEYWORD_PARTNO);
12603 if (i < 0) 12462 if (i < 0)
@@ -12667,7 +12526,7 @@ static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12667static void __devinit tg3_read_bc_ver(struct tg3 *tp) 12526static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12668{ 12527{
12669 u32 val, offset, start, ver_offset; 12528 u32 val, offset, start, ver_offset;
12670 int i; 12529 int i, dst_off;
12671 bool newver = false; 12530 bool newver = false;
12672 12531
12673 if (tg3_nvram_read(tp, 0xc, &offset) || 12532 if (tg3_nvram_read(tp, 0xc, &offset) ||
@@ -12687,8 +12546,11 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12687 newver = true; 12546 newver = true;
12688 } 12547 }
12689 12548
12549 dst_off = strlen(tp->fw_ver);
12550
12690 if (newver) { 12551 if (newver) {
12691 if (tg3_nvram_read(tp, offset + 8, &ver_offset)) 12552 if (TG3_VER_SIZE - dst_off < 16 ||
12553 tg3_nvram_read(tp, offset + 8, &ver_offset))
12692 return; 12554 return;
12693 12555
12694 offset = offset + ver_offset - start; 12556 offset = offset + ver_offset - start;
@@ -12697,7 +12559,7 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12697 if (tg3_nvram_read_be32(tp, offset + i, &v)) 12559 if (tg3_nvram_read_be32(tp, offset + i, &v))
12698 return; 12560 return;
12699 12561
12700 memcpy(tp->fw_ver + i, &v, sizeof(v)); 12562 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12701 } 12563 }
12702 } else { 12564 } else {
12703 u32 major, minor; 12565 u32 major, minor;
@@ -12708,7 +12570,8 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12708 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> 12570 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12709 TG3_NVM_BCVER_MAJSFT; 12571 TG3_NVM_BCVER_MAJSFT;
12710 minor = ver_offset & TG3_NVM_BCVER_MINMSK; 12572 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12711 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor); 12573 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12574 "v%d.%02d", major, minor);
12712 } 12575 }
12713} 12576}
12714 12577
@@ -12732,9 +12595,7 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12732{ 12595{
12733 u32 offset, major, minor, build; 12596 u32 offset, major, minor, build;
12734 12597
12735 tp->fw_ver[0] = 's'; 12598 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12736 tp->fw_ver[1] = 'b';
12737 tp->fw_ver[2] = '\0';
12738 12599
12739 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) 12600 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12740 return; 12601 return;
@@ -12771,11 +12632,14 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12771 if (minor > 99 || build > 26) 12632 if (minor > 99 || build > 26)
12772 return; 12633 return;
12773 12634
12774 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor); 12635 offset = strlen(tp->fw_ver);
12636 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12637 " v%d.%02d", major, minor);
12775 12638
12776 if (build > 0) { 12639 if (build > 0) {
12777 tp->fw_ver[8] = 'a' + build - 1; 12640 offset = strlen(tp->fw_ver);
12778 tp->fw_ver[9] = '\0'; 12641 if (offset < TG3_VER_SIZE - 1)
12642 tp->fw_ver[offset] = 'a' + build - 1;
12779 } 12643 }
12780} 12644}
12781 12645
@@ -12862,12 +12726,13 @@ static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12862static void __devinit tg3_read_fw_ver(struct tg3 *tp) 12726static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12863{ 12727{
12864 u32 val; 12728 u32 val;
12729 bool vpd_vers = false;
12865 12730
12866 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { 12731 if (tp->fw_ver[0] != 0)
12867 tp->fw_ver[0] = 's'; 12732 vpd_vers = true;
12868 tp->fw_ver[1] = 'b';
12869 tp->fw_ver[2] = '\0';
12870 12733
12734 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12735 strcat(tp->fw_ver, "sb");
12871 return; 12736 return;
12872 } 12737 }
12873 12738
@@ -12884,11 +12749,12 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12884 return; 12749 return;
12885 12750
12886 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || 12751 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12887 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) 12752 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12888 return; 12753 goto done;
12889 12754
12890 tg3_read_mgmtfw_ver(tp); 12755 tg3_read_mgmtfw_ver(tp);
12891 12756
12757done:
12892 tp->fw_ver[TG3_VER_SIZE - 1] = 0; 12758 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12893} 12759}
12894 12760
@@ -12898,9 +12764,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12898{ 12764{
12899 static struct pci_device_id write_reorder_chipsets[] = { 12765 static struct pci_device_id write_reorder_chipsets[] = {
12900 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 12766 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12901 PCI_DEVICE_ID_AMD_FE_GATE_700C) }, 12767 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12902 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 12768 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12903 PCI_DEVICE_ID_AMD_8131_BRIDGE) }, 12769 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12904 { PCI_DEVICE(PCI_VENDOR_ID_VIA, 12770 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12905 PCI_DEVICE_ID_VIA_8385_0) }, 12771 PCI_DEVICE_ID_VIA_8385_0) },
12906 { }, 12772 { },
@@ -13066,8 +12932,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13066 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; 12932 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13067 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; 12933 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13068 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); 12934 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13069 } 12935 } else {
13070 else {
13071 struct pci_dev *bridge = NULL; 12936 struct pci_dev *bridge = NULL;
13072 12937
13073 do { 12938 do {
@@ -13129,6 +12994,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13129 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 12994 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13130 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) 12995 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13131 tp->dev->features |= NETIF_F_IPV6_CSUM; 12996 tp->dev->features |= NETIF_F_IPV6_CSUM;
12997 tp->dev->features |= NETIF_F_GRO;
13132 } 12998 }
13133 12999
13134 /* Determine TSO capabilities */ 13000 /* Determine TSO capabilities */
@@ -13189,8 +13055,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13189 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; 13055 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13190 13056
13191 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || 13057 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13192 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || 13058 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13193 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) 13059 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13194 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; 13060 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13195 13061
13196 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, 13062 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
@@ -13224,7 +13090,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13224 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 13090 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13225 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); 13091 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13226 if (!tp->pcix_cap) { 13092 if (!tp->pcix_cap) {
13227 pr_err("Cannot find PCI-X capability, aborting\n"); 13093 dev_err(&tp->pdev->dev,
13094 "Cannot find PCI-X capability, aborting\n");
13228 return -EIO; 13095 return -EIO;
13229 } 13096 }
13230 13097
@@ -13421,7 +13288,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13421 /* Force the chip into D0. */ 13288 /* Force the chip into D0. */
13422 err = tg3_set_power_state(tp, PCI_D0); 13289 err = tg3_set_power_state(tp, PCI_D0);
13423 if (err) { 13290 if (err) {
13424 pr_err("(%s) transition to D0 failed\n", pci_name(tp->pdev)); 13291 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13425 return err; 13292 return err;
13426 } 13293 }
13427 13294
@@ -13595,13 +13462,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13595 13462
13596 err = tg3_phy_probe(tp); 13463 err = tg3_phy_probe(tp);
13597 if (err) { 13464 if (err) {
13598 pr_err("(%s) phy probe failed, err %d\n", 13465 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13599 pci_name(tp->pdev), err);
13600 /* ... but do not return immediately ... */ 13466 /* ... but do not return immediately ... */
13601 tg3_mdio_fini(tp); 13467 tg3_mdio_fini(tp);
13602 } 13468 }
13603 13469
13604 tg3_read_partno(tp); 13470 tg3_read_vpd(tp);
13605 tg3_read_fw_ver(tp); 13471 tg3_read_fw_ver(tp);
13606 13472
13607 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { 13473 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
@@ -13639,10 +13505,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13639 else 13505 else
13640 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; 13506 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13641 13507
13642 tp->rx_offset = NET_IP_ALIGN; 13508 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13509 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13643 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && 13510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13644 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) 13511 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13645 tp->rx_offset = 0; 13512 tp->rx_offset -= NET_IP_ALIGN;
13513#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13514 tp->rx_copy_thresh = ~(u16)0;
13515#endif
13516 }
13646 13517
13647 tp->rx_std_max_post = TG3_RX_RING_SIZE; 13518 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13648 13519
@@ -13965,11 +13836,10 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
13965 } 13836 }
13966 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 13837 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13967 13838
13968 if (to_device) { 13839 if (to_device)
13969 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); 13840 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13970 } else { 13841 else
13971 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); 13842 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13972 }
13973 13843
13974 ret = -ENODEV; 13844 ret = -ENODEV;
13975 for (i = 0; i < 40; i++) { 13845 for (i = 0; i < 40; i++) {
@@ -14105,8 +13975,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14105 /* Send the buffer to the chip. */ 13975 /* Send the buffer to the chip. */
14106 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); 13976 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14107 if (ret) { 13977 if (ret) {
14108 pr_err("tg3_test_dma() Write the buffer failed %d\n", 13978 dev_err(&tp->pdev->dev,
14109 ret); 13979 "%s: Buffer write failed. err = %d\n",
13980 __func__, ret);
14110 break; 13981 break;
14111 } 13982 }
14112 13983
@@ -14116,8 +13987,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14116 u32 val; 13987 u32 val;
14117 tg3_read_mem(tp, 0x2100 + (i*4), &val); 13988 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14118 if (le32_to_cpu(val) != p[i]) { 13989 if (le32_to_cpu(val) != p[i]) {
14119 pr_err(" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", 13990 dev_err(&tp->pdev->dev,
14120 val, i); 13991 "%s: Buffer corrupted on device! "
13992 "(%d != %d)\n", __func__, val, i);
14121 /* ret = -ENODEV here? */ 13993 /* ret = -ENODEV here? */
14122 } 13994 }
14123 p[i] = 0; 13995 p[i] = 0;
@@ -14126,9 +13998,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14126 /* Now read it back. */ 13998 /* Now read it back. */
14127 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); 13999 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14128 if (ret) { 14000 if (ret) {
14129 pr_err("tg3_test_dma() Read the buffer failed %d\n", 14001 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14130 ret); 14002 "err = %d\n", __func__, ret);
14131
14132 break; 14003 break;
14133 } 14004 }
14134 14005
@@ -14144,8 +14015,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14144 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); 14015 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14145 break; 14016 break;
14146 } else { 14017 } else {
14147 pr_err("tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", 14018 dev_err(&tp->pdev->dev,
14148 p[i], i); 14019 "%s: Buffer corrupted on read back! "
14020 "(%d != %d)\n", __func__, p[i], i);
14149 ret = -ENODEV; 14021 ret = -ENODEV;
14150 goto out; 14022 goto out;
14151 } 14023 }
@@ -14172,10 +14044,10 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
14172 if (pci_dev_present(dma_wait_state_chipsets)) { 14044 if (pci_dev_present(dma_wait_state_chipsets)) {
14173 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; 14045 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14174 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; 14046 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14175 } 14047 } else {
14176 else
14177 /* Safe to use the calculated DMA boundary. */ 14048 /* Safe to use the calculated DMA boundary. */
14178 tp->dma_rwctrl = saved_dma_rwctrl; 14049 tp->dma_rwctrl = saved_dma_rwctrl;
14050 }
14179 14051
14180 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); 14052 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14181 } 14053 }
@@ -14437,13 +14309,13 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14437 14309
14438 err = pci_enable_device(pdev); 14310 err = pci_enable_device(pdev);
14439 if (err) { 14311 if (err) {
14440 pr_err("Cannot enable PCI device, aborting\n"); 14312 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14441 return err; 14313 return err;
14442 } 14314 }
14443 14315
14444 err = pci_request_regions(pdev, DRV_MODULE_NAME); 14316 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14445 if (err) { 14317 if (err) {
14446 pr_err("Cannot obtain PCI resources, aborting\n"); 14318 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14447 goto err_out_disable_pdev; 14319 goto err_out_disable_pdev;
14448 } 14320 }
14449 14321
@@ -14452,14 +14324,15 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14452 /* Find power-management capability. */ 14324 /* Find power-management capability. */
14453 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 14325 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14454 if (pm_cap == 0) { 14326 if (pm_cap == 0) {
14455 pr_err("Cannot find PowerManagement capability, aborting\n"); 14327 dev_err(&pdev->dev,
14328 "Cannot find Power Management capability, aborting\n");
14456 err = -EIO; 14329 err = -EIO;
14457 goto err_out_free_res; 14330 goto err_out_free_res;
14458 } 14331 }
14459 14332
14460 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); 14333 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14461 if (!dev) { 14334 if (!dev) {
14462 pr_err("Etherdev alloc failed, aborting\n"); 14335 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14463 err = -ENOMEM; 14336 err = -ENOMEM;
14464 goto err_out_free_res; 14337 goto err_out_free_res;
14465 } 14338 }
@@ -14509,7 +14382,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14509 14382
14510 tp->regs = pci_ioremap_bar(pdev, BAR_0); 14383 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14511 if (!tp->regs) { 14384 if (!tp->regs) {
14512 netdev_err(dev, "Cannot map device registers, aborting\n"); 14385 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14513 err = -ENOMEM; 14386 err = -ENOMEM;
14514 goto err_out_free_dev; 14387 goto err_out_free_dev;
14515 } 14388 }
@@ -14525,7 +14398,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14525 14398
14526 err = tg3_get_invariants(tp); 14399 err = tg3_get_invariants(tp);
14527 if (err) { 14400 if (err) {
14528 netdev_err(dev, "Problem fetching invariants of chip, aborting\n"); 14401 dev_err(&pdev->dev,
14402 "Problem fetching invariants of chip, aborting\n");
14529 goto err_out_iounmap; 14403 goto err_out_iounmap;
14530 } 14404 }
14531 14405
@@ -14560,7 +14434,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14560 err = pci_set_consistent_dma_mask(pdev, 14434 err = pci_set_consistent_dma_mask(pdev,
14561 persist_dma_mask); 14435 persist_dma_mask);
14562 if (err < 0) { 14436 if (err < 0) {
14563 netdev_err(dev, "Unable to obtain 64 bit DMA for consistent allocations\n"); 14437 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14438 "DMA for consistent allocations\n");
14564 goto err_out_iounmap; 14439 goto err_out_iounmap;
14565 } 14440 }
14566 } 14441 }
@@ -14568,7 +14443,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14568 if (err || dma_mask == DMA_BIT_MASK(32)) { 14443 if (err || dma_mask == DMA_BIT_MASK(32)) {
14569 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 14444 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14570 if (err) { 14445 if (err) {
14571 netdev_err(dev, "No usable DMA configuration, aborting\n"); 14446 dev_err(&pdev->dev,
14447 "No usable DMA configuration, aborting\n");
14572 goto err_out_iounmap; 14448 goto err_out_iounmap;
14573 } 14449 }
14574 } 14450 }
@@ -14617,14 +14493,16 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14617 14493
14618 err = tg3_get_device_address(tp); 14494 err = tg3_get_device_address(tp);
14619 if (err) { 14495 if (err) {
14620 netdev_err(dev, "Could not obtain valid ethernet address, aborting\n"); 14496 dev_err(&pdev->dev,
14497 "Could not obtain valid ethernet address, aborting\n");
14621 goto err_out_iounmap; 14498 goto err_out_iounmap;
14622 } 14499 }
14623 14500
14624 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { 14501 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14625 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); 14502 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14626 if (!tp->aperegs) { 14503 if (!tp->aperegs) {
14627 netdev_err(dev, "Cannot map APE registers, aborting\n"); 14504 dev_err(&pdev->dev,
14505 "Cannot map APE registers, aborting\n");
14628 err = -ENOMEM; 14506 err = -ENOMEM;
14629 goto err_out_iounmap; 14507 goto err_out_iounmap;
14630 } 14508 }
@@ -14648,7 +14526,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14648 14526
14649 err = tg3_test_dma(tp); 14527 err = tg3_test_dma(tp);
14650 if (err) { 14528 if (err) {
14651 netdev_err(dev, "DMA engine test failed, aborting\n"); 14529 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14652 goto err_out_apeunmap; 14530 goto err_out_apeunmap;
14653 } 14531 }
14654 14532
@@ -14709,7 +14587,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14709 14587
14710 err = register_netdev(dev); 14588 err = register_netdev(dev);
14711 if (err) { 14589 if (err) {
14712 netdev_err(dev, "Cannot register net device, aborting\n"); 14590 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14713 goto err_out_apeunmap; 14591 goto err_out_apeunmap;
14714 } 14592 }
14715 14593
@@ -14722,11 +14600,12 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
14722 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { 14600 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14723 struct phy_device *phydev; 14601 struct phy_device *phydev;
14724 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; 14602 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14725 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", 14603 netdev_info(dev,
14604 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14726 phydev->drv->name, dev_name(&phydev->dev)); 14605 phydev->drv->name, dev_name(&phydev->dev));
14727 } else 14606 } else
14728 netdev_info(dev, "attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n", 14607 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14729 tg3_phy_string(tp), 14608 "(WireSpeed[%d])\n", tg3_phy_string(tp),
14730 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : 14609 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14731 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" : 14610 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14732 "10/100/1000Base-T")), 14611 "10/100/1000Base-T")),
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 19:46:05 -0400