aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/stmmac/dwmac1000_core.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/stmmac/dwmac1000_core.c')
-rw-r--r--drivers/net/stmmac/dwmac1000_core.c41
1 files changed, 16 insertions, 25 deletions
diff --git a/drivers/net/stmmac/dwmac1000_core.c b/drivers/net/stmmac/dwmac1000_core.c
index 5bd95ebfe49..917b4e16923 100644
--- a/drivers/net/stmmac/dwmac1000_core.c
+++ b/drivers/net/stmmac/dwmac1000_core.c
@@ -48,7 +48,6 @@ static void dwmac1000_core_init(unsigned long ioaddr)
48 /* Tag detection without filtering */ 48 /* Tag detection without filtering */
49 writel(0x0, ioaddr + GMAC_VLAN_TAG); 49 writel(0x0, ioaddr + GMAC_VLAN_TAG);
50#endif 50#endif
51 return;
52} 51}
53 52
54static void dwmac1000_dump_regs(unsigned long ioaddr) 53static void dwmac1000_dump_regs(unsigned long ioaddr)
@@ -61,7 +60,6 @@ static void dwmac1000_dump_regs(unsigned long ioaddr)
61 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i, 60 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
62 offset, readl(ioaddr + offset)); 61 offset, readl(ioaddr + offset));
63 } 62 }
64 return;
65} 63}
66 64
67static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr, 65static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
@@ -83,8 +81,8 @@ static void dwmac1000_set_filter(struct net_device *dev)
83 unsigned long ioaddr = dev->base_addr; 81 unsigned long ioaddr = dev->base_addr;
84 unsigned int value = 0; 82 unsigned int value = 0;
85 83
86 DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n", 84 CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
87 __func__, netdev_mc_count(dev), netdev_uc_count(dev)); 85 __func__, netdev_mc_count(dev), netdev_uc_count(dev));
88 86
89 if (dev->flags & IFF_PROMISC) 87 if (dev->flags & IFF_PROMISC)
90 value = GMAC_FRAME_FILTER_PR; 88 value = GMAC_FRAME_FILTER_PR;
@@ -95,17 +93,17 @@ static void dwmac1000_set_filter(struct net_device *dev)
95 writel(0xffffffff, ioaddr + GMAC_HASH_LOW); 93 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
96 } else if (!netdev_mc_empty(dev)) { 94 } else if (!netdev_mc_empty(dev)) {
97 u32 mc_filter[2]; 95 u32 mc_filter[2];
98 struct dev_mc_list *mclist; 96 struct netdev_hw_addr *ha;
99 97
100 /* Hash filter for multicast */ 98 /* Hash filter for multicast */
101 value = GMAC_FRAME_FILTER_HMC; 99 value = GMAC_FRAME_FILTER_HMC;
102 100
103 memset(mc_filter, 0, sizeof(mc_filter)); 101 memset(mc_filter, 0, sizeof(mc_filter));
104 netdev_for_each_mc_addr(mclist, dev) { 102 netdev_for_each_mc_addr(ha, dev) {
105 /* The upper 6 bits of the calculated CRC are used to 103 /* The upper 6 bits of the calculated CRC are used to
106 index the contens of the hash table */ 104 index the contens of the hash table */
107 int bit_nr = 105 int bit_nr =
108 bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26; 106 bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
109 /* The most significant bit determines the register to 107 /* The most significant bit determines the register to
110 * use (H/L) while the other 5 bits determine the bit 108 * use (H/L) while the other 5 bits determine the bit
111 * within the register. */ 109 * within the register. */
@@ -136,11 +134,9 @@ static void dwmac1000_set_filter(struct net_device *dev)
136#endif 134#endif
137 writel(value, ioaddr + GMAC_FRAME_FILTER); 135 writel(value, ioaddr + GMAC_FRAME_FILTER);
138 136
139 DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: " 137 CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
140 "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER), 138 "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
141 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW)); 139 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
142
143 return;
144} 140}
145 141
146static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex, 142static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
@@ -148,23 +144,22 @@ static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
148{ 144{
149 unsigned int flow = 0; 145 unsigned int flow = 0;
150 146
151 DBG(KERN_DEBUG "GMAC Flow-Control:\n"); 147 CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
152 if (fc & FLOW_RX) { 148 if (fc & FLOW_RX) {
153 DBG(KERN_DEBUG "\tReceive Flow-Control ON\n"); 149 CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
154 flow |= GMAC_FLOW_CTRL_RFE; 150 flow |= GMAC_FLOW_CTRL_RFE;
155 } 151 }
156 if (fc & FLOW_TX) { 152 if (fc & FLOW_TX) {
157 DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n"); 153 CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
158 flow |= GMAC_FLOW_CTRL_TFE; 154 flow |= GMAC_FLOW_CTRL_TFE;
159 } 155 }
160 156
161 if (duplex) { 157 if (duplex) {
162 DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time); 158 CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
163 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT); 159 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
164 } 160 }
165 161
166 writel(flow, ioaddr + GMAC_FLOW_CTRL); 162 writel(flow, ioaddr + GMAC_FLOW_CTRL);
167 return;
168} 163}
169 164
170static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode) 165static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode)
@@ -172,15 +167,14 @@ static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode)
172 unsigned int pmt = 0; 167 unsigned int pmt = 0;
173 168
174 if (mode == WAKE_MAGIC) { 169 if (mode == WAKE_MAGIC) {
175 DBG(KERN_DEBUG "GMAC: WOL Magic frame\n"); 170 CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
176 pmt |= power_down | magic_pkt_en; 171 pmt |= power_down | magic_pkt_en;
177 } else if (mode == WAKE_UCAST) { 172 } else if (mode == WAKE_UCAST) {
178 DBG(KERN_DEBUG "GMAC: WOL on global unicast\n"); 173 CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
179 pmt |= global_unicast; 174 pmt |= global_unicast;
180 } 175 }
181 176
182 writel(pmt, ioaddr + GMAC_PMT); 177 writel(pmt, ioaddr + GMAC_PMT);
183 return;
184} 178}
185 179
186 180
@@ -190,22 +184,20 @@ static void dwmac1000_irq_status(unsigned long ioaddr)
190 184
191 /* Not used events (e.g. MMC interrupts) are not handled. */ 185 /* Not used events (e.g. MMC interrupts) are not handled. */
192 if ((intr_status & mmc_tx_irq)) 186 if ((intr_status & mmc_tx_irq))
193 DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n", 187 CHIP_DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
194 readl(ioaddr + GMAC_MMC_TX_INTR)); 188 readl(ioaddr + GMAC_MMC_TX_INTR));
195 if (unlikely(intr_status & mmc_rx_irq)) 189 if (unlikely(intr_status & mmc_rx_irq))
196 DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n", 190 CHIP_DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
197 readl(ioaddr + GMAC_MMC_RX_INTR)); 191 readl(ioaddr + GMAC_MMC_RX_INTR));
198 if (unlikely(intr_status & mmc_rx_csum_offload_irq)) 192 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
199 DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n", 193 CHIP_DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
200 readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD)); 194 readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
201 if (unlikely(intr_status & pmt_irq)) { 195 if (unlikely(intr_status & pmt_irq)) {
202 DBG(KERN_DEBUG "GMAC: received Magic frame\n"); 196 CHIP_DBG(KERN_DEBUG "GMAC: received Magic frame\n");
203 /* clear the PMT bits 5 and 6 by reading the PMT 197 /* clear the PMT bits 5 and 6 by reading the PMT
204 * status register. */ 198 * status register. */
205 readl(ioaddr + GMAC_PMT); 199 readl(ioaddr + GMAC_PMT);
206 } 200 }
207
208 return;
209} 201}
210 202
211struct stmmac_ops dwmac1000_ops = { 203struct stmmac_ops dwmac1000_ops = {
@@ -230,7 +222,6 @@ struct mac_device_info *dwmac1000_setup(unsigned long ioaddr)
230 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); 222 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
231 223
232 mac->mac = &dwmac1000_ops; 224 mac->mac = &dwmac1000_ops;
233 mac->desc = &dwmac1000_desc_ops;
234 mac->dma = &dwmac1000_dma_ops; 225 mac->dma = &dwmac1000_dma_ops;
235 226
236 mac->pmt = PMT_SUPPORTED; 227 mac->pmt = PMT_SUPPORTED;