diff options
Diffstat (limited to 'drivers/net/sfc')
-rw-r--r-- | drivers/net/sfc/Makefile | 2 | ||||
-rw-r--r-- | drivers/net/sfc/falcon.c | 117 | ||||
-rw-r--r-- | drivers/net/sfc/falcon_boards.c | 127 | ||||
-rw-r--r-- | drivers/net/sfc/falcon_gmac.c | 230 | ||||
-rw-r--r-- | drivers/net/sfc/mac.h | 1 | ||||
-rw-r--r-- | drivers/net/sfc/mdio_10g.c | 30 | ||||
-rw-r--r-- | drivers/net/sfc/net_driver.h | 2 | ||||
-rw-r--r-- | drivers/net/sfc/phy.h | 7 | ||||
-rw-r--r-- | drivers/net/sfc/tenxpress.c | 424 | ||||
-rw-r--r-- | drivers/net/sfc/workarounds.h | 9 |
10 files changed, 56 insertions, 893 deletions
diff --git a/drivers/net/sfc/Makefile b/drivers/net/sfc/Makefile index fd9272b5873..39f7c1bc240 100644 --- a/drivers/net/sfc/Makefile +++ b/drivers/net/sfc/Makefile | |||
@@ -1,5 +1,5 @@ | |||
1 | sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \ | 1 | sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \ |
2 | falcon_gmac.o falcon_xmac.o mcdi_mac.o \ | 2 | falcon_xmac.o mcdi_mac.o \ |
3 | selftest.o ethtool.o qt202x_phy.o mdio_10g.o \ | 3 | selftest.o ethtool.o qt202x_phy.o mdio_10g.o \ |
4 | tenxpress.o falcon_boards.o mcdi.o mcdi_phy.o | 4 | tenxpress.o falcon_boards.o mcdi.o mcdi_phy.o |
5 | sfc-$(CONFIG_SFC_MTD) += mtd.o | 5 | sfc-$(CONFIG_SFC_MTD) += mtd.o |
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c index b398a419804..254a599935c 100644 --- a/drivers/net/sfc/falcon.c +++ b/drivers/net/sfc/falcon.c | |||
@@ -446,30 +446,19 @@ static void falcon_reset_macs(struct efx_nic *efx) | |||
446 | /* It's not safe to use GLB_CTL_REG to reset the | 446 | /* It's not safe to use GLB_CTL_REG to reset the |
447 | * macs, so instead use the internal MAC resets | 447 | * macs, so instead use the internal MAC resets |
448 | */ | 448 | */ |
449 | if (!EFX_IS10G(efx)) { | 449 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
450 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); | 450 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
451 | efx_writeo(efx, ®, FR_AB_GM_CFG1); | 451 | |
452 | udelay(1000); | 452 | for (count = 0; count < 10000; count++) { |
453 | 453 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); | |
454 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); | 454 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == |
455 | efx_writeo(efx, ®, FR_AB_GM_CFG1); | 455 | 0) |
456 | udelay(1000); | 456 | return; |
457 | return; | 457 | udelay(10); |
458 | } else { | ||
459 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); | ||
460 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); | ||
461 | |||
462 | for (count = 0; count < 10000; count++) { | ||
463 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); | ||
464 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == | ||
465 | 0) | ||
466 | return; | ||
467 | udelay(10); | ||
468 | } | ||
469 | |||
470 | netif_err(efx, hw, efx->net_dev, | ||
471 | "timed out waiting for XMAC core reset\n"); | ||
472 | } | 458 | } |
459 | |||
460 | netif_err(efx, hw, efx->net_dev, | ||
461 | "timed out waiting for XMAC core reset\n"); | ||
473 | } | 462 | } |
474 | 463 | ||
475 | /* Mac stats will fail whist the TX fifo is draining */ | 464 | /* Mac stats will fail whist the TX fifo is draining */ |
@@ -508,7 +497,6 @@ static void falcon_reset_macs(struct efx_nic *efx) | |||
508 | * are re-enabled by the caller */ | 497 | * are re-enabled by the caller */ |
509 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | 498 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
510 | 499 | ||
511 | /* This can run even when the GMAC is selected */ | ||
512 | falcon_setup_xaui(efx); | 500 | falcon_setup_xaui(efx); |
513 | } | 501 | } |
514 | 502 | ||
@@ -646,8 +634,6 @@ static void falcon_stats_timer_func(unsigned long context) | |||
646 | spin_unlock(&efx->stats_lock); | 634 | spin_unlock(&efx->stats_lock); |
647 | } | 635 | } |
648 | 636 | ||
649 | static void falcon_switch_mac(struct efx_nic *efx); | ||
650 | |||
651 | static bool falcon_loopback_link_poll(struct efx_nic *efx) | 637 | static bool falcon_loopback_link_poll(struct efx_nic *efx) |
652 | { | 638 | { |
653 | struct efx_link_state old_state = efx->link_state; | 639 | struct efx_link_state old_state = efx->link_state; |
@@ -658,11 +644,7 @@ static bool falcon_loopback_link_poll(struct efx_nic *efx) | |||
658 | efx->link_state.fd = true; | 644 | efx->link_state.fd = true; |
659 | efx->link_state.fc = efx->wanted_fc; | 645 | efx->link_state.fc = efx->wanted_fc; |
660 | efx->link_state.up = true; | 646 | efx->link_state.up = true; |
661 | 647 | efx->link_state.speed = 10000; | |
662 | if (efx->loopback_mode == LOOPBACK_GMAC) | ||
663 | efx->link_state.speed = 1000; | ||
664 | else | ||
665 | efx->link_state.speed = 10000; | ||
666 | 648 | ||
667 | return !efx_link_state_equal(&efx->link_state, &old_state); | 649 | return !efx_link_state_equal(&efx->link_state, &old_state); |
668 | } | 650 | } |
@@ -685,7 +667,7 @@ static int falcon_reconfigure_port(struct efx_nic *efx) | |||
685 | falcon_stop_nic_stats(efx); | 667 | falcon_stop_nic_stats(efx); |
686 | falcon_deconfigure_mac_wrapper(efx); | 668 | falcon_deconfigure_mac_wrapper(efx); |
687 | 669 | ||
688 | falcon_switch_mac(efx); | 670 | falcon_reset_macs(efx); |
689 | 671 | ||
690 | efx->phy_op->reconfigure(efx); | 672 | efx->phy_op->reconfigure(efx); |
691 | rc = efx->mac_op->reconfigure(efx); | 673 | rc = efx->mac_op->reconfigure(efx); |
@@ -835,69 +817,16 @@ out: | |||
835 | return rc; | 817 | return rc; |
836 | } | 818 | } |
837 | 819 | ||
838 | static void falcon_clock_mac(struct efx_nic *efx) | ||
839 | { | ||
840 | unsigned strap_val; | ||
841 | efx_oword_t nic_stat; | ||
842 | |||
843 | /* Configure the NIC generated MAC clock correctly */ | ||
844 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | ||
845 | strap_val = EFX_IS10G(efx) ? 5 : 3; | ||
846 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | ||
847 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); | ||
848 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); | ||
849 | efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT); | ||
850 | } else { | ||
851 | /* Falcon A1 does not support 1G/10G speed switching | ||
852 | * and must not be used with a PHY that does. */ | ||
853 | BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) != | ||
854 | strap_val); | ||
855 | } | ||
856 | } | ||
857 | |||
858 | static void falcon_switch_mac(struct efx_nic *efx) | ||
859 | { | ||
860 | struct efx_mac_operations *old_mac_op = efx->mac_op; | ||
861 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
862 | unsigned int stats_done_offset; | ||
863 | |||
864 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | ||
865 | WARN_ON(nic_data->stats_disable_count == 0); | ||
866 | |||
867 | efx->mac_op = (EFX_IS10G(efx) ? | ||
868 | &falcon_xmac_operations : &falcon_gmac_operations); | ||
869 | |||
870 | if (EFX_IS10G(efx)) | ||
871 | stats_done_offset = XgDmaDone_offset; | ||
872 | else | ||
873 | stats_done_offset = GDmaDone_offset; | ||
874 | nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset; | ||
875 | |||
876 | if (old_mac_op == efx->mac_op) | ||
877 | return; | ||
878 | |||
879 | falcon_clock_mac(efx); | ||
880 | |||
881 | netif_dbg(efx, hw, efx->net_dev, "selected %cMAC\n", | ||
882 | EFX_IS10G(efx) ? 'X' : 'G'); | ||
883 | /* Not all macs support a mac-level link state */ | ||
884 | efx->xmac_poll_required = false; | ||
885 | falcon_reset_macs(efx); | ||
886 | } | ||
887 | |||
888 | /* This call is responsible for hooking in the MAC and PHY operations */ | 820 | /* This call is responsible for hooking in the MAC and PHY operations */ |
889 | static int falcon_probe_port(struct efx_nic *efx) | 821 | static int falcon_probe_port(struct efx_nic *efx) |
890 | { | 822 | { |
823 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
891 | int rc; | 824 | int rc; |
892 | 825 | ||
893 | switch (efx->phy_type) { | 826 | switch (efx->phy_type) { |
894 | case PHY_TYPE_SFX7101: | 827 | case PHY_TYPE_SFX7101: |
895 | efx->phy_op = &falcon_sfx7101_phy_ops; | 828 | efx->phy_op = &falcon_sfx7101_phy_ops; |
896 | break; | 829 | break; |
897 | case PHY_TYPE_SFT9001A: | ||
898 | case PHY_TYPE_SFT9001B: | ||
899 | efx->phy_op = &falcon_sft9001_phy_ops; | ||
900 | break; | ||
901 | case PHY_TYPE_QT2022C2: | 830 | case PHY_TYPE_QT2022C2: |
902 | case PHY_TYPE_QT2025C: | 831 | case PHY_TYPE_QT2025C: |
903 | efx->phy_op = &falcon_qt202x_phy_ops; | 832 | efx->phy_op = &falcon_qt202x_phy_ops; |
@@ -937,6 +866,7 @@ static int falcon_probe_port(struct efx_nic *efx) | |||
937 | (u64)efx->stats_buffer.dma_addr, | 866 | (u64)efx->stats_buffer.dma_addr, |
938 | efx->stats_buffer.addr, | 867 | efx->stats_buffer.addr, |
939 | (u64)virt_to_phys(efx->stats_buffer.addr)); | 868 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
869 | nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset; | ||
940 | 870 | ||
941 | return 0; | 871 | return 0; |
942 | } | 872 | } |
@@ -1201,7 +1131,7 @@ static void falcon_monitor(struct efx_nic *efx) | |||
1201 | falcon_stop_nic_stats(efx); | 1131 | falcon_stop_nic_stats(efx); |
1202 | falcon_deconfigure_mac_wrapper(efx); | 1132 | falcon_deconfigure_mac_wrapper(efx); |
1203 | 1133 | ||
1204 | falcon_switch_mac(efx); | 1134 | falcon_reset_macs(efx); |
1205 | rc = efx->mac_op->reconfigure(efx); | 1135 | rc = efx->mac_op->reconfigure(efx); |
1206 | BUG_ON(rc); | 1136 | BUG_ON(rc); |
1207 | 1137 | ||
@@ -1210,8 +1140,7 @@ static void falcon_monitor(struct efx_nic *efx) | |||
1210 | efx_link_status_changed(efx); | 1140 | efx_link_status_changed(efx); |
1211 | } | 1141 | } |
1212 | 1142 | ||
1213 | if (EFX_IS10G(efx)) | 1143 | falcon_poll_xmac(efx); |
1214 | falcon_poll_xmac(efx); | ||
1215 | } | 1144 | } |
1216 | 1145 | ||
1217 | /* Zeroes out the SRAM contents. This routine must be called in | 1146 | /* Zeroes out the SRAM contents. This routine must be called in |
@@ -1604,16 +1533,6 @@ static int falcon_init_nic(struct efx_nic *efx) | |||
1604 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); | 1533 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); |
1605 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); | 1534 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); |
1606 | 1535 | ||
1607 | /* Set the source of the GMAC clock */ | ||
1608 | if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) { | ||
1609 | efx_reado(efx, &temp, FR_AB_GPIO_CTL); | ||
1610 | EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); | ||
1611 | efx_writeo(efx, &temp, FR_AB_GPIO_CTL); | ||
1612 | } | ||
1613 | |||
1614 | /* Select the correct MAC */ | ||
1615 | falcon_clock_mac(efx); | ||
1616 | |||
1617 | rc = falcon_reset_sram(efx); | 1536 | rc = falcon_reset_sram(efx); |
1618 | if (rc) | 1537 | if (rc) |
1619 | return rc; | 1538 | return rc; |
diff --git a/drivers/net/sfc/falcon_boards.c b/drivers/net/sfc/falcon_boards.c index 3d950c2cf20..bf029b3d3b0 100644 --- a/drivers/net/sfc/falcon_boards.c +++ b/drivers/net/sfc/falcon_boards.c | |||
@@ -26,7 +26,6 @@ | |||
26 | /* Board types */ | 26 | /* Board types */ |
27 | #define FALCON_BOARD_SFE4001 0x01 | 27 | #define FALCON_BOARD_SFE4001 0x01 |
28 | #define FALCON_BOARD_SFE4002 0x02 | 28 | #define FALCON_BOARD_SFE4002 0x02 |
29 | #define FALCON_BOARD_SFN4111T 0x51 | ||
30 | #define FALCON_BOARD_SFN4112F 0x52 | 29 | #define FALCON_BOARD_SFN4112F 0x52 |
31 | 30 | ||
32 | /* Board temperature is about 15°C above ambient when air flow is | 31 | /* Board temperature is about 15°C above ambient when air flow is |
@@ -142,17 +141,17 @@ static inline int efx_check_lm87(struct efx_nic *efx, unsigned mask) | |||
142 | #endif /* CONFIG_SENSORS_LM87 */ | 141 | #endif /* CONFIG_SENSORS_LM87 */ |
143 | 142 | ||
144 | /***************************************************************************** | 143 | /***************************************************************************** |
145 | * Support for the SFE4001 and SFN4111T NICs. | 144 | * Support for the SFE4001 NIC. |
146 | * | 145 | * |
147 | * The SFE4001 does not power-up fully at reset due to its high power | 146 | * The SFE4001 does not power-up fully at reset due to its high power |
148 | * consumption. We control its power via a PCA9539 I/O expander. | 147 | * consumption. We control its power via a PCA9539 I/O expander. |
149 | * Both boards have a MAX6647 temperature monitor which we expose to | 148 | * It also has a MAX6647 temperature monitor which we expose to |
150 | * the lm90 driver. | 149 | * the lm90 driver. |
151 | * | 150 | * |
152 | * This also provides minimal support for reflashing the PHY, which is | 151 | * This also provides minimal support for reflashing the PHY, which is |
153 | * initiated by resetting it with the FLASH_CFG_1 pin pulled down. | 152 | * initiated by resetting it with the FLASH_CFG_1 pin pulled down. |
154 | * On SFE4001 rev A2 and later this is connected to the 3V3X output of | 153 | * On SFE4001 rev A2 and later this is connected to the 3V3X output of |
155 | * the IO-expander; on the SFN4111T it is connected to Falcon's GPIO3. | 154 | * the IO-expander. |
156 | * We represent reflash mode as PHY_MODE_SPECIAL and make it mutually | 155 | * We represent reflash mode as PHY_MODE_SPECIAL and make it mutually |
157 | * exclusive with the network device being open. | 156 | * exclusive with the network device being open. |
158 | */ | 157 | */ |
@@ -304,34 +303,6 @@ fail_on: | |||
304 | return rc; | 303 | return rc; |
305 | } | 304 | } |
306 | 305 | ||
307 | static int sfn4111t_reset(struct efx_nic *efx) | ||
308 | { | ||
309 | struct falcon_board *board = falcon_board(efx); | ||
310 | efx_oword_t reg; | ||
311 | |||
312 | /* GPIO 3 and the GPIO register are shared with I2C, so block that */ | ||
313 | i2c_lock_adapter(&board->i2c_adap); | ||
314 | |||
315 | /* Pull RST_N (GPIO 2) low then let it up again, setting the | ||
316 | * FLASH_CFG_1 strap (GPIO 3) appropriately. Only change the | ||
317 | * output enables; the output levels should always be 0 (low) | ||
318 | * and we rely on external pull-ups. */ | ||
319 | efx_reado(efx, ®, FR_AB_GPIO_CTL); | ||
320 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true); | ||
321 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); | ||
322 | msleep(1000); | ||
323 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false); | ||
324 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, | ||
325 | !!(efx->phy_mode & PHY_MODE_SPECIAL)); | ||
326 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); | ||
327 | msleep(1); | ||
328 | |||
329 | i2c_unlock_adapter(&board->i2c_adap); | ||
330 | |||
331 | ssleep(1); | ||
332 | return 0; | ||
333 | } | ||
334 | |||
335 | static ssize_t show_phy_flash_cfg(struct device *dev, | 306 | static ssize_t show_phy_flash_cfg(struct device *dev, |
336 | struct device_attribute *attr, char *buf) | 307 | struct device_attribute *attr, char *buf) |
337 | { | 308 | { |
@@ -363,10 +334,7 @@ static ssize_t set_phy_flash_cfg(struct device *dev, | |||
363 | efx->phy_mode = new_mode; | 334 | efx->phy_mode = new_mode; |
364 | if (new_mode & PHY_MODE_SPECIAL) | 335 | if (new_mode & PHY_MODE_SPECIAL) |
365 | falcon_stop_nic_stats(efx); | 336 | falcon_stop_nic_stats(efx); |
366 | if (falcon_board(efx)->type->id == FALCON_BOARD_SFE4001) | 337 | err = sfe4001_poweron(efx); |
367 | err = sfe4001_poweron(efx); | ||
368 | else | ||
369 | err = sfn4111t_reset(efx); | ||
370 | if (!err) | 338 | if (!err) |
371 | err = efx_reconfigure_port(efx); | 339 | err = efx_reconfigure_port(efx); |
372 | if (!(new_mode & PHY_MODE_SPECIAL)) | 340 | if (!(new_mode & PHY_MODE_SPECIAL)) |
@@ -479,83 +447,6 @@ fail_hwmon: | |||
479 | return rc; | 447 | return rc; |
480 | } | 448 | } |
481 | 449 | ||
482 | static int sfn4111t_check_hw(struct efx_nic *efx) | ||
483 | { | ||
484 | s32 status; | ||
485 | |||
486 | /* If XAUI link is up then do not monitor */ | ||
487 | if (EFX_WORKAROUND_7884(efx) && !efx->xmac_poll_required) | ||
488 | return 0; | ||
489 | |||
490 | /* Test LHIGH, RHIGH, FAULT, EOT and IOT alarms */ | ||
491 | status = i2c_smbus_read_byte_data(falcon_board(efx)->hwmon_client, | ||
492 | MAX664X_REG_RSL); | ||
493 | if (status < 0) | ||
494 | return -EIO; | ||
495 | if (status & 0x57) | ||
496 | return -ERANGE; | ||
497 | return 0; | ||
498 | } | ||
499 | |||
500 | static void sfn4111t_fini(struct efx_nic *efx) | ||
501 | { | ||
502 | netif_info(efx, drv, efx->net_dev, "%s\n", __func__); | ||
503 | |||
504 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_flash_cfg); | ||
505 | i2c_unregister_device(falcon_board(efx)->hwmon_client); | ||
506 | } | ||
507 | |||
508 | static struct i2c_board_info sfn4111t_a0_hwmon_info = { | ||
509 | I2C_BOARD_INFO("max6647", 0x4e), | ||
510 | }; | ||
511 | |||
512 | static struct i2c_board_info sfn4111t_r5_hwmon_info = { | ||
513 | I2C_BOARD_INFO("max6646", 0x4d), | ||
514 | }; | ||
515 | |||
516 | static void sfn4111t_init_phy(struct efx_nic *efx) | ||
517 | { | ||
518 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { | ||
519 | if (sft9001_wait_boot(efx) != -EINVAL) | ||
520 | return; | ||
521 | |||
522 | efx->phy_mode = PHY_MODE_SPECIAL; | ||
523 | falcon_stop_nic_stats(efx); | ||
524 | } | ||
525 | |||
526 | sfn4111t_reset(efx); | ||
527 | sft9001_wait_boot(efx); | ||
528 | } | ||
529 | |||
530 | static int sfn4111t_init(struct efx_nic *efx) | ||
531 | { | ||
532 | struct falcon_board *board = falcon_board(efx); | ||
533 | int rc; | ||
534 | |||
535 | board->hwmon_client = | ||
536 | i2c_new_device(&board->i2c_adap, | ||
537 | (board->minor < 5) ? | ||
538 | &sfn4111t_a0_hwmon_info : | ||
539 | &sfn4111t_r5_hwmon_info); | ||
540 | if (!board->hwmon_client) | ||
541 | return -EIO; | ||
542 | |||
543 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_flash_cfg); | ||
544 | if (rc) | ||
545 | goto fail_hwmon; | ||
546 | |||
547 | if (efx->phy_mode & PHY_MODE_SPECIAL) | ||
548 | /* PHY may not generate a 156.25 MHz clock and MAC | ||
549 | * stats fetch will fail. */ | ||
550 | falcon_stop_nic_stats(efx); | ||
551 | |||
552 | return 0; | ||
553 | |||
554 | fail_hwmon: | ||
555 | i2c_unregister_device(board->hwmon_client); | ||
556 | return rc; | ||
557 | } | ||
558 | |||
559 | /***************************************************************************** | 450 | /***************************************************************************** |
560 | * Support for the SFE4002 | 451 | * Support for the SFE4002 |
561 | * | 452 | * |
@@ -713,16 +604,6 @@ static const struct falcon_board_type board_types[] = { | |||
713 | .monitor = sfe4002_check_hw, | 604 | .monitor = sfe4002_check_hw, |
714 | }, | 605 | }, |
715 | { | 606 | { |
716 | .id = FALCON_BOARD_SFN4111T, | ||
717 | .ref_model = "SFN4111T", | ||
718 | .gen_type = "100/1000/10GBASE-T adapter", | ||
719 | .init = sfn4111t_init, | ||
720 | .init_phy = sfn4111t_init_phy, | ||
721 | .fini = sfn4111t_fini, | ||
722 | .set_id_led = tenxpress_set_id_led, | ||
723 | .monitor = sfn4111t_check_hw, | ||
724 | }, | ||
725 | { | ||
726 | .id = FALCON_BOARD_SFN4112F, | 607 | .id = FALCON_BOARD_SFN4112F, |
727 | .ref_model = "SFN4112F", | 608 | .ref_model = "SFN4112F", |
728 | .gen_type = "SFP+ adapter", | 609 | .gen_type = "SFP+ adapter", |
diff --git a/drivers/net/sfc/falcon_gmac.c b/drivers/net/sfc/falcon_gmac.c deleted file mode 100644 index 7dadfcbd6ce..00000000000 --- a/drivers/net/sfc/falcon_gmac.c +++ /dev/null | |||
@@ -1,230 +0,0 @@ | |||
1 | /**************************************************************************** | ||
2 | * Driver for Solarflare Solarstorm network controllers and boards | ||
3 | * Copyright 2005-2006 Fen Systems Ltd. | ||
4 | * Copyright 2006-2009 Solarflare Communications Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published | ||
8 | * by the Free Software Foundation, incorporated herein by reference. | ||
9 | */ | ||
10 | |||
11 | #include <linux/delay.h> | ||
12 | #include "net_driver.h" | ||
13 | #include "efx.h" | ||
14 | #include "nic.h" | ||
15 | #include "mac.h" | ||
16 | #include "regs.h" | ||
17 | #include "io.h" | ||
18 | |||
19 | /************************************************************************** | ||
20 | * | ||
21 | * MAC operations | ||
22 | * | ||
23 | *************************************************************************/ | ||
24 | |||
25 | static int falcon_reconfigure_gmac(struct efx_nic *efx) | ||
26 | { | ||
27 | struct efx_link_state *link_state = &efx->link_state; | ||
28 | bool loopback, tx_fc, rx_fc, bytemode; | ||
29 | int if_mode; | ||
30 | unsigned int max_frame_len; | ||
31 | efx_oword_t reg; | ||
32 | |||
33 | /* Configuration register 1 */ | ||
34 | tx_fc = (link_state->fc & EFX_FC_TX) || !link_state->fd; | ||
35 | rx_fc = !!(link_state->fc & EFX_FC_RX); | ||
36 | loopback = (efx->loopback_mode == LOOPBACK_GMAC); | ||
37 | bytemode = (link_state->speed == 1000); | ||
38 | |||
39 | EFX_POPULATE_OWORD_5(reg, | ||
40 | FRF_AB_GM_LOOP, loopback, | ||
41 | FRF_AB_GM_TX_EN, 1, | ||
42 | FRF_AB_GM_TX_FC_EN, tx_fc, | ||
43 | FRF_AB_GM_RX_EN, 1, | ||
44 | FRF_AB_GM_RX_FC_EN, rx_fc); | ||
45 | efx_writeo(efx, ®, FR_AB_GM_CFG1); | ||
46 | udelay(10); | ||
47 | |||
48 | /* Configuration register 2 */ | ||
49 | if_mode = (bytemode) ? 2 : 1; | ||
50 | EFX_POPULATE_OWORD_5(reg, | ||
51 | FRF_AB_GM_IF_MODE, if_mode, | ||
52 | FRF_AB_GM_PAD_CRC_EN, 1, | ||
53 | FRF_AB_GM_LEN_CHK, 1, | ||
54 | FRF_AB_GM_FD, link_state->fd, | ||
55 | FRF_AB_GM_PAMBL_LEN, 0x7/*datasheet recommended */); | ||
56 | |||
57 | efx_writeo(efx, ®, FR_AB_GM_CFG2); | ||
58 | udelay(10); | ||
59 | |||
60 | /* Max frame len register */ | ||
61 | max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); | ||
62 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_MAX_FLEN, max_frame_len); | ||
63 | efx_writeo(efx, ®, FR_AB_GM_MAX_FLEN); | ||
64 | udelay(10); | ||
65 | |||
66 | /* FIFO configuration register 0 */ | ||
67 | EFX_POPULATE_OWORD_5(reg, | ||
68 | FRF_AB_GMF_FTFENREQ, 1, | ||
69 | FRF_AB_GMF_STFENREQ, 1, | ||
70 | FRF_AB_GMF_FRFENREQ, 1, | ||
71 | FRF_AB_GMF_SRFENREQ, 1, | ||
72 | FRF_AB_GMF_WTMENREQ, 1); | ||
73 | efx_writeo(efx, ®, FR_AB_GMF_CFG0); | ||
74 | udelay(10); | ||
75 | |||
76 | /* FIFO configuration register 1 */ | ||
77 | EFX_POPULATE_OWORD_2(reg, | ||
78 | FRF_AB_GMF_CFGFRTH, 0x12, | ||
79 | FRF_AB_GMF_CFGXOFFRTX, 0xffff); | ||
80 | efx_writeo(efx, ®, FR_AB_GMF_CFG1); | ||
81 | udelay(10); | ||
82 | |||
83 | /* FIFO configuration register 2 */ | ||
84 | EFX_POPULATE_OWORD_2(reg, | ||
85 | FRF_AB_GMF_CFGHWM, 0x3f, | ||
86 | FRF_AB_GMF_CFGLWM, 0xa); | ||
87 | efx_writeo(efx, ®, FR_AB_GMF_CFG2); | ||
88 | udelay(10); | ||
89 | |||
90 | /* FIFO configuration register 3 */ | ||
91 | EFX_POPULATE_OWORD_2(reg, | ||
92 | FRF_AB_GMF_CFGHWMFT, 0x1c, | ||
93 | FRF_AB_GMF_CFGFTTH, 0x08); | ||
94 | efx_writeo(efx, ®, FR_AB_GMF_CFG3); | ||
95 | udelay(10); | ||
96 | |||
97 | /* FIFO configuration register 4 */ | ||
98 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GMF_HSTFLTRFRM_PAUSE, 1); | ||
99 | efx_writeo(efx, ®, FR_AB_GMF_CFG4); | ||
100 | udelay(10); | ||
101 | |||
102 | /* FIFO configuration register 5 */ | ||
103 | efx_reado(efx, ®, FR_AB_GMF_CFG5); | ||
104 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGBYTMODE, bytemode); | ||
105 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGHDPLX, !link_state->fd); | ||
106 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTDRPLT64, !link_state->fd); | ||
107 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTFLTRFRMDC_PAUSE, 0); | ||
108 | efx_writeo(efx, ®, FR_AB_GMF_CFG5); | ||
109 | udelay(10); | ||
110 | |||
111 | /* MAC address */ | ||
112 | EFX_POPULATE_OWORD_4(reg, | ||
113 | FRF_AB_GM_ADR_B0, efx->net_dev->dev_addr[5], | ||
114 | FRF_AB_GM_ADR_B1, efx->net_dev->dev_addr[4], | ||
115 | FRF_AB_GM_ADR_B2, efx->net_dev->dev_addr[3], | ||
116 | FRF_AB_GM_ADR_B3, efx->net_dev->dev_addr[2]); | ||
117 | efx_writeo(efx, ®, FR_AB_GM_ADR1); | ||
118 | udelay(10); | ||
119 | EFX_POPULATE_OWORD_2(reg, | ||
120 | FRF_AB_GM_ADR_B4, efx->net_dev->dev_addr[1], | ||
121 | FRF_AB_GM_ADR_B5, efx->net_dev->dev_addr[0]); | ||
122 | efx_writeo(efx, ®, FR_AB_GM_ADR2); | ||
123 | udelay(10); | ||
124 | |||
125 | falcon_reconfigure_mac_wrapper(efx); | ||
126 | |||
127 | return 0; | ||
128 | } | ||
129 | |||
130 | static void falcon_update_stats_gmac(struct efx_nic *efx) | ||
131 | { | ||
132 | struct efx_mac_stats *mac_stats = &efx->mac_stats; | ||
133 | unsigned long old_rx_pause, old_tx_pause; | ||
134 | unsigned long new_rx_pause, new_tx_pause; | ||
135 | |||
136 | /* Pause frames are erroneously counted as errors (SFC bug 3269) */ | ||
137 | old_rx_pause = mac_stats->rx_pause; | ||
138 | old_tx_pause = mac_stats->tx_pause; | ||
139 | |||
140 | /* Update MAC stats from DMAed values */ | ||
141 | FALCON_STAT(efx, GRxGoodOct, rx_good_bytes); | ||
142 | FALCON_STAT(efx, GRxBadOct, rx_bad_bytes); | ||
143 | FALCON_STAT(efx, GRxMissPkt, rx_missed); | ||
144 | FALCON_STAT(efx, GRxFalseCRS, rx_false_carrier); | ||
145 | FALCON_STAT(efx, GRxPausePkt, rx_pause); | ||
146 | FALCON_STAT(efx, GRxBadPkt, rx_bad); | ||
147 | FALCON_STAT(efx, GRxUcastPkt, rx_unicast); | ||
148 | FALCON_STAT(efx, GRxMcastPkt, rx_multicast); | ||
149 | FALCON_STAT(efx, GRxBcastPkt, rx_broadcast); | ||
150 | FALCON_STAT(efx, GRxGoodLt64Pkt, rx_good_lt64); | ||
151 | FALCON_STAT(efx, GRxBadLt64Pkt, rx_bad_lt64); | ||
152 | FALCON_STAT(efx, GRx64Pkt, rx_64); | ||
153 | FALCON_STAT(efx, GRx65to127Pkt, rx_65_to_127); | ||
154 | FALCON_STAT(efx, GRx128to255Pkt, rx_128_to_255); | ||
155 | FALCON_STAT(efx, GRx256to511Pkt, rx_256_to_511); | ||
156 | FALCON_STAT(efx, GRx512to1023Pkt, rx_512_to_1023); | ||
157 | FALCON_STAT(efx, GRx1024to15xxPkt, rx_1024_to_15xx); | ||
158 | FALCON_STAT(efx, GRx15xxtoJumboPkt, rx_15xx_to_jumbo); | ||
159 | FALCON_STAT(efx, GRxGtJumboPkt, rx_gtjumbo); | ||
160 | FALCON_STAT(efx, GRxFcsErr64to15xxPkt, rx_bad_64_to_15xx); | ||
161 | FALCON_STAT(efx, GRxFcsErr15xxtoJumboPkt, rx_bad_15xx_to_jumbo); | ||
162 | FALCON_STAT(efx, GRxFcsErrGtJumboPkt, rx_bad_gtjumbo); | ||
163 | FALCON_STAT(efx, GTxGoodBadOct, tx_bytes); | ||
164 | FALCON_STAT(efx, GTxGoodOct, tx_good_bytes); | ||
165 | FALCON_STAT(efx, GTxSglColPkt, tx_single_collision); | ||
166 | FALCON_STAT(efx, GTxMultColPkt, tx_multiple_collision); | ||
167 | FALCON_STAT(efx, GTxExColPkt, tx_excessive_collision); | ||
168 | FALCON_STAT(efx, GTxDefPkt, tx_deferred); | ||
169 | FALCON_STAT(efx, GTxLateCol, tx_late_collision); | ||
170 | FALCON_STAT(efx, GTxExDefPkt, tx_excessive_deferred); | ||
171 | FALCON_STAT(efx, GTxPausePkt, tx_pause); | ||
172 | FALCON_STAT(efx, GTxBadPkt, tx_bad); | ||
173 | FALCON_STAT(efx, GTxUcastPkt, tx_unicast); | ||
174 | FALCON_STAT(efx, GTxMcastPkt, tx_multicast); | ||
175 | FALCON_STAT(efx, GTxBcastPkt, tx_broadcast); | ||
176 | FALCON_STAT(efx, GTxLt64Pkt, tx_lt64); | ||
177 | FALCON_STAT(efx, GTx64Pkt, tx_64); | ||
178 | FALCON_STAT(efx, GTx65to127Pkt, tx_65_to_127); | ||
179 | FALCON_STAT(efx, GTx128to255Pkt, tx_128_to_255); | ||
180 | FALCON_STAT(efx, GTx256to511Pkt, tx_256_to_511); | ||
181 | FALCON_STAT(efx, GTx512to1023Pkt, tx_512_to_1023); | ||
182 | FALCON_STAT(efx, GTx1024to15xxPkt, tx_1024_to_15xx); | ||
183 | FALCON_STAT(efx, GTx15xxtoJumboPkt, tx_15xx_to_jumbo); | ||
184 | FALCON_STAT(efx, GTxGtJumboPkt, tx_gtjumbo); | ||
185 | FALCON_STAT(efx, GTxNonTcpUdpPkt, tx_non_tcpudp); | ||
186 | FALCON_STAT(efx, GTxMacSrcErrPkt, tx_mac_src_error); | ||
187 | FALCON_STAT(efx, GTxIpSrcErrPkt, tx_ip_src_error); | ||
188 | |||
189 | /* Pause frames are erroneously counted as errors (SFC bug 3269) */ | ||
190 | new_rx_pause = mac_stats->rx_pause; | ||
191 | new_tx_pause = mac_stats->tx_pause; | ||
192 | mac_stats->rx_bad -= (new_rx_pause - old_rx_pause); | ||
193 | mac_stats->tx_bad -= (new_tx_pause - old_tx_pause); | ||
194 | |||
195 | /* Derive stats that the MAC doesn't provide directly */ | ||
196 | mac_stats->tx_bad_bytes = | ||
197 | mac_stats->tx_bytes - mac_stats->tx_good_bytes; | ||
198 | mac_stats->tx_packets = | ||
199 | mac_stats->tx_lt64 + mac_stats->tx_64 + | ||
200 | mac_stats->tx_65_to_127 + mac_stats->tx_128_to_255 + | ||
201 | mac_stats->tx_256_to_511 + mac_stats->tx_512_to_1023 + | ||
202 | mac_stats->tx_1024_to_15xx + mac_stats->tx_15xx_to_jumbo + | ||
203 | mac_stats->tx_gtjumbo; | ||
204 | mac_stats->tx_collision = | ||
205 | mac_stats->tx_single_collision + | ||
206 | mac_stats->tx_multiple_collision + | ||
207 | mac_stats->tx_excessive_collision + | ||
208 | mac_stats->tx_late_collision; | ||
209 | mac_stats->rx_bytes = | ||
210 | mac_stats->rx_good_bytes + mac_stats->rx_bad_bytes; | ||
211 | mac_stats->rx_packets = | ||
212 | mac_stats->rx_good_lt64 + mac_stats->rx_bad_lt64 + | ||
213 | mac_stats->rx_64 + mac_stats->rx_65_to_127 + | ||
214 | mac_stats->rx_128_to_255 + mac_stats->rx_256_to_511 + | ||
215 | mac_stats->rx_512_to_1023 + mac_stats->rx_1024_to_15xx + | ||
216 | mac_stats->rx_15xx_to_jumbo + mac_stats->rx_gtjumbo; | ||
217 | mac_stats->rx_good = mac_stats->rx_packets - mac_stats->rx_bad; | ||
218 | mac_stats->rx_lt64 = mac_stats->rx_good_lt64 + mac_stats->rx_bad_lt64; | ||
219 | } | ||
220 | |||
221 | static bool falcon_gmac_check_fault(struct efx_nic *efx) | ||
222 | { | ||
223 | return false; | ||
224 | } | ||
225 | |||
226 | struct efx_mac_operations falcon_gmac_operations = { | ||
227 | .reconfigure = falcon_reconfigure_gmac, | ||
228 | .update_stats = falcon_update_stats_gmac, | ||
229 | .check_fault = falcon_gmac_check_fault, | ||
230 | }; | ||
diff --git a/drivers/net/sfc/mac.h b/drivers/net/sfc/mac.h index f1aa5f37489..7a6e5ca0290 100644 --- a/drivers/net/sfc/mac.h +++ b/drivers/net/sfc/mac.h | |||
@@ -13,7 +13,6 @@ | |||
13 | 13 | ||
14 | #include "net_driver.h" | 14 | #include "net_driver.h" |
15 | 15 | ||
16 | extern struct efx_mac_operations falcon_gmac_operations; | ||
17 | extern struct efx_mac_operations falcon_xmac_operations; | 16 | extern struct efx_mac_operations falcon_xmac_operations; |
18 | extern struct efx_mac_operations efx_mcdi_mac_operations; | 17 | extern struct efx_mac_operations efx_mcdi_mac_operations; |
19 | extern void falcon_reconfigure_xmac_core(struct efx_nic *efx); | 18 | extern void falcon_reconfigure_xmac_core(struct efx_nic *efx); |
diff --git a/drivers/net/sfc/mdio_10g.c b/drivers/net/sfc/mdio_10g.c index eeaf0bd64bd..98d94602042 100644 --- a/drivers/net/sfc/mdio_10g.c +++ b/drivers/net/sfc/mdio_10g.c | |||
@@ -286,46 +286,24 @@ int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |||
286 | */ | 286 | */ |
287 | void efx_mdio_an_reconfigure(struct efx_nic *efx) | 287 | void efx_mdio_an_reconfigure(struct efx_nic *efx) |
288 | { | 288 | { |
289 | bool xnp = (efx->link_advertising & ADVERTISED_10000baseT_Full | ||
290 | || EFX_WORKAROUND_13204(efx)); | ||
291 | int reg; | 289 | int reg; |
292 | 290 | ||
293 | WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN)); | 291 | WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN)); |
294 | 292 | ||
295 | /* Set up the base page */ | 293 | /* Set up the base page */ |
296 | reg = ADVERTISE_CSMA; | 294 | reg = ADVERTISE_CSMA | ADVERTISE_RESV; |
297 | if (efx->link_advertising & ADVERTISED_10baseT_Half) | ||
298 | reg |= ADVERTISE_10HALF; | ||
299 | if (efx->link_advertising & ADVERTISED_10baseT_Full) | ||
300 | reg |= ADVERTISE_10FULL; | ||
301 | if (efx->link_advertising & ADVERTISED_100baseT_Half) | ||
302 | reg |= ADVERTISE_100HALF; | ||
303 | if (efx->link_advertising & ADVERTISED_100baseT_Full) | ||
304 | reg |= ADVERTISE_100FULL; | ||
305 | if (xnp) | ||
306 | reg |= ADVERTISE_RESV; | ||
307 | else if (efx->link_advertising & (ADVERTISED_1000baseT_Half | | ||
308 | ADVERTISED_1000baseT_Full)) | ||
309 | reg |= ADVERTISE_NPAGE; | ||
310 | if (efx->link_advertising & ADVERTISED_Pause) | 295 | if (efx->link_advertising & ADVERTISED_Pause) |
311 | reg |= ADVERTISE_PAUSE_CAP; | 296 | reg |= ADVERTISE_PAUSE_CAP; |
312 | if (efx->link_advertising & ADVERTISED_Asym_Pause) | 297 | if (efx->link_advertising & ADVERTISED_Asym_Pause) |
313 | reg |= ADVERTISE_PAUSE_ASYM; | 298 | reg |= ADVERTISE_PAUSE_ASYM; |
314 | efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); | 299 | efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); |
315 | 300 | ||
316 | /* Set up the (extended) next page if necessary */ | 301 | /* Set up the (extended) next page */ |
317 | if (efx->phy_op->set_npage_adv) | 302 | efx->phy_op->set_npage_adv(efx, efx->link_advertising); |
318 | efx->phy_op->set_npage_adv(efx, efx->link_advertising); | ||
319 | 303 | ||
320 | /* Enable and restart AN */ | 304 | /* Enable and restart AN */ |
321 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); | 305 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); |
322 | reg |= MDIO_AN_CTRL1_ENABLE; | 306 | reg |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART | MDIO_AN_CTRL1_XNP; |
323 | if (!(EFX_WORKAROUND_15195(efx) && LOOPBACK_EXTERNAL(efx))) | ||
324 | reg |= MDIO_AN_CTRL1_RESTART; | ||
325 | if (xnp) | ||
326 | reg |= MDIO_AN_CTRL1_XNP; | ||
327 | else | ||
328 | reg &= ~MDIO_AN_CTRL1_XNP; | ||
329 | efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); | 307 | efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); |
330 | } | 308 | } |
331 | 309 | ||
diff --git a/drivers/net/sfc/net_driver.h b/drivers/net/sfc/net_driver.h index b3f2bf43673..845be71bef6 100644 --- a/drivers/net/sfc/net_driver.h +++ b/drivers/net/sfc/net_driver.h | |||
@@ -406,8 +406,6 @@ enum efx_int_mode { | |||
406 | }; | 406 | }; |
407 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | 407 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) |
408 | 408 | ||
409 | #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000) | ||
410 | |||
411 | enum nic_state { | 409 | enum nic_state { |
412 | STATE_INIT = 0, | 410 | STATE_INIT = 0, |
413 | STATE_RUNNING = 1, | 411 | STATE_RUNNING = 1, |
diff --git a/drivers/net/sfc/phy.h b/drivers/net/sfc/phy.h index 5bc26137257..7ab07575c6d 100644 --- a/drivers/net/sfc/phy.h +++ b/drivers/net/sfc/phy.h | |||
@@ -11,17 +11,12 @@ | |||
11 | #define EFX_PHY_H | 11 | #define EFX_PHY_H |
12 | 12 | ||
13 | /**************************************************************************** | 13 | /**************************************************************************** |
14 | * 10Xpress (SFX7101 and SFT9001) PHYs | 14 | * 10Xpress (SFX7101) PHY |
15 | */ | 15 | */ |
16 | extern struct efx_phy_operations falcon_sfx7101_phy_ops; | 16 | extern struct efx_phy_operations falcon_sfx7101_phy_ops; |
17 | extern struct efx_phy_operations falcon_sft9001_phy_ops; | ||
18 | 17 | ||
19 | extern void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode); | 18 | extern void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode); |
20 | 19 | ||
21 | /* Wait for the PHY to boot. Return 0 on success, -EINVAL if the PHY failed | ||
22 | * to boot due to corrupt flash, or some other negative error code. */ | ||
23 | extern int sft9001_wait_boot(struct efx_nic *efx); | ||
24 | |||
25 | /**************************************************************************** | 20 | /**************************************************************************** |
26 | * AMCC/Quake QT202x PHYs | 21 | * AMCC/Quake QT202x PHYs |
27 | */ | 22 | */ |
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c index 6791be90c2f..1bc6c48c96e 100644 --- a/drivers/net/sfc/tenxpress.c +++ b/drivers/net/sfc/tenxpress.c | |||
@@ -19,10 +19,7 @@ | |||
19 | #include "workarounds.h" | 19 | #include "workarounds.h" |
20 | #include "selftest.h" | 20 | #include "selftest.h" |
21 | 21 | ||
22 | /* We expect these MMDs to be in the package. SFT9001 also has a | 22 | /* We expect these MMDs to be in the package. */ |
23 | * clause 22 extension MMD, but since it doesn't have all the generic | ||
24 | * MMD registers it is pointless to include it here. | ||
25 | */ | ||
26 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ | 23 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
27 | MDIO_DEVS_PCS | \ | 24 | MDIO_DEVS_PCS | \ |
28 | MDIO_DEVS_PHYXS | \ | 25 | MDIO_DEVS_PHYXS | \ |
@@ -33,12 +30,6 @@ | |||
33 | (1 << LOOPBACK_PMAPMD) | \ | 30 | (1 << LOOPBACK_PMAPMD) | \ |
34 | (1 << LOOPBACK_PHYXS_WS)) | 31 | (1 << LOOPBACK_PHYXS_WS)) |
35 | 32 | ||
36 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | ||
37 | (1 << LOOPBACK_PHYXS) | \ | ||
38 | (1 << LOOPBACK_PCS) | \ | ||
39 | (1 << LOOPBACK_PMAPMD) | \ | ||
40 | (1 << LOOPBACK_PHYXS_WS)) | ||
41 | |||
42 | /* We complain if we fail to see the link partner as 10G capable this many | 33 | /* We complain if we fail to see the link partner as 10G capable this many |
43 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | 34 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) |
44 | */ | 35 | */ |
@@ -50,9 +41,8 @@ | |||
50 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | 41 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 |
51 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | 42 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 |
52 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | 43 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 |
53 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | 44 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 |
54 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | 45 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 |
55 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | ||
56 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | 46 | #define PMA_PMD_EXT_CLK312_WIDTH 1 |
57 | #define PMA_PMD_EXT_LPOWER_LBN 12 | 47 | #define PMA_PMD_EXT_LPOWER_LBN 12 |
58 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | 48 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 |
@@ -84,7 +74,6 @@ | |||
84 | #define PMA_PMD_LED_FLASH (3) | 74 | #define PMA_PMD_LED_FLASH (3) |
85 | #define PMA_PMD_LED_MASK 3 | 75 | #define PMA_PMD_LED_MASK 3 |
86 | /* All LEDs under hardware control */ | 76 | /* All LEDs under hardware control */ |
87 | #define SFT9001_PMA_PMD_LED_DEFAULT 0 | ||
88 | /* Green and Amber under hardware control, Red off */ | 77 | /* Green and Amber under hardware control, Red off */ |
89 | #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | 78 | #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
90 | 79 | ||
@@ -98,31 +87,7 @@ | |||
98 | #define PMA_PMD_SPEED_LBN 4 | 87 | #define PMA_PMD_SPEED_LBN 4 |
99 | #define PMA_PMD_SPEED_WIDTH 4 | 88 | #define PMA_PMD_SPEED_WIDTH 4 |
100 | 89 | ||
101 | /* Cable diagnostics - SFT9001 only */ | 90 | /* Misc register defines */ |
102 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | ||
103 | #define CDIAG_CTRL_IMMED_LBN 15 | ||
104 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | ||
105 | #define CDIAG_CTRL_IN_PROG_LBN 11 | ||
106 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | ||
107 | #define CDIAG_CTRL_LEN_METRES 1 | ||
108 | #define PMA_PMD_CDIAG_RES_REG 49174 | ||
109 | #define CDIAG_RES_A_LBN 12 | ||
110 | #define CDIAG_RES_B_LBN 8 | ||
111 | #define CDIAG_RES_C_LBN 4 | ||
112 | #define CDIAG_RES_D_LBN 0 | ||
113 | #define CDIAG_RES_WIDTH 4 | ||
114 | #define CDIAG_RES_OPEN 2 | ||
115 | #define CDIAG_RES_OK 1 | ||
116 | #define CDIAG_RES_INVALID 0 | ||
117 | /* Set of 4 registers for pairs A-D */ | ||
118 | #define PMA_PMD_CDIAG_LEN_REG 49175 | ||
119 | |||
120 | /* Serdes control registers - SFT9001 only */ | ||
121 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | ||
122 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | ||
123 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | ||
124 | |||
125 | /* Misc register defines - SFX7101 only */ | ||
126 | #define PCS_CLOCK_CTRL_REG 55297 | 91 | #define PCS_CLOCK_CTRL_REG 55297 |
127 | #define PLL312_RST_N_LBN 2 | 92 | #define PLL312_RST_N_LBN 2 |
128 | 93 | ||
@@ -185,121 +150,17 @@ struct tenxpress_phy_data { | |||
185 | int bad_lp_tries; | 150 | int bad_lp_tries; |
186 | }; | 151 | }; |
187 | 152 | ||
188 | static ssize_t show_phy_short_reach(struct device *dev, | ||
189 | struct device_attribute *attr, char *buf) | ||
190 | { | ||
191 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | ||
192 | int reg; | ||
193 | |||
194 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); | ||
195 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); | ||
196 | } | ||
197 | |||
198 | static ssize_t set_phy_short_reach(struct device *dev, | ||
199 | struct device_attribute *attr, | ||
200 | const char *buf, size_t count) | ||
201 | { | ||
202 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | ||
203 | int rc; | ||
204 | |||
205 | rtnl_lock(); | ||
206 | if (efx->state != STATE_RUNNING) { | ||
207 | rc = -EBUSY; | ||
208 | } else { | ||
209 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, | ||
210 | MDIO_PMA_10GBT_TXPWR_SHORT, | ||
211 | count != 0 && *buf != '0'); | ||
212 | rc = efx_reconfigure_port(efx); | ||
213 | } | ||
214 | rtnl_unlock(); | ||
215 | |||
216 | return rc < 0 ? rc : (ssize_t)count; | ||
217 | } | ||
218 | |||
219 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | ||
220 | set_phy_short_reach); | ||
221 | |||
222 | int sft9001_wait_boot(struct efx_nic *efx) | ||
223 | { | ||
224 | unsigned long timeout = jiffies + HZ + 1; | ||
225 | int boot_stat; | ||
226 | |||
227 | for (;;) { | ||
228 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, | ||
229 | PCS_BOOT_STATUS_REG); | ||
230 | if (boot_stat >= 0) { | ||
231 | netif_dbg(efx, hw, efx->net_dev, | ||
232 | "PHY boot status = %#x\n", boot_stat); | ||
233 | switch (boot_stat & | ||
234 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | ||
235 | (3 << PCS_BOOT_PROGRESS_LBN) | | ||
236 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | ||
237 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | ||
238 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | ||
239 | (PCS_BOOT_PROGRESS_CHECKSUM << | ||
240 | PCS_BOOT_PROGRESS_LBN)): | ||
241 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | ||
242 | (PCS_BOOT_PROGRESS_INIT << | ||
243 | PCS_BOOT_PROGRESS_LBN) | | ||
244 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | ||
245 | return -EINVAL; | ||
246 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | ||
247 | PCS_BOOT_PROGRESS_LBN) | | ||
248 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | ||
249 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | ||
250 | 0 : -EIO; | ||
251 | case ((PCS_BOOT_PROGRESS_JUMP << | ||
252 | PCS_BOOT_PROGRESS_LBN) | | ||
253 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | ||
254 | case ((PCS_BOOT_PROGRESS_JUMP << | ||
255 | PCS_BOOT_PROGRESS_LBN) | | ||
256 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | ||
257 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | ||
258 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | ||
259 | -EIO : 0; | ||
260 | default: | ||
261 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | ||
262 | return -EIO; | ||
263 | break; | ||
264 | } | ||
265 | } | ||
266 | |||
267 | if (time_after_eq(jiffies, timeout)) | ||
268 | return -ETIMEDOUT; | ||
269 | |||
270 | msleep(50); | ||
271 | } | ||
272 | } | ||
273 | |||
274 | static int tenxpress_init(struct efx_nic *efx) | 153 | static int tenxpress_init(struct efx_nic *efx) |
275 | { | 154 | { |
276 | int reg; | 155 | /* Enable 312.5 MHz clock */ |
277 | 156 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, | |
278 | if (efx->phy_type == PHY_TYPE_SFX7101) { | 157 | 1 << CLK312_EN_LBN); |
279 | /* Enable 312.5 MHz clock */ | ||
280 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, | ||
281 | 1 << CLK312_EN_LBN); | ||
282 | } else { | ||
283 | /* Enable 312.5 MHz clock and GMII */ | ||
284 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); | ||
285 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | | ||
286 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | ||
287 | (1 << PMA_PMD_EXT_CLK312_LBN) | | ||
288 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | ||
289 | |||
290 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); | ||
291 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, | ||
292 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, | ||
293 | false); | ||
294 | } | ||
295 | 158 | ||
296 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ | 159 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
297 | if (efx->phy_type == PHY_TYPE_SFX7101) { | 160 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
298 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, | 161 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); |
299 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); | 162 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, |
300 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, | 163 | SFX7101_PMA_PMD_LED_DEFAULT); |
301 | SFX7101_PMA_PMD_LED_DEFAULT); | ||
302 | } | ||
303 | 164 | ||
304 | return 0; | 165 | return 0; |
305 | } | 166 | } |
@@ -307,7 +168,6 @@ static int tenxpress_init(struct efx_nic *efx) | |||
307 | static int tenxpress_phy_probe(struct efx_nic *efx) | 168 | static int tenxpress_phy_probe(struct efx_nic *efx) |
308 | { | 169 | { |
309 | struct tenxpress_phy_data *phy_data; | 170 | struct tenxpress_phy_data *phy_data; |
310 | int rc; | ||
311 | 171 | ||
312 | /* Allocate phy private storage */ | 172 | /* Allocate phy private storage */ |
313 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | 173 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); |
@@ -316,42 +176,15 @@ static int tenxpress_phy_probe(struct efx_nic *efx) | |||
316 | efx->phy_data = phy_data; | 176 | efx->phy_data = phy_data; |
317 | phy_data->phy_mode = efx->phy_mode; | 177 | phy_data->phy_mode = efx->phy_mode; |
318 | 178 | ||
319 | /* Create any special files */ | 179 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; |
320 | if (efx->phy_type == PHY_TYPE_SFT9001B) { | 180 | efx->mdio.mode_support = MDIO_SUPPORTS_C45; |
321 | rc = device_create_file(&efx->pci_dev->dev, | ||
322 | &dev_attr_phy_short_reach); | ||
323 | if (rc) | ||
324 | goto fail; | ||
325 | } | ||
326 | |||
327 | if (efx->phy_type == PHY_TYPE_SFX7101) { | ||
328 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | ||
329 | efx->mdio.mode_support = MDIO_SUPPORTS_C45; | ||
330 | |||
331 | efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS; | ||
332 | 181 | ||
333 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | | 182 | efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS; |
334 | ADVERTISED_10000baseT_Full); | ||
335 | } else { | ||
336 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | ||
337 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | ||
338 | 183 | ||
339 | efx->loopback_modes = (SFT9001_LOOPBACKS | | 184 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | |
340 | FALCON_XMAC_LOOPBACKS | | 185 | ADVERTISED_10000baseT_Full); |
341 | FALCON_GMAC_LOOPBACKS); | ||
342 | |||
343 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | | ||
344 | ADVERTISED_10000baseT_Full | | ||
345 | ADVERTISED_1000baseT_Full | | ||
346 | ADVERTISED_100baseT_Full); | ||
347 | } | ||
348 | 186 | ||
349 | return 0; | 187 | return 0; |
350 | |||
351 | fail: | ||
352 | kfree(efx->phy_data); | ||
353 | efx->phy_data = NULL; | ||
354 | return rc; | ||
355 | } | 188 | } |
356 | 189 | ||
357 | static int tenxpress_phy_init(struct efx_nic *efx) | 190 | static int tenxpress_phy_init(struct efx_nic *efx) |
@@ -361,16 +194,6 @@ static int tenxpress_phy_init(struct efx_nic *efx) | |||
361 | falcon_board(efx)->type->init_phy(efx); | 194 | falcon_board(efx)->type->init_phy(efx); |
362 | 195 | ||
363 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { | 196 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
364 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | ||
365 | int reg; | ||
366 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, | ||
367 | PMA_PMD_XCONTROL_REG); | ||
368 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); | ||
369 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, | ||
370 | PMA_PMD_XCONTROL_REG, reg); | ||
371 | mdelay(200); | ||
372 | } | ||
373 | |||
374 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); | 197 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
375 | if (rc < 0) | 198 | if (rc < 0) |
376 | return rc; | 199 | return rc; |
@@ -403,7 +226,7 @@ static int tenxpress_special_reset(struct efx_nic *efx) | |||
403 | { | 226 | { |
404 | int rc, reg; | 227 | int rc, reg; |
405 | 228 | ||
406 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so | 229 | /* The XGMAC clock is driven from the SFX7101 312MHz clock, so |
407 | * a special software reset can glitch the XGMAC sufficiently for stats | 230 | * a special software reset can glitch the XGMAC sufficiently for stats |
408 | * requests to fail. */ | 231 | * requests to fail. */ |
409 | falcon_stop_nic_stats(efx); | 232 | falcon_stop_nic_stats(efx); |
@@ -484,53 +307,18 @@ static bool sfx7101_link_ok(struct efx_nic *efx) | |||
484 | MDIO_DEVS_PHYXS); | 307 | MDIO_DEVS_PHYXS); |
485 | } | 308 | } |
486 | 309 | ||
487 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | ||
488 | { | ||
489 | u32 reg; | ||
490 | |||
491 | if (efx_phy_mode_disabled(efx->phy_mode)) | ||
492 | return false; | ||
493 | else if (efx->loopback_mode == LOOPBACK_GPHY) | ||
494 | return true; | ||
495 | else if (efx->loopback_mode) | ||
496 | return efx_mdio_links_ok(efx, | ||
497 | MDIO_DEVS_PMAPMD | | ||
498 | MDIO_DEVS_PHYXS); | ||
499 | |||
500 | /* We must use the same definition of link state as LASI, | ||
501 | * otherwise we can miss a link state transition | ||
502 | */ | ||
503 | if (ecmd->speed == 10000) { | ||
504 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); | ||
505 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; | ||
506 | } else { | ||
507 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); | ||
508 | return reg & (1 << C22EXT_STATUS_LINK_LBN); | ||
509 | } | ||
510 | } | ||
511 | |||
512 | static void tenxpress_ext_loopback(struct efx_nic *efx) | 310 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
513 | { | 311 | { |
514 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, | 312 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
515 | 1 << LOOPBACK_NEAR_LBN, | 313 | 1 << LOOPBACK_NEAR_LBN, |
516 | efx->loopback_mode == LOOPBACK_PHYXS); | 314 | efx->loopback_mode == LOOPBACK_PHYXS); |
517 | if (efx->phy_type != PHY_TYPE_SFX7101) | ||
518 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, | ||
519 | 1 << GPHY_LOOPBACK_NEAR_LBN, | ||
520 | efx->loopback_mode == LOOPBACK_GPHY); | ||
521 | } | 315 | } |
522 | 316 | ||
523 | static void tenxpress_low_power(struct efx_nic *efx) | 317 | static void tenxpress_low_power(struct efx_nic *efx) |
524 | { | 318 | { |
525 | if (efx->phy_type == PHY_TYPE_SFX7101) | 319 | efx_mdio_set_mmds_lpower( |
526 | efx_mdio_set_mmds_lpower( | 320 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
527 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), | 321 | TENXPRESS_REQUIRED_DEVS); |
528 | TENXPRESS_REQUIRED_DEVS); | ||
529 | else | ||
530 | efx_mdio_set_flag( | ||
531 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, | ||
532 | 1 << PMA_PMD_EXT_LPOWER_LBN, | ||
533 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); | ||
534 | } | 322 | } |
535 | 323 | ||
536 | static int tenxpress_phy_reconfigure(struct efx_nic *efx) | 324 | static int tenxpress_phy_reconfigure(struct efx_nic *efx) |
@@ -550,12 +338,7 @@ static int tenxpress_phy_reconfigure(struct efx_nic *efx) | |||
550 | 338 | ||
551 | if (loop_reset || phy_mode_change) { | 339 | if (loop_reset || phy_mode_change) { |
552 | tenxpress_special_reset(efx); | 340 | tenxpress_special_reset(efx); |
553 | 341 | falcon_reset_xaui(efx); | |
554 | /* Reset XAUI if we were in 10G, and are staying | ||
555 | * in 10G. If we're moving into and out of 10G | ||
556 | * then xaui will be reset anyway */ | ||
557 | if (EFX_IS10G(efx)) | ||
558 | falcon_reset_xaui(efx); | ||
559 | } | 342 | } |
560 | 343 | ||
561 | tenxpress_low_power(efx); | 344 | tenxpress_low_power(efx); |
@@ -578,29 +361,12 @@ static bool tenxpress_phy_poll(struct efx_nic *efx) | |||
578 | { | 361 | { |
579 | struct efx_link_state old_state = efx->link_state; | 362 | struct efx_link_state old_state = efx->link_state; |
580 | 363 | ||
581 | if (efx->phy_type == PHY_TYPE_SFX7101) { | 364 | efx->link_state.up = sfx7101_link_ok(efx); |
582 | efx->link_state.up = sfx7101_link_ok(efx); | 365 | efx->link_state.speed = 10000; |
583 | efx->link_state.speed = 10000; | 366 | efx->link_state.fd = true; |
584 | efx->link_state.fd = true; | 367 | efx->link_state.fc = efx_mdio_get_pause(efx); |
585 | efx->link_state.fc = efx_mdio_get_pause(efx); | ||
586 | |||
587 | sfx7101_check_bad_lp(efx, efx->link_state.up); | ||
588 | } else { | ||
589 | struct ethtool_cmd ecmd; | ||
590 | |||
591 | /* Check the LASI alarm first */ | ||
592 | if (efx->loopback_mode == LOOPBACK_NONE && | ||
593 | !(efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT) & | ||
594 | MDIO_PMA_LASI_LSALARM)) | ||
595 | return false; | ||
596 | 368 | ||
597 | tenxpress_get_settings(efx, &ecmd); | 369 | sfx7101_check_bad_lp(efx, efx->link_state.up); |
598 | |||
599 | efx->link_state.up = sft9001_link_ok(efx, &ecmd); | ||
600 | efx->link_state.speed = ecmd.speed; | ||
601 | efx->link_state.fd = (ecmd.duplex == DUPLEX_FULL); | ||
602 | efx->link_state.fc = efx_mdio_get_pause(efx); | ||
603 | } | ||
604 | 370 | ||
605 | return !efx_link_state_equal(&efx->link_state, &old_state); | 371 | return !efx_link_state_equal(&efx->link_state, &old_state); |
606 | } | 372 | } |
@@ -621,10 +387,6 @@ static void sfx7101_phy_fini(struct efx_nic *efx) | |||
621 | 387 | ||
622 | static void tenxpress_phy_remove(struct efx_nic *efx) | 388 | static void tenxpress_phy_remove(struct efx_nic *efx) |
623 | { | 389 | { |
624 | if (efx->phy_type == PHY_TYPE_SFT9001B) | ||
625 | device_remove_file(&efx->pci_dev->dev, | ||
626 | &dev_attr_phy_short_reach); | ||
627 | |||
628 | kfree(efx->phy_data); | 390 | kfree(efx->phy_data); |
629 | efx->phy_data = NULL; | 391 | efx->phy_data = NULL; |
630 | } | 392 | } |
@@ -647,10 +409,7 @@ void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) | |||
647 | (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN); | 409 | (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN); |
648 | break; | 410 | break; |
649 | default: | 411 | default: |
650 | if (efx->phy_type == PHY_TYPE_SFX7101) | 412 | reg = SFX7101_PMA_PMD_LED_DEFAULT; |
651 | reg = SFX7101_PMA_PMD_LED_DEFAULT; | ||
652 | else | ||
653 | reg = SFT9001_PMA_PMD_LED_DEFAULT; | ||
654 | break; | 413 | break; |
655 | } | 414 | } |
656 | 415 | ||
@@ -685,102 +444,12 @@ sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |||
685 | return rc; | 444 | return rc; |
686 | } | 445 | } |
687 | 446 | ||
688 | static const char *const sft9001_test_names[] = { | ||
689 | "bist", | ||
690 | "cable.pairA.status", | ||
691 | "cable.pairB.status", | ||
692 | "cable.pairC.status", | ||
693 | "cable.pairD.status", | ||
694 | "cable.pairA.length", | ||
695 | "cable.pairB.length", | ||
696 | "cable.pairC.length", | ||
697 | "cable.pairD.length", | ||
698 | }; | ||
699 | |||
700 | static const char *sft9001_test_name(struct efx_nic *efx, unsigned int index) | ||
701 | { | ||
702 | if (index < ARRAY_SIZE(sft9001_test_names)) | ||
703 | return sft9001_test_names[index]; | ||
704 | return NULL; | ||
705 | } | ||
706 | |||
707 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | ||
708 | { | ||
709 | int rc = 0, rc2, i, ctrl_reg, res_reg; | ||
710 | |||
711 | /* Initialise cable diagnostic results to unknown failure */ | ||
712 | for (i = 1; i < 9; ++i) | ||
713 | results[i] = -1; | ||
714 | |||
715 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | ||
716 | * A cable fault is not a self-test failure, but a timeout is. */ | ||
717 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | | ||
718 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | ||
719 | if (flags & ETH_TEST_FL_OFFLINE) { | ||
720 | /* Break the link in order to run full diagnostics. We | ||
721 | * must reset the PHY to resume normal service. */ | ||
722 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | ||
723 | } | ||
724 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, | ||
725 | ctrl_reg); | ||
726 | i = 0; | ||
727 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & | ||
728 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { | ||
729 | if (++i == 50) { | ||
730 | rc = -ETIMEDOUT; | ||
731 | goto out; | ||
732 | } | ||
733 | msleep(100); | ||
734 | } | ||
735 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); | ||
736 | for (i = 0; i < 4; i++) { | ||
737 | int pair_res = | ||
738 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | ||
739 | & ((1 << CDIAG_RES_WIDTH) - 1); | ||
740 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, | ||
741 | PMA_PMD_CDIAG_LEN_REG + i); | ||
742 | if (pair_res == CDIAG_RES_OK) | ||
743 | results[1 + i] = 1; | ||
744 | else if (pair_res == CDIAG_RES_INVALID) | ||
745 | results[1 + i] = -1; | ||
746 | else | ||
747 | results[1 + i] = -pair_res; | ||
748 | if (pair_res != CDIAG_RES_INVALID && | ||
749 | pair_res != CDIAG_RES_OPEN && | ||
750 | len_reg != 0xffff) | ||
751 | results[5 + i] = len_reg; | ||
752 | } | ||
753 | |||
754 | out: | ||
755 | if (flags & ETH_TEST_FL_OFFLINE) { | ||
756 | /* Reset, running the BIST and then resuming normal service. */ | ||
757 | rc2 = tenxpress_special_reset(efx); | ||
758 | results[0] = rc2 ? -1 : 1; | ||
759 | if (!rc) | ||
760 | rc = rc2; | ||
761 | |||
762 | efx_mdio_an_reconfigure(efx); | ||
763 | } | ||
764 | |||
765 | return rc; | ||
766 | } | ||
767 | |||
768 | static void | 447 | static void |
769 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | 448 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
770 | { | 449 | { |
771 | u32 adv = 0, lpa = 0; | 450 | u32 adv = 0, lpa = 0; |
772 | int reg; | 451 | int reg; |
773 | 452 | ||
774 | if (efx->phy_type != PHY_TYPE_SFX7101) { | ||
775 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); | ||
776 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) | ||
777 | adv |= ADVERTISED_1000baseT_Full; | ||
778 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); | ||
779 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) | ||
780 | lpa |= ADVERTISED_1000baseT_Half; | ||
781 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) | ||
782 | lpa |= ADVERTISED_1000baseT_Full; | ||
783 | } | ||
784 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); | 453 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
785 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) | 454 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) |
786 | adv |= ADVERTISED_10000baseT_Full; | 455 | adv |= ADVERTISED_10000baseT_Full; |
@@ -790,23 +459,9 @@ tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |||
790 | 459 | ||
791 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); | 460 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
792 | 461 | ||
793 | if (efx->phy_type != PHY_TYPE_SFX7101) { | ||
794 | ecmd->supported |= (SUPPORTED_100baseT_Full | | ||
795 | SUPPORTED_1000baseT_Full); | ||
796 | if (ecmd->speed != SPEED_10000) { | ||
797 | ecmd->eth_tp_mdix = | ||
798 | (efx_mdio_read(efx, MDIO_MMD_PMAPMD, | ||
799 | PMA_PMD_XSTATUS_REG) & | ||
800 | (1 << PMA_PMD_XSTAT_MDIX_LBN)) | ||
801 | ? ETH_TP_MDI_X : ETH_TP_MDI; | ||
802 | } | ||
803 | } | ||
804 | |||
805 | /* In loopback, the PHY automatically brings up the correct interface, | 462 | /* In loopback, the PHY automatically brings up the correct interface, |
806 | * but doesn't advertise the correct speed. So override it */ | 463 | * but doesn't advertise the correct speed. So override it */ |
807 | if (efx->loopback_mode == LOOPBACK_GPHY) | 464 | if (LOOPBACK_EXTERNAL(efx)) |
808 | ecmd->speed = SPEED_1000; | ||
809 | else if (LOOPBACK_EXTERNAL(efx)) | ||
810 | ecmd->speed = SPEED_10000; | 465 | ecmd->speed = SPEED_10000; |
811 | } | 466 | } |
812 | 467 | ||
@@ -825,16 +480,6 @@ static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) | |||
825 | advertising & ADVERTISED_10000baseT_Full); | 480 | advertising & ADVERTISED_10000baseT_Full); |
826 | } | 481 | } |
827 | 482 | ||
828 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) | ||
829 | { | ||
830 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, | ||
831 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | ||
832 | advertising & ADVERTISED_1000baseT_Full); | ||
833 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, | ||
834 | MDIO_AN_10GBT_CTRL_ADV10G, | ||
835 | advertising & ADVERTISED_10000baseT_Full); | ||
836 | } | ||
837 | |||
838 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | 483 | struct efx_phy_operations falcon_sfx7101_phy_ops = { |
839 | .probe = tenxpress_phy_probe, | 484 | .probe = tenxpress_phy_probe, |
840 | .init = tenxpress_phy_init, | 485 | .init = tenxpress_phy_init, |
@@ -849,18 +494,3 @@ struct efx_phy_operations falcon_sfx7101_phy_ops = { | |||
849 | .test_name = sfx7101_test_name, | 494 | .test_name = sfx7101_test_name, |
850 | .run_tests = sfx7101_run_tests, | 495 | .run_tests = sfx7101_run_tests, |
851 | }; | 496 | }; |
852 | |||
853 | struct efx_phy_operations falcon_sft9001_phy_ops = { | ||
854 | .probe = tenxpress_phy_probe, | ||
855 | .init = tenxpress_phy_init, | ||
856 | .reconfigure = tenxpress_phy_reconfigure, | ||
857 | .poll = tenxpress_phy_poll, | ||
858 | .fini = efx_port_dummy_op_void, | ||
859 | .remove = tenxpress_phy_remove, | ||
860 | .get_settings = tenxpress_get_settings, | ||
861 | .set_settings = tenxpress_set_settings, | ||
862 | .set_npage_adv = sft9001_set_npage_adv, | ||
863 | .test_alive = efx_mdio_test_alive, | ||
864 | .test_name = sft9001_test_name, | ||
865 | .run_tests = sft9001_run_tests, | ||
866 | }; | ||
diff --git a/drivers/net/sfc/workarounds.h b/drivers/net/sfc/workarounds.h index 782e45a613d..e0d63083c3a 100644 --- a/drivers/net/sfc/workarounds.h +++ b/drivers/net/sfc/workarounds.h | |||
@@ -19,9 +19,7 @@ | |||
19 | #define EFX_WORKAROUND_FALCON_A(efx) (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) | 19 | #define EFX_WORKAROUND_FALCON_A(efx) (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) |
20 | #define EFX_WORKAROUND_FALCON_AB(efx) (efx_nic_rev(efx) <= EFX_REV_FALCON_B0) | 20 | #define EFX_WORKAROUND_FALCON_AB(efx) (efx_nic_rev(efx) <= EFX_REV_FALCON_B0) |
21 | #define EFX_WORKAROUND_SIENA(efx) (efx_nic_rev(efx) == EFX_REV_SIENA_A0) | 21 | #define EFX_WORKAROUND_SIENA(efx) (efx_nic_rev(efx) == EFX_REV_SIENA_A0) |
22 | #define EFX_WORKAROUND_10G(efx) EFX_IS10G(efx) | 22 | #define EFX_WORKAROUND_10G(efx) 1 |
23 | #define EFX_WORKAROUND_SFT9001(efx) ((efx)->phy_type == PHY_TYPE_SFT9001A || \ | ||
24 | (efx)->phy_type == PHY_TYPE_SFT9001B) | ||
25 | 23 | ||
26 | /* XAUI resets if link not detected */ | 24 | /* XAUI resets if link not detected */ |
27 | #define EFX_WORKAROUND_5147 EFX_WORKAROUND_ALWAYS | 25 | #define EFX_WORKAROUND_5147 EFX_WORKAROUND_ALWAYS |
@@ -58,9 +56,4 @@ | |||
58 | /* Leak overlength packets rather than free */ | 56 | /* Leak overlength packets rather than free */ |
59 | #define EFX_WORKAROUND_8071 EFX_WORKAROUND_FALCON_A | 57 | #define EFX_WORKAROUND_8071 EFX_WORKAROUND_FALCON_A |
60 | 58 | ||
61 | /* Need to send XNP pages for 100BaseT */ | ||
62 | #define EFX_WORKAROUND_13204 EFX_WORKAROUND_SFT9001 | ||
63 | /* Don't restart AN in near-side loopback */ | ||
64 | #define EFX_WORKAROUND_15195 EFX_WORKAROUND_SFT9001 | ||
65 | |||
66 | #endif /* EFX_WORKAROUNDS_H */ | 59 | #endif /* EFX_WORKAROUNDS_H */ |