8 files changed, 12973 insertions, 0 deletions

diff --git a/drivers/net/qlcnic/Makefile b/drivers/net/qlcnic/Makefile
new file mode 100644
index 00000000000..ddba83ef3f4
--- /dev/null
+++ b/drivers/net/qlcnic/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for Qlogic 1G/10G Ethernet Driver for CNA devices
+#
+
+obj-$(CONFIG_QLCNIC) := qlcnic.o
+
+qlcnic-y := qlcnic_hw.o qlcnic_main.o qlcnic_init.o \
+        qlcnic_ethtool.o qlcnic_ctx.o
diff --git a/drivers/net/qlcnic/qlcnic.h b/drivers/net/qlcnic/qlcnic.h
new file mode 100644
index 00000000000..baf646d98fa
--- /dev/null
+++ b/drivers/net/qlcnic/qlcnic.h
@@ -0,0 +1,1553 @@
+/*
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
+ *
+ * See LICENSE.qlcnic for copyright and licensing details.
+ */
+
+#ifndef _QLCNIC_H_
+#define _QLCNIC_H_
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/in.h>
+#include <linux/tcp.h>
+#include <linux/skbuff.h>
+#include <linux/firmware.h>
+
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/timer.h>
+
+#include <linux/vmalloc.h>
+
+#include <linux/io.h>
+#include <asm/byteorder.h>
+#include <linux/bitops.h>
+#include <linux/if_vlan.h>
+
+#include "qlcnic_hdr.h"
+
+#define _QLCNIC_LINUX_MAJOR 5
+#define _QLCNIC_LINUX_MINOR 0
+#define _QLCNIC_LINUX_SUBVERSION 21
+#define QLCNIC_LINUX_VERSIONID  "5.0.21"
+#define QLCNIC_DRV_IDC_VER  0x01
+#define QLCNIC_DRIVER_VERSION  ((_QLCNIC_LINUX_MAJOR << 16) |\
+                 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
+
+#define QLCNIC_VERSION_CODE(a, b, c)    (((a) << 24) + ((b) << 16) + (c))
+#define _major(v)       (((v) >> 24) & 0xff)
+#define _minor(v)       (((v) >> 16) & 0xff)
+#define _build(v)       ((v) & 0xffff)
+
+/* version in image has weird encoding:
+ *  7:0  - major
+ * 15:8  - minor
+ * 31:16 - build (little endian)
+ */
+#define QLCNIC_DECODE_VERSION(v) \
+        QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
+
+#define QLCNIC_MIN_FW_VERSION     QLCNIC_VERSION_CODE(4, 4, 2)
+#define QLCNIC_NUM_FLASH_SECTORS (64)
+#define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
+#define QLCNIC_FLASH_TOTAL_SIZE  (QLCNIC_NUM_FLASH_SECTORS \
+                                        * QLCNIC_FLASH_SECTOR_SIZE)
+
+#define RCV_DESC_RINGSIZE(rds_ring)     \
+        (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
+#define RCV_BUFF_RINGSIZE(rds_ring)     \
+        (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
+#define STATUS_DESC_RINGSIZE(sds_ring)  \
+        (sizeof(struct status_desc) * (sds_ring)->num_desc)
+#define TX_BUFF_RINGSIZE(tx_ring)       \
+        (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
+#define TX_DESC_RINGSIZE(tx_ring)       \
+        (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
+
+#define QLCNIC_P3P_A0           0x50
+
+#define QLCNIC_IS_REVISION_P3P(REVISION)     (REVISION >= QLCNIC_P3P_A0)
+
+#define FIRST_PAGE_GROUP_START  0
+#define FIRST_PAGE_GROUP_END    0x100000
+
+#define P3P_MAX_MTU                     (9600)
+#define P3P_MIN_MTU                     (68)
+#define QLCNIC_MAX_ETHERHDR                32 /* This contains some padding */
+
+#define QLCNIC_P3P_RX_BUF_MAX_LEN         (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
+#define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN   (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
+#define QLCNIC_CT_DEFAULT_RX_BUF_LEN    2048
+#define QLCNIC_LRO_BUFFER_EXTRA         2048
+
+/* Opcodes to be used with the commands */
+#define TX_ETHER_PKT    0x01
+#define TX_TCP_PKT      0x02
+#define TX_UDP_PKT      0x03
+#define TX_IP_PKT       0x04
+#define TX_TCP_LSO      0x05
+#define TX_TCP_LSO6     0x06
+#define TX_TCPV6_PKT    0x0b
+#define TX_UDPV6_PKT    0x0c
+
+/* Tx defines */
+#define QLCNIC_MAX_FRAGS_PER_TX 14
+#define MAX_TSO_HEADER_DESC     2
+#define MGMT_CMD_DESC_RESV      4
+#define TX_STOP_THRESH          ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
+                                                        + MGMT_CMD_DESC_RESV)
+#define QLCNIC_MAX_TX_TIMEOUTS  2
+
+/*
+ * Following are the states of the Phantom. Phantom will set them and
+ * Host will read to check if the fields are correct.
+ */
+#define PHAN_INITIALIZE_FAILED          0xffff
+#define PHAN_INITIALIZE_COMPLETE        0xff01
+
+/* Host writes the following to notify that it has done the init-handshake */
+#define PHAN_INITIALIZE_ACK             0xf00f
+#define PHAN_PEG_RCV_INITIALIZED        0xff01
+
+#define NUM_RCV_DESC_RINGS      3
+
+#define RCV_RING_NORMAL 0
+#define RCV_RING_JUMBO  1
+
+#define MIN_CMD_DESCRIPTORS             64
+#define MIN_RCV_DESCRIPTORS             64
+#define MIN_JUMBO_DESCRIPTORS           32
+
+#define MAX_CMD_DESCRIPTORS             1024
+#define MAX_RCV_DESCRIPTORS_1G          4096
+#define MAX_RCV_DESCRIPTORS_10G         8192
+#define MAX_RCV_DESCRIPTORS_VF          2048
+#define MAX_JUMBO_RCV_DESCRIPTORS_1G    512
+#define MAX_JUMBO_RCV_DESCRIPTORS_10G   1024
+
+#define DEFAULT_RCV_DESCRIPTORS_1G      2048
+#define DEFAULT_RCV_DESCRIPTORS_10G     4096
+#define DEFAULT_RCV_DESCRIPTORS_VF      1024
+#define MAX_RDS_RINGS                   2
+
+#define get_next_index(index, length)   \
+        (((index) + 1) & ((length) - 1))
+
+/*
+ * Following data structures describe the descriptors that will be used.
+ * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
+ * we are doing LSO (above the 1500 size packet) only.
+ */
+
+#define FLAGS_VLAN_TAGGED       0x10
+#define FLAGS_VLAN_OOB          0x40
+
+#define qlcnic_set_tx_vlan_tci(cmd_desc, v)     \
+        (cmd_desc)->vlan_TCI = cpu_to_le16(v);
+#define qlcnic_set_cmd_desc_port(cmd_desc, var) \
+        ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
+#define qlcnic_set_cmd_desc_ctxid(cmd_desc, var)        \
+        ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
+
+#define qlcnic_set_tx_port(_desc, _port) \
+        ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
+
+#define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
+        ((_desc)->flags_opcode |= \
+        cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
+
+#define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
+        ((_desc)->nfrags__length = \
+        cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
+
+struct cmd_desc_type0 {
+        u8 tcp_hdr_offset;      /* For LSO only */
+        u8 ip_hdr_offset;       /* For LSO only */
+        __le16 flags_opcode;    /* 15:13 unused, 12:7 opcode, 6:0 flags */
+        __le32 nfrags__length;  /* 31:8 total len, 7:0 frag count */
+
+        __le64 addr_buffer2;
+
+        __le16 reference_handle;
+        __le16 mss;
+        u8 port_ctxid;          /* 7:4 ctxid 3:0 port */
+        u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
+        __le16 conn_id;         /* IPSec offoad only */
+
+        __le64 addr_buffer3;
+        __le64 addr_buffer1;
+
+        __le16 buffer_length[4];
+
+        __le64 addr_buffer4;
+
+        u8 eth_addr[ETH_ALEN];
+        __le16 vlan_TCI;
+
+} __attribute__ ((aligned(64)));
+
+/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
+struct rcv_desc {
+        __le16 reference_handle;
+        __le16 reserved;
+        __le32 buffer_length;   /* allocated buffer length (usually 2K) */
+        __le64 addr_buffer;
+} __packed;
+
+/* opcode field in status_desc */
+#define QLCNIC_SYN_OFFLOAD      0x03
+#define QLCNIC_RXPKT_DESC       0x04
+#define QLCNIC_OLD_RXPKT_DESC   0x3f
+#define QLCNIC_RESPONSE_DESC    0x05
+#define QLCNIC_LRO_DESC         0x12
+
+/* for status field in status_desc */
+#define STATUS_CKSUM_LOOP       0
+#define STATUS_CKSUM_OK         2
+
+/* owner bits of status_desc */
+#define STATUS_OWNER_HOST       (0x1ULL << 56)
+#define STATUS_OWNER_PHANTOM    (0x2ULL << 56)
+
+/* Status descriptor:
+   0-3 port, 4-7 status, 8-11 type, 12-27 total_length
+   28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
+   53-55 desc_cnt, 56-57 owner, 58-63 opcode
+ */
+#define qlcnic_get_sts_port(sts_data)   \
+        ((sts_data) & 0x0F)
+#define qlcnic_get_sts_status(sts_data) \
+        (((sts_data) >> 4) & 0x0F)
+#define qlcnic_get_sts_type(sts_data)   \
+        (((sts_data) >> 8) & 0x0F)
+#define qlcnic_get_sts_totallength(sts_data)    \
+        (((sts_data) >> 12) & 0xFFFF)
+#define qlcnic_get_sts_refhandle(sts_data)      \
+        (((sts_data) >> 28) & 0xFFFF)
+#define qlcnic_get_sts_prot(sts_data)   \
+        (((sts_data) >> 44) & 0x0F)
+#define qlcnic_get_sts_pkt_offset(sts_data)     \
+        (((sts_data) >> 48) & 0x1F)
+#define qlcnic_get_sts_desc_cnt(sts_data)       \
+        (((sts_data) >> 53) & 0x7)
+#define qlcnic_get_sts_opcode(sts_data) \
+        (((sts_data) >> 58) & 0x03F)
+
+#define qlcnic_get_lro_sts_refhandle(sts_data)  \
+        ((sts_data) & 0x0FFFF)
+#define qlcnic_get_lro_sts_length(sts_data)     \
+        (((sts_data) >> 16) & 0x0FFFF)
+#define qlcnic_get_lro_sts_l2_hdr_offset(sts_data)      \
+        (((sts_data) >> 32) & 0x0FF)
+#define qlcnic_get_lro_sts_l4_hdr_offset(sts_data)      \
+        (((sts_data) >> 40) & 0x0FF)
+#define qlcnic_get_lro_sts_timestamp(sts_data)  \
+        (((sts_data) >> 48) & 0x1)
+#define qlcnic_get_lro_sts_type(sts_data)       \
+        (((sts_data) >> 49) & 0x7)
+#define qlcnic_get_lro_sts_push_flag(sts_data)          \
+        (((sts_data) >> 52) & 0x1)
+#define qlcnic_get_lro_sts_seq_number(sts_data)         \
+        ((sts_data) & 0x0FFFFFFFF)
+
+
+struct status_desc {
+        __le64 status_desc_data[2];
+} __attribute__ ((aligned(16)));
+
+/* UNIFIED ROMIMAGE */
+#define QLCNIC_UNI_FW_MIN_SIZE          0xc8000
+#define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
+#define QLCNIC_UNI_DIR_SECT_BOOTLD      0x6
+#define QLCNIC_UNI_DIR_SECT_FW          0x7
+
+/*Offsets */
+#define QLCNIC_UNI_CHIP_REV_OFF         10
+#define QLCNIC_UNI_FLAGS_OFF            11
+#define QLCNIC_UNI_BIOS_VERSION_OFF     12
+#define QLCNIC_UNI_BOOTLD_IDX_OFF       27
+#define QLCNIC_UNI_FIRMWARE_IDX_OFF     29
+
+struct uni_table_desc{
+        u32     findex;
+        u32     num_entries;
+        u32     entry_size;
+        u32     reserved[5];
+};
+
+struct uni_data_desc{
+        u32     findex;
+        u32     size;
+        u32     reserved[5];
+};
+
+/* Flash Defines and Structures */
+#define QLCNIC_FLT_LOCATION     0x3F1000
+#define QLCNIC_FW_IMAGE_REGION  0x74
+#define QLCNIC_BOOTLD_REGION    0X72
+struct qlcnic_flt_header {
+        u16 version;
+        u16 len;
+        u16 checksum;
+        u16 reserved;
+};
+
+struct qlcnic_flt_entry {
+        u8 region;
+        u8 reserved0;
+        u8 attrib;
+        u8 reserved1;
+        u32 size;
+        u32 start_addr;
+        u32 end_addr;
+};
+
+/* Magic number to let user know flash is programmed */
+#define QLCNIC_BDINFO_MAGIC 0x12345678
+
+#define QLCNIC_BRDTYPE_P3P_REF_QG       0x0021
+#define QLCNIC_BRDTYPE_P3P_HMEZ         0x0022
+#define QLCNIC_BRDTYPE_P3P_10G_CX4_LP   0x0023
+#define QLCNIC_BRDTYPE_P3P_4_GB         0x0024
+#define QLCNIC_BRDTYPE_P3P_IMEZ         0x0025
+#define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
+#define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
+#define QLCNIC_BRDTYPE_P3P_XG_LOM       0x0028
+#define QLCNIC_BRDTYPE_P3P_4_GB_MM      0x0029
+#define QLCNIC_BRDTYPE_P3P_10G_SFP_CT   0x002a
+#define QLCNIC_BRDTYPE_P3P_10G_SFP_QT   0x002b
+#define QLCNIC_BRDTYPE_P3P_10G_CX4      0x0031
+#define QLCNIC_BRDTYPE_P3P_10G_XFP      0x0032
+#define QLCNIC_BRDTYPE_P3P_10G_TP       0x0080
+
+#define QLCNIC_MSIX_TABLE_OFFSET        0x44
+
+/* Flash memory map */
+#define QLCNIC_BRDCFG_START     0x4000          /* board config */
+#define QLCNIC_BOOTLD_START     0x10000         /* bootld */
+#define QLCNIC_IMAGE_START      0x43000         /* compressed image */
+#define QLCNIC_USER_START       0x3E8000        /* Firmare info */
+
+#define QLCNIC_FW_VERSION_OFFSET        (QLCNIC_USER_START+0x408)
+#define QLCNIC_FW_SIZE_OFFSET           (QLCNIC_USER_START+0x40c)
+#define QLCNIC_FW_SERIAL_NUM_OFFSET     (QLCNIC_USER_START+0x81c)
+#define QLCNIC_BIOS_VERSION_OFFSET      (QLCNIC_USER_START+0x83c)
+
+#define QLCNIC_BRDTYPE_OFFSET           (QLCNIC_BRDCFG_START+0x8)
+#define QLCNIC_FW_MAGIC_OFFSET          (QLCNIC_BRDCFG_START+0x128)
+
+#define QLCNIC_FW_MIN_SIZE              (0x3fffff)
+#define QLCNIC_UNIFIED_ROMIMAGE         0
+#define QLCNIC_FLASH_ROMIMAGE           1
+#define QLCNIC_UNKNOWN_ROMIMAGE         0xff
+
+#define QLCNIC_UNIFIED_ROMIMAGE_NAME    "phanfw.bin"
+#define QLCNIC_FLASH_ROMIMAGE_NAME      "flash"
+
+extern char qlcnic_driver_name[];
+
+/* Number of status descriptors to handle per interrupt */
+#define MAX_STATUS_HANDLE       (64)
+
+/*
+ * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
+ * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
+ */
+struct qlcnic_skb_frag {
+        u64 dma;
+        u64 length;
+};
+
+/*    Following defines are for the state of the buffers    */
+#define QLCNIC_BUFFER_FREE      0
+#define QLCNIC_BUFFER_BUSY      1
+
+/*
+ * There will be one qlcnic_buffer per skb packet.    These will be
+ * used to save the dma info for pci_unmap_page()
+ */
+struct qlcnic_cmd_buffer {
+        struct sk_buff *skb;
+        struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
+        u32 frag_count;
+};
+
+/* In rx_buffer, we do not need multiple fragments as is a single buffer */
+struct qlcnic_rx_buffer {
+        u16 ref_handle;
+        struct sk_buff *skb;
+        struct list_head list;
+        u64 dma;
+};
+
+/* Board types */
+#define QLCNIC_GBE      0x01
+#define QLCNIC_XGBE     0x02
+
+/*
+ * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
+ * adjusted based on configured MTU.
+ */
+#define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
+#define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
+
+#define QLCNIC_INTR_DEFAULT                     0x04
+#define QLCNIC_CONFIG_INTR_COALESCE             3
+
+struct qlcnic_nic_intr_coalesce {
+        u8      type;
+        u8      sts_ring_mask;
+        u16     rx_packets;
+        u16     rx_time_us;
+        u16     flag;
+        u32     timer_out;
+};
+
+struct qlcnic_dump_template_hdr {
+        __le32  type;
+        __le32  offset;
+        __le32  size;
+        __le32  cap_mask;
+        __le32  num_entries;
+        __le32  version;
+        __le32  timestamp;
+        __le32  checksum;
+        __le32  drv_cap_mask;
+        __le32  sys_info[3];
+        __le32  saved_state[16];
+        __le32  cap_sizes[8];
+        __le32  rsvd[0];
+};
+
+struct qlcnic_fw_dump {
+        u8      clr;    /* flag to indicate if dump is cleared */
+        u8      enable; /* enable/disable dump */
+        u32     size;   /* total size of the dump */
+        void    *data;  /* dump data area */
+        struct  qlcnic_dump_template_hdr *tmpl_hdr;
+};
+
+/*
+ * One hardware_context{} per adapter
+ * contains interrupt info as well shared hardware info.
+ */
+struct qlcnic_hardware_context {
+        void __iomem *pci_base0;
+        void __iomem *ocm_win_crb;
+
+        unsigned long pci_len0;
+
+        rwlock_t crb_lock;
+        struct mutex mem_lock;
+
+        u8 revision_id;
+        u8 pci_func;
+        u8 linkup;
+        u8 loopback_state;
+        u16 port_type;
+        u16 board_type;
+
+        struct qlcnic_nic_intr_coalesce coal;
+        struct qlcnic_fw_dump fw_dump;
+};
+
+struct qlcnic_adapter_stats {
+        u64  xmitcalled;
+        u64  xmitfinished;
+        u64  rxdropped;
+        u64  txdropped;
+        u64  csummed;
+        u64  rx_pkts;
+        u64  lro_pkts;
+        u64  rxbytes;
+        u64  txbytes;
+        u64  lrobytes;
+        u64  lso_frames;
+        u64  xmit_on;
+        u64  xmit_off;
+        u64  skb_alloc_failure;
+        u64  null_rxbuf;
+        u64  rx_dma_map_error;
+        u64  tx_dma_map_error;
+};
+
+/*
+ * Rcv Descriptor Context. One such per Rcv Descriptor. There may
+ * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
+ */
+struct qlcnic_host_rds_ring {
+        void __iomem *crb_rcv_producer;
+        struct rcv_desc *desc_head;
+        struct qlcnic_rx_buffer *rx_buf_arr;
+        u32 num_desc;
+        u32 producer;
+        u32 dma_size;
+        u32 skb_size;
+        u32 flags;
+        struct list_head free_list;
+        spinlock_t lock;
+        dma_addr_t phys_addr;
+} ____cacheline_internodealigned_in_smp;
+
+struct qlcnic_host_sds_ring {
+        u32 consumer;
+        u32 num_desc;
+        void __iomem *crb_sts_consumer;
+
+        struct status_desc *desc_head;
+        struct qlcnic_adapter *adapter;
+        struct napi_struct napi;
+        struct list_head free_list[NUM_RCV_DESC_RINGS];
+
+        void __iomem *crb_intr_mask;
+        int irq;
+
+        dma_addr_t phys_addr;
+        char name[IFNAMSIZ+4];
+} ____cacheline_internodealigned_in_smp;
+
+struct qlcnic_host_tx_ring {
+        u32 producer;
+        u32 sw_consumer;
+        u32 num_desc;
+        void __iomem *crb_cmd_producer;
+        struct cmd_desc_type0 *desc_head;
+        struct qlcnic_cmd_buffer *cmd_buf_arr;
+        __le32 *hw_consumer;
+
+        dma_addr_t phys_addr;
+        dma_addr_t hw_cons_phys_addr;
+        struct netdev_queue *txq;
+} ____cacheline_internodealigned_in_smp;
+
+/*
+ * Receive context. There is one such structure per instance of the
+ * receive processing. Any state information that is relevant to
+ * the receive, and is must be in this structure. The global data may be
+ * present elsewhere.
+ */
+struct qlcnic_recv_context {
+        struct qlcnic_host_rds_ring *rds_rings;
+        struct qlcnic_host_sds_ring *sds_rings;
+        u32 state;
+        u16 context_id;
+        u16 virt_port;
+
+};
+
+/* HW context creation */
+
+#define QLCNIC_OS_CRB_RETRY_COUNT       4000
+#define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
+        (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
+
+#define QLCNIC_CDRP_CMD_BIT             0x80000000
+
+/*
+ * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
+ * in the crb QLCNIC_CDRP_CRB_OFFSET.
+ */
+#define QLCNIC_CDRP_FORM_RSP(rsp)       (rsp)
+#define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
+
+#define QLCNIC_CDRP_RSP_OK              0x00000001
+#define QLCNIC_CDRP_RSP_FAIL            0x00000002
+#define QLCNIC_CDRP_RSP_TIMEOUT         0x00000003
+
+/*
+ * All commands must have the QLCNIC_CDRP_CMD_BIT set in
+ * the crb QLCNIC_CDRP_CRB_OFFSET.
+ */
+#define QLCNIC_CDRP_FORM_CMD(cmd)       (QLCNIC_CDRP_CMD_BIT | (cmd))
+#define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
+
+#define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
+#define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
+#define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
+#define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
+#define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
+#define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
+#define QLCNIC_CDRP_CMD_CREATE_RX_CTX           0x00000007
+#define QLCNIC_CDRP_CMD_DESTROY_RX_CTX          0x00000008
+#define QLCNIC_CDRP_CMD_CREATE_TX_CTX           0x00000009
+#define QLCNIC_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
+#define QLCNIC_CDRP_CMD_SET_MTU                 0x00000012
+#define QLCNIC_CDRP_CMD_READ_PHY                0x00000013
+#define QLCNIC_CDRP_CMD_WRITE_PHY               0x00000014
+#define QLCNIC_CDRP_CMD_READ_HW_REG             0x00000015
+#define QLCNIC_CDRP_CMD_GET_FLOW_CTL            0x00000016
+#define QLCNIC_CDRP_CMD_SET_FLOW_CTL            0x00000017
+#define QLCNIC_CDRP_CMD_READ_MAX_MTU            0x00000018
+#define QLCNIC_CDRP_CMD_READ_MAX_LRO            0x00000019
+#define QLCNIC_CDRP_CMD_MAC_ADDRESS             0x0000001f
+
+#define QLCNIC_CDRP_CMD_GET_PCI_INFO            0x00000020
+#define QLCNIC_CDRP_CMD_GET_NIC_INFO            0x00000021
+#define QLCNIC_CDRP_CMD_SET_NIC_INFO            0x00000022
+#define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY  0x00000024
+#define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH          0x00000025
+#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS      0x00000026
+#define QLCNIC_CDRP_CMD_SET_PORTMIRRORING       0x00000027
+#define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH       0x00000028
+#define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
+#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS       0x0000002a
+#define QLCNIC_CDRP_CMD_CONFIG_PORT             0x0000002E
+#define QLCNIC_CDRP_CMD_TEMP_SIZE               0x0000002f
+#define QLCNIC_CDRP_CMD_GET_TEMP_HDR            0x00000030
+
+#define QLCNIC_RCODE_SUCCESS            0
+#define QLCNIC_RCODE_NOT_SUPPORTED      9
+#define QLCNIC_RCODE_TIMEOUT            17
+#define QLCNIC_DESTROY_CTX_RESET        0
+
+/*
+ * Capabilities Announced
+ */
+#define QLCNIC_CAP0_LEGACY_CONTEXT      (1)
+#define QLCNIC_CAP0_LEGACY_MN           (1 << 2)
+#define QLCNIC_CAP0_LSO                 (1 << 6)
+#define QLCNIC_CAP0_JUMBO_CONTIGUOUS    (1 << 7)
+#define QLCNIC_CAP0_LRO_CONTIGUOUS      (1 << 8)
+#define QLCNIC_CAP0_VALIDOFF            (1 << 11)
+
+/*
+ * Context state
+ */
+#define QLCNIC_HOST_CTX_STATE_FREED     0
+#define QLCNIC_HOST_CTX_STATE_ACTIVE    2
+
+/*
+ * Rx context
+ */
+
+struct qlcnic_hostrq_sds_ring {
+        __le64 host_phys_addr;  /* Ring base addr */
+        __le32 ring_size;               /* Ring entries */
+        __le16 msi_index;
+        __le16 rsvd;            /* Padding */
+} __packed;
+
+struct qlcnic_hostrq_rds_ring {
+        __le64 host_phys_addr;  /* Ring base addr */
+        __le64 buff_size;               /* Packet buffer size */
+        __le32 ring_size;               /* Ring entries */
+        __le32 ring_kind;               /* Class of ring */
+} __packed;
+
+struct qlcnic_hostrq_rx_ctx {
+        __le64 host_rsp_dma_addr;       /* Response dma'd here */
+        __le32 capabilities[4]; /* Flag bit vector */
+        __le32 host_int_crb_mode;       /* Interrupt crb usage */
+        __le32 host_rds_crb_mode;       /* RDS crb usage */
+        /* These ring offsets are relative to data[0] below */
+        __le32 rds_ring_offset; /* Offset to RDS config */
+        __le32 sds_ring_offset; /* Offset to SDS config */
+        __le16 num_rds_rings;   /* Count of RDS rings */
+        __le16 num_sds_rings;   /* Count of SDS rings */
+        __le16 valid_field_offset;
+        u8  txrx_sds_binding;
+        u8  msix_handler;
+        u8  reserved[128];      /* reserve space for future expansion*/
+        /* MUST BE 64-bit aligned.
+           The following is packed:
+           - N hostrq_rds_rings
+           - N hostrq_sds_rings */
+        char data[0];
+} __packed;
+
+struct qlcnic_cardrsp_rds_ring{
+        __le32 host_producer_crb;       /* Crb to use */
+        __le32 rsvd1;           /* Padding */
+} __packed;
+
+struct qlcnic_cardrsp_sds_ring {
+        __le32 host_consumer_crb;       /* Crb to use */
+        __le32 interrupt_crb;   /* Crb to use */
+} __packed;
+
+struct qlcnic_cardrsp_rx_ctx {
+        /* These ring offsets are relative to data[0] below */
+        __le32 rds_ring_offset; /* Offset to RDS config */
+        __le32 sds_ring_offset; /* Offset to SDS config */
+        __le32 host_ctx_state;  /* Starting State */
+        __le32 num_fn_per_port; /* How many PCI fn share the port */
+        __le16 num_rds_rings;   /* Count of RDS rings */
+        __le16 num_sds_rings;   /* Count of SDS rings */
+        __le16 context_id;              /* Handle for context */
+        u8  phys_port;          /* Physical id of port */
+        u8  virt_port;          /* Virtual/Logical id of port */
+        u8  reserved[128];      /* save space for future expansion */
+        /*  MUST BE 64-bit aligned.
+           The following is packed:
+           - N cardrsp_rds_rings
+           - N cardrs_sds_rings */
+        char data[0];
+} __packed;
+
+#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
+        (sizeof(HOSTRQ_RX) +                                    \
+        (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) +           \
+        (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
+
+#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
+        (sizeof(CARDRSP_RX) +                                   \
+        (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) +          \
+        (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
+
+/*
+ * Tx context
+ */
+
+struct qlcnic_hostrq_cds_ring {
+        __le64 host_phys_addr;  /* Ring base addr */
+        __le32 ring_size;               /* Ring entries */
+        __le32 rsvd;            /* Padding */
+} __packed;
+
+struct qlcnic_hostrq_tx_ctx {
+        __le64 host_rsp_dma_addr;       /* Response dma'd here */
+        __le64 cmd_cons_dma_addr;       /*  */
+        __le64 dummy_dma_addr;  /*  */
+        __le32 capabilities[4]; /* Flag bit vector */
+        __le32 host_int_crb_mode;       /* Interrupt crb usage */
+        __le32 rsvd1;           /* Padding */
+        __le16 rsvd2;           /* Padding */
+        __le16 interrupt_ctl;
+        __le16 msi_index;
+        __le16 rsvd3;           /* Padding */
+        struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
+        u8  reserved[128];      /* future expansion */
+} __packed;
+
+struct qlcnic_cardrsp_cds_ring {
+        __le32 host_producer_crb;       /* Crb to use */
+        __le32 interrupt_crb;   /* Crb to use */
+} __packed;
+
+struct qlcnic_cardrsp_tx_ctx {
+        __le32 host_ctx_state;  /* Starting state */
+        __le16 context_id;              /* Handle for context */
+        u8  phys_port;          /* Physical id of port */
+        u8  virt_port;          /* Virtual/Logical id of port */
+        struct qlcnic_cardrsp_cds_ring cds_ring;        /* Card cds settings */
+        u8  reserved[128];      /* future expansion */
+} __packed;
+
+#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
+#define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
+
+/* CRB */
+
+#define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
+#define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
+#define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
+#define QLCNIC_HOST_RDS_CRB_MODE_MAX    3
+
+#define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
+#define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
+#define QLCNIC_HOST_INT_CRB_MODE_NORX   2
+#define QLCNIC_HOST_INT_CRB_MODE_NOTX   3
+#define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
+
+
+/* MAC */
+
+#define MC_COUNT_P3P    38
+
+#define QLCNIC_MAC_NOOP 0
+#define QLCNIC_MAC_ADD  1
+#define QLCNIC_MAC_DEL  2
+#define QLCNIC_MAC_VLAN_ADD     3
+#define QLCNIC_MAC_VLAN_DEL     4
+
+struct qlcnic_mac_list_s {
+        struct list_head list;
+        uint8_t mac_addr[ETH_ALEN+2];
+};
+
+#define QLCNIC_HOST_REQUEST     0x13
+#define QLCNIC_REQUEST          0x14
+
+#define QLCNIC_MAC_EVENT        0x1
+
+#define QLCNIC_IP_UP            2
+#define QLCNIC_IP_DOWN          3
+
+#define QLCNIC_ILB_MODE         0x1
+#define QLCNIC_ELB_MODE         0x2
+
+#define QLCNIC_LINKEVENT        0x1
+#define QLCNIC_LB_RESPONSE      0x2
+#define QLCNIC_IS_LB_CONFIGURED(VAL)    \
+                (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
+
+/*
+ * Driver --> Firmware
+ */
+#define QLCNIC_H2C_OPCODE_CONFIG_RSS                    0x1
+#define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE          0x3
+#define QLCNIC_H2C_OPCODE_CONFIG_LED                    0x4
+#define QLCNIC_H2C_OPCODE_LRO_REQUEST                   0x7
+#define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE          0xc
+#define QLCNIC_H2C_OPCODE_CONFIG_IPADDR         0x12
+
+#define QLCNIC_H2C_OPCODE_GET_LINKEVENT         0x15
+#define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING               0x17
+#define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO         0x18
+#define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK               0x13
+
+/*
+ * Firmware --> Driver
+ */
+
+#define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK               0x8f
+#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE        141
+
+#define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
+#define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
+#define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
+
+#define QLCNIC_LRO_REQUEST_CLEANUP      4
+
+/* Capabilites received */
+#define QLCNIC_FW_CAPABILITY_TSO                BIT_1
+#define QLCNIC_FW_CAPABILITY_BDG                BIT_8
+#define QLCNIC_FW_CAPABILITY_FVLANTX            BIT_9
+#define QLCNIC_FW_CAPABILITY_HW_LRO             BIT_10
+#define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK     BIT_27
+
+/* module types */
+#define LINKEVENT_MODULE_NOT_PRESENT                    1
+#define LINKEVENT_MODULE_OPTICAL_UNKNOWN                2
+#define LINKEVENT_MODULE_OPTICAL_SRLR                   3
+#define LINKEVENT_MODULE_OPTICAL_LRM                    4
+#define LINKEVENT_MODULE_OPTICAL_SFP_1G                 5
+#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE       6
+#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN    7
+#define LINKEVENT_MODULE_TWINAX                         8
+
+#define LINKSPEED_10GBPS        10000
+#define LINKSPEED_1GBPS         1000
+#define LINKSPEED_100MBPS       100
+#define LINKSPEED_10MBPS        10
+
+#define LINKSPEED_ENCODED_10MBPS        0
+#define LINKSPEED_ENCODED_100MBPS       1
+#define LINKSPEED_ENCODED_1GBPS         2
+
+#define LINKEVENT_AUTONEG_DISABLED      0
+#define LINKEVENT_AUTONEG_ENABLED       1
+
+#define LINKEVENT_HALF_DUPLEX           0
+#define LINKEVENT_FULL_DUPLEX           1
+
+#define LINKEVENT_LINKSPEED_MBPS        0
+#define LINKEVENT_LINKSPEED_ENCODED     1
+
+/* firmware response header:
+ *      63:58 - message type
+ *      57:56 - owner
+ *      55:53 - desc count
+ *      52:48 - reserved
+ *      47:40 - completion id
+ *      39:32 - opcode
+ *      31:16 - error code
+ *      15:00 - reserved
+ */
+#define qlcnic_get_nic_msg_opcode(msg_hdr)      \
+        ((msg_hdr >> 32) & 0xFF)
+
+struct qlcnic_fw_msg {
+        union {
+                struct {
+                        u64 hdr;
+                        u64 body[7];
+                };
+                u64 words[8];
+        };
+};
+
+struct qlcnic_nic_req {
+        __le64 qhdr;
+        __le64 req_hdr;
+        __le64 words[6];
+} __packed;
+
+struct qlcnic_mac_req {
+        u8 op;
+        u8 tag;
+        u8 mac_addr[6];
+};
+
+struct qlcnic_vlan_req {
+        __le16 vlan_id;
+        __le16 rsvd[3];
+} __packed;
+
+struct qlcnic_ipaddr {
+        __be32 ipv4;
+        __be32 ipv6[4];
+};
+
+#define QLCNIC_MSI_ENABLED              0x02
+#define QLCNIC_MSIX_ENABLED             0x04
+#define QLCNIC_LRO_ENABLED              0x08
+#define QLCNIC_LRO_DISABLED             0x00
+#define QLCNIC_BRIDGE_ENABLED           0X10
+#define QLCNIC_DIAG_ENABLED             0x20
+#define QLCNIC_ESWITCH_ENABLED          0x40
+#define QLCNIC_ADAPTER_INITIALIZED      0x80
+#define QLCNIC_TAGGING_ENABLED          0x100
+#define QLCNIC_MACSPOOF                 0x200
+#define QLCNIC_MAC_OVERRIDE_DISABLED    0x400
+#define QLCNIC_PROMISC_DISABLED         0x800
+#define QLCNIC_NEED_FLR                 0x1000
+#define QLCNIC_FW_RESET_OWNER           0x2000
+#define QLCNIC_IS_MSI_FAMILY(adapter) \
+        ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
+
+#define QLCNIC_DEF_NUM_STS_DESC_RINGS   4
+#define QLCNIC_MSIX_TBL_SPACE           8192
+#define QLCNIC_PCI_REG_MSIX_TBL         0x44
+#define QLCNIC_MSIX_TBL_PGSIZE          4096
+
+#define QLCNIC_NETDEV_WEIGHT    128
+#define QLCNIC_ADAPTER_UP_MAGIC 777
+
+#define __QLCNIC_FW_ATTACHED            0
+#define __QLCNIC_DEV_UP                 1
+#define __QLCNIC_RESETTING              2
+#define __QLCNIC_START_FW               4
+#define __QLCNIC_AER                    5
+#define __QLCNIC_DIAG_RES_ALLOC         6
+
+#define QLCNIC_INTERRUPT_TEST           1
+#define QLCNIC_LOOPBACK_TEST            2
+#define QLCNIC_LED_TEST         3
+
+#define QLCNIC_FILTER_AGE       80
+#define QLCNIC_READD_AGE        20
+#define QLCNIC_LB_MAX_FILTERS   64
+
+/* QLCNIC Driver Error Code */
+#define QLCNIC_FW_NOT_RESPOND           51
+#define QLCNIC_TEST_IN_PROGRESS         52
+#define QLCNIC_UNDEFINED_ERROR          53
+#define QLCNIC_LB_CABLE_NOT_CONN        54
+
+struct qlcnic_filter {
+        struct hlist_node fnode;
+        u8 faddr[ETH_ALEN];
+        __le16 vlan_id;
+        unsigned long ftime;
+};
+
+struct qlcnic_filter_hash {
+        struct hlist_head *fhead;
+        u8 fnum;
+        u8 fmax;
+};
+
+struct qlcnic_adapter {
+        struct qlcnic_hardware_context *ahw;
+        struct qlcnic_recv_context *recv_ctx;
+        struct qlcnic_host_tx_ring *tx_ring;
+        struct net_device *netdev;
+        struct pci_dev *pdev;
+
+        unsigned long state;
+        u32 flags;
+
+        u16 num_txd;
+        u16 num_rxd;
+        u16 num_jumbo_rxd;
+        u16 max_rxd;
+        u16 max_jumbo_rxd;
+
+        u8 max_rds_rings;
+        u8 max_sds_rings;
+        u8 msix_supported;
+        u8 portnum;
+        u8 physical_port;
+        u8 reset_context;
+
+        u8 mc_enabled;
+        u8 max_mc_count;
+        u8 fw_wait_cnt;
+        u8 fw_fail_cnt;
+        u8 tx_timeo_cnt;
+        u8 need_fw_reset;
+
+        u8 has_link_events;
+        u8 fw_type;
+        u16 tx_context_id;
+        u16 is_up;
+
+        u16 link_speed;
+        u16 link_duplex;
+        u16 link_autoneg;
+        u16 module_type;
+
+        u16 op_mode;
+        u16 switch_mode;
+        u16 max_tx_ques;
+        u16 max_rx_ques;
+        u16 max_mtu;
+        u16 pvid;
+
+        u32 fw_hal_version;
+        u32 capabilities;
+        u32 irq;
+        u32 temp;
+
+        u32 int_vec_bit;
+        u32 heartbeat;
+
+        u8 max_mac_filters;
+        u8 dev_state;
+        u8 diag_test;
+        char diag_cnt;
+        u8 reset_ack_timeo;
+        u8 dev_init_timeo;
+        u16 msg_enable;
+
+        u8 mac_addr[ETH_ALEN];
+
+        u64 dev_rst_time;
+        u8 mac_learn;
+        unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
+
+        struct qlcnic_npar_info *npars;
+        struct qlcnic_eswitch *eswitch;
+        struct qlcnic_nic_template *nic_ops;
+
+        struct qlcnic_adapter_stats stats;
+        struct list_head mac_list;
+
+        void __iomem    *tgt_mask_reg;
+        void __iomem    *tgt_status_reg;
+        void __iomem    *crb_int_state_reg;
+        void __iomem    *isr_int_vec;
+
+        struct msix_entry *msix_entries;
+
+        struct delayed_work fw_work;
+
+
+        struct qlcnic_filter_hash fhash;
+
+        spinlock_t tx_clean_lock;
+        spinlock_t mac_learn_lock;
+        __le32 file_prd_off;    /*File fw product offset*/
+        u32 fw_version;
+        const struct firmware *fw;
+};
+
+struct qlcnic_info {
+        __le16  pci_func;
+        __le16  op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
+        __le16  phys_port;
+        __le16  switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
+
+        __le32  capabilities;
+        u8      max_mac_filters;
+        u8      reserved1;
+        __le16  max_mtu;
+
+        __le16  max_tx_ques;
+        __le16  max_rx_ques;
+        __le16  min_tx_bw;
+        __le16  max_tx_bw;
+        u8      reserved2[104];
+} __packed;
+
+struct qlcnic_pci_info {
+        __le16  id; /* pci function id */
+        __le16  active; /* 1 = Enabled */
+        __le16  type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
+        __le16  default_port; /* default port number */
+
+        __le16  tx_min_bw; /* Multiple of 100mbpc */
+        __le16  tx_max_bw;
+        __le16  reserved1[2];
+
+        u8      mac[ETH_ALEN];
+        u8      reserved2[106];
+} __packed;
+
+struct qlcnic_npar_info {
+        u16     pvid;
+        u16     min_bw;
+        u16     max_bw;
+        u8      phy_port;
+        u8      type;
+        u8      active;
+        u8      enable_pm;
+        u8      dest_npar;
+        u8      discard_tagged;
+        u8      mac_override;
+        u8      mac_anti_spoof;
+        u8      promisc_mode;
+        u8      offload_flags;
+};
+
+struct qlcnic_eswitch {
+        u8      port;
+        u8      active_vports;
+        u8      active_vlans;
+        u8      active_ucast_filters;
+        u8      max_ucast_filters;
+        u8      max_active_vlans;
+
+        u32     flags;
+#define QLCNIC_SWITCH_ENABLE            BIT_1
+#define QLCNIC_SWITCH_VLAN_FILTERING    BIT_2
+#define QLCNIC_SWITCH_PROMISC_MODE      BIT_3
+#define QLCNIC_SWITCH_PORT_MIRRORING    BIT_4
+};
+
+
+/* Return codes for Error handling */
+#define QL_STATUS_INVALID_PARAM -1
+
+#define MAX_BW                  100     /* % of link speed */
+#define MAX_VLAN_ID             4095
+#define MIN_VLAN_ID             2
+#define DEFAULT_MAC_LEARN       1
+
+#define IS_VALID_VLAN(vlan)     (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
+#define IS_VALID_BW(bw)         (bw <= MAX_BW)
+
+struct qlcnic_pci_func_cfg {
+        u16     func_type;
+        u16     min_bw;
+        u16     max_bw;
+        u16     port_num;
+        u8      pci_func;
+        u8      func_state;
+        u8      def_mac_addr[6];
+};
+
+struct qlcnic_npar_func_cfg {
+        u32     fw_capab;
+        u16     port_num;
+        u16     min_bw;
+        u16     max_bw;
+        u16     max_tx_queues;
+        u16     max_rx_queues;
+        u8      pci_func;
+        u8      op_mode;
+};
+
+struct qlcnic_pm_func_cfg {
+        u8      pci_func;
+        u8      action;
+        u8      dest_npar;
+        u8      reserved[5];
+};
+
+struct qlcnic_esw_func_cfg {
+        u16     vlan_id;
+        u8      op_mode;
+        u8      op_type;
+        u8      pci_func;
+        u8      host_vlan_tag;
+        u8      promisc_mode;
+        u8      discard_tagged;
+        u8      mac_override;
+        u8      mac_anti_spoof;
+        u8      offload_flags;
+        u8      reserved[5];
+};
+
+#define QLCNIC_STATS_VERSION            1
+#define QLCNIC_STATS_PORT               1
+#define QLCNIC_STATS_ESWITCH            2
+#define QLCNIC_QUERY_RX_COUNTER         0
+#define QLCNIC_QUERY_TX_COUNTER         1
+#define QLCNIC_ESW_STATS_NOT_AVAIL      0xffffffffffffffffULL
+
+#define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
+do {    \
+        if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
+            ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
+                (VAL1) = (VAL2); \
+        else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
+                 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
+                        (VAL1) += (VAL2); \
+} while (0)
+
+struct __qlcnic_esw_statistics {
+        __le16 context_id;
+        __le16 version;
+        __le16 size;
+        __le16 unused;
+        __le64 unicast_frames;
+        __le64 multicast_frames;
+        __le64 broadcast_frames;
+        __le64 dropped_frames;
+        __le64 errors;
+        __le64 local_frames;
+        __le64 numbytes;
+        __le64 rsvd[3];
+} __packed;
+
+struct qlcnic_esw_statistics {
+        struct __qlcnic_esw_statistics rx;
+        struct __qlcnic_esw_statistics tx;
+};
+
+struct qlcnic_common_entry_hdr {
+        __le32  type;
+        __le32  offset;
+        __le32  cap_size;
+        u8      mask;
+        u8      rsvd[2];
+        u8      flags;
+} __packed;
+
+struct __crb {
+        __le32  addr;
+        u8      stride;
+        u8      rsvd1[3];
+        __le32  data_size;
+        __le32  no_ops;
+        __le32  rsvd2[4];
+} __packed;
+
+struct __ctrl {
+        __le32  addr;
+        u8      stride;
+        u8      index_a;
+        __le16  timeout;
+        __le32  data_size;
+        __le32  no_ops;
+        u8      opcode;
+        u8      index_v;
+        u8      shl_val;
+        u8      shr_val;
+        __le32  val1;
+        __le32  val2;
+        __le32  val3;
+} __packed;
+
+struct __cache {
+        __le32  addr;
+        __le16  stride;
+        __le16  init_tag_val;
+        __le32  size;
+        __le32  no_ops;
+        __le32  ctrl_addr;
+        __le32  ctrl_val;
+        __le32  read_addr;
+        u8      read_addr_stride;
+        u8      read_addr_num;
+        u8      rsvd1[2];
+} __packed;
+
+struct __ocm {
+        u8      rsvd[8];
+        __le32  size;
+        __le32  no_ops;
+        u8      rsvd1[8];
+        __le32  read_addr;
+        __le32  read_addr_stride;
+} __packed;
+
+struct __mem {
+        u8      rsvd[24];
+        __le32  addr;
+        __le32  size;
+} __packed;
+
+struct __mux {
+        __le32  addr;
+        u8      rsvd[4];
+        __le32  size;
+        __le32  no_ops;
+        __le32  val;
+        __le32  val_stride;
+        __le32  read_addr;
+        u8      rsvd2[4];
+} __packed;
+
+struct __queue {
+        __le32  sel_addr;
+        __le16  stride;
+        u8      rsvd[2];
+        __le32  size;
+        __le32  no_ops;
+        u8      rsvd2[8];
+        __le32  read_addr;
+        u8      read_addr_stride;
+        u8      read_addr_cnt;
+        u8      rsvd3[2];
+} __packed;
+
+struct qlcnic_dump_entry {
+        struct qlcnic_common_entry_hdr hdr;
+        union {
+                struct __crb    crb;
+                struct __cache  cache;
+                struct __ocm    ocm;
+                struct __mem    mem;
+                struct __mux    mux;
+                struct __queue  que;
+                struct __ctrl   ctrl;
+        } region;
+} __packed;
+
+enum op_codes {
+        QLCNIC_DUMP_NOP         = 0,
+        QLCNIC_DUMP_READ_CRB    = 1,
+        QLCNIC_DUMP_READ_MUX    = 2,
+        QLCNIC_DUMP_QUEUE       = 3,
+        QLCNIC_DUMP_BRD_CONFIG  = 4,
+        QLCNIC_DUMP_READ_OCM    = 6,
+        QLCNIC_DUMP_PEG_REG     = 7,
+        QLCNIC_DUMP_L1_DTAG     = 8,
+        QLCNIC_DUMP_L1_ITAG     = 9,
+        QLCNIC_DUMP_L1_DATA     = 11,
+        QLCNIC_DUMP_L1_INST     = 12,
+        QLCNIC_DUMP_L2_DTAG     = 21,
+        QLCNIC_DUMP_L2_ITAG     = 22,
+        QLCNIC_DUMP_L2_DATA     = 23,
+        QLCNIC_DUMP_L2_INST     = 24,
+        QLCNIC_DUMP_READ_ROM    = 71,
+        QLCNIC_DUMP_READ_MEM    = 72,
+        QLCNIC_DUMP_READ_CTRL   = 98,
+        QLCNIC_DUMP_TLHDR       = 99,
+        QLCNIC_DUMP_RDEND       = 255
+};
+
+#define QLCNIC_DUMP_WCRB        BIT_0
+#define QLCNIC_DUMP_RWCRB       BIT_1
+#define QLCNIC_DUMP_ANDCRB      BIT_2
+#define QLCNIC_DUMP_ORCRB       BIT_3
+#define QLCNIC_DUMP_POLLCRB     BIT_4
+#define QLCNIC_DUMP_RD_SAVE     BIT_5
+#define QLCNIC_DUMP_WRT_SAVED   BIT_6
+#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
+#define QLCNIC_DUMP_SKIP        BIT_7
+
+#define QLCNIC_DUMP_MASK_MIN            3
+#define QLCNIC_DUMP_MASK_DEF            0x1f
+#define QLCNIC_DUMP_MASK_MAX            0xff
+#define QLCNIC_FORCE_FW_DUMP_KEY        0xdeadfeed
+#define QLCNIC_ENABLE_FW_DUMP           0xaddfeed
+#define QLCNIC_DISABLE_FW_DUMP          0xbadfeed
+
+struct qlcnic_dump_operations {
+        enum op_codes opcode;
+        u32 (*handler)(struct qlcnic_adapter *,
+                        struct qlcnic_dump_entry *, u32 *);
+};
+
+int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
+int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
+
+u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
+int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
+int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
+int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
+void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
+void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
+
+#define ADDR_IN_RANGE(addr, low, high)  \
+        (((addr) < (high)) && ((addr) >= (low)))
+
+#define QLCRD32(adapter, off) \
+        (qlcnic_hw_read_wx_2M(adapter, off))
+#define QLCWR32(adapter, off, val) \
+        (qlcnic_hw_write_wx_2M(adapter, off, val))
+
+int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
+void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
+
+#define qlcnic_rom_lock(a)      \
+        qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
+#define qlcnic_rom_unlock(a)    \
+        qlcnic_pcie_sem_unlock((a), 2)
+#define qlcnic_phy_lock(a)      \
+        qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
+#define qlcnic_phy_unlock(a)    \
+        qlcnic_pcie_sem_unlock((a), 3)
+#define qlcnic_api_lock(a)      \
+        qlcnic_pcie_sem_lock((a), 5, 0)
+#define qlcnic_api_unlock(a)    \
+        qlcnic_pcie_sem_unlock((a), 5)
+#define qlcnic_sw_lock(a)       \
+        qlcnic_pcie_sem_lock((a), 6, 0)
+#define qlcnic_sw_unlock(a)     \
+        qlcnic_pcie_sem_unlock((a), 6)
+#define crb_win_lock(a) \
+        qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
+#define crb_win_unlock(a)       \
+        qlcnic_pcie_sem_unlock((a), 7)
+
+int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
+int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
+int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
+void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
+void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
+int qlcnic_dump_fw(struct qlcnic_adapter *);
+
+/* Functions from qlcnic_init.c */
+int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
+int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
+void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
+void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
+int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
+int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
+int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
+
+int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
+int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
+                                u8 *bytes, size_t size);
+int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
+void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
+
+void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
+
+int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
+void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
+
+int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
+void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
+
+void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
+void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
+void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
+
+int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
+void qlcnic_watchdog_task(struct work_struct *work);
+void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_rds_ring *rds_ring);
+int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
+void qlcnic_set_multi(struct net_device *netdev);
+void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
+int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
+int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
+int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
+int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
+int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
+void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
+
+int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
+int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
+u32 qlcnic_fix_features(struct net_device *netdev, u32 features);
+int qlcnic_set_features(struct net_device *netdev, u32 features);
+int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
+int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
+int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
+void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_tx_ring *tx_ring);
+void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
+void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
+void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter);
+int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode);
+
+/* Functions from qlcnic_ethtool.c */
+int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]);
+
+/* Functions from qlcnic_main.c */
+int qlcnic_reset_context(struct qlcnic_adapter *);
+u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
+        u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
+void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
+int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
+netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
+int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
+int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
+void qlcnic_dev_request_reset(struct qlcnic_adapter *);
+void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
+
+/* Management functions */
+int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
+int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
+int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
+int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
+
+/*  eSwitch management functions */
+int qlcnic_config_switch_port(struct qlcnic_adapter *,
+                                struct qlcnic_esw_func_cfg *);
+int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
+                                struct qlcnic_esw_func_cfg *);
+int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
+int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
+                                        struct __qlcnic_esw_statistics *);
+int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
+                                        struct __qlcnic_esw_statistics *);
+int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
+extern int qlcnic_config_tso;
+
+/*
+ * QLOGIC Board information
+ */
+
+#define QLCNIC_MAX_BOARD_NAME_LEN 100
+struct qlcnic_brdinfo {
+        unsigned short  vendor;
+        unsigned short  device;
+        unsigned short  sub_vendor;
+        unsigned short  sub_device;
+        char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
+};
+
+static const struct qlcnic_brdinfo qlcnic_boards[] = {
+        {0x1077, 0x8020, 0x1077, 0x203,
+                "8200 Series Single Port 10GbE Converged Network Adapter "
+                "(TCP/IP Networking)"},
+        {0x1077, 0x8020, 0x1077, 0x207,
+                "8200 Series Dual Port 10GbE Converged Network Adapter "
+                "(TCP/IP Networking)"},
+        {0x1077, 0x8020, 0x1077, 0x20b,
+                "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
+        {0x1077, 0x8020, 0x1077, 0x20c,
+                "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
+        {0x1077, 0x8020, 0x1077, 0x20f,
+                "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
+        {0x1077, 0x8020, 0x103c, 0x3733,
+                "NC523SFP 10Gb 2-port Server Adapter"},
+        {0x1077, 0x8020, 0x103c, 0x3346,
+                "CN1000Q Dual Port Converged Network Adapter"},
+        {0x1077, 0x8020, 0x1077, 0x210,
+                "QME8242-k 10GbE Dual Port Mezzanine Card"},
+        {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
+};
+
+#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
+
+static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
+{
+        if (likely(tx_ring->producer < tx_ring->sw_consumer))
+                return tx_ring->sw_consumer - tx_ring->producer;
+        else
+                return tx_ring->sw_consumer + tx_ring->num_desc -
+                                tx_ring->producer;
+}
+
+extern const struct ethtool_ops qlcnic_ethtool_ops;
+
+struct qlcnic_nic_template {
+        int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
+        int (*config_led) (struct qlcnic_adapter *, u32, u32);
+        int (*start_firmware) (struct qlcnic_adapter *);
+};
+
+#define QLCDB(adapter, lvl, _fmt, _args...) do {        \
+        if (NETIF_MSG_##lvl & adapter->msg_enable)      \
+                printk(KERN_INFO "%s: %s: " _fmt,       \
+                         dev_name(&adapter->pdev->dev), \
+                        __func__, ##_args);             \
+        } while (0)
+
+#endif                          /* __QLCNIC_H_ */
diff --git a/drivers/net/qlcnic/qlcnic_ctx.c b/drivers/net/qlcnic/qlcnic_ctx.c
new file mode 100644
index 00000000000..b0d32ddd2cc
--- /dev/null
+++ b/drivers/net/qlcnic/qlcnic_ctx.c
@@ -0,0 +1,1117 @@
+/*
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
+ *
+ * See LICENSE.qlcnic for copyright and licensing details.
+ */
+
+#include "qlcnic.h"
+
+static u32
+qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
+{
+        u32 rsp;
+        int timeout = 0;
+
+        do {
+                /* give atleast 1ms for firmware to respond */
+                msleep(1);
+
+                if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
+                        return QLCNIC_CDRP_RSP_TIMEOUT;
+
+                rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET);
+        } while (!QLCNIC_CDRP_IS_RSP(rsp));
+
+        return rsp;
+}
+
+u32
+qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
+        u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
+{
+        u32 rsp;
+        u32 signature;
+        u32 rcode = QLCNIC_RCODE_SUCCESS;
+        struct pci_dev *pdev = adapter->pdev;
+
+        signature = QLCNIC_CDRP_SIGNATURE_MAKE(pci_fn, version);
+
+        /* Acquire semaphore before accessing CRB */
+        if (qlcnic_api_lock(adapter))
+                return QLCNIC_RCODE_TIMEOUT;
+
+        QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
+        QLCWR32(adapter, QLCNIC_ARG1_CRB_OFFSET, arg1);
+        QLCWR32(adapter, QLCNIC_ARG2_CRB_OFFSET, arg2);
+        QLCWR32(adapter, QLCNIC_ARG3_CRB_OFFSET, arg3);
+        QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET, QLCNIC_CDRP_FORM_CMD(cmd));
+
+        rsp = qlcnic_poll_rsp(adapter);
+
+        if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
+                dev_err(&pdev->dev, "card response timeout.\n");
+                rcode = QLCNIC_RCODE_TIMEOUT;
+        } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
+                rcode = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
+                dev_err(&pdev->dev, "failed card response code:0x%x\n",
+                                rcode);
+        }
+
+        /* Release semaphore */
+        qlcnic_api_unlock(adapter);
+
+        return rcode;
+}
+
+static uint32_t qlcnic_temp_checksum(uint32_t *temp_buffer, u16 temp_size)
+{
+        uint64_t sum = 0;
+        int count = temp_size / sizeof(uint32_t);
+        while (count-- > 0)
+                sum += *temp_buffer++;
+        while (sum >> 32)
+                sum = (sum & 0xFFFFFFFF) + (sum >> 32);
+        return ~sum;
+}
+
+int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter)
+{
+        int err, i;
+        u16 temp_size;
+        void *tmp_addr;
+        u32 version, csum, *template, *tmp_buf;
+        struct qlcnic_hardware_context *ahw;
+        struct qlcnic_dump_template_hdr *tmpl_hdr, *tmp_tmpl;
+        dma_addr_t tmp_addr_t = 0;
+
+        ahw = adapter->ahw;
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        0,
+                        0,
+                        0,
+                        QLCNIC_CDRP_CMD_TEMP_SIZE);
+        if (err != QLCNIC_RCODE_SUCCESS) {
+                err = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
+                dev_info(&adapter->pdev->dev,
+                        "Can't get template size %d\n", err);
+                err = -EIO;
+                return err;
+        }
+        version = QLCRD32(adapter, QLCNIC_ARG3_CRB_OFFSET);
+        temp_size = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET);
+        if (!temp_size)
+                return -EIO;
+
+        tmp_addr = dma_alloc_coherent(&adapter->pdev->dev, temp_size,
+                        &tmp_addr_t, GFP_KERNEL);
+        if (!tmp_addr) {
+                dev_err(&adapter->pdev->dev,
+                        "Can't get memory for FW dump template\n");
+                return -ENOMEM;
+        }
+        err = qlcnic_issue_cmd(adapter,
+                adapter->ahw->pci_func,
+                adapter->fw_hal_version,
+                LSD(tmp_addr_t),
+                MSD(tmp_addr_t),
+                temp_size,
+                QLCNIC_CDRP_CMD_GET_TEMP_HDR);
+
+        if (err != QLCNIC_RCODE_SUCCESS) {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to get mini dump template header %d\n", err);
+                err = -EIO;
+                goto error;
+        }
+        tmp_tmpl = tmp_addr;
+        csum = qlcnic_temp_checksum((uint32_t *) tmp_addr, temp_size);
+        if (csum) {
+                dev_err(&adapter->pdev->dev,
+                        "Template header checksum validation failed\n");
+                err = -EIO;
+                goto error;
+        }
+        ahw->fw_dump.tmpl_hdr = vzalloc(temp_size);
+        if (!ahw->fw_dump.tmpl_hdr) {
+                err = -EIO;
+                goto error;
+        }
+        tmp_buf = tmp_addr;
+        template = (u32 *) ahw->fw_dump.tmpl_hdr;
+        for (i = 0; i < temp_size/sizeof(u32); i++)
+                *template++ = __le32_to_cpu(*tmp_buf++);
+
+        tmpl_hdr = ahw->fw_dump.tmpl_hdr;
+        tmpl_hdr->drv_cap_mask = QLCNIC_DUMP_MASK_DEF;
+        ahw->fw_dump.enable = 1;
+error:
+        dma_free_coherent(&adapter->pdev->dev, temp_size, tmp_addr, tmp_addr_t);
+        return err;
+}
+
+int
+qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
+{
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        if (recv_ctx->state == QLCNIC_HOST_CTX_STATE_ACTIVE) {
+                if (qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        recv_ctx->context_id,
+                        mtu,
+                        0,
+                        QLCNIC_CDRP_CMD_SET_MTU)) {
+
+                        dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
+                        return -EIO;
+                }
+        }
+
+        return 0;
+}
+
+static int
+qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
+{
+        void *addr;
+        struct qlcnic_hostrq_rx_ctx *prq;
+        struct qlcnic_cardrsp_rx_ctx *prsp;
+        struct qlcnic_hostrq_rds_ring *prq_rds;
+        struct qlcnic_hostrq_sds_ring *prq_sds;
+        struct qlcnic_cardrsp_rds_ring *prsp_rds;
+        struct qlcnic_cardrsp_sds_ring *prsp_sds;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+
+        dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
+        u64 phys_addr;
+
+        u8 i, nrds_rings, nsds_rings;
+        size_t rq_size, rsp_size;
+        u32 cap, reg, val, reg2;
+        int err;
+
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        nrds_rings = adapter->max_rds_rings;
+        nsds_rings = adapter->max_sds_rings;
+
+        rq_size =
+                SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
+                                                nsds_rings);
+        rsp_size =
+                SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
+                                                nsds_rings);
+
+        addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
+                        &hostrq_phys_addr, GFP_KERNEL);
+        if (addr == NULL)
+                return -ENOMEM;
+        prq = addr;
+
+        addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
+                        &cardrsp_phys_addr, GFP_KERNEL);
+        if (addr == NULL) {
+                err = -ENOMEM;
+                goto out_free_rq;
+        }
+        prsp = addr;
+
+        prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
+
+        cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
+                                                | QLCNIC_CAP0_VALIDOFF);
+        cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
+
+        prq->valid_field_offset = offsetof(struct qlcnic_hostrq_rx_ctx,
+                                                         msix_handler);
+        prq->txrx_sds_binding = nsds_rings - 1;
+
+        prq->capabilities[0] = cpu_to_le32(cap);
+        prq->host_int_crb_mode =
+                cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
+        prq->host_rds_crb_mode =
+                cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
+
+        prq->num_rds_rings = cpu_to_le16(nrds_rings);
+        prq->num_sds_rings = cpu_to_le16(nsds_rings);
+        prq->rds_ring_offset = 0;
+
+        val = le32_to_cpu(prq->rds_ring_offset) +
+                (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
+        prq->sds_ring_offset = cpu_to_le32(val);
+
+        prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
+                        le32_to_cpu(prq->rds_ring_offset));
+
+        for (i = 0; i < nrds_rings; i++) {
+
+                rds_ring = &recv_ctx->rds_rings[i];
+                rds_ring->producer = 0;
+
+                prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
+                prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
+                prq_rds[i].ring_kind = cpu_to_le32(i);
+                prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
+        }
+
+        prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
+                        le32_to_cpu(prq->sds_ring_offset));
+
+        for (i = 0; i < nsds_rings; i++) {
+
+                sds_ring = &recv_ctx->sds_rings[i];
+                sds_ring->consumer = 0;
+                memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
+
+                prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
+                prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
+                prq_sds[i].msi_index = cpu_to_le16(i);
+        }
+
+        phys_addr = hostrq_phys_addr;
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        (u32)(phys_addr >> 32),
+                        (u32)(phys_addr & 0xffffffff),
+                        rq_size,
+                        QLCNIC_CDRP_CMD_CREATE_RX_CTX);
+        if (err) {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to create rx ctx in firmware%d\n", err);
+                goto out_free_rsp;
+        }
+
+
+        prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
+                         &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
+
+        for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
+                rds_ring = &recv_ctx->rds_rings[i];
+
+                reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
+                rds_ring->crb_rcv_producer = adapter->ahw->pci_base0 + reg;
+        }
+
+        prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
+                        &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
+
+        for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
+                sds_ring = &recv_ctx->sds_rings[i];
+
+                reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
+                reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
+
+                sds_ring->crb_sts_consumer = adapter->ahw->pci_base0 + reg;
+                sds_ring->crb_intr_mask = adapter->ahw->pci_base0 + reg2;
+        }
+
+        recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
+        recv_ctx->context_id = le16_to_cpu(prsp->context_id);
+        recv_ctx->virt_port = prsp->virt_port;
+
+out_free_rsp:
+        dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
+                cardrsp_phys_addr);
+out_free_rq:
+        dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
+        return err;
+}
+
+static void
+qlcnic_fw_cmd_destroy_rx_ctx(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        if (qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        recv_ctx->context_id,
+                        QLCNIC_DESTROY_CTX_RESET,
+                        0,
+                        QLCNIC_CDRP_CMD_DESTROY_RX_CTX)) {
+
+                dev_err(&adapter->pdev->dev,
+                        "Failed to destroy rx ctx in firmware\n");
+        }
+
+        recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
+}
+
+static int
+qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_hostrq_tx_ctx     *prq;
+        struct qlcnic_hostrq_cds_ring   *prq_cds;
+        struct qlcnic_cardrsp_tx_ctx    *prsp;
+        void    *rq_addr, *rsp_addr;
+        size_t  rq_size, rsp_size;
+        u32     temp;
+        int     err;
+        u64     phys_addr;
+        dma_addr_t      rq_phys_addr, rsp_phys_addr;
+        struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
+
+        /* reset host resources */
+        tx_ring->producer = 0;
+        tx_ring->sw_consumer = 0;
+        *(tx_ring->hw_consumer) = 0;
+
+        rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
+        rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
+                        &rq_phys_addr, GFP_KERNEL);
+        if (!rq_addr)
+                return -ENOMEM;
+
+        rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
+        rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
+                        &rsp_phys_addr, GFP_KERNEL);
+        if (!rsp_addr) {
+                err = -ENOMEM;
+                goto out_free_rq;
+        }
+
+        memset(rq_addr, 0, rq_size);
+        prq = rq_addr;
+
+        memset(rsp_addr, 0, rsp_size);
+        prsp = rsp_addr;
+
+        prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
+
+        temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
+                                        QLCNIC_CAP0_LSO);
+        prq->capabilities[0] = cpu_to_le32(temp);
+
+        prq->host_int_crb_mode =
+                cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
+
+        prq->interrupt_ctl = 0;
+        prq->msi_index = 0;
+        prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
+
+        prq_cds = &prq->cds_ring;
+
+        prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
+        prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
+
+        phys_addr = rq_phys_addr;
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        (u32)(phys_addr >> 32),
+                        ((u32)phys_addr & 0xffffffff),
+                        rq_size,
+                        QLCNIC_CDRP_CMD_CREATE_TX_CTX);
+
+        if (err == QLCNIC_RCODE_SUCCESS) {
+                temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
+                tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
+
+                adapter->tx_context_id =
+                        le16_to_cpu(prsp->context_id);
+        } else {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to create tx ctx in firmware%d\n", err);
+                err = -EIO;
+        }
+
+        dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
+                rsp_phys_addr);
+
+out_free_rq:
+        dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
+
+        return err;
+}
+
+static void
+qlcnic_fw_cmd_destroy_tx_ctx(struct qlcnic_adapter *adapter)
+{
+        if (qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        adapter->tx_context_id,
+                        QLCNIC_DESTROY_CTX_RESET,
+                        0,
+                        QLCNIC_CDRP_CMD_DESTROY_TX_CTX)) {
+
+                dev_err(&adapter->pdev->dev,
+                        "Failed to destroy tx ctx in firmware\n");
+        }
+}
+
+int
+qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
+{
+        return qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        config,
+                        0,
+                        0,
+                        QLCNIC_CDRP_CMD_CONFIG_PORT);
+}
+
+int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
+{
+        void *addr;
+        int err;
+        int ring;
+        struct qlcnic_recv_context *recv_ctx;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_host_tx_ring *tx_ring;
+
+        struct pci_dev *pdev = adapter->pdev;
+
+        recv_ctx = adapter->recv_ctx;
+        tx_ring = adapter->tx_ring;
+
+        tx_ring->hw_consumer = (__le32 *) dma_alloc_coherent(&pdev->dev,
+                sizeof(u32), &tx_ring->hw_cons_phys_addr, GFP_KERNEL);
+        if (tx_ring->hw_consumer == NULL) {
+                dev_err(&pdev->dev, "failed to allocate tx consumer\n");
+                return -ENOMEM;
+        }
+
+        /* cmd desc ring */
+        addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
+                        &tx_ring->phys_addr, GFP_KERNEL);
+
+        if (addr == NULL) {
+                dev_err(&pdev->dev, "failed to allocate tx desc ring\n");
+                err = -ENOMEM;
+                goto err_out_free;
+        }
+
+        tx_ring->desc_head = addr;
+
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &recv_ctx->rds_rings[ring];
+                addr = dma_alloc_coherent(&adapter->pdev->dev,
+                                RCV_DESC_RINGSIZE(rds_ring),
+                                &rds_ring->phys_addr, GFP_KERNEL);
+                if (addr == NULL) {
+                        dev_err(&pdev->dev,
+                                "failed to allocate rds ring [%d]\n", ring);
+                        err = -ENOMEM;
+                        goto err_out_free;
+                }
+                rds_ring->desc_head = addr;
+
+        }
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+
+                addr = dma_alloc_coherent(&adapter->pdev->dev,
+                                STATUS_DESC_RINGSIZE(sds_ring),
+                                &sds_ring->phys_addr, GFP_KERNEL);
+                if (addr == NULL) {
+                        dev_err(&pdev->dev,
+                                "failed to allocate sds ring [%d]\n", ring);
+                        err = -ENOMEM;
+                        goto err_out_free;
+                }
+                sds_ring->desc_head = addr;
+        }
+
+        return 0;
+
+err_out_free:
+        qlcnic_free_hw_resources(adapter);
+        return err;
+}
+
+
+int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter)
+{
+        int err;
+
+        if (adapter->flags & QLCNIC_NEED_FLR) {
+                pci_reset_function(adapter->pdev);
+                adapter->flags &= ~QLCNIC_NEED_FLR;
+        }
+
+        err = qlcnic_fw_cmd_create_rx_ctx(adapter);
+        if (err)
+                return err;
+
+        err = qlcnic_fw_cmd_create_tx_ctx(adapter);
+        if (err) {
+                qlcnic_fw_cmd_destroy_rx_ctx(adapter);
+                return err;
+        }
+
+        set_bit(__QLCNIC_FW_ATTACHED, &adapter->state);
+        return 0;
+}
+
+void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
+{
+        if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
+                qlcnic_fw_cmd_destroy_rx_ctx(adapter);
+                qlcnic_fw_cmd_destroy_tx_ctx(adapter);
+
+                /* Allow dma queues to drain after context reset */
+                msleep(20);
+        }
+}
+
+void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_recv_context *recv_ctx;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_host_tx_ring *tx_ring;
+        int ring;
+
+        recv_ctx = adapter->recv_ctx;
+
+        tx_ring = adapter->tx_ring;
+        if (tx_ring->hw_consumer != NULL) {
+                dma_free_coherent(&adapter->pdev->dev,
+                                sizeof(u32),
+                                tx_ring->hw_consumer,
+                                tx_ring->hw_cons_phys_addr);
+                tx_ring->hw_consumer = NULL;
+        }
+
+        if (tx_ring->desc_head != NULL) {
+                dma_free_coherent(&adapter->pdev->dev,
+                                TX_DESC_RINGSIZE(tx_ring),
+                                tx_ring->desc_head, tx_ring->phys_addr);
+                tx_ring->desc_head = NULL;
+        }
+
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &recv_ctx->rds_rings[ring];
+
+                if (rds_ring->desc_head != NULL) {
+                        dma_free_coherent(&adapter->pdev->dev,
+                                        RCV_DESC_RINGSIZE(rds_ring),
+                                        rds_ring->desc_head,
+                                        rds_ring->phys_addr);
+                        rds_ring->desc_head = NULL;
+                }
+        }
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+
+                if (sds_ring->desc_head != NULL) {
+                        dma_free_coherent(&adapter->pdev->dev,
+                                STATUS_DESC_RINGSIZE(sds_ring),
+                                sds_ring->desc_head,
+                                sds_ring->phys_addr);
+                        sds_ring->desc_head = NULL;
+                }
+        }
+}
+
+
+/* Get MAC address of a NIC partition */
+int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
+{
+        int err;
+        u32 arg1;
+
+        arg1 = adapter->ahw->pci_func | BIT_8;
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        arg1,
+                        0,
+                        0,
+                        QLCNIC_CDRP_CMD_MAC_ADDRESS);
+
+        if (err == QLCNIC_RCODE_SUCCESS)
+                qlcnic_fetch_mac(adapter, QLCNIC_ARG1_CRB_OFFSET,
+                                QLCNIC_ARG2_CRB_OFFSET, 0, mac);
+        else {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to get mac address%d\n", err);
+                err = -EIO;
+        }
+
+        return err;
+}
+
+/* Get info of a NIC partition */
+int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
+                                struct qlcnic_info *npar_info, u8 func_id)
+{
+        int     err;
+        dma_addr_t nic_dma_t;
+        struct qlcnic_info *nic_info;
+        void *nic_info_addr;
+        size_t  nic_size = sizeof(struct qlcnic_info);
+
+        nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
+                                &nic_dma_t, GFP_KERNEL);
+        if (!nic_info_addr)
+                return -ENOMEM;
+        memset(nic_info_addr, 0, nic_size);
+
+        nic_info = nic_info_addr;
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        MSD(nic_dma_t),
+                        LSD(nic_dma_t),
+                        (func_id << 16 | nic_size),
+                        QLCNIC_CDRP_CMD_GET_NIC_INFO);
+
+        if (err == QLCNIC_RCODE_SUCCESS) {
+                npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
+                npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
+                npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
+                npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
+                npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
+                npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
+                npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
+                npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
+                npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
+                npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
+
+                dev_info(&adapter->pdev->dev,
+                        "phy port: %d switch_mode: %d,\n"
+                        "\tmax_tx_q: %d max_rx_q: %d min_tx_bw: 0x%x,\n"
+                        "\tmax_tx_bw: 0x%x max_mtu:0x%x, capabilities: 0x%x\n",
+                        npar_info->phys_port, npar_info->switch_mode,
+                        npar_info->max_tx_ques, npar_info->max_rx_ques,
+                        npar_info->min_tx_bw, npar_info->max_tx_bw,
+                        npar_info->max_mtu, npar_info->capabilities);
+        } else {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to get nic info%d\n", err);
+                err = -EIO;
+        }
+
+        dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
+                nic_dma_t);
+        return err;
+}
+
+/* Configure a NIC partition */
+int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, struct qlcnic_info *nic)
+{
+        int err = -EIO;
+        dma_addr_t nic_dma_t;
+        void *nic_info_addr;
+        struct qlcnic_info *nic_info;
+        size_t nic_size = sizeof(struct qlcnic_info);
+
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC)
+                return err;
+
+        nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
+                        &nic_dma_t, GFP_KERNEL);
+        if (!nic_info_addr)
+                return -ENOMEM;
+
+        memset(nic_info_addr, 0, nic_size);
+        nic_info = nic_info_addr;
+
+        nic_info->pci_func = cpu_to_le16(nic->pci_func);
+        nic_info->op_mode = cpu_to_le16(nic->op_mode);
+        nic_info->phys_port = cpu_to_le16(nic->phys_port);
+        nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
+        nic_info->capabilities = cpu_to_le32(nic->capabilities);
+        nic_info->max_mac_filters = nic->max_mac_filters;
+        nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
+        nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
+        nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
+        nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
+
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        MSD(nic_dma_t),
+                        LSD(nic_dma_t),
+                        ((nic->pci_func << 16) | nic_size),
+                        QLCNIC_CDRP_CMD_SET_NIC_INFO);
+
+        if (err != QLCNIC_RCODE_SUCCESS) {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to set nic info%d\n", err);
+                err = -EIO;
+        }
+
+        dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
+                nic_dma_t);
+        return err;
+}
+
+/* Get PCI Info of a partition */
+int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
+                                struct qlcnic_pci_info *pci_info)
+{
+        int err = 0, i;
+        dma_addr_t pci_info_dma_t;
+        struct qlcnic_pci_info *npar;
+        void *pci_info_addr;
+        size_t npar_size = sizeof(struct qlcnic_pci_info);
+        size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
+
+        pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
+                        &pci_info_dma_t, GFP_KERNEL);
+        if (!pci_info_addr)
+                return -ENOMEM;
+        memset(pci_info_addr, 0, pci_size);
+
+        npar = pci_info_addr;
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        MSD(pci_info_dma_t),
+                        LSD(pci_info_dma_t),
+                        pci_size,
+                        QLCNIC_CDRP_CMD_GET_PCI_INFO);
+
+        if (err == QLCNIC_RCODE_SUCCESS) {
+                for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
+                        pci_info->id = le16_to_cpu(npar->id);
+                        pci_info->active = le16_to_cpu(npar->active);
+                        pci_info->type = le16_to_cpu(npar->type);
+                        pci_info->default_port =
+                                le16_to_cpu(npar->default_port);
+                        pci_info->tx_min_bw =
+                                le16_to_cpu(npar->tx_min_bw);
+                        pci_info->tx_max_bw =
+                                le16_to_cpu(npar->tx_max_bw);
+                        memcpy(pci_info->mac, npar->mac, ETH_ALEN);
+                }
+        } else {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to get PCI Info%d\n", err);
+                err = -EIO;
+        }
+
+        dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
+                pci_info_dma_t);
+        return err;
+}
+
+/* Configure eSwitch for port mirroring */
+int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
+                                u8 enable_mirroring, u8 pci_func)
+{
+        int err = -EIO;
+        u32 arg1;
+
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC ||
+                !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
+                return err;
+
+        arg1 = id | (enable_mirroring ? BIT_4 : 0);
+        arg1 |= pci_func << 8;
+
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        arg1,
+                        0,
+                        0,
+                        QLCNIC_CDRP_CMD_SET_PORTMIRRORING);
+
+        if (err != QLCNIC_RCODE_SUCCESS) {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to configure port mirroring%d on eswitch:%d\n",
+                        pci_func, id);
+        } else {
+                dev_info(&adapter->pdev->dev,
+                        "Configured eSwitch %d for port mirroring:%d\n",
+                        id, pci_func);
+        }
+
+        return err;
+}
+
+int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
+                const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
+
+        size_t stats_size = sizeof(struct __qlcnic_esw_statistics);
+        struct __qlcnic_esw_statistics *stats;
+        dma_addr_t stats_dma_t;
+        void *stats_addr;
+        u32 arg1;
+        int err;
+
+        if (esw_stats == NULL)
+                return -ENOMEM;
+
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC &&
+            func != adapter->ahw->pci_func) {
+                dev_err(&adapter->pdev->dev,
+                        "Not privilege to query stats for func=%d", func);
+                return -EIO;
+        }
+
+        stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
+                        &stats_dma_t, GFP_KERNEL);
+        if (!stats_addr) {
+                dev_err(&adapter->pdev->dev, "Unable to allocate memory\n");
+                return -ENOMEM;
+        }
+        memset(stats_addr, 0, stats_size);
+
+        arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
+        arg1 |= rx_tx << 15 | stats_size << 16;
+
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        arg1,
+                        MSD(stats_dma_t),
+                        LSD(stats_dma_t),
+                        QLCNIC_CDRP_CMD_GET_ESWITCH_STATS);
+
+        if (!err) {
+                stats = stats_addr;
+                esw_stats->context_id = le16_to_cpu(stats->context_id);
+                esw_stats->version = le16_to_cpu(stats->version);
+                esw_stats->size = le16_to_cpu(stats->size);
+                esw_stats->multicast_frames =
+                                le64_to_cpu(stats->multicast_frames);
+                esw_stats->broadcast_frames =
+                                le64_to_cpu(stats->broadcast_frames);
+                esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
+                esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
+                esw_stats->local_frames = le64_to_cpu(stats->local_frames);
+                esw_stats->errors = le64_to_cpu(stats->errors);
+                esw_stats->numbytes = le64_to_cpu(stats->numbytes);
+        }
+
+        dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
+                stats_dma_t);
+        return err;
+}
+
+int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
+                const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
+
+        struct __qlcnic_esw_statistics port_stats;
+        u8 i;
+        int ret = -EIO;
+
+        if (esw_stats == NULL)
+                return -ENOMEM;
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC)
+                return -EIO;
+        if (adapter->npars == NULL)
+                return -EIO;
+
+        memset(esw_stats, 0, sizeof(u64));
+        esw_stats->unicast_frames = QLCNIC_ESW_STATS_NOT_AVAIL;
+        esw_stats->multicast_frames = QLCNIC_ESW_STATS_NOT_AVAIL;
+        esw_stats->broadcast_frames = QLCNIC_ESW_STATS_NOT_AVAIL;
+        esw_stats->dropped_frames = QLCNIC_ESW_STATS_NOT_AVAIL;
+        esw_stats->errors = QLCNIC_ESW_STATS_NOT_AVAIL;
+        esw_stats->local_frames = QLCNIC_ESW_STATS_NOT_AVAIL;
+        esw_stats->numbytes = QLCNIC_ESW_STATS_NOT_AVAIL;
+        esw_stats->context_id = eswitch;
+
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
+                if (adapter->npars[i].phy_port != eswitch)
+                        continue;
+
+                memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
+                if (qlcnic_get_port_stats(adapter, i, rx_tx, &port_stats))
+                        continue;
+
+                esw_stats->size = port_stats.size;
+                esw_stats->version = port_stats.version;
+                QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
+                                                port_stats.unicast_frames);
+                QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
+                                                port_stats.multicast_frames);
+                QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
+                                                port_stats.broadcast_frames);
+                QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
+                                                port_stats.dropped_frames);
+                QLCNIC_ADD_ESW_STATS(esw_stats->errors,
+                                                port_stats.errors);
+                QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
+                                                port_stats.local_frames);
+                QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
+                                                port_stats.numbytes);
+                ret = 0;
+        }
+        return ret;
+}
+
+int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
+                const u8 port, const u8 rx_tx)
+{
+
+        u32 arg1;
+
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC)
+                return -EIO;
+
+        if (func_esw == QLCNIC_STATS_PORT) {
+                if (port >= QLCNIC_MAX_PCI_FUNC)
+                        goto err_ret;
+        } else if (func_esw == QLCNIC_STATS_ESWITCH) {
+                if (port >= QLCNIC_NIU_MAX_XG_PORTS)
+                        goto err_ret;
+        } else {
+                goto err_ret;
+        }
+
+        if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
+                goto err_ret;
+
+        arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
+        arg1 |= BIT_14 | rx_tx << 15;
+
+        return qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        arg1,
+                        0,
+                        0,
+                        QLCNIC_CDRP_CMD_GET_ESWITCH_STATS);
+
+err_ret:
+        dev_err(&adapter->pdev->dev, "Invalid argument func_esw=%d port=%d"
+                "rx_ctx=%d\n", func_esw, port, rx_tx);
+        return -EIO;
+}
+
+static int
+__qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
+                                        u32 *arg1, u32 *arg2)
+{
+        int err = -EIO;
+        u8 pci_func;
+        pci_func = (*arg1 >> 8);
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        *arg1,
+                        0,
+                        0,
+                        QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG);
+
+        if (err == QLCNIC_RCODE_SUCCESS) {
+                *arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
+                *arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET);
+                dev_info(&adapter->pdev->dev,
+                        "eSwitch port config for pci func %d\n", pci_func);
+        } else {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to get eswitch port config for pci func %d\n",
+                                                                pci_func);
+        }
+        return err;
+}
+/* Configure eSwitch port
+op_mode = 0 for setting default port behavior
+op_mode = 1 for setting  vlan id
+op_mode = 2 for deleting vlan id
+op_type = 0 for vlan_id
+op_type = 1 for port vlan_id
+*/
+int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
+                struct qlcnic_esw_func_cfg *esw_cfg)
+{
+        int err = -EIO;
+        u32 arg1, arg2 = 0;
+        u8 pci_func;
+
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC)
+                return err;
+        pci_func = esw_cfg->pci_func;
+        arg1 = (adapter->npars[pci_func].phy_port & BIT_0);
+        arg1 |= (pci_func << 8);
+
+        if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
+                return err;
+        arg1 &= ~(0x0ff << 8);
+        arg1 |= (pci_func << 8);
+        arg1 &= ~(BIT_2 | BIT_3);
+        switch (esw_cfg->op_mode) {
+        case QLCNIC_PORT_DEFAULTS:
+                arg1 |= (BIT_4 | BIT_6 | BIT_7);
+                arg2 |= (BIT_0 | BIT_1);
+                if (adapter->capabilities & QLCNIC_FW_CAPABILITY_TSO)
+                        arg2 |= (BIT_2 | BIT_3);
+                if (!(esw_cfg->discard_tagged))
+                        arg1 &= ~BIT_4;
+                if (!(esw_cfg->promisc_mode))
+                        arg1 &= ~BIT_6;
+                if (!(esw_cfg->mac_override))
+                        arg1 &= ~BIT_7;
+                if (!(esw_cfg->mac_anti_spoof))
+                        arg2 &= ~BIT_0;
+                if (!(esw_cfg->offload_flags & BIT_0))
+                        arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
+                if (!(esw_cfg->offload_flags & BIT_1))
+                        arg2 &= ~BIT_2;
+                if (!(esw_cfg->offload_flags & BIT_2))
+                        arg2 &= ~BIT_3;
+                break;
+        case QLCNIC_ADD_VLAN:
+                        arg1 |= (BIT_2 | BIT_5);
+                        arg1 |= (esw_cfg->vlan_id << 16);
+                        break;
+        case QLCNIC_DEL_VLAN:
+                        arg1 |= (BIT_3 | BIT_5);
+                        arg1 &= ~(0x0ffff << 16);
+                        break;
+        default:
+                return err;
+        }
+
+        err = qlcnic_issue_cmd(adapter,
+                        adapter->ahw->pci_func,
+                        adapter->fw_hal_version,
+                        arg1,
+                        arg2,
+                        0,
+                        QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH);
+
+        if (err != QLCNIC_RCODE_SUCCESS) {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to configure eswitch pci func %d\n", pci_func);
+        } else {
+                dev_info(&adapter->pdev->dev,
+                        "Configured eSwitch for pci func %d\n", pci_func);
+        }
+
+        return err;
+}
+
+int
+qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
+                        struct qlcnic_esw_func_cfg *esw_cfg)
+{
+        u32 arg1, arg2;
+        u8 phy_port;
+        if (adapter->op_mode == QLCNIC_MGMT_FUNC)
+                phy_port = adapter->npars[esw_cfg->pci_func].phy_port;
+        else
+                phy_port = adapter->physical_port;
+        arg1 = phy_port;
+        arg1 |= (esw_cfg->pci_func << 8);
+        if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
+                return -EIO;
+
+        esw_cfg->discard_tagged = !!(arg1 & BIT_4);
+        esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
+        esw_cfg->promisc_mode = !!(arg1 & BIT_6);
+        esw_cfg->mac_override = !!(arg1 & BIT_7);
+        esw_cfg->vlan_id = LSW(arg1 >> 16);
+        esw_cfg->mac_anti_spoof = (arg2 & 0x1);
+        esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
+
+        return 0;
+}
diff --git a/drivers/net/qlcnic/qlcnic_ethtool.c b/drivers/net/qlcnic/qlcnic_ethtool.c
new file mode 100644
index 00000000000..72a723d5c98
--- /dev/null
+++ b/drivers/net/qlcnic/qlcnic_ethtool.c
@@ -0,0 +1,1222 @@
+/*
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
+ *
+ * See LICENSE.qlcnic for copyright and licensing details.
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+
+#include "qlcnic.h"
+
+struct qlcnic_stats {
+        char stat_string[ETH_GSTRING_LEN];
+        int sizeof_stat;
+        int stat_offset;
+};
+
+#define QLC_SIZEOF(m) FIELD_SIZEOF(struct qlcnic_adapter, m)
+#define QLC_OFF(m) offsetof(struct qlcnic_adapter, m)
+
+static const struct qlcnic_stats qlcnic_gstrings_stats[] = {
+        {"xmit_called",
+                QLC_SIZEOF(stats.xmitcalled), QLC_OFF(stats.xmitcalled)},
+        {"xmit_finished",
+                QLC_SIZEOF(stats.xmitfinished), QLC_OFF(stats.xmitfinished)},
+        {"rx_dropped",
+                QLC_SIZEOF(stats.rxdropped), QLC_OFF(stats.rxdropped)},
+        {"tx_dropped",
+                QLC_SIZEOF(stats.txdropped), QLC_OFF(stats.txdropped)},
+        {"csummed",
+                QLC_SIZEOF(stats.csummed), QLC_OFF(stats.csummed)},
+        {"rx_pkts",
+                QLC_SIZEOF(stats.rx_pkts), QLC_OFF(stats.rx_pkts)},
+        {"lro_pkts",
+                QLC_SIZEOF(stats.lro_pkts), QLC_OFF(stats.lro_pkts)},
+        {"rx_bytes",
+                QLC_SIZEOF(stats.rxbytes), QLC_OFF(stats.rxbytes)},
+        {"tx_bytes",
+                QLC_SIZEOF(stats.txbytes), QLC_OFF(stats.txbytes)},
+        {"lrobytes",
+                QLC_SIZEOF(stats.lrobytes), QLC_OFF(stats.lrobytes)},
+        {"lso_frames",
+                QLC_SIZEOF(stats.lso_frames), QLC_OFF(stats.lso_frames)},
+        {"xmit_on",
+                QLC_SIZEOF(stats.xmit_on), QLC_OFF(stats.xmit_on)},
+        {"xmit_off",
+                QLC_SIZEOF(stats.xmit_off), QLC_OFF(stats.xmit_off)},
+        {"skb_alloc_failure", QLC_SIZEOF(stats.skb_alloc_failure),
+                QLC_OFF(stats.skb_alloc_failure)},
+        {"null rxbuf",
+                QLC_SIZEOF(stats.null_rxbuf), QLC_OFF(stats.null_rxbuf)},
+        {"rx dma map error", QLC_SIZEOF(stats.rx_dma_map_error),
+                                         QLC_OFF(stats.rx_dma_map_error)},
+        {"tx dma map error", QLC_SIZEOF(stats.tx_dma_map_error),
+                                         QLC_OFF(stats.tx_dma_map_error)},
+
+};
+
+static const char qlcnic_device_gstrings_stats[][ETH_GSTRING_LEN] = {
+        "rx unicast frames",
+        "rx multicast frames",
+        "rx broadcast frames",
+        "rx dropped frames",
+        "rx errors",
+        "rx local frames",
+        "rx numbytes",
+        "tx unicast frames",
+        "tx multicast frames",
+        "tx broadcast frames",
+        "tx dropped frames",
+        "tx errors",
+        "tx local frames",
+        "tx numbytes",
+};
+
+#define QLCNIC_STATS_LEN        ARRAY_SIZE(qlcnic_gstrings_stats)
+#define QLCNIC_DEVICE_STATS_LEN ARRAY_SIZE(qlcnic_device_gstrings_stats)
+
+static const char qlcnic_gstrings_test[][ETH_GSTRING_LEN] = {
+        "Register_Test_on_offline",
+        "Link_Test_on_offline",
+        "Interrupt_Test_offline",
+        "Internal_Loopback_offline",
+        "External_Loopback_offline"
+};
+
+#define QLCNIC_TEST_LEN ARRAY_SIZE(qlcnic_gstrings_test)
+
+#define QLCNIC_RING_REGS_COUNT  20
+#define QLCNIC_RING_REGS_LEN    (QLCNIC_RING_REGS_COUNT * sizeof(u32))
+#define QLCNIC_MAX_EEPROM_LEN   1024
+
+static const u32 diag_registers[] = {
+        CRB_CMDPEG_STATE,
+        CRB_RCVPEG_STATE,
+        CRB_XG_STATE_P3P,
+        CRB_FW_CAPABILITIES_1,
+        ISR_INT_STATE_REG,
+        QLCNIC_CRB_DRV_ACTIVE,
+        QLCNIC_CRB_DEV_STATE,
+        QLCNIC_CRB_DRV_STATE,
+        QLCNIC_CRB_DRV_SCRATCH,
+        QLCNIC_CRB_DEV_PARTITION_INFO,
+        QLCNIC_CRB_DRV_IDC_VER,
+        QLCNIC_PEG_ALIVE_COUNTER,
+        QLCNIC_PEG_HALT_STATUS1,
+        QLCNIC_PEG_HALT_STATUS2,
+        QLCNIC_CRB_PEG_NET_0+0x3c,
+        QLCNIC_CRB_PEG_NET_1+0x3c,
+        QLCNIC_CRB_PEG_NET_2+0x3c,
+        QLCNIC_CRB_PEG_NET_4+0x3c,
+        -1
+};
+
+#define QLCNIC_MGMT_API_VERSION 2
+#define QLCNIC_DEV_INFO_SIZE    1
+#define QLCNIC_ETHTOOL_REGS_VER 2
+static int qlcnic_get_regs_len(struct net_device *dev)
+{
+        return sizeof(diag_registers) + QLCNIC_RING_REGS_LEN +
+                                QLCNIC_DEV_INFO_SIZE + 1;
+}
+
+static int qlcnic_get_eeprom_len(struct net_device *dev)
+{
+        return QLCNIC_FLASH_TOTAL_SIZE;
+}
+
+static void
+qlcnic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        u32 fw_major, fw_minor, fw_build;
+
+        fw_major = QLCRD32(adapter, QLCNIC_FW_VERSION_MAJOR);
+        fw_minor = QLCRD32(adapter, QLCNIC_FW_VERSION_MINOR);
+        fw_build = QLCRD32(adapter, QLCNIC_FW_VERSION_SUB);
+        sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
+
+        strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
+        strlcpy(drvinfo->driver, qlcnic_driver_name, 32);
+        strlcpy(drvinfo->version, QLCNIC_LINUX_VERSIONID, 32);
+}
+
+static int
+qlcnic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        int check_sfp_module = 0;
+        u16 pcifn = adapter->ahw->pci_func;
+
+        /* read which mode */
+        if (adapter->ahw->port_type == QLCNIC_GBE) {
+                ecmd->supported = (SUPPORTED_10baseT_Half |
+                                   SUPPORTED_10baseT_Full |
+                                   SUPPORTED_100baseT_Half |
+                                   SUPPORTED_100baseT_Full |
+                                   SUPPORTED_1000baseT_Half |
+                                   SUPPORTED_1000baseT_Full);
+
+                ecmd->advertising = (ADVERTISED_100baseT_Half |
+                                     ADVERTISED_100baseT_Full |
+                                     ADVERTISED_1000baseT_Half |
+                                     ADVERTISED_1000baseT_Full);
+
+                ethtool_cmd_speed_set(ecmd, adapter->link_speed);
+                ecmd->duplex = adapter->link_duplex;
+                ecmd->autoneg = adapter->link_autoneg;
+
+        } else if (adapter->ahw->port_type == QLCNIC_XGBE) {
+                u32 val;
+
+                val = QLCRD32(adapter, QLCNIC_PORT_MODE_ADDR);
+                if (val == QLCNIC_PORT_MODE_802_3_AP) {
+                        ecmd->supported = SUPPORTED_1000baseT_Full;
+                        ecmd->advertising = ADVERTISED_1000baseT_Full;
+                } else {
+                        ecmd->supported = SUPPORTED_10000baseT_Full;
+                        ecmd->advertising = ADVERTISED_10000baseT_Full;
+                }
+
+                if (netif_running(dev) && adapter->has_link_events) {
+                        ethtool_cmd_speed_set(ecmd, adapter->link_speed);
+                        ecmd->autoneg = adapter->link_autoneg;
+                        ecmd->duplex = adapter->link_duplex;
+                        goto skip;
+                }
+
+                val = QLCRD32(adapter, P3P_LINK_SPEED_REG(pcifn));
+                ethtool_cmd_speed_set(ecmd, P3P_LINK_SPEED_MHZ *
+                                      P3P_LINK_SPEED_VAL(pcifn, val));
+                ecmd->duplex = DUPLEX_FULL;
+                ecmd->autoneg = AUTONEG_DISABLE;
+        } else
+                return -EIO;
+
+skip:
+        ecmd->phy_address = adapter->physical_port;
+        ecmd->transceiver = XCVR_EXTERNAL;
+
+        switch (adapter->ahw->board_type) {
+        case QLCNIC_BRDTYPE_P3P_REF_QG:
+        case QLCNIC_BRDTYPE_P3P_4_GB:
+        case QLCNIC_BRDTYPE_P3P_4_GB_MM:
+
+                ecmd->supported |= SUPPORTED_Autoneg;
+                ecmd->advertising |= ADVERTISED_Autoneg;
+        case QLCNIC_BRDTYPE_P3P_10G_CX4:
+        case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
+        case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
+                ecmd->supported |= SUPPORTED_TP;
+                ecmd->advertising |= ADVERTISED_TP;
+                ecmd->port = PORT_TP;
+                ecmd->autoneg =  adapter->link_autoneg;
+                break;
+        case QLCNIC_BRDTYPE_P3P_IMEZ:
+        case QLCNIC_BRDTYPE_P3P_XG_LOM:
+        case QLCNIC_BRDTYPE_P3P_HMEZ:
+                ecmd->supported |= SUPPORTED_MII;
+                ecmd->advertising |= ADVERTISED_MII;
+                ecmd->port = PORT_MII;
+                ecmd->autoneg = AUTONEG_DISABLE;
+                break;
+        case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
+        case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
+        case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
+                ecmd->advertising |= ADVERTISED_TP;
+                ecmd->supported |= SUPPORTED_TP;
+                check_sfp_module = netif_running(dev) &&
+                        adapter->has_link_events;
+        case QLCNIC_BRDTYPE_P3P_10G_XFP:
+                ecmd->supported |= SUPPORTED_FIBRE;
+                ecmd->advertising |= ADVERTISED_FIBRE;
+                ecmd->port = PORT_FIBRE;
+                ecmd->autoneg = AUTONEG_DISABLE;
+                break;
+        case QLCNIC_BRDTYPE_P3P_10G_TP:
+                if (adapter->ahw->port_type == QLCNIC_XGBE) {
+                        ecmd->autoneg = AUTONEG_DISABLE;
+                        ecmd->supported |= (SUPPORTED_FIBRE | SUPPORTED_TP);
+                        ecmd->advertising |=
+                                (ADVERTISED_FIBRE | ADVERTISED_TP);
+                        ecmd->port = PORT_FIBRE;
+                        check_sfp_module = netif_running(dev) &&
+                                adapter->has_link_events;
+                } else {
+                        ecmd->autoneg = AUTONEG_ENABLE;
+                        ecmd->supported |= (SUPPORTED_TP | SUPPORTED_Autoneg);
+                        ecmd->advertising |=
+                                (ADVERTISED_TP | ADVERTISED_Autoneg);
+                        ecmd->port = PORT_TP;
+                }
+                break;
+        default:
+                dev_err(&adapter->pdev->dev, "Unsupported board model %d\n",
+                        adapter->ahw->board_type);
+                return -EIO;
+        }
+
+        if (check_sfp_module) {
+                switch (adapter->module_type) {
+                case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
+                case LINKEVENT_MODULE_OPTICAL_SRLR:
+                case LINKEVENT_MODULE_OPTICAL_LRM:
+                case LINKEVENT_MODULE_OPTICAL_SFP_1G:
+                        ecmd->port = PORT_FIBRE;
+                        break;
+                case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
+                case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
+                case LINKEVENT_MODULE_TWINAX:
+                        ecmd->port = PORT_TP;
+                        break;
+                default:
+                        ecmd->port = PORT_OTHER;
+                }
+        }
+
+        return 0;
+}
+
+static int
+qlcnic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
+{
+        u32 config = 0;
+        u32 ret = 0;
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+
+        if (adapter->ahw->port_type != QLCNIC_GBE)
+                return -EOPNOTSUPP;
+
+        /* read which mode */
+        if (ecmd->duplex)
+                config |= 0x1;
+
+        if (ecmd->autoneg)
+                config |= 0x2;
+
+        switch (ethtool_cmd_speed(ecmd)) {
+        case SPEED_10:
+                config |= (0 << 8);
+                break;
+        case SPEED_100:
+                config |= (1 << 8);
+                break;
+        case SPEED_1000:
+                config |= (10 << 8);
+                break;
+        default:
+                return -EIO;
+        }
+
+        ret = qlcnic_fw_cmd_set_port(adapter, config);
+
+        if (ret == QLCNIC_RCODE_NOT_SUPPORTED)
+                return -EOPNOTSUPP;
+        else if (ret)
+                return -EIO;
+
+        adapter->link_speed = ethtool_cmd_speed(ecmd);
+        adapter->link_duplex = ecmd->duplex;
+        adapter->link_autoneg = ecmd->autoneg;
+
+        if (!netif_running(dev))
+                return 0;
+
+        dev->netdev_ops->ndo_stop(dev);
+        return dev->netdev_ops->ndo_open(dev);
+}
+
+static void
+qlcnic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+        struct qlcnic_host_sds_ring *sds_ring;
+        u32 *regs_buff = p;
+        int ring, i = 0, j = 0;
+
+        memset(p, 0, qlcnic_get_regs_len(dev));
+        regs->version = (QLCNIC_ETHTOOL_REGS_VER << 24) |
+                (adapter->ahw->revision_id << 16) | (adapter->pdev)->device;
+
+        regs_buff[0] = (0xcafe0000 | (QLCNIC_DEV_INFO_SIZE & 0xffff));
+        regs_buff[1] = QLCNIC_MGMT_API_VERSION;
+
+        for (i = QLCNIC_DEV_INFO_SIZE + 1; diag_registers[j] != -1; j++, i++)
+                regs_buff[i] = QLCRD32(adapter, diag_registers[j]);
+
+        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                return;
+
+        regs_buff[i++] = 0xFFEFCDAB; /* Marker btw regs and ring count*/
+
+        regs_buff[i++] = 1; /* No. of tx ring */
+        regs_buff[i++] = le32_to_cpu(*(adapter->tx_ring->hw_consumer));
+        regs_buff[i++] = readl(adapter->tx_ring->crb_cmd_producer);
+
+        regs_buff[i++] = 2; /* No. of rx ring */
+        regs_buff[i++] = readl(recv_ctx->rds_rings[0].crb_rcv_producer);
+        regs_buff[i++] = readl(recv_ctx->rds_rings[1].crb_rcv_producer);
+
+        regs_buff[i++] = adapter->max_sds_rings;
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &(recv_ctx->sds_rings[ring]);
+                regs_buff[i++] = readl(sds_ring->crb_sts_consumer);
+        }
+}
+
+static u32 qlcnic_test_link(struct net_device *dev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        u32 val;
+
+        val = QLCRD32(adapter, CRB_XG_STATE_P3P);
+        val = XG_LINK_STATE_P3P(adapter->ahw->pci_func, val);
+        return (val == XG_LINK_UP_P3P) ? 0 : 1;
+}
+
+static int
+qlcnic_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
+                      u8 *bytes)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        int offset;
+        int ret;
+
+        if (eeprom->len == 0)
+                return -EINVAL;
+
+        eeprom->magic = (adapter->pdev)->vendor |
+                        ((adapter->pdev)->device << 16);
+        offset = eeprom->offset;
+
+        ret = qlcnic_rom_fast_read_words(adapter, offset, bytes,
+                                                eeprom->len);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
+static void
+qlcnic_get_ringparam(struct net_device *dev,
+                struct ethtool_ringparam *ring)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+
+        ring->rx_pending = adapter->num_rxd;
+        ring->rx_jumbo_pending = adapter->num_jumbo_rxd;
+        ring->tx_pending = adapter->num_txd;
+
+        ring->rx_max_pending = adapter->max_rxd;
+        ring->rx_jumbo_max_pending = adapter->max_jumbo_rxd;
+        ring->tx_max_pending = MAX_CMD_DESCRIPTORS;
+
+        ring->rx_mini_max_pending = 0;
+        ring->rx_mini_pending = 0;
+}
+
+static u32
+qlcnic_validate_ringparam(u32 val, u32 min, u32 max, char *r_name)
+{
+        u32 num_desc;
+        num_desc = max(val, min);
+        num_desc = min(num_desc, max);
+        num_desc = roundup_pow_of_two(num_desc);
+
+        if (val != num_desc) {
+                printk(KERN_INFO "%s: setting %s ring size %d instead of %d\n",
+                       qlcnic_driver_name, r_name, num_desc, val);
+        }
+
+        return num_desc;
+}
+
+static int
+qlcnic_set_ringparam(struct net_device *dev,
+                struct ethtool_ringparam *ring)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        u16 num_rxd, num_jumbo_rxd, num_txd;
+
+        if (ring->rx_mini_pending)
+                return -EOPNOTSUPP;
+
+        num_rxd = qlcnic_validate_ringparam(ring->rx_pending,
+                        MIN_RCV_DESCRIPTORS, adapter->max_rxd, "rx");
+
+        num_jumbo_rxd = qlcnic_validate_ringparam(ring->rx_jumbo_pending,
+                        MIN_JUMBO_DESCRIPTORS, adapter->max_jumbo_rxd,
+                                                "rx jumbo");
+
+        num_txd = qlcnic_validate_ringparam(ring->tx_pending,
+                        MIN_CMD_DESCRIPTORS, MAX_CMD_DESCRIPTORS, "tx");
+
+        if (num_rxd == adapter->num_rxd && num_txd == adapter->num_txd &&
+                        num_jumbo_rxd == adapter->num_jumbo_rxd)
+                return 0;
+
+        adapter->num_rxd = num_rxd;
+        adapter->num_jumbo_rxd = num_jumbo_rxd;
+        adapter->num_txd = num_txd;
+
+        return qlcnic_reset_context(adapter);
+}
+
+static void qlcnic_get_channels(struct net_device *dev,
+                struct ethtool_channels *channel)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+
+        channel->max_rx = rounddown_pow_of_two(min_t(int,
+                        adapter->max_rx_ques, num_online_cpus()));
+        channel->max_tx = adapter->max_tx_ques;
+
+        channel->rx_count = adapter->max_sds_rings;
+        channel->tx_count = adapter->max_tx_ques;
+}
+
+static int qlcnic_set_channels(struct net_device *dev,
+                struct ethtool_channels *channel)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        int err;
+
+        if (channel->other_count || channel->combined_count ||
+            channel->tx_count != channel->max_tx)
+                return -EINVAL;
+
+        err = qlcnic_validate_max_rss(dev, channel->max_rx, channel->rx_count);
+        if (err)
+                return err;
+
+        err = qlcnic_set_max_rss(adapter, channel->rx_count);
+        netdev_info(dev, "allocated 0x%x sds rings\n",
+                                 adapter->max_sds_rings);
+        return err;
+}
+
+static void
+qlcnic_get_pauseparam(struct net_device *netdev,
+                          struct ethtool_pauseparam *pause)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        int port = adapter->physical_port;
+        __u32 val;
+
+        if (adapter->ahw->port_type == QLCNIC_GBE) {
+                if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS))
+                        return;
+                /* get flow control settings */
+                val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port));
+                pause->rx_pause = qlcnic_gb_get_rx_flowctl(val);
+                val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL);
+                switch (port) {
+                case 0:
+                        pause->tx_pause = !(qlcnic_gb_get_gb0_mask(val));
+                        break;
+                case 1:
+                        pause->tx_pause = !(qlcnic_gb_get_gb1_mask(val));
+                        break;
+                case 2:
+                        pause->tx_pause = !(qlcnic_gb_get_gb2_mask(val));
+                        break;
+                case 3:
+                default:
+                        pause->tx_pause = !(qlcnic_gb_get_gb3_mask(val));
+                        break;
+                }
+        } else if (adapter->ahw->port_type == QLCNIC_XGBE) {
+                if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS))
+                        return;
+                pause->rx_pause = 1;
+                val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL);
+                if (port == 0)
+                        pause->tx_pause = !(qlcnic_xg_get_xg0_mask(val));
+                else
+                        pause->tx_pause = !(qlcnic_xg_get_xg1_mask(val));
+        } else {
+                dev_err(&netdev->dev, "Unknown board type: %x\n",
+                                        adapter->ahw->port_type);
+        }
+}
+
+static int
+qlcnic_set_pauseparam(struct net_device *netdev,
+                          struct ethtool_pauseparam *pause)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        int port = adapter->physical_port;
+        __u32 val;
+
+        /* read mode */
+        if (adapter->ahw->port_type == QLCNIC_GBE) {
+                if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS))
+                        return -EIO;
+                /* set flow control */
+                val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port));
+
+                if (pause->rx_pause)
+                        qlcnic_gb_rx_flowctl(val);
+                else
+                        qlcnic_gb_unset_rx_flowctl(val);
+
+                QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port),
+                                val);
+                /* set autoneg */
+                val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL);
+                switch (port) {
+                case 0:
+                        if (pause->tx_pause)
+                                qlcnic_gb_unset_gb0_mask(val);
+                        else
+                                qlcnic_gb_set_gb0_mask(val);
+                        break;
+                case 1:
+                        if (pause->tx_pause)
+                                qlcnic_gb_unset_gb1_mask(val);
+                        else
+                                qlcnic_gb_set_gb1_mask(val);
+                        break;
+                case 2:
+                        if (pause->tx_pause)
+                                qlcnic_gb_unset_gb2_mask(val);
+                        else
+                                qlcnic_gb_set_gb2_mask(val);
+                        break;
+                case 3:
+                default:
+                        if (pause->tx_pause)
+                                qlcnic_gb_unset_gb3_mask(val);
+                        else
+                                qlcnic_gb_set_gb3_mask(val);
+                        break;
+                }
+                QLCWR32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, val);
+        } else if (adapter->ahw->port_type == QLCNIC_XGBE) {
+                if (!pause->rx_pause || pause->autoneg)
+                        return -EOPNOTSUPP;
+
+                if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS))
+                        return -EIO;
+
+                val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL);
+                if (port == 0) {
+                        if (pause->tx_pause)
+                                qlcnic_xg_unset_xg0_mask(val);
+                        else
+                                qlcnic_xg_set_xg0_mask(val);
+                } else {
+                        if (pause->tx_pause)
+                                qlcnic_xg_unset_xg1_mask(val);
+                        else
+                                qlcnic_xg_set_xg1_mask(val);
+                }
+                QLCWR32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, val);
+        } else {
+                dev_err(&netdev->dev, "Unknown board type: %x\n",
+                                adapter->ahw->port_type);
+        }
+        return 0;
+}
+
+static int qlcnic_reg_test(struct net_device *dev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        u32 data_read;
+
+        data_read = QLCRD32(adapter, QLCNIC_PCIX_PH_REG(0));
+        if ((data_read & 0xffff) != adapter->pdev->vendor)
+                return 1;
+
+        return 0;
+}
+
+static int qlcnic_get_sset_count(struct net_device *dev, int sset)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        switch (sset) {
+        case ETH_SS_TEST:
+                return QLCNIC_TEST_LEN;
+        case ETH_SS_STATS:
+                if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
+                        return QLCNIC_STATS_LEN + QLCNIC_DEVICE_STATS_LEN;
+                return QLCNIC_STATS_LEN;
+        default:
+                return -EOPNOTSUPP;
+        }
+}
+
+static int qlcnic_irq_test(struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        int max_sds_rings = adapter->max_sds_rings;
+        int ret;
+
+        if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                return -EIO;
+
+        ret = qlcnic_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST);
+        if (ret)
+                goto clear_it;
+
+        adapter->diag_cnt = 0;
+        ret = qlcnic_issue_cmd(adapter, adapter->ahw->pci_func,
+                        adapter->fw_hal_version, adapter->ahw->pci_func,
+                        0, 0, 0x00000011);
+        if (ret)
+                goto done;
+
+        msleep(10);
+
+        ret = !adapter->diag_cnt;
+
+done:
+        qlcnic_diag_free_res(netdev, max_sds_rings);
+
+clear_it:
+        adapter->max_sds_rings = max_sds_rings;
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+        return ret;
+}
+
+#define QLCNIC_ILB_PKT_SIZE 64
+#define QLCNIC_NUM_ILB_PKT      16
+#define QLCNIC_ILB_MAX_RCV_LOOP 10
+
+static void qlcnic_create_loopback_buff(unsigned char *data, u8 mac[])
+{
+        unsigned char random_data[] = {0xa8, 0x06, 0x45, 0x00};
+
+        memset(data, 0x4e, QLCNIC_ILB_PKT_SIZE);
+
+        memcpy(data, mac, ETH_ALEN);
+        memcpy(data + ETH_ALEN, mac, ETH_ALEN);
+
+        memcpy(data + 2 * ETH_ALEN, random_data, sizeof(random_data));
+}
+
+int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[])
+{
+        unsigned char buff[QLCNIC_ILB_PKT_SIZE];
+        qlcnic_create_loopback_buff(buff, mac);
+        return memcmp(data, buff, QLCNIC_ILB_PKT_SIZE);
+}
+
+static int qlcnic_do_lb_test(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+        struct qlcnic_host_sds_ring *sds_ring = &recv_ctx->sds_rings[0];
+        struct sk_buff *skb;
+        int i, loop, cnt = 0;
+
+        for (i = 0; i < QLCNIC_NUM_ILB_PKT; i++) {
+                skb = dev_alloc_skb(QLCNIC_ILB_PKT_SIZE);
+                qlcnic_create_loopback_buff(skb->data, adapter->mac_addr);
+                skb_put(skb, QLCNIC_ILB_PKT_SIZE);
+
+                adapter->diag_cnt = 0;
+                qlcnic_xmit_frame(skb, adapter->netdev);
+
+                loop = 0;
+                do {
+                        msleep(1);
+                        qlcnic_process_rcv_ring_diag(sds_ring);
+                        if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP)
+                                break;
+                } while (!adapter->diag_cnt);
+
+                dev_kfree_skb_any(skb);
+
+                if (!adapter->diag_cnt)
+                        dev_warn(&adapter->pdev->dev, "LB Test: %dth packet"
+                                " not recevied\n", i + 1);
+                else
+                        cnt++;
+        }
+        if (cnt != i) {
+                dev_warn(&adapter->pdev->dev, "LB Test failed\n");
+                return -1;
+        }
+        return 0;
+}
+
+static int qlcnic_loopback_test(struct net_device *netdev, u8 mode)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        int max_sds_rings = adapter->max_sds_rings;
+        struct qlcnic_host_sds_ring *sds_ring;
+        int loop = 0;
+        int ret;
+
+        if (!(adapter->capabilities & QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK)) {
+                netdev_info(netdev, "Firmware is not loopback test capable\n");
+                return -EOPNOTSUPP;
+        }
+
+        netdev_info(netdev, "%s loopback test in progress\n",
+                   mode == QLCNIC_ILB_MODE ? "internal" : "external");
+        if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC) {
+                netdev_warn(netdev, "Loopback test not supported for non "
+                                "privilege function\n");
+                return 0;
+        }
+
+        if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                return -EBUSY;
+
+        ret = qlcnic_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST);
+        if (ret)
+                goto clear_it;
+
+        sds_ring = &adapter->recv_ctx->sds_rings[0];
+
+        ret = qlcnic_set_lb_mode(adapter, mode);
+        if (ret)
+                goto free_res;
+
+        adapter->diag_cnt = 0;
+        do {
+                msleep(500);
+                qlcnic_process_rcv_ring_diag(sds_ring);
+                if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
+                        netdev_info(netdev, "firmware didnt respond to loopback"
+                                " configure request\n");
+                        ret = -QLCNIC_FW_NOT_RESPOND;
+                        goto free_res;
+                } else if (adapter->diag_cnt) {
+                        ret = adapter->diag_cnt;
+                        goto free_res;
+                }
+        } while (!QLCNIC_IS_LB_CONFIGURED(adapter->ahw->loopback_state));
+
+        ret = qlcnic_do_lb_test(adapter);
+
+        qlcnic_clear_lb_mode(adapter);
+
+ free_res:
+        qlcnic_diag_free_res(netdev, max_sds_rings);
+
+ clear_it:
+        adapter->max_sds_rings = max_sds_rings;
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+        return ret;
+}
+
+static void
+qlcnic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
+                     u64 *data)
+{
+        memset(data, 0, sizeof(u64) * QLCNIC_TEST_LEN);
+
+        data[0] = qlcnic_reg_test(dev);
+        if (data[0])
+                eth_test->flags |= ETH_TEST_FL_FAILED;
+
+        data[1] = (u64) qlcnic_test_link(dev);
+        if (data[1])
+                eth_test->flags |= ETH_TEST_FL_FAILED;
+
+        if (eth_test->flags & ETH_TEST_FL_OFFLINE) {
+                data[2] = qlcnic_irq_test(dev);
+                if (data[2])
+                        eth_test->flags |= ETH_TEST_FL_FAILED;
+
+                data[3] = qlcnic_loopback_test(dev, QLCNIC_ILB_MODE);
+                if (data[3])
+                        eth_test->flags |= ETH_TEST_FL_FAILED;
+
+                if (eth_test->flags & ETH_TEST_FL_EXTERNAL_LB) {
+                        data[4] = qlcnic_loopback_test(dev, QLCNIC_ELB_MODE);
+                        if (data[4])
+                                eth_test->flags |= ETH_TEST_FL_FAILED;
+                        eth_test->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
+                }
+        }
+}
+
+static void
+qlcnic_get_strings(struct net_device *dev, u32 stringset, u8 * data)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        int index, i;
+
+        switch (stringset) {
+        case ETH_SS_TEST:
+                memcpy(data, *qlcnic_gstrings_test,
+                       QLCNIC_TEST_LEN * ETH_GSTRING_LEN);
+                break;
+        case ETH_SS_STATS:
+                for (index = 0; index < QLCNIC_STATS_LEN; index++) {
+                        memcpy(data + index * ETH_GSTRING_LEN,
+                               qlcnic_gstrings_stats[index].stat_string,
+                               ETH_GSTRING_LEN);
+                }
+                if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED))
+                        return;
+                for (i = 0; i < QLCNIC_DEVICE_STATS_LEN; index++, i++) {
+                        memcpy(data + index * ETH_GSTRING_LEN,
+                               qlcnic_device_gstrings_stats[i],
+                               ETH_GSTRING_LEN);
+                }
+        }
+}
+
+#define QLCNIC_FILL_ESWITCH_STATS(VAL1) \
+        (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) ? 0 : VAL1)
+
+static void
+qlcnic_fill_device_stats(int *index, u64 *data,
+                struct __qlcnic_esw_statistics *stats)
+{
+        int ind = *index;
+
+        data[ind++] = QLCNIC_FILL_ESWITCH_STATS(stats->unicast_frames);
+        data[ind++] = QLCNIC_FILL_ESWITCH_STATS(stats->multicast_frames);
+        data[ind++] = QLCNIC_FILL_ESWITCH_STATS(stats->broadcast_frames);
+        data[ind++] = QLCNIC_FILL_ESWITCH_STATS(stats->dropped_frames);
+        data[ind++] = QLCNIC_FILL_ESWITCH_STATS(stats->errors);
+        data[ind++] = QLCNIC_FILL_ESWITCH_STATS(stats->local_frames);
+        data[ind++] = QLCNIC_FILL_ESWITCH_STATS(stats->numbytes);
+
+        *index = ind;
+}
+
+static void
+qlcnic_get_ethtool_stats(struct net_device *dev,
+                             struct ethtool_stats *stats, u64 * data)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        struct qlcnic_esw_statistics port_stats;
+        int index, ret;
+
+        for (index = 0; index < QLCNIC_STATS_LEN; index++) {
+                char *p =
+                    (char *)adapter +
+                    qlcnic_gstrings_stats[index].stat_offset;
+                data[index] =
+                    (qlcnic_gstrings_stats[index].sizeof_stat ==
+                     sizeof(u64)) ? *(u64 *)p:(*(u32 *)p);
+        }
+
+        if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED))
+                return;
+
+        memset(&port_stats, 0, sizeof(struct qlcnic_esw_statistics));
+        ret = qlcnic_get_port_stats(adapter, adapter->ahw->pci_func,
+                        QLCNIC_QUERY_RX_COUNTER, &port_stats.rx);
+        if (ret)
+                return;
+
+        qlcnic_fill_device_stats(&index, data, &port_stats.rx);
+
+        ret = qlcnic_get_port_stats(adapter, adapter->ahw->pci_func,
+                        QLCNIC_QUERY_TX_COUNTER, &port_stats.tx);
+        if (ret)
+                return;
+
+        qlcnic_fill_device_stats(&index, data, &port_stats.tx);
+}
+
+static int qlcnic_set_led(struct net_device *dev,
+                          enum ethtool_phys_id_state state)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        int max_sds_rings = adapter->max_sds_rings;
+
+        switch (state) {
+        case ETHTOOL_ID_ACTIVE:
+                if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
+                        if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                                return -EIO;
+
+                        if (qlcnic_diag_alloc_res(dev, QLCNIC_LED_TEST)) {
+                                clear_bit(__QLCNIC_RESETTING, &adapter->state);
+                                return -EIO;
+                        }
+                        set_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state);
+                }
+
+                if (adapter->nic_ops->config_led(adapter, 1, 0xf) == 0)
+                        return 0;
+
+                dev_err(&adapter->pdev->dev,
+                        "Failed to set LED blink state.\n");
+                break;
+
+        case ETHTOOL_ID_INACTIVE:
+                if (adapter->nic_ops->config_led(adapter, 0, 0xf))
+                        dev_err(&adapter->pdev->dev,
+                                "Failed to reset LED blink state.\n");
+
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        if (test_and_clear_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state)) {
+                qlcnic_diag_free_res(dev, max_sds_rings);
+                clear_bit(__QLCNIC_RESETTING, &adapter->state);
+        }
+
+        return -EIO;
+}
+
+static void
+qlcnic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        u32 wol_cfg;
+
+        wol->supported = 0;
+        wol->wolopts = 0;
+
+        wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
+        if (wol_cfg & (1UL << adapter->portnum))
+                wol->supported |= WAKE_MAGIC;
+
+        wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
+        if (wol_cfg & (1UL << adapter->portnum))
+                wol->wolopts |= WAKE_MAGIC;
+}
+
+static int
+qlcnic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(dev);
+        u32 wol_cfg;
+
+        if (wol->wolopts & ~WAKE_MAGIC)
+                return -EOPNOTSUPP;
+
+        wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
+        if (!(wol_cfg & (1 << adapter->portnum)))
+                return -EOPNOTSUPP;
+
+        wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
+        if (wol->wolopts & WAKE_MAGIC)
+                wol_cfg |= 1UL << adapter->portnum;
+        else
+                wol_cfg &= ~(1UL << adapter->portnum);
+
+        QLCWR32(adapter, QLCNIC_WOL_CONFIG, wol_cfg);
+
+        return 0;
+}
+
+/*
+ * Set the coalescing parameters. Currently only normal is supported.
+ * If rx_coalesce_usecs == 0 or rx_max_coalesced_frames == 0 then set the
+ * firmware coalescing to default.
+ */
+static int qlcnic_set_intr_coalesce(struct net_device *netdev,
+                        struct ethtool_coalesce *ethcoal)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                return -EINVAL;
+
+        /*
+        * Return Error if unsupported values or
+        * unsupported parameters are set.
+        */
+        if (ethcoal->rx_coalesce_usecs > 0xffff ||
+                ethcoal->rx_max_coalesced_frames > 0xffff ||
+                ethcoal->tx_coalesce_usecs ||
+                ethcoal->tx_max_coalesced_frames ||
+                ethcoal->rx_coalesce_usecs_irq ||
+                ethcoal->rx_max_coalesced_frames_irq ||
+                ethcoal->tx_coalesce_usecs_irq ||
+                ethcoal->tx_max_coalesced_frames_irq ||
+                ethcoal->stats_block_coalesce_usecs ||
+                ethcoal->use_adaptive_rx_coalesce ||
+                ethcoal->use_adaptive_tx_coalesce ||
+                ethcoal->pkt_rate_low ||
+                ethcoal->rx_coalesce_usecs_low ||
+                ethcoal->rx_max_coalesced_frames_low ||
+                ethcoal->tx_coalesce_usecs_low ||
+                ethcoal->tx_max_coalesced_frames_low ||
+                ethcoal->pkt_rate_high ||
+                ethcoal->rx_coalesce_usecs_high ||
+                ethcoal->rx_max_coalesced_frames_high ||
+                ethcoal->tx_coalesce_usecs_high ||
+                ethcoal->tx_max_coalesced_frames_high)
+                return -EINVAL;
+
+        if (!ethcoal->rx_coalesce_usecs ||
+                !ethcoal->rx_max_coalesced_frames) {
+                adapter->ahw->coal.flag = QLCNIC_INTR_DEFAULT;
+                adapter->ahw->coal.rx_time_us =
+                        QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US;
+                adapter->ahw->coal.rx_packets =
+                        QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS;
+        } else {
+                adapter->ahw->coal.flag = 0;
+                adapter->ahw->coal.rx_time_us = ethcoal->rx_coalesce_usecs;
+                adapter->ahw->coal.rx_packets =
+                        ethcoal->rx_max_coalesced_frames;
+        }
+
+        qlcnic_config_intr_coalesce(adapter);
+
+        return 0;
+}
+
+static int qlcnic_get_intr_coalesce(struct net_device *netdev,
+                        struct ethtool_coalesce *ethcoal)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
+                return -EINVAL;
+
+        ethcoal->rx_coalesce_usecs = adapter->ahw->coal.rx_time_us;
+        ethcoal->rx_max_coalesced_frames = adapter->ahw->coal.rx_packets;
+
+        return 0;
+}
+
+static u32 qlcnic_get_msglevel(struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        return adapter->msg_enable;
+}
+
+static void qlcnic_set_msglevel(struct net_device *netdev, u32 msglvl)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        adapter->msg_enable = msglvl;
+}
+
+static int
+qlcnic_get_dump_flag(struct net_device *netdev, struct ethtool_dump *dump)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
+
+        dump->len = fw_dump->tmpl_hdr->size + fw_dump->size;
+        dump->flag = fw_dump->tmpl_hdr->drv_cap_mask;
+        dump->version = adapter->fw_version;
+        return 0;
+}
+
+static int
+qlcnic_get_dump_data(struct net_device *netdev, struct ethtool_dump *dump,
+                        void *buffer)
+{
+        int i, copy_sz;
+        u32 *hdr_ptr, *data;
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
+
+        if (!fw_dump->clr) {
+                netdev_info(netdev, "Dump not available\n");
+                qlcnic_api_unlock(adapter);
+                return -EINVAL;
+        }
+        /* Copy template header first */
+        copy_sz = fw_dump->tmpl_hdr->size;
+        hdr_ptr = (u32 *) fw_dump->tmpl_hdr;
+        data = buffer;
+        for (i = 0; i < copy_sz/sizeof(u32); i++)
+                *data++ = cpu_to_le32(*hdr_ptr++);
+
+        /* Copy captured dump data */
+        memcpy(buffer + copy_sz, fw_dump->data, fw_dump->size);
+        dump->len = copy_sz + fw_dump->size;
+        dump->flag = fw_dump->tmpl_hdr->drv_cap_mask;
+
+        /* Free dump area once data has been captured */
+        vfree(fw_dump->data);
+        fw_dump->data = NULL;
+        fw_dump->clr = 0;
+
+        return 0;
+}
+
+static int
+qlcnic_set_dump(struct net_device *netdev, struct ethtool_dump *val)
+{
+        int ret = 0;
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
+
+        if (val->flag == QLCNIC_FORCE_FW_DUMP_KEY) {
+                if (!fw_dump->enable) {
+                        netdev_info(netdev, "FW dump not enabled\n");
+                        return ret;
+                }
+                if (fw_dump->clr) {
+                        dev_info(&adapter->pdev->dev,
+                        "Previous dump not cleared, not forcing dump\n");
+                        return ret;
+                }
+                netdev_info(netdev, "Forcing a FW dump\n");
+                qlcnic_dev_request_reset(adapter);
+        } else if (val->flag == QLCNIC_DISABLE_FW_DUMP) {
+                if (fw_dump->enable) {
+                        netdev_info(netdev, "Disabling FW dump\n");
+                        fw_dump->enable = 0;
+                }
+        } else if (val->flag == QLCNIC_ENABLE_FW_DUMP) {
+                if (!fw_dump->enable && fw_dump->tmpl_hdr) {
+                        netdev_info(netdev, "Enabling FW dump\n");
+                        fw_dump->enable = 1;
+                }
+        } else {
+                if (val->flag > QLCNIC_DUMP_MASK_MAX ||
+                        val->flag < QLCNIC_DUMP_MASK_MIN) {
+                                netdev_info(netdev,
+                                "Invalid dump level: 0x%x\n", val->flag);
+                                ret = -EINVAL;
+                                goto out;
+                }
+                fw_dump->tmpl_hdr->drv_cap_mask = val->flag & 0xff;
+                netdev_info(netdev, "Driver mask changed to: 0x%x\n",
+                        fw_dump->tmpl_hdr->drv_cap_mask);
+        }
+out:
+        return ret;
+}
+
+const struct ethtool_ops qlcnic_ethtool_ops = {
+        .get_settings = qlcnic_get_settings,
+        .set_settings = qlcnic_set_settings,
+        .get_drvinfo = qlcnic_get_drvinfo,
+        .get_regs_len = qlcnic_get_regs_len,
+        .get_regs = qlcnic_get_regs,
+        .get_link = ethtool_op_get_link,
+        .get_eeprom_len = qlcnic_get_eeprom_len,
+        .get_eeprom = qlcnic_get_eeprom,
+        .get_ringparam = qlcnic_get_ringparam,
+        .set_ringparam = qlcnic_set_ringparam,
+        .get_channels = qlcnic_get_channels,
+        .set_channels = qlcnic_set_channels,
+        .get_pauseparam = qlcnic_get_pauseparam,
+        .set_pauseparam = qlcnic_set_pauseparam,
+        .get_wol = qlcnic_get_wol,
+        .set_wol = qlcnic_set_wol,
+        .self_test = qlcnic_diag_test,
+        .get_strings = qlcnic_get_strings,
+        .get_ethtool_stats = qlcnic_get_ethtool_stats,
+        .get_sset_count = qlcnic_get_sset_count,
+        .get_coalesce = qlcnic_get_intr_coalesce,
+        .set_coalesce = qlcnic_set_intr_coalesce,
+        .set_phys_id = qlcnic_set_led,
+        .set_msglevel = qlcnic_set_msglevel,
+        .get_msglevel = qlcnic_get_msglevel,
+        .get_dump_flag = qlcnic_get_dump_flag,
+        .get_dump_data = qlcnic_get_dump_data,
+        .set_dump = qlcnic_set_dump,
+};
diff --git a/drivers/net/qlcnic/qlcnic_hdr.h b/drivers/net/qlcnic/qlcnic_hdr.h
new file mode 100644
index 00000000000..d14506f764e
--- /dev/null
+++ b/drivers/net/qlcnic/qlcnic_hdr.h
@@ -0,0 +1,1023 @@
+/*
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
+ *
+ * See LICENSE.qlcnic for copyright and licensing details.
+ */
+
+#ifndef __QLCNIC_HDR_H_
+#define __QLCNIC_HDR_H_
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+/*
+ * The basic unit of access when reading/writing control registers.
+ */
+
+enum {
+        QLCNIC_HW_H0_CH_HUB_ADR = 0x05,
+        QLCNIC_HW_H1_CH_HUB_ADR = 0x0E,
+        QLCNIC_HW_H2_CH_HUB_ADR = 0x03,
+        QLCNIC_HW_H3_CH_HUB_ADR = 0x01,
+        QLCNIC_HW_H4_CH_HUB_ADR = 0x06,
+        QLCNIC_HW_H5_CH_HUB_ADR = 0x07,
+        QLCNIC_HW_H6_CH_HUB_ADR = 0x08
+};
+
+/*  Hub 0 */
+enum {
+        QLCNIC_HW_MN_CRB_AGT_ADR = 0x15,
+        QLCNIC_HW_MS_CRB_AGT_ADR = 0x25
+};
+
+/*  Hub 1 */
+enum {
+        QLCNIC_HW_PS_CRB_AGT_ADR = 0x73,
+        QLCNIC_HW_SS_CRB_AGT_ADR = 0x20,
+        QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b,
+        QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00,
+        QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01,
+        QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02,
+        QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03,
+        QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04,
+        QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58,
+        QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59,
+        QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a,
+        QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a,
+        QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c,
+        QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f,
+        QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12,
+        QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18
+};
+
+/*  Hub 2 */
+enum {
+        QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31,
+        QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19,
+        QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29,
+
+        QLCNIC_HW_SN_CRB_AGT_ADR = 0x10,
+        QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20,
+        QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22,
+        QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21,
+        QLCNIC_HW_QM_CRB_AGT_ADR = 0x66,
+        QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60,
+        QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61,
+        QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62,
+        QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63,
+        QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09,
+        QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d,
+        QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e,
+        QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11
+};
+
+/*  Hub 3 */
+enum {
+        QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A,
+        QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50,
+        QLCNIC_HW_EG_CRB_AGT_ADR = 0x51,
+        QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08
+};
+
+/*  Hub 4 */
+enum {
+        QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40,
+        QLCNIC_HW_PEGN1_CRB_AGT_ADR,
+        QLCNIC_HW_PEGN2_CRB_AGT_ADR,
+        QLCNIC_HW_PEGN3_CRB_AGT_ADR,
+        QLCNIC_HW_PEGNI_CRB_AGT_ADR,
+        QLCNIC_HW_PEGND_CRB_AGT_ADR,
+        QLCNIC_HW_PEGNC_CRB_AGT_ADR,
+        QLCNIC_HW_PEGR0_CRB_AGT_ADR,
+        QLCNIC_HW_PEGR1_CRB_AGT_ADR,
+        QLCNIC_HW_PEGR2_CRB_AGT_ADR,
+        QLCNIC_HW_PEGR3_CRB_AGT_ADR,
+        QLCNIC_HW_PEGN4_CRB_AGT_ADR
+};
+
+/*  Hub 5 */
+enum {
+        QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40,
+        QLCNIC_HW_PEGS1_CRB_AGT_ADR,
+        QLCNIC_HW_PEGS2_CRB_AGT_ADR,
+        QLCNIC_HW_PEGS3_CRB_AGT_ADR,
+        QLCNIC_HW_PEGSI_CRB_AGT_ADR,
+        QLCNIC_HW_PEGSD_CRB_AGT_ADR,
+        QLCNIC_HW_PEGSC_CRB_AGT_ADR
+};
+
+/*  Hub 6 */
+enum {
+        QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46,
+        QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47,
+        QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48,
+        QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49,
+        QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16,
+        QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17,
+        QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05,
+        QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06,
+        QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07
+};
+
+/*  Floaters - non existent modules */
+#define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
+
+/*  This field defines PCI/X adr [25:20] of agents on the CRB */
+enum {
+        QLCNIC_HW_PX_MAP_CRB_PH = 0,
+        QLCNIC_HW_PX_MAP_CRB_PS,
+        QLCNIC_HW_PX_MAP_CRB_MN,
+        QLCNIC_HW_PX_MAP_CRB_MS,
+        QLCNIC_HW_PX_MAP_CRB_PGR1,
+        QLCNIC_HW_PX_MAP_CRB_SRE,
+        QLCNIC_HW_PX_MAP_CRB_NIU,
+        QLCNIC_HW_PX_MAP_CRB_QMN,
+        QLCNIC_HW_PX_MAP_CRB_SQN0,
+        QLCNIC_HW_PX_MAP_CRB_SQN1,
+        QLCNIC_HW_PX_MAP_CRB_SQN2,
+        QLCNIC_HW_PX_MAP_CRB_SQN3,
+        QLCNIC_HW_PX_MAP_CRB_QMS,
+        QLCNIC_HW_PX_MAP_CRB_SQS0,
+        QLCNIC_HW_PX_MAP_CRB_SQS1,
+        QLCNIC_HW_PX_MAP_CRB_SQS2,
+        QLCNIC_HW_PX_MAP_CRB_SQS3,
+        QLCNIC_HW_PX_MAP_CRB_PGN0,
+        QLCNIC_HW_PX_MAP_CRB_PGN1,
+        QLCNIC_HW_PX_MAP_CRB_PGN2,
+        QLCNIC_HW_PX_MAP_CRB_PGN3,
+        QLCNIC_HW_PX_MAP_CRB_PGND,
+        QLCNIC_HW_PX_MAP_CRB_PGNI,
+        QLCNIC_HW_PX_MAP_CRB_PGS0,
+        QLCNIC_HW_PX_MAP_CRB_PGS1,
+        QLCNIC_HW_PX_MAP_CRB_PGS2,
+        QLCNIC_HW_PX_MAP_CRB_PGS3,
+        QLCNIC_HW_PX_MAP_CRB_PGSD,
+        QLCNIC_HW_PX_MAP_CRB_PGSI,
+        QLCNIC_HW_PX_MAP_CRB_SN,
+        QLCNIC_HW_PX_MAP_CRB_PGR2,
+        QLCNIC_HW_PX_MAP_CRB_EG,
+        QLCNIC_HW_PX_MAP_CRB_PH2,
+        QLCNIC_HW_PX_MAP_CRB_PS2,
+        QLCNIC_HW_PX_MAP_CRB_CAM,
+        QLCNIC_HW_PX_MAP_CRB_CAS0,
+        QLCNIC_HW_PX_MAP_CRB_CAS1,
+        QLCNIC_HW_PX_MAP_CRB_CAS2,
+        QLCNIC_HW_PX_MAP_CRB_C2C0,
+        QLCNIC_HW_PX_MAP_CRB_C2C1,
+        QLCNIC_HW_PX_MAP_CRB_TIMR,
+        QLCNIC_HW_PX_MAP_CRB_PGR3,
+        QLCNIC_HW_PX_MAP_CRB_RPMX1,
+        QLCNIC_HW_PX_MAP_CRB_RPMX2,
+        QLCNIC_HW_PX_MAP_CRB_RPMX3,
+        QLCNIC_HW_PX_MAP_CRB_RPMX4,
+        QLCNIC_HW_PX_MAP_CRB_RPMX5,
+        QLCNIC_HW_PX_MAP_CRB_RPMX6,
+        QLCNIC_HW_PX_MAP_CRB_RPMX7,
+        QLCNIC_HW_PX_MAP_CRB_XDMA,
+        QLCNIC_HW_PX_MAP_CRB_I2Q,
+        QLCNIC_HW_PX_MAP_CRB_ROMUSB,
+        QLCNIC_HW_PX_MAP_CRB_CAS3,
+        QLCNIC_HW_PX_MAP_CRB_RPMX0,
+        QLCNIC_HW_PX_MAP_CRB_RPMX8,
+        QLCNIC_HW_PX_MAP_CRB_RPMX9,
+        QLCNIC_HW_PX_MAP_CRB_OCM0,
+        QLCNIC_HW_PX_MAP_CRB_OCM1,
+        QLCNIC_HW_PX_MAP_CRB_SMB,
+        QLCNIC_HW_PX_MAP_CRB_I2C0,
+        QLCNIC_HW_PX_MAP_CRB_I2C1,
+        QLCNIC_HW_PX_MAP_CRB_LPC,
+        QLCNIC_HW_PX_MAP_CRB_PGNC,
+        QLCNIC_HW_PX_MAP_CRB_PGR0
+};
+
+#define BIT_0   0x1
+#define BIT_1   0x2
+#define BIT_2   0x4
+#define BIT_3   0x8
+#define BIT_4   0x10
+#define BIT_5   0x20
+#define BIT_6   0x40
+#define BIT_7   0x80
+#define BIT_8   0x100
+#define BIT_9   0x200
+#define BIT_10  0x400
+#define BIT_11  0x800
+#define BIT_12  0x1000
+#define BIT_13  0x2000
+#define BIT_14  0x4000
+#define BIT_15  0x8000
+#define BIT_16  0x10000
+#define BIT_17  0x20000
+#define BIT_18  0x40000
+#define BIT_19  0x80000
+#define BIT_20  0x100000
+#define BIT_21  0x200000
+#define BIT_22  0x400000
+#define BIT_23  0x800000
+#define BIT_24  0x1000000
+#define BIT_25  0x2000000
+#define BIT_26  0x4000000
+#define BIT_27  0x8000000
+#define BIT_28  0x10000000
+#define BIT_29  0x20000000
+#define BIT_30  0x40000000
+#define BIT_31  0x80000000
+
+/*  This field defines CRB adr [31:20] of the agents */
+
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_MN    \
+        ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PH    \
+        ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_MS    \
+        ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR)
+
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PS    \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SS    \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS   \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0  \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1  \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2  \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3  \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0  \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1  \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB   \
+        ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR)
+
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU   \
+        ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0  \
+        ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1  \
+        ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR)
+
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE   \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_EG    \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN   \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3  \
+        ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR)
+
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3  \
+        ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR)
+
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI  \
+        ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD  \
+        ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0  \
+        ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1  \
+        ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2  \
+        ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3  \
+        ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC  \
+        ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR)
+
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM   \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR  \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA  \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_SN    \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q   \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB        \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0  \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1  \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR)
+#define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC   \
+        ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR)
+
+#define QLCNIC_SRE_MISC         (QLCNIC_CRB_SRE + 0x0002c)
+
+#define QLCNIC_I2Q_CLR_PCI_HI   (QLCNIC_CRB_I2Q + 0x00034)
+
+#define ROMUSB_GLB              (QLCNIC_CRB_ROMUSB + 0x00000)
+#define ROMUSB_ROM              (QLCNIC_CRB_ROMUSB + 0x10000)
+
+#define QLCNIC_ROMUSB_GLB_STATUS        (ROMUSB_GLB + 0x0004)
+#define QLCNIC_ROMUSB_GLB_SW_RESET      (ROMUSB_GLB + 0x0008)
+#define QLCNIC_ROMUSB_GLB_PAD_GPIO_I    (ROMUSB_GLB + 0x000c)
+#define QLCNIC_ROMUSB_GLB_CAS_RST       (ROMUSB_GLB + 0x0038)
+#define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL  (ROMUSB_GLB + 0x0044)
+#define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE  (ROMUSB_GLB + 0x005c)
+#define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
+
+#define QLCNIC_ROMUSB_GPIO(n)           (ROMUSB_GLB + 0x60 + (4 * (n)))
+
+#define QLCNIC_ROMUSB_ROM_INSTR_OPCODE  (ROMUSB_ROM + 0x0004)
+#define QLCNIC_ROMUSB_ROM_ADDRESS       (ROMUSB_ROM + 0x0008)
+#define QLCNIC_ROMUSB_ROM_WDATA         (ROMUSB_ROM + 0x000c)
+#define QLCNIC_ROMUSB_ROM_ABYTE_CNT     (ROMUSB_ROM + 0x0010)
+#define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
+#define QLCNIC_ROMUSB_ROM_RDATA         (ROMUSB_ROM + 0x0018)
+
+/* Lock IDs for ROM lock */
+#define ROM_LOCK_DRIVER 0x0d417340
+
+/******************************************************************************
+*
+*    Definitions specific to M25P flash
+*
+*******************************************************************************
+*/
+
+/* all are 1MB windows */
+
+#define QLCNIC_PCI_CRB_WINDOWSIZE       0x00100000
+#define QLCNIC_PCI_CRB_WINDOW(A)        \
+        (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE)
+
+#define QLCNIC_CRB_NIU          QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU)
+#define QLCNIC_CRB_SRE          QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE)
+#define QLCNIC_CRB_ROMUSB       \
+        QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB)
+#define QLCNIC_CRB_I2Q          QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q)
+#define QLCNIC_CRB_I2C0         QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0)
+#define QLCNIC_CRB_SMB          QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB)
+#define QLCNIC_CRB_MAX          QLCNIC_PCI_CRB_WINDOW(64)
+
+#define QLCNIC_CRB_PCIX_HOST    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH)
+#define QLCNIC_CRB_PCIX_HOST2   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2)
+#define QLCNIC_CRB_PEG_NET_0    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0)
+#define QLCNIC_CRB_PEG_NET_1    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1)
+#define QLCNIC_CRB_PEG_NET_2    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2)
+#define QLCNIC_CRB_PEG_NET_3    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3)
+#define QLCNIC_CRB_PEG_NET_4    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2)
+#define QLCNIC_CRB_PEG_NET_D    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND)
+#define QLCNIC_CRB_PEG_NET_I    QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI)
+#define QLCNIC_CRB_DDR_NET      QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN)
+#define QLCNIC_CRB_QDR_NET      QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN)
+
+#define QLCNIC_CRB_PCIX_MD      QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS)
+#define QLCNIC_CRB_PCIE         QLCNIC_CRB_PCIX_MD
+
+#define ISR_INT_VECTOR          (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR))
+#define ISR_INT_MASK            (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
+#define ISR_INT_MASK_SLOW       (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
+#define ISR_INT_TARGET_STATUS   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS))
+#define ISR_INT_TARGET_MASK     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK))
+#define ISR_INT_TARGET_STATUS_F1   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
+#define ISR_INT_TARGET_MASK_F1     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
+#define ISR_INT_TARGET_STATUS_F2   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
+#define ISR_INT_TARGET_MASK_F2     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
+#define ISR_INT_TARGET_STATUS_F3   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
+#define ISR_INT_TARGET_MASK_F3     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
+#define ISR_INT_TARGET_STATUS_F4   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
+#define ISR_INT_TARGET_MASK_F4     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
+#define ISR_INT_TARGET_STATUS_F5   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
+#define ISR_INT_TARGET_MASK_F5     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
+#define ISR_INT_TARGET_STATUS_F6   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
+#define ISR_INT_TARGET_MASK_F6     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
+#define ISR_INT_TARGET_STATUS_F7   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
+#define ISR_INT_TARGET_MASK_F7     (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
+
+#define QLCNIC_PCI_MN_2M        (0)
+#define QLCNIC_PCI_MS_2M        (0x80000)
+#define QLCNIC_PCI_OCM0_2M      (0x000c0000UL)
+#define QLCNIC_PCI_CRBSPACE     (0x06000000UL)
+#define QLCNIC_PCI_CAMQM        (0x04800000UL)
+#define QLCNIC_PCI_CAMQM_END    (0x04800800UL)
+#define QLCNIC_PCI_2MB_SIZE     (0x00200000UL)
+#define QLCNIC_PCI_CAMQM_2M_BASE        (0x000ff800UL)
+
+#define QLCNIC_CRB_CAM  QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM)
+
+#define QLCNIC_ADDR_DDR_NET     (0x0000000000000000ULL)
+#define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
+#define QLCNIC_ADDR_OCM0        (0x0000000200000000ULL)
+#define QLCNIC_ADDR_OCM0_MAX    (0x00000002000fffffULL)
+#define QLCNIC_ADDR_OCM1        (0x0000000200400000ULL)
+#define QLCNIC_ADDR_OCM1_MAX    (0x00000002004fffffULL)
+#define QLCNIC_ADDR_QDR_NET     (0x0000000300000000ULL)
+#define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
+
+/*
+ *   Register offsets for MN
+ */
+#define QLCNIC_MIU_CONTROL      (0x000)
+#define QLCNIC_MIU_MN_CONTROL   (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL)
+
+/* 200ms delay in each loop */
+#define QLCNIC_NIU_PHY_WAITLEN          200000
+/* 10 seconds before we give up */
+#define QLCNIC_NIU_PHY_WAITMAX          50
+#define QLCNIC_NIU_MAX_GBE_PORTS        4
+#define QLCNIC_NIU_MAX_XG_PORTS         2
+
+#define QLCNIC_NIU_MODE                 (QLCNIC_CRB_NIU + 0x00000)
+#define QLCNIC_NIU_GB_PAUSE_CTL         (QLCNIC_CRB_NIU + 0x0030c)
+#define QLCNIC_NIU_XG_PAUSE_CTL         (QLCNIC_CRB_NIU + 0x00098)
+
+#define QLCNIC_NIU_GB_MAC_CONFIG_0(I)           \
+                (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000)
+#define QLCNIC_NIU_GB_MAC_CONFIG_1(I)           \
+                (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)
+
+
+#define TEST_AGT_CTRL   (0x00)
+
+#define TA_CTL_START    BIT_0
+#define TA_CTL_ENABLE   BIT_1
+#define TA_CTL_WRITE    BIT_2
+#define TA_CTL_BUSY     BIT_3
+
+/*
+ *   Register offsets for MN
+ */
+#define MIU_TEST_AGT_BASE               (0x90)
+
+#define MIU_TEST_AGT_ADDR_LO            (0x04)
+#define MIU_TEST_AGT_ADDR_HI            (0x08)
+#define MIU_TEST_AGT_WRDATA_LO          (0x10)
+#define MIU_TEST_AGT_WRDATA_HI          (0x14)
+#define MIU_TEST_AGT_WRDATA_UPPER_LO    (0x20)
+#define MIU_TEST_AGT_WRDATA_UPPER_HI    (0x24)
+#define MIU_TEST_AGT_WRDATA(i)          (0x10+(0x10*((i)>>1))+(4*((i)&1)))
+#define MIU_TEST_AGT_RDDATA_LO          (0x18)
+#define MIU_TEST_AGT_RDDATA_HI          (0x1c)
+#define MIU_TEST_AGT_RDDATA_UPPER_LO    (0x28)
+#define MIU_TEST_AGT_RDDATA_UPPER_HI    (0x2c)
+#define MIU_TEST_AGT_RDDATA(i)          (0x18+(0x10*((i)>>1))+(4*((i)&1)))
+
+#define MIU_TEST_AGT_ADDR_MASK          0xfffffff8
+#define MIU_TEST_AGT_UPPER_ADDR(off)    (0)
+
+/*
+ *   Register offsets for MS
+ */
+#define SIU_TEST_AGT_BASE               (0x60)
+
+#define SIU_TEST_AGT_ADDR_LO            (0x04)
+#define SIU_TEST_AGT_ADDR_HI            (0x18)
+#define SIU_TEST_AGT_WRDATA_LO          (0x08)
+#define SIU_TEST_AGT_WRDATA_HI          (0x0c)
+#define SIU_TEST_AGT_WRDATA(i)          (0x08+(4*(i)))
+#define SIU_TEST_AGT_RDDATA_LO          (0x10)
+#define SIU_TEST_AGT_RDDATA_HI          (0x14)
+#define SIU_TEST_AGT_RDDATA(i)          (0x10+(4*(i)))
+
+#define SIU_TEST_AGT_ADDR_MASK          0x3ffff8
+#define SIU_TEST_AGT_UPPER_ADDR(off)    ((off)>>22)
+
+/* XG Link status */
+#define XG_LINK_UP      0x10
+#define XG_LINK_DOWN    0x20
+
+#define XG_LINK_UP_P3P  0x01
+#define XG_LINK_DOWN_P3P        0x02
+#define XG_LINK_STATE_P3P_MASK 0xf
+#define XG_LINK_STATE_P3P(pcifn, val) \
+        (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK)
+
+#define P3P_LINK_SPEED_MHZ      100
+#define P3P_LINK_SPEED_MASK     0xff
+#define P3P_LINK_SPEED_REG(pcifn)       \
+        (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4))
+#define P3P_LINK_SPEED_VAL(pcifn, reg)  \
+        (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK)
+
+#define QLCNIC_CAM_RAM_BASE     (QLCNIC_CRB_CAM + 0x02000)
+#define QLCNIC_CAM_RAM(reg)     (QLCNIC_CAM_RAM_BASE + (reg))
+#define QLCNIC_FW_VERSION_MAJOR (QLCNIC_CAM_RAM(0x150))
+#define QLCNIC_FW_VERSION_MINOR (QLCNIC_CAM_RAM(0x154))
+#define QLCNIC_FW_VERSION_SUB   (QLCNIC_CAM_RAM(0x158))
+#define QLCNIC_ROM_LOCK_ID      (QLCNIC_CAM_RAM(0x100))
+#define QLCNIC_PHY_LOCK_ID      (QLCNIC_CAM_RAM(0x120))
+#define QLCNIC_CRB_WIN_LOCK_ID  (QLCNIC_CAM_RAM(0x124))
+
+#define NIC_CRB_BASE            (QLCNIC_CAM_RAM(0x200))
+#define NIC_CRB_BASE_2          (QLCNIC_CAM_RAM(0x700))
+#define QLCNIC_REG(X)           (NIC_CRB_BASE+(X))
+#define QLCNIC_REG_2(X)         (NIC_CRB_BASE_2+(X))
+
+#define QLCNIC_CDRP_CRB_OFFSET          (QLCNIC_REG(0x18))
+#define QLCNIC_ARG1_CRB_OFFSET          (QLCNIC_REG(0x1c))
+#define QLCNIC_ARG2_CRB_OFFSET          (QLCNIC_REG(0x20))
+#define QLCNIC_ARG3_CRB_OFFSET          (QLCNIC_REG(0x24))
+#define QLCNIC_SIGN_CRB_OFFSET          (QLCNIC_REG(0x28))
+
+#define CRB_CMDPEG_STATE                (QLCNIC_REG(0x50))
+#define CRB_RCVPEG_STATE                (QLCNIC_REG(0x13c))
+
+#define CRB_XG_STATE_P3P                (QLCNIC_REG(0x98))
+#define CRB_PF_LINK_SPEED_1             (QLCNIC_REG(0xe8))
+#define CRB_PF_LINK_SPEED_2             (QLCNIC_REG(0xec))
+
+#define CRB_TEMP_STATE                  (QLCNIC_REG(0x1b4))
+
+#define CRB_V2P_0                       (QLCNIC_REG(0x290))
+#define CRB_V2P(port)                   (CRB_V2P_0+((port)*4))
+#define CRB_DRIVER_VERSION              (QLCNIC_REG(0x2a0))
+
+#define CRB_FW_CAPABILITIES_1           (QLCNIC_CAM_RAM(0x128))
+#define CRB_MAC_BLOCK_START             (QLCNIC_CAM_RAM(0x1c0))
+
+/*
+ * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
+ * which can be read by the Phantom host to get producer/consumer indexes from
+ * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
+ * registers will be used for the addresses of the ring's shared memory
+ * on the Phantom.
+ */
+
+#define qlcnic_get_temp_val(x)          ((x) >> 16)
+#define qlcnic_get_temp_state(x)        ((x) & 0xffff)
+#define qlcnic_encode_temp(val, state)  (((val) << 16) | (state))
+
+/*
+ * Temperature control.
+ */
+enum {
+        QLCNIC_TEMP_NORMAL = 0x1,       /* Normal operating range */
+        QLCNIC_TEMP_WARN,       /* Sound alert, temperature getting high */
+        QLCNIC_TEMP_PANIC       /* Fatal error, hardware has shut down. */
+};
+
+/* Lock IDs for PHY lock */
+#define PHY_LOCK_DRIVER         0x44524956
+
+/* Used for PS PCI Memory access */
+#define PCIX_PS_OP_ADDR_LO      (0x10000)
+/*   via CRB  (PS side only)     */
+#define PCIX_PS_OP_ADDR_HI      (0x10004)
+
+#define PCIX_INT_VECTOR         (0x10100)
+#define PCIX_INT_MASK           (0x10104)
+
+#define PCIX_OCM_WINDOW         (0x10800)
+#define PCIX_OCM_WINDOW_REG(func)       (PCIX_OCM_WINDOW + 0x4 * (func))
+
+#define PCIX_TARGET_STATUS      (0x10118)
+#define PCIX_TARGET_STATUS_F1   (0x10160)
+#define PCIX_TARGET_STATUS_F2   (0x10164)
+#define PCIX_TARGET_STATUS_F3   (0x10168)
+#define PCIX_TARGET_STATUS_F4   (0x10360)
+#define PCIX_TARGET_STATUS_F5   (0x10364)
+#define PCIX_TARGET_STATUS_F6   (0x10368)
+#define PCIX_TARGET_STATUS_F7   (0x1036c)
+
+#define PCIX_TARGET_MASK        (0x10128)
+#define PCIX_TARGET_MASK_F1     (0x10170)
+#define PCIX_TARGET_MASK_F2     (0x10174)
+#define PCIX_TARGET_MASK_F3     (0x10178)
+#define PCIX_TARGET_MASK_F4     (0x10370)
+#define PCIX_TARGET_MASK_F5     (0x10374)
+#define PCIX_TARGET_MASK_F6     (0x10378)
+#define PCIX_TARGET_MASK_F7     (0x1037c)
+
+#define PCIX_MSI_F(i)           (0x13000+((i)*4))
+
+#define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg))
+#define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg))
+#define QLCNIC_PCIE_REG(reg)    (QLCNIC_CRB_PCIE + (reg))
+
+#define PCIE_SEM0_LOCK          (0x1c000)
+#define PCIE_SEM0_UNLOCK        (0x1c004)
+#define PCIE_SEM_LOCK(N)        (PCIE_SEM0_LOCK + 8*(N))
+#define PCIE_SEM_UNLOCK(N)      (PCIE_SEM0_UNLOCK + 8*(N))
+
+#define PCIE_SETUP_FUNCTION     (0x12040)
+#define PCIE_SETUP_FUNCTION2    (0x12048)
+#define PCIE_MISCCFG_RC         (0x1206c)
+#define PCIE_TGT_SPLIT_CHICKEN  (0x12080)
+#define PCIE_CHICKEN3           (0x120c8)
+
+#define ISR_INT_STATE_REG       (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC))
+#define PCIE_MAX_MASTER_SPLIT   (0x14048)
+
+#define QLCNIC_PORT_MODE_NONE           0
+#define QLCNIC_PORT_MODE_XG             1
+#define QLCNIC_PORT_MODE_GB             2
+#define QLCNIC_PORT_MODE_802_3_AP       3
+#define QLCNIC_PORT_MODE_AUTO_NEG       4
+#define QLCNIC_PORT_MODE_AUTO_NEG_1G    5
+#define QLCNIC_PORT_MODE_AUTO_NEG_XG    6
+#define QLCNIC_PORT_MODE_ADDR           (QLCNIC_CAM_RAM(0x24))
+#define QLCNIC_WOL_PORT_MODE            (QLCNIC_CAM_RAM(0x198))
+
+#define QLCNIC_WOL_CONFIG_NV            (QLCNIC_CAM_RAM(0x184))
+#define QLCNIC_WOL_CONFIG               (QLCNIC_CAM_RAM(0x188))
+
+#define QLCNIC_PEG_TUNE_MN_PRESENT      0x1
+#define QLCNIC_PEG_TUNE_CAPABILITY      (QLCNIC_CAM_RAM(0x02c))
+
+#define QLCNIC_DMA_WATCHDOG_CTRL        (QLCNIC_CAM_RAM(0x14))
+#define QLCNIC_PEG_ALIVE_COUNTER        (QLCNIC_CAM_RAM(0xb0))
+#define QLCNIC_PEG_HALT_STATUS1         (QLCNIC_CAM_RAM(0xa8))
+#define QLCNIC_PEG_HALT_STATUS2         (QLCNIC_CAM_RAM(0xac))
+#define QLCNIC_CRB_DRV_ACTIVE   (QLCNIC_CAM_RAM(0x138))
+#define QLCNIC_CRB_DEV_STATE            (QLCNIC_CAM_RAM(0x140))
+
+#define QLCNIC_CRB_DRV_STATE            (QLCNIC_CAM_RAM(0x144))
+#define QLCNIC_CRB_DRV_SCRATCH          (QLCNIC_CAM_RAM(0x148))
+#define QLCNIC_CRB_DEV_PARTITION_INFO   (QLCNIC_CAM_RAM(0x14c))
+#define QLCNIC_CRB_DRV_IDC_VER          (QLCNIC_CAM_RAM(0x174))
+#define QLCNIC_CRB_DEV_NPAR_STATE       (QLCNIC_CAM_RAM(0x19c))
+#define QLCNIC_ROM_DEV_INIT_TIMEOUT     (0x3e885c)
+#define QLCNIC_ROM_DRV_RESET_TIMEOUT    (0x3e8860)
+
+/* Device State */
+#define QLCNIC_DEV_COLD                 0x1
+#define QLCNIC_DEV_INITIALIZING         0x2
+#define QLCNIC_DEV_READY                0x3
+#define QLCNIC_DEV_NEED_RESET           0x4
+#define QLCNIC_DEV_NEED_QUISCENT        0x5
+#define QLCNIC_DEV_FAILED               0x6
+#define QLCNIC_DEV_QUISCENT             0x7
+
+#define QLCNIC_DEV_NPAR_NON_OPER        0 /* NON Operational */
+#define QLCNIC_DEV_NPAR_OPER            1 /* NPAR Operational */
+#define QLCNIC_DEV_NPAR_OPER_TIMEO      30 /* Operational time out */
+
+#define QLC_DEV_CHECK_ACTIVE(VAL, FN)           ((VAL) & (1 << (FN * 4)))
+#define QLC_DEV_SET_REF_CNT(VAL, FN)            ((VAL) |= (1 << (FN * 4)))
+#define QLC_DEV_CLR_REF_CNT(VAL, FN)            ((VAL) &= ~(1 << (FN * 4)))
+#define QLC_DEV_SET_RST_RDY(VAL, FN)            ((VAL) |= (1 << (FN * 4)))
+#define QLC_DEV_SET_QSCNT_RDY(VAL, FN)          ((VAL) |= (2 << (FN * 4)))
+#define QLC_DEV_CLR_RST_QSCNT(VAL, FN)          ((VAL) &= ~(3 << (FN * 4)))
+
+#define QLC_DEV_GET_DRV(VAL, FN)                (0xf & ((VAL) >> (FN * 4)))
+#define QLC_DEV_SET_DRV(VAL, FN)                ((VAL) << (FN * 4))
+
+#define QLCNIC_TYPE_NIC         1
+#define QLCNIC_TYPE_FCOE                2
+#define QLCNIC_TYPE_ISCSI               3
+
+#define QLCNIC_RCODE_DRIVER_INFO                0x20000000
+#define QLCNIC_RCODE_DRIVER_CAN_RELOAD          BIT_30
+#define QLCNIC_RCODE_FATAL_ERROR                BIT_31
+#define QLCNIC_FWERROR_PEGNUM(code)             ((code) & 0xff)
+#define QLCNIC_FWERROR_CODE(code)               ((code >> 8) & 0xfffff)
+
+#define FW_POLL_DELAY           (1 * HZ)
+#define FW_FAIL_THRESH          2
+
+#define QLCNIC_RESET_TIMEOUT_SECS       10
+#define QLCNIC_INIT_TIMEOUT_SECS        30
+#define QLCNIC_RCVPEG_CHECK_RETRY_COUNT 2000
+#define QLCNIC_RCVPEG_CHECK_DELAY       10
+#define QLCNIC_CMDPEG_CHECK_RETRY_COUNT 60
+#define QLCNIC_CMDPEG_CHECK_DELAY       500
+#define QLCNIC_HEARTBEAT_PERIOD_MSECS   200
+#define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT      45
+
+#define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
+#define ISR_LEGACY_INT_TRIGGERED(VAL)   (((VAL) & 0x300) == 0x200)
+
+/*
+ * PCI Interrupt Vector Values.
+ */
+#define PCIX_INT_VECTOR_BIT_F0  0x0080
+#define PCIX_INT_VECTOR_BIT_F1  0x0100
+#define PCIX_INT_VECTOR_BIT_F2  0x0200
+#define PCIX_INT_VECTOR_BIT_F3  0x0400
+#define PCIX_INT_VECTOR_BIT_F4  0x0800
+#define PCIX_INT_VECTOR_BIT_F5  0x1000
+#define PCIX_INT_VECTOR_BIT_F6  0x2000
+#define PCIX_INT_VECTOR_BIT_F7  0x4000
+
+struct qlcnic_legacy_intr_set {
+        u32     int_vec_bit;
+        u32     tgt_status_reg;
+        u32     tgt_mask_reg;
+        u32     pci_int_reg;
+};
+
+#define QLCNIC_FW_API           0x1b216c
+#define QLCNIC_DRV_OP_MODE      0x1b2170
+#define QLCNIC_MSIX_BASE        0x132110
+#define QLCNIC_MAX_PCI_FUNC     8
+#define QLCNIC_MAX_VLAN_FILTERS 64
+
+/* FW dump defines */
+#define MIU_TEST_CTR            0x41000090
+#define MIU_TEST_ADDR_LO        0x41000094
+#define MIU_TEST_ADDR_HI        0x41000098
+#define FLASH_ROM_WINDOW        0x42110030
+#define FLASH_ROM_DATA          0x42150000
+
+static const u32 MIU_TEST_READ_DATA[] = {
+        0x410000A8, 0x410000AC, 0x410000B8, 0x410000BC, };
+
+#define QLCNIC_FW_DUMP_REG1     0x00130060
+#define QLCNIC_FW_DUMP_REG2     0x001e0000
+#define QLCNIC_FLASH_SEM2_LK    0x0013C010
+#define QLCNIC_FLASH_SEM2_ULK   0x0013C014
+#define QLCNIC_FLASH_LOCK_ID    0x001B2100
+
+#define QLCNIC_RD_DUMP_REG(addr, bar0, data) do {                       \
+        writel((addr & 0xFFFF0000), (void *) (bar0 +                    \
+                QLCNIC_FW_DUMP_REG1));                                  \
+        readl((void *) (bar0 + QLCNIC_FW_DUMP_REG1));                   \
+        *data = readl((void *) (bar0 + QLCNIC_FW_DUMP_REG2 +            \
+                LSW(addr)));                                            \
+} while (0)
+
+#define QLCNIC_WR_DUMP_REG(addr, bar0, data) do {                       \
+        writel((addr & 0xFFFF0000), (void *) (bar0 +                    \
+                QLCNIC_FW_DUMP_REG1));                                  \
+        readl((void *) (bar0 + QLCNIC_FW_DUMP_REG1));                   \
+        writel(data, (void *) (bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr)));\
+        readl((void *) (bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr)));       \
+} while (0)
+
+/* PCI function operational mode */
+enum {
+        QLCNIC_MGMT_FUNC        = 0,
+        QLCNIC_PRIV_FUNC        = 1,
+        QLCNIC_NON_PRIV_FUNC    = 2
+};
+
+enum {
+        QLCNIC_PORT_DEFAULTS    = 0,
+        QLCNIC_ADD_VLAN = 1,
+        QLCNIC_DEL_VLAN = 2
+};
+
+#define QLC_DEV_DRV_DEFAULT 0x11111111
+
+#define LSB(x)  ((uint8_t)(x))
+#define MSB(x)  ((uint8_t)((uint16_t)(x) >> 8))
+
+#define LSW(x)  ((uint16_t)((uint32_t)(x)))
+#define MSW(x)  ((uint16_t)((uint32_t)(x) >> 16))
+
+#define LSD(x)  ((uint32_t)((uint64_t)(x)))
+#define MSD(x)  ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
+
+#define QLCNIC_LEGACY_INTR_CONFIG                                       \
+{                                                                       \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F0,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS,          \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK,            \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(0) },       \
+                                                                        \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F1,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS_F1,       \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK_F1,         \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(1) },       \
+                                                                        \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F2,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS_F2,       \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK_F2,         \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(2) },       \
+                                                                        \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F3,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS_F3,       \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK_F3,         \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(3) },       \
+                                                                        \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F4,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS_F4,       \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK_F4,         \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(4) },       \
+                                                                        \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F5,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS_F5,       \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK_F5,         \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(5) },       \
+                                                                        \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F6,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS_F6,       \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK_F6,         \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(6) },       \
+                                                                        \
+        {                                                               \
+                .int_vec_bit    =       PCIX_INT_VECTOR_BIT_F7,         \
+                .tgt_status_reg =       ISR_INT_TARGET_STATUS_F7,       \
+                .tgt_mask_reg   =       ISR_INT_TARGET_MASK_F7,         \
+                .pci_int_reg    =       ISR_MSI_INT_TRIGGER(7) },       \
+}
+
+/* NIU REGS */
+
+#define _qlcnic_crb_get_bit(var, bit)  ((var >> bit) & 0x1)
+
+/*
+ * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
+ *
+ *      Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
+ *      Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
+ *      Bit 2 : enable_rx => 1:enable frame recv, 0:disable
+ *      Bit 3 : rx_synced => R/O: recv enable synched to recv stream
+ *      Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
+ *      Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
+ *      Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
+ *      Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
+ *      Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
+ *      Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
+ *      Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
+ *      Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
+ */
+#define qlcnic_gb_rx_flowctl(config_word)       \
+        ((config_word) |= 1 << 5)
+#define qlcnic_gb_get_rx_flowctl(config_word)   \
+        _qlcnic_crb_get_bit((config_word), 5)
+#define qlcnic_gb_unset_rx_flowctl(config_word) \
+        ((config_word) &= ~(1 << 5))
+
+/*
+ * NIU GB Pause Ctl Register
+ */
+
+#define qlcnic_gb_set_gb0_mask(config_word)    \
+        ((config_word) |= 1 << 0)
+#define qlcnic_gb_set_gb1_mask(config_word)    \
+        ((config_word) |= 1 << 2)
+#define qlcnic_gb_set_gb2_mask(config_word)    \
+        ((config_word) |= 1 << 4)
+#define qlcnic_gb_set_gb3_mask(config_word)    \
+        ((config_word) |= 1 << 6)
+
+#define qlcnic_gb_get_gb0_mask(config_word)    \
+        _qlcnic_crb_get_bit((config_word), 0)
+#define qlcnic_gb_get_gb1_mask(config_word)    \
+        _qlcnic_crb_get_bit((config_word), 2)
+#define qlcnic_gb_get_gb2_mask(config_word)    \
+        _qlcnic_crb_get_bit((config_word), 4)
+#define qlcnic_gb_get_gb3_mask(config_word)    \
+        _qlcnic_crb_get_bit((config_word), 6)
+
+#define qlcnic_gb_unset_gb0_mask(config_word)  \
+        ((config_word) &= ~(1 << 0))
+#define qlcnic_gb_unset_gb1_mask(config_word)  \
+        ((config_word) &= ~(1 << 2))
+#define qlcnic_gb_unset_gb2_mask(config_word)  \
+        ((config_word) &= ~(1 << 4))
+#define qlcnic_gb_unset_gb3_mask(config_word)  \
+        ((config_word) &= ~(1 << 6))
+
+/*
+ * NIU XG Pause Ctl Register
+ *
+ *      Bit 0       : xg0_mask => 1:disable tx pause frames
+ *      Bit 1       : xg0_request => 1:request single pause frame
+ *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
+ *      Bit 3       : xg1_mask => 1:disable tx pause frames
+ *      Bit 4       : xg1_request => 1:request single pause frame
+ *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
+ */
+
+#define qlcnic_xg_set_xg0_mask(config_word)    \
+        ((config_word) |= 1 << 0)
+#define qlcnic_xg_set_xg1_mask(config_word)    \
+        ((config_word) |= 1 << 3)
+
+#define qlcnic_xg_get_xg0_mask(config_word)    \
+        _qlcnic_crb_get_bit((config_word), 0)
+#define qlcnic_xg_get_xg1_mask(config_word)    \
+        _qlcnic_crb_get_bit((config_word), 3)
+
+#define qlcnic_xg_unset_xg0_mask(config_word)  \
+        ((config_word) &= ~(1 << 0))
+#define qlcnic_xg_unset_xg1_mask(config_word)  \
+        ((config_word) &= ~(1 << 3))
+
+/*
+ * NIU XG Pause Ctl Register
+ *
+ *      Bit 0       : xg0_mask => 1:disable tx pause frames
+ *      Bit 1       : xg0_request => 1:request single pause frame
+ *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
+ *      Bit 3       : xg1_mask => 1:disable tx pause frames
+ *      Bit 4       : xg1_request => 1:request single pause frame
+ *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
+ */
+
+/*
+ * PHY-Specific MII control/status registers.
+ */
+#define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG             4
+#define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS          17
+
+/*
+ * PHY-Specific Status Register (reg 17).
+ *
+ * Bit 0      : jabber => 1:jabber detected, 0:not
+ * Bit 1      : polarity => 1:polarity reversed, 0:normal
+ * Bit 2      : recvpause => 1:receive pause enabled, 0:disabled
+ * Bit 3      : xmitpause => 1:transmit pause enabled, 0:disabled
+ * Bit 4      : energydetect => 1:sleep, 0:active
+ * Bit 5      : downshift => 1:downshift, 0:no downshift
+ * Bit 6      : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
+ * Bits 7-9   : cablelen => not valid in 10Mb/s mode
+ *                      0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
+ * Bit 10     : link => 1:link up, 0:link down
+ * Bit 11     : resolved => 1:speed and duplex resolved, 0:not yet
+ * Bit 12     : pagercvd => 1:page received, 0:page not received
+ * Bit 13     : duplex => 1:full duplex, 0:half duplex
+ * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
+ */
+
+#define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
+
+#define qlcnic_set_phy_speed(config_word, val)  \
+                ((config_word) |= ((val & 0x03) << 14))
+#define qlcnic_set_phy_duplex(config_word)      \
+                ((config_word) |= 1 << 13)
+#define qlcnic_clear_phy_duplex(config_word)    \
+                ((config_word) &= ~(1 << 13))
+
+#define qlcnic_get_phy_link(config_word)        \
+                _qlcnic_crb_get_bit(config_word, 10)
+#define qlcnic_get_phy_duplex(config_word)      \
+                _qlcnic_crb_get_bit(config_word, 13)
+
+#define QLCNIC_NIU_NON_PROMISC_MODE     0
+#define QLCNIC_NIU_PROMISC_MODE         1
+#define QLCNIC_NIU_ALLMULTI_MODE        2
+
+struct crb_128M_2M_sub_block_map {
+        unsigned valid;
+        unsigned start_128M;
+        unsigned end_128M;
+        unsigned start_2M;
+};
+
+struct crb_128M_2M_block_map{
+        struct crb_128M_2M_sub_block_map sub_block[16];
+};
+#endif                          /* __QLCNIC_HDR_H_ */
diff --git a/drivers/net/qlcnic/qlcnic_hw.c b/drivers/net/qlcnic/qlcnic_hw.c
new file mode 100644
index 00000000000..4055c218ef2
--- /dev/null
+++ b/drivers/net/qlcnic/qlcnic_hw.c
@@ -0,0 +1,1787 @@
+/*
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
+ *
+ * See LICENSE.qlcnic for copyright and licensing details.
+ */
+
+#include "qlcnic.h"
+
+#include <linux/slab.h>
+#include <net/ip.h>
+#include <linux/bitops.h>
+
+#define MASK(n) ((1ULL<<(n))-1)
+#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
+
+#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
+
+#define CRB_BLK(off)    ((off >> 20) & 0x3f)
+#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
+#define CRB_WINDOW_2M   (0x130060)
+#define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
+#define CRB_INDIRECT_2M (0x1e0000UL)
+
+
+#ifndef readq
+static inline u64 readq(void __iomem *addr)
+{
+        return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
+}
+#endif
+
+#ifndef writeq
+static inline void writeq(u64 val, void __iomem *addr)
+{
+        writel(((u32) (val)), (addr));
+        writel(((u32) (val >> 32)), (addr + 4));
+}
+#endif
+
+static const struct crb_128M_2M_block_map
+crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
+    {{{0, 0,         0,         0} } },         /* 0: PCI */
+    {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
+          {1, 0x0110000, 0x0120000, 0x130000},
+          {1, 0x0120000, 0x0122000, 0x124000},
+          {1, 0x0130000, 0x0132000, 0x126000},
+          {1, 0x0140000, 0x0142000, 0x128000},
+          {1, 0x0150000, 0x0152000, 0x12a000},
+          {1, 0x0160000, 0x0170000, 0x110000},
+          {1, 0x0170000, 0x0172000, 0x12e000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {1, 0x01e0000, 0x01e0800, 0x122000},
+          {0, 0x0000000, 0x0000000, 0x000000} } },
+        {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
+    {{{0, 0,         0,         0} } },     /* 3: */
+    {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
+    {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
+    {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
+    {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
+    {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {1, 0x08f0000, 0x08f2000, 0x172000} } },
+    {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {1, 0x09f0000, 0x09f2000, 0x176000} } },
+    {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {1, 0x0af0000, 0x0af2000, 0x17a000} } },
+    {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {0, 0x0000000, 0x0000000, 0x000000},
+      {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
+        {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
+        {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
+        {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
+        {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
+        {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
+        {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
+        {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
+        {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
+        {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
+        {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
+        {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
+        {{{0, 0,         0,         0} } },     /* 23: */
+        {{{0, 0,         0,         0} } },     /* 24: */
+        {{{0, 0,         0,         0} } },     /* 25: */
+        {{{0, 0,         0,         0} } },     /* 26: */
+        {{{0, 0,         0,         0} } },     /* 27: */
+        {{{0, 0,         0,         0} } },     /* 28: */
+        {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
+    {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
+    {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
+        {{{0} } },                              /* 32: PCI */
+        {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
+          {1, 0x2110000, 0x2120000, 0x130000},
+          {1, 0x2120000, 0x2122000, 0x124000},
+          {1, 0x2130000, 0x2132000, 0x126000},
+          {1, 0x2140000, 0x2142000, 0x128000},
+          {1, 0x2150000, 0x2152000, 0x12a000},
+          {1, 0x2160000, 0x2170000, 0x110000},
+          {1, 0x2170000, 0x2172000, 0x12e000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000},
+          {0, 0x0000000, 0x0000000, 0x000000} } },
+        {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
+        {{{0} } },                              /* 35: */
+        {{{0} } },                              /* 36: */
+        {{{0} } },                              /* 37: */
+        {{{0} } },                              /* 38: */
+        {{{0} } },                              /* 39: */
+        {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
+        {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
+        {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
+        {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
+        {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
+        {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
+        {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
+        {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
+        {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
+        {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
+        {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
+        {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
+        {{{0} } },                              /* 52: */
+        {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
+        {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
+        {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
+        {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
+        {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
+        {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
+        {{{0} } },                              /* 59: I2C0 */
+        {{{0} } },                              /* 60: I2C1 */
+        {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
+        {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
+        {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
+};
+
+/*
+ * top 12 bits of crb internal address (hub, agent)
+ */
+static const unsigned crb_hub_agt[64] = {
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
+        0,
+        0,
+        0,
+        0,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
+        0,
+        QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
+        0,
+};
+
+/*  PCI Windowing for DDR regions.  */
+
+#define QLCNIC_PCIE_SEM_TIMEOUT 10000
+
+int
+qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
+{
+        int done = 0, timeout = 0;
+
+        while (!done) {
+                done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
+                if (done == 1)
+                        break;
+                if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
+                        dev_err(&adapter->pdev->dev,
+                                "Failed to acquire sem=%d lock; holdby=%d\n",
+                                sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
+                        return -EIO;
+                }
+                msleep(1);
+        }
+
+        if (id_reg)
+                QLCWR32(adapter, id_reg, adapter->portnum);
+
+        return 0;
+}
+
+void
+qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
+{
+        QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
+}
+
+static int
+qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
+                struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
+{
+        u32 i, producer, consumer;
+        struct qlcnic_cmd_buffer *pbuf;
+        struct cmd_desc_type0 *cmd_desc;
+        struct qlcnic_host_tx_ring *tx_ring;
+
+        i = 0;
+
+        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
+                return -EIO;
+
+        tx_ring = adapter->tx_ring;
+        __netif_tx_lock_bh(tx_ring->txq);
+
+        producer = tx_ring->producer;
+        consumer = tx_ring->sw_consumer;
+
+        if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
+                netif_tx_stop_queue(tx_ring->txq);
+                smp_mb();
+                if (qlcnic_tx_avail(tx_ring) > nr_desc) {
+                        if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
+                                netif_tx_wake_queue(tx_ring->txq);
+                } else {
+                        adapter->stats.xmit_off++;
+                        __netif_tx_unlock_bh(tx_ring->txq);
+                        return -EBUSY;
+                }
+        }
+
+        do {
+                cmd_desc = &cmd_desc_arr[i];
+
+                pbuf = &tx_ring->cmd_buf_arr[producer];
+                pbuf->skb = NULL;
+                pbuf->frag_count = 0;
+
+                memcpy(&tx_ring->desc_head[producer],
+                        &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
+
+                producer = get_next_index(producer, tx_ring->num_desc);
+                i++;
+
+        } while (i != nr_desc);
+
+        tx_ring->producer = producer;
+
+        qlcnic_update_cmd_producer(adapter, tx_ring);
+
+        __netif_tx_unlock_bh(tx_ring->txq);
+
+        return 0;
+}
+
+static int
+qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
+                                __le16 vlan_id, unsigned op)
+{
+        struct qlcnic_nic_req req;
+        struct qlcnic_mac_req *mac_req;
+        struct qlcnic_vlan_req *vlan_req;
+        u64 word;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+        req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
+
+        word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+
+        mac_req = (struct qlcnic_mac_req *)&req.words[0];
+        mac_req->op = op;
+        memcpy(mac_req->mac_addr, addr, 6);
+
+        vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
+        vlan_req->vlan_id = vlan_id;
+
+        return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+}
+
+static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
+{
+        struct list_head *head;
+        struct qlcnic_mac_list_s *cur;
+
+        /* look up if already exists */
+        list_for_each(head, &adapter->mac_list) {
+                cur = list_entry(head, struct qlcnic_mac_list_s, list);
+                if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
+                        return 0;
+        }
+
+        cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
+        if (cur == NULL) {
+                dev_err(&adapter->netdev->dev,
+                        "failed to add mac address filter\n");
+                return -ENOMEM;
+        }
+        memcpy(cur->mac_addr, addr, ETH_ALEN);
+
+        if (qlcnic_sre_macaddr_change(adapter,
+                                cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
+                kfree(cur);
+                return -EIO;
+        }
+
+        list_add_tail(&cur->list, &adapter->mac_list);
+        return 0;
+}
+
+void qlcnic_set_multi(struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct netdev_hw_addr *ha;
+        static const u8 bcast_addr[ETH_ALEN] = {
+                0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+        };
+        u32 mode = VPORT_MISS_MODE_DROP;
+
+        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
+                return;
+
+        qlcnic_nic_add_mac(adapter, adapter->mac_addr);
+        qlcnic_nic_add_mac(adapter, bcast_addr);
+
+        if (netdev->flags & IFF_PROMISC) {
+                if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
+                        mode = VPORT_MISS_MODE_ACCEPT_ALL;
+                goto send_fw_cmd;
+        }
+
+        if ((netdev->flags & IFF_ALLMULTI) ||
+            (netdev_mc_count(netdev) > adapter->max_mc_count)) {
+                mode = VPORT_MISS_MODE_ACCEPT_MULTI;
+                goto send_fw_cmd;
+        }
+
+        if (!netdev_mc_empty(netdev)) {
+                netdev_for_each_mc_addr(ha, netdev) {
+                        qlcnic_nic_add_mac(adapter, ha->addr);
+                }
+        }
+
+send_fw_cmd:
+        if (mode == VPORT_MISS_MODE_ACCEPT_ALL) {
+                qlcnic_alloc_lb_filters_mem(adapter);
+                adapter->mac_learn = 1;
+        } else {
+                adapter->mac_learn = 0;
+        }
+
+        qlcnic_nic_set_promisc(adapter, mode);
+}
+
+int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
+{
+        struct qlcnic_nic_req req;
+        u64 word;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
+                        ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+
+        req.words[0] = cpu_to_le64(mode);
+
+        return qlcnic_send_cmd_descs(adapter,
+                                (struct cmd_desc_type0 *)&req, 1);
+}
+
+void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_mac_list_s *cur;
+        struct list_head *head = &adapter->mac_list;
+
+        while (!list_empty(head)) {
+                cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
+                qlcnic_sre_macaddr_change(adapter,
+                                cur->mac_addr, 0, QLCNIC_MAC_DEL);
+                list_del(&cur->list);
+                kfree(cur);
+        }
+}
+
+void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_filter *tmp_fil;
+        struct hlist_node *tmp_hnode, *n;
+        struct hlist_head *head;
+        int i;
+
+        for (i = 0; i < adapter->fhash.fmax; i++) {
+                head = &(adapter->fhash.fhead[i]);
+
+                hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
+                {
+                        if (jiffies >
+                                (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
+                                qlcnic_sre_macaddr_change(adapter,
+                                        tmp_fil->faddr, tmp_fil->vlan_id,
+                                        tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
+                                        QLCNIC_MAC_DEL);
+                                spin_lock_bh(&adapter->mac_learn_lock);
+                                adapter->fhash.fnum--;
+                                hlist_del(&tmp_fil->fnode);
+                                spin_unlock_bh(&adapter->mac_learn_lock);
+                                kfree(tmp_fil);
+                        }
+                }
+        }
+}
+
+void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_filter *tmp_fil;
+        struct hlist_node *tmp_hnode, *n;
+        struct hlist_head *head;
+        int i;
+
+        for (i = 0; i < adapter->fhash.fmax; i++) {
+                head = &(adapter->fhash.fhead[i]);
+
+                hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
+                        qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
+                                tmp_fil->vlan_id, tmp_fil->vlan_id ?
+                                QLCNIC_MAC_VLAN_DEL :  QLCNIC_MAC_DEL);
+                        spin_lock_bh(&adapter->mac_learn_lock);
+                        adapter->fhash.fnum--;
+                        hlist_del(&tmp_fil->fnode);
+                        spin_unlock_bh(&adapter->mac_learn_lock);
+                        kfree(tmp_fil);
+                }
+        }
+}
+
+int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
+{
+        struct qlcnic_nic_req req;
+        int rv;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+        req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
+                ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
+
+        req.words[0] = cpu_to_le64(flag);
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
+                                flag ? "Set" : "Reset");
+        return rv;
+}
+
+int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
+{
+        if (qlcnic_set_fw_loopback(adapter, mode))
+                return -EIO;
+
+        if (qlcnic_nic_set_promisc(adapter, VPORT_MISS_MODE_ACCEPT_ALL)) {
+                qlcnic_set_fw_loopback(adapter, mode);
+                return -EIO;
+        }
+
+        msleep(1000);
+        return 0;
+}
+
+void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter)
+{
+        int mode = VPORT_MISS_MODE_DROP;
+        struct net_device *netdev = adapter->netdev;
+
+        qlcnic_set_fw_loopback(adapter, 0);
+
+        if (netdev->flags & IFF_PROMISC)
+                mode = VPORT_MISS_MODE_ACCEPT_ALL;
+        else if (netdev->flags & IFF_ALLMULTI)
+                mode = VPORT_MISS_MODE_ACCEPT_MULTI;
+
+        qlcnic_nic_set_promisc(adapter, mode);
+        msleep(1000);
+}
+
+/*
+ * Send the interrupt coalescing parameter set by ethtool to the card.
+ */
+int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_nic_req req;
+        int rv;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
+                ((u64) adapter->portnum << 16));
+
+        req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
+        req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
+                        ((u64) adapter->ahw->coal.rx_time_us) << 16);
+        req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
+                        ((u64) adapter->ahw->coal.type) << 32 |
+                        ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->netdev->dev,
+                        "Could not send interrupt coalescing parameters\n");
+        return rv;
+}
+
+int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
+{
+        struct qlcnic_nic_req req;
+        u64 word;
+        int rv;
+
+        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
+                return 0;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+
+        req.words[0] = cpu_to_le64(enable);
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->netdev->dev,
+                        "Could not send configure hw lro request\n");
+
+        return rv;
+}
+
+int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
+{
+        struct qlcnic_nic_req req;
+        u64 word;
+        int rv;
+
+        if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
+                return 0;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
+                ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+
+        req.words[0] = cpu_to_le64(enable);
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->netdev->dev,
+                        "Could not send configure bridge mode request\n");
+
+        adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
+
+        return rv;
+}
+
+
+#define RSS_HASHTYPE_IP_TCP     0x3
+
+int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
+{
+        struct qlcnic_nic_req req;
+        u64 word;
+        int i, rv;
+
+        static const u64 key[] = {
+                0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
+                0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
+                0x255b0ec26d5a56daULL
+        };
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+
+        /*
+         * RSS request:
+         * bits 3-0: hash_method
+         *      5-4: hash_type_ipv4
+         *      7-6: hash_type_ipv6
+         *        8: enable
+         *        9: use indirection table
+         *    47-10: reserved
+         *    63-48: indirection table mask
+         */
+        word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
+                ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
+                ((u64)(enable & 0x1) << 8) |
+                ((0x7ULL) << 48);
+        req.words[0] = cpu_to_le64(word);
+        for (i = 0; i < 5; i++)
+                req.words[i+1] = cpu_to_le64(key[i]);
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->netdev->dev, "could not configure RSS\n");
+
+        return rv;
+}
+
+int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
+{
+        struct qlcnic_nic_req req;
+        struct qlcnic_ipaddr *ipa;
+        u64 word;
+        int rv;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+
+        req.words[0] = cpu_to_le64(cmd);
+        ipa = (struct qlcnic_ipaddr *)&req.words[1];
+        ipa->ipv4 = ip;
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->netdev->dev,
+                                "could not notify %s IP 0x%x reuqest\n",
+                                (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
+
+        return rv;
+}
+
+int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
+{
+        struct qlcnic_nic_req req;
+        u64 word;
+        int rv;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+        req.words[0] = cpu_to_le64(enable | (enable << 8));
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->netdev->dev,
+                                "could not configure link notification\n");
+
+        return rv;
+}
+
+int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_nic_req req;
+        u64 word;
+        int rv;
+
+        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
+                return 0;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
+                ((u64)adapter->portnum << 16) |
+                ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
+
+        req.req_hdr = cpu_to_le64(word);
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv != 0)
+                dev_err(&adapter->netdev->dev,
+                                 "could not cleanup lro flows\n");
+
+        return rv;
+}
+
+/*
+ * qlcnic_change_mtu - Change the Maximum Transfer Unit
+ * @returns 0 on success, negative on failure
+ */
+
+int qlcnic_change_mtu(struct net_device *netdev, int mtu)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        int rc = 0;
+
+        if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
+                dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
+                        " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
+                return -EINVAL;
+        }
+
+        rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
+
+        if (!rc)
+                netdev->mtu = mtu;
+
+        return rc;
+}
+
+
+u32 qlcnic_fix_features(struct net_device *netdev, u32 features)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        if ((adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
+                u32 changed = features ^ netdev->features;
+                features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM);
+        }
+
+        if (!(features & NETIF_F_RXCSUM))
+                features &= ~NETIF_F_LRO;
+
+        return features;
+}
+
+
+int qlcnic_set_features(struct net_device *netdev, u32 features)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        u32 changed = netdev->features ^ features;
+        int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
+
+        if (!(changed & NETIF_F_LRO))
+                return 0;
+
+        netdev->features = features ^ NETIF_F_LRO;
+
+        if (qlcnic_config_hw_lro(adapter, hw_lro))
+                return -EIO;
+
+        if ((hw_lro == 0) && qlcnic_send_lro_cleanup(adapter))
+                return -EIO;
+
+        return 0;
+}
+
+/*
+ * Changes the CRB window to the specified window.
+ */
+ /* Returns < 0 if off is not valid,
+ *       1 if window access is needed. 'off' is set to offset from
+ *         CRB space in 128M pci map
+ *       0 if no window access is needed. 'off' is set to 2M addr
+ * In: 'off' is offset from base in 128M pci map
+ */
+static int
+qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
+                ulong off, void __iomem **addr)
+{
+        const struct crb_128M_2M_sub_block_map *m;
+
+        if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
+                return -EINVAL;
+
+        off -= QLCNIC_PCI_CRBSPACE;
+
+        /*
+         * Try direct map
+         */
+        m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
+
+        if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
+                *addr = adapter->ahw->pci_base0 + m->start_2M +
+                        (off - m->start_128M);
+                return 0;
+        }
+
+        /*
+         * Not in direct map, use crb window
+         */
+        *addr = adapter->ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
+        return 1;
+}
+
+/*
+ * In: 'off' is offset from CRB space in 128M pci map
+ * Out: 'off' is 2M pci map addr
+ * side effect: lock crb window
+ */
+static int
+qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
+{
+        u32 window;
+        void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
+
+        off -= QLCNIC_PCI_CRBSPACE;
+
+        window = CRB_HI(off);
+        if (window == 0) {
+                dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
+                return -EIO;
+        }
+
+        writel(window, addr);
+        if (readl(addr) != window) {
+                if (printk_ratelimit())
+                        dev_warn(&adapter->pdev->dev,
+                                "failed to set CRB window to %d off 0x%lx\n",
+                                window, off);
+                return -EIO;
+        }
+        return 0;
+}
+
+int
+qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
+{
+        unsigned long flags;
+        int rv;
+        void __iomem *addr = NULL;
+
+        rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
+
+        if (rv == 0) {
+                writel(data, addr);
+                return 0;
+        }
+
+        if (rv > 0) {
+                /* indirect access */
+                write_lock_irqsave(&adapter->ahw->crb_lock, flags);
+                crb_win_lock(adapter);
+                rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
+                if (!rv)
+                        writel(data, addr);
+                crb_win_unlock(adapter);
+                write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
+                return rv;
+        }
+
+        dev_err(&adapter->pdev->dev,
+                        "%s: invalid offset: 0x%016lx\n", __func__, off);
+        dump_stack();
+        return -EIO;
+}
+
+u32
+qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
+{
+        unsigned long flags;
+        int rv;
+        u32 data = -1;
+        void __iomem *addr = NULL;
+
+        rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
+
+        if (rv == 0)
+                return readl(addr);
+
+        if (rv > 0) {
+                /* indirect access */
+                write_lock_irqsave(&adapter->ahw->crb_lock, flags);
+                crb_win_lock(adapter);
+                if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
+                        data = readl(addr);
+                crb_win_unlock(adapter);
+                write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
+                return data;
+        }
+
+        dev_err(&adapter->pdev->dev,
+                        "%s: invalid offset: 0x%016lx\n", __func__, off);
+        dump_stack();
+        return -1;
+}
+
+
+void __iomem *
+qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
+{
+        void __iomem *addr = NULL;
+
+        WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
+
+        return addr;
+}
+
+
+static int
+qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
+                u64 addr, u32 *start)
+{
+        u32 window;
+
+        window = OCM_WIN_P3P(addr);
+
+        writel(window, adapter->ahw->ocm_win_crb);
+        /* read back to flush */
+        readl(adapter->ahw->ocm_win_crb);
+
+        *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
+        return 0;
+}
+
+static int
+qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
+                u64 *data, int op)
+{
+        void __iomem *addr;
+        int ret;
+        u32 start;
+
+        mutex_lock(&adapter->ahw->mem_lock);
+
+        ret = qlcnic_pci_set_window_2M(adapter, off, &start);
+        if (ret != 0)
+                goto unlock;
+
+        addr = adapter->ahw->pci_base0 + start;
+
+        if (op == 0)    /* read */
+                *data = readq(addr);
+        else            /* write */
+                writeq(*data, addr);
+
+unlock:
+        mutex_unlock(&adapter->ahw->mem_lock);
+
+        return ret;
+}
+
+void
+qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
+{
+        void __iomem *addr = adapter->ahw->pci_base0 +
+                QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
+
+        mutex_lock(&adapter->ahw->mem_lock);
+        *data = readq(addr);
+        mutex_unlock(&adapter->ahw->mem_lock);
+}
+
+void
+qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
+{
+        void __iomem *addr = adapter->ahw->pci_base0 +
+                QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
+
+        mutex_lock(&adapter->ahw->mem_lock);
+        writeq(data, addr);
+        mutex_unlock(&adapter->ahw->mem_lock);
+}
+
+#define MAX_CTL_CHECK   1000
+
+int
+qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
+                u64 off, u64 data)
+{
+        int i, j, ret;
+        u32 temp, off8;
+        void __iomem *mem_crb;
+
+        /* Only 64-bit aligned access */
+        if (off & 7)
+                return -EIO;
+
+        /* P3 onward, test agent base for MIU and SIU is same */
+        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
+                                QLCNIC_ADDR_QDR_NET_MAX)) {
+                mem_crb = qlcnic_get_ioaddr(adapter,
+                                QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
+                goto correct;
+        }
+
+        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
+                mem_crb = qlcnic_get_ioaddr(adapter,
+                                QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
+                goto correct;
+        }
+
+        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
+                return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
+
+        return -EIO;
+
+correct:
+        off8 = off & ~0xf;
+
+        mutex_lock(&adapter->ahw->mem_lock);
+
+        writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
+        writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
+
+        i = 0;
+        writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
+        writel((TA_CTL_START | TA_CTL_ENABLE),
+                        (mem_crb + TEST_AGT_CTRL));
+
+        for (j = 0; j < MAX_CTL_CHECK; j++) {
+                temp = readl(mem_crb + TEST_AGT_CTRL);
+                if ((temp & TA_CTL_BUSY) == 0)
+                        break;
+        }
+
+        if (j >= MAX_CTL_CHECK) {
+                ret = -EIO;
+                goto done;
+        }
+
+        i = (off & 0xf) ? 0 : 2;
+        writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
+                        mem_crb + MIU_TEST_AGT_WRDATA(i));
+        writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
+                        mem_crb + MIU_TEST_AGT_WRDATA(i+1));
+        i = (off & 0xf) ? 2 : 0;
+
+        writel(data & 0xffffffff,
+                        mem_crb + MIU_TEST_AGT_WRDATA(i));
+        writel((data >> 32) & 0xffffffff,
+                        mem_crb + MIU_TEST_AGT_WRDATA(i+1));
+
+        writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
+        writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
+                        (mem_crb + TEST_AGT_CTRL));
+
+        for (j = 0; j < MAX_CTL_CHECK; j++) {
+                temp = readl(mem_crb + TEST_AGT_CTRL);
+                if ((temp & TA_CTL_BUSY) == 0)
+                        break;
+        }
+
+        if (j >= MAX_CTL_CHECK) {
+                if (printk_ratelimit())
+                        dev_err(&adapter->pdev->dev,
+                                        "failed to write through agent\n");
+                ret = -EIO;
+        } else
+                ret = 0;
+
+done:
+        mutex_unlock(&adapter->ahw->mem_lock);
+
+        return ret;
+}
+
+int
+qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
+                u64 off, u64 *data)
+{
+        int j, ret;
+        u32 temp, off8;
+        u64 val;
+        void __iomem *mem_crb;
+
+        /* Only 64-bit aligned access */
+        if (off & 7)
+                return -EIO;
+
+        /* P3 onward, test agent base for MIU and SIU is same */
+        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
+                                QLCNIC_ADDR_QDR_NET_MAX)) {
+                mem_crb = qlcnic_get_ioaddr(adapter,
+                                QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
+                goto correct;
+        }
+
+        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
+                mem_crb = qlcnic_get_ioaddr(adapter,
+                                QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
+                goto correct;
+        }
+
+        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
+                return qlcnic_pci_mem_access_direct(adapter,
+                                off, data, 0);
+        }
+
+        return -EIO;
+
+correct:
+        off8 = off & ~0xf;
+
+        mutex_lock(&adapter->ahw->mem_lock);
+
+        writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
+        writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
+        writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
+        writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
+
+        for (j = 0; j < MAX_CTL_CHECK; j++) {
+                temp = readl(mem_crb + TEST_AGT_CTRL);
+                if ((temp & TA_CTL_BUSY) == 0)
+                        break;
+        }
+
+        if (j >= MAX_CTL_CHECK) {
+                if (printk_ratelimit())
+                        dev_err(&adapter->pdev->dev,
+                                        "failed to read through agent\n");
+                ret = -EIO;
+        } else {
+                off8 = MIU_TEST_AGT_RDDATA_LO;
+                if (off & 0xf)
+                        off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
+
+                temp = readl(mem_crb + off8 + 4);
+                val = (u64)temp << 32;
+                val |= readl(mem_crb + off8);
+                *data = val;
+                ret = 0;
+        }
+
+        mutex_unlock(&adapter->ahw->mem_lock);
+
+        return ret;
+}
+
+int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
+{
+        int offset, board_type, magic;
+        struct pci_dev *pdev = adapter->pdev;
+
+        offset = QLCNIC_FW_MAGIC_OFFSET;
+        if (qlcnic_rom_fast_read(adapter, offset, &magic))
+                return -EIO;
+
+        if (magic != QLCNIC_BDINFO_MAGIC) {
+                dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
+                        magic);
+                return -EIO;
+        }
+
+        offset = QLCNIC_BRDTYPE_OFFSET;
+        if (qlcnic_rom_fast_read(adapter, offset, &board_type))
+                return -EIO;
+
+        adapter->ahw->board_type = board_type;
+
+        if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
+                u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
+                if ((gpio & 0x8000) == 0)
+                        board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
+        }
+
+        switch (board_type) {
+        case QLCNIC_BRDTYPE_P3P_HMEZ:
+        case QLCNIC_BRDTYPE_P3P_XG_LOM:
+        case QLCNIC_BRDTYPE_P3P_10G_CX4:
+        case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
+        case QLCNIC_BRDTYPE_P3P_IMEZ:
+        case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
+        case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
+        case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
+        case QLCNIC_BRDTYPE_P3P_10G_XFP:
+        case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
+                adapter->ahw->port_type = QLCNIC_XGBE;
+                break;
+        case QLCNIC_BRDTYPE_P3P_REF_QG:
+        case QLCNIC_BRDTYPE_P3P_4_GB:
+        case QLCNIC_BRDTYPE_P3P_4_GB_MM:
+                adapter->ahw->port_type = QLCNIC_GBE;
+                break;
+        case QLCNIC_BRDTYPE_P3P_10G_TP:
+                adapter->ahw->port_type = (adapter->portnum < 2) ?
+                        QLCNIC_XGBE : QLCNIC_GBE;
+                break;
+        default:
+                dev_err(&pdev->dev, "unknown board type %x\n", board_type);
+                adapter->ahw->port_type = QLCNIC_XGBE;
+                break;
+        }
+
+        return 0;
+}
+
+int
+qlcnic_wol_supported(struct qlcnic_adapter *adapter)
+{
+        u32 wol_cfg;
+
+        wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
+        if (wol_cfg & (1UL << adapter->portnum)) {
+                wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
+                if (wol_cfg & (1 << adapter->portnum))
+                        return 1;
+        }
+
+        return 0;
+}
+
+int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
+{
+        struct qlcnic_nic_req   req;
+        int rv;
+        u64 word;
+
+        memset(&req, 0, sizeof(struct qlcnic_nic_req));
+        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
+
+        word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
+        req.req_hdr = cpu_to_le64(word);
+
+        req.words[0] = cpu_to_le64((u64)rate << 32);
+        req.words[1] = cpu_to_le64(state);
+
+        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
+        if (rv)
+                dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
+
+        return rv;
+}
+
+/* FW dump related functions */
+static u32
+qlcnic_dump_crb(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
+                u32 *buffer)
+{
+        int i;
+        u32 addr, data;
+        struct __crb *crb = &entry->region.crb;
+        void __iomem *base = adapter->ahw->pci_base0;
+
+        addr = crb->addr;
+
+        for (i = 0; i < crb->no_ops; i++) {
+                QLCNIC_RD_DUMP_REG(addr, base, &data);
+                *buffer++ = cpu_to_le32(addr);
+                *buffer++ = cpu_to_le32(data);
+                addr += crb->stride;
+        }
+        return crb->no_ops * 2 * sizeof(u32);
+}
+
+static u32
+qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
+        struct qlcnic_dump_entry *entry, u32 *buffer)
+{
+        int i, k, timeout = 0;
+        void __iomem *base = adapter->ahw->pci_base0;
+        u32 addr, data;
+        u8 opcode, no_ops;
+        struct __ctrl *ctr = &entry->region.ctrl;
+        struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;
+
+        addr = ctr->addr;
+        no_ops = ctr->no_ops;
+
+        for (i = 0; i < no_ops; i++) {
+                k = 0;
+                opcode = 0;
+                for (k = 0; k < 8; k++) {
+                        if (!(ctr->opcode & (1 << k)))
+                                continue;
+                        switch (1 << k) {
+                        case QLCNIC_DUMP_WCRB:
+                                QLCNIC_WR_DUMP_REG(addr, base, ctr->val1);
+                                break;
+                        case QLCNIC_DUMP_RWCRB:
+                                QLCNIC_RD_DUMP_REG(addr, base, &data);
+                                QLCNIC_WR_DUMP_REG(addr, base, data);
+                                break;
+                        case QLCNIC_DUMP_ANDCRB:
+                                QLCNIC_RD_DUMP_REG(addr, base, &data);
+                                QLCNIC_WR_DUMP_REG(addr, base,
+                                        (data & ctr->val2));
+                                break;
+                        case QLCNIC_DUMP_ORCRB:
+                                QLCNIC_RD_DUMP_REG(addr, base, &data);
+                                QLCNIC_WR_DUMP_REG(addr, base,
+                                        (data | ctr->val3));
+                                break;
+                        case QLCNIC_DUMP_POLLCRB:
+                                while (timeout <= ctr->timeout) {
+                                        QLCNIC_RD_DUMP_REG(addr, base, &data);
+                                        if ((data & ctr->val2) == ctr->val1)
+                                                break;
+                                        msleep(1);
+                                        timeout++;
+                                }
+                                if (timeout > ctr->timeout) {
+                                        dev_info(&adapter->pdev->dev,
+                                        "Timed out, aborting poll CRB\n");
+                                        return -EINVAL;
+                                }
+                                break;
+                        case QLCNIC_DUMP_RD_SAVE:
+                                if (ctr->index_a)
+                                        addr = t_hdr->saved_state[ctr->index_a];
+                                QLCNIC_RD_DUMP_REG(addr, base, &data);
+                                t_hdr->saved_state[ctr->index_v] = data;
+                                break;
+                        case QLCNIC_DUMP_WRT_SAVED:
+                                if (ctr->index_v)
+                                        data = t_hdr->saved_state[ctr->index_v];
+                                else
+                                        data = ctr->val1;
+                                if (ctr->index_a)
+                                        addr = t_hdr->saved_state[ctr->index_a];
+                                QLCNIC_WR_DUMP_REG(addr, base, data);
+                                break;
+                        case QLCNIC_DUMP_MOD_SAVE_ST:
+                                data = t_hdr->saved_state[ctr->index_v];
+                                data <<= ctr->shl_val;
+                                data >>= ctr->shr_val;
+                                if (ctr->val2)
+                                        data &= ctr->val2;
+                                data |= ctr->val3;
+                                data += ctr->val1;
+                                t_hdr->saved_state[ctr->index_v] = data;
+                                break;
+                        default:
+                                dev_info(&adapter->pdev->dev,
+                                        "Unknown opcode\n");
+                                break;
+                        }
+                }
+                addr += ctr->stride;
+        }
+        return 0;
+}
+
+static u32
+qlcnic_dump_mux(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
+        u32 *buffer)
+{
+        int loop;
+        u32 val, data = 0;
+        struct __mux *mux = &entry->region.mux;
+        void __iomem *base = adapter->ahw->pci_base0;
+
+        val = mux->val;
+        for (loop = 0; loop < mux->no_ops; loop++) {
+                QLCNIC_WR_DUMP_REG(mux->addr, base, val);
+                QLCNIC_RD_DUMP_REG(mux->read_addr, base, &data);
+                *buffer++ = cpu_to_le32(val);
+                *buffer++ = cpu_to_le32(data);
+                val += mux->val_stride;
+        }
+        return 2 * mux->no_ops * sizeof(u32);
+}
+
+static u32
+qlcnic_dump_que(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
+        u32 *buffer)
+{
+        int i, loop;
+        u32 cnt, addr, data, que_id = 0;
+        void __iomem *base = adapter->ahw->pci_base0;
+        struct __queue *que = &entry->region.que;
+
+        addr = que->read_addr;
+        cnt = que->read_addr_cnt;
+
+        for (loop = 0; loop < que->no_ops; loop++) {
+                QLCNIC_WR_DUMP_REG(que->sel_addr, base, que_id);
+                addr = que->read_addr;
+                for (i = 0; i < cnt; i++) {
+                        QLCNIC_RD_DUMP_REG(addr, base, &data);
+                        *buffer++ = cpu_to_le32(data);
+                        addr += que->read_addr_stride;
+                }
+                que_id += que->stride;
+        }
+        return que->no_ops * cnt * sizeof(u32);
+}
+
+static u32
+qlcnic_dump_ocm(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
+        u32 *buffer)
+{
+        int i;
+        u32 data;
+        void __iomem *addr;
+        struct __ocm *ocm = &entry->region.ocm;
+
+        addr = adapter->ahw->pci_base0 + ocm->read_addr;
+        for (i = 0; i < ocm->no_ops; i++) {
+                data = readl(addr);
+                *buffer++ = cpu_to_le32(data);
+                addr += ocm->read_addr_stride;
+        }
+        return ocm->no_ops * sizeof(u32);
+}
+
+static u32
+qlcnic_read_rom(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
+        u32 *buffer)
+{
+        int i, count = 0;
+        u32 fl_addr, size, val, lck_val, addr;
+        struct __mem *rom = &entry->region.mem;
+        void __iomem *base = adapter->ahw->pci_base0;
+
+        fl_addr = rom->addr;
+        size = rom->size/4;
+lock_try:
+        lck_val = readl(base + QLCNIC_FLASH_SEM2_LK);
+        if (!lck_val && count < MAX_CTL_CHECK) {
+                msleep(10);
+                count++;
+                goto lock_try;
+        }
+        writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
+        for (i = 0; i < size; i++) {
+                addr = fl_addr & 0xFFFF0000;
+                QLCNIC_WR_DUMP_REG(FLASH_ROM_WINDOW, base, addr);
+                addr = LSW(fl_addr) + FLASH_ROM_DATA;
+                QLCNIC_RD_DUMP_REG(addr, base, &val);
+                fl_addr += 4;
+                *buffer++ = cpu_to_le32(val);
+        }
+        readl(base + QLCNIC_FLASH_SEM2_ULK);
+        return rom->size;
+}
+
+static u32
+qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
+        struct qlcnic_dump_entry *entry, u32 *buffer)
+{
+        int i;
+        u32 cnt, val, data, addr;
+        void __iomem *base = adapter->ahw->pci_base0;
+        struct __cache *l1 = &entry->region.cache;
+
+        val = l1->init_tag_val;
+
+        for (i = 0; i < l1->no_ops; i++) {
+                QLCNIC_WR_DUMP_REG(l1->addr, base, val);
+                QLCNIC_WR_DUMP_REG(l1->ctrl_addr, base, LSW(l1->ctrl_val));
+                addr = l1->read_addr;
+                cnt = l1->read_addr_num;
+                while (cnt) {
+                        QLCNIC_RD_DUMP_REG(addr, base, &data);
+                        *buffer++ = cpu_to_le32(data);
+                        addr += l1->read_addr_stride;
+                        cnt--;
+                }
+                val += l1->stride;
+        }
+        return l1->no_ops * l1->read_addr_num * sizeof(u32);
+}
+
+static u32
+qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
+        struct qlcnic_dump_entry *entry, u32 *buffer)
+{
+        int i;
+        u32 cnt, val, data, addr;
+        u8 poll_mask, poll_to, time_out = 0;
+        void __iomem *base = adapter->ahw->pci_base0;
+        struct __cache *l2 = &entry->region.cache;
+
+        val = l2->init_tag_val;
+        poll_mask = LSB(MSW(l2->ctrl_val));
+        poll_to = MSB(MSW(l2->ctrl_val));
+
+        for (i = 0; i < l2->no_ops; i++) {
+                QLCNIC_WR_DUMP_REG(l2->addr, base, val);
+                if (LSW(l2->ctrl_val))
+                        QLCNIC_WR_DUMP_REG(l2->ctrl_addr, base,
+                                LSW(l2->ctrl_val));
+                if (!poll_mask)
+                        goto skip_poll;
+                do {
+                        QLCNIC_RD_DUMP_REG(l2->ctrl_addr, base, &data);
+                        if (!(data & poll_mask))
+                                break;
+                        msleep(1);
+                        time_out++;
+                } while (time_out <= poll_to);
+
+                if (time_out > poll_to) {
+                        dev_err(&adapter->pdev->dev,
+                                "Timeout exceeded in %s, aborting dump\n",
+                                __func__);
+                        return -EINVAL;
+                }
+skip_poll:
+                addr = l2->read_addr;
+                cnt = l2->read_addr_num;
+                while (cnt) {
+                        QLCNIC_RD_DUMP_REG(addr, base, &data);
+                        *buffer++ = cpu_to_le32(data);
+                        addr += l2->read_addr_stride;
+                        cnt--;
+                }
+                val += l2->stride;
+        }
+        return l2->no_ops * l2->read_addr_num * sizeof(u32);
+}
+
+static u32
+qlcnic_read_memory(struct qlcnic_adapter *adapter,
+        struct qlcnic_dump_entry *entry, u32 *buffer)
+{
+        u32 addr, data, test, ret = 0;
+        int i, reg_read;
+        struct __mem *mem = &entry->region.mem;
+        void __iomem *base = adapter->ahw->pci_base0;
+
+        reg_read = mem->size;
+        addr = mem->addr;
+        /* check for data size of multiple of 16 and 16 byte alignment */
+        if ((addr & 0xf) || (reg_read%16)) {
+                dev_info(&adapter->pdev->dev,
+                        "Unaligned memory addr:0x%x size:0x%x\n",
+                        addr, reg_read);
+                return -EINVAL;
+        }
+
+        mutex_lock(&adapter->ahw->mem_lock);
+
+        while (reg_read != 0) {
+                QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_LO, base, addr);
+                QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_HI, base, 0);
+                QLCNIC_WR_DUMP_REG(MIU_TEST_CTR, base,
+                        TA_CTL_ENABLE | TA_CTL_START);
+
+                for (i = 0; i < MAX_CTL_CHECK; i++) {
+                        QLCNIC_RD_DUMP_REG(MIU_TEST_CTR, base, &test);
+                        if (!(test & TA_CTL_BUSY))
+                                break;
+                }
+                if (i == MAX_CTL_CHECK) {
+                        if (printk_ratelimit()) {
+                                dev_err(&adapter->pdev->dev,
+                                        "failed to read through agent\n");
+                                ret = -EINVAL;
+                                goto out;
+                        }
+                }
+                for (i = 0; i < 4; i++) {
+                        QLCNIC_RD_DUMP_REG(MIU_TEST_READ_DATA[i], base, &data);
+                        *buffer++ = cpu_to_le32(data);
+                }
+                addr += 16;
+                reg_read -= 16;
+                ret += 16;
+        }
+out:
+        mutex_unlock(&adapter->ahw->mem_lock);
+        return mem->size;
+}
+
+static u32
+qlcnic_dump_nop(struct qlcnic_adapter *adapter,
+        struct qlcnic_dump_entry *entry, u32 *buffer)
+{
+        entry->hdr.flags |= QLCNIC_DUMP_SKIP;
+        return 0;
+}
+
+struct qlcnic_dump_operations fw_dump_ops[] = {
+        { QLCNIC_DUMP_NOP, qlcnic_dump_nop },
+        { QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
+        { QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
+        { QLCNIC_DUMP_QUEUE, qlcnic_dump_que },
+        { QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom },
+        { QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm },
+        { QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl },
+        { QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache },
+        { QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache },
+        { QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache },
+        { QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache },
+        { QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache },
+        { QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache },
+        { QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache },
+        { QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache },
+        { QLCNIC_DUMP_READ_ROM, qlcnic_read_rom },
+        { QLCNIC_DUMP_READ_MEM, qlcnic_read_memory },
+        { QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl },
+        { QLCNIC_DUMP_TLHDR, qlcnic_dump_nop },
+        { QLCNIC_DUMP_RDEND, qlcnic_dump_nop },
+};
+
+/* Walk the template and collect dump for each entry in the dump template */
+static int
+qlcnic_valid_dump_entry(struct device *dev, struct qlcnic_dump_entry *entry,
+        u32 size)
+{
+        int ret = 1;
+        if (size != entry->hdr.cap_size) {
+                dev_info(dev,
+                "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
+                entry->hdr.type, entry->hdr.mask, size, entry->hdr.cap_size);
+                dev_info(dev, "Aborting further dump capture\n");
+                ret = 0;
+        }
+        return ret;
+}
+
+int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
+{
+        u32 *buffer;
+        char mesg[64];
+        char *msg[] = {mesg, NULL};
+        int i, k, ops_cnt, ops_index, dump_size = 0;
+        u32 entry_offset, dump, no_entries, buf_offset = 0;
+        struct qlcnic_dump_entry *entry;
+        struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
+        struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;
+
+        if (fw_dump->clr) {
+                dev_info(&adapter->pdev->dev,
+                        "Previous dump not cleared, not capturing dump\n");
+                return -EIO;
+        }
+        /* Calculate the size for dump data area only */
+        for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
+                if (i & tmpl_hdr->drv_cap_mask)
+                        dump_size += tmpl_hdr->cap_sizes[k];
+        if (!dump_size)
+                return -EIO;
+
+        fw_dump->data = vzalloc(dump_size);
+        if (!fw_dump->data) {
+                dev_info(&adapter->pdev->dev,
+                        "Unable to allocate (%d KB) for fw dump\n",
+                        dump_size/1024);
+                return -ENOMEM;
+        }
+        buffer = fw_dump->data;
+        fw_dump->size = dump_size;
+        no_entries = tmpl_hdr->num_entries;
+        ops_cnt = ARRAY_SIZE(fw_dump_ops);
+        entry_offset = tmpl_hdr->offset;
+        tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
+        tmpl_hdr->sys_info[1] = adapter->fw_version;
+
+        for (i = 0; i < no_entries; i++) {
+                entry = (void *)tmpl_hdr + entry_offset;
+                if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
+                        entry->hdr.flags |= QLCNIC_DUMP_SKIP;
+                        entry_offset += entry->hdr.offset;
+                        continue;
+                }
+                /* Find the handler for this entry */
+                ops_index = 0;
+                while (ops_index < ops_cnt) {
+                        if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
+                                break;
+                        ops_index++;
+                }
+                if (ops_index == ops_cnt) {
+                        dev_info(&adapter->pdev->dev,
+                                "Invalid entry type %d, exiting dump\n",
+                                entry->hdr.type);
+                        goto error;
+                }
+                /* Collect dump for this entry */
+                dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
+                if (dump && !qlcnic_valid_dump_entry(&adapter->pdev->dev, entry,
+                        dump))
+                        entry->hdr.flags |= QLCNIC_DUMP_SKIP;
+                buf_offset += entry->hdr.cap_size;
+                entry_offset += entry->hdr.offset;
+                buffer = fw_dump->data + buf_offset;
+        }
+        if (dump_size != buf_offset) {
+                dev_info(&adapter->pdev->dev,
+                        "Captured(%d) and expected size(%d) do not match\n",
+                        buf_offset, dump_size);
+                goto error;
+        } else {
+                fw_dump->clr = 1;
+                snprintf(mesg, sizeof(mesg), "FW dump for device: %d\n",
+                        adapter->pdev->devfn);
+                dev_info(&adapter->pdev->dev, "Dump data, %d bytes captured\n",
+                        fw_dump->size);
+                /* Send a udev event to notify availability of FW dump */
+                kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
+                return 0;
+        }
+error:
+        vfree(fw_dump->data);
+        return -EINVAL;
+}
diff --git a/drivers/net/qlcnic/qlcnic_init.c b/drivers/net/qlcnic/qlcnic_init.c
new file mode 100644
index 00000000000..ee8a3982395
--- /dev/null
+++ b/drivers/net/qlcnic/qlcnic_init.c
@@ -0,0 +1,1897 @@
+/*
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
+ *
+ * See LICENSE.qlcnic for copyright and licensing details.
+ */
+
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/if_vlan.h>
+#include "qlcnic.h"
+
+struct crb_addr_pair {
+        u32 addr;
+        u32 data;
+};
+
+#define QLCNIC_MAX_CRB_XFORM 60
+static unsigned int crb_addr_xform[QLCNIC_MAX_CRB_XFORM];
+
+#define crb_addr_transform(name) \
+        (crb_addr_xform[QLCNIC_HW_PX_MAP_CRB_##name] = \
+        QLCNIC_HW_CRB_HUB_AGT_ADR_##name << 20)
+
+#define QLCNIC_ADDR_ERROR (0xffffffff)
+
+static void
+qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_rds_ring *rds_ring);
+
+static int
+qlcnic_check_fw_hearbeat(struct qlcnic_adapter *adapter);
+
+static void crb_addr_transform_setup(void)
+{
+        crb_addr_transform(XDMA);
+        crb_addr_transform(TIMR);
+        crb_addr_transform(SRE);
+        crb_addr_transform(SQN3);
+        crb_addr_transform(SQN2);
+        crb_addr_transform(SQN1);
+        crb_addr_transform(SQN0);
+        crb_addr_transform(SQS3);
+        crb_addr_transform(SQS2);
+        crb_addr_transform(SQS1);
+        crb_addr_transform(SQS0);
+        crb_addr_transform(RPMX7);
+        crb_addr_transform(RPMX6);
+        crb_addr_transform(RPMX5);
+        crb_addr_transform(RPMX4);
+        crb_addr_transform(RPMX3);
+        crb_addr_transform(RPMX2);
+        crb_addr_transform(RPMX1);
+        crb_addr_transform(RPMX0);
+        crb_addr_transform(ROMUSB);
+        crb_addr_transform(SN);
+        crb_addr_transform(QMN);
+        crb_addr_transform(QMS);
+        crb_addr_transform(PGNI);
+        crb_addr_transform(PGND);
+        crb_addr_transform(PGN3);
+        crb_addr_transform(PGN2);
+        crb_addr_transform(PGN1);
+        crb_addr_transform(PGN0);
+        crb_addr_transform(PGSI);
+        crb_addr_transform(PGSD);
+        crb_addr_transform(PGS3);
+        crb_addr_transform(PGS2);
+        crb_addr_transform(PGS1);
+        crb_addr_transform(PGS0);
+        crb_addr_transform(PS);
+        crb_addr_transform(PH);
+        crb_addr_transform(NIU);
+        crb_addr_transform(I2Q);
+        crb_addr_transform(EG);
+        crb_addr_transform(MN);
+        crb_addr_transform(MS);
+        crb_addr_transform(CAS2);
+        crb_addr_transform(CAS1);
+        crb_addr_transform(CAS0);
+        crb_addr_transform(CAM);
+        crb_addr_transform(C2C1);
+        crb_addr_transform(C2C0);
+        crb_addr_transform(SMB);
+        crb_addr_transform(OCM0);
+        crb_addr_transform(I2C0);
+}
+
+void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_recv_context *recv_ctx;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct qlcnic_rx_buffer *rx_buf;
+        int i, ring;
+
+        recv_ctx = adapter->recv_ctx;
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &recv_ctx->rds_rings[ring];
+                for (i = 0; i < rds_ring->num_desc; ++i) {
+                        rx_buf = &(rds_ring->rx_buf_arr[i]);
+                        if (rx_buf->skb == NULL)
+                                continue;
+
+                        pci_unmap_single(adapter->pdev,
+                                        rx_buf->dma,
+                                        rds_ring->dma_size,
+                                        PCI_DMA_FROMDEVICE);
+
+                        dev_kfree_skb_any(rx_buf->skb);
+                }
+        }
+}
+
+void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_recv_context *recv_ctx;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct qlcnic_rx_buffer *rx_buf;
+        int i, ring;
+
+        recv_ctx = adapter->recv_ctx;
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &recv_ctx->rds_rings[ring];
+
+                INIT_LIST_HEAD(&rds_ring->free_list);
+
+                rx_buf = rds_ring->rx_buf_arr;
+                for (i = 0; i < rds_ring->num_desc; i++) {
+                        list_add_tail(&rx_buf->list,
+                                        &rds_ring->free_list);
+                        rx_buf++;
+                }
+        }
+}
+
+void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_cmd_buffer *cmd_buf;
+        struct qlcnic_skb_frag *buffrag;
+        int i, j;
+        struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
+
+        cmd_buf = tx_ring->cmd_buf_arr;
+        for (i = 0; i < tx_ring->num_desc; i++) {
+                buffrag = cmd_buf->frag_array;
+                if (buffrag->dma) {
+                        pci_unmap_single(adapter->pdev, buffrag->dma,
+                                         buffrag->length, PCI_DMA_TODEVICE);
+                        buffrag->dma = 0ULL;
+                }
+                for (j = 0; j < cmd_buf->frag_count; j++) {
+                        buffrag++;
+                        if (buffrag->dma) {
+                                pci_unmap_page(adapter->pdev, buffrag->dma,
+                                               buffrag->length,
+                                               PCI_DMA_TODEVICE);
+                                buffrag->dma = 0ULL;
+                        }
+                }
+                if (cmd_buf->skb) {
+                        dev_kfree_skb_any(cmd_buf->skb);
+                        cmd_buf->skb = NULL;
+                }
+                cmd_buf++;
+        }
+}
+
+void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_recv_context *recv_ctx;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct qlcnic_host_tx_ring *tx_ring;
+        int ring;
+
+        recv_ctx = adapter->recv_ctx;
+
+        if (recv_ctx->rds_rings == NULL)
+                goto skip_rds;
+
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &recv_ctx->rds_rings[ring];
+                vfree(rds_ring->rx_buf_arr);
+                rds_ring->rx_buf_arr = NULL;
+        }
+        kfree(recv_ctx->rds_rings);
+
+skip_rds:
+        if (adapter->tx_ring == NULL)
+                return;
+
+        tx_ring = adapter->tx_ring;
+        vfree(tx_ring->cmd_buf_arr);
+        tx_ring->cmd_buf_arr = NULL;
+        kfree(adapter->tx_ring);
+        adapter->tx_ring = NULL;
+}
+
+int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_recv_context *recv_ctx;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_host_tx_ring *tx_ring;
+        struct qlcnic_rx_buffer *rx_buf;
+        int ring, i, size;
+
+        struct qlcnic_cmd_buffer *cmd_buf_arr;
+        struct net_device *netdev = adapter->netdev;
+
+        size = sizeof(struct qlcnic_host_tx_ring);
+        tx_ring = kzalloc(size, GFP_KERNEL);
+        if (tx_ring == NULL) {
+                dev_err(&netdev->dev, "failed to allocate tx ring struct\n");
+                return -ENOMEM;
+        }
+        adapter->tx_ring = tx_ring;
+
+        tx_ring->num_desc = adapter->num_txd;
+        tx_ring->txq = netdev_get_tx_queue(netdev, 0);
+
+        cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
+        if (cmd_buf_arr == NULL) {
+                dev_err(&netdev->dev, "failed to allocate cmd buffer ring\n");
+                goto err_out;
+        }
+        tx_ring->cmd_buf_arr = cmd_buf_arr;
+
+        recv_ctx = adapter->recv_ctx;
+
+        size = adapter->max_rds_rings * sizeof(struct qlcnic_host_rds_ring);
+        rds_ring = kzalloc(size, GFP_KERNEL);
+        if (rds_ring == NULL) {
+                dev_err(&netdev->dev, "failed to allocate rds ring struct\n");
+                goto err_out;
+        }
+        recv_ctx->rds_rings = rds_ring;
+
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &recv_ctx->rds_rings[ring];
+                switch (ring) {
+                case RCV_RING_NORMAL:
+                        rds_ring->num_desc = adapter->num_rxd;
+                        rds_ring->dma_size = QLCNIC_P3P_RX_BUF_MAX_LEN;
+                        rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
+                        break;
+
+                case RCV_RING_JUMBO:
+                        rds_ring->num_desc = adapter->num_jumbo_rxd;
+                        rds_ring->dma_size =
+                                QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN;
+
+                        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_HW_LRO)
+                                rds_ring->dma_size += QLCNIC_LRO_BUFFER_EXTRA;
+
+                        rds_ring->skb_size =
+                                rds_ring->dma_size + NET_IP_ALIGN;
+                        break;
+                }
+                rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
+                if (rds_ring->rx_buf_arr == NULL) {
+                        dev_err(&netdev->dev, "Failed to allocate "
+                                "rx buffer ring %d\n", ring);
+                        goto err_out;
+                }
+                INIT_LIST_HEAD(&rds_ring->free_list);
+                /*
+                 * Now go through all of them, set reference handles
+                 * and put them in the queues.
+                 */
+                rx_buf = rds_ring->rx_buf_arr;
+                for (i = 0; i < rds_ring->num_desc; i++) {
+                        list_add_tail(&rx_buf->list,
+                                        &rds_ring->free_list);
+                        rx_buf->ref_handle = i;
+                        rx_buf++;
+                }
+                spin_lock_init(&rds_ring->lock);
+        }
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+                sds_ring->irq = adapter->msix_entries[ring].vector;
+                sds_ring->adapter = adapter;
+                sds_ring->num_desc = adapter->num_rxd;
+
+                for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
+                        INIT_LIST_HEAD(&sds_ring->free_list[i]);
+        }
+
+        return 0;
+
+err_out:
+        qlcnic_free_sw_resources(adapter);
+        return -ENOMEM;
+}
+
+/*
+ * Utility to translate from internal Phantom CRB address
+ * to external PCI CRB address.
+ */
+static u32 qlcnic_decode_crb_addr(u32 addr)
+{
+        int i;
+        u32 base_addr, offset, pci_base;
+
+        crb_addr_transform_setup();
+
+        pci_base = QLCNIC_ADDR_ERROR;
+        base_addr = addr & 0xfff00000;
+        offset = addr & 0x000fffff;
+
+        for (i = 0; i < QLCNIC_MAX_CRB_XFORM; i++) {
+                if (crb_addr_xform[i] == base_addr) {
+                        pci_base = i << 20;
+                        break;
+                }
+        }
+        if (pci_base == QLCNIC_ADDR_ERROR)
+                return pci_base;
+        else
+                return pci_base + offset;
+}
+
+#define QLCNIC_MAX_ROM_WAIT_USEC        100
+
+static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter)
+{
+        long timeout = 0;
+        long done = 0;
+
+        cond_resched();
+
+        while (done == 0) {
+                done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS);
+                done &= 2;
+                if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) {
+                        dev_err(&adapter->pdev->dev,
+                                "Timeout reached  waiting for rom done");
+                        return -EIO;
+                }
+                udelay(1);
+        }
+        return 0;
+}
+
+static int do_rom_fast_read(struct qlcnic_adapter *adapter,
+                            u32 addr, u32 *valp)
+{
+        QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr);
+        QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
+        QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3);
+        QLCWR32(adapter, QLCNIC_ROMUSB_ROM_INSTR_OPCODE, 0xb);
+        if (qlcnic_wait_rom_done(adapter)) {
+                dev_err(&adapter->pdev->dev, "Error waiting for rom done\n");
+                return -EIO;
+        }
+        /* reset abyte_cnt and dummy_byte_cnt */
+        QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 0);
+        udelay(10);
+        QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
+
+        *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA);
+        return 0;
+}
+
+static int do_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
+                                  u8 *bytes, size_t size)
+{
+        int addridx;
+        int ret = 0;
+
+        for (addridx = addr; addridx < (addr + size); addridx += 4) {
+                int v;
+                ret = do_rom_fast_read(adapter, addridx, &v);
+                if (ret != 0)
+                        break;
+                *(__le32 *)bytes = cpu_to_le32(v);
+                bytes += 4;
+        }
+
+        return ret;
+}
+
+int
+qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
+                                u8 *bytes, size_t size)
+{
+        int ret;
+
+        ret = qlcnic_rom_lock(adapter);
+        if (ret < 0)
+                return ret;
+
+        ret = do_rom_fast_read_words(adapter, addr, bytes, size);
+
+        qlcnic_rom_unlock(adapter);
+        return ret;
+}
+
+int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp)
+{
+        int ret;
+
+        if (qlcnic_rom_lock(adapter) != 0)
+                return -EIO;
+
+        ret = do_rom_fast_read(adapter, addr, valp);
+        qlcnic_rom_unlock(adapter);
+        return ret;
+}
+
+int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
+{
+        int addr, val;
+        int i, n, init_delay;
+        struct crb_addr_pair *buf;
+        unsigned offset;
+        u32 off;
+        struct pci_dev *pdev = adapter->pdev;
+
+        QLCWR32(adapter, CRB_CMDPEG_STATE, 0);
+        QLCWR32(adapter, CRB_RCVPEG_STATE, 0);
+
+        qlcnic_rom_lock(adapter);
+        QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xfeffffff);
+        qlcnic_rom_unlock(adapter);
+
+        /* Init HW CRB block */
+        if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
+                        qlcnic_rom_fast_read(adapter, 4, &n) != 0) {
+                dev_err(&pdev->dev, "ERROR Reading crb_init area: val:%x\n", n);
+                return -EIO;
+        }
+        offset = n & 0xffffU;
+        n = (n >> 16) & 0xffffU;
+
+        if (n >= 1024) {
+                dev_err(&pdev->dev, "QLOGIC card flash not initialized.\n");
+                return -EIO;
+        }
+
+        buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
+        if (buf == NULL) {
+                dev_err(&pdev->dev, "Unable to calloc memory for rom read.\n");
+                return -ENOMEM;
+        }
+
+        for (i = 0; i < n; i++) {
+                if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
+                qlcnic_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
+                        kfree(buf);
+                        return -EIO;
+                }
+
+                buf[i].addr = addr;
+                buf[i].data = val;
+        }
+
+        for (i = 0; i < n; i++) {
+
+                off = qlcnic_decode_crb_addr(buf[i].addr);
+                if (off == QLCNIC_ADDR_ERROR) {
+                        dev_err(&pdev->dev, "CRB init value out of range %x\n",
+                                        buf[i].addr);
+                        continue;
+                }
+                off += QLCNIC_PCI_CRBSPACE;
+
+                if (off & 1)
+                        continue;
+
+                /* skipping cold reboot MAGIC */
+                if (off == QLCNIC_CAM_RAM(0x1fc))
+                        continue;
+                if (off == (QLCNIC_CRB_I2C0 + 0x1c))
+                        continue;
+                if (off == (ROMUSB_GLB + 0xbc)) /* do not reset PCI */
+                        continue;
+                if (off == (ROMUSB_GLB + 0xa8))
+                        continue;
+                if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
+                        continue;
+                if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
+                        continue;
+                if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
+                        continue;
+                if ((off & 0x0ff00000) == QLCNIC_CRB_DDR_NET)
+                        continue;
+                /* skip the function enable register */
+                if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION))
+                        continue;
+                if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION2))
+                        continue;
+                if ((off & 0x0ff00000) == QLCNIC_CRB_SMB)
+                        continue;
+
+                init_delay = 1;
+                /* After writing this register, HW needs time for CRB */
+                /* to quiet down (else crb_window returns 0xffffffff) */
+                if (off == QLCNIC_ROMUSB_GLB_SW_RESET)
+                        init_delay = 1000;
+
+                QLCWR32(adapter, off, buf[i].data);
+
+                msleep(init_delay);
+        }
+        kfree(buf);
+
+        /* Initialize protocol process engine */
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0xec, 0x1e);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0x4c, 8);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_I + 0x4c, 8);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x8, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0xc, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x8, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0xc, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x8, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0xc, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x8, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x8, 0);
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0xc, 0);
+        msleep(1);
+        QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS1, 0);
+        QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS2, 0);
+        return 0;
+}
+
+static int qlcnic_cmd_peg_ready(struct qlcnic_adapter *adapter)
+{
+        u32 val;
+        int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
+
+        do {
+                val = QLCRD32(adapter, CRB_CMDPEG_STATE);
+
+                switch (val) {
+                case PHAN_INITIALIZE_COMPLETE:
+                case PHAN_INITIALIZE_ACK:
+                        return 0;
+                case PHAN_INITIALIZE_FAILED:
+                        goto out_err;
+                default:
+                        break;
+                }
+
+                msleep(QLCNIC_CMDPEG_CHECK_DELAY);
+
+        } while (--retries);
+
+        QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
+
+out_err:
+        dev_err(&adapter->pdev->dev, "Command Peg initialization not "
+                      "complete, state: 0x%x.\n", val);
+        return -EIO;
+}
+
+static int
+qlcnic_receive_peg_ready(struct qlcnic_adapter *adapter)
+{
+        u32 val;
+        int retries = QLCNIC_RCVPEG_CHECK_RETRY_COUNT;
+
+        do {
+                val = QLCRD32(adapter, CRB_RCVPEG_STATE);
+
+                if (val == PHAN_PEG_RCV_INITIALIZED)
+                        return 0;
+
+                msleep(QLCNIC_RCVPEG_CHECK_DELAY);
+
+        } while (--retries);
+
+        if (!retries) {
+                dev_err(&adapter->pdev->dev, "Receive Peg initialization not "
+                              "complete, state: 0x%x.\n", val);
+                return -EIO;
+        }
+
+        return 0;
+}
+
+int
+qlcnic_check_fw_status(struct qlcnic_adapter *adapter)
+{
+        int err;
+
+        err = qlcnic_cmd_peg_ready(adapter);
+        if (err)
+                return err;
+
+        err = qlcnic_receive_peg_ready(adapter);
+        if (err)
+                return err;
+
+        QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
+
+        return err;
+}
+
+int
+qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
+
+        int timeo;
+        u32 val;
+
+        val = QLCRD32(adapter, QLCNIC_CRB_DEV_PARTITION_INFO);
+        val = QLC_DEV_GET_DRV(val, adapter->portnum);
+        if ((val & 0x3) != QLCNIC_TYPE_NIC) {
+                dev_err(&adapter->pdev->dev,
+                        "Not an Ethernet NIC func=%u\n", val);
+                return -EIO;
+        }
+        adapter->physical_port = (val >> 2);
+        if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DEV_INIT_TIMEOUT, &timeo))
+                timeo = QLCNIC_INIT_TIMEOUT_SECS;
+
+        adapter->dev_init_timeo = timeo;
+
+        if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DRV_RESET_TIMEOUT, &timeo))
+                timeo = QLCNIC_RESET_TIMEOUT_SECS;
+
+        adapter->reset_ack_timeo = timeo;
+
+        return 0;
+}
+
+static int qlcnic_get_flt_entry(struct qlcnic_adapter *adapter, u8 region,
+                                struct qlcnic_flt_entry *region_entry)
+{
+        struct qlcnic_flt_header flt_hdr;
+        struct qlcnic_flt_entry *flt_entry;
+        int i = 0, ret;
+        u32 entry_size;
+
+        memset(region_entry, 0, sizeof(struct qlcnic_flt_entry));
+        ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION,
+                                         (u8 *)&flt_hdr,
+                                         sizeof(struct qlcnic_flt_header));
+        if (ret) {
+                dev_warn(&adapter->pdev->dev,
+                         "error reading flash layout header\n");
+                return -EIO;
+        }
+
+        entry_size = flt_hdr.len - sizeof(struct qlcnic_flt_header);
+        flt_entry = (struct qlcnic_flt_entry *)vzalloc(entry_size);
+        if (flt_entry == NULL) {
+                dev_warn(&adapter->pdev->dev, "error allocating memory\n");
+                return -EIO;
+        }
+
+        ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION +
+                                         sizeof(struct qlcnic_flt_header),
+                                         (u8 *)flt_entry, entry_size);
+        if (ret) {
+                dev_warn(&adapter->pdev->dev,
+                         "error reading flash layout entries\n");
+                goto err_out;
+        }
+
+        while (i < (entry_size/sizeof(struct qlcnic_flt_entry))) {
+                if (flt_entry[i].region == region)
+                        break;
+                i++;
+        }
+        if (i >= (entry_size/sizeof(struct qlcnic_flt_entry))) {
+                dev_warn(&adapter->pdev->dev,
+                         "region=%x not found in %d regions\n", region, i);
+                ret = -EIO;
+                goto err_out;
+        }
+        memcpy(region_entry, &flt_entry[i], sizeof(struct qlcnic_flt_entry));
+
+err_out:
+        vfree(flt_entry);
+        return ret;
+}
+
+int
+qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_flt_entry fw_entry;
+        u32 ver = -1, min_ver;
+        int ret;
+
+        ret = qlcnic_get_flt_entry(adapter, QLCNIC_FW_IMAGE_REGION, &fw_entry);
+        if (!ret)
+                /* 0-4:-signature,  4-8:-fw version */
+                qlcnic_rom_fast_read(adapter, fw_entry.start_addr + 4,
+                                     (int *)&ver);
+        else
+                qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET,
+                                     (int *)&ver);
+
+        ver = QLCNIC_DECODE_VERSION(ver);
+        min_ver = QLCNIC_MIN_FW_VERSION;
+
+        if (ver < min_ver) {
+                dev_err(&adapter->pdev->dev,
+                        "firmware version %d.%d.%d unsupported."
+                        "Min supported version %d.%d.%d\n",
+                        _major(ver), _minor(ver), _build(ver),
+                        _major(min_ver), _minor(min_ver), _build(min_ver));
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int
+qlcnic_has_mn(struct qlcnic_adapter *adapter)
+{
+        u32 capability;
+        capability = 0;
+
+        capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY);
+        if (capability & QLCNIC_PEG_TUNE_MN_PRESENT)
+                return 1;
+
+        return 0;
+}
+
+static
+struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section)
+{
+        u32 i;
+        struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
+        __le32 entries = cpu_to_le32(directory->num_entries);
+
+        for (i = 0; i < entries; i++) {
+
+                __le32 offs = cpu_to_le32(directory->findex) +
+                                (i * cpu_to_le32(directory->entry_size));
+                __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
+
+                if (tab_type == section)
+                        return (struct uni_table_desc *) &unirom[offs];
+        }
+
+        return NULL;
+}
+
+#define FILEHEADER_SIZE (14 * 4)
+
+static int
+qlcnic_validate_header(struct qlcnic_adapter *adapter)
+{
+        const u8 *unirom = adapter->fw->data;
+        struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
+        __le32 fw_file_size = adapter->fw->size;
+        __le32 entries;
+        __le32 entry_size;
+        __le32 tab_size;
+
+        if (fw_file_size < FILEHEADER_SIZE)
+                return -EINVAL;
+
+        entries = cpu_to_le32(directory->num_entries);
+        entry_size = cpu_to_le32(directory->entry_size);
+        tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
+
+        if (fw_file_size < tab_size)
+                return -EINVAL;
+
+        return 0;
+}
+
+static int
+qlcnic_validate_bootld(struct qlcnic_adapter *adapter)
+{
+        struct uni_table_desc *tab_desc;
+        struct uni_data_desc *descr;
+        const u8 *unirom = adapter->fw->data;
+        int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
+                                QLCNIC_UNI_BOOTLD_IDX_OFF));
+        __le32 offs;
+        __le32 tab_size;
+        __le32 data_size;
+
+        tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD);
+
+        if (!tab_desc)
+                return -EINVAL;
+
+        tab_size = cpu_to_le32(tab_desc->findex) +
+                        (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
+
+        if (adapter->fw->size < tab_size)
+                return -EINVAL;
+
+        offs = cpu_to_le32(tab_desc->findex) +
+                (cpu_to_le32(tab_desc->entry_size) * (idx));
+        descr = (struct uni_data_desc *)&unirom[offs];
+
+        data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
+
+        if (adapter->fw->size < data_size)
+                return -EINVAL;
+
+        return 0;
+}
+
+static int
+qlcnic_validate_fw(struct qlcnic_adapter *adapter)
+{
+        struct uni_table_desc *tab_desc;
+        struct uni_data_desc *descr;
+        const u8 *unirom = adapter->fw->data;
+        int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
+                                QLCNIC_UNI_FIRMWARE_IDX_OFF));
+        __le32 offs;
+        __le32 tab_size;
+        __le32 data_size;
+
+        tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW);
+
+        if (!tab_desc)
+                return -EINVAL;
+
+        tab_size = cpu_to_le32(tab_desc->findex) +
+                        (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
+
+        if (adapter->fw->size < tab_size)
+                return -EINVAL;
+
+        offs = cpu_to_le32(tab_desc->findex) +
+                (cpu_to_le32(tab_desc->entry_size) * (idx));
+        descr = (struct uni_data_desc *)&unirom[offs];
+        data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
+
+        if (adapter->fw->size < data_size)
+                return -EINVAL;
+
+        return 0;
+}
+
+static int
+qlcnic_validate_product_offs(struct qlcnic_adapter *adapter)
+{
+        struct uni_table_desc *ptab_descr;
+        const u8 *unirom = adapter->fw->data;
+        int mn_present = qlcnic_has_mn(adapter);
+        __le32 entries;
+        __le32 entry_size;
+        __le32 tab_size;
+        u32 i;
+
+        ptab_descr = qlcnic_get_table_desc(unirom,
+                                QLCNIC_UNI_DIR_SECT_PRODUCT_TBL);
+        if (!ptab_descr)
+                return -EINVAL;
+
+        entries = cpu_to_le32(ptab_descr->num_entries);
+        entry_size = cpu_to_le32(ptab_descr->entry_size);
+        tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
+
+        if (adapter->fw->size < tab_size)
+                return -EINVAL;
+
+nomn:
+        for (i = 0; i < entries; i++) {
+
+                __le32 flags, file_chiprev, offs;
+                u8 chiprev = adapter->ahw->revision_id;
+                u32 flagbit;
+
+                offs = cpu_to_le32(ptab_descr->findex) +
+                                (i * cpu_to_le32(ptab_descr->entry_size));
+                flags = cpu_to_le32(*((int *)&unirom[offs] +
+                                                QLCNIC_UNI_FLAGS_OFF));
+                file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
+                                                QLCNIC_UNI_CHIP_REV_OFF));
+
+                flagbit = mn_present ? 1 : 2;
+
+                if ((chiprev == file_chiprev) &&
+                                        ((1ULL << flagbit) & flags)) {
+                        adapter->file_prd_off = offs;
+                        return 0;
+                }
+        }
+        if (mn_present) {
+                mn_present = 0;
+                goto nomn;
+        }
+        return -EINVAL;
+}
+
+static int
+qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter)
+{
+        if (qlcnic_validate_header(adapter)) {
+                dev_err(&adapter->pdev->dev,
+                                "unified image: header validation failed\n");
+                return -EINVAL;
+        }
+
+        if (qlcnic_validate_product_offs(adapter)) {
+                dev_err(&adapter->pdev->dev,
+                                "unified image: product validation failed\n");
+                return -EINVAL;
+        }
+
+        if (qlcnic_validate_bootld(adapter)) {
+                dev_err(&adapter->pdev->dev,
+                                "unified image: bootld validation failed\n");
+                return -EINVAL;
+        }
+
+        if (qlcnic_validate_fw(adapter)) {
+                dev_err(&adapter->pdev->dev,
+                                "unified image: firmware validation failed\n");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static
+struct uni_data_desc *qlcnic_get_data_desc(struct qlcnic_adapter *adapter,
+                        u32 section, u32 idx_offset)
+{
+        const u8 *unirom = adapter->fw->data;
+        int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
+                                                                idx_offset));
+        struct uni_table_desc *tab_desc;
+        __le32 offs;
+
+        tab_desc = qlcnic_get_table_desc(unirom, section);
+
+        if (tab_desc == NULL)
+                return NULL;
+
+        offs = cpu_to_le32(tab_desc->findex) +
+                        (cpu_to_le32(tab_desc->entry_size) * idx);
+
+        return (struct uni_data_desc *)&unirom[offs];
+}
+
+static u8 *
+qlcnic_get_bootld_offs(struct qlcnic_adapter *adapter)
+{
+        u32 offs = QLCNIC_BOOTLD_START;
+
+        if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
+                offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
+                                        QLCNIC_UNI_DIR_SECT_BOOTLD,
+                                        QLCNIC_UNI_BOOTLD_IDX_OFF))->findex);
+
+        return (u8 *)&adapter->fw->data[offs];
+}
+
+static u8 *
+qlcnic_get_fw_offs(struct qlcnic_adapter *adapter)
+{
+        u32 offs = QLCNIC_IMAGE_START;
+
+        if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
+                offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
+                                        QLCNIC_UNI_DIR_SECT_FW,
+                                        QLCNIC_UNI_FIRMWARE_IDX_OFF))->findex);
+
+        return (u8 *)&adapter->fw->data[offs];
+}
+
+static __le32
+qlcnic_get_fw_size(struct qlcnic_adapter *adapter)
+{
+        if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
+                return cpu_to_le32((qlcnic_get_data_desc(adapter,
+                                        QLCNIC_UNI_DIR_SECT_FW,
+                                        QLCNIC_UNI_FIRMWARE_IDX_OFF))->size);
+        else
+                return cpu_to_le32(
+                        *(u32 *)&adapter->fw->data[QLCNIC_FW_SIZE_OFFSET]);
+}
+
+static __le32
+qlcnic_get_fw_version(struct qlcnic_adapter *adapter)
+{
+        struct uni_data_desc *fw_data_desc;
+        const struct firmware *fw = adapter->fw;
+        __le32 major, minor, sub;
+        const u8 *ver_str;
+        int i, ret;
+
+        if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
+                return cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_VERSION_OFFSET]);
+
+        fw_data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
+                        QLCNIC_UNI_FIRMWARE_IDX_OFF);
+        ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
+                cpu_to_le32(fw_data_desc->size) - 17;
+
+        for (i = 0; i < 12; i++) {
+                if (!strncmp(&ver_str[i], "REV=", 4)) {
+                        ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
+                                        &major, &minor, &sub);
+                        if (ret != 3)
+                                return 0;
+                        else
+                                return major + (minor << 8) + (sub << 16);
+                }
+        }
+
+        return 0;
+}
+
+static __le32
+qlcnic_get_bios_version(struct qlcnic_adapter *adapter)
+{
+        const struct firmware *fw = adapter->fw;
+        __le32 bios_ver, prd_off = adapter->file_prd_off;
+
+        if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
+                return cpu_to_le32(
+                        *(u32 *)&fw->data[QLCNIC_BIOS_VERSION_OFFSET]);
+
+        bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
+                                + QLCNIC_UNI_BIOS_VERSION_OFF));
+
+        return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24);
+}
+
+static void qlcnic_rom_lock_recovery(struct qlcnic_adapter *adapter)
+{
+        if (qlcnic_pcie_sem_lock(adapter, 2, QLCNIC_ROM_LOCK_ID))
+                dev_info(&adapter->pdev->dev, "Resetting rom_lock\n");
+
+        qlcnic_pcie_sem_unlock(adapter, 2);
+}
+
+static int
+qlcnic_check_fw_hearbeat(struct qlcnic_adapter *adapter)
+{
+        u32 heartbeat, ret = -EIO;
+        int retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
+
+        adapter->heartbeat = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
+
+        do {
+                msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
+                heartbeat = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
+                if (heartbeat != adapter->heartbeat) {
+                        ret = QLCNIC_RCODE_SUCCESS;
+                        break;
+                }
+        } while (--retries);
+
+        return ret;
+}
+
+int
+qlcnic_need_fw_reset(struct qlcnic_adapter *adapter)
+{
+        if (qlcnic_check_fw_hearbeat(adapter)) {
+                qlcnic_rom_lock_recovery(adapter);
+                return 1;
+        }
+
+        if (adapter->need_fw_reset)
+                return 1;
+
+        if (adapter->fw)
+                return 1;
+
+        return 0;
+}
+
+static const char *fw_name[] = {
+        QLCNIC_UNIFIED_ROMIMAGE_NAME,
+        QLCNIC_FLASH_ROMIMAGE_NAME,
+};
+
+int
+qlcnic_load_firmware(struct qlcnic_adapter *adapter)
+{
+        u64 *ptr64;
+        u32 i, flashaddr, size;
+        const struct firmware *fw = adapter->fw;
+        struct pci_dev *pdev = adapter->pdev;
+
+        dev_info(&pdev->dev, "loading firmware from %s\n",
+                        fw_name[adapter->fw_type]);
+
+        if (fw) {
+                __le64 data;
+
+                size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
+
+                ptr64 = (u64 *)qlcnic_get_bootld_offs(adapter);
+                flashaddr = QLCNIC_BOOTLD_START;
+
+                for (i = 0; i < size; i++) {
+                        data = cpu_to_le64(ptr64[i]);
+
+                        if (qlcnic_pci_mem_write_2M(adapter, flashaddr, data))
+                                return -EIO;
+
+                        flashaddr += 8;
+                }
+
+                size = (__force u32)qlcnic_get_fw_size(adapter) / 8;
+
+                ptr64 = (u64 *)qlcnic_get_fw_offs(adapter);
+                flashaddr = QLCNIC_IMAGE_START;
+
+                for (i = 0; i < size; i++) {
+                        data = cpu_to_le64(ptr64[i]);
+
+                        if (qlcnic_pci_mem_write_2M(adapter,
+                                                flashaddr, data))
+                                return -EIO;
+
+                        flashaddr += 8;
+                }
+
+                size = (__force u32)qlcnic_get_fw_size(adapter) % 8;
+                if (size) {
+                        data = cpu_to_le64(ptr64[i]);
+
+                        if (qlcnic_pci_mem_write_2M(adapter,
+                                                flashaddr, data))
+                                return -EIO;
+                }
+
+        } else {
+                u64 data;
+                u32 hi, lo;
+                int ret;
+                struct qlcnic_flt_entry bootld_entry;
+
+                ret = qlcnic_get_flt_entry(adapter, QLCNIC_BOOTLD_REGION,
+                                        &bootld_entry);
+                if (!ret) {
+                        size = bootld_entry.size / 8;
+                        flashaddr = bootld_entry.start_addr;
+                } else {
+                        size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
+                        flashaddr = QLCNIC_BOOTLD_START;
+                        dev_info(&pdev->dev,
+                                "using legacy method to get flash fw region");
+                }
+
+                for (i = 0; i < size; i++) {
+                        if (qlcnic_rom_fast_read(adapter,
+                                        flashaddr, (int *)&lo) != 0)
+                                return -EIO;
+                        if (qlcnic_rom_fast_read(adapter,
+                                        flashaddr + 4, (int *)&hi) != 0)
+                                return -EIO;
+
+                        data = (((u64)hi << 32) | lo);
+
+                        if (qlcnic_pci_mem_write_2M(adapter,
+                                                flashaddr, data))
+                                return -EIO;
+
+                        flashaddr += 8;
+                }
+        }
+        msleep(1);
+
+        QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
+        QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
+        return 0;
+}
+
+static int
+qlcnic_validate_firmware(struct qlcnic_adapter *adapter)
+{
+        __le32 val;
+        u32 ver, bios, min_size;
+        struct pci_dev *pdev = adapter->pdev;
+        const struct firmware *fw = adapter->fw;
+        u8 fw_type = adapter->fw_type;
+
+        if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) {
+                if (qlcnic_validate_unified_romimage(adapter))
+                        return -EINVAL;
+
+                min_size = QLCNIC_UNI_FW_MIN_SIZE;
+        } else {
+                val = cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]);
+                if ((__force u32)val != QLCNIC_BDINFO_MAGIC)
+                        return -EINVAL;
+
+                min_size = QLCNIC_FW_MIN_SIZE;
+        }
+
+        if (fw->size < min_size)
+                return -EINVAL;
+
+        val = qlcnic_get_fw_version(adapter);
+        ver = QLCNIC_DECODE_VERSION(val);
+
+        if (ver < QLCNIC_MIN_FW_VERSION) {
+                dev_err(&pdev->dev,
+                                "%s: firmware version %d.%d.%d unsupported\n",
+                fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
+                return -EINVAL;
+        }
+
+        val = qlcnic_get_bios_version(adapter);
+        qlcnic_rom_fast_read(adapter, QLCNIC_BIOS_VERSION_OFFSET, (int *)&bios);
+        if ((__force u32)val != bios) {
+                dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
+                                fw_name[fw_type]);
+                return -EINVAL;
+        }
+
+        QLCWR32(adapter, QLCNIC_CAM_RAM(0x1fc), QLCNIC_BDINFO_MAGIC);
+        return 0;
+}
+
+static void
+qlcnic_get_next_fwtype(struct qlcnic_adapter *adapter)
+{
+        u8 fw_type;
+
+        switch (adapter->fw_type) {
+        case QLCNIC_UNKNOWN_ROMIMAGE:
+                fw_type = QLCNIC_UNIFIED_ROMIMAGE;
+                break;
+
+        case QLCNIC_UNIFIED_ROMIMAGE:
+        default:
+                fw_type = QLCNIC_FLASH_ROMIMAGE;
+                break;
+        }
+
+        adapter->fw_type = fw_type;
+}
+
+
+
+void qlcnic_request_firmware(struct qlcnic_adapter *adapter)
+{
+        struct pci_dev *pdev = adapter->pdev;
+        int rc;
+
+        adapter->fw_type = QLCNIC_UNKNOWN_ROMIMAGE;
+
+next:
+        qlcnic_get_next_fwtype(adapter);
+
+        if (adapter->fw_type == QLCNIC_FLASH_ROMIMAGE) {
+                adapter->fw = NULL;
+        } else {
+                rc = request_firmware(&adapter->fw,
+                                fw_name[adapter->fw_type], &pdev->dev);
+                if (rc != 0)
+                        goto next;
+
+                rc = qlcnic_validate_firmware(adapter);
+                if (rc != 0) {
+                        release_firmware(adapter->fw);
+                        msleep(1);
+                        goto next;
+                }
+        }
+}
+
+
+void
+qlcnic_release_firmware(struct qlcnic_adapter *adapter)
+{
+        if (adapter->fw)
+                release_firmware(adapter->fw);
+        adapter->fw = NULL;
+}
+
+static void
+qlcnic_handle_linkevent(struct qlcnic_adapter *adapter,
+                                struct qlcnic_fw_msg *msg)
+{
+        u32 cable_OUI;
+        u16 cable_len;
+        u16 link_speed;
+        u8  link_status, module, duplex, autoneg;
+        u8 lb_status = 0;
+        struct net_device *netdev = adapter->netdev;
+
+        adapter->has_link_events = 1;
+
+        cable_OUI = msg->body[1] & 0xffffffff;
+        cable_len = (msg->body[1] >> 32) & 0xffff;
+        link_speed = (msg->body[1] >> 48) & 0xffff;
+
+        link_status = msg->body[2] & 0xff;
+        duplex = (msg->body[2] >> 16) & 0xff;
+        autoneg = (msg->body[2] >> 24) & 0xff;
+        lb_status = (msg->body[2] >> 32) & 0x3;
+
+        module = (msg->body[2] >> 8) & 0xff;
+        if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE)
+                dev_info(&netdev->dev, "unsupported cable: OUI 0x%x, "
+                                "length %d\n", cable_OUI, cable_len);
+        else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN)
+                dev_info(&netdev->dev, "unsupported cable length %d\n",
+                                cable_len);
+
+        if (!link_status && (lb_status == QLCNIC_ILB_MODE ||
+            lb_status == QLCNIC_ELB_MODE))
+                adapter->ahw->loopback_state |= QLCNIC_LINKEVENT;
+
+        qlcnic_advert_link_change(adapter, link_status);
+
+        if (duplex == LINKEVENT_FULL_DUPLEX)
+                adapter->link_duplex = DUPLEX_FULL;
+        else
+                adapter->link_duplex = DUPLEX_HALF;
+
+        adapter->module_type = module;
+        adapter->link_autoneg = autoneg;
+        adapter->link_speed = link_speed;
+}
+
+static void
+qlcnic_handle_fw_message(int desc_cnt, int index,
+                struct qlcnic_host_sds_ring *sds_ring)
+{
+        struct qlcnic_fw_msg msg;
+        struct status_desc *desc;
+        struct qlcnic_adapter *adapter;
+        struct device *dev;
+        int i = 0, opcode, ret;
+
+        while (desc_cnt > 0 && i < 8) {
+                desc = &sds_ring->desc_head[index];
+                msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
+                msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
+
+                index = get_next_index(index, sds_ring->num_desc);
+                desc_cnt--;
+        }
+
+        adapter = sds_ring->adapter;
+        dev = &adapter->pdev->dev;
+        opcode = qlcnic_get_nic_msg_opcode(msg.body[0]);
+
+        switch (opcode) {
+        case QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
+                qlcnic_handle_linkevent(adapter, &msg);
+                break;
+        case QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK:
+                ret = (u32)(msg.body[1]);
+                switch (ret) {
+                case 0:
+                        adapter->ahw->loopback_state |= QLCNIC_LB_RESPONSE;
+                        break;
+                case 1:
+                        dev_info(dev, "loopback already in progress\n");
+                        adapter->diag_cnt = -QLCNIC_TEST_IN_PROGRESS;
+                        break;
+                case 2:
+                        dev_info(dev, "loopback cable is not connected\n");
+                        adapter->diag_cnt = -QLCNIC_LB_CABLE_NOT_CONN;
+                        break;
+                default:
+                        dev_info(dev, "loopback configure request failed,"
+                                        " ret %x\n", ret);
+                        adapter->diag_cnt = -QLCNIC_UNDEFINED_ERROR;
+                        break;
+                }
+                break;
+        default:
+                break;
+        }
+}
+
+static int
+qlcnic_alloc_rx_skb(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_rds_ring *rds_ring,
+                struct qlcnic_rx_buffer *buffer)
+{
+        struct sk_buff *skb;
+        dma_addr_t dma;
+        struct pci_dev *pdev = adapter->pdev;
+
+        skb = dev_alloc_skb(rds_ring->skb_size);
+        if (!skb) {
+                adapter->stats.skb_alloc_failure++;
+                return -ENOMEM;
+        }
+
+        skb_reserve(skb, NET_IP_ALIGN);
+
+        dma = pci_map_single(pdev, skb->data,
+                        rds_ring->dma_size, PCI_DMA_FROMDEVICE);
+
+        if (pci_dma_mapping_error(pdev, dma)) {
+                adapter->stats.rx_dma_map_error++;
+                dev_kfree_skb_any(skb);
+                return -ENOMEM;
+        }
+
+        buffer->skb = skb;
+        buffer->dma = dma;
+
+        return 0;
+}
+
+static struct sk_buff *qlcnic_process_rxbuf(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_rds_ring *rds_ring, u16 index, u16 cksum)
+{
+        struct qlcnic_rx_buffer *buffer;
+        struct sk_buff *skb;
+
+        buffer = &rds_ring->rx_buf_arr[index];
+
+        if (unlikely(buffer->skb == NULL)) {
+                WARN_ON(1);
+                return NULL;
+        }
+
+        pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
+                        PCI_DMA_FROMDEVICE);
+
+        skb = buffer->skb;
+
+        if (likely((adapter->netdev->features & NETIF_F_RXCSUM) &&
+            (cksum == STATUS_CKSUM_OK || cksum == STATUS_CKSUM_LOOP))) {
+                adapter->stats.csummed++;
+                skb->ip_summed = CHECKSUM_UNNECESSARY;
+        } else {
+                skb_checksum_none_assert(skb);
+        }
+
+        skb->dev = adapter->netdev;
+
+        buffer->skb = NULL;
+
+        return skb;
+}
+
+static inline int
+qlcnic_check_rx_tagging(struct qlcnic_adapter *adapter, struct sk_buff *skb,
+                        u16 *vlan_tag)
+{
+        struct ethhdr *eth_hdr;
+
+        if (!__vlan_get_tag(skb, vlan_tag)) {
+                eth_hdr = (struct ethhdr *) skb->data;
+                memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
+                skb_pull(skb, VLAN_HLEN);
+        }
+        if (!adapter->pvid)
+                return 0;
+
+        if (*vlan_tag == adapter->pvid) {
+                /* Outer vlan tag. Packet should follow non-vlan path */
+                *vlan_tag = 0xffff;
+                return 0;
+        }
+        if (adapter->flags & QLCNIC_TAGGING_ENABLED)
+                return 0;
+
+        return -EINVAL;
+}
+
+static struct qlcnic_rx_buffer *
+qlcnic_process_rcv(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_sds_ring *sds_ring,
+                int ring, u64 sts_data0)
+{
+        struct net_device *netdev = adapter->netdev;
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+        struct qlcnic_rx_buffer *buffer;
+        struct sk_buff *skb;
+        struct qlcnic_host_rds_ring *rds_ring;
+        int index, length, cksum, pkt_offset;
+        u16 vid = 0xffff;
+
+        if (unlikely(ring >= adapter->max_rds_rings))
+                return NULL;
+
+        rds_ring = &recv_ctx->rds_rings[ring];
+
+        index = qlcnic_get_sts_refhandle(sts_data0);
+        if (unlikely(index >= rds_ring->num_desc))
+                return NULL;
+
+        buffer = &rds_ring->rx_buf_arr[index];
+
+        length = qlcnic_get_sts_totallength(sts_data0);
+        cksum  = qlcnic_get_sts_status(sts_data0);
+        pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
+
+        skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
+        if (!skb)
+                return buffer;
+
+        if (length > rds_ring->skb_size)
+                skb_put(skb, rds_ring->skb_size);
+        else
+                skb_put(skb, length);
+
+        if (pkt_offset)
+                skb_pull(skb, pkt_offset);
+
+        if (unlikely(qlcnic_check_rx_tagging(adapter, skb, &vid))) {
+                adapter->stats.rxdropped++;
+                dev_kfree_skb(skb);
+                return buffer;
+        }
+
+        skb->protocol = eth_type_trans(skb, netdev);
+
+        if (vid != 0xffff)
+                __vlan_hwaccel_put_tag(skb, vid);
+
+        napi_gro_receive(&sds_ring->napi, skb);
+
+        adapter->stats.rx_pkts++;
+        adapter->stats.rxbytes += length;
+
+        return buffer;
+}
+
+#define QLC_TCP_HDR_SIZE            20
+#define QLC_TCP_TS_OPTION_SIZE      12
+#define QLC_TCP_TS_HDR_SIZE         (QLC_TCP_HDR_SIZE + QLC_TCP_TS_OPTION_SIZE)
+
+static struct qlcnic_rx_buffer *
+qlcnic_process_lro(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_sds_ring *sds_ring,
+                int ring, u64 sts_data0, u64 sts_data1)
+{
+        struct net_device *netdev = adapter->netdev;
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+        struct qlcnic_rx_buffer *buffer;
+        struct sk_buff *skb;
+        struct qlcnic_host_rds_ring *rds_ring;
+        struct iphdr *iph;
+        struct tcphdr *th;
+        bool push, timestamp;
+        int l2_hdr_offset, l4_hdr_offset;
+        int index;
+        u16 lro_length, length, data_offset;
+        u32 seq_number;
+        u16 vid = 0xffff;
+
+        if (unlikely(ring > adapter->max_rds_rings))
+                return NULL;
+
+        rds_ring = &recv_ctx->rds_rings[ring];
+
+        index = qlcnic_get_lro_sts_refhandle(sts_data0);
+        if (unlikely(index > rds_ring->num_desc))
+                return NULL;
+
+        buffer = &rds_ring->rx_buf_arr[index];
+
+        timestamp = qlcnic_get_lro_sts_timestamp(sts_data0);
+        lro_length = qlcnic_get_lro_sts_length(sts_data0);
+        l2_hdr_offset = qlcnic_get_lro_sts_l2_hdr_offset(sts_data0);
+        l4_hdr_offset = qlcnic_get_lro_sts_l4_hdr_offset(sts_data0);
+        push = qlcnic_get_lro_sts_push_flag(sts_data0);
+        seq_number = qlcnic_get_lro_sts_seq_number(sts_data1);
+
+        skb = qlcnic_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
+        if (!skb)
+                return buffer;
+
+        if (timestamp)
+                data_offset = l4_hdr_offset + QLC_TCP_TS_HDR_SIZE;
+        else
+                data_offset = l4_hdr_offset + QLC_TCP_HDR_SIZE;
+
+        skb_put(skb, lro_length + data_offset);
+
+        skb_pull(skb, l2_hdr_offset);
+
+        if (unlikely(qlcnic_check_rx_tagging(adapter, skb, &vid))) {
+                adapter->stats.rxdropped++;
+                dev_kfree_skb(skb);
+                return buffer;
+        }
+
+        skb->protocol = eth_type_trans(skb, netdev);
+
+        iph = (struct iphdr *)skb->data;
+        th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
+
+        length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
+        iph->tot_len = htons(length);
+        iph->check = 0;
+        iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
+        th->psh = push;
+        th->seq = htonl(seq_number);
+
+        length = skb->len;
+
+        if (vid != 0xffff)
+                __vlan_hwaccel_put_tag(skb, vid);
+        netif_receive_skb(skb);
+
+        adapter->stats.lro_pkts++;
+        adapter->stats.lrobytes += length;
+
+        return buffer;
+}
+
+int
+qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max)
+{
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+        struct list_head *cur;
+        struct status_desc *desc;
+        struct qlcnic_rx_buffer *rxbuf;
+        u64 sts_data0, sts_data1;
+
+        int count = 0;
+        int opcode, ring, desc_cnt;
+        u32 consumer = sds_ring->consumer;
+
+        while (count < max) {
+                desc = &sds_ring->desc_head[consumer];
+                sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
+
+                if (!(sts_data0 & STATUS_OWNER_HOST))
+                        break;
+
+                desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
+                opcode = qlcnic_get_sts_opcode(sts_data0);
+
+                switch (opcode) {
+                case QLCNIC_RXPKT_DESC:
+                case QLCNIC_OLD_RXPKT_DESC:
+                case QLCNIC_SYN_OFFLOAD:
+                        ring = qlcnic_get_sts_type(sts_data0);
+                        rxbuf = qlcnic_process_rcv(adapter, sds_ring,
+                                        ring, sts_data0);
+                        break;
+                case QLCNIC_LRO_DESC:
+                        ring = qlcnic_get_lro_sts_type(sts_data0);
+                        sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
+                        rxbuf = qlcnic_process_lro(adapter, sds_ring,
+                                        ring, sts_data0, sts_data1);
+                        break;
+                case QLCNIC_RESPONSE_DESC:
+                        qlcnic_handle_fw_message(desc_cnt, consumer, sds_ring);
+                default:
+                        goto skip;
+                }
+
+                WARN_ON(desc_cnt > 1);
+
+                if (likely(rxbuf))
+                        list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
+                else
+                        adapter->stats.null_rxbuf++;
+
+skip:
+                for (; desc_cnt > 0; desc_cnt--) {
+                        desc = &sds_ring->desc_head[consumer];
+                        desc->status_desc_data[0] =
+                                cpu_to_le64(STATUS_OWNER_PHANTOM);
+                        consumer = get_next_index(consumer, sds_ring->num_desc);
+                }
+                count++;
+        }
+
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                struct qlcnic_host_rds_ring *rds_ring =
+                        &adapter->recv_ctx->rds_rings[ring];
+
+                if (!list_empty(&sds_ring->free_list[ring])) {
+                        list_for_each(cur, &sds_ring->free_list[ring]) {
+                                rxbuf = list_entry(cur,
+                                                struct qlcnic_rx_buffer, list);
+                                qlcnic_alloc_rx_skb(adapter, rds_ring, rxbuf);
+                        }
+                        spin_lock(&rds_ring->lock);
+                        list_splice_tail_init(&sds_ring->free_list[ring],
+                                                &rds_ring->free_list);
+                        spin_unlock(&rds_ring->lock);
+                }
+
+                qlcnic_post_rx_buffers_nodb(adapter, rds_ring);
+        }
+
+        if (count) {
+                sds_ring->consumer = consumer;
+                writel(consumer, sds_ring->crb_sts_consumer);
+        }
+
+        return count;
+}
+
+void
+qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
+        struct qlcnic_host_rds_ring *rds_ring)
+{
+        struct rcv_desc *pdesc;
+        struct qlcnic_rx_buffer *buffer;
+        int count = 0;
+        u32 producer;
+        struct list_head *head;
+
+        producer = rds_ring->producer;
+
+        head = &rds_ring->free_list;
+        while (!list_empty(head)) {
+
+                buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
+
+                if (!buffer->skb) {
+                        if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
+                                break;
+                }
+
+                count++;
+                list_del(&buffer->list);
+
+                /* make a rcv descriptor  */
+                pdesc = &rds_ring->desc_head[producer];
+                pdesc->addr_buffer = cpu_to_le64(buffer->dma);
+                pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
+                pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
+
+                producer = get_next_index(producer, rds_ring->num_desc);
+        }
+
+        if (count) {
+                rds_ring->producer = producer;
+                writel((producer-1) & (rds_ring->num_desc-1),
+                                rds_ring->crb_rcv_producer);
+        }
+}
+
+static void
+qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_rds_ring *rds_ring)
+{
+        struct rcv_desc *pdesc;
+        struct qlcnic_rx_buffer *buffer;
+        int  count = 0;
+        uint32_t producer;
+        struct list_head *head;
+
+        if (!spin_trylock(&rds_ring->lock))
+                return;
+
+        producer = rds_ring->producer;
+
+        head = &rds_ring->free_list;
+        while (!list_empty(head)) {
+
+                buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
+
+                if (!buffer->skb) {
+                        if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
+                                break;
+                }
+
+                count++;
+                list_del(&buffer->list);
+
+                /* make a rcv descriptor  */
+                pdesc = &rds_ring->desc_head[producer];
+                pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
+                pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
+                pdesc->addr_buffer = cpu_to_le64(buffer->dma);
+
+                producer = get_next_index(producer, rds_ring->num_desc);
+        }
+
+        if (count) {
+                rds_ring->producer = producer;
+                writel((producer - 1) & (rds_ring->num_desc - 1),
+                                rds_ring->crb_rcv_producer);
+        }
+        spin_unlock(&rds_ring->lock);
+}
+
+static void dump_skb(struct sk_buff *skb)
+{
+        int i;
+        unsigned char *data = skb->data;
+
+        printk(KERN_INFO "\n");
+        for (i = 0; i < skb->len; i++) {
+                printk(KERN_INFO "%02x ", data[i]);
+                if ((i & 0x0f) == 8)
+                        printk(KERN_INFO "\n");
+        }
+}
+
+void qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_sds_ring *sds_ring,
+                int ring, u64 sts_data0)
+{
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+        struct sk_buff *skb;
+        struct qlcnic_host_rds_ring *rds_ring;
+        int index, length, cksum, pkt_offset;
+
+        if (unlikely(ring >= adapter->max_rds_rings))
+                return;
+
+        rds_ring = &recv_ctx->rds_rings[ring];
+
+        index = qlcnic_get_sts_refhandle(sts_data0);
+        length = qlcnic_get_sts_totallength(sts_data0);
+        if (unlikely(index >= rds_ring->num_desc))
+                return;
+
+        cksum  = qlcnic_get_sts_status(sts_data0);
+        pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
+
+        skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
+        if (!skb)
+                return;
+
+        if (length > rds_ring->skb_size)
+                skb_put(skb, rds_ring->skb_size);
+        else
+                skb_put(skb, length);
+
+        if (pkt_offset)
+                skb_pull(skb, pkt_offset);
+
+        if (!qlcnic_check_loopback_buff(skb->data, adapter->mac_addr))
+                adapter->diag_cnt++;
+        else
+                dump_skb(skb);
+
+        dev_kfree_skb_any(skb);
+        adapter->stats.rx_pkts++;
+        adapter->stats.rxbytes += length;
+
+        return;
+}
+
+void
+qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
+{
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+        struct status_desc *desc;
+        u64 sts_data0;
+        int ring, opcode, desc_cnt;
+
+        u32 consumer = sds_ring->consumer;
+
+        desc = &sds_ring->desc_head[consumer];
+        sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
+
+        if (!(sts_data0 & STATUS_OWNER_HOST))
+                return;
+
+        desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
+        opcode = qlcnic_get_sts_opcode(sts_data0);
+        switch (opcode) {
+        case QLCNIC_RESPONSE_DESC:
+                qlcnic_handle_fw_message(desc_cnt, consumer, sds_ring);
+                break;
+        default:
+                ring = qlcnic_get_sts_type(sts_data0);
+                qlcnic_process_rcv_diag(adapter, sds_ring, ring, sts_data0);
+                break;
+        }
+
+        for (; desc_cnt > 0; desc_cnt--) {
+                desc = &sds_ring->desc_head[consumer];
+                desc->status_desc_data[0] = cpu_to_le64(STATUS_OWNER_PHANTOM);
+                consumer = get_next_index(consumer, sds_ring->num_desc);
+        }
+
+        sds_ring->consumer = consumer;
+        writel(consumer, sds_ring->crb_sts_consumer);
+}
+
+void
+qlcnic_fetch_mac(struct qlcnic_adapter *adapter, u32 off1, u32 off2,
+                        u8 alt_mac, u8 *mac)
+{
+        u32 mac_low, mac_high;
+        int i;
+
+        mac_low = QLCRD32(adapter, off1);
+        mac_high = QLCRD32(adapter, off2);
+
+        if (alt_mac) {
+                mac_low |= (mac_low >> 16) | (mac_high << 16);
+                mac_high >>= 16;
+        }
+
+        for (i = 0; i < 2; i++)
+                mac[i] = (u8)(mac_high >> ((1 - i) * 8));
+        for (i = 2; i < 6; i++)
+                mac[i] = (u8)(mac_low >> ((5 - i) * 8));
+}
diff --git a/drivers/net/qlcnic/qlcnic_main.c b/drivers/net/qlcnic/qlcnic_main.c
new file mode 100644
index 00000000000..5ca1b562443
--- /dev/null
+++ b/drivers/net/qlcnic/qlcnic_main.c
@@ -0,0 +1,4366 @@
+/*
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
+ *
+ * See LICENSE.qlcnic for copyright and licensing details.
+ */
+
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+
+#include "qlcnic.h"
+
+#include <linux/swab.h>
+#include <linux/dma-mapping.h>
+#include <net/ip.h>
+#include <linux/ipv6.h>
+#include <linux/inetdevice.h>
+#include <linux/sysfs.h>
+#include <linux/aer.h>
+#include <linux/log2.h>
+
+MODULE_DESCRIPTION("QLogic 1/10 GbE Converged/Intelligent Ethernet Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(QLCNIC_LINUX_VERSIONID);
+MODULE_FIRMWARE(QLCNIC_UNIFIED_ROMIMAGE_NAME);
+
+char qlcnic_driver_name[] = "qlcnic";
+static const char qlcnic_driver_string[] = "QLogic 1/10 GbE "
+        "Converged/Intelligent Ethernet Driver v" QLCNIC_LINUX_VERSIONID;
+
+static struct workqueue_struct *qlcnic_wq;
+static int qlcnic_mac_learn;
+module_param(qlcnic_mac_learn, int, 0444);
+MODULE_PARM_DESC(qlcnic_mac_learn, "Mac Filter (0=disabled, 1=enabled)");
+
+static int use_msi = 1;
+module_param(use_msi, int, 0444);
+MODULE_PARM_DESC(use_msi, "MSI interrupt (0=disabled, 1=enabled");
+
+static int use_msi_x = 1;
+module_param(use_msi_x, int, 0444);
+MODULE_PARM_DESC(use_msi_x, "MSI-X interrupt (0=disabled, 1=enabled");
+
+static int auto_fw_reset = 1;
+module_param(auto_fw_reset, int, 0644);
+MODULE_PARM_DESC(auto_fw_reset, "Auto firmware reset (0=disabled, 1=enabled");
+
+static int load_fw_file;
+module_param(load_fw_file, int, 0444);
+MODULE_PARM_DESC(load_fw_file, "Load firmware from (0=flash, 1=file");
+
+static int qlcnic_config_npars;
+module_param(qlcnic_config_npars, int, 0444);
+MODULE_PARM_DESC(qlcnic_config_npars, "Configure NPARs (0=disabled, 1=enabled");
+
+static int __devinit qlcnic_probe(struct pci_dev *pdev,
+                const struct pci_device_id *ent);
+static void __devexit qlcnic_remove(struct pci_dev *pdev);
+static int qlcnic_open(struct net_device *netdev);
+static int qlcnic_close(struct net_device *netdev);
+static void qlcnic_tx_timeout(struct net_device *netdev);
+static void qlcnic_attach_work(struct work_struct *work);
+static void qlcnic_fwinit_work(struct work_struct *work);
+static void qlcnic_fw_poll_work(struct work_struct *work);
+static void qlcnic_schedule_work(struct qlcnic_adapter *adapter,
+                work_func_t func, int delay);
+static void qlcnic_cancel_fw_work(struct qlcnic_adapter *adapter);
+static int qlcnic_poll(struct napi_struct *napi, int budget);
+static int qlcnic_rx_poll(struct napi_struct *napi, int budget);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void qlcnic_poll_controller(struct net_device *netdev);
+#endif
+
+static void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
+static void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
+static void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter);
+static void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter);
+
+static void qlcnic_idc_debug_info(struct qlcnic_adapter *adapter, u8 encoding);
+static void qlcnic_clr_all_drv_state(struct qlcnic_adapter *adapter, u8);
+static int qlcnic_can_start_firmware(struct qlcnic_adapter *adapter);
+
+static irqreturn_t qlcnic_tmp_intr(int irq, void *data);
+static irqreturn_t qlcnic_intr(int irq, void *data);
+static irqreturn_t qlcnic_msi_intr(int irq, void *data);
+static irqreturn_t qlcnic_msix_intr(int irq, void *data);
+
+static struct net_device_stats *qlcnic_get_stats(struct net_device *netdev);
+static void qlcnic_restore_indev_addr(struct net_device *dev, unsigned long);
+static int qlcnic_start_firmware(struct qlcnic_adapter *);
+
+static void qlcnic_free_lb_filters_mem(struct qlcnic_adapter *adapter);
+static void qlcnic_dev_set_npar_ready(struct qlcnic_adapter *);
+static int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
+static int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
+static int qlcnicvf_start_firmware(struct qlcnic_adapter *);
+static void qlcnic_set_netdev_features(struct qlcnic_adapter *,
+                                struct qlcnic_esw_func_cfg *);
+static void qlcnic_vlan_rx_add(struct net_device *, u16);
+static void qlcnic_vlan_rx_del(struct net_device *, u16);
+
+/*  PCI Device ID Table  */
+#define ENTRY(device) \
+        {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, (device)), \
+        .class = PCI_CLASS_NETWORK_ETHERNET << 8, .class_mask = ~0}
+
+#define PCI_DEVICE_ID_QLOGIC_QLE824X  0x8020
+
+static DEFINE_PCI_DEVICE_TABLE(qlcnic_pci_tbl) = {
+        ENTRY(PCI_DEVICE_ID_QLOGIC_QLE824X),
+        {0,}
+};
+
+MODULE_DEVICE_TABLE(pci, qlcnic_pci_tbl);
+
+
+inline void
+qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_tx_ring *tx_ring)
+{
+        writel(tx_ring->producer, tx_ring->crb_cmd_producer);
+}
+
+static const u32 msi_tgt_status[8] = {
+        ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
+        ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
+        ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
+        ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
+};
+
+static const
+struct qlcnic_legacy_intr_set legacy_intr[] = QLCNIC_LEGACY_INTR_CONFIG;
+
+static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring)
+{
+        writel(0, sds_ring->crb_intr_mask);
+}
+
+static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring)
+{
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+
+        writel(0x1, sds_ring->crb_intr_mask);
+
+        if (!QLCNIC_IS_MSI_FAMILY(adapter))
+                writel(0xfbff, adapter->tgt_mask_reg);
+}
+
+static int
+qlcnic_alloc_sds_rings(struct qlcnic_recv_context *recv_ctx, int count)
+{
+        int size = sizeof(struct qlcnic_host_sds_ring) * count;
+
+        recv_ctx->sds_rings = kzalloc(size, GFP_KERNEL);
+
+        return recv_ctx->sds_rings == NULL;
+}
+
+static void
+qlcnic_free_sds_rings(struct qlcnic_recv_context *recv_ctx)
+{
+        if (recv_ctx->sds_rings != NULL)
+                kfree(recv_ctx->sds_rings);
+
+        recv_ctx->sds_rings = NULL;
+}
+
+static int
+qlcnic_napi_add(struct qlcnic_adapter *adapter, struct net_device *netdev)
+{
+        int ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        if (qlcnic_alloc_sds_rings(recv_ctx, adapter->max_sds_rings))
+                return -ENOMEM;
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+
+                if (ring == adapter->max_sds_rings - 1)
+                        netif_napi_add(netdev, &sds_ring->napi, qlcnic_poll,
+                                QLCNIC_NETDEV_WEIGHT/adapter->max_sds_rings);
+                else
+                        netif_napi_add(netdev, &sds_ring->napi,
+                                qlcnic_rx_poll, QLCNIC_NETDEV_WEIGHT*2);
+        }
+
+        return 0;
+}
+
+static void
+qlcnic_napi_del(struct qlcnic_adapter *adapter)
+{
+        int ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+                netif_napi_del(&sds_ring->napi);
+        }
+
+        qlcnic_free_sds_rings(adapter->recv_ctx);
+}
+
+static void
+qlcnic_napi_enable(struct qlcnic_adapter *adapter)
+{
+        int ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
+                return;
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+                napi_enable(&sds_ring->napi);
+                qlcnic_enable_int(sds_ring);
+        }
+}
+
+static void
+qlcnic_napi_disable(struct qlcnic_adapter *adapter)
+{
+        int ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
+                return;
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+                qlcnic_disable_int(sds_ring);
+                napi_synchronize(&sds_ring->napi);
+                napi_disable(&sds_ring->napi);
+        }
+}
+
+static void qlcnic_clear_stats(struct qlcnic_adapter *adapter)
+{
+        memset(&adapter->stats, 0, sizeof(adapter->stats));
+}
+
+static void qlcnic_set_msix_bit(struct pci_dev *pdev, int enable)
+{
+        u32 control;
+        int pos;
+
+        pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
+        if (pos) {
+                pci_read_config_dword(pdev, pos, &control);
+                if (enable)
+                        control |= PCI_MSIX_FLAGS_ENABLE;
+                else
+                        control = 0;
+                pci_write_config_dword(pdev, pos, control);
+        }
+}
+
+static void qlcnic_init_msix_entries(struct qlcnic_adapter *adapter, int count)
+{
+        int i;
+
+        for (i = 0; i < count; i++)
+                adapter->msix_entries[i].entry = i;
+}
+
+static int
+qlcnic_read_mac_addr(struct qlcnic_adapter *adapter)
+{
+        u8 mac_addr[ETH_ALEN];
+        struct net_device *netdev = adapter->netdev;
+        struct pci_dev *pdev = adapter->pdev;
+
+        if (qlcnic_get_mac_address(adapter, mac_addr) != 0)
+                return -EIO;
+
+        memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
+        memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
+        memcpy(adapter->mac_addr, netdev->dev_addr, netdev->addr_len);
+
+        /* set station address */
+
+        if (!is_valid_ether_addr(netdev->perm_addr))
+                dev_warn(&pdev->dev, "Bad MAC address %pM.\n",
+                                        netdev->dev_addr);
+
+        return 0;
+}
+
+static int qlcnic_set_mac(struct net_device *netdev, void *p)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct sockaddr *addr = p;
+
+        if ((adapter->flags & QLCNIC_MAC_OVERRIDE_DISABLED))
+                return -EOPNOTSUPP;
+
+        if (!is_valid_ether_addr(addr->sa_data))
+                return -EINVAL;
+
+        if (test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
+                netif_device_detach(netdev);
+                qlcnic_napi_disable(adapter);
+        }
+
+        memcpy(adapter->mac_addr, addr->sa_data, netdev->addr_len);
+        memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+        qlcnic_set_multi(adapter->netdev);
+
+        if (test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
+                netif_device_attach(netdev);
+                qlcnic_napi_enable(adapter);
+        }
+        return 0;
+}
+
+static const struct net_device_ops qlcnic_netdev_ops = {
+        .ndo_open          = qlcnic_open,
+        .ndo_stop          = qlcnic_close,
+        .ndo_start_xmit    = qlcnic_xmit_frame,
+        .ndo_get_stats     = qlcnic_get_stats,
+        .ndo_validate_addr = eth_validate_addr,
+        .ndo_set_multicast_list = qlcnic_set_multi,
+        .ndo_set_mac_address    = qlcnic_set_mac,
+        .ndo_change_mtu    = qlcnic_change_mtu,
+        .ndo_fix_features  = qlcnic_fix_features,
+        .ndo_set_features  = qlcnic_set_features,
+        .ndo_tx_timeout    = qlcnic_tx_timeout,
+        .ndo_vlan_rx_add_vid    = qlcnic_vlan_rx_add,
+        .ndo_vlan_rx_kill_vid   = qlcnic_vlan_rx_del,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+        .ndo_poll_controller = qlcnic_poll_controller,
+#endif
+};
+
+static struct qlcnic_nic_template qlcnic_ops = {
+        .config_bridged_mode = qlcnic_config_bridged_mode,
+        .config_led = qlcnic_config_led,
+        .start_firmware = qlcnic_start_firmware
+};
+
+static struct qlcnic_nic_template qlcnic_vf_ops = {
+        .config_bridged_mode = qlcnicvf_config_bridged_mode,
+        .config_led = qlcnicvf_config_led,
+        .start_firmware = qlcnicvf_start_firmware
+};
+
+static int qlcnic_enable_msix(struct qlcnic_adapter *adapter, u32 num_msix)
+{
+        struct pci_dev *pdev = adapter->pdev;
+        int err = -1;
+
+        adapter->max_sds_rings = 1;
+        adapter->flags &= ~(QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED);
+        qlcnic_set_msix_bit(pdev, 0);
+
+        if (adapter->msix_supported) {
+ enable_msix:
+                qlcnic_init_msix_entries(adapter, num_msix);
+                err = pci_enable_msix(pdev, adapter->msix_entries, num_msix);
+                if (err == 0) {
+                        adapter->flags |= QLCNIC_MSIX_ENABLED;
+                        qlcnic_set_msix_bit(pdev, 1);
+
+                        adapter->max_sds_rings = num_msix;
+
+                        dev_info(&pdev->dev, "using msi-x interrupts\n");
+                        return err;
+                }
+                if (err > 0) {
+                        num_msix = rounddown_pow_of_two(err);
+                        if (num_msix)
+                                goto enable_msix;
+                }
+        }
+        return err;
+}
+
+
+static void qlcnic_enable_msi_legacy(struct qlcnic_adapter *adapter)
+{
+        const struct qlcnic_legacy_intr_set *legacy_intrp;
+        struct pci_dev *pdev = adapter->pdev;
+
+        if (use_msi && !pci_enable_msi(pdev)) {
+                adapter->flags |= QLCNIC_MSI_ENABLED;
+                adapter->tgt_status_reg = qlcnic_get_ioaddr(adapter,
+                                msi_tgt_status[adapter->ahw->pci_func]);
+                dev_info(&pdev->dev, "using msi interrupts\n");
+                adapter->msix_entries[0].vector = pdev->irq;
+                return;
+        }
+
+        legacy_intrp = &legacy_intr[adapter->ahw->pci_func];
+
+        adapter->int_vec_bit = legacy_intrp->int_vec_bit;
+        adapter->tgt_status_reg = qlcnic_get_ioaddr(adapter,
+                        legacy_intrp->tgt_status_reg);
+        adapter->tgt_mask_reg = qlcnic_get_ioaddr(adapter,
+                        legacy_intrp->tgt_mask_reg);
+        adapter->isr_int_vec = qlcnic_get_ioaddr(adapter, ISR_INT_VECTOR);
+
+        adapter->crb_int_state_reg = qlcnic_get_ioaddr(adapter,
+                        ISR_INT_STATE_REG);
+        dev_info(&pdev->dev, "using legacy interrupts\n");
+        adapter->msix_entries[0].vector = pdev->irq;
+}
+
+static void
+qlcnic_setup_intr(struct qlcnic_adapter *adapter)
+{
+        int num_msix;
+
+        if (adapter->msix_supported) {
+                num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
+                                QLCNIC_DEF_NUM_STS_DESC_RINGS));
+        } else
+                num_msix = 1;
+
+        if (!qlcnic_enable_msix(adapter, num_msix))
+                return;
+
+        qlcnic_enable_msi_legacy(adapter);
+}
+
+static void
+qlcnic_teardown_intr(struct qlcnic_adapter *adapter)
+{
+        if (adapter->flags & QLCNIC_MSIX_ENABLED)
+                pci_disable_msix(adapter->pdev);
+        if (adapter->flags & QLCNIC_MSI_ENABLED)
+                pci_disable_msi(adapter->pdev);
+}
+
+static void
+qlcnic_cleanup_pci_map(struct qlcnic_adapter *adapter)
+{
+        if (adapter->ahw->pci_base0 != NULL)
+                iounmap(adapter->ahw->pci_base0);
+}
+
+static int
+qlcnic_init_pci_info(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_pci_info *pci_info;
+        int i, ret = 0;
+        u8 pfn;
+
+        pci_info = kcalloc(QLCNIC_MAX_PCI_FUNC, sizeof(*pci_info), GFP_KERNEL);
+        if (!pci_info)
+                return -ENOMEM;
+
+        adapter->npars = kzalloc(sizeof(struct qlcnic_npar_info) *
+                                QLCNIC_MAX_PCI_FUNC, GFP_KERNEL);
+        if (!adapter->npars) {
+                ret = -ENOMEM;
+                goto err_pci_info;
+        }
+
+        adapter->eswitch = kzalloc(sizeof(struct qlcnic_eswitch) *
+                                QLCNIC_NIU_MAX_XG_PORTS, GFP_KERNEL);
+        if (!adapter->eswitch) {
+                ret = -ENOMEM;
+                goto err_npars;
+        }
+
+        ret = qlcnic_get_pci_info(adapter, pci_info);
+        if (ret)
+                goto err_eswitch;
+
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
+                pfn = pci_info[i].id;
+                if (pfn > QLCNIC_MAX_PCI_FUNC) {
+                        ret = QL_STATUS_INVALID_PARAM;
+                        goto err_eswitch;
+                }
+                adapter->npars[pfn].active = (u8)pci_info[i].active;
+                adapter->npars[pfn].type = (u8)pci_info[i].type;
+                adapter->npars[pfn].phy_port = (u8)pci_info[i].default_port;
+                adapter->npars[pfn].min_bw = pci_info[i].tx_min_bw;
+                adapter->npars[pfn].max_bw = pci_info[i].tx_max_bw;
+        }
+
+        for (i = 0; i < QLCNIC_NIU_MAX_XG_PORTS; i++)
+                adapter->eswitch[i].flags |= QLCNIC_SWITCH_ENABLE;
+
+        kfree(pci_info);
+        return 0;
+
+err_eswitch:
+        kfree(adapter->eswitch);
+        adapter->eswitch = NULL;
+err_npars:
+        kfree(adapter->npars);
+        adapter->npars = NULL;
+err_pci_info:
+        kfree(pci_info);
+
+        return ret;
+}
+
+static int
+qlcnic_set_function_modes(struct qlcnic_adapter *adapter)
+{
+        u8 id;
+        u32 ref_count;
+        int i, ret = 1;
+        u32 data = QLCNIC_MGMT_FUNC;
+        void __iomem *priv_op = adapter->ahw->pci_base0 + QLCNIC_DRV_OP_MODE;
+
+        /* If other drivers are not in use set their privilege level */
+        ref_count = QLCRD32(adapter, QLCNIC_CRB_DRV_ACTIVE);
+        ret = qlcnic_api_lock(adapter);
+        if (ret)
+                goto err_lock;
+
+        if (qlcnic_config_npars) {
+                for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
+                        id = i;
+                        if (adapter->npars[i].type != QLCNIC_TYPE_NIC ||
+                                id == adapter->ahw->pci_func)
+                                continue;
+                        data |= (qlcnic_config_npars &
+                                        QLC_DEV_SET_DRV(0xf, id));
+                }
+        } else {
+                data = readl(priv_op);
+                data = (data & ~QLC_DEV_SET_DRV(0xf, adapter->ahw->pci_func)) |
+                        (QLC_DEV_SET_DRV(QLCNIC_MGMT_FUNC,
+                        adapter->ahw->pci_func));
+        }
+        writel(data, priv_op);
+        qlcnic_api_unlock(adapter);
+err_lock:
+        return ret;
+}
+
+static void
+qlcnic_check_vf(struct qlcnic_adapter *adapter)
+{
+        void __iomem *msix_base_addr;
+        void __iomem *priv_op;
+        u32 func;
+        u32 msix_base;
+        u32 op_mode, priv_level;
+
+        /* Determine FW API version */
+        adapter->fw_hal_version = readl(adapter->ahw->pci_base0 +
+                                        QLCNIC_FW_API);
+
+        /* Find PCI function number */
+        pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
+        msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
+        msix_base = readl(msix_base_addr);
+        func = (func - msix_base)/QLCNIC_MSIX_TBL_PGSIZE;
+        adapter->ahw->pci_func = func;
+
+        /* Determine function privilege level */
+        priv_op = adapter->ahw->pci_base0 + QLCNIC_DRV_OP_MODE;
+        op_mode = readl(priv_op);
+        if (op_mode == QLC_DEV_DRV_DEFAULT)
+                priv_level = QLCNIC_MGMT_FUNC;
+        else
+                priv_level = QLC_DEV_GET_DRV(op_mode, adapter->ahw->pci_func);
+
+        if (priv_level == QLCNIC_NON_PRIV_FUNC) {
+                adapter->op_mode = QLCNIC_NON_PRIV_FUNC;
+                dev_info(&adapter->pdev->dev,
+                        "HAL Version: %d Non Privileged function\n",
+                        adapter->fw_hal_version);
+                adapter->nic_ops = &qlcnic_vf_ops;
+        } else
+                adapter->nic_ops = &qlcnic_ops;
+}
+
+static int
+qlcnic_setup_pci_map(struct qlcnic_adapter *adapter)
+{
+        void __iomem *mem_ptr0 = NULL;
+        resource_size_t mem_base;
+        unsigned long mem_len, pci_len0 = 0;
+
+        struct pci_dev *pdev = adapter->pdev;
+
+        /* remap phys address */
+        mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */
+        mem_len = pci_resource_len(pdev, 0);
+
+        if (mem_len == QLCNIC_PCI_2MB_SIZE) {
+
+                mem_ptr0 = pci_ioremap_bar(pdev, 0);
+                if (mem_ptr0 == NULL) {
+                        dev_err(&pdev->dev, "failed to map PCI bar 0\n");
+                        return -EIO;
+                }
+                pci_len0 = mem_len;
+        } else {
+                return -EIO;
+        }
+
+        dev_info(&pdev->dev, "%dMB memory map\n", (int)(mem_len>>20));
+
+        adapter->ahw->pci_base0 = mem_ptr0;
+        adapter->ahw->pci_len0 = pci_len0;
+
+        qlcnic_check_vf(adapter);
+
+        adapter->ahw->ocm_win_crb = qlcnic_get_ioaddr(adapter,
+                QLCNIC_PCIX_PS_REG(PCIX_OCM_WINDOW_REG(
+                        adapter->ahw->pci_func)));
+
+        return 0;
+}
+
+static void get_brd_name(struct qlcnic_adapter *adapter, char *name)
+{
+        struct pci_dev *pdev = adapter->pdev;
+        int i, found = 0;
+
+        for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
+                if (qlcnic_boards[i].vendor == pdev->vendor &&
+                        qlcnic_boards[i].device == pdev->device &&
+                        qlcnic_boards[i].sub_vendor == pdev->subsystem_vendor &&
+                        qlcnic_boards[i].sub_device == pdev->subsystem_device) {
+                                sprintf(name, "%pM: %s" ,
+                                        adapter->mac_addr,
+                                        qlcnic_boards[i].short_name);
+                                found = 1;
+                                break;
+                }
+
+        }
+
+        if (!found)
+                sprintf(name, "%pM Gigabit Ethernet", adapter->mac_addr);
+}
+
+static void
+qlcnic_check_options(struct qlcnic_adapter *adapter)
+{
+        u32 fw_major, fw_minor, fw_build;
+        struct pci_dev *pdev = adapter->pdev;
+
+        fw_major = QLCRD32(adapter, QLCNIC_FW_VERSION_MAJOR);
+        fw_minor = QLCRD32(adapter, QLCNIC_FW_VERSION_MINOR);
+        fw_build = QLCRD32(adapter, QLCNIC_FW_VERSION_SUB);
+
+        adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
+
+        dev_info(&pdev->dev, "firmware v%d.%d.%d\n",
+                        fw_major, fw_minor, fw_build);
+        if (adapter->ahw->port_type == QLCNIC_XGBE) {
+                if (adapter->flags & QLCNIC_ESWITCH_ENABLED) {
+                        adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_VF;
+                        adapter->max_rxd = MAX_RCV_DESCRIPTORS_VF;
+                } else {
+                        adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
+                        adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
+                }
+
+                adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
+                adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
+
+        } else if (adapter->ahw->port_type == QLCNIC_GBE) {
+                adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
+                adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
+                adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
+                adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
+        }
+
+        adapter->msix_supported = !!use_msi_x;
+
+        adapter->num_txd = MAX_CMD_DESCRIPTORS;
+
+        adapter->max_rds_rings = MAX_RDS_RINGS;
+}
+
+static int
+qlcnic_initialize_nic(struct qlcnic_adapter *adapter)
+{
+        int err;
+        struct qlcnic_info nic_info;
+
+        err = qlcnic_get_nic_info(adapter, &nic_info, adapter->ahw->pci_func);
+        if (err)
+                return err;
+
+        adapter->physical_port = (u8)nic_info.phys_port;
+        adapter->switch_mode = nic_info.switch_mode;
+        adapter->max_tx_ques = nic_info.max_tx_ques;
+        adapter->max_rx_ques = nic_info.max_rx_ques;
+        adapter->capabilities = nic_info.capabilities;
+        adapter->max_mac_filters = nic_info.max_mac_filters;
+        adapter->max_mtu = nic_info.max_mtu;
+
+        if (adapter->capabilities & BIT_6)
+                adapter->flags |= QLCNIC_ESWITCH_ENABLED;
+        else
+                adapter->flags &= ~QLCNIC_ESWITCH_ENABLED;
+
+        return err;
+}
+
+static void
+qlcnic_set_vlan_config(struct qlcnic_adapter *adapter,
+                struct qlcnic_esw_func_cfg *esw_cfg)
+{
+        if (esw_cfg->discard_tagged)
+                adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
+        else
+                adapter->flags |= QLCNIC_TAGGING_ENABLED;
+
+        if (esw_cfg->vlan_id)
+                adapter->pvid = esw_cfg->vlan_id;
+        else
+                adapter->pvid = 0;
+}
+
+static void
+qlcnic_vlan_rx_add(struct net_device *netdev, u16 vid)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        set_bit(vid, adapter->vlans);
+}
+
+static void
+qlcnic_vlan_rx_del(struct net_device *netdev, u16 vid)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        qlcnic_restore_indev_addr(netdev, NETDEV_DOWN);
+        clear_bit(vid, adapter->vlans);
+}
+
+static void
+qlcnic_set_eswitch_port_features(struct qlcnic_adapter *adapter,
+                struct qlcnic_esw_func_cfg *esw_cfg)
+{
+        adapter->flags &= ~(QLCNIC_MACSPOOF | QLCNIC_MAC_OVERRIDE_DISABLED |
+                                QLCNIC_PROMISC_DISABLED);
+
+        if (esw_cfg->mac_anti_spoof)
+                adapter->flags |= QLCNIC_MACSPOOF;
+
+        if (!esw_cfg->mac_override)
+                adapter->flags |= QLCNIC_MAC_OVERRIDE_DISABLED;
+
+        if (!esw_cfg->promisc_mode)
+                adapter->flags |= QLCNIC_PROMISC_DISABLED;
+
+        qlcnic_set_netdev_features(adapter, esw_cfg);
+}
+
+static int
+qlcnic_set_eswitch_port_config(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_esw_func_cfg esw_cfg;
+
+        if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED))
+                return 0;
+
+        esw_cfg.pci_func = adapter->ahw->pci_func;
+        if (qlcnic_get_eswitch_port_config(adapter, &esw_cfg))
+                        return -EIO;
+        qlcnic_set_vlan_config(adapter, &esw_cfg);
+        qlcnic_set_eswitch_port_features(adapter, &esw_cfg);
+
+        return 0;
+}
+
+static void
+qlcnic_set_netdev_features(struct qlcnic_adapter *adapter,
+                struct qlcnic_esw_func_cfg *esw_cfg)
+{
+        struct net_device *netdev = adapter->netdev;
+        unsigned long features, vlan_features;
+
+        features = (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+                        NETIF_F_IPV6_CSUM | NETIF_F_GRO);
+        vlan_features = (NETIF_F_SG | NETIF_F_IP_CSUM |
+                        NETIF_F_IPV6_CSUM | NETIF_F_HW_VLAN_FILTER);
+
+        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_TSO) {
+                features |= (NETIF_F_TSO | NETIF_F_TSO6);
+                vlan_features |= (NETIF_F_TSO | NETIF_F_TSO6);
+        }
+
+        if (netdev->features & NETIF_F_LRO)
+                features |= NETIF_F_LRO;
+
+        if (esw_cfg->offload_flags & BIT_0) {
+                netdev->features |= features;
+                if (!(esw_cfg->offload_flags & BIT_1))
+                        netdev->features &= ~NETIF_F_TSO;
+                if (!(esw_cfg->offload_flags & BIT_2))
+                        netdev->features &= ~NETIF_F_TSO6;
+        } else {
+                netdev->features &= ~features;
+        }
+
+        netdev->vlan_features = (features & vlan_features);
+}
+
+static int
+qlcnic_check_eswitch_mode(struct qlcnic_adapter *adapter)
+{
+        void __iomem *priv_op;
+        u32 op_mode, priv_level;
+        int err = 0;
+
+        err = qlcnic_initialize_nic(adapter);
+        if (err)
+                return err;
+
+        if (adapter->flags & QLCNIC_ADAPTER_INITIALIZED)
+                return 0;
+
+        priv_op = adapter->ahw->pci_base0 + QLCNIC_DRV_OP_MODE;
+        op_mode = readl(priv_op);
+        priv_level = QLC_DEV_GET_DRV(op_mode, adapter->ahw->pci_func);
+
+        if (op_mode == QLC_DEV_DRV_DEFAULT)
+                priv_level = QLCNIC_MGMT_FUNC;
+        else
+                priv_level = QLC_DEV_GET_DRV(op_mode, adapter->ahw->pci_func);
+
+        if (adapter->flags & QLCNIC_ESWITCH_ENABLED) {
+                if (priv_level == QLCNIC_MGMT_FUNC) {
+                        adapter->op_mode = QLCNIC_MGMT_FUNC;
+                        err = qlcnic_init_pci_info(adapter);
+                        if (err)
+                                return err;
+                        /* Set privilege level for other functions */
+                        qlcnic_set_function_modes(adapter);
+                        dev_info(&adapter->pdev->dev,
+                                "HAL Version: %d, Management function\n",
+                                adapter->fw_hal_version);
+                } else if (priv_level == QLCNIC_PRIV_FUNC) {
+                        adapter->op_mode = QLCNIC_PRIV_FUNC;
+                        dev_info(&adapter->pdev->dev,
+                                "HAL Version: %d, Privileged function\n",
+                                adapter->fw_hal_version);
+                }
+        }
+
+        adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
+
+        return err;
+}
+
+static int
+qlcnic_set_default_offload_settings(struct qlcnic_adapter *adapter)
+{
+        struct qlcnic_esw_func_cfg esw_cfg;
+        struct qlcnic_npar_info *npar;
+        u8 i;
+
+        if (adapter->need_fw_reset)
+                return 0;
+
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
+                if (adapter->npars[i].type != QLCNIC_TYPE_NIC)
+                        continue;
+                memset(&esw_cfg, 0, sizeof(struct qlcnic_esw_func_cfg));
+                esw_cfg.pci_func = i;
+                esw_cfg.offload_flags = BIT_0;
+                esw_cfg.mac_override = BIT_0;
+                esw_cfg.promisc_mode = BIT_0;
+                if (adapter->capabilities  & QLCNIC_FW_CAPABILITY_TSO)
+                        esw_cfg.offload_flags |= (BIT_1 | BIT_2);
+                if (qlcnic_config_switch_port(adapter, &esw_cfg))
+                        return -EIO;
+                npar = &adapter->npars[i];
+                npar->pvid = esw_cfg.vlan_id;
+                npar->mac_override = esw_cfg.mac_override;
+                npar->mac_anti_spoof = esw_cfg.mac_anti_spoof;
+                npar->discard_tagged = esw_cfg.discard_tagged;
+                npar->promisc_mode = esw_cfg.promisc_mode;
+                npar->offload_flags = esw_cfg.offload_flags;
+        }
+
+        return 0;
+}
+
+static int
+qlcnic_reset_eswitch_config(struct qlcnic_adapter *adapter,
+                        struct qlcnic_npar_info *npar, int pci_func)
+{
+        struct qlcnic_esw_func_cfg esw_cfg;
+        esw_cfg.op_mode = QLCNIC_PORT_DEFAULTS;
+        esw_cfg.pci_func = pci_func;
+        esw_cfg.vlan_id = npar->pvid;
+        esw_cfg.mac_override = npar->mac_override;
+        esw_cfg.discard_tagged = npar->discard_tagged;
+        esw_cfg.mac_anti_spoof = npar->mac_anti_spoof;
+        esw_cfg.offload_flags = npar->offload_flags;
+        esw_cfg.promisc_mode = npar->promisc_mode;
+        if (qlcnic_config_switch_port(adapter, &esw_cfg))
+                return -EIO;
+
+        esw_cfg.op_mode = QLCNIC_ADD_VLAN;
+        if (qlcnic_config_switch_port(adapter, &esw_cfg))
+                return -EIO;
+
+        return 0;
+}
+
+static int
+qlcnic_reset_npar_config(struct qlcnic_adapter *adapter)
+{
+        int i, err;
+        struct qlcnic_npar_info *npar;
+        struct qlcnic_info nic_info;
+
+        if (!adapter->need_fw_reset)
+                return 0;
+
+        /* Set the NPAR config data after FW reset */
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
+                npar = &adapter->npars[i];
+                if (npar->type != QLCNIC_TYPE_NIC)
+                        continue;
+                err = qlcnic_get_nic_info(adapter, &nic_info, i);
+                if (err)
+                        return err;
+                nic_info.min_tx_bw = npar->min_bw;
+                nic_info.max_tx_bw = npar->max_bw;
+                err = qlcnic_set_nic_info(adapter, &nic_info);
+                if (err)
+                        return err;
+
+                if (npar->enable_pm) {
+                        err = qlcnic_config_port_mirroring(adapter,
+                                                        npar->dest_npar, 1, i);
+                        if (err)
+                                return err;
+                }
+                err = qlcnic_reset_eswitch_config(adapter, npar, i);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int qlcnic_check_npar_opertional(struct qlcnic_adapter *adapter)
+{
+        u8 npar_opt_timeo = QLCNIC_DEV_NPAR_OPER_TIMEO;
+        u32 npar_state;
+
+        if (adapter->op_mode == QLCNIC_MGMT_FUNC)
+                return 0;
+
+        npar_state = QLCRD32(adapter, QLCNIC_CRB_DEV_NPAR_STATE);
+        while (npar_state != QLCNIC_DEV_NPAR_OPER && --npar_opt_timeo) {
+                msleep(1000);
+                npar_state = QLCRD32(adapter, QLCNIC_CRB_DEV_NPAR_STATE);
+        }
+        if (!npar_opt_timeo) {
+                dev_err(&adapter->pdev->dev,
+                        "Waiting for NPAR state to opertional timeout\n");
+                return -EIO;
+        }
+        return 0;
+}
+
+static int
+qlcnic_set_mgmt_operations(struct qlcnic_adapter *adapter)
+{
+        int err;
+
+        if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED) ||
+                    adapter->op_mode != QLCNIC_MGMT_FUNC)
+                return 0;
+
+        err = qlcnic_set_default_offload_settings(adapter);
+        if (err)
+                return err;
+
+        err = qlcnic_reset_npar_config(adapter);
+        if (err)
+                return err;
+
+        qlcnic_dev_set_npar_ready(adapter);
+
+        return err;
+}
+
+static int
+qlcnic_start_firmware(struct qlcnic_adapter *adapter)
+{
+        int err;
+
+        err = qlcnic_can_start_firmware(adapter);
+        if (err < 0)
+                return err;
+        else if (!err)
+                goto check_fw_status;
+
+        if (load_fw_file)
+                qlcnic_request_firmware(adapter);
+        else {
+                err = qlcnic_check_flash_fw_ver(adapter);
+                if (err)
+                        goto err_out;
+
+                adapter->fw_type = QLCNIC_FLASH_ROMIMAGE;
+        }
+
+        err = qlcnic_need_fw_reset(adapter);
+        if (err == 0)
+                goto check_fw_status;
+
+        err = qlcnic_pinit_from_rom(adapter);
+        if (err)
+                goto err_out;
+
+        err = qlcnic_load_firmware(adapter);
+        if (err)
+                goto err_out;
+
+        qlcnic_release_firmware(adapter);
+        QLCWR32(adapter, CRB_DRIVER_VERSION, QLCNIC_DRIVER_VERSION);
+
+check_fw_status:
+        err = qlcnic_check_fw_status(adapter);
+        if (err)
+                goto err_out;
+
+        QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_READY);
+        qlcnic_idc_debug_info(adapter, 1);
+
+        err = qlcnic_check_eswitch_mode(adapter);
+        if (err) {
+                dev_err(&adapter->pdev->dev,
+                        "Memory allocation failed for eswitch\n");
+                goto err_out;
+        }
+        err = qlcnic_set_mgmt_operations(adapter);
+        if (err)
+                goto err_out;
+
+        qlcnic_check_options(adapter);
+        adapter->need_fw_reset = 0;
+
+        qlcnic_release_firmware(adapter);
+        return 0;
+
+err_out:
+        QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_FAILED);
+        dev_err(&adapter->pdev->dev, "Device state set to failed\n");
+
+        qlcnic_release_firmware(adapter);
+        return err;
+}
+
+static int
+qlcnic_request_irq(struct qlcnic_adapter *adapter)
+{
+        irq_handler_t handler;
+        struct qlcnic_host_sds_ring *sds_ring;
+        int err, ring;
+
+        unsigned long flags = 0;
+        struct net_device *netdev = adapter->netdev;
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        if (adapter->diag_test == QLCNIC_INTERRUPT_TEST) {
+                handler = qlcnic_tmp_intr;
+                if (!QLCNIC_IS_MSI_FAMILY(adapter))
+                        flags |= IRQF_SHARED;
+
+        } else {
+                if (adapter->flags & QLCNIC_MSIX_ENABLED)
+                        handler = qlcnic_msix_intr;
+                else if (adapter->flags & QLCNIC_MSI_ENABLED)
+                        handler = qlcnic_msi_intr;
+                else {
+                        flags |= IRQF_SHARED;
+                        handler = qlcnic_intr;
+                }
+        }
+        adapter->irq = netdev->irq;
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+                sprintf(sds_ring->name, "%s[%d]", netdev->name, ring);
+                err = request_irq(sds_ring->irq, handler,
+                                  flags, sds_ring->name, sds_ring);
+                if (err)
+                        return err;
+        }
+
+        return 0;
+}
+
+static void
+qlcnic_free_irq(struct qlcnic_adapter *adapter)
+{
+        int ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+                free_irq(sds_ring->irq, sds_ring);
+        }
+}
+
+static int
+__qlcnic_up(struct qlcnic_adapter *adapter, struct net_device *netdev)
+{
+        int ring;
+        struct qlcnic_host_rds_ring *rds_ring;
+
+        if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
+                return -EIO;
+
+        if (test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                return 0;
+        if (qlcnic_set_eswitch_port_config(adapter))
+                return -EIO;
+
+        if (qlcnic_fw_create_ctx(adapter))
+                return -EIO;
+
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &adapter->recv_ctx->rds_rings[ring];
+                qlcnic_post_rx_buffers(adapter, rds_ring);
+        }
+
+        qlcnic_set_multi(netdev);
+        qlcnic_fw_cmd_set_mtu(adapter, netdev->mtu);
+
+        adapter->ahw->linkup = 0;
+
+        if (adapter->max_sds_rings > 1)
+                qlcnic_config_rss(adapter, 1);
+
+        qlcnic_config_intr_coalesce(adapter);
+
+        if (netdev->features & NETIF_F_LRO)
+                qlcnic_config_hw_lro(adapter, QLCNIC_LRO_ENABLED);
+
+        qlcnic_napi_enable(adapter);
+
+        qlcnic_linkevent_request(adapter, 1);
+
+        adapter->reset_context = 0;
+        set_bit(__QLCNIC_DEV_UP, &adapter->state);
+        return 0;
+}
+
+/* Usage: During resume and firmware recovery module.*/
+
+static int
+qlcnic_up(struct qlcnic_adapter *adapter, struct net_device *netdev)
+{
+        int err = 0;
+
+        rtnl_lock();
+        if (netif_running(netdev))
+                err = __qlcnic_up(adapter, netdev);
+        rtnl_unlock();
+
+        return err;
+}
+
+static void
+__qlcnic_down(struct qlcnic_adapter *adapter, struct net_device *netdev)
+{
+        if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
+                return;
+
+        if (!test_and_clear_bit(__QLCNIC_DEV_UP, &adapter->state))
+                return;
+
+        smp_mb();
+        spin_lock(&adapter->tx_clean_lock);
+        netif_carrier_off(netdev);
+        netif_tx_disable(netdev);
+
+        qlcnic_free_mac_list(adapter);
+
+        if (adapter->fhash.fnum)
+                qlcnic_delete_lb_filters(adapter);
+
+        qlcnic_nic_set_promisc(adapter, QLCNIC_NIU_NON_PROMISC_MODE);
+
+        qlcnic_napi_disable(adapter);
+
+        qlcnic_fw_destroy_ctx(adapter);
+
+        qlcnic_reset_rx_buffers_list(adapter);
+        qlcnic_release_tx_buffers(adapter);
+        spin_unlock(&adapter->tx_clean_lock);
+}
+
+/* Usage: During suspend and firmware recovery module */
+
+static void
+qlcnic_down(struct qlcnic_adapter *adapter, struct net_device *netdev)
+{
+        rtnl_lock();
+        if (netif_running(netdev))
+                __qlcnic_down(adapter, netdev);
+        rtnl_unlock();
+
+}
+
+static int
+qlcnic_attach(struct qlcnic_adapter *adapter)
+{
+        struct net_device *netdev = adapter->netdev;
+        struct pci_dev *pdev = adapter->pdev;
+        int err;
+
+        if (adapter->is_up == QLCNIC_ADAPTER_UP_MAGIC)
+                return 0;
+
+        err = qlcnic_napi_add(adapter, netdev);
+        if (err)
+                return err;
+
+        err = qlcnic_alloc_sw_resources(adapter);
+        if (err) {
+                dev_err(&pdev->dev, "Error in setting sw resources\n");
+                goto err_out_napi_del;
+        }
+
+        err = qlcnic_alloc_hw_resources(adapter);
+        if (err) {
+                dev_err(&pdev->dev, "Error in setting hw resources\n");
+                goto err_out_free_sw;
+        }
+
+        err = qlcnic_request_irq(adapter);
+        if (err) {
+                dev_err(&pdev->dev, "failed to setup interrupt\n");
+                goto err_out_free_hw;
+        }
+
+        qlcnic_create_sysfs_entries(adapter);
+
+        adapter->is_up = QLCNIC_ADAPTER_UP_MAGIC;
+        return 0;
+
+err_out_free_hw:
+        qlcnic_free_hw_resources(adapter);
+err_out_free_sw:
+        qlcnic_free_sw_resources(adapter);
+err_out_napi_del:
+        qlcnic_napi_del(adapter);
+        return err;
+}
+
+static void
+qlcnic_detach(struct qlcnic_adapter *adapter)
+{
+        if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
+                return;
+
+        qlcnic_remove_sysfs_entries(adapter);
+
+        qlcnic_free_hw_resources(adapter);
+        qlcnic_release_rx_buffers(adapter);
+        qlcnic_free_irq(adapter);
+        qlcnic_napi_del(adapter);
+        qlcnic_free_sw_resources(adapter);
+
+        adapter->is_up = 0;
+}
+
+void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct qlcnic_host_sds_ring *sds_ring;
+        int ring;
+
+        clear_bit(__QLCNIC_DEV_UP, &adapter->state);
+        if (adapter->diag_test == QLCNIC_INTERRUPT_TEST) {
+                for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                        sds_ring = &adapter->recv_ctx->sds_rings[ring];
+                        qlcnic_disable_int(sds_ring);
+                }
+        }
+
+        qlcnic_fw_destroy_ctx(adapter);
+
+        qlcnic_detach(adapter);
+
+        adapter->diag_test = 0;
+        adapter->max_sds_rings = max_sds_rings;
+
+        if (qlcnic_attach(adapter))
+                goto out;
+
+        if (netif_running(netdev))
+                __qlcnic_up(adapter, netdev);
+out:
+        netif_device_attach(netdev);
+}
+
+static int qlcnic_alloc_adapter_resources(struct qlcnic_adapter *adapter)
+{
+        int err = 0;
+        adapter->ahw = kzalloc(sizeof(struct qlcnic_hardware_context),
+                                GFP_KERNEL);
+        if (!adapter->ahw) {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to allocate recv ctx resources for adapter\n");
+                err = -ENOMEM;
+                goto err_out;
+        }
+        adapter->recv_ctx = kzalloc(sizeof(struct qlcnic_recv_context),
+                                GFP_KERNEL);
+        if (!adapter->recv_ctx) {
+                dev_err(&adapter->pdev->dev,
+                        "Failed to allocate recv ctx resources for adapter\n");
+                kfree(adapter->ahw);
+                adapter->ahw = NULL;
+                err = -ENOMEM;
+                goto err_out;
+        }
+        /* Initialize interrupt coalesce parameters */
+        adapter->ahw->coal.flag = QLCNIC_INTR_DEFAULT;
+        adapter->ahw->coal.rx_time_us = QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US;
+        adapter->ahw->coal.rx_packets = QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS;
+err_out:
+        return err;
+}
+
+static void qlcnic_free_adapter_resources(struct qlcnic_adapter *adapter)
+{
+        kfree(adapter->recv_ctx);
+        adapter->recv_ctx = NULL;
+
+        if (adapter->ahw->fw_dump.tmpl_hdr) {
+                vfree(adapter->ahw->fw_dump.tmpl_hdr);
+                adapter->ahw->fw_dump.tmpl_hdr = NULL;
+        }
+        kfree(adapter->ahw);
+        adapter->ahw = NULL;
+}
+
+int qlcnic_diag_alloc_res(struct net_device *netdev, int test)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_host_rds_ring *rds_ring;
+        int ring;
+        int ret;
+
+        netif_device_detach(netdev);
+
+        if (netif_running(netdev))
+                __qlcnic_down(adapter, netdev);
+
+        qlcnic_detach(adapter);
+
+        adapter->max_sds_rings = 1;
+        adapter->diag_test = test;
+
+        ret = qlcnic_attach(adapter);
+        if (ret) {
+                netif_device_attach(netdev);
+                return ret;
+        }
+
+        ret = qlcnic_fw_create_ctx(adapter);
+        if (ret) {
+                qlcnic_detach(adapter);
+                netif_device_attach(netdev);
+                return ret;
+        }
+
+        for (ring = 0; ring < adapter->max_rds_rings; ring++) {
+                rds_ring = &adapter->recv_ctx->rds_rings[ring];
+                qlcnic_post_rx_buffers(adapter, rds_ring);
+        }
+
+        if (adapter->diag_test == QLCNIC_INTERRUPT_TEST) {
+                for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                        sds_ring = &adapter->recv_ctx->sds_rings[ring];
+                        qlcnic_enable_int(sds_ring);
+                }
+        }
+
+        if (adapter->diag_test == QLCNIC_LOOPBACK_TEST) {
+                adapter->ahw->loopback_state = 0;
+                qlcnic_linkevent_request(adapter, 1);
+        }
+
+        set_bit(__QLCNIC_DEV_UP, &adapter->state);
+
+        return 0;
+}
+
+/* Reset context in hardware only */
+static int
+qlcnic_reset_hw_context(struct qlcnic_adapter *adapter)
+{
+        struct net_device *netdev = adapter->netdev;
+
+        if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                return -EBUSY;
+
+        netif_device_detach(netdev);
+
+        qlcnic_down(adapter, netdev);
+
+        qlcnic_up(adapter, netdev);
+
+        netif_device_attach(netdev);
+
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+        return 0;
+}
+
+int
+qlcnic_reset_context(struct qlcnic_adapter *adapter)
+{
+        int err = 0;
+        struct net_device *netdev = adapter->netdev;
+
+        if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                return -EBUSY;
+
+        if (adapter->is_up == QLCNIC_ADAPTER_UP_MAGIC) {
+
+                netif_device_detach(netdev);
+
+                if (netif_running(netdev))
+                        __qlcnic_down(adapter, netdev);
+
+                qlcnic_detach(adapter);
+
+                if (netif_running(netdev)) {
+                        err = qlcnic_attach(adapter);
+                        if (!err)
+                                __qlcnic_up(adapter, netdev);
+                }
+
+                netif_device_attach(netdev);
+        }
+
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+        return err;
+}
+
+static int
+qlcnic_setup_netdev(struct qlcnic_adapter *adapter,
+                struct net_device *netdev, u8 pci_using_dac)
+{
+        int err;
+        struct pci_dev *pdev = adapter->pdev;
+
+        adapter->mc_enabled = 0;
+        adapter->max_mc_count = 38;
+
+        netdev->netdev_ops         = &qlcnic_netdev_ops;
+        netdev->watchdog_timeo     = 5*HZ;
+
+        qlcnic_change_mtu(netdev, netdev->mtu);
+
+        SET_ETHTOOL_OPS(netdev, &qlcnic_ethtool_ops);
+
+        netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
+                NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
+
+        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_TSO)
+                netdev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
+        if (pci_using_dac)
+                netdev->hw_features |= NETIF_F_HIGHDMA;
+
+        netdev->vlan_features = netdev->hw_features;
+
+        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_FVLANTX)
+                netdev->hw_features |= NETIF_F_HW_VLAN_TX;
+        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_HW_LRO)
+                netdev->hw_features |= NETIF_F_LRO;
+
+        netdev->features |= netdev->hw_features |
+                NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
+
+        netdev->irq = adapter->msix_entries[0].vector;
+
+        err = register_netdev(netdev);
+        if (err) {
+                dev_err(&pdev->dev, "failed to register net device\n");
+                return err;
+        }
+
+        return 0;
+}
+
+static int qlcnic_set_dma_mask(struct pci_dev *pdev, u8 *pci_using_dac)
+{
+        if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
+                        !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
+                *pci_using_dac = 1;
+        else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
+                        !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
+                *pci_using_dac = 0;
+        else {
+                dev_err(&pdev->dev, "Unable to set DMA mask, aborting\n");
+                return -EIO;
+        }
+
+        return 0;
+}
+
+static int
+qlcnic_alloc_msix_entries(struct qlcnic_adapter *adapter, u16 count)
+{
+        adapter->msix_entries = kcalloc(count, sizeof(struct msix_entry),
+                                        GFP_KERNEL);
+
+        if (adapter->msix_entries)
+                return 0;
+
+        dev_err(&adapter->pdev->dev, "failed allocating msix_entries\n");
+        return -ENOMEM;
+}
+
+static int __devinit
+qlcnic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+        struct net_device *netdev = NULL;
+        struct qlcnic_adapter *adapter = NULL;
+        int err;
+        uint8_t revision_id;
+        uint8_t pci_using_dac;
+        char brd_name[QLCNIC_MAX_BOARD_NAME_LEN];
+
+        err = pci_enable_device(pdev);
+        if (err)
+                return err;
+
+        if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
+                err = -ENODEV;
+                goto err_out_disable_pdev;
+        }
+
+        err = qlcnic_set_dma_mask(pdev, &pci_using_dac);
+        if (err)
+                goto err_out_disable_pdev;
+
+        err = pci_request_regions(pdev, qlcnic_driver_name);
+        if (err)
+                goto err_out_disable_pdev;
+
+        pci_set_master(pdev);
+        pci_enable_pcie_error_reporting(pdev);
+
+        netdev = alloc_etherdev(sizeof(struct qlcnic_adapter));
+        if (!netdev) {
+                dev_err(&pdev->dev, "failed to allocate net_device\n");
+                err = -ENOMEM;
+                goto err_out_free_res;
+        }
+
+        SET_NETDEV_DEV(netdev, &pdev->dev);
+
+        adapter = netdev_priv(netdev);
+        adapter->netdev  = netdev;
+        adapter->pdev    = pdev;
+
+        if (qlcnic_alloc_adapter_resources(adapter))
+                goto err_out_free_netdev;
+
+        adapter->dev_rst_time = jiffies;
+        revision_id = pdev->revision;
+        adapter->ahw->revision_id = revision_id;
+        adapter->mac_learn = qlcnic_mac_learn;
+
+        rwlock_init(&adapter->ahw->crb_lock);
+        mutex_init(&adapter->ahw->mem_lock);
+
+        spin_lock_init(&adapter->tx_clean_lock);
+        INIT_LIST_HEAD(&adapter->mac_list);
+
+        err = qlcnic_setup_pci_map(adapter);
+        if (err)
+                goto err_out_free_hw;
+
+        /* This will be reset for mezz cards  */
+        adapter->portnum = adapter->ahw->pci_func;
+
+        err = qlcnic_get_board_info(adapter);
+        if (err) {
+                dev_err(&pdev->dev, "Error getting board config info.\n");
+                goto err_out_iounmap;
+        }
+
+        err = qlcnic_setup_idc_param(adapter);
+        if (err)
+                goto err_out_iounmap;
+
+        adapter->flags |= QLCNIC_NEED_FLR;
+
+        err = adapter->nic_ops->start_firmware(adapter);
+        if (err) {
+                dev_err(&pdev->dev, "Loading fw failed.Please Reboot\n");
+                goto err_out_decr_ref;
+        }
+
+        /* Get FW dump template and store it */
+        if (adapter->op_mode != QLCNIC_NON_PRIV_FUNC)
+                if (!qlcnic_fw_cmd_get_minidump_temp(adapter))
+                        dev_info(&pdev->dev,
+                                "Supports FW dump capability\n");
+
+        if (qlcnic_read_mac_addr(adapter))
+                dev_warn(&pdev->dev, "failed to read mac addr\n");
+
+        if (adapter->portnum == 0) {
+                get_brd_name(adapter, brd_name);
+
+                pr_info("%s: %s Board Chip rev 0x%x\n",
+                                module_name(THIS_MODULE),
+                                brd_name, adapter->ahw->revision_id);
+        }
+
+        qlcnic_clear_stats(adapter);
+
+        err = qlcnic_alloc_msix_entries(adapter, adapter->max_rx_ques);
+        if (err)
+                goto err_out_decr_ref;
+
+        qlcnic_setup_intr(adapter);
+
+        err = qlcnic_setup_netdev(adapter, netdev, pci_using_dac);
+        if (err)
+                goto err_out_disable_msi;
+
+        pci_set_drvdata(pdev, adapter);
+
+        qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
+
+        switch (adapter->ahw->port_type) {
+        case QLCNIC_GBE:
+                dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n",
+                                adapter->netdev->name);
+                break;
+        case QLCNIC_XGBE:
+                dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
+                                adapter->netdev->name);
+                break;
+        }
+
+        if (adapter->mac_learn)
+                qlcnic_alloc_lb_filters_mem(adapter);
+
+        qlcnic_create_diag_entries(adapter);
+
+        return 0;
+
+err_out_disable_msi:
+        qlcnic_teardown_intr(adapter);
+        kfree(adapter->msix_entries);
+
+err_out_decr_ref:
+        qlcnic_clr_all_drv_state(adapter, 0);
+
+err_out_iounmap:
+        qlcnic_cleanup_pci_map(adapter);
+
+err_out_free_hw:
+        qlcnic_free_adapter_resources(adapter);
+
+err_out_free_netdev:
+        free_netdev(netdev);
+
+err_out_free_res:
+        pci_release_regions(pdev);
+
+err_out_disable_pdev:
+        pci_set_drvdata(pdev, NULL);
+        pci_disable_device(pdev);
+        return err;
+}
+
+static void __devexit qlcnic_remove(struct pci_dev *pdev)
+{
+        struct qlcnic_adapter *adapter;
+        struct net_device *netdev;
+
+        adapter = pci_get_drvdata(pdev);
+        if (adapter == NULL)
+                return;
+
+        netdev = adapter->netdev;
+
+        qlcnic_cancel_fw_work(adapter);
+
+        unregister_netdev(netdev);
+
+        qlcnic_detach(adapter);
+
+        if (adapter->npars != NULL)
+                kfree(adapter->npars);
+        if (adapter->eswitch != NULL)
+                kfree(adapter->eswitch);
+
+        qlcnic_clr_all_drv_state(adapter, 0);
+
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+
+        qlcnic_free_lb_filters_mem(adapter);
+
+        qlcnic_teardown_intr(adapter);
+        kfree(adapter->msix_entries);
+
+        qlcnic_remove_diag_entries(adapter);
+
+        qlcnic_cleanup_pci_map(adapter);
+
+        qlcnic_release_firmware(adapter);
+
+        pci_disable_pcie_error_reporting(pdev);
+        pci_release_regions(pdev);
+        pci_disable_device(pdev);
+        pci_set_drvdata(pdev, NULL);
+
+        qlcnic_free_adapter_resources(adapter);
+        free_netdev(netdev);
+}
+static int __qlcnic_shutdown(struct pci_dev *pdev)
+{
+        struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
+        int retval;
+
+        netif_device_detach(netdev);
+
+        qlcnic_cancel_fw_work(adapter);
+
+        if (netif_running(netdev))
+                qlcnic_down(adapter, netdev);
+
+        qlcnic_clr_all_drv_state(adapter, 0);
+
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+
+        retval = pci_save_state(pdev);
+        if (retval)
+                return retval;
+
+        if (qlcnic_wol_supported(adapter)) {
+                pci_enable_wake(pdev, PCI_D3cold, 1);
+                pci_enable_wake(pdev, PCI_D3hot, 1);
+        }
+
+        return 0;
+}
+
+static void qlcnic_shutdown(struct pci_dev *pdev)
+{
+        if (__qlcnic_shutdown(pdev))
+                return;
+
+        pci_disable_device(pdev);
+}
+
+#ifdef CONFIG_PM
+static int
+qlcnic_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+        int retval;
+
+        retval = __qlcnic_shutdown(pdev);
+        if (retval)
+                return retval;
+
+        pci_set_power_state(pdev, pci_choose_state(pdev, state));
+        return 0;
+}
+
+static int
+qlcnic_resume(struct pci_dev *pdev)
+{
+        struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
+        int err;
+
+        err = pci_enable_device(pdev);
+        if (err)
+                return err;
+
+        pci_set_power_state(pdev, PCI_D0);
+        pci_set_master(pdev);
+        pci_restore_state(pdev);
+
+        err = adapter->nic_ops->start_firmware(adapter);
+        if (err) {
+                dev_err(&pdev->dev, "failed to start firmware\n");
+                return err;
+        }
+
+        if (netif_running(netdev)) {
+                err = qlcnic_up(adapter, netdev);
+                if (err)
+                        goto done;
+
+                qlcnic_restore_indev_addr(netdev, NETDEV_UP);
+        }
+done:
+        netif_device_attach(netdev);
+        qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
+        return 0;
+}
+#endif
+
+static int qlcnic_open(struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        int err;
+
+        netif_carrier_off(netdev);
+
+        err = qlcnic_attach(adapter);
+        if (err)
+                return err;
+
+        err = __qlcnic_up(adapter, netdev);
+        if (err)
+                goto err_out;
+
+        netif_start_queue(netdev);
+
+        return 0;
+
+err_out:
+        qlcnic_detach(adapter);
+        return err;
+}
+
+/*
+ * qlcnic_close - Disables a network interface entry point
+ */
+static int qlcnic_close(struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        __qlcnic_down(adapter, netdev);
+        return 0;
+}
+
+void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter)
+{
+        void *head;
+        int i;
+
+        if (adapter->fhash.fmax && adapter->fhash.fhead)
+                return;
+
+        spin_lock_init(&adapter->mac_learn_lock);
+
+        head = kcalloc(QLCNIC_LB_MAX_FILTERS, sizeof(struct hlist_head),
+                                                                GFP_KERNEL);
+        if (!head)
+                return;
+
+        adapter->fhash.fmax = QLCNIC_LB_MAX_FILTERS;
+        adapter->fhash.fhead = head;
+
+        for (i = 0; i < adapter->fhash.fmax; i++)
+                INIT_HLIST_HEAD(&adapter->fhash.fhead[i]);
+}
+
+static void qlcnic_free_lb_filters_mem(struct qlcnic_adapter *adapter)
+{
+        if (adapter->fhash.fmax && adapter->fhash.fhead)
+                kfree(adapter->fhash.fhead);
+
+        adapter->fhash.fhead = NULL;
+        adapter->fhash.fmax = 0;
+}
+
+static void qlcnic_change_filter(struct qlcnic_adapter *adapter,
+                u64 uaddr, __le16 vlan_id, struct qlcnic_host_tx_ring *tx_ring)
+{
+        struct cmd_desc_type0 *hwdesc;
+        struct qlcnic_nic_req *req;
+        struct qlcnic_mac_req *mac_req;
+        struct qlcnic_vlan_req *vlan_req;
+        u32 producer;
+        u64 word;
+
+        producer = tx_ring->producer;
+        hwdesc = &tx_ring->desc_head[tx_ring->producer];
+
+        req = (struct qlcnic_nic_req *)hwdesc;
+        memset(req, 0, sizeof(struct qlcnic_nic_req));
+        req->qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
+
+        word = QLCNIC_MAC_EVENT | ((u64)(adapter->portnum) << 16);
+        req->req_hdr = cpu_to_le64(word);
+
+        mac_req = (struct qlcnic_mac_req *)&(req->words[0]);
+        mac_req->op = vlan_id ? QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_ADD;
+        memcpy(mac_req->mac_addr, &uaddr, ETH_ALEN);
+
+        vlan_req = (struct qlcnic_vlan_req *)&req->words[1];
+        vlan_req->vlan_id = vlan_id;
+
+        tx_ring->producer = get_next_index(producer, tx_ring->num_desc);
+        smp_mb();
+}
+
+#define QLCNIC_MAC_HASH(MAC)\
+        ((((MAC) & 0x70000) >> 0x10) | (((MAC) & 0x70000000000ULL) >> 0x25))
+
+static void
+qlcnic_send_filter(struct qlcnic_adapter *adapter,
+                struct qlcnic_host_tx_ring *tx_ring,
+                struct cmd_desc_type0 *first_desc,
+                struct sk_buff *skb)
+{
+        struct ethhdr *phdr = (struct ethhdr *)(skb->data);
+        struct qlcnic_filter *fil, *tmp_fil;
+        struct hlist_node *tmp_hnode, *n;
+        struct hlist_head *head;
+        u64 src_addr = 0;
+        __le16 vlan_id = 0;
+        u8 hindex;
+
+        if (!compare_ether_addr(phdr->h_source, adapter->mac_addr))
+                return;
+
+        if (adapter->fhash.fnum >= adapter->fhash.fmax)
+                return;
+
+        /* Only NPAR capable devices support vlan based learning*/
+        if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
+                vlan_id = first_desc->vlan_TCI;
+        memcpy(&src_addr, phdr->h_source, ETH_ALEN);
+        hindex = QLCNIC_MAC_HASH(src_addr) & (QLCNIC_LB_MAX_FILTERS - 1);
+        head = &(adapter->fhash.fhead[hindex]);
+
+        hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
+                if (!memcmp(tmp_fil->faddr, &src_addr, ETH_ALEN) &&
+                            tmp_fil->vlan_id == vlan_id) {
+
+                        if (jiffies >
+                            (QLCNIC_READD_AGE * HZ + tmp_fil->ftime))
+                                qlcnic_change_filter(adapter, src_addr, vlan_id,
+                                                                tx_ring);
+                        tmp_fil->ftime = jiffies;
+                        return;
+                }
+        }
+
+        fil = kzalloc(sizeof(struct qlcnic_filter), GFP_ATOMIC);
+        if (!fil)
+                return;
+
+        qlcnic_change_filter(adapter, src_addr, vlan_id, tx_ring);
+
+        fil->ftime = jiffies;
+        fil->vlan_id = vlan_id;
+        memcpy(fil->faddr, &src_addr, ETH_ALEN);
+        spin_lock(&adapter->mac_learn_lock);
+        hlist_add_head(&(fil->fnode), head);
+        adapter->fhash.fnum++;
+        spin_unlock(&adapter->mac_learn_lock);
+}
+
+static int
+qlcnic_tx_pkt(struct qlcnic_adapter *adapter,
+                struct cmd_desc_type0 *first_desc,
+                struct sk_buff *skb)
+{
+        u8 opcode = 0, hdr_len = 0;
+        u16 flags = 0, vlan_tci = 0;
+        int copied, offset, copy_len;
+        struct cmd_desc_type0 *hwdesc;
+        struct vlan_ethhdr *vh;
+        struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
+        u16 protocol = ntohs(skb->protocol);
+        u32 producer = tx_ring->producer;
+
+        if (protocol == ETH_P_8021Q) {
+                vh = (struct vlan_ethhdr *)skb->data;
+                flags = FLAGS_VLAN_TAGGED;
+                vlan_tci = vh->h_vlan_TCI;
+        } else if (vlan_tx_tag_present(skb)) {
+                flags = FLAGS_VLAN_OOB;
+                vlan_tci = vlan_tx_tag_get(skb);
+        }
+        if (unlikely(adapter->pvid)) {
+                if (vlan_tci && !(adapter->flags & QLCNIC_TAGGING_ENABLED))
+                        return -EIO;
+                if (vlan_tci && (adapter->flags & QLCNIC_TAGGING_ENABLED))
+                        goto set_flags;
+
+                flags = FLAGS_VLAN_OOB;
+                vlan_tci = adapter->pvid;
+        }
+set_flags:
+        qlcnic_set_tx_vlan_tci(first_desc, vlan_tci);
+        qlcnic_set_tx_flags_opcode(first_desc, flags, opcode);
+
+        if (*(skb->data) & BIT_0) {
+                flags |= BIT_0;
+                memcpy(&first_desc->eth_addr, skb->data, ETH_ALEN);
+        }
+        opcode = TX_ETHER_PKT;
+        if ((adapter->netdev->features & (NETIF_F_TSO | NETIF_F_TSO6)) &&
+                        skb_shinfo(skb)->gso_size > 0) {
+
+                hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
+
+                first_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
+                first_desc->total_hdr_length = hdr_len;
+
+                opcode = (protocol == ETH_P_IPV6) ? TX_TCP_LSO6 : TX_TCP_LSO;
+
+                /* For LSO, we need to copy the MAC/IP/TCP headers into
+                * the descriptor ring */
+                copied = 0;
+                offset = 2;
+
+                if (flags & FLAGS_VLAN_OOB) {
+                        first_desc->total_hdr_length += VLAN_HLEN;
+                        first_desc->tcp_hdr_offset = VLAN_HLEN;
+                        first_desc->ip_hdr_offset = VLAN_HLEN;
+                        /* Only in case of TSO on vlan device */
+                        flags |= FLAGS_VLAN_TAGGED;
+
+                        /* Create a TSO vlan header template for firmware */
+
+                        hwdesc = &tx_ring->desc_head[producer];
+                        tx_ring->cmd_buf_arr[producer].skb = NULL;
+
+                        copy_len = min((int)sizeof(struct cmd_desc_type0) -
+                                offset, hdr_len + VLAN_HLEN);
+
+                        vh = (struct vlan_ethhdr *)((char *) hwdesc + 2);
+                        skb_copy_from_linear_data(skb, vh, 12);
+                        vh->h_vlan_proto = htons(ETH_P_8021Q);
+                        vh->h_vlan_TCI = htons(vlan_tci);
+
+                        skb_copy_from_linear_data_offset(skb, 12,
+                                (char *)vh + 16, copy_len - 16);
+
+                        copied = copy_len - VLAN_HLEN;
+                        offset = 0;
+
+                        producer = get_next_index(producer, tx_ring->num_desc);
+                }
+
+                while (copied < hdr_len) {
+
+                        copy_len = min((int)sizeof(struct cmd_desc_type0) -
+                                offset, (hdr_len - copied));
+
+                        hwdesc = &tx_ring->desc_head[producer];
+                        tx_ring->cmd_buf_arr[producer].skb = NULL;
+
+                        skb_copy_from_linear_data_offset(skb, copied,
+                                 (char *) hwdesc + offset, copy_len);
+
+                        copied += copy_len;
+                        offset = 0;
+
+                        producer = get_next_index(producer, tx_ring->num_desc);
+                }
+
+                tx_ring->producer = producer;
+                smp_mb();
+                adapter->stats.lso_frames++;
+
+        } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
+                u8 l4proto;
+
+                if (protocol == ETH_P_IP) {
+                        l4proto = ip_hdr(skb)->protocol;
+
+                        if (l4proto == IPPROTO_TCP)
+                                opcode = TX_TCP_PKT;
+                        else if (l4proto == IPPROTO_UDP)
+                                opcode = TX_UDP_PKT;
+                } else if (protocol == ETH_P_IPV6) {
+                        l4proto = ipv6_hdr(skb)->nexthdr;
+
+                        if (l4proto == IPPROTO_TCP)
+                                opcode = TX_TCPV6_PKT;
+                        else if (l4proto == IPPROTO_UDP)
+                                opcode = TX_UDPV6_PKT;
+                }
+        }
+        first_desc->tcp_hdr_offset += skb_transport_offset(skb);
+        first_desc->ip_hdr_offset += skb_network_offset(skb);
+        qlcnic_set_tx_flags_opcode(first_desc, flags, opcode);
+
+        return 0;
+}
+
+static int
+qlcnic_map_tx_skb(struct pci_dev *pdev,
+                struct sk_buff *skb, struct qlcnic_cmd_buffer *pbuf)
+{
+        struct qlcnic_skb_frag *nf;
+        struct skb_frag_struct *frag;
+        int i, nr_frags;
+        dma_addr_t map;
+
+        nr_frags = skb_shinfo(skb)->nr_frags;
+        nf = &pbuf->frag_array[0];
+
+        map = pci_map_single(pdev, skb->data,
+                        skb_headlen(skb), PCI_DMA_TODEVICE);
+        if (pci_dma_mapping_error(pdev, map))
+                goto out_err;
+
+        nf->dma = map;
+        nf->length = skb_headlen(skb);
+
+        for (i = 0; i < nr_frags; i++) {
+                frag = &skb_shinfo(skb)->frags[i];
+                nf = &pbuf->frag_array[i+1];
+
+                map = pci_map_page(pdev, frag->page, frag->page_offset,
+                                frag->size, PCI_DMA_TODEVICE);
+                if (pci_dma_mapping_error(pdev, map))
+                        goto unwind;
+
+                nf->dma = map;
+                nf->length = frag->size;
+        }
+
+        return 0;
+
+unwind:
+        while (--i >= 0) {
+                nf = &pbuf->frag_array[i+1];
+                pci_unmap_page(pdev, nf->dma, nf->length, PCI_DMA_TODEVICE);
+        }
+
+        nf = &pbuf->frag_array[0];
+        pci_unmap_single(pdev, nf->dma, skb_headlen(skb), PCI_DMA_TODEVICE);
+
+out_err:
+        return -ENOMEM;
+}
+
+static void
+qlcnic_unmap_buffers(struct pci_dev *pdev, struct sk_buff *skb,
+                        struct qlcnic_cmd_buffer *pbuf)
+{
+        struct qlcnic_skb_frag *nf = &pbuf->frag_array[0];
+        int nr_frags = skb_shinfo(skb)->nr_frags;
+        int i;
+
+        for (i = 0; i < nr_frags; i++) {
+                nf = &pbuf->frag_array[i+1];
+                pci_unmap_page(pdev, nf->dma, nf->length, PCI_DMA_TODEVICE);
+        }
+
+        nf = &pbuf->frag_array[0];
+        pci_unmap_single(pdev, nf->dma, skb_headlen(skb), PCI_DMA_TODEVICE);
+        pbuf->skb = NULL;
+}
+
+static inline void
+qlcnic_clear_cmddesc(u64 *desc)
+{
+        desc[0] = 0ULL;
+        desc[2] = 0ULL;
+        desc[7] = 0ULL;
+}
+
+netdev_tx_t
+qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
+        struct qlcnic_cmd_buffer *pbuf;
+        struct qlcnic_skb_frag *buffrag;
+        struct cmd_desc_type0 *hwdesc, *first_desc;
+        struct pci_dev *pdev;
+        struct ethhdr *phdr;
+        int delta = 0;
+        int i, k;
+
+        u32 producer;
+        int frag_count;
+        u32 num_txd = tx_ring->num_desc;
+
+        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
+                netif_stop_queue(netdev);
+                return NETDEV_TX_BUSY;
+        }
+
+        if (adapter->flags & QLCNIC_MACSPOOF) {
+                phdr = (struct ethhdr *)skb->data;
+                if (compare_ether_addr(phdr->h_source,
+                                        adapter->mac_addr))
+                        goto drop_packet;
+        }
+
+        frag_count = skb_shinfo(skb)->nr_frags + 1;
+        /* 14 frags supported for normal packet and
+         * 32 frags supported for TSO packet
+         */
+        if (!skb_is_gso(skb) && frag_count > QLCNIC_MAX_FRAGS_PER_TX) {
+
+                for (i = 0; i < (frag_count - QLCNIC_MAX_FRAGS_PER_TX); i++)
+                        delta += skb_shinfo(skb)->frags[i].size;
+
+                if (!__pskb_pull_tail(skb, delta))
+                        goto drop_packet;
+
+                frag_count = 1 + skb_shinfo(skb)->nr_frags;
+        }
+
+        if (unlikely(qlcnic_tx_avail(tx_ring) <= TX_STOP_THRESH)) {
+                netif_stop_queue(netdev);
+                if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
+                        netif_start_queue(netdev);
+                else {
+                        adapter->stats.xmit_off++;
+                        return NETDEV_TX_BUSY;
+                }
+        }
+
+        producer = tx_ring->producer;
+        pbuf = &tx_ring->cmd_buf_arr[producer];
+
+        pdev = adapter->pdev;
+
+        first_desc = hwdesc = &tx_ring->desc_head[producer];
+        qlcnic_clear_cmddesc((u64 *)hwdesc);
+
+        if (qlcnic_map_tx_skb(pdev, skb, pbuf)) {
+                adapter->stats.tx_dma_map_error++;
+                goto drop_packet;
+        }
+
+        pbuf->skb = skb;
+        pbuf->frag_count = frag_count;
+
+        qlcnic_set_tx_frags_len(first_desc, frag_count, skb->len);
+        qlcnic_set_tx_port(first_desc, adapter->portnum);
+
+        for (i = 0; i < frag_count; i++) {
+
+                k = i % 4;
+
+                if ((k == 0) && (i > 0)) {
+                        /* move to next desc.*/
+                        producer = get_next_index(producer, num_txd);
+                        hwdesc = &tx_ring->desc_head[producer];
+                        qlcnic_clear_cmddesc((u64 *)hwdesc);
+                        tx_ring->cmd_buf_arr[producer].skb = NULL;
+                }
+
+                buffrag = &pbuf->frag_array[i];
+
+                hwdesc->buffer_length[k] = cpu_to_le16(buffrag->length);
+                switch (k) {
+                case 0:
+                        hwdesc->addr_buffer1 = cpu_to_le64(buffrag->dma);
+                        break;
+                case 1:
+                        hwdesc->addr_buffer2 = cpu_to_le64(buffrag->dma);
+                        break;
+                case 2:
+                        hwdesc->addr_buffer3 = cpu_to_le64(buffrag->dma);
+                        break;
+                case 3:
+                        hwdesc->addr_buffer4 = cpu_to_le64(buffrag->dma);
+                        break;
+                }
+        }
+
+        tx_ring->producer = get_next_index(producer, num_txd);
+        smp_mb();
+
+        if (unlikely(qlcnic_tx_pkt(adapter, first_desc, skb)))
+                goto unwind_buff;
+
+        if (adapter->mac_learn)
+                qlcnic_send_filter(adapter, tx_ring, first_desc, skb);
+
+        adapter->stats.txbytes += skb->len;
+        adapter->stats.xmitcalled++;
+
+        qlcnic_update_cmd_producer(adapter, tx_ring);
+
+        return NETDEV_TX_OK;
+
+unwind_buff:
+        qlcnic_unmap_buffers(pdev, skb, pbuf);
+drop_packet:
+        adapter->stats.txdropped++;
+        dev_kfree_skb_any(skb);
+        return NETDEV_TX_OK;
+}
+
+static int qlcnic_check_temp(struct qlcnic_adapter *adapter)
+{
+        struct net_device *netdev = adapter->netdev;
+        u32 temp, temp_state, temp_val;
+        int rv = 0;
+
+        temp = QLCRD32(adapter, CRB_TEMP_STATE);
+
+        temp_state = qlcnic_get_temp_state(temp);
+        temp_val = qlcnic_get_temp_val(temp);
+
+        if (temp_state == QLCNIC_TEMP_PANIC) {
+                dev_err(&netdev->dev,
+                       "Device temperature %d degrees C exceeds"
+                       " maximum allowed. Hardware has been shut down.\n",
+                       temp_val);
+                rv = 1;
+        } else if (temp_state == QLCNIC_TEMP_WARN) {
+                if (adapter->temp == QLCNIC_TEMP_NORMAL) {
+                        dev_err(&netdev->dev,
+                               "Device temperature %d degrees C "
+                               "exceeds operating range."
+                               " Immediate action needed.\n",
+                               temp_val);
+                }
+        } else {
+                if (adapter->temp == QLCNIC_TEMP_WARN) {
+                        dev_info(&netdev->dev,
+                               "Device temperature is now %d degrees C"
+                               " in normal range.\n", temp_val);
+                }
+        }
+        adapter->temp = temp_state;
+        return rv;
+}
+
+void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup)
+{
+        struct net_device *netdev = adapter->netdev;
+
+        if (adapter->ahw->linkup && !linkup) {
+                netdev_info(netdev, "NIC Link is down\n");
+                adapter->ahw->linkup = 0;
+                if (netif_running(netdev)) {
+                        netif_carrier_off(netdev);
+                        netif_stop_queue(netdev);
+                }
+        } else if (!adapter->ahw->linkup && linkup) {
+                netdev_info(netdev, "NIC Link is up\n");
+                adapter->ahw->linkup = 1;
+                if (netif_running(netdev)) {
+                        netif_carrier_on(netdev);
+                        netif_wake_queue(netdev);
+                }
+        }
+}
+
+static void qlcnic_tx_timeout(struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+
+        if (test_bit(__QLCNIC_RESETTING, &adapter->state))
+                return;
+
+        dev_err(&netdev->dev, "transmit timeout, resetting.\n");
+
+        if (++adapter->tx_timeo_cnt >= QLCNIC_MAX_TX_TIMEOUTS)
+                adapter->need_fw_reset = 1;
+        else
+                adapter->reset_context = 1;
+}
+
+static struct net_device_stats *qlcnic_get_stats(struct net_device *netdev)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct net_device_stats *stats = &netdev->stats;
+
+        stats->rx_packets = adapter->stats.rx_pkts + adapter->stats.lro_pkts;
+        stats->tx_packets = adapter->stats.xmitfinished;
+        stats->rx_bytes = adapter->stats.rxbytes + adapter->stats.lrobytes;
+        stats->tx_bytes = adapter->stats.txbytes;
+        stats->rx_dropped = adapter->stats.rxdropped;
+        stats->tx_dropped = adapter->stats.txdropped;
+
+        return stats;
+}
+
+static irqreturn_t qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
+{
+        u32 status;
+
+        status = readl(adapter->isr_int_vec);
+
+        if (!(status & adapter->int_vec_bit))
+                return IRQ_NONE;
+
+        /* check interrupt state machine, to be sure */
+        status = readl(adapter->crb_int_state_reg);
+        if (!ISR_LEGACY_INT_TRIGGERED(status))
+                return IRQ_NONE;
+
+        writel(0xffffffff, adapter->tgt_status_reg);
+        /* read twice to ensure write is flushed */
+        readl(adapter->isr_int_vec);
+        readl(adapter->isr_int_vec);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t qlcnic_tmp_intr(int irq, void *data)
+{
+        struct qlcnic_host_sds_ring *sds_ring = data;
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+
+        if (adapter->flags & QLCNIC_MSIX_ENABLED)
+                goto done;
+        else if (adapter->flags & QLCNIC_MSI_ENABLED) {
+                writel(0xffffffff, adapter->tgt_status_reg);
+                goto done;
+        }
+
+        if (qlcnic_clear_legacy_intr(adapter) == IRQ_NONE)
+                return IRQ_NONE;
+
+done:
+        adapter->diag_cnt++;
+        qlcnic_enable_int(sds_ring);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t qlcnic_intr(int irq, void *data)
+{
+        struct qlcnic_host_sds_ring *sds_ring = data;
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+
+        if (qlcnic_clear_legacy_intr(adapter) == IRQ_NONE)
+                return IRQ_NONE;
+
+        napi_schedule(&sds_ring->napi);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t qlcnic_msi_intr(int irq, void *data)
+{
+        struct qlcnic_host_sds_ring *sds_ring = data;
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+
+        /* clear interrupt */
+        writel(0xffffffff, adapter->tgt_status_reg);
+
+        napi_schedule(&sds_ring->napi);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t qlcnic_msix_intr(int irq, void *data)
+{
+        struct qlcnic_host_sds_ring *sds_ring = data;
+
+        napi_schedule(&sds_ring->napi);
+        return IRQ_HANDLED;
+}
+
+static int qlcnic_process_cmd_ring(struct qlcnic_adapter *adapter)
+{
+        u32 sw_consumer, hw_consumer;
+        int count = 0, i;
+        struct qlcnic_cmd_buffer *buffer;
+        struct pci_dev *pdev = adapter->pdev;
+        struct net_device *netdev = adapter->netdev;
+        struct qlcnic_skb_frag *frag;
+        int done;
+        struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
+
+        if (!spin_trylock(&adapter->tx_clean_lock))
+                return 1;
+
+        sw_consumer = tx_ring->sw_consumer;
+        hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
+
+        while (sw_consumer != hw_consumer) {
+                buffer = &tx_ring->cmd_buf_arr[sw_consumer];
+                if (buffer->skb) {
+                        frag = &buffer->frag_array[0];
+                        pci_unmap_single(pdev, frag->dma, frag->length,
+                                         PCI_DMA_TODEVICE);
+                        frag->dma = 0ULL;
+                        for (i = 1; i < buffer->frag_count; i++) {
+                                frag++;
+                                pci_unmap_page(pdev, frag->dma, frag->length,
+                                               PCI_DMA_TODEVICE);
+                                frag->dma = 0ULL;
+                        }
+
+                        adapter->stats.xmitfinished++;
+                        dev_kfree_skb_any(buffer->skb);
+                        buffer->skb = NULL;
+                }
+
+                sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
+                if (++count >= MAX_STATUS_HANDLE)
+                        break;
+        }
+
+        if (count && netif_running(netdev)) {
+                tx_ring->sw_consumer = sw_consumer;
+
+                smp_mb();
+
+                if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
+                        if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH) {
+                                netif_wake_queue(netdev);
+                                adapter->stats.xmit_on++;
+                        }
+                }
+                adapter->tx_timeo_cnt = 0;
+        }
+        /*
+         * If everything is freed up to consumer then check if the ring is full
+         * If the ring is full then check if more needs to be freed and
+         * schedule the call back again.
+         *
+         * This happens when there are 2 CPUs. One could be freeing and the
+         * other filling it. If the ring is full when we get out of here and
+         * the card has already interrupted the host then the host can miss the
+         * interrupt.
+         *
+         * There is still a possible race condition and the host could miss an
+         * interrupt. The card has to take care of this.
+         */
+        hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
+        done = (sw_consumer == hw_consumer);
+        spin_unlock(&adapter->tx_clean_lock);
+
+        return done;
+}
+
+static int qlcnic_poll(struct napi_struct *napi, int budget)
+{
+        struct qlcnic_host_sds_ring *sds_ring =
+                container_of(napi, struct qlcnic_host_sds_ring, napi);
+
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+
+        int tx_complete;
+        int work_done;
+
+        tx_complete = qlcnic_process_cmd_ring(adapter);
+
+        work_done = qlcnic_process_rcv_ring(sds_ring, budget);
+
+        if ((work_done < budget) && tx_complete) {
+                napi_complete(&sds_ring->napi);
+                if (test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                        qlcnic_enable_int(sds_ring);
+        }
+
+        return work_done;
+}
+
+static int qlcnic_rx_poll(struct napi_struct *napi, int budget)
+{
+        struct qlcnic_host_sds_ring *sds_ring =
+                container_of(napi, struct qlcnic_host_sds_ring, napi);
+
+        struct qlcnic_adapter *adapter = sds_ring->adapter;
+        int work_done;
+
+        work_done = qlcnic_process_rcv_ring(sds_ring, budget);
+
+        if (work_done < budget) {
+                napi_complete(&sds_ring->napi);
+                if (test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                        qlcnic_enable_int(sds_ring);
+        }
+
+        return work_done;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void qlcnic_poll_controller(struct net_device *netdev)
+{
+        int ring;
+        struct qlcnic_host_sds_ring *sds_ring;
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
+
+        disable_irq(adapter->irq);
+        for (ring = 0; ring < adapter->max_sds_rings; ring++) {
+                sds_ring = &recv_ctx->sds_rings[ring];
+                qlcnic_intr(adapter->irq, sds_ring);
+        }
+        enable_irq(adapter->irq);
+}
+#endif
+
+static void
+qlcnic_idc_debug_info(struct qlcnic_adapter *adapter, u8 encoding)
+{
+        u32 val;
+
+        val = adapter->portnum & 0xf;
+        val |= encoding << 7;
+        val |= (jiffies - adapter->dev_rst_time) << 8;
+
+        QLCWR32(adapter, QLCNIC_CRB_DRV_SCRATCH, val);
+        adapter->dev_rst_time = jiffies;
+}
+
+static int
+qlcnic_set_drv_state(struct qlcnic_adapter *adapter, u8 state)
+{
+        u32  val;
+
+        WARN_ON(state != QLCNIC_DEV_NEED_RESET &&
+                        state != QLCNIC_DEV_NEED_QUISCENT);
+
+        if (qlcnic_api_lock(adapter))
+                return -EIO;
+
+        val = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+
+        if (state == QLCNIC_DEV_NEED_RESET)
+                QLC_DEV_SET_RST_RDY(val, adapter->portnum);
+        else if (state == QLCNIC_DEV_NEED_QUISCENT)
+                QLC_DEV_SET_QSCNT_RDY(val, adapter->portnum);
+
+        QLCWR32(adapter, QLCNIC_CRB_DRV_STATE, val);
+
+        qlcnic_api_unlock(adapter);
+
+        return 0;
+}
+
+static int
+qlcnic_clr_drv_state(struct qlcnic_adapter *adapter)
+{
+        u32  val;
+
+        if (qlcnic_api_lock(adapter))
+                return -EBUSY;
+
+        val = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+        QLC_DEV_CLR_RST_QSCNT(val, adapter->portnum);
+        QLCWR32(adapter, QLCNIC_CRB_DRV_STATE, val);
+
+        qlcnic_api_unlock(adapter);
+
+        return 0;
+}
+
+static void
+qlcnic_clr_all_drv_state(struct qlcnic_adapter *adapter, u8 failed)
+{
+        u32  val;
+
+        if (qlcnic_api_lock(adapter))
+                goto err;
+
+        val = QLCRD32(adapter, QLCNIC_CRB_DRV_ACTIVE);
+        QLC_DEV_CLR_REF_CNT(val, adapter->portnum);
+        QLCWR32(adapter, QLCNIC_CRB_DRV_ACTIVE, val);
+
+        if (failed) {
+                QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_FAILED);
+                dev_info(&adapter->pdev->dev,
+                                "Device state set to Failed. Please Reboot\n");
+        } else if (!(val & 0x11111111))
+                QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_COLD);
+
+        val = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+        QLC_DEV_CLR_RST_QSCNT(val, adapter->portnum);
+        QLCWR32(adapter, QLCNIC_CRB_DRV_STATE, val);
+
+        qlcnic_api_unlock(adapter);
+err:
+        adapter->fw_fail_cnt = 0;
+        clear_bit(__QLCNIC_START_FW, &adapter->state);
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+}
+
+/* Grab api lock, before checking state */
+static int
+qlcnic_check_drv_state(struct qlcnic_adapter *adapter)
+{
+        int act, state, active_mask;
+
+        state = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+        act = QLCRD32(adapter, QLCNIC_CRB_DRV_ACTIVE);
+
+        if (adapter->flags & QLCNIC_FW_RESET_OWNER) {
+                active_mask = (~(1 << (adapter->ahw->pci_func * 4)));
+                act = act & active_mask;
+        }
+
+        if (((state & 0x11111111) == (act & 0x11111111)) ||
+                        ((act & 0x11111111) == ((state >> 1) & 0x11111111)))
+                return 0;
+        else
+                return 1;
+}
+
+static int qlcnic_check_idc_ver(struct qlcnic_adapter *adapter)
+{
+        u32 val = QLCRD32(adapter, QLCNIC_CRB_DRV_IDC_VER);
+
+        if (val != QLCNIC_DRV_IDC_VER) {
+                dev_warn(&adapter->pdev->dev, "IDC Version mismatch, driver's"
+                        " idc ver = %x; reqd = %x\n", QLCNIC_DRV_IDC_VER, val);
+        }
+
+        return 0;
+}
+
+static int
+qlcnic_can_start_firmware(struct qlcnic_adapter *adapter)
+{
+        u32 val, prev_state;
+        u8 dev_init_timeo = adapter->dev_init_timeo;
+        u8 portnum = adapter->portnum;
+        u8 ret;
+
+        if (test_and_clear_bit(__QLCNIC_START_FW, &adapter->state))
+                return 1;
+
+        if (qlcnic_api_lock(adapter))
+                return -1;
+
+        val = QLCRD32(adapter, QLCNIC_CRB_DRV_ACTIVE);
+        if (!(val & (1 << (portnum * 4)))) {
+                QLC_DEV_SET_REF_CNT(val, portnum);
+                QLCWR32(adapter, QLCNIC_CRB_DRV_ACTIVE, val);
+        }
+
+        prev_state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
+        QLCDB(adapter, HW, "Device state = %u\n", prev_state);
+
+        switch (prev_state) {
+        case QLCNIC_DEV_COLD:
+                QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_INITIALIZING);
+                QLCWR32(adapter, QLCNIC_CRB_DRV_IDC_VER, QLCNIC_DRV_IDC_VER);
+                qlcnic_idc_debug_info(adapter, 0);
+                qlcnic_api_unlock(adapter);
+                return 1;
+
+        case QLCNIC_DEV_READY:
+                ret = qlcnic_check_idc_ver(adapter);
+                qlcnic_api_unlock(adapter);
+                return ret;
+
+        case QLCNIC_DEV_NEED_RESET:
+                val = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+                QLC_DEV_SET_RST_RDY(val, portnum);
+                QLCWR32(adapter, QLCNIC_CRB_DRV_STATE, val);
+                break;
+
+        case QLCNIC_DEV_NEED_QUISCENT:
+                val = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+                QLC_DEV_SET_QSCNT_RDY(val, portnum);
+                QLCWR32(adapter, QLCNIC_CRB_DRV_STATE, val);
+                break;
+
+        case QLCNIC_DEV_FAILED:
+                dev_err(&adapter->pdev->dev, "Device in failed state.\n");
+                qlcnic_api_unlock(adapter);
+                return -1;
+
+        case QLCNIC_DEV_INITIALIZING:
+        case QLCNIC_DEV_QUISCENT:
+                break;
+        }
+
+        qlcnic_api_unlock(adapter);
+
+        do {
+                msleep(1000);
+                prev_state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
+
+                if (prev_state == QLCNIC_DEV_QUISCENT)
+                        continue;
+        } while ((prev_state != QLCNIC_DEV_READY) && --dev_init_timeo);
+
+        if (!dev_init_timeo) {
+                dev_err(&adapter->pdev->dev,
+                        "Waiting for device to initialize timeout\n");
+                return -1;
+        }
+
+        if (qlcnic_api_lock(adapter))
+                return -1;
+
+        val = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+        QLC_DEV_CLR_RST_QSCNT(val, portnum);
+        QLCWR32(adapter, QLCNIC_CRB_DRV_STATE, val);
+
+        ret = qlcnic_check_idc_ver(adapter);
+        qlcnic_api_unlock(adapter);
+
+        return ret;
+}
+
+static void
+qlcnic_fwinit_work(struct work_struct *work)
+{
+        struct qlcnic_adapter *adapter = container_of(work,
+                        struct qlcnic_adapter, fw_work.work);
+        u32 dev_state = 0xf;
+        u32 val;
+
+        if (qlcnic_api_lock(adapter))
+                goto err_ret;
+
+        dev_state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
+        if (dev_state == QLCNIC_DEV_QUISCENT ||
+            dev_state == QLCNIC_DEV_NEED_QUISCENT) {
+                qlcnic_api_unlock(adapter);
+                qlcnic_schedule_work(adapter, qlcnic_fwinit_work,
+                                                FW_POLL_DELAY * 2);
+                return;
+        }
+
+        if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC) {
+                qlcnic_api_unlock(adapter);
+                goto wait_npar;
+        }
+
+        if (adapter->fw_wait_cnt++ > adapter->reset_ack_timeo) {
+                dev_err(&adapter->pdev->dev, "Reset:Failed to get ack %d sec\n",
+                                        adapter->reset_ack_timeo);
+                goto skip_ack_check;
+        }
+
+        if (!qlcnic_check_drv_state(adapter)) {
+skip_ack_check:
+                dev_state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
+
+                if (dev_state == QLCNIC_DEV_NEED_RESET) {
+                        QLCWR32(adapter, QLCNIC_CRB_DEV_STATE,
+                                                QLCNIC_DEV_INITIALIZING);
+                        set_bit(__QLCNIC_START_FW, &adapter->state);
+                        QLCDB(adapter, DRV, "Restarting fw\n");
+                        qlcnic_idc_debug_info(adapter, 0);
+                        val = QLCRD32(adapter, QLCNIC_CRB_DRV_STATE);
+                        QLC_DEV_SET_RST_RDY(val, adapter->portnum);
+                        QLCWR32(adapter, QLCNIC_CRB_DRV_STATE, val);
+                }
+
+                qlcnic_api_unlock(adapter);
+
+                rtnl_lock();
+                if (adapter->ahw->fw_dump.enable &&
+                    (adapter->flags & QLCNIC_FW_RESET_OWNER)) {
+                        QLCDB(adapter, DRV, "Take FW dump\n");
+                        qlcnic_dump_fw(adapter);
+                }
+                rtnl_unlock();
+
+                adapter->flags &= ~QLCNIC_FW_RESET_OWNER;
+                if (!adapter->nic_ops->start_firmware(adapter)) {
+                        qlcnic_schedule_work(adapter, qlcnic_attach_work, 0);
+                        adapter->fw_wait_cnt = 0;
+                        return;
+                }
+                goto err_ret;
+        }
+
+        qlcnic_api_unlock(adapter);
+
+wait_npar:
+        dev_state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
+        QLCDB(adapter, HW, "Func waiting: Device state=%u\n", dev_state);
+
+        switch (dev_state) {
+        case QLCNIC_DEV_READY:
+                if (!adapter->nic_ops->start_firmware(adapter)) {
+                        qlcnic_schedule_work(adapter, qlcnic_attach_work, 0);
+                        adapter->fw_wait_cnt = 0;
+                        return;
+                }
+        case QLCNIC_DEV_FAILED:
+                break;
+        default:
+                qlcnic_schedule_work(adapter,
+                        qlcnic_fwinit_work, FW_POLL_DELAY);
+                return;
+        }
+
+err_ret:
+        dev_err(&adapter->pdev->dev, "Fwinit work failed state=%u "
+                "fw_wait_cnt=%u\n", dev_state, adapter->fw_wait_cnt);
+        netif_device_attach(adapter->netdev);
+        qlcnic_clr_all_drv_state(adapter, 0);
+}
+
+static void
+qlcnic_detach_work(struct work_struct *work)
+{
+        struct qlcnic_adapter *adapter = container_of(work,
+                        struct qlcnic_adapter, fw_work.work);
+        struct net_device *netdev = adapter->netdev;
+        u32 status;
+
+        netif_device_detach(netdev);
+
+        /* Dont grab rtnl lock during Quiscent mode */
+        if (adapter->dev_state == QLCNIC_DEV_NEED_QUISCENT) {
+                if (netif_running(netdev))
+                        __qlcnic_down(adapter, netdev);
+        } else
+                qlcnic_down(adapter, netdev);
+
+        status = QLCRD32(adapter, QLCNIC_PEG_HALT_STATUS1);
+
+        if (status & QLCNIC_RCODE_FATAL_ERROR)
+                goto err_ret;
+
+        if (adapter->temp == QLCNIC_TEMP_PANIC)
+                goto err_ret;
+        /* Dont ack if this instance is the reset owner */
+        if (!(adapter->flags & QLCNIC_FW_RESET_OWNER)) {
+                if (qlcnic_set_drv_state(adapter, adapter->dev_state))
+                        goto err_ret;
+        }
+
+        adapter->fw_wait_cnt = 0;
+
+        qlcnic_schedule_work(adapter, qlcnic_fwinit_work, FW_POLL_DELAY);
+
+        return;
+
+err_ret:
+        dev_err(&adapter->pdev->dev, "detach failed; status=%d temp=%d\n",
+                        status, adapter->temp);
+        netif_device_attach(netdev);
+        qlcnic_clr_all_drv_state(adapter, 1);
+}
+
+/*Transit NPAR state to NON Operational */
+static void
+qlcnic_set_npar_non_operational(struct qlcnic_adapter *adapter)
+{
+        u32 state;
+
+        state = QLCRD32(adapter, QLCNIC_CRB_DEV_NPAR_STATE);
+        if (state == QLCNIC_DEV_NPAR_NON_OPER)
+                return;
+
+        if (qlcnic_api_lock(adapter))
+                return;
+        QLCWR32(adapter, QLCNIC_CRB_DEV_NPAR_STATE, QLCNIC_DEV_NPAR_NON_OPER);
+        qlcnic_api_unlock(adapter);
+}
+
+/*Transit to RESET state from READY state only */
+void
+qlcnic_dev_request_reset(struct qlcnic_adapter *adapter)
+{
+        u32 state;
+
+        adapter->need_fw_reset = 1;
+        if (qlcnic_api_lock(adapter))
+                return;
+
+        state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
+
+        if (state == QLCNIC_DEV_READY) {
+                QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_NEED_RESET);
+                adapter->flags |= QLCNIC_FW_RESET_OWNER;
+                QLCDB(adapter, DRV, "NEED_RESET state set\n");
+                qlcnic_idc_debug_info(adapter, 0);
+        }
+
+        QLCWR32(adapter, QLCNIC_CRB_DEV_NPAR_STATE, QLCNIC_DEV_NPAR_NON_OPER);
+        qlcnic_api_unlock(adapter);
+}
+
+/* Transit to NPAR READY state from NPAR NOT READY state */
+static void
+qlcnic_dev_set_npar_ready(struct qlcnic_adapter *adapter)
+{
+        if (qlcnic_api_lock(adapter))
+                return;
+
+        QLCWR32(adapter, QLCNIC_CRB_DEV_NPAR_STATE, QLCNIC_DEV_NPAR_OPER);
+        QLCDB(adapter, DRV, "NPAR operational state set\n");
+
+        qlcnic_api_unlock(adapter);
+}
+
+static void
+qlcnic_schedule_work(struct qlcnic_adapter *adapter,
+                work_func_t func, int delay)
+{
+        if (test_bit(__QLCNIC_AER, &adapter->state))
+                return;
+
+        INIT_DELAYED_WORK(&adapter->fw_work, func);
+        queue_delayed_work(qlcnic_wq, &adapter->fw_work,
+                                        round_jiffies_relative(delay));
+}
+
+static void
+qlcnic_cancel_fw_work(struct qlcnic_adapter *adapter)
+{
+        while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                msleep(10);
+
+        cancel_delayed_work_sync(&adapter->fw_work);
+}
+
+static void
+qlcnic_attach_work(struct work_struct *work)
+{
+        struct qlcnic_adapter *adapter = container_of(work,
+                                struct qlcnic_adapter, fw_work.work);
+        struct net_device *netdev = adapter->netdev;
+        u32 npar_state;
+
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC) {
+                npar_state = QLCRD32(adapter, QLCNIC_CRB_DEV_NPAR_STATE);
+                if (adapter->fw_wait_cnt++ > QLCNIC_DEV_NPAR_OPER_TIMEO)
+                        qlcnic_clr_all_drv_state(adapter, 0);
+                else if (npar_state != QLCNIC_DEV_NPAR_OPER)
+                        qlcnic_schedule_work(adapter, qlcnic_attach_work,
+                                                        FW_POLL_DELAY);
+                else
+                        goto attach;
+                QLCDB(adapter, DRV, "Waiting for NPAR state to operational\n");
+                return;
+        }
+attach:
+        if (netif_running(netdev)) {
+                if (qlcnic_up(adapter, netdev))
+                        goto done;
+
+                qlcnic_restore_indev_addr(netdev, NETDEV_UP);
+        }
+
+done:
+        netif_device_attach(netdev);
+        adapter->fw_fail_cnt = 0;
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+
+        if (!qlcnic_clr_drv_state(adapter))
+                qlcnic_schedule_work(adapter, qlcnic_fw_poll_work,
+                                                        FW_POLL_DELAY);
+}
+
+static int
+qlcnic_check_health(struct qlcnic_adapter *adapter)
+{
+        u32 state = 0, heartbeat;
+        struct net_device *netdev = adapter->netdev;
+
+        if (qlcnic_check_temp(adapter))
+                goto detach;
+
+        if (adapter->need_fw_reset)
+                qlcnic_dev_request_reset(adapter);
+
+        state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
+        if (state == QLCNIC_DEV_NEED_RESET) {
+                qlcnic_set_npar_non_operational(adapter);
+                adapter->need_fw_reset = 1;
+        } else if (state == QLCNIC_DEV_NEED_QUISCENT)
+                goto detach;
+
+        heartbeat = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
+        if (heartbeat != adapter->heartbeat) {
+                adapter->heartbeat = heartbeat;
+                adapter->fw_fail_cnt = 0;
+                if (adapter->need_fw_reset)
+                        goto detach;
+
+                if (adapter->reset_context && auto_fw_reset) {
+                        qlcnic_reset_hw_context(adapter);
+                        adapter->netdev->trans_start = jiffies;
+                }
+
+                return 0;
+        }
+
+        if (++adapter->fw_fail_cnt < FW_FAIL_THRESH)
+                return 0;
+
+        qlcnic_dev_request_reset(adapter);
+
+        if (auto_fw_reset)
+                clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state);
+
+        dev_info(&netdev->dev, "firmware hang detected\n");
+
+detach:
+        adapter->dev_state = (state == QLCNIC_DEV_NEED_QUISCENT) ? state :
+                QLCNIC_DEV_NEED_RESET;
+
+        if (auto_fw_reset &&
+                !test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) {
+
+                qlcnic_schedule_work(adapter, qlcnic_detach_work, 0);
+                QLCDB(adapter, DRV, "fw recovery scheduled.\n");
+        }
+
+        return 1;
+}
+
+static void
+qlcnic_fw_poll_work(struct work_struct *work)
+{
+        struct qlcnic_adapter *adapter = container_of(work,
+                                struct qlcnic_adapter, fw_work.work);
+
+        if (test_bit(__QLCNIC_RESETTING, &adapter->state))
+                goto reschedule;
+
+
+        if (qlcnic_check_health(adapter))
+                return;
+
+        if (adapter->fhash.fnum)
+                qlcnic_prune_lb_filters(adapter);
+
+reschedule:
+        qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
+}
+
+static int qlcnic_is_first_func(struct pci_dev *pdev)
+{
+        struct pci_dev *oth_pdev;
+        int val = pdev->devfn;
+
+        while (val-- > 0) {
+                oth_pdev = pci_get_domain_bus_and_slot(pci_domain_nr
+                        (pdev->bus), pdev->bus->number,
+                        PCI_DEVFN(PCI_SLOT(pdev->devfn), val));
+                if (!oth_pdev)
+                        continue;
+
+                if (oth_pdev->current_state != PCI_D3cold) {
+                        pci_dev_put(oth_pdev);
+                        return 0;
+                }
+                pci_dev_put(oth_pdev);
+        }
+        return 1;
+}
+
+static int qlcnic_attach_func(struct pci_dev *pdev)
+{
+        int err, first_func;
+        struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
+
+        pdev->error_state = pci_channel_io_normal;
+
+        err = pci_enable_device(pdev);
+        if (err)
+                return err;
+
+        pci_set_power_state(pdev, PCI_D0);
+        pci_set_master(pdev);
+        pci_restore_state(pdev);
+
+        first_func = qlcnic_is_first_func(pdev);
+
+        if (qlcnic_api_lock(adapter))
+                return -EINVAL;
+
+        if (adapter->op_mode != QLCNIC_NON_PRIV_FUNC && first_func) {
+                adapter->need_fw_reset = 1;
+                set_bit(__QLCNIC_START_FW, &adapter->state);
+                QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_INITIALIZING);
+                QLCDB(adapter, DRV, "Restarting fw\n");
+        }
+        qlcnic_api_unlock(adapter);
+
+        err = adapter->nic_ops->start_firmware(adapter);
+        if (err)
+                return err;
+
+        qlcnic_clr_drv_state(adapter);
+        qlcnic_setup_intr(adapter);
+
+        if (netif_running(netdev)) {
+                err = qlcnic_attach(adapter);
+                if (err) {
+                        qlcnic_clr_all_drv_state(adapter, 1);
+                        clear_bit(__QLCNIC_AER, &adapter->state);
+                        netif_device_attach(netdev);
+                        return err;
+                }
+
+                err = qlcnic_up(adapter, netdev);
+                if (err)
+                        goto done;
+
+                qlcnic_restore_indev_addr(netdev, NETDEV_UP);
+        }
+ done:
+        netif_device_attach(netdev);
+        return err;
+}
+
+static pci_ers_result_t qlcnic_io_error_detected(struct pci_dev *pdev,
+                                                pci_channel_state_t state)
+{
+        struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
+
+        if (state == pci_channel_io_perm_failure)
+                return PCI_ERS_RESULT_DISCONNECT;
+
+        if (state == pci_channel_io_normal)
+                return PCI_ERS_RESULT_RECOVERED;
+
+        set_bit(__QLCNIC_AER, &adapter->state);
+        netif_device_detach(netdev);
+
+        cancel_delayed_work_sync(&adapter->fw_work);
+
+        if (netif_running(netdev))
+                qlcnic_down(adapter, netdev);
+
+        qlcnic_detach(adapter);
+        qlcnic_teardown_intr(adapter);
+
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+
+        pci_save_state(pdev);
+        pci_disable_device(pdev);
+
+        return PCI_ERS_RESULT_NEED_RESET;
+}
+
+static pci_ers_result_t qlcnic_io_slot_reset(struct pci_dev *pdev)
+{
+        return qlcnic_attach_func(pdev) ? PCI_ERS_RESULT_DISCONNECT :
+                                PCI_ERS_RESULT_RECOVERED;
+}
+
+static void qlcnic_io_resume(struct pci_dev *pdev)
+{
+        struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
+
+        pci_cleanup_aer_uncorrect_error_status(pdev);
+
+        if (QLCRD32(adapter, QLCNIC_CRB_DEV_STATE) == QLCNIC_DEV_READY &&
+            test_and_clear_bit(__QLCNIC_AER, &adapter->state))
+                qlcnic_schedule_work(adapter, qlcnic_fw_poll_work,
+                                                FW_POLL_DELAY);
+}
+
+static int
+qlcnicvf_start_firmware(struct qlcnic_adapter *adapter)
+{
+        int err;
+
+        err = qlcnic_can_start_firmware(adapter);
+        if (err)
+                return err;
+
+        err = qlcnic_check_npar_opertional(adapter);
+        if (err)
+                return err;
+
+        err = qlcnic_initialize_nic(adapter);
+        if (err)
+                return err;
+
+        qlcnic_check_options(adapter);
+
+        err = qlcnic_set_eswitch_port_config(adapter);
+        if (err)
+                return err;
+
+        adapter->need_fw_reset = 0;
+
+        return err;
+}
+
+static int
+qlcnicvf_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
+{
+        return -EOPNOTSUPP;
+}
+
+static int
+qlcnicvf_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
+{
+        return -EOPNOTSUPP;
+}
+
+static ssize_t
+qlcnic_store_bridged_mode(struct device *dev,
+                struct device_attribute *attr, const char *buf, size_t len)
+{
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        unsigned long new;
+        int ret = -EINVAL;
+
+        if (!(adapter->capabilities & QLCNIC_FW_CAPABILITY_BDG))
+                goto err_out;
+
+        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                goto err_out;
+
+        if (strict_strtoul(buf, 2, &new))
+                goto err_out;
+
+        if (!adapter->nic_ops->config_bridged_mode(adapter, !!new))
+                ret = len;
+
+err_out:
+        return ret;
+}
+
+static ssize_t
+qlcnic_show_bridged_mode(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        int bridged_mode = 0;
+
+        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_BDG)
+                bridged_mode = !!(adapter->flags & QLCNIC_BRIDGE_ENABLED);
+
+        return sprintf(buf, "%d\n", bridged_mode);
+}
+
+static struct device_attribute dev_attr_bridged_mode = {
+       .attr = {.name = "bridged_mode", .mode = (S_IRUGO | S_IWUSR)},
+       .show = qlcnic_show_bridged_mode,
+       .store = qlcnic_store_bridged_mode,
+};
+
+static ssize_t
+qlcnic_store_diag_mode(struct device *dev,
+                struct device_attribute *attr, const char *buf, size_t len)
+{
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        unsigned long new;
+
+        if (strict_strtoul(buf, 2, &new))
+                return -EINVAL;
+
+        if (!!new != !!(adapter->flags & QLCNIC_DIAG_ENABLED))
+                adapter->flags ^= QLCNIC_DIAG_ENABLED;
+
+        return len;
+}
+
+static ssize_t
+qlcnic_show_diag_mode(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+
+        return sprintf(buf, "%d\n",
+                        !!(adapter->flags & QLCNIC_DIAG_ENABLED));
+}
+
+static struct device_attribute dev_attr_diag_mode = {
+        .attr = {.name = "diag_mode", .mode = (S_IRUGO | S_IWUSR)},
+        .show = qlcnic_show_diag_mode,
+        .store = qlcnic_store_diag_mode,
+};
+
+int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val)
+{
+        if (!use_msi_x && !use_msi) {
+                netdev_info(netdev, "no msix or msi support, hence no rss\n");
+                return -EINVAL;
+        }
+
+        if ((val > max_hw) || (val <  2) || !is_power_of_2(val)) {
+                netdev_info(netdev, "rss_ring valid range [2 - %x] in "
+                        " powers of 2\n", max_hw);
+                return -EINVAL;
+        }
+        return 0;
+
+}
+
+int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data)
+{
+        struct net_device *netdev = adapter->netdev;
+        int err = 0;
+
+        if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                return -EBUSY;
+
+        netif_device_detach(netdev);
+        if (netif_running(netdev))
+                __qlcnic_down(adapter, netdev);
+        qlcnic_detach(adapter);
+        qlcnic_teardown_intr(adapter);
+
+        if (qlcnic_enable_msix(adapter, data)) {
+                netdev_info(netdev, "failed setting max_rss; rss disabled\n");
+                qlcnic_enable_msi_legacy(adapter);
+        }
+
+        if (netif_running(netdev)) {
+                err = qlcnic_attach(adapter);
+                if (err)
+                        goto done;
+                err = __qlcnic_up(adapter, netdev);
+                if (err)
+                        goto done;
+                qlcnic_restore_indev_addr(netdev, NETDEV_UP);
+        }
+ done:
+        netif_device_attach(netdev);
+        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+        return err;
+}
+
+static int
+qlcnic_sysfs_validate_crb(struct qlcnic_adapter *adapter,
+                loff_t offset, size_t size)
+{
+        size_t crb_size = 4;
+
+        if (!(adapter->flags & QLCNIC_DIAG_ENABLED))
+                return -EIO;
+
+        if (offset < QLCNIC_PCI_CRBSPACE) {
+                if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM,
+                                        QLCNIC_PCI_CAMQM_END))
+                        crb_size = 8;
+                else
+                        return -EINVAL;
+        }
+
+        if ((size != crb_size) || (offset & (crb_size-1)))
+                return  -EINVAL;
+
+        return 0;
+}
+
+static ssize_t
+qlcnic_sysfs_read_crb(struct file *filp, struct kobject *kobj,
+                struct bin_attribute *attr,
+                char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        u32 data;
+        u64 qmdata;
+        int ret;
+
+        ret = qlcnic_sysfs_validate_crb(adapter, offset, size);
+        if (ret != 0)
+                return ret;
+
+        if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
+                qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
+                memcpy(buf, &qmdata, size);
+        } else {
+                data = QLCRD32(adapter, offset);
+                memcpy(buf, &data, size);
+        }
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_write_crb(struct file *filp, struct kobject *kobj,
+                struct bin_attribute *attr,
+                char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        u32 data;
+        u64 qmdata;
+        int ret;
+
+        ret = qlcnic_sysfs_validate_crb(adapter, offset, size);
+        if (ret != 0)
+                return ret;
+
+        if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
+                memcpy(&qmdata, buf, size);
+                qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
+        } else {
+                memcpy(&data, buf, size);
+                QLCWR32(adapter, offset, data);
+        }
+        return size;
+}
+
+static int
+qlcnic_sysfs_validate_mem(struct qlcnic_adapter *adapter,
+                loff_t offset, size_t size)
+{
+        if (!(adapter->flags & QLCNIC_DIAG_ENABLED))
+                return -EIO;
+
+        if ((size != 8) || (offset & 0x7))
+                return  -EIO;
+
+        return 0;
+}
+
+static ssize_t
+qlcnic_sysfs_read_mem(struct file *filp, struct kobject *kobj,
+                struct bin_attribute *attr,
+                char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        u64 data;
+        int ret;
+
+        ret = qlcnic_sysfs_validate_mem(adapter, offset, size);
+        if (ret != 0)
+                return ret;
+
+        if (qlcnic_pci_mem_read_2M(adapter, offset, &data))
+                return -EIO;
+
+        memcpy(buf, &data, size);
+
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_write_mem(struct file *filp, struct kobject *kobj,
+                struct bin_attribute *attr,
+                char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        u64 data;
+        int ret;
+
+        ret = qlcnic_sysfs_validate_mem(adapter, offset, size);
+        if (ret != 0)
+                return ret;
+
+        memcpy(&data, buf, size);
+
+        if (qlcnic_pci_mem_write_2M(adapter, offset, data))
+                return -EIO;
+
+        return size;
+}
+
+static struct bin_attribute bin_attr_crb = {
+        .attr = {.name = "crb", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_read_crb,
+        .write = qlcnic_sysfs_write_crb,
+};
+
+static struct bin_attribute bin_attr_mem = {
+        .attr = {.name = "mem", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_read_mem,
+        .write = qlcnic_sysfs_write_mem,
+};
+
+static int
+validate_pm_config(struct qlcnic_adapter *adapter,
+                        struct qlcnic_pm_func_cfg *pm_cfg, int count)
+{
+
+        u8 src_pci_func, s_esw_id, d_esw_id;
+        u8 dest_pci_func;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                src_pci_func = pm_cfg[i].pci_func;
+                dest_pci_func = pm_cfg[i].dest_npar;
+                if (src_pci_func >= QLCNIC_MAX_PCI_FUNC
+                                || dest_pci_func >= QLCNIC_MAX_PCI_FUNC)
+                        return QL_STATUS_INVALID_PARAM;
+
+                if (adapter->npars[src_pci_func].type != QLCNIC_TYPE_NIC)
+                        return QL_STATUS_INVALID_PARAM;
+
+                if (adapter->npars[dest_pci_func].type != QLCNIC_TYPE_NIC)
+                        return QL_STATUS_INVALID_PARAM;
+
+                s_esw_id = adapter->npars[src_pci_func].phy_port;
+                d_esw_id = adapter->npars[dest_pci_func].phy_port;
+
+                if (s_esw_id != d_esw_id)
+                        return QL_STATUS_INVALID_PARAM;
+
+        }
+        return 0;
+
+}
+
+static ssize_t
+qlcnic_sysfs_write_pm_config(struct file *filp, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_pm_func_cfg *pm_cfg;
+        u32 id, action, pci_func;
+        int count, rem, i, ret;
+
+        count   = size / sizeof(struct qlcnic_pm_func_cfg);
+        rem     = size % sizeof(struct qlcnic_pm_func_cfg);
+        if (rem)
+                return QL_STATUS_INVALID_PARAM;
+
+        pm_cfg = (struct qlcnic_pm_func_cfg *) buf;
+
+        ret = validate_pm_config(adapter, pm_cfg, count);
+        if (ret)
+                return ret;
+        for (i = 0; i < count; i++) {
+                pci_func = pm_cfg[i].pci_func;
+                action = !!pm_cfg[i].action;
+                id = adapter->npars[pci_func].phy_port;
+                ret = qlcnic_config_port_mirroring(adapter, id,
+                                                action, pci_func);
+                if (ret)
+                        return ret;
+        }
+
+        for (i = 0; i < count; i++) {
+                pci_func = pm_cfg[i].pci_func;
+                id = adapter->npars[pci_func].phy_port;
+                adapter->npars[pci_func].enable_pm = !!pm_cfg[i].action;
+                adapter->npars[pci_func].dest_npar = id;
+        }
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_read_pm_config(struct file *filp, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_pm_func_cfg pm_cfg[QLCNIC_MAX_PCI_FUNC];
+        int i;
+
+        if (size != sizeof(pm_cfg))
+                return QL_STATUS_INVALID_PARAM;
+
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
+                if (adapter->npars[i].type != QLCNIC_TYPE_NIC)
+                        continue;
+                pm_cfg[i].action = adapter->npars[i].enable_pm;
+                pm_cfg[i].dest_npar = 0;
+                pm_cfg[i].pci_func = i;
+        }
+        memcpy(buf, &pm_cfg, size);
+
+        return size;
+}
+
+static int
+validate_esw_config(struct qlcnic_adapter *adapter,
+        struct qlcnic_esw_func_cfg *esw_cfg, int count)
+{
+        u32 op_mode;
+        u8 pci_func;
+        int i;
+
+        op_mode = readl(adapter->ahw->pci_base0 + QLCNIC_DRV_OP_MODE);
+
+        for (i = 0; i < count; i++) {
+                pci_func = esw_cfg[i].pci_func;
+                if (pci_func >= QLCNIC_MAX_PCI_FUNC)
+                        return QL_STATUS_INVALID_PARAM;
+
+                if (adapter->op_mode == QLCNIC_MGMT_FUNC)
+                        if (adapter->npars[pci_func].type != QLCNIC_TYPE_NIC)
+                                return QL_STATUS_INVALID_PARAM;
+
+                switch (esw_cfg[i].op_mode) {
+                case QLCNIC_PORT_DEFAULTS:
+                        if (QLC_DEV_GET_DRV(op_mode, pci_func) !=
+                                                QLCNIC_NON_PRIV_FUNC) {
+                                if (esw_cfg[i].mac_anti_spoof != 0)
+                                        return QL_STATUS_INVALID_PARAM;
+                                if (esw_cfg[i].mac_override != 1)
+                                        return QL_STATUS_INVALID_PARAM;
+                                if (esw_cfg[i].promisc_mode != 1)
+                                        return QL_STATUS_INVALID_PARAM;
+                        }
+                        break;
+                case QLCNIC_ADD_VLAN:
+                        if (!IS_VALID_VLAN(esw_cfg[i].vlan_id))
+                                return QL_STATUS_INVALID_PARAM;
+                        if (!esw_cfg[i].op_type)
+                                return QL_STATUS_INVALID_PARAM;
+                        break;
+                case QLCNIC_DEL_VLAN:
+                        if (!esw_cfg[i].op_type)
+                                return QL_STATUS_INVALID_PARAM;
+                        break;
+                default:
+                        return QL_STATUS_INVALID_PARAM;
+                }
+        }
+        return 0;
+}
+
+static ssize_t
+qlcnic_sysfs_write_esw_config(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_esw_func_cfg *esw_cfg;
+        struct qlcnic_npar_info *npar;
+        int count, rem, i, ret;
+        u8 pci_func, op_mode = 0;
+
+        count   = size / sizeof(struct qlcnic_esw_func_cfg);
+        rem     = size % sizeof(struct qlcnic_esw_func_cfg);
+        if (rem)
+                return QL_STATUS_INVALID_PARAM;
+
+        esw_cfg = (struct qlcnic_esw_func_cfg *) buf;
+        ret = validate_esw_config(adapter, esw_cfg, count);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < count; i++) {
+                if (adapter->op_mode == QLCNIC_MGMT_FUNC)
+                        if (qlcnic_config_switch_port(adapter, &esw_cfg[i]))
+                                return QL_STATUS_INVALID_PARAM;
+
+                if (adapter->ahw->pci_func != esw_cfg[i].pci_func)
+                        continue;
+
+                op_mode = esw_cfg[i].op_mode;
+                qlcnic_get_eswitch_port_config(adapter, &esw_cfg[i]);
+                esw_cfg[i].op_mode = op_mode;
+                esw_cfg[i].pci_func = adapter->ahw->pci_func;
+
+                switch (esw_cfg[i].op_mode) {
+                case QLCNIC_PORT_DEFAULTS:
+                        qlcnic_set_eswitch_port_features(adapter, &esw_cfg[i]);
+                        break;
+                case QLCNIC_ADD_VLAN:
+                        qlcnic_set_vlan_config(adapter, &esw_cfg[i]);
+                        break;
+                case QLCNIC_DEL_VLAN:
+                        esw_cfg[i].vlan_id = 0;
+                        qlcnic_set_vlan_config(adapter, &esw_cfg[i]);
+                        break;
+                }
+        }
+
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC)
+                goto out;
+
+        for (i = 0; i < count; i++) {
+                pci_func = esw_cfg[i].pci_func;
+                npar = &adapter->npars[pci_func];
+                switch (esw_cfg[i].op_mode) {
+                case QLCNIC_PORT_DEFAULTS:
+                        npar->promisc_mode = esw_cfg[i].promisc_mode;
+                        npar->mac_override = esw_cfg[i].mac_override;
+                        npar->offload_flags = esw_cfg[i].offload_flags;
+                        npar->mac_anti_spoof = esw_cfg[i].mac_anti_spoof;
+                        npar->discard_tagged = esw_cfg[i].discard_tagged;
+                        break;
+                case QLCNIC_ADD_VLAN:
+                        npar->pvid = esw_cfg[i].vlan_id;
+                        break;
+                case QLCNIC_DEL_VLAN:
+                        npar->pvid = 0;
+                        break;
+                }
+        }
+out:
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_read_esw_config(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_esw_func_cfg esw_cfg[QLCNIC_MAX_PCI_FUNC];
+        u8 i;
+
+        if (size != sizeof(esw_cfg))
+                return QL_STATUS_INVALID_PARAM;
+
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) {
+                if (adapter->npars[i].type != QLCNIC_TYPE_NIC)
+                        continue;
+                esw_cfg[i].pci_func = i;
+                if (qlcnic_get_eswitch_port_config(adapter, &esw_cfg[i]))
+                        return QL_STATUS_INVALID_PARAM;
+        }
+        memcpy(buf, &esw_cfg, size);
+
+        return size;
+}
+
+static int
+validate_npar_config(struct qlcnic_adapter *adapter,
+                                struct qlcnic_npar_func_cfg *np_cfg, int count)
+{
+        u8 pci_func, i;
+
+        for (i = 0; i < count; i++) {
+                pci_func = np_cfg[i].pci_func;
+                if (pci_func >= QLCNIC_MAX_PCI_FUNC)
+                        return QL_STATUS_INVALID_PARAM;
+
+                if (adapter->npars[pci_func].type != QLCNIC_TYPE_NIC)
+                        return QL_STATUS_INVALID_PARAM;
+
+                if (!IS_VALID_BW(np_cfg[i].min_bw) ||
+                    !IS_VALID_BW(np_cfg[i].max_bw))
+                        return QL_STATUS_INVALID_PARAM;
+        }
+        return 0;
+}
+
+static ssize_t
+qlcnic_sysfs_write_npar_config(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_info nic_info;
+        struct qlcnic_npar_func_cfg *np_cfg;
+        int i, count, rem, ret;
+        u8 pci_func;
+
+        count   = size / sizeof(struct qlcnic_npar_func_cfg);
+        rem     = size % sizeof(struct qlcnic_npar_func_cfg);
+        if (rem)
+                return QL_STATUS_INVALID_PARAM;
+
+        np_cfg = (struct qlcnic_npar_func_cfg *) buf;
+        ret = validate_npar_config(adapter, np_cfg, count);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < count ; i++) {
+                pci_func = np_cfg[i].pci_func;
+                ret = qlcnic_get_nic_info(adapter, &nic_info, pci_func);
+                if (ret)
+                        return ret;
+                nic_info.pci_func = pci_func;
+                nic_info.min_tx_bw = np_cfg[i].min_bw;
+                nic_info.max_tx_bw = np_cfg[i].max_bw;
+                ret = qlcnic_set_nic_info(adapter, &nic_info);
+                if (ret)
+                        return ret;
+                adapter->npars[i].min_bw = nic_info.min_tx_bw;
+                adapter->npars[i].max_bw = nic_info.max_tx_bw;
+        }
+
+        return size;
+
+}
+static ssize_t
+qlcnic_sysfs_read_npar_config(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_info nic_info;
+        struct qlcnic_npar_func_cfg np_cfg[QLCNIC_MAX_PCI_FUNC];
+        int i, ret;
+
+        if (size != sizeof(np_cfg))
+                return QL_STATUS_INVALID_PARAM;
+
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC ; i++) {
+                if (adapter->npars[i].type != QLCNIC_TYPE_NIC)
+                        continue;
+                ret = qlcnic_get_nic_info(adapter, &nic_info, i);
+                if (ret)
+                        return ret;
+
+                np_cfg[i].pci_func = i;
+                np_cfg[i].op_mode = (u8)nic_info.op_mode;
+                np_cfg[i].port_num = nic_info.phys_port;
+                np_cfg[i].fw_capab = nic_info.capabilities;
+                np_cfg[i].min_bw = nic_info.min_tx_bw ;
+                np_cfg[i].max_bw = nic_info.max_tx_bw;
+                np_cfg[i].max_tx_queues = nic_info.max_tx_ques;
+                np_cfg[i].max_rx_queues = nic_info.max_rx_ques;
+        }
+        memcpy(buf, &np_cfg, size);
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_get_port_stats(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_esw_statistics port_stats;
+        int ret;
+
+        if (size != sizeof(struct qlcnic_esw_statistics))
+                return QL_STATUS_INVALID_PARAM;
+
+        if (offset >= QLCNIC_MAX_PCI_FUNC)
+                return QL_STATUS_INVALID_PARAM;
+
+        memset(&port_stats, 0, size);
+        ret = qlcnic_get_port_stats(adapter, offset, QLCNIC_QUERY_RX_COUNTER,
+                                                                &port_stats.rx);
+        if (ret)
+                return ret;
+
+        ret = qlcnic_get_port_stats(adapter, offset, QLCNIC_QUERY_TX_COUNTER,
+                                                                &port_stats.tx);
+        if (ret)
+                return ret;
+
+        memcpy(buf, &port_stats, size);
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_get_esw_stats(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_esw_statistics esw_stats;
+        int ret;
+
+        if (size != sizeof(struct qlcnic_esw_statistics))
+                return QL_STATUS_INVALID_PARAM;
+
+        if (offset >= QLCNIC_NIU_MAX_XG_PORTS)
+                return QL_STATUS_INVALID_PARAM;
+
+        memset(&esw_stats, 0, size);
+        ret = qlcnic_get_eswitch_stats(adapter, offset, QLCNIC_QUERY_RX_COUNTER,
+                                                                &esw_stats.rx);
+        if (ret)
+                return ret;
+
+        ret = qlcnic_get_eswitch_stats(adapter, offset, QLCNIC_QUERY_TX_COUNTER,
+                                                                &esw_stats.tx);
+        if (ret)
+                return ret;
+
+        memcpy(buf, &esw_stats, size);
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_clear_esw_stats(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        int ret;
+
+        if (offset >= QLCNIC_NIU_MAX_XG_PORTS)
+                return QL_STATUS_INVALID_PARAM;
+
+        ret = qlcnic_clear_esw_stats(adapter, QLCNIC_STATS_ESWITCH, offset,
+                                                QLCNIC_QUERY_RX_COUNTER);
+        if (ret)
+                return ret;
+
+        ret = qlcnic_clear_esw_stats(adapter, QLCNIC_STATS_ESWITCH, offset,
+                                                QLCNIC_QUERY_TX_COUNTER);
+        if (ret)
+                return ret;
+
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_clear_port_stats(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        int ret;
+
+        if (offset >= QLCNIC_MAX_PCI_FUNC)
+                return QL_STATUS_INVALID_PARAM;
+
+        ret = qlcnic_clear_esw_stats(adapter, QLCNIC_STATS_PORT, offset,
+                                                QLCNIC_QUERY_RX_COUNTER);
+        if (ret)
+                return ret;
+
+        ret = qlcnic_clear_esw_stats(adapter, QLCNIC_STATS_PORT, offset,
+                                                QLCNIC_QUERY_TX_COUNTER);
+        if (ret)
+                return ret;
+
+        return size;
+}
+
+static ssize_t
+qlcnic_sysfs_read_pci_config(struct file *file, struct kobject *kobj,
+        struct bin_attribute *attr, char *buf, loff_t offset, size_t size)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
+        struct qlcnic_pci_func_cfg pci_cfg[QLCNIC_MAX_PCI_FUNC];
+        struct qlcnic_pci_info *pci_info;
+        int i, ret;
+
+        if (size != sizeof(pci_cfg))
+                return QL_STATUS_INVALID_PARAM;
+
+        pci_info = kcalloc(QLCNIC_MAX_PCI_FUNC, sizeof(*pci_info), GFP_KERNEL);
+        if (!pci_info)
+                return -ENOMEM;
+
+        ret = qlcnic_get_pci_info(adapter, pci_info);
+        if (ret) {
+                kfree(pci_info);
+                return ret;
+        }
+
+        for (i = 0; i < QLCNIC_MAX_PCI_FUNC ; i++) {
+                pci_cfg[i].pci_func = pci_info[i].id;
+                pci_cfg[i].func_type = pci_info[i].type;
+                pci_cfg[i].port_num = pci_info[i].default_port;
+                pci_cfg[i].min_bw = pci_info[i].tx_min_bw;
+                pci_cfg[i].max_bw = pci_info[i].tx_max_bw;
+                memcpy(&pci_cfg[i].def_mac_addr, &pci_info[i].mac, ETH_ALEN);
+        }
+        memcpy(buf, &pci_cfg, size);
+        kfree(pci_info);
+        return size;
+}
+static struct bin_attribute bin_attr_npar_config = {
+        .attr = {.name = "npar_config", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_read_npar_config,
+        .write = qlcnic_sysfs_write_npar_config,
+};
+
+static struct bin_attribute bin_attr_pci_config = {
+        .attr = {.name = "pci_config", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_read_pci_config,
+        .write = NULL,
+};
+
+static struct bin_attribute bin_attr_port_stats = {
+        .attr = {.name = "port_stats", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_get_port_stats,
+        .write = qlcnic_sysfs_clear_port_stats,
+};
+
+static struct bin_attribute bin_attr_esw_stats = {
+        .attr = {.name = "esw_stats", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_get_esw_stats,
+        .write = qlcnic_sysfs_clear_esw_stats,
+};
+
+static struct bin_attribute bin_attr_esw_config = {
+        .attr = {.name = "esw_config", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_read_esw_config,
+        .write = qlcnic_sysfs_write_esw_config,
+};
+
+static struct bin_attribute bin_attr_pm_config = {
+        .attr = {.name = "pm_config", .mode = (S_IRUGO | S_IWUSR)},
+        .size = 0,
+        .read = qlcnic_sysfs_read_pm_config,
+        .write = qlcnic_sysfs_write_pm_config,
+};
+
+static void
+qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter)
+{
+        struct device *dev = &adapter->pdev->dev;
+
+        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_BDG)
+                if (device_create_file(dev, &dev_attr_bridged_mode))
+                        dev_warn(dev,
+                                "failed to create bridged_mode sysfs entry\n");
+}
+
+static void
+qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter)
+{
+        struct device *dev = &adapter->pdev->dev;
+
+        if (adapter->capabilities & QLCNIC_FW_CAPABILITY_BDG)
+                device_remove_file(dev, &dev_attr_bridged_mode);
+}
+
+static void
+qlcnic_create_diag_entries(struct qlcnic_adapter *adapter)
+{
+        struct device *dev = &adapter->pdev->dev;
+
+        if (device_create_bin_file(dev, &bin_attr_port_stats))
+                dev_info(dev, "failed to create port stats sysfs entry");
+
+        if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC)
+                return;
+        if (device_create_file(dev, &dev_attr_diag_mode))
+                dev_info(dev, "failed to create diag_mode sysfs entry\n");
+        if (device_create_bin_file(dev, &bin_attr_crb))
+                dev_info(dev, "failed to create crb sysfs entry\n");
+        if (device_create_bin_file(dev, &bin_attr_mem))
+                dev_info(dev, "failed to create mem sysfs entry\n");
+        if (device_create_bin_file(dev, &bin_attr_pci_config))
+                dev_info(dev, "failed to create pci config sysfs entry");
+        if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED))
+                return;
+        if (device_create_bin_file(dev, &bin_attr_esw_config))
+                dev_info(dev, "failed to create esw config sysfs entry");
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC)
+                return;
+        if (device_create_bin_file(dev, &bin_attr_npar_config))
+                dev_info(dev, "failed to create npar config sysfs entry");
+        if (device_create_bin_file(dev, &bin_attr_pm_config))
+                dev_info(dev, "failed to create pm config sysfs entry");
+        if (device_create_bin_file(dev, &bin_attr_esw_stats))
+                dev_info(dev, "failed to create eswitch stats sysfs entry");
+}
+
+static void
+qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter)
+{
+        struct device *dev = &adapter->pdev->dev;
+
+        device_remove_bin_file(dev, &bin_attr_port_stats);
+
+        if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC)
+                return;
+        device_remove_file(dev, &dev_attr_diag_mode);
+        device_remove_bin_file(dev, &bin_attr_crb);
+        device_remove_bin_file(dev, &bin_attr_mem);
+        device_remove_bin_file(dev, &bin_attr_pci_config);
+        if (!(adapter->flags & QLCNIC_ESWITCH_ENABLED))
+                return;
+        device_remove_bin_file(dev, &bin_attr_esw_config);
+        if (adapter->op_mode != QLCNIC_MGMT_FUNC)
+                return;
+        device_remove_bin_file(dev, &bin_attr_npar_config);
+        device_remove_bin_file(dev, &bin_attr_pm_config);
+        device_remove_bin_file(dev, &bin_attr_esw_stats);
+}
+
+#ifdef CONFIG_INET
+
+#define is_qlcnic_netdev(dev) (dev->netdev_ops == &qlcnic_netdev_ops)
+
+static void
+qlcnic_config_indev_addr(struct qlcnic_adapter *adapter,
+                        struct net_device *dev, unsigned long event)
+{
+        struct in_device *indev;
+
+        indev = in_dev_get(dev);
+        if (!indev)
+                return;
+
+        for_ifa(indev) {
+                switch (event) {
+                case NETDEV_UP:
+                        qlcnic_config_ipaddr(adapter,
+                                        ifa->ifa_address, QLCNIC_IP_UP);
+                        break;
+                case NETDEV_DOWN:
+                        qlcnic_config_ipaddr(adapter,
+                                        ifa->ifa_address, QLCNIC_IP_DOWN);
+                        break;
+                default:
+                        break;
+                }
+        } endfor_ifa(indev);
+
+        in_dev_put(indev);
+}
+
+static void
+qlcnic_restore_indev_addr(struct net_device *netdev, unsigned long event)
+{
+        struct qlcnic_adapter *adapter = netdev_priv(netdev);
+        struct net_device *dev;
+        u16 vid;
+
+        qlcnic_config_indev_addr(adapter, netdev, event);
+
+        for_each_set_bit(vid, adapter->vlans, VLAN_N_VID) {
+                dev = __vlan_find_dev_deep(netdev, vid);
+                if (!dev)
+                        continue;
+                qlcnic_config_indev_addr(adapter, dev, event);
+        }
+}
+
+static int qlcnic_netdev_event(struct notifier_block *this,
+                                 unsigned long event, void *ptr)
+{
+        struct qlcnic_adapter *adapter;
+        struct net_device *dev = (struct net_device *)ptr;
+
+recheck:
+        if (dev == NULL)
+                goto done;
+
+        if (dev->priv_flags & IFF_802_1Q_VLAN) {
+                dev = vlan_dev_real_dev(dev);
+                goto recheck;
+        }
+
+        if (!is_qlcnic_netdev(dev))
+                goto done;
+
+        adapter = netdev_priv(dev);
+
+        if (!adapter)
+                goto done;
+
+        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                goto done;
+
+        qlcnic_config_indev_addr(adapter, dev, event);
+done:
+        return NOTIFY_DONE;
+}
+
+static int
+qlcnic_inetaddr_event(struct notifier_block *this,
+                unsigned long event, void *ptr)
+{
+        struct qlcnic_adapter *adapter;
+        struct net_device *dev;
+
+        struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
+
+        dev = ifa->ifa_dev ? ifa->ifa_dev->dev : NULL;
+
+recheck:
+        if (dev == NULL)
+                goto done;
+
+        if (dev->priv_flags & IFF_802_1Q_VLAN) {
+                dev = vlan_dev_real_dev(dev);
+                goto recheck;
+        }
+
+        if (!is_qlcnic_netdev(dev))
+                goto done;
+
+        adapter = netdev_priv(dev);
+
+        if (!adapter)
+                goto done;
+
+        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state))
+                goto done;
+
+        switch (event) {
+        case NETDEV_UP:
+                qlcnic_config_ipaddr(adapter, ifa->ifa_address, QLCNIC_IP_UP);
+                break;
+        case NETDEV_DOWN:
+                qlcnic_config_ipaddr(adapter, ifa->ifa_address, QLCNIC_IP_DOWN);
+                break;
+        default:
+                break;
+        }
+
+done:
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block    qlcnic_netdev_cb = {
+        .notifier_call = qlcnic_netdev_event,
+};
+
+static struct notifier_block qlcnic_inetaddr_cb = {
+        .notifier_call = qlcnic_inetaddr_event,
+};
+#else
+static void
+qlcnic_restore_indev_addr(struct net_device *dev, unsigned long event)
+{ }
+#endif
+static struct pci_error_handlers qlcnic_err_handler = {
+        .error_detected = qlcnic_io_error_detected,
+        .slot_reset = qlcnic_io_slot_reset,
+        .resume = qlcnic_io_resume,
+};
+
+static struct pci_driver qlcnic_driver = {
+        .name = qlcnic_driver_name,
+        .id_table = qlcnic_pci_tbl,
+        .probe = qlcnic_probe,
+        .remove = __devexit_p(qlcnic_remove),
+#ifdef CONFIG_PM
+        .suspend = qlcnic_suspend,
+        .resume = qlcnic_resume,
+#endif
+        .shutdown = qlcnic_shutdown,
+        .err_handler = &qlcnic_err_handler
+
+};
+
+static int __init qlcnic_init_module(void)
+{
+        int ret;
+
+        printk(KERN_INFO "%s\n", qlcnic_driver_string);
+
+        qlcnic_wq = create_singlethread_workqueue("qlcnic");
+        if (qlcnic_wq == NULL) {
+                printk(KERN_ERR "qlcnic: cannot create workqueue\n");
+                return -ENOMEM;
+        }
+
+#ifdef CONFIG_INET
+        register_netdevice_notifier(&qlcnic_netdev_cb);
+        register_inetaddr_notifier(&qlcnic_inetaddr_cb);
+#endif
+
+        ret = pci_register_driver(&qlcnic_driver);
+        if (ret) {
+#ifdef CONFIG_INET
+                unregister_inetaddr_notifier(&qlcnic_inetaddr_cb);
+                unregister_netdevice_notifier(&qlcnic_netdev_cb);
+#endif
+                destroy_workqueue(qlcnic_wq);
+        }
+
+        return ret;
+}
+
+module_init(qlcnic_init_module);
+
+static void __exit qlcnic_exit_module(void)
+{
+
+        pci_unregister_driver(&qlcnic_driver);
+
+#ifdef CONFIG_INET
+        unregister_inetaddr_notifier(&qlcnic_inetaddr_cb);
+        unregister_netdevice_notifier(&qlcnic_netdev_cb);
+#endif
+        destroy_workqueue(qlcnic_wq);
+}
+
+module_exit(qlcnic_exit_module);