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-rw-r--r--drivers/net/netxen/Makefile29
-rw-r--r--drivers/net/netxen/netxen_nic.h1435
-rw-r--r--drivers/net/netxen/netxen_nic_ctx.c793
-rw-r--r--drivers/net/netxen/netxen_nic_ethtool.c835
-rw-r--r--drivers/net/netxen/netxen_nic_hdr.h1050
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c1976
-rw-r--r--drivers/net/netxen/netxen_nic_hw.h287
-rw-r--r--drivers/net/netxen/netxen_nic_init.c1945
-rw-r--r--drivers/net/netxen/netxen_nic_main.c3013
9 files changed, 11363 insertions, 0 deletions
diff --git a/drivers/net/netxen/Makefile b/drivers/net/netxen/Makefile
new file mode 100644
index 00000000000..861a0590b1f
--- /dev/null
+++ b/drivers/net/netxen/Makefile
@@ -0,0 +1,29 @@
1# Copyright (C) 2003 - 2009 NetXen, Inc.
2# Copyright (C) 2009 - QLogic Corporation.
3# All rights reserved.
4#
5# This program is free software; you can redistribute it and/or
6# modify it under the terms of the GNU General Public License
7# as published by the Free Software Foundation; either version 2
8# of the License, or (at your option) any later version.
9#
10# This program is distributed in the hope that it will be useful, but
11# WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15# You should have received a copy of the GNU General Public License
16# along with this program; if not, write to the Free Software
17# Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18# MA 02111-1307, USA.
19#
20# The full GNU General Public License is included in this distribution
21# in the file called "COPYING".
22#
23#
24
25
26obj-$(CONFIG_NETXEN_NIC) := netxen_nic.o
27
28netxen_nic-y := netxen_nic_hw.o netxen_nic_main.o netxen_nic_init.o \
29 netxen_nic_ethtool.o netxen_nic_ctx.o
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
new file mode 100644
index 00000000000..f744d291218
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic.h
@@ -0,0 +1,1435 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#ifndef _NETXEN_NIC_H_
27#define _NETXEN_NIC_H_
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/ioport.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/ip.h>
37#include <linux/in.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/firmware.h>
41
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/timer.h>
45
46#include <linux/vmalloc.h>
47
48#include <asm/io.h>
49#include <asm/byteorder.h>
50
51#include "netxen_nic_hdr.h"
52#include "netxen_nic_hw.h"
53
54#define _NETXEN_NIC_LINUX_MAJOR 4
55#define _NETXEN_NIC_LINUX_MINOR 0
56#define _NETXEN_NIC_LINUX_SUBVERSION 76
57#define NETXEN_NIC_LINUX_VERSIONID "4.0.76"
58
59#define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
60#define _major(v) (((v) >> 24) & 0xff)
61#define _minor(v) (((v) >> 16) & 0xff)
62#define _build(v) ((v) & 0xffff)
63
64/* version in image has weird encoding:
65 * 7:0 - major
66 * 15:8 - minor
67 * 31:16 - build (little endian)
68 */
69#define NETXEN_DECODE_VERSION(v) \
70 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71
72#define NETXEN_NUM_FLASH_SECTORS (64)
73#define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
74#define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
75 * NETXEN_FLASH_SECTOR_SIZE)
76
77#define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79#define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
81#define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83#define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
85#define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
87
88#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
89
90#define NETXEN_RCV_PRODUCER_OFFSET 0
91#define NETXEN_RCV_PEG_DB_ID 2
92#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
93#define FLASH_SUCCESS 0
94
95#define ADDR_IN_WINDOW1(off) \
96 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
97
98#define ADDR_IN_RANGE(addr, low, high) \
99 (((addr) < (high)) && ((addr) >= (low)))
100
101/*
102 * normalize a 64MB crb address to 32MB PCI window
103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
104 */
105#define NETXEN_CRB_NORMAL(reg) \
106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
107
108#define NETXEN_CRB_NORMALIZE(adapter, reg) \
109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
110
111#define DB_NORMALIZE(adapter, off) \
112 (adapter->ahw.db_base + (off))
113
114#define NX_P2_C0 0x24
115#define NX_P2_C1 0x25
116#define NX_P3_A0 0x30
117#define NX_P3_A2 0x30
118#define NX_P3_B0 0x40
119#define NX_P3_B1 0x41
120#define NX_P3_B2 0x42
121#define NX_P3P_A0 0x50
122
123#define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
124#define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
125#define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0)
126
127#define FIRST_PAGE_GROUP_START 0
128#define FIRST_PAGE_GROUP_END 0x100000
129
130#define SECOND_PAGE_GROUP_START 0x6000000
131#define SECOND_PAGE_GROUP_END 0x68BC000
132
133#define THIRD_PAGE_GROUP_START 0x70E4000
134#define THIRD_PAGE_GROUP_END 0x8000000
135
136#define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
137#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
138#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
139
140#define P2_MAX_MTU (8000)
141#define P3_MAX_MTU (9600)
142#define NX_ETHERMTU 1500
143#define NX_MAX_ETHERHDR 32 /* This contains some padding */
144
145#define NX_P2_RX_BUF_MAX_LEN 1760
146#define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
147#define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
148#define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
149#define NX_CT_DEFAULT_RX_BUF_LEN 2048
150#define NX_LRO_BUFFER_EXTRA 2048
151
152#define NX_RX_LRO_BUFFER_LENGTH (8060)
153
154/*
155 * Maximum number of ring contexts
156 */
157#define MAX_RING_CTX 1
158
159/* Opcodes to be used with the commands */
160#define TX_ETHER_PKT 0x01
161#define TX_TCP_PKT 0x02
162#define TX_UDP_PKT 0x03
163#define TX_IP_PKT 0x04
164#define TX_TCP_LSO 0x05
165#define TX_TCP_LSO6 0x06
166#define TX_IPSEC 0x07
167#define TX_IPSEC_CMD 0x0a
168#define TX_TCPV6_PKT 0x0b
169#define TX_UDPV6_PKT 0x0c
170
171/* The following opcodes are for internal consumption. */
172#define NETXEN_CONTROL_OP 0x10
173#define PEGNET_REQUEST 0x11
174
175#define MAX_NUM_CARDS 4
176
177#define NETXEN_MAX_FRAGS_PER_TX 14
178#define MAX_TSO_HEADER_DESC 2
179#define MGMT_CMD_DESC_RESV 4
180#define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
181 + MGMT_CMD_DESC_RESV)
182#define NX_MAX_TX_TIMEOUTS 2
183
184/*
185 * Following are the states of the Phantom. Phantom will set them and
186 * Host will read to check if the fields are correct.
187 */
188#define PHAN_INITIALIZE_START 0xff00
189#define PHAN_INITIALIZE_FAILED 0xffff
190#define PHAN_INITIALIZE_COMPLETE 0xff01
191
192/* Host writes the following to notify that it has done the init-handshake */
193#define PHAN_INITIALIZE_ACK 0xf00f
194
195#define NUM_RCV_DESC_RINGS 3
196#define NUM_STS_DESC_RINGS 4
197
198#define RCV_RING_NORMAL 0
199#define RCV_RING_JUMBO 1
200#define RCV_RING_LRO 2
201
202#define MIN_CMD_DESCRIPTORS 64
203#define MIN_RCV_DESCRIPTORS 64
204#define MIN_JUMBO_DESCRIPTORS 32
205
206#define MAX_CMD_DESCRIPTORS 1024
207#define MAX_RCV_DESCRIPTORS_1G 4096
208#define MAX_RCV_DESCRIPTORS_10G 8192
209#define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
210#define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
211#define MAX_LRO_RCV_DESCRIPTORS 8
212
213#define DEFAULT_RCV_DESCRIPTORS_1G 2048
214#define DEFAULT_RCV_DESCRIPTORS_10G 4096
215
216#define NETXEN_CTX_SIGNATURE 0xdee0
217#define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
218#define NETXEN_CTX_RESET 0xbad0
219#define NETXEN_CTX_D3_RESET 0xacc0
220#define NETXEN_RCV_PRODUCER(ringid) (ringid)
221
222#define PHAN_PEG_RCV_INITIALIZED 0xff01
223#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
224
225#define get_next_index(index, length) \
226 (((index) + 1) & ((length) - 1))
227
228#define get_index_range(index,length,count) \
229 (((index) + (count)) & ((length) - 1))
230
231#define MPORT_SINGLE_FUNCTION_MODE 0x1111
232#define MPORT_MULTI_FUNCTION_MODE 0x2222
233
234#define NX_MAX_PCI_FUNC 8
235
236/*
237 * NetXen host-peg signal message structure
238 *
239 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
240 * Bit 2 : priv_id => must be 1
241 * Bit 3-17 : count => for doorbell
242 * Bit 18-27 : ctx_id => Context id
243 * Bit 28-31 : opcode
244 */
245
246typedef u32 netxen_ctx_msg;
247
248#define netxen_set_msg_peg_id(config_word, val) \
249 ((config_word) &= ~3, (config_word) |= val & 3)
250#define netxen_set_msg_privid(config_word) \
251 ((config_word) |= 1 << 2)
252#define netxen_set_msg_count(config_word, val) \
253 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
254#define netxen_set_msg_ctxid(config_word, val) \
255 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
256#define netxen_set_msg_opcode(config_word, val) \
257 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
258
259struct netxen_rcv_ring {
260 __le64 addr;
261 __le32 size;
262 __le32 rsrvd;
263};
264
265struct netxen_sts_ring {
266 __le64 addr;
267 __le32 size;
268 __le16 msi_index;
269 __le16 rsvd;
270} ;
271
272struct netxen_ring_ctx {
273
274 /* one command ring */
275 __le64 cmd_consumer_offset;
276 __le64 cmd_ring_addr;
277 __le32 cmd_ring_size;
278 __le32 rsrvd;
279
280 /* three receive rings */
281 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
282
283 __le64 sts_ring_addr;
284 __le32 sts_ring_size;
285
286 __le32 ctx_id;
287
288 __le64 rsrvd_2[3];
289 __le32 sts_ring_count;
290 __le32 rsrvd_3;
291 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
292
293} __attribute__ ((aligned(64)));
294
295/*
296 * Following data structures describe the descriptors that will be used.
297 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
298 * we are doing LSO (above the 1500 size packet) only.
299 */
300
301/*
302 * The size of reference handle been changed to 16 bits to pass the MSS fields
303 * for the LSO packet
304 */
305
306#define FLAGS_CHECKSUM_ENABLED 0x01
307#define FLAGS_LSO_ENABLED 0x02
308#define FLAGS_IPSEC_SA_ADD 0x04
309#define FLAGS_IPSEC_SA_DELETE 0x08
310#define FLAGS_VLAN_TAGGED 0x10
311#define FLAGS_VLAN_OOB 0x40
312
313#define netxen_set_tx_vlan_tci(cmd_desc, v) \
314 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
315
316#define netxen_set_cmd_desc_port(cmd_desc, var) \
317 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
318#define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
319 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
320
321#define netxen_set_tx_port(_desc, _port) \
322 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
323
324#define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
325 (_desc)->flags_opcode = \
326 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
327
328#define netxen_set_tx_frags_len(_desc, _frags, _len) \
329 (_desc)->nfrags__length = \
330 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
331
332struct cmd_desc_type0 {
333 u8 tcp_hdr_offset; /* For LSO only */
334 u8 ip_hdr_offset; /* For LSO only */
335 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
336 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
337
338 __le64 addr_buffer2;
339
340 __le16 reference_handle;
341 __le16 mss;
342 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
343 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
344 __le16 conn_id; /* IPSec offoad only */
345
346 __le64 addr_buffer3;
347 __le64 addr_buffer1;
348
349 __le16 buffer_length[4];
350
351 __le64 addr_buffer4;
352
353 __le32 reserved2;
354 __le16 reserved;
355 __le16 vlan_TCI;
356
357} __attribute__ ((aligned(64)));
358
359/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
360struct rcv_desc {
361 __le16 reference_handle;
362 __le16 reserved;
363 __le32 buffer_length; /* allocated buffer length (usually 2K) */
364 __le64 addr_buffer;
365};
366
367/* opcode field in status_desc */
368#define NETXEN_NIC_SYN_OFFLOAD 0x03
369#define NETXEN_NIC_RXPKT_DESC 0x04
370#define NETXEN_OLD_RXPKT_DESC 0x3f
371#define NETXEN_NIC_RESPONSE_DESC 0x05
372#define NETXEN_NIC_LRO_DESC 0x12
373
374/* for status field in status_desc */
375#define STATUS_NEED_CKSUM (1)
376#define STATUS_CKSUM_OK (2)
377
378/* owner bits of status_desc */
379#define STATUS_OWNER_HOST (0x1ULL << 56)
380#define STATUS_OWNER_PHANTOM (0x2ULL << 56)
381
382/* Status descriptor:
383 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
384 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
385 53-55 desc_cnt, 56-57 owner, 58-63 opcode
386 */
387#define netxen_get_sts_port(sts_data) \
388 ((sts_data) & 0x0F)
389#define netxen_get_sts_status(sts_data) \
390 (((sts_data) >> 4) & 0x0F)
391#define netxen_get_sts_type(sts_data) \
392 (((sts_data) >> 8) & 0x0F)
393#define netxen_get_sts_totallength(sts_data) \
394 (((sts_data) >> 12) & 0xFFFF)
395#define netxen_get_sts_refhandle(sts_data) \
396 (((sts_data) >> 28) & 0xFFFF)
397#define netxen_get_sts_prot(sts_data) \
398 (((sts_data) >> 44) & 0x0F)
399#define netxen_get_sts_pkt_offset(sts_data) \
400 (((sts_data) >> 48) & 0x1F)
401#define netxen_get_sts_desc_cnt(sts_data) \
402 (((sts_data) >> 53) & 0x7)
403#define netxen_get_sts_opcode(sts_data) \
404 (((sts_data) >> 58) & 0x03F)
405
406#define netxen_get_lro_sts_refhandle(sts_data) \
407 ((sts_data) & 0x0FFFF)
408#define netxen_get_lro_sts_length(sts_data) \
409 (((sts_data) >> 16) & 0x0FFFF)
410#define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
411 (((sts_data) >> 32) & 0x0FF)
412#define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
413 (((sts_data) >> 40) & 0x0FF)
414#define netxen_get_lro_sts_timestamp(sts_data) \
415 (((sts_data) >> 48) & 0x1)
416#define netxen_get_lro_sts_type(sts_data) \
417 (((sts_data) >> 49) & 0x7)
418#define netxen_get_lro_sts_push_flag(sts_data) \
419 (((sts_data) >> 52) & 0x1)
420#define netxen_get_lro_sts_seq_number(sts_data) \
421 ((sts_data) & 0x0FFFFFFFF)
422
423
424struct status_desc {
425 __le64 status_desc_data[2];
426} __attribute__ ((aligned(16)));
427
428/* UNIFIED ROMIMAGE *************************/
429#define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0
430#define NX_UNI_DIR_SECT_BOOTLD 0x6
431#define NX_UNI_DIR_SECT_FW 0x7
432
433/*Offsets */
434#define NX_UNI_CHIP_REV_OFF 10
435#define NX_UNI_FLAGS_OFF 11
436#define NX_UNI_BIOS_VERSION_OFF 12
437#define NX_UNI_BOOTLD_IDX_OFF 27
438#define NX_UNI_FIRMWARE_IDX_OFF 29
439
440struct uni_table_desc{
441 uint32_t findex;
442 uint32_t num_entries;
443 uint32_t entry_size;
444 uint32_t reserved[5];
445};
446
447struct uni_data_desc{
448 uint32_t findex;
449 uint32_t size;
450 uint32_t reserved[5];
451};
452
453/* UNIFIED ROMIMAGE *************************/
454
455/* The version of the main data structure */
456#define NETXEN_BDINFO_VERSION 1
457
458/* Magic number to let user know flash is programmed */
459#define NETXEN_BDINFO_MAGIC 0x12345678
460
461/* Max number of Gig ports on a Phantom board */
462#define NETXEN_MAX_PORTS 4
463
464#define NETXEN_BRDTYPE_P1_BD 0x0000
465#define NETXEN_BRDTYPE_P1_SB 0x0001
466#define NETXEN_BRDTYPE_P1_SMAX 0x0002
467#define NETXEN_BRDTYPE_P1_SOCK 0x0003
468
469#define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
470#define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
471#define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
472#define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
473#define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
474
475#define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
476#define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
477#define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
478
479#define NETXEN_BRDTYPE_P3_REF_QG 0x0021
480#define NETXEN_BRDTYPE_P3_HMEZ 0x0022
481#define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
482#define NETXEN_BRDTYPE_P3_4_GB 0x0024
483#define NETXEN_BRDTYPE_P3_IMEZ 0x0025
484#define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
485#define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
486#define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
487#define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
488#define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
489#define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
490#define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
491#define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
492#define NETXEN_BRDTYPE_P3_10G_TP 0x0080
493
494/* Flash memory map */
495#define NETXEN_CRBINIT_START 0 /* crbinit section */
496#define NETXEN_BRDCFG_START 0x4000 /* board config */
497#define NETXEN_INITCODE_START 0x6000 /* pegtune code */
498#define NETXEN_BOOTLD_START 0x10000 /* bootld */
499#define NETXEN_IMAGE_START 0x43000 /* compressed image */
500#define NETXEN_SECONDARY_START 0x200000 /* backup images */
501#define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
502#define NETXEN_USER_START 0x3E8000 /* Firmare info */
503#define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
504#define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
505
506#define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
507#define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
508#define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
509#define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
510#define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
511#define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
512
513#define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
514#define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
515#define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
516
517#define NX_FW_MIN_SIZE (0x3fffff)
518#define NX_P2_MN_ROMIMAGE 0
519#define NX_P3_CT_ROMIMAGE 1
520#define NX_P3_MN_ROMIMAGE 2
521#define NX_UNIFIED_ROMIMAGE 3
522#define NX_FLASH_ROMIMAGE 4
523#define NX_UNKNOWN_ROMIMAGE 0xff
524
525#define NX_P2_MN_ROMIMAGE_NAME "nxromimg.bin"
526#define NX_P3_CT_ROMIMAGE_NAME "nx3fwct.bin"
527#define NX_P3_MN_ROMIMAGE_NAME "nx3fwmn.bin"
528#define NX_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
529#define NX_FLASH_ROMIMAGE_NAME "flash"
530
531extern char netxen_nic_driver_name[];
532
533/* Number of status descriptors to handle per interrupt */
534#define MAX_STATUS_HANDLE (64)
535
536/*
537 * netxen_skb_frag{} is to contain mapping info for each SG list. This
538 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
539 */
540struct netxen_skb_frag {
541 u64 dma;
542 u64 length;
543};
544
545struct netxen_recv_crb {
546 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
547 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
548 u32 sw_int_mask[NUM_STS_DESC_RINGS];
549};
550
551/* Following defines are for the state of the buffers */
552#define NETXEN_BUFFER_FREE 0
553#define NETXEN_BUFFER_BUSY 1
554
555/*
556 * There will be one netxen_buffer per skb packet. These will be
557 * used to save the dma info for pci_unmap_page()
558 */
559struct netxen_cmd_buffer {
560 struct sk_buff *skb;
561 struct netxen_skb_frag frag_array[MAX_SKB_FRAGS + 1];
562 u32 frag_count;
563};
564
565/* In rx_buffer, we do not need multiple fragments as is a single buffer */
566struct netxen_rx_buffer {
567 struct list_head list;
568 struct sk_buff *skb;
569 u64 dma;
570 u16 ref_handle;
571 u16 state;
572};
573
574/* Board types */
575#define NETXEN_NIC_GBE 0x01
576#define NETXEN_NIC_XGBE 0x02
577
578/*
579 * One hardware_context{} per adapter
580 * contains interrupt info as well shared hardware info.
581 */
582struct netxen_hardware_context {
583 void __iomem *pci_base0;
584 void __iomem *pci_base1;
585 void __iomem *pci_base2;
586 void __iomem *db_base;
587 void __iomem *ocm_win_crb;
588
589 unsigned long db_len;
590 unsigned long pci_len0;
591
592 u32 ocm_win;
593 u32 crb_win;
594
595 rwlock_t crb_lock;
596 spinlock_t mem_lock;
597
598 u8 cut_through;
599 u8 revision_id;
600 u8 pci_func;
601 u8 linkup;
602 u16 port_type;
603 u16 board_type;
604};
605
606#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
607#define ETHERNET_FCS_SIZE 4
608
609struct netxen_adapter_stats {
610 u64 xmitcalled;
611 u64 xmitfinished;
612 u64 rxdropped;
613 u64 txdropped;
614 u64 csummed;
615 u64 rx_pkts;
616 u64 lro_pkts;
617 u64 rxbytes;
618 u64 txbytes;
619};
620
621/*
622 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
623 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
624 */
625struct nx_host_rds_ring {
626 u32 producer;
627 u32 num_desc;
628 u32 dma_size;
629 u32 skb_size;
630 u32 flags;
631 void __iomem *crb_rcv_producer;
632 struct rcv_desc *desc_head;
633 struct netxen_rx_buffer *rx_buf_arr;
634 struct list_head free_list;
635 spinlock_t lock;
636 dma_addr_t phys_addr;
637};
638
639struct nx_host_sds_ring {
640 u32 consumer;
641 u32 num_desc;
642 void __iomem *crb_sts_consumer;
643 void __iomem *crb_intr_mask;
644
645 struct status_desc *desc_head;
646 struct netxen_adapter *adapter;
647 struct napi_struct napi;
648 struct list_head free_list[NUM_RCV_DESC_RINGS];
649
650 int irq;
651
652 dma_addr_t phys_addr;
653 char name[IFNAMSIZ+4];
654};
655
656struct nx_host_tx_ring {
657 u32 producer;
658 __le32 *hw_consumer;
659 u32 sw_consumer;
660 void __iomem *crb_cmd_producer;
661 void __iomem *crb_cmd_consumer;
662 u32 num_desc;
663
664 struct netdev_queue *txq;
665
666 struct netxen_cmd_buffer *cmd_buf_arr;
667 struct cmd_desc_type0 *desc_head;
668 dma_addr_t phys_addr;
669};
670
671/*
672 * Receive context. There is one such structure per instance of the
673 * receive processing. Any state information that is relevant to
674 * the receive, and is must be in this structure. The global data may be
675 * present elsewhere.
676 */
677struct netxen_recv_context {
678 u32 state;
679 u16 context_id;
680 u16 virt_port;
681
682 struct nx_host_rds_ring *rds_rings;
683 struct nx_host_sds_ring *sds_rings;
684
685 struct netxen_ring_ctx *hwctx;
686 dma_addr_t phys_addr;
687};
688
689/* New HW context creation */
690
691#define NX_OS_CRB_RETRY_COUNT 4000
692#define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
693 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
694
695#define NX_CDRP_CLEAR 0x00000000
696#define NX_CDRP_CMD_BIT 0x80000000
697
698/*
699 * All responses must have the NX_CDRP_CMD_BIT cleared
700 * in the crb NX_CDRP_CRB_OFFSET.
701 */
702#define NX_CDRP_FORM_RSP(rsp) (rsp)
703#define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
704
705#define NX_CDRP_RSP_OK 0x00000001
706#define NX_CDRP_RSP_FAIL 0x00000002
707#define NX_CDRP_RSP_TIMEOUT 0x00000003
708
709/*
710 * All commands must have the NX_CDRP_CMD_BIT set in
711 * the crb NX_CDRP_CRB_OFFSET.
712 */
713#define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
714#define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
715
716#define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
717#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
718#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
719#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
720#define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
721#define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
722#define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
723#define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
724#define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
725#define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
726#define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
727#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
728#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
729#define NX_CDRP_CMD_SET_MTU 0x00000012
730#define NX_CDRP_CMD_READ_PHY 0x00000013
731#define NX_CDRP_CMD_WRITE_PHY 0x00000014
732#define NX_CDRP_CMD_READ_HW_REG 0x00000015
733#define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
734#define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
735#define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
736#define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
737#define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
738#define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
739#define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
740#define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
741#define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
742#define NX_CDRP_CMD_CONFIG_GBE_PORT 0x0000001f
743#define NX_CDRP_CMD_MAX 0x00000020
744
745#define NX_RCODE_SUCCESS 0
746#define NX_RCODE_NO_HOST_MEM 1
747#define NX_RCODE_NO_HOST_RESOURCE 2
748#define NX_RCODE_NO_CARD_CRB 3
749#define NX_RCODE_NO_CARD_MEM 4
750#define NX_RCODE_NO_CARD_RESOURCE 5
751#define NX_RCODE_INVALID_ARGS 6
752#define NX_RCODE_INVALID_ACTION 7
753#define NX_RCODE_INVALID_STATE 8
754#define NX_RCODE_NOT_SUPPORTED 9
755#define NX_RCODE_NOT_PERMITTED 10
756#define NX_RCODE_NOT_READY 11
757#define NX_RCODE_DOES_NOT_EXIST 12
758#define NX_RCODE_ALREADY_EXISTS 13
759#define NX_RCODE_BAD_SIGNATURE 14
760#define NX_RCODE_CMD_NOT_IMPL 15
761#define NX_RCODE_CMD_INVALID 16
762#define NX_RCODE_TIMEOUT 17
763#define NX_RCODE_CMD_FAILED 18
764#define NX_RCODE_MAX_EXCEEDED 19
765#define NX_RCODE_MAX 20
766
767#define NX_DESTROY_CTX_RESET 0
768#define NX_DESTROY_CTX_D3_RESET 1
769#define NX_DESTROY_CTX_MAX 2
770
771/*
772 * Capabilities
773 */
774#define NX_CAP_BIT(class, bit) (1 << bit)
775#define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
776#define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
777#define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
778#define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
779#define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
780#define NX_CAP0_LRO NX_CAP_BIT(0, 5)
781#define NX_CAP0_LSO NX_CAP_BIT(0, 6)
782#define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
783#define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
784#define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
785
786/*
787 * Context state
788 */
789#define NX_HOST_CTX_STATE_FREED 0
790#define NX_HOST_CTX_STATE_ALLOCATED 1
791#define NX_HOST_CTX_STATE_ACTIVE 2
792#define NX_HOST_CTX_STATE_DISABLED 3
793#define NX_HOST_CTX_STATE_QUIESCED 4
794#define NX_HOST_CTX_STATE_MAX 5
795
796/*
797 * Rx context
798 */
799
800typedef struct {
801 __le64 host_phys_addr; /* Ring base addr */
802 __le32 ring_size; /* Ring entries */
803 __le16 msi_index;
804 __le16 rsvd; /* Padding */
805} nx_hostrq_sds_ring_t;
806
807typedef struct {
808 __le64 host_phys_addr; /* Ring base addr */
809 __le64 buff_size; /* Packet buffer size */
810 __le32 ring_size; /* Ring entries */
811 __le32 ring_kind; /* Class of ring */
812} nx_hostrq_rds_ring_t;
813
814typedef struct {
815 __le64 host_rsp_dma_addr; /* Response dma'd here */
816 __le32 capabilities[4]; /* Flag bit vector */
817 __le32 host_int_crb_mode; /* Interrupt crb usage */
818 __le32 host_rds_crb_mode; /* RDS crb usage */
819 /* These ring offsets are relative to data[0] below */
820 __le32 rds_ring_offset; /* Offset to RDS config */
821 __le32 sds_ring_offset; /* Offset to SDS config */
822 __le16 num_rds_rings; /* Count of RDS rings */
823 __le16 num_sds_rings; /* Count of SDS rings */
824 __le16 rsvd1; /* Padding */
825 __le16 rsvd2; /* Padding */
826 u8 reserved[128]; /* reserve space for future expansion*/
827 /* MUST BE 64-bit aligned.
828 The following is packed:
829 - N hostrq_rds_rings
830 - N hostrq_sds_rings */
831 char data[0];
832} nx_hostrq_rx_ctx_t;
833
834typedef struct {
835 __le32 host_producer_crb; /* Crb to use */
836 __le32 rsvd1; /* Padding */
837} nx_cardrsp_rds_ring_t;
838
839typedef struct {
840 __le32 host_consumer_crb; /* Crb to use */
841 __le32 interrupt_crb; /* Crb to use */
842} nx_cardrsp_sds_ring_t;
843
844typedef struct {
845 /* These ring offsets are relative to data[0] below */
846 __le32 rds_ring_offset; /* Offset to RDS config */
847 __le32 sds_ring_offset; /* Offset to SDS config */
848 __le32 host_ctx_state; /* Starting State */
849 __le32 num_fn_per_port; /* How many PCI fn share the port */
850 __le16 num_rds_rings; /* Count of RDS rings */
851 __le16 num_sds_rings; /* Count of SDS rings */
852 __le16 context_id; /* Handle for context */
853 u8 phys_port; /* Physical id of port */
854 u8 virt_port; /* Virtual/Logical id of port */
855 u8 reserved[128]; /* save space for future expansion */
856 /* MUST BE 64-bit aligned.
857 The following is packed:
858 - N cardrsp_rds_rings
859 - N cardrs_sds_rings */
860 char data[0];
861} nx_cardrsp_rx_ctx_t;
862
863#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
864 (sizeof(HOSTRQ_RX) + \
865 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
866 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
867
868#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
869 (sizeof(CARDRSP_RX) + \
870 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
871 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
872
873/*
874 * Tx context
875 */
876
877typedef struct {
878 __le64 host_phys_addr; /* Ring base addr */
879 __le32 ring_size; /* Ring entries */
880 __le32 rsvd; /* Padding */
881} nx_hostrq_cds_ring_t;
882
883typedef struct {
884 __le64 host_rsp_dma_addr; /* Response dma'd here */
885 __le64 cmd_cons_dma_addr; /* */
886 __le64 dummy_dma_addr; /* */
887 __le32 capabilities[4]; /* Flag bit vector */
888 __le32 host_int_crb_mode; /* Interrupt crb usage */
889 __le32 rsvd1; /* Padding */
890 __le16 rsvd2; /* Padding */
891 __le16 interrupt_ctl;
892 __le16 msi_index;
893 __le16 rsvd3; /* Padding */
894 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
895 u8 reserved[128]; /* future expansion */
896} nx_hostrq_tx_ctx_t;
897
898typedef struct {
899 __le32 host_producer_crb; /* Crb to use */
900 __le32 interrupt_crb; /* Crb to use */
901} nx_cardrsp_cds_ring_t;
902
903typedef struct {
904 __le32 host_ctx_state; /* Starting state */
905 __le16 context_id; /* Handle for context */
906 u8 phys_port; /* Physical id of port */
907 u8 virt_port; /* Virtual/Logical id of port */
908 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
909 u8 reserved[128]; /* future expansion */
910} nx_cardrsp_tx_ctx_t;
911
912#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
913#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
914
915/* CRB */
916
917#define NX_HOST_RDS_CRB_MODE_UNIQUE 0
918#define NX_HOST_RDS_CRB_MODE_SHARED 1
919#define NX_HOST_RDS_CRB_MODE_CUSTOM 2
920#define NX_HOST_RDS_CRB_MODE_MAX 3
921
922#define NX_HOST_INT_CRB_MODE_UNIQUE 0
923#define NX_HOST_INT_CRB_MODE_SHARED 1
924#define NX_HOST_INT_CRB_MODE_NORX 2
925#define NX_HOST_INT_CRB_MODE_NOTX 3
926#define NX_HOST_INT_CRB_MODE_NORXTX 4
927
928
929/* MAC */
930
931#define MC_COUNT_P2 16
932#define MC_COUNT_P3 38
933
934#define NETXEN_MAC_NOOP 0
935#define NETXEN_MAC_ADD 1
936#define NETXEN_MAC_DEL 2
937
938typedef struct nx_mac_list_s {
939 struct list_head list;
940 uint8_t mac_addr[ETH_ALEN+2];
941} nx_mac_list_t;
942
943/*
944 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
945 * adjusted based on configured MTU.
946 */
947#define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
948#define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
949#define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
950#define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
951
952#define NETXEN_NIC_INTR_DEFAULT 0x04
953
954typedef union {
955 struct {
956 uint16_t rx_packets;
957 uint16_t rx_time_us;
958 uint16_t tx_packets;
959 uint16_t tx_time_us;
960 } data;
961 uint64_t word;
962} nx_nic_intr_coalesce_data_t;
963
964typedef struct {
965 uint16_t stats_time_us;
966 uint16_t rate_sample_time;
967 uint16_t flags;
968 uint16_t rsvd_1;
969 uint32_t low_threshold;
970 uint32_t high_threshold;
971 nx_nic_intr_coalesce_data_t normal;
972 nx_nic_intr_coalesce_data_t low;
973 nx_nic_intr_coalesce_data_t high;
974 nx_nic_intr_coalesce_data_t irq;
975} nx_nic_intr_coalesce_t;
976
977#define NX_HOST_REQUEST 0x13
978#define NX_NIC_REQUEST 0x14
979
980#define NX_MAC_EVENT 0x1
981
982#define NX_IP_UP 2
983#define NX_IP_DOWN 3
984
985/*
986 * Driver --> Firmware
987 */
988#define NX_NIC_H2C_OPCODE_START 0
989#define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
990#define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
991#define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
992#define NX_NIC_H2C_OPCODE_CONFIG_LED 4
993#define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
994#define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
995#define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
996#define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
997#define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
998#define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
999#define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1000#define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1001#define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1002#define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1003#define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1004#define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1005#define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1006#define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1007#define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1008#define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1009#define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1010#define NX_NIC_C2C_OPCODE 22
1011#define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
1012#define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
1013#define NX_NIC_H2C_OPCODE_LAST 25
1014
1015/*
1016 * Firmware --> Driver
1017 */
1018
1019#define NX_NIC_C2H_OPCODE_START 128
1020#define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1021#define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1022#define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1023#define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1024#define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1025#define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1026#define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1027#define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1028#define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1029#define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1030#define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1031#define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1032#define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1033#define NX_NIC_C2H_OPCODE_LAST 142
1034
1035#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1036#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1037#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1038
1039#define NX_NIC_LRO_REQUEST_FIRST 0
1040#define NX_NIC_LRO_REQUEST_ADD_FLOW 1
1041#define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
1042#define NX_NIC_LRO_REQUEST_TIMER 3
1043#define NX_NIC_LRO_REQUEST_CLEANUP 4
1044#define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1045#define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1046#define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1047#define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1048#define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1049#define NX_TOE_LRO_REQUEST_TIMER 10
1050#define NX_NIC_LRO_REQUEST_LAST 11
1051
1052#define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1053#define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1054#define NX_FW_CAPABILITY_PEXQ (1 << 7)
1055#define NX_FW_CAPABILITY_BDG (1 << 8)
1056#define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1057#define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1058#define NX_FW_CAPABILITY_GBE_LINK_CFG (1 << 11)
1059
1060/* module types */
1061#define LINKEVENT_MODULE_NOT_PRESENT 1
1062#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1063#define LINKEVENT_MODULE_OPTICAL_SRLR 3
1064#define LINKEVENT_MODULE_OPTICAL_LRM 4
1065#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1066#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1067#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1068#define LINKEVENT_MODULE_TWINAX 8
1069
1070#define LINKSPEED_10GBPS 10000
1071#define LINKSPEED_1GBPS 1000
1072#define LINKSPEED_100MBPS 100
1073#define LINKSPEED_10MBPS 10
1074
1075#define LINKSPEED_ENCODED_10MBPS 0
1076#define LINKSPEED_ENCODED_100MBPS 1
1077#define LINKSPEED_ENCODED_1GBPS 2
1078
1079#define LINKEVENT_AUTONEG_DISABLED 0
1080#define LINKEVENT_AUTONEG_ENABLED 1
1081
1082#define LINKEVENT_HALF_DUPLEX 0
1083#define LINKEVENT_FULL_DUPLEX 1
1084
1085#define LINKEVENT_LINKSPEED_MBPS 0
1086#define LINKEVENT_LINKSPEED_ENCODED 1
1087
1088#define AUTO_FW_RESET_ENABLED 0xEF10AF12
1089#define AUTO_FW_RESET_DISABLED 0xDCBAAF12
1090
1091/* firmware response header:
1092 * 63:58 - message type
1093 * 57:56 - owner
1094 * 55:53 - desc count
1095 * 52:48 - reserved
1096 * 47:40 - completion id
1097 * 39:32 - opcode
1098 * 31:16 - error code
1099 * 15:00 - reserved
1100 */
1101#define netxen_get_nic_msgtype(msg_hdr) \
1102 ((msg_hdr >> 58) & 0x3F)
1103#define netxen_get_nic_msg_compid(msg_hdr) \
1104 ((msg_hdr >> 40) & 0xFF)
1105#define netxen_get_nic_msg_opcode(msg_hdr) \
1106 ((msg_hdr >> 32) & 0xFF)
1107#define netxen_get_nic_msg_errcode(msg_hdr) \
1108 ((msg_hdr >> 16) & 0xFFFF)
1109
1110typedef struct {
1111 union {
1112 struct {
1113 u64 hdr;
1114 u64 body[7];
1115 };
1116 u64 words[8];
1117 };
1118} nx_fw_msg_t;
1119
1120typedef struct {
1121 __le64 qhdr;
1122 __le64 req_hdr;
1123 __le64 words[6];
1124} nx_nic_req_t;
1125
1126typedef struct {
1127 u8 op;
1128 u8 tag;
1129 u8 mac_addr[6];
1130} nx_mac_req_t;
1131
1132#define MAX_PENDING_DESC_BLOCK_SIZE 64
1133
1134#define NETXEN_NIC_MSI_ENABLED 0x02
1135#define NETXEN_NIC_MSIX_ENABLED 0x04
1136#define NETXEN_NIC_LRO_ENABLED 0x08
1137#define NETXEN_NIC_LRO_DISABLED 0x00
1138#define NETXEN_NIC_BRIDGE_ENABLED 0X10
1139#define NETXEN_NIC_DIAG_ENABLED 0x20
1140#define NETXEN_IS_MSI_FAMILY(adapter) \
1141 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1142
1143#define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1144#define NETXEN_MSIX_TBL_SPACE 8192
1145#define NETXEN_PCI_REG_MSIX_TBL 0x44
1146
1147#define NETXEN_DB_MAPSIZE_BYTES 0x1000
1148
1149#define NETXEN_NETDEV_WEIGHT 128
1150#define NETXEN_ADAPTER_UP_MAGIC 777
1151#define NETXEN_NIC_PEG_TUNE 0
1152
1153#define __NX_FW_ATTACHED 0
1154#define __NX_DEV_UP 1
1155#define __NX_RESETTING 2
1156
1157struct netxen_dummy_dma {
1158 void *addr;
1159 dma_addr_t phys_addr;
1160};
1161
1162struct netxen_adapter {
1163 struct netxen_hardware_context ahw;
1164
1165 struct net_device *netdev;
1166 struct pci_dev *pdev;
1167 struct list_head mac_list;
1168
1169 spinlock_t tx_clean_lock;
1170
1171 u16 num_txd;
1172 u16 num_rxd;
1173 u16 num_jumbo_rxd;
1174 u16 num_lro_rxd;
1175
1176 u8 max_rds_rings;
1177 u8 max_sds_rings;
1178 u8 driver_mismatch;
1179 u8 msix_supported;
1180 u8 __pad;
1181 u8 pci_using_dac;
1182 u8 portnum;
1183 u8 physical_port;
1184
1185 u8 mc_enabled;
1186 u8 max_mc_count;
1187 u8 rss_supported;
1188 u8 link_changed;
1189 u8 fw_wait_cnt;
1190 u8 fw_fail_cnt;
1191 u8 tx_timeo_cnt;
1192 u8 need_fw_reset;
1193
1194 u8 has_link_events;
1195 u8 fw_type;
1196 u16 tx_context_id;
1197 u16 mtu;
1198 u16 is_up;
1199
1200 u16 link_speed;
1201 u16 link_duplex;
1202 u16 link_autoneg;
1203 u16 module_type;
1204
1205 u32 capabilities;
1206 u32 flags;
1207 u32 irq;
1208 u32 temp;
1209
1210 u32 int_vec_bit;
1211 u32 heartbit;
1212
1213 u8 mac_addr[ETH_ALEN];
1214
1215 struct netxen_adapter_stats stats;
1216
1217 struct netxen_recv_context recv_ctx;
1218 struct nx_host_tx_ring *tx_ring;
1219
1220 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1221 int (*set_mtu) (struct netxen_adapter *, int);
1222 int (*set_promisc) (struct netxen_adapter *, u32);
1223 void (*set_multi) (struct net_device *);
1224 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1225 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1226 int (*init_port) (struct netxen_adapter *, int);
1227 int (*stop_port) (struct netxen_adapter *);
1228
1229 u32 (*crb_read)(struct netxen_adapter *, ulong);
1230 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1231
1232 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
1233 int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
1234
1235 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *);
1236
1237 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1238 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1239
1240 void __iomem *tgt_mask_reg;
1241 void __iomem *pci_int_reg;
1242 void __iomem *tgt_status_reg;
1243 void __iomem *crb_int_state_reg;
1244 void __iomem *isr_int_vec;
1245
1246 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1247
1248 struct netxen_dummy_dma dummy_dma;
1249
1250 struct delayed_work fw_work;
1251
1252 struct work_struct tx_timeout_task;
1253
1254 nx_nic_intr_coalesce_t coal;
1255
1256 unsigned long state;
1257 __le32 file_prd_off; /*File fw product offset*/
1258 u32 fw_version;
1259 const struct firmware *fw;
1260};
1261
1262int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1263int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1264
1265#define NXRD32(adapter, off) \
1266 (adapter->crb_read(adapter, off))
1267#define NXWR32(adapter, off, val) \
1268 (adapter->crb_write(adapter, off, val))
1269#define NXRDIO(adapter, addr) \
1270 (adapter->io_read(adapter, addr))
1271#define NXWRIO(adapter, addr, val) \
1272 (adapter->io_write(adapter, addr, val))
1273
1274int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1275void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1276
1277#define netxen_rom_lock(a) \
1278 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1279#define netxen_rom_unlock(a) \
1280 netxen_pcie_sem_unlock((a), 2)
1281#define netxen_phy_lock(a) \
1282 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1283#define netxen_phy_unlock(a) \
1284 netxen_pcie_sem_unlock((a), 3)
1285#define netxen_api_lock(a) \
1286 netxen_pcie_sem_lock((a), 5, 0)
1287#define netxen_api_unlock(a) \
1288 netxen_pcie_sem_unlock((a), 5)
1289#define netxen_sw_lock(a) \
1290 netxen_pcie_sem_lock((a), 6, 0)
1291#define netxen_sw_unlock(a) \
1292 netxen_pcie_sem_unlock((a), 6)
1293#define crb_win_lock(a) \
1294 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1295#define crb_win_unlock(a) \
1296 netxen_pcie_sem_unlock((a), 7)
1297
1298int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1299int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1300
1301/* Functions from netxen_nic_init.c */
1302int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1303void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1304
1305int netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter);
1306int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1307int netxen_load_firmware(struct netxen_adapter *adapter);
1308int netxen_need_fw_reset(struct netxen_adapter *adapter);
1309void netxen_request_firmware(struct netxen_adapter *adapter);
1310void netxen_release_firmware(struct netxen_adapter *adapter);
1311int netxen_pinit_from_rom(struct netxen_adapter *adapter);
1312
1313int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1314int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1315 u8 *bytes, size_t size);
1316int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1317 u8 *bytes, size_t size);
1318int netxen_flash_unlock(struct netxen_adapter *adapter);
1319int netxen_backup_crbinit(struct netxen_adapter *adapter);
1320int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1321int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1322void netxen_halt_pegs(struct netxen_adapter *adapter);
1323
1324int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1325
1326int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1327void netxen_free_sw_resources(struct netxen_adapter *adapter);
1328
1329void netxen_setup_hwops(struct netxen_adapter *adapter);
1330void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1331
1332int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1333void netxen_free_hw_resources(struct netxen_adapter *adapter);
1334
1335void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1336void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1337
1338int netxen_init_firmware(struct netxen_adapter *adapter);
1339void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1340void netxen_watchdog_task(struct work_struct *work);
1341void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1342 struct nx_host_rds_ring *rds_ring);
1343int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1344int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1345
1346void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1347int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1348int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1349int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1350int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1351void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1352void netxen_pci_camqm_read_2M(struct netxen_adapter *, u64, u64 *);
1353void netxen_pci_camqm_write_2M(struct netxen_adapter *, u64, u64);
1354
1355int nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
1356 u32 speed, u32 duplex, u32 autoneg);
1357int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1358int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1359int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1360int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1361int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1362
1363void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1364 struct nx_host_tx_ring *tx_ring);
1365
1366/* Functions from netxen_nic_main.c */
1367int netxen_nic_reset_context(struct netxen_adapter *);
1368
1369/*
1370 * NetXen Board information
1371 */
1372
1373#define NETXEN_MAX_SHORT_NAME 32
1374struct netxen_brdinfo {
1375 int brdtype; /* type of board */
1376 long ports; /* max no of physical ports */
1377 char short_name[NETXEN_MAX_SHORT_NAME];
1378};
1379
1380static const struct netxen_brdinfo netxen_boards[] = {
1381 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1382 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1383 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1384 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1385 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1386 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1387 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1388 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1389 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1390 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1391 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1392 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1393 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1394 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1395 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1396 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1397 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1398 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1399 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1400};
1401
1402#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1403
1404static inline void get_brd_name_by_type(u32 type, char *name)
1405{
1406 int i, found = 0;
1407 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1408 if (netxen_boards[i].brdtype == type) {
1409 strcpy(name, netxen_boards[i].short_name);
1410 found = 1;
1411 break;
1412 }
1413
1414 }
1415 if (!found)
1416 name = "Unknown";
1417}
1418
1419static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1420{
1421 smp_mb();
1422 return find_diff_among(tx_ring->producer,
1423 tx_ring->sw_consumer, tx_ring->num_desc);
1424
1425}
1426
1427int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1428int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1429extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1430extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1431 int *valp);
1432
1433extern const struct ethtool_ops netxen_nic_ethtool_ops;
1434
1435#endif /* __NETXEN_NIC_H_ */
diff --git a/drivers/net/netxen/netxen_nic_ctx.c b/drivers/net/netxen/netxen_nic_ctx.c
new file mode 100644
index 00000000000..a925392abd6
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_ctx.c
@@ -0,0 +1,793 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#include "netxen_nic_hw.h"
27#include "netxen_nic.h"
28
29#define NXHAL_VERSION 1
30
31static u32
32netxen_poll_rsp(struct netxen_adapter *adapter)
33{
34 u32 rsp = NX_CDRP_RSP_OK;
35 int timeout = 0;
36
37 do {
38 /* give atleast 1ms for firmware to respond */
39 msleep(1);
40
41 if (++timeout > NX_OS_CRB_RETRY_COUNT)
42 return NX_CDRP_RSP_TIMEOUT;
43
44 rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
45 } while (!NX_CDRP_IS_RSP(rsp));
46
47 return rsp;
48}
49
50static u32
51netxen_issue_cmd(struct netxen_adapter *adapter,
52 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
53{
54 u32 rsp;
55 u32 signature = 0;
56 u32 rcode = NX_RCODE_SUCCESS;
57
58 signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version);
59
60 /* Acquire semaphore before accessing CRB */
61 if (netxen_api_lock(adapter))
62 return NX_RCODE_TIMEOUT;
63
64 NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
65
66 NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1);
67
68 NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2);
69
70 NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3);
71
72 NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd));
73
74 rsp = netxen_poll_rsp(adapter);
75
76 if (rsp == NX_CDRP_RSP_TIMEOUT) {
77 printk(KERN_ERR "%s: card response timeout.\n",
78 netxen_nic_driver_name);
79
80 rcode = NX_RCODE_TIMEOUT;
81 } else if (rsp == NX_CDRP_RSP_FAIL) {
82 rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
83
84 printk(KERN_ERR "%s: failed card response code:0x%x\n",
85 netxen_nic_driver_name, rcode);
86 }
87
88 /* Release semaphore */
89 netxen_api_unlock(adapter);
90
91 return rcode;
92}
93
94int
95nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu)
96{
97 u32 rcode = NX_RCODE_SUCCESS;
98 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
99
100 if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE)
101 rcode = netxen_issue_cmd(adapter,
102 adapter->ahw.pci_func,
103 NXHAL_VERSION,
104 recv_ctx->context_id,
105 mtu,
106 0,
107 NX_CDRP_CMD_SET_MTU);
108
109 if (rcode != NX_RCODE_SUCCESS)
110 return -EIO;
111
112 return 0;
113}
114
115int
116nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
117 u32 speed, u32 duplex, u32 autoneg)
118{
119
120 return netxen_issue_cmd(adapter,
121 adapter->ahw.pci_func,
122 NXHAL_VERSION,
123 speed,
124 duplex,
125 autoneg,
126 NX_CDRP_CMD_CONFIG_GBE_PORT);
127
128}
129
130static int
131nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
132{
133 void *addr;
134 nx_hostrq_rx_ctx_t *prq;
135 nx_cardrsp_rx_ctx_t *prsp;
136 nx_hostrq_rds_ring_t *prq_rds;
137 nx_hostrq_sds_ring_t *prq_sds;
138 nx_cardrsp_rds_ring_t *prsp_rds;
139 nx_cardrsp_sds_ring_t *prsp_sds;
140 struct nx_host_rds_ring *rds_ring;
141 struct nx_host_sds_ring *sds_ring;
142
143 dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
144 u64 phys_addr;
145
146 int i, nrds_rings, nsds_rings;
147 size_t rq_size, rsp_size;
148 u32 cap, reg, val;
149
150 int err;
151
152 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
153
154 nrds_rings = adapter->max_rds_rings;
155 nsds_rings = adapter->max_sds_rings;
156
157 rq_size =
158 SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings);
159 rsp_size =
160 SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings);
161
162 addr = pci_alloc_consistent(adapter->pdev,
163 rq_size, &hostrq_phys_addr);
164 if (addr == NULL)
165 return -ENOMEM;
166 prq = addr;
167
168 addr = pci_alloc_consistent(adapter->pdev,
169 rsp_size, &cardrsp_phys_addr);
170 if (addr == NULL) {
171 err = -ENOMEM;
172 goto out_free_rq;
173 }
174 prsp = addr;
175
176 prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
177
178 cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN);
179 cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS);
180
181 prq->capabilities[0] = cpu_to_le32(cap);
182 prq->host_int_crb_mode =
183 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
184 prq->host_rds_crb_mode =
185 cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE);
186
187 prq->num_rds_rings = cpu_to_le16(nrds_rings);
188 prq->num_sds_rings = cpu_to_le16(nsds_rings);
189 prq->rds_ring_offset = cpu_to_le32(0);
190
191 val = le32_to_cpu(prq->rds_ring_offset) +
192 (sizeof(nx_hostrq_rds_ring_t) * nrds_rings);
193 prq->sds_ring_offset = cpu_to_le32(val);
194
195 prq_rds = (nx_hostrq_rds_ring_t *)(prq->data +
196 le32_to_cpu(prq->rds_ring_offset));
197
198 for (i = 0; i < nrds_rings; i++) {
199
200 rds_ring = &recv_ctx->rds_rings[i];
201
202 prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
203 prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
204 prq_rds[i].ring_kind = cpu_to_le32(i);
205 prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
206 }
207
208 prq_sds = (nx_hostrq_sds_ring_t *)(prq->data +
209 le32_to_cpu(prq->sds_ring_offset));
210
211 for (i = 0; i < nsds_rings; i++) {
212
213 sds_ring = &recv_ctx->sds_rings[i];
214
215 prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
216 prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
217 prq_sds[i].msi_index = cpu_to_le16(i);
218 }
219
220 phys_addr = hostrq_phys_addr;
221 err = netxen_issue_cmd(adapter,
222 adapter->ahw.pci_func,
223 NXHAL_VERSION,
224 (u32)(phys_addr >> 32),
225 (u32)(phys_addr & 0xffffffff),
226 rq_size,
227 NX_CDRP_CMD_CREATE_RX_CTX);
228 if (err) {
229 printk(KERN_WARNING
230 "Failed to create rx ctx in firmware%d\n", err);
231 goto out_free_rsp;
232 }
233
234
235 prsp_rds = ((nx_cardrsp_rds_ring_t *)
236 &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
237
238 for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
239 rds_ring = &recv_ctx->rds_rings[i];
240
241 reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
242 rds_ring->crb_rcv_producer = netxen_get_ioaddr(adapter,
243 NETXEN_NIC_REG(reg - 0x200));
244 }
245
246 prsp_sds = ((nx_cardrsp_sds_ring_t *)
247 &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
248
249 for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
250 sds_ring = &recv_ctx->sds_rings[i];
251
252 reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
253 sds_ring->crb_sts_consumer = netxen_get_ioaddr(adapter,
254 NETXEN_NIC_REG(reg - 0x200));
255
256 reg = le32_to_cpu(prsp_sds[i].interrupt_crb);
257 sds_ring->crb_intr_mask = netxen_get_ioaddr(adapter,
258 NETXEN_NIC_REG(reg - 0x200));
259 }
260
261 recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
262 recv_ctx->context_id = le16_to_cpu(prsp->context_id);
263 recv_ctx->virt_port = prsp->virt_port;
264
265out_free_rsp:
266 pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
267out_free_rq:
268 pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
269 return err;
270}
271
272static void
273nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
274{
275 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
276
277 if (netxen_issue_cmd(adapter,
278 adapter->ahw.pci_func,
279 NXHAL_VERSION,
280 recv_ctx->context_id,
281 NX_DESTROY_CTX_RESET,
282 0,
283 NX_CDRP_CMD_DESTROY_RX_CTX)) {
284
285 printk(KERN_WARNING
286 "%s: Failed to destroy rx ctx in firmware\n",
287 netxen_nic_driver_name);
288 }
289}
290
291static int
292nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
293{
294 nx_hostrq_tx_ctx_t *prq;
295 nx_hostrq_cds_ring_t *prq_cds;
296 nx_cardrsp_tx_ctx_t *prsp;
297 void *rq_addr, *rsp_addr;
298 size_t rq_size, rsp_size;
299 u32 temp;
300 int err = 0;
301 u64 offset, phys_addr;
302 dma_addr_t rq_phys_addr, rsp_phys_addr;
303 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
304 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
305
306 rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
307 rq_addr = pci_alloc_consistent(adapter->pdev,
308 rq_size, &rq_phys_addr);
309 if (!rq_addr)
310 return -ENOMEM;
311
312 rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t);
313 rsp_addr = pci_alloc_consistent(adapter->pdev,
314 rsp_size, &rsp_phys_addr);
315 if (!rsp_addr) {
316 err = -ENOMEM;
317 goto out_free_rq;
318 }
319
320 memset(rq_addr, 0, rq_size);
321 prq = rq_addr;
322
323 memset(rsp_addr, 0, rsp_size);
324 prsp = rsp_addr;
325
326 prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
327
328 temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO);
329 prq->capabilities[0] = cpu_to_le32(temp);
330
331 prq->host_int_crb_mode =
332 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
333
334 prq->interrupt_ctl = 0;
335 prq->msi_index = 0;
336
337 prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr);
338
339 offset = recv_ctx->phys_addr + sizeof(struct netxen_ring_ctx);
340 prq->cmd_cons_dma_addr = cpu_to_le64(offset);
341
342 prq_cds = &prq->cds_ring;
343
344 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
345 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
346
347 phys_addr = rq_phys_addr;
348 err = netxen_issue_cmd(adapter,
349 adapter->ahw.pci_func,
350 NXHAL_VERSION,
351 (u32)(phys_addr >> 32),
352 ((u32)phys_addr & 0xffffffff),
353 rq_size,
354 NX_CDRP_CMD_CREATE_TX_CTX);
355
356 if (err == NX_RCODE_SUCCESS) {
357 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
358 tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter,
359 NETXEN_NIC_REG(temp - 0x200));
360#if 0
361 adapter->tx_state =
362 le32_to_cpu(prsp->host_ctx_state);
363#endif
364 adapter->tx_context_id =
365 le16_to_cpu(prsp->context_id);
366 } else {
367 printk(KERN_WARNING
368 "Failed to create tx ctx in firmware%d\n", err);
369 err = -EIO;
370 }
371
372 pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
373
374out_free_rq:
375 pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
376
377 return err;
378}
379
380static void
381nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
382{
383 if (netxen_issue_cmd(adapter,
384 adapter->ahw.pci_func,
385 NXHAL_VERSION,
386 adapter->tx_context_id,
387 NX_DESTROY_CTX_RESET,
388 0,
389 NX_CDRP_CMD_DESTROY_TX_CTX)) {
390
391 printk(KERN_WARNING
392 "%s: Failed to destroy tx ctx in firmware\n",
393 netxen_nic_driver_name);
394 }
395}
396
397int
398nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val)
399{
400 u32 rcode;
401
402 rcode = netxen_issue_cmd(adapter,
403 adapter->ahw.pci_func,
404 NXHAL_VERSION,
405 reg,
406 0,
407 0,
408 NX_CDRP_CMD_READ_PHY);
409
410 if (rcode != NX_RCODE_SUCCESS)
411 return -EIO;
412
413 return NXRD32(adapter, NX_ARG1_CRB_OFFSET);
414}
415
416int
417nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val)
418{
419 u32 rcode;
420
421 rcode = netxen_issue_cmd(adapter,
422 adapter->ahw.pci_func,
423 NXHAL_VERSION,
424 reg,
425 val,
426 0,
427 NX_CDRP_CMD_WRITE_PHY);
428
429 if (rcode != NX_RCODE_SUCCESS)
430 return -EIO;
431
432 return 0;
433}
434
435static u64 ctx_addr_sig_regs[][3] = {
436 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
437 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
438 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
439 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
440};
441
442#define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
443#define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
444#define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
445
446#define lower32(x) ((u32)((x) & 0xffffffff))
447#define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff))
448
449static struct netxen_recv_crb recv_crb_registers[] = {
450 /* Instance 0 */
451 {
452 /* crb_rcv_producer: */
453 {
454 NETXEN_NIC_REG(0x100),
455 /* Jumbo frames */
456 NETXEN_NIC_REG(0x110),
457 /* LRO */
458 NETXEN_NIC_REG(0x120)
459 },
460 /* crb_sts_consumer: */
461 {
462 NETXEN_NIC_REG(0x138),
463 NETXEN_NIC_REG_2(0x000),
464 NETXEN_NIC_REG_2(0x004),
465 NETXEN_NIC_REG_2(0x008),
466 },
467 /* sw_int_mask */
468 {
469 CRB_SW_INT_MASK_0,
470 NETXEN_NIC_REG_2(0x044),
471 NETXEN_NIC_REG_2(0x048),
472 NETXEN_NIC_REG_2(0x04c),
473 },
474 },
475 /* Instance 1 */
476 {
477 /* crb_rcv_producer: */
478 {
479 NETXEN_NIC_REG(0x144),
480 /* Jumbo frames */
481 NETXEN_NIC_REG(0x154),
482 /* LRO */
483 NETXEN_NIC_REG(0x164)
484 },
485 /* crb_sts_consumer: */
486 {
487 NETXEN_NIC_REG(0x17c),
488 NETXEN_NIC_REG_2(0x020),
489 NETXEN_NIC_REG_2(0x024),
490 NETXEN_NIC_REG_2(0x028),
491 },
492 /* sw_int_mask */
493 {
494 CRB_SW_INT_MASK_1,
495 NETXEN_NIC_REG_2(0x064),
496 NETXEN_NIC_REG_2(0x068),
497 NETXEN_NIC_REG_2(0x06c),
498 },
499 },
500 /* Instance 2 */
501 {
502 /* crb_rcv_producer: */
503 {
504 NETXEN_NIC_REG(0x1d8),
505 /* Jumbo frames */
506 NETXEN_NIC_REG(0x1f8),
507 /* LRO */
508 NETXEN_NIC_REG(0x208)
509 },
510 /* crb_sts_consumer: */
511 {
512 NETXEN_NIC_REG(0x220),
513 NETXEN_NIC_REG_2(0x03c),
514 NETXEN_NIC_REG_2(0x03c),
515 NETXEN_NIC_REG_2(0x03c),
516 },
517 /* sw_int_mask */
518 {
519 CRB_SW_INT_MASK_2,
520 NETXEN_NIC_REG_2(0x03c),
521 NETXEN_NIC_REG_2(0x03c),
522 NETXEN_NIC_REG_2(0x03c),
523 },
524 },
525 /* Instance 3 */
526 {
527 /* crb_rcv_producer: */
528 {
529 NETXEN_NIC_REG(0x22c),
530 /* Jumbo frames */
531 NETXEN_NIC_REG(0x23c),
532 /* LRO */
533 NETXEN_NIC_REG(0x24c)
534 },
535 /* crb_sts_consumer: */
536 {
537 NETXEN_NIC_REG(0x264),
538 NETXEN_NIC_REG_2(0x03c),
539 NETXEN_NIC_REG_2(0x03c),
540 NETXEN_NIC_REG_2(0x03c),
541 },
542 /* sw_int_mask */
543 {
544 CRB_SW_INT_MASK_3,
545 NETXEN_NIC_REG_2(0x03c),
546 NETXEN_NIC_REG_2(0x03c),
547 NETXEN_NIC_REG_2(0x03c),
548 },
549 },
550};
551
552static int
553netxen_init_old_ctx(struct netxen_adapter *adapter)
554{
555 struct netxen_recv_context *recv_ctx;
556 struct nx_host_rds_ring *rds_ring;
557 struct nx_host_sds_ring *sds_ring;
558 struct nx_host_tx_ring *tx_ring;
559 int ring;
560 int port = adapter->portnum;
561 struct netxen_ring_ctx *hwctx;
562 u32 signature;
563
564 tx_ring = adapter->tx_ring;
565 recv_ctx = &adapter->recv_ctx;
566 hwctx = recv_ctx->hwctx;
567
568 hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr);
569 hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc);
570
571
572 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
573 rds_ring = &recv_ctx->rds_rings[ring];
574
575 hwctx->rcv_rings[ring].addr =
576 cpu_to_le64(rds_ring->phys_addr);
577 hwctx->rcv_rings[ring].size =
578 cpu_to_le32(rds_ring->num_desc);
579 }
580
581 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
582 sds_ring = &recv_ctx->sds_rings[ring];
583
584 if (ring == 0) {
585 hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
586 hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
587 }
588 hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr);
589 hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc);
590 hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring);
591 }
592 hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings);
593
594 signature = (adapter->max_sds_rings > 1) ?
595 NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE;
596
597 NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port),
598 lower32(recv_ctx->phys_addr));
599 NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port),
600 upper32(recv_ctx->phys_addr));
601 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
602 signature | port);
603 return 0;
604}
605
606int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
607{
608 void *addr;
609 int err = 0;
610 int ring;
611 struct netxen_recv_context *recv_ctx;
612 struct nx_host_rds_ring *rds_ring;
613 struct nx_host_sds_ring *sds_ring;
614 struct nx_host_tx_ring *tx_ring;
615
616 struct pci_dev *pdev = adapter->pdev;
617 struct net_device *netdev = adapter->netdev;
618 int port = adapter->portnum;
619
620 recv_ctx = &adapter->recv_ctx;
621 tx_ring = adapter->tx_ring;
622
623 addr = pci_alloc_consistent(pdev,
624 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
625 &recv_ctx->phys_addr);
626 if (addr == NULL) {
627 dev_err(&pdev->dev, "failed to allocate hw context\n");
628 return -ENOMEM;
629 }
630
631 memset(addr, 0, sizeof(struct netxen_ring_ctx));
632 recv_ctx->hwctx = addr;
633 recv_ctx->hwctx->ctx_id = cpu_to_le32(port);
634 recv_ctx->hwctx->cmd_consumer_offset =
635 cpu_to_le64(recv_ctx->phys_addr +
636 sizeof(struct netxen_ring_ctx));
637 tx_ring->hw_consumer =
638 (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
639
640 /* cmd desc ring */
641 addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
642 &tx_ring->phys_addr);
643
644 if (addr == NULL) {
645 dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n",
646 netdev->name);
647 err = -ENOMEM;
648 goto err_out_free;
649 }
650
651 tx_ring->desc_head = addr;
652
653 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
654 rds_ring = &recv_ctx->rds_rings[ring];
655 addr = pci_alloc_consistent(adapter->pdev,
656 RCV_DESC_RINGSIZE(rds_ring),
657 &rds_ring->phys_addr);
658 if (addr == NULL) {
659 dev_err(&pdev->dev,
660 "%s: failed to allocate rds ring [%d]\n",
661 netdev->name, ring);
662 err = -ENOMEM;
663 goto err_out_free;
664 }
665 rds_ring->desc_head = addr;
666
667 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
668 rds_ring->crb_rcv_producer =
669 netxen_get_ioaddr(adapter,
670 recv_crb_registers[port].crb_rcv_producer[ring]);
671 }
672
673 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
674 sds_ring = &recv_ctx->sds_rings[ring];
675
676 addr = pci_alloc_consistent(adapter->pdev,
677 STATUS_DESC_RINGSIZE(sds_ring),
678 &sds_ring->phys_addr);
679 if (addr == NULL) {
680 dev_err(&pdev->dev,
681 "%s: failed to allocate sds ring [%d]\n",
682 netdev->name, ring);
683 err = -ENOMEM;
684 goto err_out_free;
685 }
686 sds_ring->desc_head = addr;
687
688 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
689 sds_ring->crb_sts_consumer =
690 netxen_get_ioaddr(adapter,
691 recv_crb_registers[port].crb_sts_consumer[ring]);
692
693 sds_ring->crb_intr_mask =
694 netxen_get_ioaddr(adapter,
695 recv_crb_registers[port].sw_int_mask[ring]);
696 }
697 }
698
699
700 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
701 if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state))
702 goto done;
703 err = nx_fw_cmd_create_rx_ctx(adapter);
704 if (err)
705 goto err_out_free;
706 err = nx_fw_cmd_create_tx_ctx(adapter);
707 if (err)
708 goto err_out_free;
709 } else {
710 err = netxen_init_old_ctx(adapter);
711 if (err)
712 goto err_out_free;
713 }
714
715done:
716 return 0;
717
718err_out_free:
719 netxen_free_hw_resources(adapter);
720 return err;
721}
722
723void netxen_free_hw_resources(struct netxen_adapter *adapter)
724{
725 struct netxen_recv_context *recv_ctx;
726 struct nx_host_rds_ring *rds_ring;
727 struct nx_host_sds_ring *sds_ring;
728 struct nx_host_tx_ring *tx_ring;
729 int ring;
730
731 int port = adapter->portnum;
732
733 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
734 if (!test_and_clear_bit(__NX_FW_ATTACHED, &adapter->state))
735 goto done;
736
737 nx_fw_cmd_destroy_rx_ctx(adapter);
738 nx_fw_cmd_destroy_tx_ctx(adapter);
739 } else {
740 netxen_api_lock(adapter);
741 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
742 NETXEN_CTX_D3_RESET | port);
743 netxen_api_unlock(adapter);
744 }
745
746 /* Allow dma queues to drain after context reset */
747 msleep(20);
748
749done:
750 recv_ctx = &adapter->recv_ctx;
751
752 if (recv_ctx->hwctx != NULL) {
753 pci_free_consistent(adapter->pdev,
754 sizeof(struct netxen_ring_ctx) +
755 sizeof(uint32_t),
756 recv_ctx->hwctx,
757 recv_ctx->phys_addr);
758 recv_ctx->hwctx = NULL;
759 }
760
761 tx_ring = adapter->tx_ring;
762 if (tx_ring->desc_head != NULL) {
763 pci_free_consistent(adapter->pdev,
764 TX_DESC_RINGSIZE(tx_ring),
765 tx_ring->desc_head, tx_ring->phys_addr);
766 tx_ring->desc_head = NULL;
767 }
768
769 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
770 rds_ring = &recv_ctx->rds_rings[ring];
771
772 if (rds_ring->desc_head != NULL) {
773 pci_free_consistent(adapter->pdev,
774 RCV_DESC_RINGSIZE(rds_ring),
775 rds_ring->desc_head,
776 rds_ring->phys_addr);
777 rds_ring->desc_head = NULL;
778 }
779 }
780
781 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
782 sds_ring = &recv_ctx->sds_rings[ring];
783
784 if (sds_ring->desc_head != NULL) {
785 pci_free_consistent(adapter->pdev,
786 STATUS_DESC_RINGSIZE(sds_ring),
787 sds_ring->desc_head,
788 sds_ring->phys_addr);
789 sds_ring->desc_head = NULL;
790 }
791 }
792}
793
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
new file mode 100644
index 00000000000..b34fb74d07e
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -0,0 +1,835 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#include <linux/types.h>
27#include <linux/delay.h>
28#include <linux/pci.h>
29#include <asm/io.h>
30#include <linux/netdevice.h>
31#include <linux/ethtool.h>
32
33#include "netxen_nic.h"
34#include "netxen_nic_hw.h"
35
36struct netxen_nic_stats {
37 char stat_string[ETH_GSTRING_LEN];
38 int sizeof_stat;
39 int stat_offset;
40};
41
42#define NETXEN_NIC_STAT(m) sizeof(((struct netxen_adapter *)0)->m), \
43 offsetof(struct netxen_adapter, m)
44
45#define NETXEN_NIC_PORT_WINDOW 0x10000
46#define NETXEN_NIC_INVALID_DATA 0xDEADBEEF
47
48static const struct netxen_nic_stats netxen_nic_gstrings_stats[] = {
49 {"xmit_called", NETXEN_NIC_STAT(stats.xmitcalled)},
50 {"xmit_finished", NETXEN_NIC_STAT(stats.xmitfinished)},
51 {"rx_dropped", NETXEN_NIC_STAT(stats.rxdropped)},
52 {"tx_dropped", NETXEN_NIC_STAT(stats.txdropped)},
53 {"csummed", NETXEN_NIC_STAT(stats.csummed)},
54 {"rx_pkts", NETXEN_NIC_STAT(stats.rx_pkts)},
55 {"lro_pkts", NETXEN_NIC_STAT(stats.lro_pkts)},
56 {"rx_bytes", NETXEN_NIC_STAT(stats.rxbytes)},
57 {"tx_bytes", NETXEN_NIC_STAT(stats.txbytes)},
58};
59
60#define NETXEN_NIC_STATS_LEN ARRAY_SIZE(netxen_nic_gstrings_stats)
61
62static const char netxen_nic_gstrings_test[][ETH_GSTRING_LEN] = {
63 "Register_Test_on_offline",
64 "Link_Test_on_offline"
65};
66
67#define NETXEN_NIC_TEST_LEN ARRAY_SIZE(netxen_nic_gstrings_test)
68
69#define NETXEN_NIC_REGS_COUNT 30
70#define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32))
71#define NETXEN_MAX_EEPROM_LEN 1024
72
73static int netxen_nic_get_eeprom_len(struct net_device *dev)
74{
75 return NETXEN_FLASH_TOTAL_SIZE;
76}
77
78static void
79netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
80{
81 struct netxen_adapter *adapter = netdev_priv(dev);
82 u32 fw_major = 0;
83 u32 fw_minor = 0;
84 u32 fw_build = 0;
85
86 strncpy(drvinfo->driver, netxen_nic_driver_name, 32);
87 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
88 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
89 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
90 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
91 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
92
93 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
94 drvinfo->regdump_len = NETXEN_NIC_REGS_LEN;
95 drvinfo->eedump_len = netxen_nic_get_eeprom_len(dev);
96}
97
98static int
99netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
100{
101 struct netxen_adapter *adapter = netdev_priv(dev);
102 int check_sfp_module = 0;
103
104 /* read which mode */
105 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
106 ecmd->supported = (SUPPORTED_10baseT_Half |
107 SUPPORTED_10baseT_Full |
108 SUPPORTED_100baseT_Half |
109 SUPPORTED_100baseT_Full |
110 SUPPORTED_1000baseT_Half |
111 SUPPORTED_1000baseT_Full);
112
113 ecmd->advertising = (ADVERTISED_100baseT_Half |
114 ADVERTISED_100baseT_Full |
115 ADVERTISED_1000baseT_Half |
116 ADVERTISED_1000baseT_Full);
117
118 ecmd->port = PORT_TP;
119
120 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
121 ecmd->duplex = adapter->link_duplex;
122 ecmd->autoneg = adapter->link_autoneg;
123
124 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
125 u32 val;
126
127 val = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
128 if (val == NETXEN_PORT_MODE_802_3_AP) {
129 ecmd->supported = SUPPORTED_1000baseT_Full;
130 ecmd->advertising = ADVERTISED_1000baseT_Full;
131 } else {
132 ecmd->supported = SUPPORTED_10000baseT_Full;
133 ecmd->advertising = ADVERTISED_10000baseT_Full;
134 }
135
136 if (netif_running(dev) && adapter->has_link_events) {
137 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
138 ecmd->autoneg = adapter->link_autoneg;
139 ecmd->duplex = adapter->link_duplex;
140 goto skip;
141 }
142
143 ecmd->port = PORT_TP;
144
145 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
146 u16 pcifn = adapter->ahw.pci_func;
147
148 val = NXRD32(adapter, P3_LINK_SPEED_REG(pcifn));
149 ethtool_cmd_speed_set(ecmd, P3_LINK_SPEED_MHZ *
150 P3_LINK_SPEED_VAL(pcifn, val));
151 } else
152 ethtool_cmd_speed_set(ecmd, SPEED_10000);
153
154 ecmd->duplex = DUPLEX_FULL;
155 ecmd->autoneg = AUTONEG_DISABLE;
156 } else
157 return -EIO;
158
159skip:
160 ecmd->phy_address = adapter->physical_port;
161 ecmd->transceiver = XCVR_EXTERNAL;
162
163 switch (adapter->ahw.board_type) {
164 case NETXEN_BRDTYPE_P2_SB35_4G:
165 case NETXEN_BRDTYPE_P2_SB31_2G:
166 case NETXEN_BRDTYPE_P3_REF_QG:
167 case NETXEN_BRDTYPE_P3_4_GB:
168 case NETXEN_BRDTYPE_P3_4_GB_MM:
169
170 ecmd->supported |= SUPPORTED_Autoneg;
171 ecmd->advertising |= ADVERTISED_Autoneg;
172 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
173 case NETXEN_BRDTYPE_P3_10G_CX4:
174 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
175 case NETXEN_BRDTYPE_P3_10000_BASE_T:
176 ecmd->supported |= SUPPORTED_TP;
177 ecmd->advertising |= ADVERTISED_TP;
178 ecmd->port = PORT_TP;
179 ecmd->autoneg = (adapter->ahw.board_type ==
180 NETXEN_BRDTYPE_P2_SB31_10G_CX4) ?
181 (AUTONEG_DISABLE) : (adapter->link_autoneg);
182 break;
183 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
184 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
185 case NETXEN_BRDTYPE_P3_IMEZ:
186 case NETXEN_BRDTYPE_P3_XG_LOM:
187 case NETXEN_BRDTYPE_P3_HMEZ:
188 ecmd->supported |= SUPPORTED_MII;
189 ecmd->advertising |= ADVERTISED_MII;
190 ecmd->port = PORT_MII;
191 ecmd->autoneg = AUTONEG_DISABLE;
192 break;
193 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
194 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
195 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
196 ecmd->advertising |= ADVERTISED_TP;
197 ecmd->supported |= SUPPORTED_TP;
198 check_sfp_module = netif_running(dev) &&
199 adapter->has_link_events;
200 case NETXEN_BRDTYPE_P2_SB31_10G:
201 case NETXEN_BRDTYPE_P3_10G_XFP:
202 ecmd->supported |= SUPPORTED_FIBRE;
203 ecmd->advertising |= ADVERTISED_FIBRE;
204 ecmd->port = PORT_FIBRE;
205 ecmd->autoneg = AUTONEG_DISABLE;
206 break;
207 case NETXEN_BRDTYPE_P3_10G_TP:
208 if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
209 ecmd->autoneg = AUTONEG_DISABLE;
210 ecmd->supported |= (SUPPORTED_FIBRE | SUPPORTED_TP);
211 ecmd->advertising |=
212 (ADVERTISED_FIBRE | ADVERTISED_TP);
213 ecmd->port = PORT_FIBRE;
214 check_sfp_module = netif_running(dev) &&
215 adapter->has_link_events;
216 } else {
217 ecmd->supported |= (SUPPORTED_TP |SUPPORTED_Autoneg);
218 ecmd->advertising |=
219 (ADVERTISED_TP | ADVERTISED_Autoneg);
220 ecmd->port = PORT_TP;
221 }
222 break;
223 default:
224 printk(KERN_ERR "netxen-nic: Unsupported board model %d\n",
225 adapter->ahw.board_type);
226 return -EIO;
227 }
228
229 if (check_sfp_module) {
230 switch (adapter->module_type) {
231 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
232 case LINKEVENT_MODULE_OPTICAL_SRLR:
233 case LINKEVENT_MODULE_OPTICAL_LRM:
234 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
235 ecmd->port = PORT_FIBRE;
236 break;
237 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
238 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
239 case LINKEVENT_MODULE_TWINAX:
240 ecmd->port = PORT_TP;
241 break;
242 default:
243 ecmd->port = -1;
244 }
245 }
246
247 return 0;
248}
249
250static int
251netxen_nic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
252{
253 struct netxen_adapter *adapter = netdev_priv(dev);
254 u32 speed = ethtool_cmd_speed(ecmd);
255 int ret;
256
257 if (adapter->ahw.port_type != NETXEN_NIC_GBE)
258 return -EOPNOTSUPP;
259
260 if (!(adapter->capabilities & NX_FW_CAPABILITY_GBE_LINK_CFG))
261 return -EOPNOTSUPP;
262
263 ret = nx_fw_cmd_set_gbe_port(adapter, speed, ecmd->duplex,
264 ecmd->autoneg);
265 if (ret == NX_RCODE_NOT_SUPPORTED)
266 return -EOPNOTSUPP;
267 else if (ret)
268 return -EIO;
269
270 adapter->link_speed = speed;
271 adapter->link_duplex = ecmd->duplex;
272 adapter->link_autoneg = ecmd->autoneg;
273
274 if (!netif_running(dev))
275 return 0;
276
277 dev->netdev_ops->ndo_stop(dev);
278 return dev->netdev_ops->ndo_open(dev);
279}
280
281static int netxen_nic_get_regs_len(struct net_device *dev)
282{
283 return NETXEN_NIC_REGS_LEN;
284}
285
286static void
287netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
288{
289 struct netxen_adapter *adapter = netdev_priv(dev);
290 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
291 struct nx_host_sds_ring *sds_ring;
292 u32 *regs_buff = p;
293 int ring, i = 0;
294 int port = adapter->physical_port;
295
296 memset(p, 0, NETXEN_NIC_REGS_LEN);
297
298 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
299 (adapter->pdev)->device;
300
301 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
302 return;
303
304 regs_buff[i++] = NXRD32(adapter, CRB_CMDPEG_STATE);
305 regs_buff[i++] = NXRD32(adapter, CRB_RCVPEG_STATE);
306 regs_buff[i++] = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
307 regs_buff[i++] = NXRDIO(adapter, adapter->crb_int_state_reg);
308 regs_buff[i++] = NXRD32(adapter, NX_CRB_DEV_REF_COUNT);
309 regs_buff[i++] = NXRD32(adapter, NX_CRB_DEV_STATE);
310 regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
311 regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_HALT_STATUS1);
312 regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_HALT_STATUS2);
313
314 regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_0+0x3c);
315 regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_1+0x3c);
316 regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_2+0x3c);
317 regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_3+0x3c);
318
319 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
320
321 regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_4+0x3c);
322 i += 2;
323
324 regs_buff[i++] = NXRD32(adapter, CRB_XG_STATE_P3);
325 regs_buff[i++] = le32_to_cpu(*(adapter->tx_ring->hw_consumer));
326
327 } else {
328 i++;
329
330 regs_buff[i++] = NXRD32(adapter,
331 NETXEN_NIU_XGE_CONFIG_0+(0x10000*port));
332 regs_buff[i++] = NXRD32(adapter,
333 NETXEN_NIU_XGE_CONFIG_1+(0x10000*port));
334
335 regs_buff[i++] = NXRD32(adapter, CRB_XG_STATE);
336 regs_buff[i++] = NXRDIO(adapter,
337 adapter->tx_ring->crb_cmd_consumer);
338 }
339
340 regs_buff[i++] = NXRDIO(adapter, adapter->tx_ring->crb_cmd_producer);
341
342 regs_buff[i++] = NXRDIO(adapter,
343 recv_ctx->rds_rings[0].crb_rcv_producer);
344 regs_buff[i++] = NXRDIO(adapter,
345 recv_ctx->rds_rings[1].crb_rcv_producer);
346
347 regs_buff[i++] = adapter->max_sds_rings;
348
349 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
350 sds_ring = &(recv_ctx->sds_rings[ring]);
351 regs_buff[i++] = NXRDIO(adapter,
352 sds_ring->crb_sts_consumer);
353 }
354}
355
356static u32 netxen_nic_test_link(struct net_device *dev)
357{
358 struct netxen_adapter *adapter = netdev_priv(dev);
359 u32 val, port;
360
361 port = adapter->physical_port;
362 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
363 val = NXRD32(adapter, CRB_XG_STATE_P3);
364 val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val);
365 return (val == XG_LINK_UP_P3) ? 0 : 1;
366 } else {
367 val = NXRD32(adapter, CRB_XG_STATE);
368 val = (val >> port*8) & 0xff;
369 return (val == XG_LINK_UP) ? 0 : 1;
370 }
371}
372
373static int
374netxen_nic_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
375 u8 * bytes)
376{
377 struct netxen_adapter *adapter = netdev_priv(dev);
378 int offset;
379 int ret;
380
381 if (eeprom->len == 0)
382 return -EINVAL;
383
384 eeprom->magic = (adapter->pdev)->vendor |
385 ((adapter->pdev)->device << 16);
386 offset = eeprom->offset;
387
388 ret = netxen_rom_fast_read_words(adapter, offset, bytes,
389 eeprom->len);
390 if (ret < 0)
391 return ret;
392
393 return 0;
394}
395
396static void
397netxen_nic_get_ringparam(struct net_device *dev,
398 struct ethtool_ringparam *ring)
399{
400 struct netxen_adapter *adapter = netdev_priv(dev);
401
402 ring->rx_pending = adapter->num_rxd;
403 ring->rx_jumbo_pending = adapter->num_jumbo_rxd;
404 ring->rx_jumbo_pending += adapter->num_lro_rxd;
405 ring->tx_pending = adapter->num_txd;
406
407 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
408 ring->rx_max_pending = MAX_RCV_DESCRIPTORS_1G;
409 ring->rx_jumbo_max_pending = MAX_JUMBO_RCV_DESCRIPTORS_1G;
410 } else {
411 ring->rx_max_pending = MAX_RCV_DESCRIPTORS_10G;
412 ring->rx_jumbo_max_pending = MAX_JUMBO_RCV_DESCRIPTORS_10G;
413 }
414
415 ring->tx_max_pending = MAX_CMD_DESCRIPTORS;
416
417 ring->rx_mini_max_pending = 0;
418 ring->rx_mini_pending = 0;
419}
420
421static u32
422netxen_validate_ringparam(u32 val, u32 min, u32 max, char *r_name)
423{
424 u32 num_desc;
425 num_desc = max(val, min);
426 num_desc = min(num_desc, max);
427 num_desc = roundup_pow_of_two(num_desc);
428
429 if (val != num_desc) {
430 printk(KERN_INFO "%s: setting %s ring size %d instead of %d\n",
431 netxen_nic_driver_name, r_name, num_desc, val);
432 }
433
434 return num_desc;
435}
436
437static int
438netxen_nic_set_ringparam(struct net_device *dev,
439 struct ethtool_ringparam *ring)
440{
441 struct netxen_adapter *adapter = netdev_priv(dev);
442 u16 max_rcv_desc = MAX_RCV_DESCRIPTORS_10G;
443 u16 max_jumbo_desc = MAX_JUMBO_RCV_DESCRIPTORS_10G;
444 u16 num_rxd, num_jumbo_rxd, num_txd;
445
446 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
447 return -EOPNOTSUPP;
448
449 if (ring->rx_mini_pending)
450 return -EOPNOTSUPP;
451
452 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
453 max_rcv_desc = MAX_RCV_DESCRIPTORS_1G;
454 max_jumbo_desc = MAX_JUMBO_RCV_DESCRIPTORS_10G;
455 }
456
457 num_rxd = netxen_validate_ringparam(ring->rx_pending,
458 MIN_RCV_DESCRIPTORS, max_rcv_desc, "rx");
459
460 num_jumbo_rxd = netxen_validate_ringparam(ring->rx_jumbo_pending,
461 MIN_JUMBO_DESCRIPTORS, max_jumbo_desc, "rx jumbo");
462
463 num_txd = netxen_validate_ringparam(ring->tx_pending,
464 MIN_CMD_DESCRIPTORS, MAX_CMD_DESCRIPTORS, "tx");
465
466 if (num_rxd == adapter->num_rxd && num_txd == adapter->num_txd &&
467 num_jumbo_rxd == adapter->num_jumbo_rxd)
468 return 0;
469
470 adapter->num_rxd = num_rxd;
471 adapter->num_jumbo_rxd = num_jumbo_rxd;
472 adapter->num_txd = num_txd;
473
474 return netxen_nic_reset_context(adapter);
475}
476
477static void
478netxen_nic_get_pauseparam(struct net_device *dev,
479 struct ethtool_pauseparam *pause)
480{
481 struct netxen_adapter *adapter = netdev_priv(dev);
482 __u32 val;
483 int port = adapter->physical_port;
484
485 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
486 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
487 return;
488 /* get flow control settings */
489 val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
490 pause->rx_pause = netxen_gb_get_rx_flowctl(val);
491 val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
492 switch (port) {
493 case 0:
494 pause->tx_pause = !(netxen_gb_get_gb0_mask(val));
495 break;
496 case 1:
497 pause->tx_pause = !(netxen_gb_get_gb1_mask(val));
498 break;
499 case 2:
500 pause->tx_pause = !(netxen_gb_get_gb2_mask(val));
501 break;
502 case 3:
503 default:
504 pause->tx_pause = !(netxen_gb_get_gb3_mask(val));
505 break;
506 }
507 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
508 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
509 return;
510 pause->rx_pause = 1;
511 val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
512 if (port == 0)
513 pause->tx_pause = !(netxen_xg_get_xg0_mask(val));
514 else
515 pause->tx_pause = !(netxen_xg_get_xg1_mask(val));
516 } else {
517 printk(KERN_ERR"%s: Unknown board type: %x\n",
518 netxen_nic_driver_name, adapter->ahw.port_type);
519 }
520}
521
522static int
523netxen_nic_set_pauseparam(struct net_device *dev,
524 struct ethtool_pauseparam *pause)
525{
526 struct netxen_adapter *adapter = netdev_priv(dev);
527 __u32 val;
528 int port = adapter->physical_port;
529 /* read mode */
530 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
531 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
532 return -EIO;
533 /* set flow control */
534 val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
535
536 if (pause->rx_pause)
537 netxen_gb_rx_flowctl(val);
538 else
539 netxen_gb_unset_rx_flowctl(val);
540
541 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
542 val);
543 /* set autoneg */
544 val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
545 switch (port) {
546 case 0:
547 if (pause->tx_pause)
548 netxen_gb_unset_gb0_mask(val);
549 else
550 netxen_gb_set_gb0_mask(val);
551 break;
552 case 1:
553 if (pause->tx_pause)
554 netxen_gb_unset_gb1_mask(val);
555 else
556 netxen_gb_set_gb1_mask(val);
557 break;
558 case 2:
559 if (pause->tx_pause)
560 netxen_gb_unset_gb2_mask(val);
561 else
562 netxen_gb_set_gb2_mask(val);
563 break;
564 case 3:
565 default:
566 if (pause->tx_pause)
567 netxen_gb_unset_gb3_mask(val);
568 else
569 netxen_gb_set_gb3_mask(val);
570 break;
571 }
572 NXWR32(adapter, NETXEN_NIU_GB_PAUSE_CTL, val);
573 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
574 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
575 return -EIO;
576 val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
577 if (port == 0) {
578 if (pause->tx_pause)
579 netxen_xg_unset_xg0_mask(val);
580 else
581 netxen_xg_set_xg0_mask(val);
582 } else {
583 if (pause->tx_pause)
584 netxen_xg_unset_xg1_mask(val);
585 else
586 netxen_xg_set_xg1_mask(val);
587 }
588 NXWR32(adapter, NETXEN_NIU_XG_PAUSE_CTL, val);
589 } else {
590 printk(KERN_ERR "%s: Unknown board type: %x\n",
591 netxen_nic_driver_name,
592 adapter->ahw.port_type);
593 }
594 return 0;
595}
596
597static int netxen_nic_reg_test(struct net_device *dev)
598{
599 struct netxen_adapter *adapter = netdev_priv(dev);
600 u32 data_read, data_written;
601
602 data_read = NXRD32(adapter, NETXEN_PCIX_PH_REG(0));
603 if ((data_read & 0xffff) != adapter->pdev->vendor)
604 return 1;
605
606 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
607 return 0;
608
609 data_written = (u32)0xa5a5a5a5;
610
611 NXWR32(adapter, CRB_SCRATCHPAD_TEST, data_written);
612 data_read = NXRD32(adapter, CRB_SCRATCHPAD_TEST);
613 if (data_written != data_read)
614 return 1;
615
616 return 0;
617}
618
619static int netxen_get_sset_count(struct net_device *dev, int sset)
620{
621 switch (sset) {
622 case ETH_SS_TEST:
623 return NETXEN_NIC_TEST_LEN;
624 case ETH_SS_STATS:
625 return NETXEN_NIC_STATS_LEN;
626 default:
627 return -EOPNOTSUPP;
628 }
629}
630
631static void
632netxen_nic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
633 u64 * data)
634{
635 memset(data, 0, sizeof(uint64_t) * NETXEN_NIC_TEST_LEN);
636 if ((data[0] = netxen_nic_reg_test(dev)))
637 eth_test->flags |= ETH_TEST_FL_FAILED;
638 /* link test */
639 if ((data[1] = (u64) netxen_nic_test_link(dev)))
640 eth_test->flags |= ETH_TEST_FL_FAILED;
641}
642
643static void
644netxen_nic_get_strings(struct net_device *dev, u32 stringset, u8 * data)
645{
646 int index;
647
648 switch (stringset) {
649 case ETH_SS_TEST:
650 memcpy(data, *netxen_nic_gstrings_test,
651 NETXEN_NIC_TEST_LEN * ETH_GSTRING_LEN);
652 break;
653 case ETH_SS_STATS:
654 for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
655 memcpy(data + index * ETH_GSTRING_LEN,
656 netxen_nic_gstrings_stats[index].stat_string,
657 ETH_GSTRING_LEN);
658 }
659 break;
660 }
661}
662
663static void
664netxen_nic_get_ethtool_stats(struct net_device *dev,
665 struct ethtool_stats *stats, u64 * data)
666{
667 struct netxen_adapter *adapter = netdev_priv(dev);
668 int index;
669
670 for (index = 0; index < NETXEN_NIC_STATS_LEN; index++) {
671 char *p =
672 (char *)adapter +
673 netxen_nic_gstrings_stats[index].stat_offset;
674 data[index] =
675 (netxen_nic_gstrings_stats[index].sizeof_stat ==
676 sizeof(u64)) ? *(u64 *) p : *(u32 *) p;
677 }
678}
679
680static void
681netxen_nic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
682{
683 struct netxen_adapter *adapter = netdev_priv(dev);
684 u32 wol_cfg = 0;
685
686 wol->supported = 0;
687 wol->wolopts = 0;
688
689 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
690 return;
691
692 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
693 if (wol_cfg & (1UL << adapter->portnum))
694 wol->supported |= WAKE_MAGIC;
695
696 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
697 if (wol_cfg & (1UL << adapter->portnum))
698 wol->wolopts |= WAKE_MAGIC;
699}
700
701static int
702netxen_nic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
703{
704 struct netxen_adapter *adapter = netdev_priv(dev);
705 u32 wol_cfg = 0;
706
707 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
708 return -EOPNOTSUPP;
709
710 if (wol->wolopts & ~WAKE_MAGIC)
711 return -EOPNOTSUPP;
712
713 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
714 if (!(wol_cfg & (1 << adapter->portnum)))
715 return -EOPNOTSUPP;
716
717 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
718 if (wol->wolopts & WAKE_MAGIC)
719 wol_cfg |= 1UL << adapter->portnum;
720 else
721 wol_cfg &= ~(1UL << adapter->portnum);
722 NXWR32(adapter, NETXEN_WOL_CONFIG, wol_cfg);
723
724 return 0;
725}
726
727/*
728 * Set the coalescing parameters. Currently only normal is supported.
729 * If rx_coalesce_usecs == 0 or rx_max_coalesced_frames == 0 then set the
730 * firmware coalescing to default.
731 */
732static int netxen_set_intr_coalesce(struct net_device *netdev,
733 struct ethtool_coalesce *ethcoal)
734{
735 struct netxen_adapter *adapter = netdev_priv(netdev);
736
737 if (!NX_IS_REVISION_P3(adapter->ahw.revision_id))
738 return -EINVAL;
739
740 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
741 return -EINVAL;
742
743 /*
744 * Return Error if unsupported values or
745 * unsupported parameters are set.
746 */
747 if (ethcoal->rx_coalesce_usecs > 0xffff ||
748 ethcoal->rx_max_coalesced_frames > 0xffff ||
749 ethcoal->tx_coalesce_usecs > 0xffff ||
750 ethcoal->tx_max_coalesced_frames > 0xffff ||
751 ethcoal->rx_coalesce_usecs_irq ||
752 ethcoal->rx_max_coalesced_frames_irq ||
753 ethcoal->tx_coalesce_usecs_irq ||
754 ethcoal->tx_max_coalesced_frames_irq ||
755 ethcoal->stats_block_coalesce_usecs ||
756 ethcoal->use_adaptive_rx_coalesce ||
757 ethcoal->use_adaptive_tx_coalesce ||
758 ethcoal->pkt_rate_low ||
759 ethcoal->rx_coalesce_usecs_low ||
760 ethcoal->rx_max_coalesced_frames_low ||
761 ethcoal->tx_coalesce_usecs_low ||
762 ethcoal->tx_max_coalesced_frames_low ||
763 ethcoal->pkt_rate_high ||
764 ethcoal->rx_coalesce_usecs_high ||
765 ethcoal->rx_max_coalesced_frames_high ||
766 ethcoal->tx_coalesce_usecs_high ||
767 ethcoal->tx_max_coalesced_frames_high)
768 return -EINVAL;
769
770 if (!ethcoal->rx_coalesce_usecs ||
771 !ethcoal->rx_max_coalesced_frames) {
772 adapter->coal.flags = NETXEN_NIC_INTR_DEFAULT;
773 adapter->coal.normal.data.rx_time_us =
774 NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US;
775 adapter->coal.normal.data.rx_packets =
776 NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS;
777 } else {
778 adapter->coal.flags = 0;
779 adapter->coal.normal.data.rx_time_us =
780 ethcoal->rx_coalesce_usecs;
781 adapter->coal.normal.data.rx_packets =
782 ethcoal->rx_max_coalesced_frames;
783 }
784 adapter->coal.normal.data.tx_time_us = ethcoal->tx_coalesce_usecs;
785 adapter->coal.normal.data.tx_packets =
786 ethcoal->tx_max_coalesced_frames;
787
788 netxen_config_intr_coalesce(adapter);
789
790 return 0;
791}
792
793static int netxen_get_intr_coalesce(struct net_device *netdev,
794 struct ethtool_coalesce *ethcoal)
795{
796 struct netxen_adapter *adapter = netdev_priv(netdev);
797
798 if (!NX_IS_REVISION_P3(adapter->ahw.revision_id))
799 return -EINVAL;
800
801 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
802 return -EINVAL;
803
804 ethcoal->rx_coalesce_usecs = adapter->coal.normal.data.rx_time_us;
805 ethcoal->tx_coalesce_usecs = adapter->coal.normal.data.tx_time_us;
806 ethcoal->rx_max_coalesced_frames =
807 adapter->coal.normal.data.rx_packets;
808 ethcoal->tx_max_coalesced_frames =
809 adapter->coal.normal.data.tx_packets;
810
811 return 0;
812}
813
814const struct ethtool_ops netxen_nic_ethtool_ops = {
815 .get_settings = netxen_nic_get_settings,
816 .set_settings = netxen_nic_set_settings,
817 .get_drvinfo = netxen_nic_get_drvinfo,
818 .get_regs_len = netxen_nic_get_regs_len,
819 .get_regs = netxen_nic_get_regs,
820 .get_link = ethtool_op_get_link,
821 .get_eeprom_len = netxen_nic_get_eeprom_len,
822 .get_eeprom = netxen_nic_get_eeprom,
823 .get_ringparam = netxen_nic_get_ringparam,
824 .set_ringparam = netxen_nic_set_ringparam,
825 .get_pauseparam = netxen_nic_get_pauseparam,
826 .set_pauseparam = netxen_nic_set_pauseparam,
827 .get_wol = netxen_nic_get_wol,
828 .set_wol = netxen_nic_set_wol,
829 .self_test = netxen_nic_diag_test,
830 .get_strings = netxen_nic_get_strings,
831 .get_ethtool_stats = netxen_nic_get_ethtool_stats,
832 .get_sset_count = netxen_get_sset_count,
833 .get_coalesce = netxen_get_intr_coalesce,
834 .set_coalesce = netxen_set_intr_coalesce,
835};
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h
new file mode 100644
index 00000000000..dc1967c1f31
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_hdr.h
@@ -0,0 +1,1050 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#ifndef __NETXEN_NIC_HDR_H_
27#define __NETXEN_NIC_HDR_H_
28
29#include <linux/kernel.h>
30#include <linux/types.h>
31
32/*
33 * The basic unit of access when reading/writing control registers.
34 */
35
36typedef __le32 netxen_crbword_t; /* single word in CRB space */
37
38enum {
39 NETXEN_HW_H0_CH_HUB_ADR = 0x05,
40 NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
41 NETXEN_HW_H2_CH_HUB_ADR = 0x03,
42 NETXEN_HW_H3_CH_HUB_ADR = 0x01,
43 NETXEN_HW_H4_CH_HUB_ADR = 0x06,
44 NETXEN_HW_H5_CH_HUB_ADR = 0x07,
45 NETXEN_HW_H6_CH_HUB_ADR = 0x08
46};
47
48/* Hub 0 */
49enum {
50 NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
51 NETXEN_HW_MS_CRB_AGT_ADR = 0x25
52};
53
54/* Hub 1 */
55enum {
56 NETXEN_HW_PS_CRB_AGT_ADR = 0x73,
57 NETXEN_HW_SS_CRB_AGT_ADR = 0x20,
58 NETXEN_HW_RPMX3_CRB_AGT_ADR = 0x0b,
59 NETXEN_HW_QMS_CRB_AGT_ADR = 0x00,
60 NETXEN_HW_SQGS0_CRB_AGT_ADR = 0x01,
61 NETXEN_HW_SQGS1_CRB_AGT_ADR = 0x02,
62 NETXEN_HW_SQGS2_CRB_AGT_ADR = 0x03,
63 NETXEN_HW_SQGS3_CRB_AGT_ADR = 0x04,
64 NETXEN_HW_C2C0_CRB_AGT_ADR = 0x58,
65 NETXEN_HW_C2C1_CRB_AGT_ADR = 0x59,
66 NETXEN_HW_C2C2_CRB_AGT_ADR = 0x5a,
67 NETXEN_HW_RPMX2_CRB_AGT_ADR = 0x0a,
68 NETXEN_HW_RPMX4_CRB_AGT_ADR = 0x0c,
69 NETXEN_HW_RPMX7_CRB_AGT_ADR = 0x0f,
70 NETXEN_HW_RPMX9_CRB_AGT_ADR = 0x12,
71 NETXEN_HW_SMB_CRB_AGT_ADR = 0x18
72};
73
74/* Hub 2 */
75enum {
76 NETXEN_HW_NIU_CRB_AGT_ADR = 0x31,
77 NETXEN_HW_I2C0_CRB_AGT_ADR = 0x19,
78 NETXEN_HW_I2C1_CRB_AGT_ADR = 0x29,
79
80 NETXEN_HW_SN_CRB_AGT_ADR = 0x10,
81 NETXEN_HW_I2Q_CRB_AGT_ADR = 0x20,
82 NETXEN_HW_LPC_CRB_AGT_ADR = 0x22,
83 NETXEN_HW_ROMUSB_CRB_AGT_ADR = 0x21,
84 NETXEN_HW_QM_CRB_AGT_ADR = 0x66,
85 NETXEN_HW_SQG0_CRB_AGT_ADR = 0x60,
86 NETXEN_HW_SQG1_CRB_AGT_ADR = 0x61,
87 NETXEN_HW_SQG2_CRB_AGT_ADR = 0x62,
88 NETXEN_HW_SQG3_CRB_AGT_ADR = 0x63,
89 NETXEN_HW_RPMX1_CRB_AGT_ADR = 0x09,
90 NETXEN_HW_RPMX5_CRB_AGT_ADR = 0x0d,
91 NETXEN_HW_RPMX6_CRB_AGT_ADR = 0x0e,
92 NETXEN_HW_RPMX8_CRB_AGT_ADR = 0x11
93};
94
95/* Hub 3 */
96enum {
97 NETXEN_HW_PH_CRB_AGT_ADR = 0x1A,
98 NETXEN_HW_SRE_CRB_AGT_ADR = 0x50,
99 NETXEN_HW_EG_CRB_AGT_ADR = 0x51,
100 NETXEN_HW_RPMX0_CRB_AGT_ADR = 0x08
101};
102
103/* Hub 4 */
104enum {
105 NETXEN_HW_PEGN0_CRB_AGT_ADR = 0x40,
106 NETXEN_HW_PEGN1_CRB_AGT_ADR,
107 NETXEN_HW_PEGN2_CRB_AGT_ADR,
108 NETXEN_HW_PEGN3_CRB_AGT_ADR,
109 NETXEN_HW_PEGNI_CRB_AGT_ADR,
110 NETXEN_HW_PEGND_CRB_AGT_ADR,
111 NETXEN_HW_PEGNC_CRB_AGT_ADR,
112 NETXEN_HW_PEGR0_CRB_AGT_ADR,
113 NETXEN_HW_PEGR1_CRB_AGT_ADR,
114 NETXEN_HW_PEGR2_CRB_AGT_ADR,
115 NETXEN_HW_PEGR3_CRB_AGT_ADR,
116 NETXEN_HW_PEGN4_CRB_AGT_ADR
117};
118
119/* Hub 5 */
120enum {
121 NETXEN_HW_PEGS0_CRB_AGT_ADR = 0x40,
122 NETXEN_HW_PEGS1_CRB_AGT_ADR,
123 NETXEN_HW_PEGS2_CRB_AGT_ADR,
124 NETXEN_HW_PEGS3_CRB_AGT_ADR,
125 NETXEN_HW_PEGSI_CRB_AGT_ADR,
126 NETXEN_HW_PEGSD_CRB_AGT_ADR,
127 NETXEN_HW_PEGSC_CRB_AGT_ADR
128};
129
130/* Hub 6 */
131enum {
132 NETXEN_HW_CAS0_CRB_AGT_ADR = 0x46,
133 NETXEN_HW_CAS1_CRB_AGT_ADR = 0x47,
134 NETXEN_HW_CAS2_CRB_AGT_ADR = 0x48,
135 NETXEN_HW_CAS3_CRB_AGT_ADR = 0x49,
136 NETXEN_HW_NCM_CRB_AGT_ADR = 0x16,
137 NETXEN_HW_TMR_CRB_AGT_ADR = 0x17,
138 NETXEN_HW_XDMA_CRB_AGT_ADR = 0x05,
139 NETXEN_HW_OCM0_CRB_AGT_ADR = 0x06,
140 NETXEN_HW_OCM1_CRB_AGT_ADR = 0x07
141};
142
143/* Floaters - non existent modules */
144#define NETXEN_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
145
146/* This field defines PCI/X adr [25:20] of agents on the CRB */
147enum {
148 NETXEN_HW_PX_MAP_CRB_PH = 0,
149 NETXEN_HW_PX_MAP_CRB_PS,
150 NETXEN_HW_PX_MAP_CRB_MN,
151 NETXEN_HW_PX_MAP_CRB_MS,
152 NETXEN_HW_PX_MAP_CRB_PGR1,
153 NETXEN_HW_PX_MAP_CRB_SRE,
154 NETXEN_HW_PX_MAP_CRB_NIU,
155 NETXEN_HW_PX_MAP_CRB_QMN,
156 NETXEN_HW_PX_MAP_CRB_SQN0,
157 NETXEN_HW_PX_MAP_CRB_SQN1,
158 NETXEN_HW_PX_MAP_CRB_SQN2,
159 NETXEN_HW_PX_MAP_CRB_SQN3,
160 NETXEN_HW_PX_MAP_CRB_QMS,
161 NETXEN_HW_PX_MAP_CRB_SQS0,
162 NETXEN_HW_PX_MAP_CRB_SQS1,
163 NETXEN_HW_PX_MAP_CRB_SQS2,
164 NETXEN_HW_PX_MAP_CRB_SQS3,
165 NETXEN_HW_PX_MAP_CRB_PGN0,
166 NETXEN_HW_PX_MAP_CRB_PGN1,
167 NETXEN_HW_PX_MAP_CRB_PGN2,
168 NETXEN_HW_PX_MAP_CRB_PGN3,
169 NETXEN_HW_PX_MAP_CRB_PGND,
170 NETXEN_HW_PX_MAP_CRB_PGNI,
171 NETXEN_HW_PX_MAP_CRB_PGS0,
172 NETXEN_HW_PX_MAP_CRB_PGS1,
173 NETXEN_HW_PX_MAP_CRB_PGS2,
174 NETXEN_HW_PX_MAP_CRB_PGS3,
175 NETXEN_HW_PX_MAP_CRB_PGSD,
176 NETXEN_HW_PX_MAP_CRB_PGSI,
177 NETXEN_HW_PX_MAP_CRB_SN,
178 NETXEN_HW_PX_MAP_CRB_PGR2,
179 NETXEN_HW_PX_MAP_CRB_EG,
180 NETXEN_HW_PX_MAP_CRB_PH2,
181 NETXEN_HW_PX_MAP_CRB_PS2,
182 NETXEN_HW_PX_MAP_CRB_CAM,
183 NETXEN_HW_PX_MAP_CRB_CAS0,
184 NETXEN_HW_PX_MAP_CRB_CAS1,
185 NETXEN_HW_PX_MAP_CRB_CAS2,
186 NETXEN_HW_PX_MAP_CRB_C2C0,
187 NETXEN_HW_PX_MAP_CRB_C2C1,
188 NETXEN_HW_PX_MAP_CRB_TIMR,
189 NETXEN_HW_PX_MAP_CRB_PGR3,
190 NETXEN_HW_PX_MAP_CRB_RPMX1,
191 NETXEN_HW_PX_MAP_CRB_RPMX2,
192 NETXEN_HW_PX_MAP_CRB_RPMX3,
193 NETXEN_HW_PX_MAP_CRB_RPMX4,
194 NETXEN_HW_PX_MAP_CRB_RPMX5,
195 NETXEN_HW_PX_MAP_CRB_RPMX6,
196 NETXEN_HW_PX_MAP_CRB_RPMX7,
197 NETXEN_HW_PX_MAP_CRB_XDMA,
198 NETXEN_HW_PX_MAP_CRB_I2Q,
199 NETXEN_HW_PX_MAP_CRB_ROMUSB,
200 NETXEN_HW_PX_MAP_CRB_CAS3,
201 NETXEN_HW_PX_MAP_CRB_RPMX0,
202 NETXEN_HW_PX_MAP_CRB_RPMX8,
203 NETXEN_HW_PX_MAP_CRB_RPMX9,
204 NETXEN_HW_PX_MAP_CRB_OCM0,
205 NETXEN_HW_PX_MAP_CRB_OCM1,
206 NETXEN_HW_PX_MAP_CRB_SMB,
207 NETXEN_HW_PX_MAP_CRB_I2C0,
208 NETXEN_HW_PX_MAP_CRB_I2C1,
209 NETXEN_HW_PX_MAP_CRB_LPC,
210 NETXEN_HW_PX_MAP_CRB_PGNC,
211 NETXEN_HW_PX_MAP_CRB_PGR0
212};
213
214/* This field defines CRB adr [31:20] of the agents */
215
216#define NETXEN_HW_CRB_HUB_AGT_ADR_MN \
217 ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MN_CRB_AGT_ADR)
218#define NETXEN_HW_CRB_HUB_AGT_ADR_PH \
219 ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_PH_CRB_AGT_ADR)
220#define NETXEN_HW_CRB_HUB_AGT_ADR_MS \
221 ((NETXEN_HW_H0_CH_HUB_ADR << 7) | NETXEN_HW_MS_CRB_AGT_ADR)
222
223#define NETXEN_HW_CRB_HUB_AGT_ADR_PS \
224 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_PS_CRB_AGT_ADR)
225#define NETXEN_HW_CRB_HUB_AGT_ADR_SS \
226 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SS_CRB_AGT_ADR)
227#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3 \
228 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX3_CRB_AGT_ADR)
229#define NETXEN_HW_CRB_HUB_AGT_ADR_QMS \
230 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_QMS_CRB_AGT_ADR)
231#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS0 \
232 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS0_CRB_AGT_ADR)
233#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS1 \
234 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS1_CRB_AGT_ADR)
235#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS2 \
236 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS2_CRB_AGT_ADR)
237#define NETXEN_HW_CRB_HUB_AGT_ADR_SQS3 \
238 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SQGS3_CRB_AGT_ADR)
239#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C0 \
240 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C0_CRB_AGT_ADR)
241#define NETXEN_HW_CRB_HUB_AGT_ADR_C2C1 \
242 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_C2C1_CRB_AGT_ADR)
243#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2 \
244 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX2_CRB_AGT_ADR)
245#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4 \
246 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX4_CRB_AGT_ADR)
247#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7 \
248 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX7_CRB_AGT_ADR)
249#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9 \
250 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_RPMX9_CRB_AGT_ADR)
251#define NETXEN_HW_CRB_HUB_AGT_ADR_SMB \
252 ((NETXEN_HW_H1_CH_HUB_ADR << 7) | NETXEN_HW_SMB_CRB_AGT_ADR)
253
254#define NETXEN_HW_CRB_HUB_AGT_ADR_NIU \
255 ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_NIU_CRB_AGT_ADR)
256#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C0 \
257 ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C0_CRB_AGT_ADR)
258#define NETXEN_HW_CRB_HUB_AGT_ADR_I2C1 \
259 ((NETXEN_HW_H2_CH_HUB_ADR << 7) | NETXEN_HW_I2C1_CRB_AGT_ADR)
260
261#define NETXEN_HW_CRB_HUB_AGT_ADR_SRE \
262 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SRE_CRB_AGT_ADR)
263#define NETXEN_HW_CRB_HUB_AGT_ADR_EG \
264 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_EG_CRB_AGT_ADR)
265#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0 \
266 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX0_CRB_AGT_ADR)
267#define NETXEN_HW_CRB_HUB_AGT_ADR_QMN \
268 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_QM_CRB_AGT_ADR)
269#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN0 \
270 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG0_CRB_AGT_ADR)
271#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN1 \
272 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG1_CRB_AGT_ADR)
273#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN2 \
274 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG2_CRB_AGT_ADR)
275#define NETXEN_HW_CRB_HUB_AGT_ADR_SQN3 \
276 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_SQG3_CRB_AGT_ADR)
277#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1 \
278 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX1_CRB_AGT_ADR)
279#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5 \
280 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX5_CRB_AGT_ADR)
281#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6 \
282 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX6_CRB_AGT_ADR)
283#define NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8 \
284 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_RPMX8_CRB_AGT_ADR)
285#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS0 \
286 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS0_CRB_AGT_ADR)
287#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS1 \
288 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS1_CRB_AGT_ADR)
289#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS2 \
290 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS2_CRB_AGT_ADR)
291#define NETXEN_HW_CRB_HUB_AGT_ADR_CAS3 \
292 ((NETXEN_HW_H3_CH_HUB_ADR << 7) | NETXEN_HW_CAS3_CRB_AGT_ADR)
293
294#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNI \
295 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNI_CRB_AGT_ADR)
296#define NETXEN_HW_CRB_HUB_AGT_ADR_PGND \
297 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGND_CRB_AGT_ADR)
298#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN0 \
299 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN0_CRB_AGT_ADR)
300#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN1 \
301 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN1_CRB_AGT_ADR)
302#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN2 \
303 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN2_CRB_AGT_ADR)
304#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN3 \
305 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN3_CRB_AGT_ADR)
306#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN4 \
307 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN4_CRB_AGT_ADR)
308#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNC \
309 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNC_CRB_AGT_ADR)
310#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR0 \
311 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR0_CRB_AGT_ADR)
312#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR1 \
313 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR1_CRB_AGT_ADR)
314#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR2 \
315 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR2_CRB_AGT_ADR)
316#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR3 \
317 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGR3_CRB_AGT_ADR)
318
319#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSI \
320 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSI_CRB_AGT_ADR)
321#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSD \
322 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSD_CRB_AGT_ADR)
323#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS0 \
324 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS0_CRB_AGT_ADR)
325#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS1 \
326 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS1_CRB_AGT_ADR)
327#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS2 \
328 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS2_CRB_AGT_ADR)
329#define NETXEN_HW_CRB_HUB_AGT_ADR_PGS3 \
330 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGS3_CRB_AGT_ADR)
331#define NETXEN_HW_CRB_HUB_AGT_ADR_PGSC \
332 ((NETXEN_HW_H5_CH_HUB_ADR << 7) | NETXEN_HW_PEGSC_CRB_AGT_ADR)
333
334#define NETXEN_HW_CRB_HUB_AGT_ADR_CAM \
335 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_NCM_CRB_AGT_ADR)
336#define NETXEN_HW_CRB_HUB_AGT_ADR_TIMR \
337 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_TMR_CRB_AGT_ADR)
338#define NETXEN_HW_CRB_HUB_AGT_ADR_XDMA \
339 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_XDMA_CRB_AGT_ADR)
340#define NETXEN_HW_CRB_HUB_AGT_ADR_SN \
341 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_SN_CRB_AGT_ADR)
342#define NETXEN_HW_CRB_HUB_AGT_ADR_I2Q \
343 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_I2Q_CRB_AGT_ADR)
344#define NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB \
345 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_ROMUSB_CRB_AGT_ADR)
346#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM0 \
347 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM0_CRB_AGT_ADR)
348#define NETXEN_HW_CRB_HUB_AGT_ADR_OCM1 \
349 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_OCM1_CRB_AGT_ADR)
350#define NETXEN_HW_CRB_HUB_AGT_ADR_LPC \
351 ((NETXEN_HW_H6_CH_HUB_ADR << 7) | NETXEN_HW_LPC_CRB_AGT_ADR)
352
353#define NETXEN_SRE_MISC (NETXEN_CRB_SRE + 0x0002c)
354#define NETXEN_SRE_INT_STATUS (NETXEN_CRB_SRE + 0x00034)
355#define NETXEN_SRE_PBI_ACTIVE_STATUS (NETXEN_CRB_SRE + 0x01014)
356#define NETXEN_SRE_L1RE_CTL (NETXEN_CRB_SRE + 0x03000)
357#define NETXEN_SRE_L2RE_CTL (NETXEN_CRB_SRE + 0x05000)
358#define NETXEN_SRE_BUF_CTL (NETXEN_CRB_SRE + 0x01000)
359
360#define NETXEN_DMA_BASE(U) (NETXEN_CRB_PCIX_MD + 0x20000 + ((U)<<16))
361#define NETXEN_DMA_COMMAND(U) (NETXEN_DMA_BASE(U) + 0x00008)
362
363#define NETXEN_I2Q_CLR_PCI_HI (NETXEN_CRB_I2Q + 0x00034)
364
365#define PEG_NETWORK_BASE(N) (NETXEN_CRB_PEG_NET_0 + (((N)&3) << 20))
366#define CRB_REG_EX_PC 0x3c
367
368#define ROMUSB_GLB (NETXEN_CRB_ROMUSB + 0x00000)
369#define ROMUSB_ROM (NETXEN_CRB_ROMUSB + 0x10000)
370
371#define NETXEN_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
372#define NETXEN_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
373#define NETXEN_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
374#define NETXEN_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
375#define NETXEN_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
376#define NETXEN_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
377#define NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
378
379#define NETXEN_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
380
381#define NETXEN_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
382#define NETXEN_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
383#define NETXEN_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
384#define NETXEN_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
385#define NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
386#define NETXEN_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
387
388/* Lock IDs for ROM lock */
389#define ROM_LOCK_DRIVER 0x0d417340
390
391/******************************************************************************
392*
393* Definitions specific to M25P flash
394*
395*******************************************************************************
396* Instructions
397*/
398#define M25P_INSTR_WREN 0x06
399#define M25P_INSTR_WRDI 0x04
400#define M25P_INSTR_RDID 0x9f
401#define M25P_INSTR_RDSR 0x05
402#define M25P_INSTR_WRSR 0x01
403#define M25P_INSTR_READ 0x03
404#define M25P_INSTR_FAST_READ 0x0b
405#define M25P_INSTR_PP 0x02
406#define M25P_INSTR_SE 0xd8
407#define M25P_INSTR_BE 0xc7
408#define M25P_INSTR_DP 0xb9
409#define M25P_INSTR_RES 0xab
410
411/* all are 1MB windows */
412
413#define NETXEN_PCI_CRB_WINDOWSIZE 0x00100000
414#define NETXEN_PCI_CRB_WINDOW(A) \
415 (NETXEN_PCI_CRBSPACE + (A)*NETXEN_PCI_CRB_WINDOWSIZE)
416
417#define NETXEN_CRB_NIU NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_NIU)
418#define NETXEN_CRB_SRE NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SRE)
419#define NETXEN_CRB_ROMUSB \
420 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_ROMUSB)
421#define NETXEN_CRB_I2Q NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2Q)
422#define NETXEN_CRB_I2C0 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2C0)
423#define NETXEN_CRB_SMB NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SMB)
424#define NETXEN_CRB_MAX NETXEN_PCI_CRB_WINDOW(64)
425
426#define NETXEN_CRB_PCIX_HOST NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH)
427#define NETXEN_CRB_PCIX_HOST2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH2)
428#define NETXEN_CRB_PEG_NET_0 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN0)
429#define NETXEN_CRB_PEG_NET_1 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN1)
430#define NETXEN_CRB_PEG_NET_2 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN2)
431#define NETXEN_CRB_PEG_NET_3 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGN3)
432#define NETXEN_CRB_PEG_NET_4 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SQS2)
433#define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND)
434#define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI)
435#define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN)
436#define NETXEN_CRB_QDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SN)
437
438#define NETXEN_CRB_PCIX_MD NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PS)
439#define NETXEN_CRB_PCIE NETXEN_CRB_PCIX_MD
440
441#define ISR_INT_VECTOR (NETXEN_PCIX_PS_REG(PCIX_INT_VECTOR))
442#define ISR_INT_MASK (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
443#define ISR_INT_MASK_SLOW (NETXEN_PCIX_PS_REG(PCIX_INT_MASK))
444#define ISR_INT_TARGET_STATUS (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS))
445#define ISR_INT_TARGET_MASK (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK))
446#define ISR_INT_TARGET_STATUS_F1 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
447#define ISR_INT_TARGET_MASK_F1 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
448#define ISR_INT_TARGET_STATUS_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
449#define ISR_INT_TARGET_MASK_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
450#define ISR_INT_TARGET_STATUS_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
451#define ISR_INT_TARGET_MASK_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
452#define ISR_INT_TARGET_STATUS_F4 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
453#define ISR_INT_TARGET_MASK_F4 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
454#define ISR_INT_TARGET_STATUS_F5 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
455#define ISR_INT_TARGET_MASK_F5 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
456#define ISR_INT_TARGET_STATUS_F6 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
457#define ISR_INT_TARGET_MASK_F6 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
458#define ISR_INT_TARGET_STATUS_F7 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
459#define ISR_INT_TARGET_MASK_F7 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
460
461#define NETXEN_PCI_MAPSIZE 128
462#define NETXEN_PCI_DDR_NET (0x00000000UL)
463#define NETXEN_PCI_QDR_NET (0x04000000UL)
464#define NETXEN_PCI_DIRECT_CRB (0x04400000UL)
465#define NETXEN_PCI_CAMQM (0x04800000UL)
466#define NETXEN_PCI_CAMQM_MAX (0x04ffffffUL)
467#define NETXEN_PCI_OCM0 (0x05000000UL)
468#define NETXEN_PCI_OCM0_MAX (0x050fffffUL)
469#define NETXEN_PCI_OCM1 (0x05100000UL)
470#define NETXEN_PCI_OCM1_MAX (0x051fffffUL)
471#define NETXEN_PCI_CRBSPACE (0x06000000UL)
472#define NETXEN_PCI_128MB_SIZE (0x08000000UL)
473#define NETXEN_PCI_32MB_SIZE (0x02000000UL)
474#define NETXEN_PCI_2MB_SIZE (0x00200000UL)
475
476#define NETXEN_PCI_MN_2M (0)
477#define NETXEN_PCI_MS_2M (0x80000)
478#define NETXEN_PCI_OCM0_2M (0x000c0000UL)
479#define NETXEN_PCI_CAMQM_2M_BASE (0x000ff800UL)
480#define NETXEN_PCI_CAMQM_2M_END (0x04800800UL)
481
482#define NETXEN_CRB_CAM NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_CAM)
483
484#define NETXEN_ADDR_DDR_NET (0x0000000000000000ULL)
485#define NETXEN_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
486#define NETXEN_ADDR_OCM0 (0x0000000200000000ULL)
487#define NETXEN_ADDR_OCM0_MAX (0x00000002000fffffULL)
488#define NETXEN_ADDR_OCM1 (0x0000000200400000ULL)
489#define NETXEN_ADDR_OCM1_MAX (0x00000002004fffffULL)
490#define NETXEN_ADDR_QDR_NET (0x0000000300000000ULL)
491#define NETXEN_ADDR_QDR_NET_MAX_P2 (0x00000003003fffffULL)
492#define NETXEN_ADDR_QDR_NET_MAX_P3 (0x0000000303ffffffULL)
493
494/*
495 * Register offsets for MN
496 */
497#define NETXEN_MIU_CONTROL (0x000)
498#define NETXEN_MIU_MN_CONTROL (NETXEN_CRB_DDR_NET+NETXEN_MIU_CONTROL)
499
500 /* 200ms delay in each loop */
501#define NETXEN_NIU_PHY_WAITLEN 200000
502 /* 10 seconds before we give up */
503#define NETXEN_NIU_PHY_WAITMAX 50
504#define NETXEN_NIU_MAX_GBE_PORTS 4
505#define NETXEN_NIU_MAX_XG_PORTS 2
506
507#define NETXEN_NIU_MODE (NETXEN_CRB_NIU + 0x00000)
508
509#define NETXEN_NIU_XG_SINGLE_TERM (NETXEN_CRB_NIU + 0x00004)
510#define NETXEN_NIU_XG_DRIVE_HI (NETXEN_CRB_NIU + 0x00008)
511#define NETXEN_NIU_XG_DRIVE_LO (NETXEN_CRB_NIU + 0x0000c)
512#define NETXEN_NIU_XG_DTX (NETXEN_CRB_NIU + 0x00010)
513#define NETXEN_NIU_XG_DEQ (NETXEN_CRB_NIU + 0x00014)
514#define NETXEN_NIU_XG_WORD_ALIGN (NETXEN_CRB_NIU + 0x00018)
515#define NETXEN_NIU_XG_RESET (NETXEN_CRB_NIU + 0x0001c)
516#define NETXEN_NIU_XG_POWER_DOWN (NETXEN_CRB_NIU + 0x00020)
517#define NETXEN_NIU_XG_RESET_PLL (NETXEN_CRB_NIU + 0x00024)
518#define NETXEN_NIU_XG_SERDES_LOOPBACK (NETXEN_CRB_NIU + 0x00028)
519#define NETXEN_NIU_XG_DO_BYTE_ALIGN (NETXEN_CRB_NIU + 0x0002c)
520#define NETXEN_NIU_XG_TX_ENABLE (NETXEN_CRB_NIU + 0x00030)
521#define NETXEN_NIU_XG_RX_ENABLE (NETXEN_CRB_NIU + 0x00034)
522#define NETXEN_NIU_XG_STATUS (NETXEN_CRB_NIU + 0x00038)
523#define NETXEN_NIU_XG_PAUSE_THRESHOLD (NETXEN_CRB_NIU + 0x0003c)
524#define NETXEN_NIU_INT_MASK (NETXEN_CRB_NIU + 0x00040)
525#define NETXEN_NIU_ACTIVE_INT (NETXEN_CRB_NIU + 0x00044)
526#define NETXEN_NIU_MASKABLE_INT (NETXEN_CRB_NIU + 0x00048)
527
528#define NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER (NETXEN_CRB_NIU + 0x0004c)
529
530#define NETXEN_NIU_GB_SERDES_RESET (NETXEN_CRB_NIU + 0x00050)
531#define NETXEN_NIU_GB0_GMII_MODE (NETXEN_CRB_NIU + 0x00054)
532#define NETXEN_NIU_GB0_MII_MODE (NETXEN_CRB_NIU + 0x00058)
533#define NETXEN_NIU_GB1_GMII_MODE (NETXEN_CRB_NIU + 0x0005c)
534#define NETXEN_NIU_GB1_MII_MODE (NETXEN_CRB_NIU + 0x00060)
535#define NETXEN_NIU_GB2_GMII_MODE (NETXEN_CRB_NIU + 0x00064)
536#define NETXEN_NIU_GB2_MII_MODE (NETXEN_CRB_NIU + 0x00068)
537#define NETXEN_NIU_GB3_GMII_MODE (NETXEN_CRB_NIU + 0x0006c)
538#define NETXEN_NIU_GB3_MII_MODE (NETXEN_CRB_NIU + 0x00070)
539#define NETXEN_NIU_REMOTE_LOOPBACK (NETXEN_CRB_NIU + 0x00074)
540#define NETXEN_NIU_GB0_HALF_DUPLEX (NETXEN_CRB_NIU + 0x00078)
541#define NETXEN_NIU_GB1_HALF_DUPLEX (NETXEN_CRB_NIU + 0x0007c)
542#define NETXEN_NIU_RESET_SYS_FIFOS (NETXEN_CRB_NIU + 0x00088)
543#define NETXEN_NIU_GB_CRC_DROP (NETXEN_CRB_NIU + 0x0008c)
544#define NETXEN_NIU_GB_DROP_WRONGADDR (NETXEN_CRB_NIU + 0x00090)
545#define NETXEN_NIU_TEST_MUX_CTL (NETXEN_CRB_NIU + 0x00094)
546#define NETXEN_NIU_XG_PAUSE_CTL (NETXEN_CRB_NIU + 0x00098)
547#define NETXEN_NIU_XG_PAUSE_LEVEL (NETXEN_CRB_NIU + 0x000dc)
548#define NETXEN_NIU_FRAME_COUNT_SELECT (NETXEN_CRB_NIU + 0x000ac)
549#define NETXEN_NIU_FRAME_COUNT (NETXEN_CRB_NIU + 0x000b0)
550#define NETXEN_NIU_XG_SEL (NETXEN_CRB_NIU + 0x00128)
551#define NETXEN_NIU_GB_PAUSE_CTL (NETXEN_CRB_NIU + 0x0030c)
552
553#define NETXEN_NIU_FULL_LEVEL_XG (NETXEN_CRB_NIU + 0x00450)
554
555#define NETXEN_NIU_XG1_RESET (NETXEN_CRB_NIU + 0x0011c)
556#define NETXEN_NIU_XG1_POWER_DOWN (NETXEN_CRB_NIU + 0x00120)
557#define NETXEN_NIU_XG1_RESET_PLL (NETXEN_CRB_NIU + 0x00124)
558
559#define NETXEN_MAC_ADDR_CNTL_REG (NETXEN_CRB_NIU + 0x1000)
560
561#define NETXEN_MULTICAST_ADDR_HI_0 (NETXEN_CRB_NIU + 0x1010)
562#define NETXEN_MULTICAST_ADDR_HI_1 (NETXEN_CRB_NIU + 0x1014)
563#define NETXEN_MULTICAST_ADDR_HI_2 (NETXEN_CRB_NIU + 0x1018)
564#define NETXEN_MULTICAST_ADDR_HI_3 (NETXEN_CRB_NIU + 0x101c)
565
566#define NETXEN_UNICAST_ADDR_BASE (NETXEN_CRB_NIU + 0x1080)
567#define NETXEN_MULTICAST_ADDR_BASE (NETXEN_CRB_NIU + 0x1100)
568
569#define NETXEN_NIU_GB_MAC_CONFIG_0(I) \
570 (NETXEN_CRB_NIU + 0x30000 + (I)*0x10000)
571#define NETXEN_NIU_GB_MAC_CONFIG_1(I) \
572 (NETXEN_CRB_NIU + 0x30004 + (I)*0x10000)
573#define NETXEN_NIU_GB_MAC_IPG_IFG(I) \
574 (NETXEN_CRB_NIU + 0x30008 + (I)*0x10000)
575#define NETXEN_NIU_GB_HALF_DUPLEX_CTRL(I) \
576 (NETXEN_CRB_NIU + 0x3000c + (I)*0x10000)
577#define NETXEN_NIU_GB_MAX_FRAME_SIZE(I) \
578 (NETXEN_CRB_NIU + 0x30010 + (I)*0x10000)
579#define NETXEN_NIU_GB_TEST_REG(I) \
580 (NETXEN_CRB_NIU + 0x3001c + (I)*0x10000)
581#define NETXEN_NIU_GB_MII_MGMT_CONFIG(I) \
582 (NETXEN_CRB_NIU + 0x30020 + (I)*0x10000)
583#define NETXEN_NIU_GB_MII_MGMT_COMMAND(I) \
584 (NETXEN_CRB_NIU + 0x30024 + (I)*0x10000)
585#define NETXEN_NIU_GB_MII_MGMT_ADDR(I) \
586 (NETXEN_CRB_NIU + 0x30028 + (I)*0x10000)
587#define NETXEN_NIU_GB_MII_MGMT_CTRL(I) \
588 (NETXEN_CRB_NIU + 0x3002c + (I)*0x10000)
589#define NETXEN_NIU_GB_MII_MGMT_STATUS(I) \
590 (NETXEN_CRB_NIU + 0x30030 + (I)*0x10000)
591#define NETXEN_NIU_GB_MII_MGMT_INDICATE(I) \
592 (NETXEN_CRB_NIU + 0x30034 + (I)*0x10000)
593#define NETXEN_NIU_GB_INTERFACE_CTRL(I) \
594 (NETXEN_CRB_NIU + 0x30038 + (I)*0x10000)
595#define NETXEN_NIU_GB_INTERFACE_STATUS(I) \
596 (NETXEN_CRB_NIU + 0x3003c + (I)*0x10000)
597#define NETXEN_NIU_GB_STATION_ADDR_0(I) \
598 (NETXEN_CRB_NIU + 0x30040 + (I)*0x10000)
599#define NETXEN_NIU_GB_STATION_ADDR_1(I) \
600 (NETXEN_CRB_NIU + 0x30044 + (I)*0x10000)
601
602#define NETXEN_NIU_XGE_CONFIG_0 (NETXEN_CRB_NIU + 0x70000)
603#define NETXEN_NIU_XGE_CONFIG_1 (NETXEN_CRB_NIU + 0x70004)
604#define NETXEN_NIU_XGE_IPG (NETXEN_CRB_NIU + 0x70008)
605#define NETXEN_NIU_XGE_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x7000c)
606#define NETXEN_NIU_XGE_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x70010)
607#define NETXEN_NIU_XGE_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x70014)
608#define NETXEN_NIU_XGE_STATUS (NETXEN_CRB_NIU + 0x70018)
609#define NETXEN_NIU_XGE_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x7001c)
610#define NETXEN_NIU_XGE_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x70020)
611#define NETXEN_NIU_XGE_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x70024)
612#define NETXEN_NIU_XGE_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x70028)
613#define NETXEN_NIU_XGE_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x7002c)
614#define NETXEN_NIU_XGE_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x70030)
615#define NETXEN_NIU_XGE_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x70034)
616#define NETXEN_NIU_XGE_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x70038)
617#define NETXEN_NIU_XGE_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x7003c)
618#define NETXEN_NIU_XGE_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x70040)
619#define NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70044)
620#define NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x70048)
621#define NETXEN_NIU_XGE_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x7004c)
622#define NETXEN_NIU_XGE_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x70050)
623#define NETXEN_NIU_XGE_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x70054)
624#define NETXEN_NIU_XGE_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x70058)
625#define NETXEN_NIU_XG1_CONFIG_0 (NETXEN_CRB_NIU + 0x80000)
626#define NETXEN_NIU_XG1_CONFIG_1 (NETXEN_CRB_NIU + 0x80004)
627#define NETXEN_NIU_XG1_IPG (NETXEN_CRB_NIU + 0x80008)
628#define NETXEN_NIU_XG1_STATION_ADDR_0_HI (NETXEN_CRB_NIU + 0x8000c)
629#define NETXEN_NIU_XG1_STATION_ADDR_0_1 (NETXEN_CRB_NIU + 0x80010)
630#define NETXEN_NIU_XG1_STATION_ADDR_1_LO (NETXEN_CRB_NIU + 0x80014)
631#define NETXEN_NIU_XG1_STATUS (NETXEN_CRB_NIU + 0x80018)
632#define NETXEN_NIU_XG1_MAX_FRAME_SIZE (NETXEN_CRB_NIU + 0x8001c)
633#define NETXEN_NIU_XG1_PAUSE_FRAME_VALUE (NETXEN_CRB_NIU + 0x80020)
634#define NETXEN_NIU_XG1_TX_BYTE_CNT (NETXEN_CRB_NIU + 0x80024)
635#define NETXEN_NIU_XG1_TX_FRAME_CNT (NETXEN_CRB_NIU + 0x80028)
636#define NETXEN_NIU_XG1_RX_BYTE_CNT (NETXEN_CRB_NIU + 0x8002c)
637#define NETXEN_NIU_XG1_RX_FRAME_CNT (NETXEN_CRB_NIU + 0x80030)
638#define NETXEN_NIU_XG1_AGGR_ERROR_CNT (NETXEN_CRB_NIU + 0x80034)
639#define NETXEN_NIU_XG1_MULTICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x80038)
640#define NETXEN_NIU_XG1_UNICAST_FRAME_CNT (NETXEN_CRB_NIU + 0x8003c)
641#define NETXEN_NIU_XG1_CRC_ERROR_CNT (NETXEN_CRB_NIU + 0x80040)
642#define NETXEN_NIU_XG1_OVERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80044)
643#define NETXEN_NIU_XG1_UNDERSIZE_FRAME_ERR (NETXEN_CRB_NIU + 0x80048)
644#define NETXEN_NIU_XG1_LOCAL_ERROR_CNT (NETXEN_CRB_NIU + 0x8004c)
645#define NETXEN_NIU_XG1_REMOTE_ERROR_CNT (NETXEN_CRB_NIU + 0x80050)
646#define NETXEN_NIU_XG1_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x80054)
647#define NETXEN_NIU_XG1_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x80058)
648
649/* P3 802.3ap */
650#define NETXEN_NIU_AP_MAC_CONFIG_0(I) (NETXEN_CRB_NIU+0xa0000+(I)*0x10000)
651#define NETXEN_NIU_AP_MAC_CONFIG_1(I) (NETXEN_CRB_NIU+0xa0004+(I)*0x10000)
652#define NETXEN_NIU_AP_MAC_IPG_IFG(I) (NETXEN_CRB_NIU+0xa0008+(I)*0x10000)
653#define NETXEN_NIU_AP_HALF_DUPLEX_CTRL(I) (NETXEN_CRB_NIU+0xa000c+(I)*0x10000)
654#define NETXEN_NIU_AP_MAX_FRAME_SIZE(I) (NETXEN_CRB_NIU+0xa0010+(I)*0x10000)
655#define NETXEN_NIU_AP_TEST_REG(I) (NETXEN_CRB_NIU+0xa001c+(I)*0x10000)
656#define NETXEN_NIU_AP_MII_MGMT_CONFIG(I) (NETXEN_CRB_NIU+0xa0020+(I)*0x10000)
657#define NETXEN_NIU_AP_MII_MGMT_COMMAND(I) (NETXEN_CRB_NIU+0xa0024+(I)*0x10000)
658#define NETXEN_NIU_AP_MII_MGMT_ADDR(I) (NETXEN_CRB_NIU+0xa0028+(I)*0x10000)
659#define NETXEN_NIU_AP_MII_MGMT_CTRL(I) (NETXEN_CRB_NIU+0xa002c+(I)*0x10000)
660#define NETXEN_NIU_AP_MII_MGMT_STATUS(I) (NETXEN_CRB_NIU+0xa0030+(I)*0x10000)
661#define NETXEN_NIU_AP_MII_MGMT_INDICATE(I) (NETXEN_CRB_NIU+0xa0034+(I)*0x10000)
662#define NETXEN_NIU_AP_INTERFACE_CTRL(I) (NETXEN_CRB_NIU+0xa0038+(I)*0x10000)
663#define NETXEN_NIU_AP_INTERFACE_STATUS(I) (NETXEN_CRB_NIU+0xa003c+(I)*0x10000)
664#define NETXEN_NIU_AP_STATION_ADDR_0(I) (NETXEN_CRB_NIU+0xa0040+(I)*0x10000)
665#define NETXEN_NIU_AP_STATION_ADDR_1(I) (NETXEN_CRB_NIU+0xa0044+(I)*0x10000)
666
667
668#define TEST_AGT_CTRL (0x00)
669
670#define TA_CTL_START 1
671#define TA_CTL_ENABLE 2
672#define TA_CTL_WRITE 4
673#define TA_CTL_BUSY 8
674
675/*
676 * Register offsets for MN
677 */
678#define MIU_TEST_AGT_BASE (0x90)
679
680#define MIU_TEST_AGT_ADDR_LO (0x04)
681#define MIU_TEST_AGT_ADDR_HI (0x08)
682#define MIU_TEST_AGT_WRDATA_LO (0x10)
683#define MIU_TEST_AGT_WRDATA_HI (0x14)
684#define MIU_TEST_AGT_RDDATA_LO (0x18)
685#define MIU_TEST_AGT_RDDATA_HI (0x1c)
686
687#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
688#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
689
690/*
691 * Register offsets for MS
692 */
693#define SIU_TEST_AGT_BASE (0x60)
694
695#define SIU_TEST_AGT_ADDR_LO (0x04)
696#define SIU_TEST_AGT_ADDR_HI (0x18)
697#define SIU_TEST_AGT_WRDATA_LO (0x08)
698#define SIU_TEST_AGT_WRDATA_HI (0x0c)
699#define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i)))
700#define SIU_TEST_AGT_RDDATA_LO (0x10)
701#define SIU_TEST_AGT_RDDATA_HI (0x14)
702#define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i)))
703
704#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
705#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
706
707/* XG Link status */
708#define XG_LINK_UP 0x10
709#define XG_LINK_DOWN 0x20
710
711#define XG_LINK_UP_P3 0x01
712#define XG_LINK_DOWN_P3 0x02
713#define XG_LINK_STATE_P3_MASK 0xf
714#define XG_LINK_STATE_P3(pcifn,val) \
715 (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK)
716
717#define P3_LINK_SPEED_MHZ 100
718#define P3_LINK_SPEED_MASK 0xff
719#define P3_LINK_SPEED_REG(pcifn) \
720 (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4))
721#define P3_LINK_SPEED_VAL(pcifn, reg) \
722 (((reg) >> (8 * ((pcifn) & 0x3))) & P3_LINK_SPEED_MASK)
723
724#define NETXEN_CAM_RAM_BASE (NETXEN_CRB_CAM + 0x02000)
725#define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg))
726#define NETXEN_FW_VERSION_MAJOR (NETXEN_CAM_RAM(0x150))
727#define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154))
728#define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158))
729#define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100))
730#define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120))
731#define NETXEN_CRB_WIN_LOCK_ID (NETXEN_CAM_RAM(0x124))
732
733#define NIC_CRB_BASE (NETXEN_CAM_RAM(0x200))
734#define NIC_CRB_BASE_2 (NETXEN_CAM_RAM(0x700))
735#define NETXEN_NIC_REG(X) (NIC_CRB_BASE+(X))
736#define NETXEN_NIC_REG_2(X) (NIC_CRB_BASE_2+(X))
737
738#define NX_CDRP_CRB_OFFSET (NETXEN_NIC_REG(0x18))
739#define NX_ARG1_CRB_OFFSET (NETXEN_NIC_REG(0x1c))
740#define NX_ARG2_CRB_OFFSET (NETXEN_NIC_REG(0x20))
741#define NX_ARG3_CRB_OFFSET (NETXEN_NIC_REG(0x24))
742#define NX_SIGN_CRB_OFFSET (NETXEN_NIC_REG(0x28))
743
744#define CRB_HOST_DUMMY_BUF_ADDR_HI (NETXEN_NIC_REG(0x3c))
745#define CRB_HOST_DUMMY_BUF_ADDR_LO (NETXEN_NIC_REG(0x40))
746
747#define CRB_CMDPEG_STATE (NETXEN_NIC_REG(0x50))
748#define CRB_RCVPEG_STATE (NETXEN_NIC_REG(0x13c))
749
750#define CRB_XG_STATE (NETXEN_NIC_REG(0x94))
751#define CRB_XG_STATE_P3 (NETXEN_NIC_REG(0x98))
752#define CRB_PF_LINK_SPEED_1 (NETXEN_NIC_REG(0xe8))
753#define CRB_PF_LINK_SPEED_2 (NETXEN_NIC_REG(0xec))
754
755#define CRB_MPORT_MODE (NETXEN_NIC_REG(0xc4))
756#define CRB_DMA_SHIFT (NETXEN_NIC_REG(0xcc))
757#define CRB_INT_VECTOR (NETXEN_NIC_REG(0xd4))
758
759#define CRB_CMD_PRODUCER_OFFSET (NETXEN_NIC_REG(0x08))
760#define CRB_CMD_CONSUMER_OFFSET (NETXEN_NIC_REG(0x0c))
761#define CRB_CMD_PRODUCER_OFFSET_1 (NETXEN_NIC_REG(0x1ac))
762#define CRB_CMD_CONSUMER_OFFSET_1 (NETXEN_NIC_REG(0x1b0))
763#define CRB_CMD_PRODUCER_OFFSET_2 (NETXEN_NIC_REG(0x1b8))
764#define CRB_CMD_CONSUMER_OFFSET_2 (NETXEN_NIC_REG(0x1bc))
765#define CRB_CMD_PRODUCER_OFFSET_3 (NETXEN_NIC_REG(0x1d0))
766#define CRB_CMD_CONSUMER_OFFSET_3 (NETXEN_NIC_REG(0x1d4))
767#define CRB_TEMP_STATE (NETXEN_NIC_REG(0x1b4))
768
769#define CRB_V2P_0 (NETXEN_NIC_REG(0x290))
770#define CRB_V2P(port) (CRB_V2P_0+((port)*4))
771#define CRB_DRIVER_VERSION (NETXEN_NIC_REG(0x2a0))
772
773#define CRB_SW_INT_MASK_0 (NETXEN_NIC_REG(0x1d8))
774#define CRB_SW_INT_MASK_1 (NETXEN_NIC_REG(0x1e0))
775#define CRB_SW_INT_MASK_2 (NETXEN_NIC_REG(0x1e4))
776#define CRB_SW_INT_MASK_3 (NETXEN_NIC_REG(0x1e8))
777
778#define CRB_FW_CAPABILITIES_1 (NETXEN_CAM_RAM(0x128))
779#define CRB_MAC_BLOCK_START (NETXEN_CAM_RAM(0x1c0))
780
781/*
782 * capabilities register, can be used to selectively enable/disable features
783 * for backward compatibility
784 */
785#define CRB_NIC_CAPABILITIES_HOST NETXEN_NIC_REG(0x1a8)
786#define CRB_NIC_MSI_MODE_HOST NETXEN_NIC_REG(0x270)
787
788#define INTR_SCHEME_PERPORT 0x1
789#define MSI_MODE_MULTIFUNC 0x1
790
791/* used for ethtool tests */
792#define CRB_SCRATCHPAD_TEST NETXEN_NIC_REG(0x280)
793
794/*
795 * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
796 * which can be read by the Phantom host to get producer/consumer indexes from
797 * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
798 * registers will be used for the addresses of the ring's shared memory
799 * on the Phantom.
800 */
801
802#define nx_get_temp_val(x) ((x) >> 16)
803#define nx_get_temp_state(x) ((x) & 0xffff)
804#define nx_encode_temp(val, state) (((val) << 16) | (state))
805
806/*
807 * Temperature control.
808 */
809enum {
810 NX_TEMP_NORMAL = 0x1, /* Normal operating range */
811 NX_TEMP_WARN, /* Sound alert, temperature getting high */
812 NX_TEMP_PANIC /* Fatal error, hardware has shut down. */
813};
814
815/* Lock IDs for PHY lock */
816#define PHY_LOCK_DRIVER 0x44524956
817
818/* Used for PS PCI Memory access */
819#define PCIX_PS_OP_ADDR_LO (0x10000)
820/* via CRB (PS side only) */
821#define PCIX_PS_OP_ADDR_HI (0x10004)
822
823#define PCIX_INT_VECTOR (0x10100)
824#define PCIX_INT_MASK (0x10104)
825
826#define PCIX_CRB_WINDOW (0x10210)
827#define PCIX_CRB_WINDOW_F0 (0x10210)
828#define PCIX_CRB_WINDOW_F1 (0x10230)
829#define PCIX_CRB_WINDOW_F2 (0x10250)
830#define PCIX_CRB_WINDOW_F3 (0x10270)
831#define PCIX_CRB_WINDOW_F4 (0x102ac)
832#define PCIX_CRB_WINDOW_F5 (0x102bc)
833#define PCIX_CRB_WINDOW_F6 (0x102cc)
834#define PCIX_CRB_WINDOW_F7 (0x102dc)
835#define PCIE_CRB_WINDOW_REG(func) (((func) < 4) ? \
836 (PCIX_CRB_WINDOW_F0 + (0x20 * (func))) :\
837 (PCIX_CRB_WINDOW_F4 + (0x10 * ((func)-4))))
838
839#define PCIX_MN_WINDOW (0x10200)
840#define PCIX_MN_WINDOW_F0 (0x10200)
841#define PCIX_MN_WINDOW_F1 (0x10220)
842#define PCIX_MN_WINDOW_F2 (0x10240)
843#define PCIX_MN_WINDOW_F3 (0x10260)
844#define PCIX_MN_WINDOW_F4 (0x102a0)
845#define PCIX_MN_WINDOW_F5 (0x102b0)
846#define PCIX_MN_WINDOW_F6 (0x102c0)
847#define PCIX_MN_WINDOW_F7 (0x102d0)
848#define PCIE_MN_WINDOW_REG(func) (((func) < 4) ? \
849 (PCIX_MN_WINDOW_F0 + (0x20 * (func))) :\
850 (PCIX_MN_WINDOW_F4 + (0x10 * ((func)-4))))
851
852#define PCIX_SN_WINDOW (0x10208)
853#define PCIX_SN_WINDOW_F0 (0x10208)
854#define PCIX_SN_WINDOW_F1 (0x10228)
855#define PCIX_SN_WINDOW_F2 (0x10248)
856#define PCIX_SN_WINDOW_F3 (0x10268)
857#define PCIX_SN_WINDOW_F4 (0x102a8)
858#define PCIX_SN_WINDOW_F5 (0x102b8)
859#define PCIX_SN_WINDOW_F6 (0x102c8)
860#define PCIX_SN_WINDOW_F7 (0x102d8)
861#define PCIE_SN_WINDOW_REG(func) (((func) < 4) ? \
862 (PCIX_SN_WINDOW_F0 + (0x20 * (func))) :\
863 (PCIX_SN_WINDOW_F4 + (0x10 * ((func)-4))))
864
865#define PCIX_OCM_WINDOW (0x10800)
866#define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x20 * (func))
867
868#define PCIX_TARGET_STATUS (0x10118)
869#define PCIX_TARGET_STATUS_F1 (0x10160)
870#define PCIX_TARGET_STATUS_F2 (0x10164)
871#define PCIX_TARGET_STATUS_F3 (0x10168)
872#define PCIX_TARGET_STATUS_F4 (0x10360)
873#define PCIX_TARGET_STATUS_F5 (0x10364)
874#define PCIX_TARGET_STATUS_F6 (0x10368)
875#define PCIX_TARGET_STATUS_F7 (0x1036c)
876
877#define PCIX_TARGET_MASK (0x10128)
878#define PCIX_TARGET_MASK_F1 (0x10170)
879#define PCIX_TARGET_MASK_F2 (0x10174)
880#define PCIX_TARGET_MASK_F3 (0x10178)
881#define PCIX_TARGET_MASK_F4 (0x10370)
882#define PCIX_TARGET_MASK_F5 (0x10374)
883#define PCIX_TARGET_MASK_F6 (0x10378)
884#define PCIX_TARGET_MASK_F7 (0x1037c)
885
886#define PCIX_MSI_F0 (0x13000)
887#define PCIX_MSI_F1 (0x13004)
888#define PCIX_MSI_F2 (0x13008)
889#define PCIX_MSI_F3 (0x1300c)
890#define PCIX_MSI_F4 (0x13010)
891#define PCIX_MSI_F5 (0x13014)
892#define PCIX_MSI_F6 (0x13018)
893#define PCIX_MSI_F7 (0x1301c)
894#define PCIX_MSI_F(i) (0x13000+((i)*4))
895
896#define PCIX_PS_MEM_SPACE (0x90000)
897
898#define NETXEN_PCIX_PH_REG(reg) (NETXEN_CRB_PCIE + (reg))
899#define NETXEN_PCIX_PS_REG(reg) (NETXEN_CRB_PCIX_MD + (reg))
900
901#define NETXEN_PCIE_REG(reg) (NETXEN_CRB_PCIE + (reg))
902
903#define PCIE_MAX_DMA_XFER_SIZE (0x1404c)
904
905#define PCIE_DCR 0x00d8
906
907#define PCIE_SEM0_LOCK (0x1c000)
908#define PCIE_SEM0_UNLOCK (0x1c004)
909#define PCIE_SEM1_LOCK (0x1c008)
910#define PCIE_SEM1_UNLOCK (0x1c00c)
911#define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
912#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
913#define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */
914#define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */
915#define PCIE_SEM4_LOCK (0x1c020)
916#define PCIE_SEM4_UNLOCK (0x1c024)
917#define PCIE_SEM5_LOCK (0x1c028) /* API lock */
918#define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */
919#define PCIE_SEM6_LOCK (0x1c030) /* sw lock */
920#define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */
921#define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
922#define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
923#define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N))
924#define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N))
925
926#define PCIE_SETUP_FUNCTION (0x12040)
927#define PCIE_SETUP_FUNCTION2 (0x12048)
928#define PCIE_MISCCFG_RC (0x1206c)
929#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
930#define PCIE_CHICKEN3 (0x120c8)
931
932#define ISR_INT_STATE_REG (NETXEN_PCIX_PS_REG(PCIE_MISCCFG_RC))
933#define PCIE_MAX_MASTER_SPLIT (0x14048)
934
935#define NETXEN_PORT_MODE_NONE 0
936#define NETXEN_PORT_MODE_XG 1
937#define NETXEN_PORT_MODE_GB 2
938#define NETXEN_PORT_MODE_802_3_AP 3
939#define NETXEN_PORT_MODE_AUTO_NEG 4
940#define NETXEN_PORT_MODE_AUTO_NEG_1G 5
941#define NETXEN_PORT_MODE_AUTO_NEG_XG 6
942#define NETXEN_PORT_MODE_ADDR (NETXEN_CAM_RAM(0x24))
943#define NETXEN_WOL_PORT_MODE (NETXEN_CAM_RAM(0x198))
944
945#define NETXEN_WOL_CONFIG_NV (NETXEN_CAM_RAM(0x184))
946#define NETXEN_WOL_CONFIG (NETXEN_CAM_RAM(0x188))
947
948#define NX_PEG_TUNE_MN_PRESENT 0x1
949#define NX_PEG_TUNE_CAPABILITY (NETXEN_CAM_RAM(0x02c))
950
951#define NETXEN_DMA_WATCHDOG_CTRL (NETXEN_CAM_RAM(0x14))
952#define NETXEN_PEG_ALIVE_COUNTER (NETXEN_CAM_RAM(0xb0))
953#define NETXEN_PEG_HALT_STATUS1 (NETXEN_CAM_RAM(0xa8))
954#define NETXEN_PEG_HALT_STATUS2 (NETXEN_CAM_RAM(0xac))
955#define NX_CRB_DEV_REF_COUNT (NETXEN_CAM_RAM(0x138))
956#define NX_CRB_DEV_STATE (NETXEN_CAM_RAM(0x140))
957
958/* Device State */
959#define NX_DEV_COLD 1
960#define NX_DEV_INITALIZING 2
961#define NX_DEV_READY 3
962#define NX_DEV_NEED_RESET 4
963#define NX_DEV_NEED_QUISCENT 5
964#define NX_DEV_NEED_AER 6
965#define NX_DEV_FAILED 7
966
967#define NX_RCODE_DRIVER_INFO 0x20000000
968#define NX_RCODE_DRIVER_CAN_RELOAD 0x40000000
969#define NX_RCODE_FATAL_ERROR 0x80000000
970#define NX_FWERROR_PEGNUM(code) ((code) & 0xff)
971#define NX_FWERROR_CODE(code) ((code >> 8) & 0xfffff)
972
973#define FW_POLL_DELAY (2 * HZ)
974#define FW_FAIL_THRESH 3
975#define FW_POLL_THRESH 10
976
977#define ISR_MSI_INT_TRIGGER(FUNC) (NETXEN_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
978#define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
979
980/*
981 * PCI Interrupt Vector Values.
982 */
983#define PCIX_INT_VECTOR_BIT_F0 0x0080
984#define PCIX_INT_VECTOR_BIT_F1 0x0100
985#define PCIX_INT_VECTOR_BIT_F2 0x0200
986#define PCIX_INT_VECTOR_BIT_F3 0x0400
987#define PCIX_INT_VECTOR_BIT_F4 0x0800
988#define PCIX_INT_VECTOR_BIT_F5 0x1000
989#define PCIX_INT_VECTOR_BIT_F6 0x2000
990#define PCIX_INT_VECTOR_BIT_F7 0x4000
991
992struct netxen_legacy_intr_set {
993 uint32_t int_vec_bit;
994 uint32_t tgt_status_reg;
995 uint32_t tgt_mask_reg;
996 uint32_t pci_int_reg;
997};
998
999#define NX_LEGACY_INTR_CONFIG \
1000{ \
1001 { \
1002 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
1003 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
1004 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
1005 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
1006 \
1007 { \
1008 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
1009 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
1010 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
1011 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
1012 \
1013 { \
1014 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
1015 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
1016 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
1017 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
1018 \
1019 { \
1020 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
1021 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
1022 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
1023 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
1024 \
1025 { \
1026 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
1027 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
1028 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
1029 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
1030 \
1031 { \
1032 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
1033 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
1034 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
1035 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
1036 \
1037 { \
1038 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
1039 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
1040 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
1041 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
1042 \
1043 { \
1044 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
1045 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
1046 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
1047 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
1048}
1049
1050#endif /* __NETXEN_NIC_HDR_H_ */
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
new file mode 100644
index 00000000000..3f89e57cae5
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -0,0 +1,1976 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#include <linux/slab.h>
27#include "netxen_nic.h"
28#include "netxen_nic_hw.h"
29
30#include <net/ip.h>
31
32#define MASK(n) ((1ULL<<(n))-1)
33#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
34#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
35#define MS_WIN(addr) (addr & 0x0ffc0000)
36
37#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38
39#define CRB_BLK(off) ((off >> 20) & 0x3f)
40#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41#define CRB_WINDOW_2M (0x130060)
42#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43#define CRB_INDIRECT_2M (0x1e0000UL)
44
45static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
48 void __iomem *addr);
49
50#ifndef readq
51static inline u64 readq(void __iomem *addr)
52{
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54}
55#endif
56
57#ifndef writeq
58static inline void writeq(u64 val, void __iomem *addr)
59{
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62}
63#endif
64
65#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
66 ((adapter)->ahw.pci_base0 + (off))
67#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
69#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
71
72static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
73 unsigned long off)
74{
75 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
76 return PCI_OFFSET_FIRST_RANGE(adapter, off);
77
78 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
79 return PCI_OFFSET_SECOND_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
82 return PCI_OFFSET_THIRD_RANGE(adapter, off);
83
84 return NULL;
85}
86
87static crb_128M_2M_block_map_t
88crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
89 {{{0, 0, 0, 0} } }, /* 0: PCI */
90 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
91 {1, 0x0110000, 0x0120000, 0x130000},
92 {1, 0x0120000, 0x0122000, 0x124000},
93 {1, 0x0130000, 0x0132000, 0x126000},
94 {1, 0x0140000, 0x0142000, 0x128000},
95 {1, 0x0150000, 0x0152000, 0x12a000},
96 {1, 0x0160000, 0x0170000, 0x110000},
97 {1, 0x0170000, 0x0172000, 0x12e000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {1, 0x01e0000, 0x01e0800, 0x122000},
105 {0, 0x0000000, 0x0000000, 0x000000} } },
106 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
107 {{{0, 0, 0, 0} } }, /* 3: */
108 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
109 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
110 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
111 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
112 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x08f0000, 0x08f2000, 0x172000} } },
128 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {1, 0x09f0000, 0x09f2000, 0x176000} } },
144 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
160 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
176 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
177 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
178 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
179 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
180 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
181 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
182 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
183 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
184 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
185 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
186 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
187 {{{0, 0, 0, 0} } }, /* 23: */
188 {{{0, 0, 0, 0} } }, /* 24: */
189 {{{0, 0, 0, 0} } }, /* 25: */
190 {{{0, 0, 0, 0} } }, /* 26: */
191 {{{0, 0, 0, 0} } }, /* 27: */
192 {{{0, 0, 0, 0} } }, /* 28: */
193 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
194 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
195 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
196 {{{0} } }, /* 32: PCI */
197 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
198 {1, 0x2110000, 0x2120000, 0x130000},
199 {1, 0x2120000, 0x2122000, 0x124000},
200 {1, 0x2130000, 0x2132000, 0x126000},
201 {1, 0x2140000, 0x2142000, 0x128000},
202 {1, 0x2150000, 0x2152000, 0x12a000},
203 {1, 0x2160000, 0x2170000, 0x110000},
204 {1, 0x2170000, 0x2172000, 0x12e000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000} } },
213 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
214 {{{0} } }, /* 35: */
215 {{{0} } }, /* 36: */
216 {{{0} } }, /* 37: */
217 {{{0} } }, /* 38: */
218 {{{0} } }, /* 39: */
219 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
220 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
221 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
222 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
223 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
224 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
225 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
226 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
227 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
228 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
229 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
230 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
231 {{{0} } }, /* 52: */
232 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
233 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
234 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
235 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
236 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
237 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
238 {{{0} } }, /* 59: I2C0 */
239 {{{0} } }, /* 60: I2C1 */
240 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
241 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
242 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
243};
244
245/*
246 * top 12 bits of crb internal address (hub, agent)
247 */
248static unsigned crb_hub_agt[64] =
249{
250 0,
251 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
252 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
253 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
254 0,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
256 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
257 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
263 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
264 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
277 0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
279 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
280 0,
281 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
282 0,
283 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
284 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
285 0,
286 0,
287 0,
288 0,
289 0,
290 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
291 0,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
299 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
300 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
301 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
302 0,
303 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
304 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
306 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
307 0,
308 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
309 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
311 0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
313 0,
314};
315
316/* PCI Windowing for DDR regions. */
317
318#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
319
320#define NETXEN_PCIE_SEM_TIMEOUT 10000
321
322static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
323
324int
325netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
326{
327 int done = 0, timeout = 0;
328
329 while (!done) {
330 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
331 if (done == 1)
332 break;
333 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
334 return -EIO;
335 msleep(1);
336 }
337
338 if (id_reg)
339 NXWR32(adapter, id_reg, adapter->portnum);
340
341 return 0;
342}
343
344void
345netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
346{
347 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
348}
349
350static int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
351{
352 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
353 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
355 }
356
357 return 0;
358}
359
360/* Disable an XG interface */
361static int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
362{
363 __u32 mac_cfg;
364 u32 port = adapter->physical_port;
365
366 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
367 return 0;
368
369 if (port > NETXEN_NIU_MAX_XG_PORTS)
370 return -EINVAL;
371
372 mac_cfg = 0;
373 if (NXWR32(adapter,
374 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
375 return -EIO;
376 return 0;
377}
378
379#define NETXEN_UNICAST_ADDR(port, index) \
380 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
381#define NETXEN_MCAST_ADDR(port, index) \
382 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
383#define MAC_HI(addr) \
384 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
385#define MAC_LO(addr) \
386 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
387
388static int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
389{
390 u32 mac_cfg;
391 u32 cnt = 0;
392 __u32 reg = 0x0200;
393 u32 port = adapter->physical_port;
394 u16 board_type = adapter->ahw.board_type;
395
396 if (port > NETXEN_NIU_MAX_XG_PORTS)
397 return -EINVAL;
398
399 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
400 mac_cfg &= ~0x4;
401 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
402
403 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
404 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
405 reg = (0x20 << port);
406
407 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
408
409 mdelay(10);
410
411 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
412 mdelay(10);
413
414 if (cnt < 20) {
415
416 reg = NXRD32(adapter,
417 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
418
419 if (mode == NETXEN_NIU_PROMISC_MODE)
420 reg = (reg | 0x2000UL);
421 else
422 reg = (reg & ~0x2000UL);
423
424 if (mode == NETXEN_NIU_ALLMULTI_MODE)
425 reg = (reg | 0x1000UL);
426 else
427 reg = (reg & ~0x1000UL);
428
429 NXWR32(adapter,
430 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
431 }
432
433 mac_cfg |= 0x4;
434 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
435
436 return 0;
437}
438
439static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
440{
441 u32 mac_hi, mac_lo;
442 u32 reg_hi, reg_lo;
443
444 u8 phy = adapter->physical_port;
445
446 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
447 return -EINVAL;
448
449 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
450 mac_hi = addr[2] | ((u32)addr[3] << 8) |
451 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
452
453 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
454 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
455
456 /* write twice to flush */
457 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
458 return -EIO;
459 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
460 return -EIO;
461
462 return 0;
463}
464
465static int
466netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
467{
468 u32 val = 0;
469 u16 port = adapter->physical_port;
470 u8 *addr = adapter->mac_addr;
471
472 if (adapter->mc_enabled)
473 return 0;
474
475 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
476 val |= (1UL << (28+port));
477 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
478
479 /* add broadcast addr to filter */
480 val = 0xffffff;
481 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
483
484 /* add station addr to filter */
485 val = MAC_HI(addr);
486 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
487 val = MAC_LO(addr);
488 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
489
490 adapter->mc_enabled = 1;
491 return 0;
492}
493
494static int
495netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
496{
497 u32 val = 0;
498 u16 port = adapter->physical_port;
499 u8 *addr = adapter->mac_addr;
500
501 if (!adapter->mc_enabled)
502 return 0;
503
504 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
505 val &= ~(1UL << (28+port));
506 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
507
508 val = MAC_HI(addr);
509 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
510 val = MAC_LO(addr);
511 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
512
513 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
514 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
515
516 adapter->mc_enabled = 0;
517 return 0;
518}
519
520static int
521netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
522 int index, u8 *addr)
523{
524 u32 hi = 0, lo = 0;
525 u16 port = adapter->physical_port;
526
527 lo = MAC_LO(addr);
528 hi = MAC_HI(addr);
529
530 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
531 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
532
533 return 0;
534}
535
536static void netxen_p2_nic_set_multi(struct net_device *netdev)
537{
538 struct netxen_adapter *adapter = netdev_priv(netdev);
539 struct netdev_hw_addr *ha;
540 u8 null_addr[6];
541 int i;
542
543 memset(null_addr, 0, 6);
544
545 if (netdev->flags & IFF_PROMISC) {
546
547 adapter->set_promisc(adapter,
548 NETXEN_NIU_PROMISC_MODE);
549
550 /* Full promiscuous mode */
551 netxen_nic_disable_mcast_filter(adapter);
552
553 return;
554 }
555
556 if (netdev_mc_empty(netdev)) {
557 adapter->set_promisc(adapter,
558 NETXEN_NIU_NON_PROMISC_MODE);
559 netxen_nic_disable_mcast_filter(adapter);
560 return;
561 }
562
563 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
564 if (netdev->flags & IFF_ALLMULTI ||
565 netdev_mc_count(netdev) > adapter->max_mc_count) {
566 netxen_nic_disable_mcast_filter(adapter);
567 return;
568 }
569
570 netxen_nic_enable_mcast_filter(adapter);
571
572 i = 0;
573 netdev_for_each_mc_addr(ha, netdev)
574 netxen_nic_set_mcast_addr(adapter, i++, ha->addr);
575
576 /* Clear out remaining addresses */
577 while (i < adapter->max_mc_count)
578 netxen_nic_set_mcast_addr(adapter, i++, null_addr);
579}
580
581static int
582netxen_send_cmd_descs(struct netxen_adapter *adapter,
583 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
584{
585 u32 i, producer, consumer;
586 struct netxen_cmd_buffer *pbuf;
587 struct cmd_desc_type0 *cmd_desc;
588 struct nx_host_tx_ring *tx_ring;
589
590 i = 0;
591
592 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
593 return -EIO;
594
595 tx_ring = adapter->tx_ring;
596 __netif_tx_lock_bh(tx_ring->txq);
597
598 producer = tx_ring->producer;
599 consumer = tx_ring->sw_consumer;
600
601 if (nr_desc >= netxen_tx_avail(tx_ring)) {
602 netif_tx_stop_queue(tx_ring->txq);
603 smp_mb();
604 if (netxen_tx_avail(tx_ring) > nr_desc) {
605 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
606 netif_tx_wake_queue(tx_ring->txq);
607 } else {
608 __netif_tx_unlock_bh(tx_ring->txq);
609 return -EBUSY;
610 }
611 }
612
613 do {
614 cmd_desc = &cmd_desc_arr[i];
615
616 pbuf = &tx_ring->cmd_buf_arr[producer];
617 pbuf->skb = NULL;
618 pbuf->frag_count = 0;
619
620 memcpy(&tx_ring->desc_head[producer],
621 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
622
623 producer = get_next_index(producer, tx_ring->num_desc);
624 i++;
625
626 } while (i != nr_desc);
627
628 tx_ring->producer = producer;
629
630 netxen_nic_update_cmd_producer(adapter, tx_ring);
631
632 __netif_tx_unlock_bh(tx_ring->txq);
633
634 return 0;
635}
636
637static int
638nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
639{
640 nx_nic_req_t req;
641 nx_mac_req_t *mac_req;
642 u64 word;
643
644 memset(&req, 0, sizeof(nx_nic_req_t));
645 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
646
647 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
648 req.req_hdr = cpu_to_le64(word);
649
650 mac_req = (nx_mac_req_t *)&req.words[0];
651 mac_req->op = op;
652 memcpy(mac_req->mac_addr, addr, 6);
653
654 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
655}
656
657static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
658 const u8 *addr, struct list_head *del_list)
659{
660 struct list_head *head;
661 nx_mac_list_t *cur;
662
663 /* look up if already exists */
664 list_for_each(head, del_list) {
665 cur = list_entry(head, nx_mac_list_t, list);
666
667 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
668 list_move_tail(head, &adapter->mac_list);
669 return 0;
670 }
671 }
672
673 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
674 if (cur == NULL) {
675 printk(KERN_ERR "%s: failed to add mac address filter\n",
676 adapter->netdev->name);
677 return -ENOMEM;
678 }
679 memcpy(cur->mac_addr, addr, ETH_ALEN);
680 list_add_tail(&cur->list, &adapter->mac_list);
681 return nx_p3_sre_macaddr_change(adapter,
682 cur->mac_addr, NETXEN_MAC_ADD);
683}
684
685static void netxen_p3_nic_set_multi(struct net_device *netdev)
686{
687 struct netxen_adapter *adapter = netdev_priv(netdev);
688 struct netdev_hw_addr *ha;
689 static const u8 bcast_addr[ETH_ALEN] = {
690 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
691 };
692 u32 mode = VPORT_MISS_MODE_DROP;
693 LIST_HEAD(del_list);
694 struct list_head *head;
695 nx_mac_list_t *cur;
696
697 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
698 return;
699
700 list_splice_tail_init(&adapter->mac_list, &del_list);
701
702 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
703 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
704
705 if (netdev->flags & IFF_PROMISC) {
706 mode = VPORT_MISS_MODE_ACCEPT_ALL;
707 goto send_fw_cmd;
708 }
709
710 if ((netdev->flags & IFF_ALLMULTI) ||
711 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
712 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
713 goto send_fw_cmd;
714 }
715
716 if (!netdev_mc_empty(netdev)) {
717 netdev_for_each_mc_addr(ha, netdev)
718 nx_p3_nic_add_mac(adapter, ha->addr, &del_list);
719 }
720
721send_fw_cmd:
722 adapter->set_promisc(adapter, mode);
723 head = &del_list;
724 while (!list_empty(head)) {
725 cur = list_entry(head->next, nx_mac_list_t, list);
726
727 nx_p3_sre_macaddr_change(adapter,
728 cur->mac_addr, NETXEN_MAC_DEL);
729 list_del(&cur->list);
730 kfree(cur);
731 }
732}
733
734static int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
735{
736 nx_nic_req_t req;
737 u64 word;
738
739 memset(&req, 0, sizeof(nx_nic_req_t));
740
741 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
742
743 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
744 ((u64)adapter->portnum << 16);
745 req.req_hdr = cpu_to_le64(word);
746
747 req.words[0] = cpu_to_le64(mode);
748
749 return netxen_send_cmd_descs(adapter,
750 (struct cmd_desc_type0 *)&req, 1);
751}
752
753void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
754{
755 nx_mac_list_t *cur;
756 struct list_head *head = &adapter->mac_list;
757
758 while (!list_empty(head)) {
759 cur = list_entry(head->next, nx_mac_list_t, list);
760 nx_p3_sre_macaddr_change(adapter,
761 cur->mac_addr, NETXEN_MAC_DEL);
762 list_del(&cur->list);
763 kfree(cur);
764 }
765}
766
767static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
768{
769 /* assuming caller has already copied new addr to netdev */
770 netxen_p3_nic_set_multi(adapter->netdev);
771 return 0;
772}
773
774#define NETXEN_CONFIG_INTR_COALESCE 3
775
776/*
777 * Send the interrupt coalescing parameter set by ethtool to the card.
778 */
779int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
780{
781 nx_nic_req_t req;
782 u64 word[6];
783 int rv, i;
784
785 memset(&req, 0, sizeof(nx_nic_req_t));
786 memset(word, 0, sizeof(word));
787
788 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
789
790 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
791 req.req_hdr = cpu_to_le64(word[0]);
792
793 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
794 for (i = 0; i < 6; i++)
795 req.words[i] = cpu_to_le64(word[i]);
796
797 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
798 if (rv != 0) {
799 printk(KERN_ERR "ERROR. Could not send "
800 "interrupt coalescing parameters\n");
801 }
802
803 return rv;
804}
805
806int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
807{
808 nx_nic_req_t req;
809 u64 word;
810 int rv = 0;
811
812 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
813 return 0;
814
815 memset(&req, 0, sizeof(nx_nic_req_t));
816
817 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
818
819 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
820 req.req_hdr = cpu_to_le64(word);
821
822 req.words[0] = cpu_to_le64(enable);
823
824 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
825 if (rv != 0) {
826 printk(KERN_ERR "ERROR. Could not send "
827 "configure hw lro request\n");
828 }
829
830 return rv;
831}
832
833int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
834{
835 nx_nic_req_t req;
836 u64 word;
837 int rv = 0;
838
839 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
840 return rv;
841
842 memset(&req, 0, sizeof(nx_nic_req_t));
843
844 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
845
846 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
847 ((u64)adapter->portnum << 16);
848 req.req_hdr = cpu_to_le64(word);
849
850 req.words[0] = cpu_to_le64(enable);
851
852 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
853 if (rv != 0) {
854 printk(KERN_ERR "ERROR. Could not send "
855 "configure bridge mode request\n");
856 }
857
858 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
859
860 return rv;
861}
862
863
864#define RSS_HASHTYPE_IP_TCP 0x3
865
866int netxen_config_rss(struct netxen_adapter *adapter, int enable)
867{
868 nx_nic_req_t req;
869 u64 word;
870 int i, rv;
871
872 static const u64 key[] = {
873 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
874 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
875 0x255b0ec26d5a56daULL
876 };
877
878
879 memset(&req, 0, sizeof(nx_nic_req_t));
880 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
881
882 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
883 req.req_hdr = cpu_to_le64(word);
884
885 /*
886 * RSS request:
887 * bits 3-0: hash_method
888 * 5-4: hash_type_ipv4
889 * 7-6: hash_type_ipv6
890 * 8: enable
891 * 9: use indirection table
892 * 47-10: reserved
893 * 63-48: indirection table mask
894 */
895 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
896 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
897 ((u64)(enable & 0x1) << 8) |
898 ((0x7ULL) << 48);
899 req.words[0] = cpu_to_le64(word);
900 for (i = 0; i < ARRAY_SIZE(key); i++)
901 req.words[i+1] = cpu_to_le64(key[i]);
902
903
904 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
905 if (rv != 0) {
906 printk(KERN_ERR "%s: could not configure RSS\n",
907 adapter->netdev->name);
908 }
909
910 return rv;
911}
912
913int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
914{
915 nx_nic_req_t req;
916 u64 word;
917 int rv;
918
919 memset(&req, 0, sizeof(nx_nic_req_t));
920 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
921
922 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
923 req.req_hdr = cpu_to_le64(word);
924
925 req.words[0] = cpu_to_le64(cmd);
926 req.words[1] = cpu_to_le64(ip);
927
928 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
929 if (rv != 0) {
930 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
931 adapter->netdev->name,
932 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
933 }
934 return rv;
935}
936
937int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
938{
939 nx_nic_req_t req;
940 u64 word;
941 int rv;
942
943 memset(&req, 0, sizeof(nx_nic_req_t));
944 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
945
946 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
947 req.req_hdr = cpu_to_le64(word);
948 req.words[0] = cpu_to_le64(enable | (enable << 8));
949
950 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
951 if (rv != 0) {
952 printk(KERN_ERR "%s: could not configure link notification\n",
953 adapter->netdev->name);
954 }
955
956 return rv;
957}
958
959int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
960{
961 nx_nic_req_t req;
962 u64 word;
963 int rv;
964
965 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
966 return 0;
967
968 memset(&req, 0, sizeof(nx_nic_req_t));
969 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
970
971 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
972 ((u64)adapter->portnum << 16) |
973 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
974
975 req.req_hdr = cpu_to_le64(word);
976
977 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
978 if (rv != 0) {
979 printk(KERN_ERR "%s: could not cleanup lro flows\n",
980 adapter->netdev->name);
981 }
982 return rv;
983}
984
985/*
986 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
987 * @returns 0 on success, negative on failure
988 */
989
990#define MTU_FUDGE_FACTOR 100
991
992int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
993{
994 struct netxen_adapter *adapter = netdev_priv(netdev);
995 int max_mtu;
996 int rc = 0;
997
998 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
999 max_mtu = P3_MAX_MTU;
1000 else
1001 max_mtu = P2_MAX_MTU;
1002
1003 if (mtu > max_mtu) {
1004 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
1005 netdev->name, max_mtu);
1006 return -EINVAL;
1007 }
1008
1009 if (adapter->set_mtu)
1010 rc = adapter->set_mtu(adapter, mtu);
1011
1012 if (!rc)
1013 netdev->mtu = mtu;
1014
1015 return rc;
1016}
1017
1018static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
1019 int size, __le32 * buf)
1020{
1021 int i, v, addr;
1022 __le32 *ptr32;
1023
1024 addr = base;
1025 ptr32 = buf;
1026 for (i = 0; i < size / sizeof(u32); i++) {
1027 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1028 return -1;
1029 *ptr32 = cpu_to_le32(v);
1030 ptr32++;
1031 addr += sizeof(u32);
1032 }
1033 if ((char *)buf + size > (char *)ptr32) {
1034 __le32 local;
1035 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1036 return -1;
1037 local = cpu_to_le32(v);
1038 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1039 }
1040
1041 return 0;
1042}
1043
1044int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1045{
1046 __le32 *pmac = (__le32 *) mac;
1047 u32 offset;
1048
1049 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1050
1051 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1052 return -1;
1053
1054 if (*mac == cpu_to_le64(~0ULL)) {
1055
1056 offset = NX_OLD_MAC_ADDR_OFFSET +
1057 (adapter->portnum * sizeof(u64));
1058
1059 if (netxen_get_flash_block(adapter,
1060 offset, sizeof(u64), pmac) == -1)
1061 return -1;
1062
1063 if (*mac == cpu_to_le64(~0ULL))
1064 return -1;
1065 }
1066 return 0;
1067}
1068
1069int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1070{
1071 uint32_t crbaddr, mac_hi, mac_lo;
1072 int pci_func = adapter->ahw.pci_func;
1073
1074 crbaddr = CRB_MAC_BLOCK_START +
1075 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1076
1077 mac_lo = NXRD32(adapter, crbaddr);
1078 mac_hi = NXRD32(adapter, crbaddr+4);
1079
1080 if (pci_func & 1)
1081 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1082 else
1083 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1084
1085 return 0;
1086}
1087
1088/*
1089 * Changes the CRB window to the specified window.
1090 */
1091static void
1092netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1093 u32 window)
1094{
1095 void __iomem *offset;
1096 int count = 10;
1097 u8 func = adapter->ahw.pci_func;
1098
1099 if (adapter->ahw.crb_win == window)
1100 return;
1101
1102 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1103 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1104
1105 writel(window, offset);
1106 do {
1107 if (window == readl(offset))
1108 break;
1109
1110 if (printk_ratelimit())
1111 dev_warn(&adapter->pdev->dev,
1112 "failed to set CRB window to %d\n",
1113 (window == NETXEN_WINDOW_ONE));
1114 udelay(1);
1115
1116 } while (--count > 0);
1117
1118 if (count > 0)
1119 adapter->ahw.crb_win = window;
1120}
1121
1122/*
1123 * Returns < 0 if off is not valid,
1124 * 1 if window access is needed. 'off' is set to offset from
1125 * CRB space in 128M pci map
1126 * 0 if no window access is needed. 'off' is set to 2M addr
1127 * In: 'off' is offset from base in 128M pci map
1128 */
1129static int
1130netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1131 ulong off, void __iomem **addr)
1132{
1133 crb_128M_2M_sub_block_map_t *m;
1134
1135
1136 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
1137 return -EINVAL;
1138
1139 off -= NETXEN_PCI_CRBSPACE;
1140
1141 /*
1142 * Try direct map
1143 */
1144 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1145
1146 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1147 *addr = adapter->ahw.pci_base0 + m->start_2M +
1148 (off - m->start_128M);
1149 return 0;
1150 }
1151
1152 /*
1153 * Not in direct map, use crb window
1154 */
1155 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1156 (off & MASK(16));
1157 return 1;
1158}
1159
1160/*
1161 * In: 'off' is offset from CRB space in 128M pci map
1162 * Out: 'off' is 2M pci map addr
1163 * side effect: lock crb window
1164 */
1165static void
1166netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
1167{
1168 u32 window;
1169 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1170
1171 off -= NETXEN_PCI_CRBSPACE;
1172
1173 window = CRB_HI(off);
1174
1175 writel(window, addr);
1176 if (readl(addr) != window) {
1177 if (printk_ratelimit())
1178 dev_warn(&adapter->pdev->dev,
1179 "failed to set CRB window to %d off 0x%lx\n",
1180 window, off);
1181 }
1182}
1183
1184static void __iomem *
1185netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1186 ulong win_off, void __iomem **mem_ptr)
1187{
1188 ulong off = win_off;
1189 void __iomem *addr;
1190 resource_size_t mem_base;
1191
1192 if (ADDR_IN_WINDOW1(win_off))
1193 off = NETXEN_CRB_NORMAL(win_off);
1194
1195 addr = pci_base_offset(adapter, off);
1196 if (addr)
1197 return addr;
1198
1199 if (adapter->ahw.pci_len0 == 0)
1200 off -= NETXEN_PCI_CRBSPACE;
1201
1202 mem_base = pci_resource_start(adapter->pdev, 0);
1203 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1204 if (*mem_ptr)
1205 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1206
1207 return addr;
1208}
1209
1210static int
1211netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1212{
1213 unsigned long flags;
1214 void __iomem *addr, *mem_ptr = NULL;
1215
1216 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1217 if (!addr)
1218 return -EIO;
1219
1220 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1221 netxen_nic_io_write_128M(adapter, addr, data);
1222 } else { /* Window 0 */
1223 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1224 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1225 writel(data, addr);
1226 netxen_nic_pci_set_crbwindow_128M(adapter,
1227 NETXEN_WINDOW_ONE);
1228 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1229 }
1230
1231 if (mem_ptr)
1232 iounmap(mem_ptr);
1233
1234 return 0;
1235}
1236
1237static u32
1238netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1239{
1240 unsigned long flags;
1241 void __iomem *addr, *mem_ptr = NULL;
1242 u32 data;
1243
1244 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1245 if (!addr)
1246 return -EIO;
1247
1248 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1249 data = netxen_nic_io_read_128M(adapter, addr);
1250 } else { /* Window 0 */
1251 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1252 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1253 data = readl(addr);
1254 netxen_nic_pci_set_crbwindow_128M(adapter,
1255 NETXEN_WINDOW_ONE);
1256 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1257 }
1258
1259 if (mem_ptr)
1260 iounmap(mem_ptr);
1261
1262 return data;
1263}
1264
1265static int
1266netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1267{
1268 unsigned long flags;
1269 int rv;
1270 void __iomem *addr = NULL;
1271
1272 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1273
1274 if (rv == 0) {
1275 writel(data, addr);
1276 return 0;
1277 }
1278
1279 if (rv > 0) {
1280 /* indirect access */
1281 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1282 crb_win_lock(adapter);
1283 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1284 writel(data, addr);
1285 crb_win_unlock(adapter);
1286 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1287 return 0;
1288 }
1289
1290 dev_err(&adapter->pdev->dev,
1291 "%s: invalid offset: 0x%016lx\n", __func__, off);
1292 dump_stack();
1293 return -EIO;
1294}
1295
1296static u32
1297netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1298{
1299 unsigned long flags;
1300 int rv;
1301 u32 data;
1302 void __iomem *addr = NULL;
1303
1304 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1305
1306 if (rv == 0)
1307 return readl(addr);
1308
1309 if (rv > 0) {
1310 /* indirect access */
1311 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1312 crb_win_lock(adapter);
1313 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1314 data = readl(addr);
1315 crb_win_unlock(adapter);
1316 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1317 return data;
1318 }
1319
1320 dev_err(&adapter->pdev->dev,
1321 "%s: invalid offset: 0x%016lx\n", __func__, off);
1322 dump_stack();
1323 return -1;
1324}
1325
1326/* window 1 registers only */
1327static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1328 void __iomem *addr, u32 data)
1329{
1330 read_lock(&adapter->ahw.crb_lock);
1331 writel(data, addr);
1332 read_unlock(&adapter->ahw.crb_lock);
1333}
1334
1335static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1336 void __iomem *addr)
1337{
1338 u32 val;
1339
1340 read_lock(&adapter->ahw.crb_lock);
1341 val = readl(addr);
1342 read_unlock(&adapter->ahw.crb_lock);
1343
1344 return val;
1345}
1346
1347static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1348 void __iomem *addr, u32 data)
1349{
1350 writel(data, addr);
1351}
1352
1353static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1354 void __iomem *addr)
1355{
1356 return readl(addr);
1357}
1358
1359void __iomem *
1360netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1361{
1362 void __iomem *addr = NULL;
1363
1364 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1365 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1366 (offset > NETXEN_CRB_PCIX_HOST))
1367 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1368 else
1369 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1370 } else {
1371 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1372 offset, &addr));
1373 }
1374
1375 return addr;
1376}
1377
1378static int
1379netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1380 u64 addr, u32 *start)
1381{
1382 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1383 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1384 return 0;
1385 } else if (ADDR_IN_RANGE(addr,
1386 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1387 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1388 return 0;
1389 }
1390
1391 return -EIO;
1392}
1393
1394static int
1395netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1396 u64 addr, u32 *start)
1397{
1398 u32 window;
1399
1400 window = OCM_WIN(addr);
1401
1402 writel(window, adapter->ahw.ocm_win_crb);
1403 /* read back to flush */
1404 readl(adapter->ahw.ocm_win_crb);
1405
1406 adapter->ahw.ocm_win = window;
1407 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1408 return 0;
1409}
1410
1411static int
1412netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1413 u64 *data, int op)
1414{
1415 void __iomem *addr, *mem_ptr = NULL;
1416 resource_size_t mem_base;
1417 int ret;
1418 u32 start;
1419
1420 spin_lock(&adapter->ahw.mem_lock);
1421
1422 ret = adapter->pci_set_window(adapter, off, &start);
1423 if (ret != 0)
1424 goto unlock;
1425
1426 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1427 addr = adapter->ahw.pci_base0 + start;
1428 } else {
1429 addr = pci_base_offset(adapter, start);
1430 if (addr)
1431 goto noremap;
1432
1433 mem_base = pci_resource_start(adapter->pdev, 0) +
1434 (start & PAGE_MASK);
1435 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1436 if (mem_ptr == NULL) {
1437 ret = -EIO;
1438 goto unlock;
1439 }
1440
1441 addr = mem_ptr + (start & (PAGE_SIZE-1));
1442 }
1443noremap:
1444 if (op == 0) /* read */
1445 *data = readq(addr);
1446 else /* write */
1447 writeq(*data, addr);
1448
1449unlock:
1450 spin_unlock(&adapter->ahw.mem_lock);
1451
1452 if (mem_ptr)
1453 iounmap(mem_ptr);
1454 return ret;
1455}
1456
1457void
1458netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data)
1459{
1460 void __iomem *addr = adapter->ahw.pci_base0 +
1461 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1462
1463 spin_lock(&adapter->ahw.mem_lock);
1464 *data = readq(addr);
1465 spin_unlock(&adapter->ahw.mem_lock);
1466}
1467
1468void
1469netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data)
1470{
1471 void __iomem *addr = adapter->ahw.pci_base0 +
1472 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1473
1474 spin_lock(&adapter->ahw.mem_lock);
1475 writeq(data, addr);
1476 spin_unlock(&adapter->ahw.mem_lock);
1477}
1478
1479#define MAX_CTL_CHECK 1000
1480
1481static int
1482netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1483 u64 off, u64 data)
1484{
1485 int j, ret;
1486 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1487 void __iomem *mem_crb;
1488
1489 /* Only 64-bit aligned access */
1490 if (off & 7)
1491 return -EIO;
1492
1493 /* P2 has different SIU and MIU test agent base addr */
1494 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1495 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1496 mem_crb = pci_base_offset(adapter,
1497 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1498 addr_hi = SIU_TEST_AGT_ADDR_HI;
1499 data_lo = SIU_TEST_AGT_WRDATA_LO;
1500 data_hi = SIU_TEST_AGT_WRDATA_HI;
1501 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1502 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1503 goto correct;
1504 }
1505
1506 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1507 mem_crb = pci_base_offset(adapter,
1508 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1509 addr_hi = MIU_TEST_AGT_ADDR_HI;
1510 data_lo = MIU_TEST_AGT_WRDATA_LO;
1511 data_hi = MIU_TEST_AGT_WRDATA_HI;
1512 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1513 off_hi = 0;
1514 goto correct;
1515 }
1516
1517 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1518 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1519 if (adapter->ahw.pci_len0 != 0) {
1520 return netxen_nic_pci_mem_access_direct(adapter,
1521 off, &data, 1);
1522 }
1523 }
1524
1525 return -EIO;
1526
1527correct:
1528 spin_lock(&adapter->ahw.mem_lock);
1529 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1530
1531 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1532 writel(off_hi, (mem_crb + addr_hi));
1533 writel(data & 0xffffffff, (mem_crb + data_lo));
1534 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1535 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1536 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1537 (mem_crb + TEST_AGT_CTRL));
1538
1539 for (j = 0; j < MAX_CTL_CHECK; j++) {
1540 temp = readl((mem_crb + TEST_AGT_CTRL));
1541 if ((temp & TA_CTL_BUSY) == 0)
1542 break;
1543 }
1544
1545 if (j >= MAX_CTL_CHECK) {
1546 if (printk_ratelimit())
1547 dev_err(&adapter->pdev->dev,
1548 "failed to write through agent\n");
1549 ret = -EIO;
1550 } else
1551 ret = 0;
1552
1553 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1554 spin_unlock(&adapter->ahw.mem_lock);
1555 return ret;
1556}
1557
1558static int
1559netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1560 u64 off, u64 *data)
1561{
1562 int j, ret;
1563 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1564 u64 val;
1565 void __iomem *mem_crb;
1566
1567 /* Only 64-bit aligned access */
1568 if (off & 7)
1569 return -EIO;
1570
1571 /* P2 has different SIU and MIU test agent base addr */
1572 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1573 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1574 mem_crb = pci_base_offset(adapter,
1575 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1576 addr_hi = SIU_TEST_AGT_ADDR_HI;
1577 data_lo = SIU_TEST_AGT_RDDATA_LO;
1578 data_hi = SIU_TEST_AGT_RDDATA_HI;
1579 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1580 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1581 goto correct;
1582 }
1583
1584 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1585 mem_crb = pci_base_offset(adapter,
1586 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1587 addr_hi = MIU_TEST_AGT_ADDR_HI;
1588 data_lo = MIU_TEST_AGT_RDDATA_LO;
1589 data_hi = MIU_TEST_AGT_RDDATA_HI;
1590 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1591 off_hi = 0;
1592 goto correct;
1593 }
1594
1595 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1596 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1597 if (adapter->ahw.pci_len0 != 0) {
1598 return netxen_nic_pci_mem_access_direct(adapter,
1599 off, data, 0);
1600 }
1601 }
1602
1603 return -EIO;
1604
1605correct:
1606 spin_lock(&adapter->ahw.mem_lock);
1607 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1608
1609 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1610 writel(off_hi, (mem_crb + addr_hi));
1611 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1612 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1613
1614 for (j = 0; j < MAX_CTL_CHECK; j++) {
1615 temp = readl(mem_crb + TEST_AGT_CTRL);
1616 if ((temp & TA_CTL_BUSY) == 0)
1617 break;
1618 }
1619
1620 if (j >= MAX_CTL_CHECK) {
1621 if (printk_ratelimit())
1622 dev_err(&adapter->pdev->dev,
1623 "failed to read through agent\n");
1624 ret = -EIO;
1625 } else {
1626
1627 temp = readl(mem_crb + data_hi);
1628 val = ((u64)temp << 32);
1629 val |= readl(mem_crb + data_lo);
1630 *data = val;
1631 ret = 0;
1632 }
1633
1634 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1635 spin_unlock(&adapter->ahw.mem_lock);
1636
1637 return ret;
1638}
1639
1640static int
1641netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1642 u64 off, u64 data)
1643{
1644 int j, ret;
1645 u32 temp, off8;
1646 void __iomem *mem_crb;
1647
1648 /* Only 64-bit aligned access */
1649 if (off & 7)
1650 return -EIO;
1651
1652 /* P3 onward, test agent base for MIU and SIU is same */
1653 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1654 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1655 mem_crb = netxen_get_ioaddr(adapter,
1656 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1657 goto correct;
1658 }
1659
1660 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1661 mem_crb = netxen_get_ioaddr(adapter,
1662 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1663 goto correct;
1664 }
1665
1666 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1667 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1668
1669 return -EIO;
1670
1671correct:
1672 off8 = off & 0xfffffff8;
1673
1674 spin_lock(&adapter->ahw.mem_lock);
1675
1676 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1677 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1678
1679 writel(data & 0xffffffff,
1680 mem_crb + MIU_TEST_AGT_WRDATA_LO);
1681 writel((data >> 32) & 0xffffffff,
1682 mem_crb + MIU_TEST_AGT_WRDATA_HI);
1683
1684 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1685 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1686 (mem_crb + TEST_AGT_CTRL));
1687
1688 for (j = 0; j < MAX_CTL_CHECK; j++) {
1689 temp = readl(mem_crb + TEST_AGT_CTRL);
1690 if ((temp & TA_CTL_BUSY) == 0)
1691 break;
1692 }
1693
1694 if (j >= MAX_CTL_CHECK) {
1695 if (printk_ratelimit())
1696 dev_err(&adapter->pdev->dev,
1697 "failed to write through agent\n");
1698 ret = -EIO;
1699 } else
1700 ret = 0;
1701
1702 spin_unlock(&adapter->ahw.mem_lock);
1703
1704 return ret;
1705}
1706
1707static int
1708netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1709 u64 off, u64 *data)
1710{
1711 int j, ret;
1712 u32 temp, off8;
1713 u64 val;
1714 void __iomem *mem_crb;
1715
1716 /* Only 64-bit aligned access */
1717 if (off & 7)
1718 return -EIO;
1719
1720 /* P3 onward, test agent base for MIU and SIU is same */
1721 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1722 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1723 mem_crb = netxen_get_ioaddr(adapter,
1724 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1725 goto correct;
1726 }
1727
1728 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1729 mem_crb = netxen_get_ioaddr(adapter,
1730 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1731 goto correct;
1732 }
1733
1734 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1735 return netxen_nic_pci_mem_access_direct(adapter,
1736 off, data, 0);
1737 }
1738
1739 return -EIO;
1740
1741correct:
1742 off8 = off & 0xfffffff8;
1743
1744 spin_lock(&adapter->ahw.mem_lock);
1745
1746 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1747 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1748 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1749 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1750
1751 for (j = 0; j < MAX_CTL_CHECK; j++) {
1752 temp = readl(mem_crb + TEST_AGT_CTRL);
1753 if ((temp & TA_CTL_BUSY) == 0)
1754 break;
1755 }
1756
1757 if (j >= MAX_CTL_CHECK) {
1758 if (printk_ratelimit())
1759 dev_err(&adapter->pdev->dev,
1760 "failed to read through agent\n");
1761 ret = -EIO;
1762 } else {
1763 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32;
1764 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
1765 *data = val;
1766 ret = 0;
1767 }
1768
1769 spin_unlock(&adapter->ahw.mem_lock);
1770
1771 return ret;
1772}
1773
1774void
1775netxen_setup_hwops(struct netxen_adapter *adapter)
1776{
1777 adapter->init_port = netxen_niu_xg_init_port;
1778 adapter->stop_port = netxen_niu_disable_xg_port;
1779
1780 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1781 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1782 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1783 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1784 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1785 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1786 adapter->io_read = netxen_nic_io_read_128M,
1787 adapter->io_write = netxen_nic_io_write_128M,
1788
1789 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1790 adapter->set_multi = netxen_p2_nic_set_multi;
1791 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1792 adapter->set_promisc = netxen_p2_nic_set_promisc;
1793
1794 } else {
1795 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1796 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1797 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1798 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1799 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1800 adapter->io_read = netxen_nic_io_read_2M,
1801 adapter->io_write = netxen_nic_io_write_2M,
1802
1803 adapter->set_mtu = nx_fw_cmd_set_mtu;
1804 adapter->set_promisc = netxen_p3_nic_set_promisc;
1805 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1806 adapter->set_multi = netxen_p3_nic_set_multi;
1807
1808 adapter->phy_read = nx_fw_cmd_query_phy;
1809 adapter->phy_write = nx_fw_cmd_set_phy;
1810 }
1811}
1812
1813int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1814{
1815 int offset, board_type, magic;
1816 struct pci_dev *pdev = adapter->pdev;
1817
1818 offset = NX_FW_MAGIC_OFFSET;
1819 if (netxen_rom_fast_read(adapter, offset, &magic))
1820 return -EIO;
1821
1822 if (magic != NETXEN_BDINFO_MAGIC) {
1823 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1824 magic);
1825 return -EIO;
1826 }
1827
1828 offset = NX_BRDTYPE_OFFSET;
1829 if (netxen_rom_fast_read(adapter, offset, &board_type))
1830 return -EIO;
1831
1832 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1833 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1834 if ((gpio & 0x8000) == 0)
1835 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1836 }
1837
1838 adapter->ahw.board_type = board_type;
1839
1840 switch (board_type) {
1841 case NETXEN_BRDTYPE_P2_SB35_4G:
1842 adapter->ahw.port_type = NETXEN_NIC_GBE;
1843 break;
1844 case NETXEN_BRDTYPE_P2_SB31_10G:
1845 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1846 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1847 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1848 case NETXEN_BRDTYPE_P3_HMEZ:
1849 case NETXEN_BRDTYPE_P3_XG_LOM:
1850 case NETXEN_BRDTYPE_P3_10G_CX4:
1851 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1852 case NETXEN_BRDTYPE_P3_IMEZ:
1853 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1854 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1855 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1856 case NETXEN_BRDTYPE_P3_10G_XFP:
1857 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1858 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1859 break;
1860 case NETXEN_BRDTYPE_P1_BD:
1861 case NETXEN_BRDTYPE_P1_SB:
1862 case NETXEN_BRDTYPE_P1_SMAX:
1863 case NETXEN_BRDTYPE_P1_SOCK:
1864 case NETXEN_BRDTYPE_P3_REF_QG:
1865 case NETXEN_BRDTYPE_P3_4_GB:
1866 case NETXEN_BRDTYPE_P3_4_GB_MM:
1867 adapter->ahw.port_type = NETXEN_NIC_GBE;
1868 break;
1869 case NETXEN_BRDTYPE_P3_10G_TP:
1870 adapter->ahw.port_type = (adapter->portnum < 2) ?
1871 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1872 break;
1873 default:
1874 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1875 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1876 break;
1877 }
1878
1879 return 0;
1880}
1881
1882/* NIU access sections */
1883static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1884{
1885 new_mtu += MTU_FUDGE_FACTOR;
1886 if (adapter->physical_port == 0)
1887 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1888 else
1889 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1890 return 0;
1891}
1892
1893void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1894{
1895 __u32 status;
1896 __u32 autoneg;
1897 __u32 port_mode;
1898
1899 if (!netif_carrier_ok(adapter->netdev)) {
1900 adapter->link_speed = 0;
1901 adapter->link_duplex = -1;
1902 adapter->link_autoneg = AUTONEG_ENABLE;
1903 return;
1904 }
1905
1906 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1907 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1908 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1909 adapter->link_speed = SPEED_1000;
1910 adapter->link_duplex = DUPLEX_FULL;
1911 adapter->link_autoneg = AUTONEG_DISABLE;
1912 return;
1913 }
1914
1915 if (adapter->phy_read &&
1916 adapter->phy_read(adapter,
1917 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1918 &status) == 0) {
1919 if (netxen_get_phy_link(status)) {
1920 switch (netxen_get_phy_speed(status)) {
1921 case 0:
1922 adapter->link_speed = SPEED_10;
1923 break;
1924 case 1:
1925 adapter->link_speed = SPEED_100;
1926 break;
1927 case 2:
1928 adapter->link_speed = SPEED_1000;
1929 break;
1930 default:
1931 adapter->link_speed = 0;
1932 break;
1933 }
1934 switch (netxen_get_phy_duplex(status)) {
1935 case 0:
1936 adapter->link_duplex = DUPLEX_HALF;
1937 break;
1938 case 1:
1939 adapter->link_duplex = DUPLEX_FULL;
1940 break;
1941 default:
1942 adapter->link_duplex = -1;
1943 break;
1944 }
1945 if (adapter->phy_read &&
1946 adapter->phy_read(adapter,
1947 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1948 &autoneg) != 0)
1949 adapter->link_autoneg = autoneg;
1950 } else
1951 goto link_down;
1952 } else {
1953 link_down:
1954 adapter->link_speed = 0;
1955 adapter->link_duplex = -1;
1956 }
1957 }
1958}
1959
1960int
1961netxen_nic_wol_supported(struct netxen_adapter *adapter)
1962{
1963 u32 wol_cfg;
1964
1965 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1966 return 0;
1967
1968 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1969 if (wol_cfg & (1UL << adapter->portnum)) {
1970 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1971 if (wol_cfg & (1 << adapter->portnum))
1972 return 1;
1973 }
1974
1975 return 0;
1976}
diff --git a/drivers/net/netxen/netxen_nic_hw.h b/drivers/net/netxen/netxen_nic_hw.h
new file mode 100644
index 00000000000..e2c5b6f2df0
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_hw.h
@@ -0,0 +1,287 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#ifndef __NETXEN_NIC_HW_H_
27#define __NETXEN_NIC_HW_H_
28
29/* Hardware memory size of 128 meg */
30#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
31
32struct netxen_adapter;
33
34#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
35
36void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
37
38/* Nibble or Byte mode for phy interface (GbE mode only) */
39
40#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
41
42/*
43 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
44 *
45 * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
46 * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
47 * Bit 2 : enable_rx => 1:enable frame recv, 0:disable
48 * Bit 3 : rx_synced => R/O: recv enable synched to recv stream
49 * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
50 * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
51 * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
52 * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
53 * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
54 * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
55 * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
56 * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
57 */
58
59#define netxen_gb_tx_flowctl(config_word) \
60 ((config_word) |= 1 << 4)
61#define netxen_gb_rx_flowctl(config_word) \
62 ((config_word) |= 1 << 5)
63#define netxen_gb_tx_reset_pb(config_word) \
64 ((config_word) |= 1 << 16)
65#define netxen_gb_rx_reset_pb(config_word) \
66 ((config_word) |= 1 << 17)
67#define netxen_gb_tx_reset_mac(config_word) \
68 ((config_word) |= 1 << 18)
69#define netxen_gb_rx_reset_mac(config_word) \
70 ((config_word) |= 1 << 19)
71
72#define netxen_gb_unset_tx_flowctl(config_word) \
73 ((config_word) &= ~(1 << 4))
74#define netxen_gb_unset_rx_flowctl(config_word) \
75 ((config_word) &= ~(1 << 5))
76
77#define netxen_gb_get_tx_synced(config_word) \
78 _netxen_crb_get_bit((config_word), 1)
79#define netxen_gb_get_rx_synced(config_word) \
80 _netxen_crb_get_bit((config_word), 3)
81#define netxen_gb_get_tx_flowctl(config_word) \
82 _netxen_crb_get_bit((config_word), 4)
83#define netxen_gb_get_rx_flowctl(config_word) \
84 _netxen_crb_get_bit((config_word), 5)
85#define netxen_gb_get_soft_reset(config_word) \
86 _netxen_crb_get_bit((config_word), 31)
87
88#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
89
90#define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
91 ((config_word) |= ((val) & 0x07))
92#define netxen_gb_mii_mgmt_reset(config_word) \
93 ((config_word) |= 1 << 31)
94#define netxen_gb_mii_mgmt_unset(config_word) \
95 ((config_word) &= ~(1 << 31))
96
97/*
98 * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
99 * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
100 * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
101 */
102
103#define netxen_gb_mii_mgmt_set_read_cycle(config_word) \
104 ((config_word) |= 1 << 0)
105#define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
106 ((config_word) |= ((val) & 0x1F))
107#define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
108 ((config_word) |= (((val) & 0x1F) << 8))
109
110/*
111 * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
112 * Read-only register.
113 * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
114 * Bit 1 : scanning => 1:scan operation in progress, 0:idle
115 * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
116 */
117#define netxen_get_gb_mii_mgmt_busy(config_word) \
118 _netxen_crb_get_bit(config_word, 0)
119#define netxen_get_gb_mii_mgmt_scanning(config_word) \
120 _netxen_crb_get_bit(config_word, 1)
121#define netxen_get_gb_mii_mgmt_notvalid(config_word) \
122 _netxen_crb_get_bit(config_word, 2)
123/*
124 * NIU XG Pause Ctl Register
125 *
126 * Bit 0 : xg0_mask => 1:disable tx pause frames
127 * Bit 1 : xg0_request => 1:request single pause frame
128 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
129 * Bit 3 : xg1_mask => 1:disable tx pause frames
130 * Bit 4 : xg1_request => 1:request single pause frame
131 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
132 */
133
134#define netxen_xg_set_xg0_mask(config_word) \
135 ((config_word) |= 1 << 0)
136#define netxen_xg_set_xg1_mask(config_word) \
137 ((config_word) |= 1 << 3)
138
139#define netxen_xg_get_xg0_mask(config_word) \
140 _netxen_crb_get_bit((config_word), 0)
141#define netxen_xg_get_xg1_mask(config_word) \
142 _netxen_crb_get_bit((config_word), 3)
143
144#define netxen_xg_unset_xg0_mask(config_word) \
145 ((config_word) &= ~(1 << 0))
146#define netxen_xg_unset_xg1_mask(config_word) \
147 ((config_word) &= ~(1 << 3))
148
149/*
150 * NIU XG Pause Ctl Register
151 *
152 * Bit 0 : xg0_mask => 1:disable tx pause frames
153 * Bit 1 : xg0_request => 1:request single pause frame
154 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
155 * Bit 3 : xg1_mask => 1:disable tx pause frames
156 * Bit 4 : xg1_request => 1:request single pause frame
157 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
158 */
159#define netxen_gb_set_gb0_mask(config_word) \
160 ((config_word) |= 1 << 0)
161#define netxen_gb_set_gb1_mask(config_word) \
162 ((config_word) |= 1 << 2)
163#define netxen_gb_set_gb2_mask(config_word) \
164 ((config_word) |= 1 << 4)
165#define netxen_gb_set_gb3_mask(config_word) \
166 ((config_word) |= 1 << 6)
167
168#define netxen_gb_get_gb0_mask(config_word) \
169 _netxen_crb_get_bit((config_word), 0)
170#define netxen_gb_get_gb1_mask(config_word) \
171 _netxen_crb_get_bit((config_word), 2)
172#define netxen_gb_get_gb2_mask(config_word) \
173 _netxen_crb_get_bit((config_word), 4)
174#define netxen_gb_get_gb3_mask(config_word) \
175 _netxen_crb_get_bit((config_word), 6)
176
177#define netxen_gb_unset_gb0_mask(config_word) \
178 ((config_word) &= ~(1 << 0))
179#define netxen_gb_unset_gb1_mask(config_word) \
180 ((config_word) &= ~(1 << 2))
181#define netxen_gb_unset_gb2_mask(config_word) \
182 ((config_word) &= ~(1 << 4))
183#define netxen_gb_unset_gb3_mask(config_word) \
184 ((config_word) &= ~(1 << 6))
185
186
187/*
188 * PHY-Specific MII control/status registers.
189 */
190#define NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL 0
191#define NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS 1
192#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 2
193#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 3
194#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG 4
195#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART 5
196#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE 6
197#define NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT 7
198#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE 8
199#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL 9
200#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS 10
201#define NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS 15
202#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL 16
203#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17
204#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE 18
205#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS 19
206#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE 20
207#define NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT 21
208#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL 24
209#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE 25
210#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET 26
211#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE 27
212
213/*
214 * PHY-Specific Status Register (reg 17).
215 *
216 * Bit 0 : jabber => 1:jabber detected, 0:not
217 * Bit 1 : polarity => 1:polarity reversed, 0:normal
218 * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
219 * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
220 * Bit 4 : energydetect => 1:sleep, 0:active
221 * Bit 5 : downshift => 1:downshift, 0:no downshift
222 * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
223 * Bits 7-9 : cablelen => not valid in 10Mb/s mode
224 * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
225 * Bit 10 : link => 1:link up, 0:link down
226 * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
227 * Bit 12 : pagercvd => 1:page received, 0:page not received
228 * Bit 13 : duplex => 1:full duplex, 0:half duplex
229 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
230 */
231
232#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
233
234#define netxen_set_phy_speed(config_word, val) \
235 ((config_word) |= ((val & 0x03) << 14))
236#define netxen_set_phy_duplex(config_word) \
237 ((config_word) |= 1 << 13)
238#define netxen_clear_phy_duplex(config_word) \
239 ((config_word) &= ~(1 << 13))
240
241#define netxen_get_phy_link(config_word) \
242 _netxen_crb_get_bit(config_word, 10)
243#define netxen_get_phy_duplex(config_word) \
244 _netxen_crb_get_bit(config_word, 13)
245
246/*
247 * NIU Mode Register.
248 * Bit 0 : enable FibreChannel
249 * Bit 1 : enable 10/100/1000 Ethernet
250 * Bit 2 : enable 10Gb Ethernet
251 */
252
253#define netxen_get_niu_enable_ge(config_word) \
254 _netxen_crb_get_bit(config_word, 1)
255
256#define NETXEN_NIU_NON_PROMISC_MODE 0
257#define NETXEN_NIU_PROMISC_MODE 1
258#define NETXEN_NIU_ALLMULTI_MODE 2
259
260/*
261 * NIU XG MAC Config Register
262 *
263 * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
264 * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
265 * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
266 * Bit 27: xaui_framer_reset
267 * Bit 28: xaui_rx_reset
268 * Bit 29: xaui_tx_reset
269 * Bit 30: xg_ingress_afifo_reset
270 * Bit 31: xg_egress_afifo_reset
271 */
272
273#define netxen_xg_soft_reset(config_word) \
274 ((config_word) |= 1 << 4)
275
276typedef struct {
277 unsigned valid;
278 unsigned start_128M;
279 unsigned end_128M;
280 unsigned start_2M;
281} crb_128M_2M_sub_block_map_t;
282
283typedef struct {
284 crb_128M_2M_sub_block_map_t sub_block[16];
285} crb_128M_2M_block_map_t;
286
287#endif /* __NETXEN_NIC_HW_H_ */
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
new file mode 100644
index 00000000000..e8993a76a08
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -0,0 +1,1945 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#include <linux/netdevice.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include "netxen_nic.h"
30#include "netxen_nic_hw.h"
31
32struct crb_addr_pair {
33 u32 addr;
34 u32 data;
35};
36
37#define NETXEN_MAX_CRB_XFORM 60
38static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
39#define NETXEN_ADDR_ERROR (0xffffffff)
40
41#define crb_addr_transform(name) \
42 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
43 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
44
45#define NETXEN_NIC_XDMA_RESET 0x8000ff
46
47static void
48netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
49 struct nx_host_rds_ring *rds_ring);
50static int netxen_p3_has_mn(struct netxen_adapter *adapter);
51
52static void crb_addr_transform_setup(void)
53{
54 crb_addr_transform(XDMA);
55 crb_addr_transform(TIMR);
56 crb_addr_transform(SRE);
57 crb_addr_transform(SQN3);
58 crb_addr_transform(SQN2);
59 crb_addr_transform(SQN1);
60 crb_addr_transform(SQN0);
61 crb_addr_transform(SQS3);
62 crb_addr_transform(SQS2);
63 crb_addr_transform(SQS1);
64 crb_addr_transform(SQS0);
65 crb_addr_transform(RPMX7);
66 crb_addr_transform(RPMX6);
67 crb_addr_transform(RPMX5);
68 crb_addr_transform(RPMX4);
69 crb_addr_transform(RPMX3);
70 crb_addr_transform(RPMX2);
71 crb_addr_transform(RPMX1);
72 crb_addr_transform(RPMX0);
73 crb_addr_transform(ROMUSB);
74 crb_addr_transform(SN);
75 crb_addr_transform(QMN);
76 crb_addr_transform(QMS);
77 crb_addr_transform(PGNI);
78 crb_addr_transform(PGND);
79 crb_addr_transform(PGN3);
80 crb_addr_transform(PGN2);
81 crb_addr_transform(PGN1);
82 crb_addr_transform(PGN0);
83 crb_addr_transform(PGSI);
84 crb_addr_transform(PGSD);
85 crb_addr_transform(PGS3);
86 crb_addr_transform(PGS2);
87 crb_addr_transform(PGS1);
88 crb_addr_transform(PGS0);
89 crb_addr_transform(PS);
90 crb_addr_transform(PH);
91 crb_addr_transform(NIU);
92 crb_addr_transform(I2Q);
93 crb_addr_transform(EG);
94 crb_addr_transform(MN);
95 crb_addr_transform(MS);
96 crb_addr_transform(CAS2);
97 crb_addr_transform(CAS1);
98 crb_addr_transform(CAS0);
99 crb_addr_transform(CAM);
100 crb_addr_transform(C2C1);
101 crb_addr_transform(C2C0);
102 crb_addr_transform(SMB);
103 crb_addr_transform(OCM0);
104 crb_addr_transform(I2C0);
105}
106
107void netxen_release_rx_buffers(struct netxen_adapter *adapter)
108{
109 struct netxen_recv_context *recv_ctx;
110 struct nx_host_rds_ring *rds_ring;
111 struct netxen_rx_buffer *rx_buf;
112 int i, ring;
113
114 recv_ctx = &adapter->recv_ctx;
115 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
116 rds_ring = &recv_ctx->rds_rings[ring];
117 for (i = 0; i < rds_ring->num_desc; ++i) {
118 rx_buf = &(rds_ring->rx_buf_arr[i]);
119 if (rx_buf->state == NETXEN_BUFFER_FREE)
120 continue;
121 pci_unmap_single(adapter->pdev,
122 rx_buf->dma,
123 rds_ring->dma_size,
124 PCI_DMA_FROMDEVICE);
125 if (rx_buf->skb != NULL)
126 dev_kfree_skb_any(rx_buf->skb);
127 }
128 }
129}
130
131void netxen_release_tx_buffers(struct netxen_adapter *adapter)
132{
133 struct netxen_cmd_buffer *cmd_buf;
134 struct netxen_skb_frag *buffrag;
135 int i, j;
136 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
137
138 cmd_buf = tx_ring->cmd_buf_arr;
139 for (i = 0; i < tx_ring->num_desc; i++) {
140 buffrag = cmd_buf->frag_array;
141 if (buffrag->dma) {
142 pci_unmap_single(adapter->pdev, buffrag->dma,
143 buffrag->length, PCI_DMA_TODEVICE);
144 buffrag->dma = 0ULL;
145 }
146 for (j = 0; j < cmd_buf->frag_count; j++) {
147 buffrag++;
148 if (buffrag->dma) {
149 pci_unmap_page(adapter->pdev, buffrag->dma,
150 buffrag->length,
151 PCI_DMA_TODEVICE);
152 buffrag->dma = 0ULL;
153 }
154 }
155 if (cmd_buf->skb) {
156 dev_kfree_skb_any(cmd_buf->skb);
157 cmd_buf->skb = NULL;
158 }
159 cmd_buf++;
160 }
161}
162
163void netxen_free_sw_resources(struct netxen_adapter *adapter)
164{
165 struct netxen_recv_context *recv_ctx;
166 struct nx_host_rds_ring *rds_ring;
167 struct nx_host_tx_ring *tx_ring;
168 int ring;
169
170 recv_ctx = &adapter->recv_ctx;
171
172 if (recv_ctx->rds_rings == NULL)
173 goto skip_rds;
174
175 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
176 rds_ring = &recv_ctx->rds_rings[ring];
177 vfree(rds_ring->rx_buf_arr);
178 rds_ring->rx_buf_arr = NULL;
179 }
180 kfree(recv_ctx->rds_rings);
181
182skip_rds:
183 if (adapter->tx_ring == NULL)
184 return;
185
186 tx_ring = adapter->tx_ring;
187 vfree(tx_ring->cmd_buf_arr);
188 kfree(tx_ring);
189 adapter->tx_ring = NULL;
190}
191
192int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
193{
194 struct netxen_recv_context *recv_ctx;
195 struct nx_host_rds_ring *rds_ring;
196 struct nx_host_sds_ring *sds_ring;
197 struct nx_host_tx_ring *tx_ring;
198 struct netxen_rx_buffer *rx_buf;
199 int ring, i, size;
200
201 struct netxen_cmd_buffer *cmd_buf_arr;
202 struct net_device *netdev = adapter->netdev;
203 struct pci_dev *pdev = adapter->pdev;
204
205 size = sizeof(struct nx_host_tx_ring);
206 tx_ring = kzalloc(size, GFP_KERNEL);
207 if (tx_ring == NULL) {
208 dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
209 netdev->name);
210 return -ENOMEM;
211 }
212 adapter->tx_ring = tx_ring;
213
214 tx_ring->num_desc = adapter->num_txd;
215 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
216
217 cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
218 if (cmd_buf_arr == NULL) {
219 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
220 netdev->name);
221 goto err_out;
222 }
223 tx_ring->cmd_buf_arr = cmd_buf_arr;
224
225 recv_ctx = &adapter->recv_ctx;
226
227 size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
228 rds_ring = kzalloc(size, GFP_KERNEL);
229 if (rds_ring == NULL) {
230 dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
231 netdev->name);
232 goto err_out;
233 }
234 recv_ctx->rds_rings = rds_ring;
235
236 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
237 rds_ring = &recv_ctx->rds_rings[ring];
238 switch (ring) {
239 case RCV_RING_NORMAL:
240 rds_ring->num_desc = adapter->num_rxd;
241 if (adapter->ahw.cut_through) {
242 rds_ring->dma_size =
243 NX_CT_DEFAULT_RX_BUF_LEN;
244 rds_ring->skb_size =
245 NX_CT_DEFAULT_RX_BUF_LEN;
246 } else {
247 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
248 rds_ring->dma_size =
249 NX_P3_RX_BUF_MAX_LEN;
250 else
251 rds_ring->dma_size =
252 NX_P2_RX_BUF_MAX_LEN;
253 rds_ring->skb_size =
254 rds_ring->dma_size + NET_IP_ALIGN;
255 }
256 break;
257
258 case RCV_RING_JUMBO:
259 rds_ring->num_desc = adapter->num_jumbo_rxd;
260 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
261 rds_ring->dma_size =
262 NX_P3_RX_JUMBO_BUF_MAX_LEN;
263 else
264 rds_ring->dma_size =
265 NX_P2_RX_JUMBO_BUF_MAX_LEN;
266
267 if (adapter->capabilities & NX_CAP0_HW_LRO)
268 rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
269
270 rds_ring->skb_size =
271 rds_ring->dma_size + NET_IP_ALIGN;
272 break;
273
274 case RCV_RING_LRO:
275 rds_ring->num_desc = adapter->num_lro_rxd;
276 rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
277 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
278 break;
279
280 }
281 rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
282 if (rds_ring->rx_buf_arr == NULL) {
283 printk(KERN_ERR "%s: Failed to allocate "
284 "rx buffer ring %d\n",
285 netdev->name, ring);
286 /* free whatever was already allocated */
287 goto err_out;
288 }
289 INIT_LIST_HEAD(&rds_ring->free_list);
290 /*
291 * Now go through all of them, set reference handles
292 * and put them in the queues.
293 */
294 rx_buf = rds_ring->rx_buf_arr;
295 for (i = 0; i < rds_ring->num_desc; i++) {
296 list_add_tail(&rx_buf->list,
297 &rds_ring->free_list);
298 rx_buf->ref_handle = i;
299 rx_buf->state = NETXEN_BUFFER_FREE;
300 rx_buf++;
301 }
302 spin_lock_init(&rds_ring->lock);
303 }
304
305 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
306 sds_ring = &recv_ctx->sds_rings[ring];
307 sds_ring->irq = adapter->msix_entries[ring].vector;
308 sds_ring->adapter = adapter;
309 sds_ring->num_desc = adapter->num_rxd;
310
311 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
312 INIT_LIST_HEAD(&sds_ring->free_list[i]);
313 }
314
315 return 0;
316
317err_out:
318 netxen_free_sw_resources(adapter);
319 return -ENOMEM;
320}
321
322/*
323 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
324 * address to external PCI CRB address.
325 */
326static u32 netxen_decode_crb_addr(u32 addr)
327{
328 int i;
329 u32 base_addr, offset, pci_base;
330
331 crb_addr_transform_setup();
332
333 pci_base = NETXEN_ADDR_ERROR;
334 base_addr = addr & 0xfff00000;
335 offset = addr & 0x000fffff;
336
337 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
338 if (crb_addr_xform[i] == base_addr) {
339 pci_base = i << 20;
340 break;
341 }
342 }
343 if (pci_base == NETXEN_ADDR_ERROR)
344 return pci_base;
345 else
346 return pci_base + offset;
347}
348
349#define NETXEN_MAX_ROM_WAIT_USEC 100
350
351static int netxen_wait_rom_done(struct netxen_adapter *adapter)
352{
353 long timeout = 0;
354 long done = 0;
355
356 cond_resched();
357
358 while (done == 0) {
359 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
360 done &= 2;
361 if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
362 dev_err(&adapter->pdev->dev,
363 "Timeout reached waiting for rom done");
364 return -EIO;
365 }
366 udelay(1);
367 }
368 return 0;
369}
370
371static int do_rom_fast_read(struct netxen_adapter *adapter,
372 int addr, int *valp)
373{
374 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
375 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
376 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
377 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
378 if (netxen_wait_rom_done(adapter)) {
379 printk("Error waiting for rom done\n");
380 return -EIO;
381 }
382 /* reset abyte_cnt and dummy_byte_cnt */
383 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
384 udelay(10);
385 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
386
387 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
388 return 0;
389}
390
391static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
392 u8 *bytes, size_t size)
393{
394 int addridx;
395 int ret = 0;
396
397 for (addridx = addr; addridx < (addr + size); addridx += 4) {
398 int v;
399 ret = do_rom_fast_read(adapter, addridx, &v);
400 if (ret != 0)
401 break;
402 *(__le32 *)bytes = cpu_to_le32(v);
403 bytes += 4;
404 }
405
406 return ret;
407}
408
409int
410netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
411 u8 *bytes, size_t size)
412{
413 int ret;
414
415 ret = netxen_rom_lock(adapter);
416 if (ret < 0)
417 return ret;
418
419 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
420
421 netxen_rom_unlock(adapter);
422 return ret;
423}
424
425int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
426{
427 int ret;
428
429 if (netxen_rom_lock(adapter) != 0)
430 return -EIO;
431
432 ret = do_rom_fast_read(adapter, addr, valp);
433 netxen_rom_unlock(adapter);
434 return ret;
435}
436
437#define NETXEN_BOARDTYPE 0x4008
438#define NETXEN_BOARDNUM 0x400c
439#define NETXEN_CHIPNUM 0x4010
440
441int netxen_pinit_from_rom(struct netxen_adapter *adapter)
442{
443 int addr, val;
444 int i, n, init_delay = 0;
445 struct crb_addr_pair *buf;
446 unsigned offset;
447 u32 off;
448
449 /* resetall */
450 netxen_rom_lock(adapter);
451 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
452 netxen_rom_unlock(adapter);
453
454 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
455 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
456 (n != 0xcafecafe) ||
457 netxen_rom_fast_read(adapter, 4, &n) != 0) {
458 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
459 "n: %08x\n", netxen_nic_driver_name, n);
460 return -EIO;
461 }
462 offset = n & 0xffffU;
463 n = (n >> 16) & 0xffffU;
464 } else {
465 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
466 !(n & 0x80000000)) {
467 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
468 "n: %08x\n", netxen_nic_driver_name, n);
469 return -EIO;
470 }
471 offset = 1;
472 n &= ~0x80000000;
473 }
474
475 if (n >= 1024) {
476 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
477 " initialized.\n", __func__, n);
478 return -EIO;
479 }
480
481 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
482 if (buf == NULL) {
483 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
484 netxen_nic_driver_name);
485 return -ENOMEM;
486 }
487
488 for (i = 0; i < n; i++) {
489 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
490 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
491 kfree(buf);
492 return -EIO;
493 }
494
495 buf[i].addr = addr;
496 buf[i].data = val;
497
498 }
499
500 for (i = 0; i < n; i++) {
501
502 off = netxen_decode_crb_addr(buf[i].addr);
503 if (off == NETXEN_ADDR_ERROR) {
504 printk(KERN_ERR"CRB init value out of range %x\n",
505 buf[i].addr);
506 continue;
507 }
508 off += NETXEN_PCI_CRBSPACE;
509
510 if (off & 1)
511 continue;
512
513 /* skipping cold reboot MAGIC */
514 if (off == NETXEN_CAM_RAM(0x1fc))
515 continue;
516
517 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
518 if (off == (NETXEN_CRB_I2C0 + 0x1c))
519 continue;
520 /* do not reset PCI */
521 if (off == (ROMUSB_GLB + 0xbc))
522 continue;
523 if (off == (ROMUSB_GLB + 0xa8))
524 continue;
525 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
526 continue;
527 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
528 continue;
529 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
530 continue;
531 if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
532 continue;
533 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
534 !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
535 buf[i].data = 0x1020;
536 /* skip the function enable register */
537 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
538 continue;
539 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
540 continue;
541 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
542 continue;
543 }
544
545 init_delay = 1;
546 /* After writing this register, HW needs time for CRB */
547 /* to quiet down (else crb_window returns 0xffffffff) */
548 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
549 init_delay = 1000;
550 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
551 /* hold xdma in reset also */
552 buf[i].data = NETXEN_NIC_XDMA_RESET;
553 buf[i].data = 0x8000ff;
554 }
555 }
556
557 NXWR32(adapter, off, buf[i].data);
558
559 msleep(init_delay);
560 }
561 kfree(buf);
562
563 /* disable_peg_cache_all */
564
565 /* unreset_net_cache */
566 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
567 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
568 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
569 }
570
571 /* p2dn replyCount */
572 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
573 /* disable_peg_cache 0 */
574 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
575 /* disable_peg_cache 1 */
576 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
577
578 /* peg_clr_all */
579
580 /* peg_clr 0 */
581 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
582 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
583 /* peg_clr 1 */
584 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
585 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
586 /* peg_clr 2 */
587 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
588 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
589 /* peg_clr 3 */
590 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
591 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
592 return 0;
593}
594
595static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
596{
597 uint32_t i;
598 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
599 __le32 entries = cpu_to_le32(directory->num_entries);
600
601 for (i = 0; i < entries; i++) {
602
603 __le32 offs = cpu_to_le32(directory->findex) +
604 (i * cpu_to_le32(directory->entry_size));
605 __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
606
607 if (tab_type == section)
608 return (struct uni_table_desc *) &unirom[offs];
609 }
610
611 return NULL;
612}
613
614#define QLCNIC_FILEHEADER_SIZE (14 * 4)
615
616static int
617netxen_nic_validate_header(struct netxen_adapter *adapter)
618 {
619 const u8 *unirom = adapter->fw->data;
620 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
621 u32 fw_file_size = adapter->fw->size;
622 u32 tab_size;
623 __le32 entries;
624 __le32 entry_size;
625
626 if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
627 return -EINVAL;
628
629 entries = cpu_to_le32(directory->num_entries);
630 entry_size = cpu_to_le32(directory->entry_size);
631 tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
632
633 if (fw_file_size < tab_size)
634 return -EINVAL;
635
636 return 0;
637}
638
639static int
640netxen_nic_validate_bootld(struct netxen_adapter *adapter)
641{
642 struct uni_table_desc *tab_desc;
643 struct uni_data_desc *descr;
644 const u8 *unirom = adapter->fw->data;
645 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
646 NX_UNI_BOOTLD_IDX_OFF));
647 u32 offs;
648 u32 tab_size;
649 u32 data_size;
650
651 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
652
653 if (!tab_desc)
654 return -EINVAL;
655
656 tab_size = cpu_to_le32(tab_desc->findex) +
657 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
658
659 if (adapter->fw->size < tab_size)
660 return -EINVAL;
661
662 offs = cpu_to_le32(tab_desc->findex) +
663 (cpu_to_le32(tab_desc->entry_size) * (idx));
664 descr = (struct uni_data_desc *)&unirom[offs];
665
666 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
667
668 if (adapter->fw->size < data_size)
669 return -EINVAL;
670
671 return 0;
672}
673
674static int
675netxen_nic_validate_fw(struct netxen_adapter *adapter)
676{
677 struct uni_table_desc *tab_desc;
678 struct uni_data_desc *descr;
679 const u8 *unirom = adapter->fw->data;
680 __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
681 NX_UNI_FIRMWARE_IDX_OFF));
682 u32 offs;
683 u32 tab_size;
684 u32 data_size;
685
686 tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
687
688 if (!tab_desc)
689 return -EINVAL;
690
691 tab_size = cpu_to_le32(tab_desc->findex) +
692 (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
693
694 if (adapter->fw->size < tab_size)
695 return -EINVAL;
696
697 offs = cpu_to_le32(tab_desc->findex) +
698 (cpu_to_le32(tab_desc->entry_size) * (idx));
699 descr = (struct uni_data_desc *)&unirom[offs];
700 data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
701
702 if (adapter->fw->size < data_size)
703 return -EINVAL;
704
705 return 0;
706}
707
708
709static int
710netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
711{
712 struct uni_table_desc *ptab_descr;
713 const u8 *unirom = adapter->fw->data;
714 int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
715 1 : netxen_p3_has_mn(adapter);
716 __le32 entries;
717 __le32 entry_size;
718 u32 tab_size;
719 u32 i;
720
721 ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
722 if (ptab_descr == NULL)
723 return -EINVAL;
724
725 entries = cpu_to_le32(ptab_descr->num_entries);
726 entry_size = cpu_to_le32(ptab_descr->entry_size);
727 tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
728
729 if (adapter->fw->size < tab_size)
730 return -EINVAL;
731
732nomn:
733 for (i = 0; i < entries; i++) {
734
735 __le32 flags, file_chiprev, offs;
736 u8 chiprev = adapter->ahw.revision_id;
737 uint32_t flagbit;
738
739 offs = cpu_to_le32(ptab_descr->findex) +
740 (i * cpu_to_le32(ptab_descr->entry_size));
741 flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
742 file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
743 NX_UNI_CHIP_REV_OFF));
744
745 flagbit = mn_present ? 1 : 2;
746
747 if ((chiprev == file_chiprev) &&
748 ((1ULL << flagbit) & flags)) {
749 adapter->file_prd_off = offs;
750 return 0;
751 }
752 }
753
754 if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
755 mn_present = 0;
756 goto nomn;
757 }
758
759 return -EINVAL;
760}
761
762static int
763netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
764{
765 if (netxen_nic_validate_header(adapter)) {
766 dev_err(&adapter->pdev->dev,
767 "unified image: header validation failed\n");
768 return -EINVAL;
769 }
770
771 if (netxen_nic_validate_product_offs(adapter)) {
772 dev_err(&adapter->pdev->dev,
773 "unified image: product validation failed\n");
774 return -EINVAL;
775 }
776
777 if (netxen_nic_validate_bootld(adapter)) {
778 dev_err(&adapter->pdev->dev,
779 "unified image: bootld validation failed\n");
780 return -EINVAL;
781 }
782
783 if (netxen_nic_validate_fw(adapter)) {
784 dev_err(&adapter->pdev->dev,
785 "unified image: firmware validation failed\n");
786 return -EINVAL;
787 }
788
789 return 0;
790}
791
792static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
793 u32 section, u32 idx_offset)
794{
795 const u8 *unirom = adapter->fw->data;
796 int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
797 idx_offset));
798 struct uni_table_desc *tab_desc;
799 __le32 offs;
800
801 tab_desc = nx_get_table_desc(unirom, section);
802
803 if (tab_desc == NULL)
804 return NULL;
805
806 offs = cpu_to_le32(tab_desc->findex) +
807 (cpu_to_le32(tab_desc->entry_size) * idx);
808
809 return (struct uni_data_desc *)&unirom[offs];
810}
811
812static u8 *
813nx_get_bootld_offs(struct netxen_adapter *adapter)
814{
815 u32 offs = NETXEN_BOOTLD_START;
816
817 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
818 offs = cpu_to_le32((nx_get_data_desc(adapter,
819 NX_UNI_DIR_SECT_BOOTLD,
820 NX_UNI_BOOTLD_IDX_OFF))->findex);
821
822 return (u8 *)&adapter->fw->data[offs];
823}
824
825static u8 *
826nx_get_fw_offs(struct netxen_adapter *adapter)
827{
828 u32 offs = NETXEN_IMAGE_START;
829
830 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
831 offs = cpu_to_le32((nx_get_data_desc(adapter,
832 NX_UNI_DIR_SECT_FW,
833 NX_UNI_FIRMWARE_IDX_OFF))->findex);
834
835 return (u8 *)&adapter->fw->data[offs];
836}
837
838static __le32
839nx_get_fw_size(struct netxen_adapter *adapter)
840{
841 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
842 return cpu_to_le32((nx_get_data_desc(adapter,
843 NX_UNI_DIR_SECT_FW,
844 NX_UNI_FIRMWARE_IDX_OFF))->size);
845 else
846 return cpu_to_le32(
847 *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
848}
849
850static __le32
851nx_get_fw_version(struct netxen_adapter *adapter)
852{
853 struct uni_data_desc *fw_data_desc;
854 const struct firmware *fw = adapter->fw;
855 __le32 major, minor, sub;
856 const u8 *ver_str;
857 int i, ret = 0;
858
859 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
860
861 fw_data_desc = nx_get_data_desc(adapter,
862 NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
863 ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
864 cpu_to_le32(fw_data_desc->size) - 17;
865
866 for (i = 0; i < 12; i++) {
867 if (!strncmp(&ver_str[i], "REV=", 4)) {
868 ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
869 &major, &minor, &sub);
870 break;
871 }
872 }
873
874 if (ret != 3)
875 return 0;
876
877 return major + (minor << 8) + (sub << 16);
878
879 } else
880 return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
881}
882
883static __le32
884nx_get_bios_version(struct netxen_adapter *adapter)
885{
886 const struct firmware *fw = adapter->fw;
887 __le32 bios_ver, prd_off = adapter->file_prd_off;
888
889 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
890 bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
891 + NX_UNI_BIOS_VERSION_OFF));
892 return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
893 (bios_ver >> 24);
894 } else
895 return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
896
897}
898
899int
900netxen_need_fw_reset(struct netxen_adapter *adapter)
901{
902 u32 count, old_count;
903 u32 val, version, major, minor, build;
904 int i, timeout;
905 u8 fw_type;
906
907 /* NX2031 firmware doesn't support heartbit */
908 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
909 return 1;
910
911 if (adapter->need_fw_reset)
912 return 1;
913
914 /* last attempt had failed */
915 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
916 return 1;
917
918 old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
919
920 for (i = 0; i < 10; i++) {
921
922 timeout = msleep_interruptible(200);
923 if (timeout) {
924 NXWR32(adapter, CRB_CMDPEG_STATE,
925 PHAN_INITIALIZE_FAILED);
926 return -EINTR;
927 }
928
929 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
930 if (count != old_count)
931 break;
932 }
933
934 /* firmware is dead */
935 if (count == old_count)
936 return 1;
937
938 /* check if we have got newer or different file firmware */
939 if (adapter->fw) {
940
941 val = nx_get_fw_version(adapter);
942
943 version = NETXEN_DECODE_VERSION(val);
944
945 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
946 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
947 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
948
949 if (version > NETXEN_VERSION_CODE(major, minor, build))
950 return 1;
951
952 if (version == NETXEN_VERSION_CODE(major, minor, build) &&
953 adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
954
955 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
956 fw_type = (val & 0x4) ?
957 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
958
959 if (adapter->fw_type != fw_type)
960 return 1;
961 }
962 }
963
964 return 0;
965}
966
967#define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
968
969int
970netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
971{
972 u32 flash_fw_ver, min_fw_ver;
973
974 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
975 return 0;
976
977 if (netxen_rom_fast_read(adapter,
978 NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
979 dev_err(&adapter->pdev->dev, "Unable to read flash fw"
980 "version\n");
981 return -EIO;
982 }
983
984 flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
985 min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
986 if (flash_fw_ver >= min_fw_ver)
987 return 0;
988
989 dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
990 "[4.0.505]. Please update firmware on flash\n",
991 _major(flash_fw_ver), _minor(flash_fw_ver),
992 _build(flash_fw_ver));
993 return -EINVAL;
994}
995
996static char *fw_name[] = {
997 NX_P2_MN_ROMIMAGE_NAME,
998 NX_P3_CT_ROMIMAGE_NAME,
999 NX_P3_MN_ROMIMAGE_NAME,
1000 NX_UNIFIED_ROMIMAGE_NAME,
1001 NX_FLASH_ROMIMAGE_NAME,
1002};
1003
1004int
1005netxen_load_firmware(struct netxen_adapter *adapter)
1006{
1007 u64 *ptr64;
1008 u32 i, flashaddr, size;
1009 const struct firmware *fw = adapter->fw;
1010 struct pci_dev *pdev = adapter->pdev;
1011
1012 dev_info(&pdev->dev, "loading firmware from %s\n",
1013 fw_name[adapter->fw_type]);
1014
1015 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1016 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
1017
1018 if (fw) {
1019 __le64 data;
1020
1021 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
1022
1023 ptr64 = (u64 *)nx_get_bootld_offs(adapter);
1024 flashaddr = NETXEN_BOOTLD_START;
1025
1026 for (i = 0; i < size; i++) {
1027 data = cpu_to_le64(ptr64[i]);
1028
1029 if (adapter->pci_mem_write(adapter, flashaddr, data))
1030 return -EIO;
1031
1032 flashaddr += 8;
1033 }
1034
1035 size = (__force u32)nx_get_fw_size(adapter) / 8;
1036
1037 ptr64 = (u64 *)nx_get_fw_offs(adapter);
1038 flashaddr = NETXEN_IMAGE_START;
1039
1040 for (i = 0; i < size; i++) {
1041 data = cpu_to_le64(ptr64[i]);
1042
1043 if (adapter->pci_mem_write(adapter,
1044 flashaddr, data))
1045 return -EIO;
1046
1047 flashaddr += 8;
1048 }
1049
1050 size = (__force u32)nx_get_fw_size(adapter) % 8;
1051 if (size) {
1052 data = cpu_to_le64(ptr64[i]);
1053
1054 if (adapter->pci_mem_write(adapter,
1055 flashaddr, data))
1056 return -EIO;
1057 }
1058
1059 } else {
1060 u64 data;
1061 u32 hi, lo;
1062
1063 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
1064 flashaddr = NETXEN_BOOTLD_START;
1065
1066 for (i = 0; i < size; i++) {
1067 if (netxen_rom_fast_read(adapter,
1068 flashaddr, (int *)&lo) != 0)
1069 return -EIO;
1070 if (netxen_rom_fast_read(adapter,
1071 flashaddr + 4, (int *)&hi) != 0)
1072 return -EIO;
1073
1074 /* hi, lo are already in host endian byteorder */
1075 data = (((u64)hi << 32) | lo);
1076
1077 if (adapter->pci_mem_write(adapter,
1078 flashaddr, data))
1079 return -EIO;
1080
1081 flashaddr += 8;
1082 }
1083 }
1084 msleep(1);
1085
1086 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
1087 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
1088 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
1089 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1090 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1091 else {
1092 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1093 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1094 }
1095
1096 return 0;
1097}
1098
1099static int
1100netxen_validate_firmware(struct netxen_adapter *adapter)
1101{
1102 __le32 val;
1103 __le32 flash_fw_ver;
1104 u32 file_fw_ver, min_ver, bios;
1105 struct pci_dev *pdev = adapter->pdev;
1106 const struct firmware *fw = adapter->fw;
1107 u8 fw_type = adapter->fw_type;
1108 u32 crbinit_fix_fw;
1109
1110 if (fw_type == NX_UNIFIED_ROMIMAGE) {
1111 if (netxen_nic_validate_unified_romimage(adapter))
1112 return -EINVAL;
1113 } else {
1114 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1115 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1116 return -EINVAL;
1117
1118 if (fw->size < NX_FW_MIN_SIZE)
1119 return -EINVAL;
1120 }
1121
1122 val = nx_get_fw_version(adapter);
1123
1124 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1125 min_ver = NETXEN_MIN_P3_FW_SUPP;
1126 else
1127 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1128
1129 file_fw_ver = NETXEN_DECODE_VERSION(val);
1130
1131 if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
1132 (file_fw_ver < min_ver)) {
1133 dev_err(&pdev->dev,
1134 "%s: firmware version %d.%d.%d unsupported\n",
1135 fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
1136 _build(file_fw_ver));
1137 return -EINVAL;
1138 }
1139
1140 val = nx_get_bios_version(adapter);
1141 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1142 if ((__force u32)val != bios) {
1143 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1144 fw_name[fw_type]);
1145 return -EINVAL;
1146 }
1147
1148 if (netxen_rom_fast_read(adapter,
1149 NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
1150 dev_err(&pdev->dev, "Unable to read flash fw version\n");
1151 return -EIO;
1152 }
1153 flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
1154
1155 /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
1156 crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
1157 if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
1158 NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1159 dev_err(&pdev->dev, "Incompatibility detected between driver "
1160 "and firmware version on flash. This configuration "
1161 "is not recommended. Please update the firmware on "
1162 "flash immediately\n");
1163 return -EINVAL;
1164 }
1165
1166 /* check if flashed firmware is newer only for no-mn and P2 case*/
1167 if (!netxen_p3_has_mn(adapter) ||
1168 NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1169 if (flash_fw_ver > file_fw_ver) {
1170 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
1171 fw_name[fw_type]);
1172 return -EINVAL;
1173 }
1174 }
1175
1176 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1177 return 0;
1178}
1179
1180static void
1181nx_get_next_fwtype(struct netxen_adapter *adapter)
1182{
1183 u8 fw_type;
1184
1185 switch (adapter->fw_type) {
1186 case NX_UNKNOWN_ROMIMAGE:
1187 fw_type = NX_UNIFIED_ROMIMAGE;
1188 break;
1189
1190 case NX_UNIFIED_ROMIMAGE:
1191 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1192 fw_type = NX_FLASH_ROMIMAGE;
1193 else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1194 fw_type = NX_P2_MN_ROMIMAGE;
1195 else if (netxen_p3_has_mn(adapter))
1196 fw_type = NX_P3_MN_ROMIMAGE;
1197 else
1198 fw_type = NX_P3_CT_ROMIMAGE;
1199 break;
1200
1201 case NX_P3_MN_ROMIMAGE:
1202 fw_type = NX_P3_CT_ROMIMAGE;
1203 break;
1204
1205 case NX_P2_MN_ROMIMAGE:
1206 case NX_P3_CT_ROMIMAGE:
1207 default:
1208 fw_type = NX_FLASH_ROMIMAGE;
1209 break;
1210 }
1211
1212 adapter->fw_type = fw_type;
1213}
1214
1215static int
1216netxen_p3_has_mn(struct netxen_adapter *adapter)
1217{
1218 u32 capability, flashed_ver;
1219 capability = 0;
1220
1221 /* NX2031 always had MN */
1222 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1223 return 1;
1224
1225 netxen_rom_fast_read(adapter,
1226 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1227 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
1228
1229 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1230
1231 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
1232 if (capability & NX_PEG_TUNE_MN_PRESENT)
1233 return 1;
1234 }
1235 return 0;
1236}
1237
1238void netxen_request_firmware(struct netxen_adapter *adapter)
1239{
1240 struct pci_dev *pdev = adapter->pdev;
1241 int rc = 0;
1242
1243 adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
1244
1245next:
1246 nx_get_next_fwtype(adapter);
1247
1248 if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
1249 adapter->fw = NULL;
1250 } else {
1251 rc = request_firmware(&adapter->fw,
1252 fw_name[adapter->fw_type], &pdev->dev);
1253 if (rc != 0)
1254 goto next;
1255
1256 rc = netxen_validate_firmware(adapter);
1257 if (rc != 0) {
1258 release_firmware(adapter->fw);
1259 msleep(1);
1260 goto next;
1261 }
1262 }
1263}
1264
1265
1266void
1267netxen_release_firmware(struct netxen_adapter *adapter)
1268{
1269 if (adapter->fw)
1270 release_firmware(adapter->fw);
1271 adapter->fw = NULL;
1272}
1273
1274int netxen_init_dummy_dma(struct netxen_adapter *adapter)
1275{
1276 u64 addr;
1277 u32 hi, lo;
1278
1279 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1280 return 0;
1281
1282 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
1283 NETXEN_HOST_DUMMY_DMA_SIZE,
1284 &adapter->dummy_dma.phys_addr);
1285 if (adapter->dummy_dma.addr == NULL) {
1286 dev_err(&adapter->pdev->dev,
1287 "ERROR: Could not allocate dummy DMA memory\n");
1288 return -ENOMEM;
1289 }
1290
1291 addr = (uint64_t) adapter->dummy_dma.phys_addr;
1292 hi = (addr >> 32) & 0xffffffff;
1293 lo = addr & 0xffffffff;
1294
1295 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
1296 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
1297
1298 return 0;
1299}
1300
1301/*
1302 * NetXen DMA watchdog control:
1303 *
1304 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1305 * Bit 1 : disable_request => 1 req disable dma watchdog
1306 * Bit 2 : enable_request => 1 req enable dma watchdog
1307 * Bit 3-31 : unused
1308 */
1309void netxen_free_dummy_dma(struct netxen_adapter *adapter)
1310{
1311 int i = 100;
1312 u32 ctrl;
1313
1314 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1315 return;
1316
1317 if (!adapter->dummy_dma.addr)
1318 return;
1319
1320 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1321 if ((ctrl & 0x1) != 0) {
1322 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
1323
1324 while ((ctrl & 0x1) != 0) {
1325
1326 msleep(50);
1327
1328 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1329
1330 if (--i == 0)
1331 break;
1332 }
1333 }
1334
1335 if (i) {
1336 pci_free_consistent(adapter->pdev,
1337 NETXEN_HOST_DUMMY_DMA_SIZE,
1338 adapter->dummy_dma.addr,
1339 adapter->dummy_dma.phys_addr);
1340 adapter->dummy_dma.addr = NULL;
1341 } else
1342 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
1343}
1344
1345int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
1346{
1347 u32 val = 0;
1348 int retries = 60;
1349
1350 if (pegtune_val)
1351 return 0;
1352
1353 do {
1354 val = NXRD32(adapter, CRB_CMDPEG_STATE);
1355
1356 switch (val) {
1357 case PHAN_INITIALIZE_COMPLETE:
1358 case PHAN_INITIALIZE_ACK:
1359 return 0;
1360 case PHAN_INITIALIZE_FAILED:
1361 goto out_err;
1362 default:
1363 break;
1364 }
1365
1366 msleep(500);
1367
1368 } while (--retries);
1369
1370 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1371
1372out_err:
1373 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
1374 return -EIO;
1375}
1376
1377static int
1378netxen_receive_peg_ready(struct netxen_adapter *adapter)
1379{
1380 u32 val = 0;
1381 int retries = 2000;
1382
1383 do {
1384 val = NXRD32(adapter, CRB_RCVPEG_STATE);
1385
1386 if (val == PHAN_PEG_RCV_INITIALIZED)
1387 return 0;
1388
1389 msleep(10);
1390
1391 } while (--retries);
1392
1393 if (!retries) {
1394 printk(KERN_ERR "Receive Peg initialization not "
1395 "complete, state: 0x%x.\n", val);
1396 return -EIO;
1397 }
1398
1399 return 0;
1400}
1401
1402int netxen_init_firmware(struct netxen_adapter *adapter)
1403{
1404 int err;
1405
1406 err = netxen_receive_peg_ready(adapter);
1407 if (err)
1408 return err;
1409
1410 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
1411 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1412 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
1413
1414 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1415 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1416
1417 return err;
1418}
1419
1420static void
1421netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1422{
1423 u32 cable_OUI;
1424 u16 cable_len;
1425 u16 link_speed;
1426 u8 link_status, module, duplex, autoneg;
1427 struct net_device *netdev = adapter->netdev;
1428
1429 adapter->has_link_events = 1;
1430
1431 cable_OUI = msg->body[1] & 0xffffffff;
1432 cable_len = (msg->body[1] >> 32) & 0xffff;
1433 link_speed = (msg->body[1] >> 48) & 0xffff;
1434
1435 link_status = msg->body[2] & 0xff;
1436 duplex = (msg->body[2] >> 16) & 0xff;
1437 autoneg = (msg->body[2] >> 24) & 0xff;
1438
1439 module = (msg->body[2] >> 8) & 0xff;
1440 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1441 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1442 netdev->name, cable_OUI, cable_len);
1443 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1444 printk(KERN_INFO "%s: unsupported cable length %d\n",
1445 netdev->name, cable_len);
1446 }
1447
1448 netxen_advert_link_change(adapter, link_status);
1449
1450 /* update link parameters */
1451 if (duplex == LINKEVENT_FULL_DUPLEX)
1452 adapter->link_duplex = DUPLEX_FULL;
1453 else
1454 adapter->link_duplex = DUPLEX_HALF;
1455 adapter->module_type = module;
1456 adapter->link_autoneg = autoneg;
1457 adapter->link_speed = link_speed;
1458}
1459
1460static void
1461netxen_handle_fw_message(int desc_cnt, int index,
1462 struct nx_host_sds_ring *sds_ring)
1463{
1464 nx_fw_msg_t msg;
1465 struct status_desc *desc;
1466 int i = 0, opcode;
1467
1468 while (desc_cnt > 0 && i < 8) {
1469 desc = &sds_ring->desc_head[index];
1470 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1471 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1472
1473 index = get_next_index(index, sds_ring->num_desc);
1474 desc_cnt--;
1475 }
1476
1477 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1478 switch (opcode) {
1479 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1480 netxen_handle_linkevent(sds_ring->adapter, &msg);
1481 break;
1482 default:
1483 break;
1484 }
1485}
1486
1487static int
1488netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1489 struct nx_host_rds_ring *rds_ring,
1490 struct netxen_rx_buffer *buffer)
1491{
1492 struct sk_buff *skb;
1493 dma_addr_t dma;
1494 struct pci_dev *pdev = adapter->pdev;
1495
1496 buffer->skb = dev_alloc_skb(rds_ring->skb_size);
1497 if (!buffer->skb)
1498 return 1;
1499
1500 skb = buffer->skb;
1501
1502 if (!adapter->ahw.cut_through)
1503 skb_reserve(skb, 2);
1504
1505 dma = pci_map_single(pdev, skb->data,
1506 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1507
1508 if (pci_dma_mapping_error(pdev, dma)) {
1509 dev_kfree_skb_any(skb);
1510 buffer->skb = NULL;
1511 return 1;
1512 }
1513
1514 buffer->skb = skb;
1515 buffer->dma = dma;
1516 buffer->state = NETXEN_BUFFER_BUSY;
1517
1518 return 0;
1519}
1520
1521static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1522 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1523{
1524 struct netxen_rx_buffer *buffer;
1525 struct sk_buff *skb;
1526
1527 buffer = &rds_ring->rx_buf_arr[index];
1528
1529 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1530 PCI_DMA_FROMDEVICE);
1531
1532 skb = buffer->skb;
1533 if (!skb)
1534 goto no_skb;
1535
1536 if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
1537 && cksum == STATUS_CKSUM_OK)) {
1538 adapter->stats.csummed++;
1539 skb->ip_summed = CHECKSUM_UNNECESSARY;
1540 } else
1541 skb->ip_summed = CHECKSUM_NONE;
1542
1543 skb->dev = adapter->netdev;
1544
1545 buffer->skb = NULL;
1546no_skb:
1547 buffer->state = NETXEN_BUFFER_FREE;
1548 return skb;
1549}
1550
1551static struct netxen_rx_buffer *
1552netxen_process_rcv(struct netxen_adapter *adapter,
1553 struct nx_host_sds_ring *sds_ring,
1554 int ring, u64 sts_data0)
1555{
1556 struct net_device *netdev = adapter->netdev;
1557 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1558 struct netxen_rx_buffer *buffer;
1559 struct sk_buff *skb;
1560 struct nx_host_rds_ring *rds_ring;
1561 int index, length, cksum, pkt_offset;
1562
1563 if (unlikely(ring >= adapter->max_rds_rings))
1564 return NULL;
1565
1566 rds_ring = &recv_ctx->rds_rings[ring];
1567
1568 index = netxen_get_sts_refhandle(sts_data0);
1569 if (unlikely(index >= rds_ring->num_desc))
1570 return NULL;
1571
1572 buffer = &rds_ring->rx_buf_arr[index];
1573
1574 length = netxen_get_sts_totallength(sts_data0);
1575 cksum = netxen_get_sts_status(sts_data0);
1576 pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
1577
1578 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1579 if (!skb)
1580 return buffer;
1581
1582 if (length > rds_ring->skb_size)
1583 skb_put(skb, rds_ring->skb_size);
1584 else
1585 skb_put(skb, length);
1586
1587
1588 if (pkt_offset)
1589 skb_pull(skb, pkt_offset);
1590
1591 skb->protocol = eth_type_trans(skb, netdev);
1592
1593 napi_gro_receive(&sds_ring->napi, skb);
1594
1595 adapter->stats.rx_pkts++;
1596 adapter->stats.rxbytes += length;
1597
1598 return buffer;
1599}
1600
1601#define TCP_HDR_SIZE 20
1602#define TCP_TS_OPTION_SIZE 12
1603#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
1604
1605static struct netxen_rx_buffer *
1606netxen_process_lro(struct netxen_adapter *adapter,
1607 struct nx_host_sds_ring *sds_ring,
1608 int ring, u64 sts_data0, u64 sts_data1)
1609{
1610 struct net_device *netdev = adapter->netdev;
1611 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1612 struct netxen_rx_buffer *buffer;
1613 struct sk_buff *skb;
1614 struct nx_host_rds_ring *rds_ring;
1615 struct iphdr *iph;
1616 struct tcphdr *th;
1617 bool push, timestamp;
1618 int l2_hdr_offset, l4_hdr_offset;
1619 int index;
1620 u16 lro_length, length, data_offset;
1621 u32 seq_number;
1622
1623 if (unlikely(ring > adapter->max_rds_rings))
1624 return NULL;
1625
1626 rds_ring = &recv_ctx->rds_rings[ring];
1627
1628 index = netxen_get_lro_sts_refhandle(sts_data0);
1629 if (unlikely(index > rds_ring->num_desc))
1630 return NULL;
1631
1632 buffer = &rds_ring->rx_buf_arr[index];
1633
1634 timestamp = netxen_get_lro_sts_timestamp(sts_data0);
1635 lro_length = netxen_get_lro_sts_length(sts_data0);
1636 l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
1637 l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
1638 push = netxen_get_lro_sts_push_flag(sts_data0);
1639 seq_number = netxen_get_lro_sts_seq_number(sts_data1);
1640
1641 skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
1642 if (!skb)
1643 return buffer;
1644
1645 if (timestamp)
1646 data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
1647 else
1648 data_offset = l4_hdr_offset + TCP_HDR_SIZE;
1649
1650 skb_put(skb, lro_length + data_offset);
1651
1652 skb_pull(skb, l2_hdr_offset);
1653 skb->protocol = eth_type_trans(skb, netdev);
1654
1655 iph = (struct iphdr *)skb->data;
1656 th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
1657
1658 length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
1659 iph->tot_len = htons(length);
1660 iph->check = 0;
1661 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
1662 th->psh = push;
1663 th->seq = htonl(seq_number);
1664
1665 length = skb->len;
1666
1667 netif_receive_skb(skb);
1668
1669 adapter->stats.lro_pkts++;
1670 adapter->stats.rxbytes += length;
1671
1672 return buffer;
1673}
1674
1675#define netxen_merge_rx_buffers(list, head) \
1676 do { list_splice_tail_init(list, head); } while (0);
1677
1678int
1679netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
1680{
1681 struct netxen_adapter *adapter = sds_ring->adapter;
1682
1683 struct list_head *cur;
1684
1685 struct status_desc *desc;
1686 struct netxen_rx_buffer *rxbuf;
1687
1688 u32 consumer = sds_ring->consumer;
1689
1690 int count = 0;
1691 u64 sts_data0, sts_data1;
1692 int opcode, ring = 0, desc_cnt;
1693
1694 while (count < max) {
1695 desc = &sds_ring->desc_head[consumer];
1696 sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
1697
1698 if (!(sts_data0 & STATUS_OWNER_HOST))
1699 break;
1700
1701 desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
1702
1703 opcode = netxen_get_sts_opcode(sts_data0);
1704
1705 switch (opcode) {
1706 case NETXEN_NIC_RXPKT_DESC:
1707 case NETXEN_OLD_RXPKT_DESC:
1708 case NETXEN_NIC_SYN_OFFLOAD:
1709 ring = netxen_get_sts_type(sts_data0);
1710 rxbuf = netxen_process_rcv(adapter, sds_ring,
1711 ring, sts_data0);
1712 break;
1713 case NETXEN_NIC_LRO_DESC:
1714 ring = netxen_get_lro_sts_type(sts_data0);
1715 sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
1716 rxbuf = netxen_process_lro(adapter, sds_ring,
1717 ring, sts_data0, sts_data1);
1718 break;
1719 case NETXEN_NIC_RESPONSE_DESC:
1720 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1721 default:
1722 goto skip;
1723 }
1724
1725 WARN_ON(desc_cnt > 1);
1726
1727 if (rxbuf)
1728 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1729
1730skip:
1731 for (; desc_cnt > 0; desc_cnt--) {
1732 desc = &sds_ring->desc_head[consumer];
1733 desc->status_desc_data[0] =
1734 cpu_to_le64(STATUS_OWNER_PHANTOM);
1735 consumer = get_next_index(consumer, sds_ring->num_desc);
1736 }
1737 count++;
1738 }
1739
1740 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1741 struct nx_host_rds_ring *rds_ring =
1742 &adapter->recv_ctx.rds_rings[ring];
1743
1744 if (!list_empty(&sds_ring->free_list[ring])) {
1745 list_for_each(cur, &sds_ring->free_list[ring]) {
1746 rxbuf = list_entry(cur,
1747 struct netxen_rx_buffer, list);
1748 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1749 }
1750 spin_lock(&rds_ring->lock);
1751 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1752 &rds_ring->free_list);
1753 spin_unlock(&rds_ring->lock);
1754 }
1755
1756 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1757 }
1758
1759 if (count) {
1760 sds_ring->consumer = consumer;
1761 NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
1762 }
1763
1764 return count;
1765}
1766
1767/* Process Command status ring */
1768int netxen_process_cmd_ring(struct netxen_adapter *adapter)
1769{
1770 u32 sw_consumer, hw_consumer;
1771 int count = 0, i;
1772 struct netxen_cmd_buffer *buffer;
1773 struct pci_dev *pdev = adapter->pdev;
1774 struct net_device *netdev = adapter->netdev;
1775 struct netxen_skb_frag *frag;
1776 int done = 0;
1777 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
1778
1779 if (!spin_trylock(&adapter->tx_clean_lock))
1780 return 1;
1781
1782 sw_consumer = tx_ring->sw_consumer;
1783 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1784
1785 while (sw_consumer != hw_consumer) {
1786 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
1787 if (buffer->skb) {
1788 frag = &buffer->frag_array[0];
1789 pci_unmap_single(pdev, frag->dma, frag->length,
1790 PCI_DMA_TODEVICE);
1791 frag->dma = 0ULL;
1792 for (i = 1; i < buffer->frag_count; i++) {
1793 frag++; /* Get the next frag */
1794 pci_unmap_page(pdev, frag->dma, frag->length,
1795 PCI_DMA_TODEVICE);
1796 frag->dma = 0ULL;
1797 }
1798
1799 adapter->stats.xmitfinished++;
1800 dev_kfree_skb_any(buffer->skb);
1801 buffer->skb = NULL;
1802 }
1803
1804 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
1805 if (++count >= MAX_STATUS_HANDLE)
1806 break;
1807 }
1808
1809 if (count && netif_running(netdev)) {
1810 tx_ring->sw_consumer = sw_consumer;
1811
1812 smp_mb();
1813
1814 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
1815 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
1816 netif_wake_queue(netdev);
1817 adapter->tx_timeo_cnt = 0;
1818 }
1819 /*
1820 * If everything is freed up to consumer then check if the ring is full
1821 * If the ring is full then check if more needs to be freed and
1822 * schedule the call back again.
1823 *
1824 * This happens when there are 2 CPUs. One could be freeing and the
1825 * other filling it. If the ring is full when we get out of here and
1826 * the card has already interrupted the host then the host can miss the
1827 * interrupt.
1828 *
1829 * There is still a possible race condition and the host could miss an
1830 * interrupt. The card has to take care of this.
1831 */
1832 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1833 done = (sw_consumer == hw_consumer);
1834 spin_unlock(&adapter->tx_clean_lock);
1835
1836 return done;
1837}
1838
1839void
1840netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1841 struct nx_host_rds_ring *rds_ring)
1842{
1843 struct rcv_desc *pdesc;
1844 struct netxen_rx_buffer *buffer;
1845 int producer, count = 0;
1846 netxen_ctx_msg msg = 0;
1847 struct list_head *head;
1848
1849 producer = rds_ring->producer;
1850
1851 head = &rds_ring->free_list;
1852 while (!list_empty(head)) {
1853
1854 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
1855
1856 if (!buffer->skb) {
1857 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1858 break;
1859 }
1860
1861 count++;
1862 list_del(&buffer->list);
1863
1864 /* make a rcv descriptor */
1865 pdesc = &rds_ring->desc_head[producer];
1866 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
1867 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
1868 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
1869
1870 producer = get_next_index(producer, rds_ring->num_desc);
1871 }
1872
1873 if (count) {
1874 rds_ring->producer = producer;
1875 NXWRIO(adapter, rds_ring->crb_rcv_producer,
1876 (producer-1) & (rds_ring->num_desc-1));
1877
1878 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1879 /*
1880 * Write a doorbell msg to tell phanmon of change in
1881 * receive ring producer
1882 * Only for firmware version < 4.0.0
1883 */
1884 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1885 netxen_set_msg_privid(msg);
1886 netxen_set_msg_count(msg,
1887 ((producer - 1) &
1888 (rds_ring->num_desc - 1)));
1889 netxen_set_msg_ctxid(msg, adapter->portnum);
1890 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
1891 NXWRIO(adapter, DB_NORMALIZE(adapter,
1892 NETXEN_RCV_PRODUCER_OFFSET), msg);
1893 }
1894 }
1895}
1896
1897static void
1898netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1899 struct nx_host_rds_ring *rds_ring)
1900{
1901 struct rcv_desc *pdesc;
1902 struct netxen_rx_buffer *buffer;
1903 int producer, count = 0;
1904 struct list_head *head;
1905
1906 if (!spin_trylock(&rds_ring->lock))
1907 return;
1908
1909 producer = rds_ring->producer;
1910
1911 head = &rds_ring->free_list;
1912 while (!list_empty(head)) {
1913
1914 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
1915
1916 if (!buffer->skb) {
1917 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1918 break;
1919 }
1920
1921 count++;
1922 list_del(&buffer->list);
1923
1924 /* make a rcv descriptor */
1925 pdesc = &rds_ring->desc_head[producer];
1926 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
1927 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
1928 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
1929
1930 producer = get_next_index(producer, rds_ring->num_desc);
1931 }
1932
1933 if (count) {
1934 rds_ring->producer = producer;
1935 NXWRIO(adapter, rds_ring->crb_rcv_producer,
1936 (producer - 1) & (rds_ring->num_desc - 1));
1937 }
1938 spin_unlock(&rds_ring->lock);
1939}
1940
1941void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1942{
1943 memset(&adapter->stats, 0, sizeof(adapter->stats));
1944}
1945
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
new file mode 100644
index 00000000000..f574edff7fc
--- /dev/null
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -0,0 +1,3013 @@
1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#include <linux/slab.h>
27#include <linux/vmalloc.h>
28#include <linux/interrupt.h>
29#include "netxen_nic_hw.h"
30
31#include "netxen_nic.h"
32
33#include <linux/dma-mapping.h>
34#include <linux/if_vlan.h>
35#include <net/ip.h>
36#include <linux/ipv6.h>
37#include <linux/inetdevice.h>
38#include <linux/sysfs.h>
39#include <linux/aer.h>
40
41MODULE_DESCRIPTION("QLogic/NetXen (1/10) GbE Intelligent Ethernet Driver");
42MODULE_LICENSE("GPL");
43MODULE_VERSION(NETXEN_NIC_LINUX_VERSIONID);
44MODULE_FIRMWARE(NX_UNIFIED_ROMIMAGE_NAME);
45
46char netxen_nic_driver_name[] = "netxen_nic";
47static char netxen_nic_driver_string[] = "QLogic/NetXen Network Driver v"
48 NETXEN_NIC_LINUX_VERSIONID;
49
50static int port_mode = NETXEN_PORT_MODE_AUTO_NEG;
51
52/* Default to restricted 1G auto-neg mode */
53static int wol_port_mode = 5;
54
55static int use_msi = 1;
56
57static int use_msi_x = 1;
58
59static int auto_fw_reset = AUTO_FW_RESET_ENABLED;
60module_param(auto_fw_reset, int, 0644);
61MODULE_PARM_DESC(auto_fw_reset,"Auto firmware reset (0=disabled, 1=enabled");
62
63static int __devinit netxen_nic_probe(struct pci_dev *pdev,
64 const struct pci_device_id *ent);
65static void __devexit netxen_nic_remove(struct pci_dev *pdev);
66static int netxen_nic_open(struct net_device *netdev);
67static int netxen_nic_close(struct net_device *netdev);
68static netdev_tx_t netxen_nic_xmit_frame(struct sk_buff *,
69 struct net_device *);
70static void netxen_tx_timeout(struct net_device *netdev);
71static void netxen_tx_timeout_task(struct work_struct *work);
72static void netxen_fw_poll_work(struct work_struct *work);
73static void netxen_schedule_work(struct netxen_adapter *adapter,
74 work_func_t func, int delay);
75static void netxen_cancel_fw_work(struct netxen_adapter *adapter);
76static int netxen_nic_poll(struct napi_struct *napi, int budget);
77#ifdef CONFIG_NET_POLL_CONTROLLER
78static void netxen_nic_poll_controller(struct net_device *netdev);
79#endif
80
81static void netxen_create_sysfs_entries(struct netxen_adapter *adapter);
82static void netxen_remove_sysfs_entries(struct netxen_adapter *adapter);
83static void netxen_create_diag_entries(struct netxen_adapter *adapter);
84static void netxen_remove_diag_entries(struct netxen_adapter *adapter);
85
86static int nx_dev_request_aer(struct netxen_adapter *adapter);
87static int nx_decr_dev_ref_cnt(struct netxen_adapter *adapter);
88static int netxen_can_start_firmware(struct netxen_adapter *adapter);
89
90static irqreturn_t netxen_intr(int irq, void *data);
91static irqreturn_t netxen_msi_intr(int irq, void *data);
92static irqreturn_t netxen_msix_intr(int irq, void *data);
93
94static void netxen_config_indev_addr(struct net_device *dev, unsigned long);
95static struct rtnl_link_stats64 *netxen_nic_get_stats(struct net_device *dev,
96 struct rtnl_link_stats64 *stats);
97static int netxen_nic_set_mac(struct net_device *netdev, void *p);
98
99/* PCI Device ID Table */
100#define ENTRY(device) \
101 {PCI_DEVICE(PCI_VENDOR_ID_NETXEN, (device)), \
102 .class = PCI_CLASS_NETWORK_ETHERNET << 8, .class_mask = ~0}
103
104static DEFINE_PCI_DEVICE_TABLE(netxen_pci_tbl) = {
105 ENTRY(PCI_DEVICE_ID_NX2031_10GXSR),
106 ENTRY(PCI_DEVICE_ID_NX2031_10GCX4),
107 ENTRY(PCI_DEVICE_ID_NX2031_4GCU),
108 ENTRY(PCI_DEVICE_ID_NX2031_IMEZ),
109 ENTRY(PCI_DEVICE_ID_NX2031_HMEZ),
110 ENTRY(PCI_DEVICE_ID_NX2031_XG_MGMT),
111 ENTRY(PCI_DEVICE_ID_NX2031_XG_MGMT2),
112 ENTRY(PCI_DEVICE_ID_NX3031),
113 {0,}
114};
115
116MODULE_DEVICE_TABLE(pci, netxen_pci_tbl);
117
118static uint32_t crb_cmd_producer[4] = {
119 CRB_CMD_PRODUCER_OFFSET, CRB_CMD_PRODUCER_OFFSET_1,
120 CRB_CMD_PRODUCER_OFFSET_2, CRB_CMD_PRODUCER_OFFSET_3
121};
122
123void
124netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
125 struct nx_host_tx_ring *tx_ring)
126{
127 NXWRIO(adapter, tx_ring->crb_cmd_producer, tx_ring->producer);
128}
129
130static uint32_t crb_cmd_consumer[4] = {
131 CRB_CMD_CONSUMER_OFFSET, CRB_CMD_CONSUMER_OFFSET_1,
132 CRB_CMD_CONSUMER_OFFSET_2, CRB_CMD_CONSUMER_OFFSET_3
133};
134
135static inline void
136netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter,
137 struct nx_host_tx_ring *tx_ring)
138{
139 NXWRIO(adapter, tx_ring->crb_cmd_consumer, tx_ring->sw_consumer);
140}
141
142static uint32_t msi_tgt_status[8] = {
143 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
144 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
145 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
146 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
147};
148
149static struct netxen_legacy_intr_set legacy_intr[] = NX_LEGACY_INTR_CONFIG;
150
151static inline void netxen_nic_disable_int(struct nx_host_sds_ring *sds_ring)
152{
153 struct netxen_adapter *adapter = sds_ring->adapter;
154
155 NXWRIO(adapter, sds_ring->crb_intr_mask, 0);
156}
157
158static inline void netxen_nic_enable_int(struct nx_host_sds_ring *sds_ring)
159{
160 struct netxen_adapter *adapter = sds_ring->adapter;
161
162 NXWRIO(adapter, sds_ring->crb_intr_mask, 0x1);
163
164 if (!NETXEN_IS_MSI_FAMILY(adapter))
165 NXWRIO(adapter, adapter->tgt_mask_reg, 0xfbff);
166}
167
168static int
169netxen_alloc_sds_rings(struct netxen_recv_context *recv_ctx, int count)
170{
171 int size = sizeof(struct nx_host_sds_ring) * count;
172
173 recv_ctx->sds_rings = kzalloc(size, GFP_KERNEL);
174
175 return recv_ctx->sds_rings == NULL;
176}
177
178static void
179netxen_free_sds_rings(struct netxen_recv_context *recv_ctx)
180{
181 if (recv_ctx->sds_rings != NULL)
182 kfree(recv_ctx->sds_rings);
183
184 recv_ctx->sds_rings = NULL;
185}
186
187static int
188netxen_napi_add(struct netxen_adapter *adapter, struct net_device *netdev)
189{
190 int ring;
191 struct nx_host_sds_ring *sds_ring;
192 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
193
194 if (netxen_alloc_sds_rings(recv_ctx, adapter->max_sds_rings))
195 return -ENOMEM;
196
197 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
198 sds_ring = &recv_ctx->sds_rings[ring];
199 netif_napi_add(netdev, &sds_ring->napi,
200 netxen_nic_poll, NETXEN_NETDEV_WEIGHT);
201 }
202
203 return 0;
204}
205
206static void
207netxen_napi_del(struct netxen_adapter *adapter)
208{
209 int ring;
210 struct nx_host_sds_ring *sds_ring;
211 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
212
213 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
214 sds_ring = &recv_ctx->sds_rings[ring];
215 netif_napi_del(&sds_ring->napi);
216 }
217
218 netxen_free_sds_rings(&adapter->recv_ctx);
219}
220
221static void
222netxen_napi_enable(struct netxen_adapter *adapter)
223{
224 int ring;
225 struct nx_host_sds_ring *sds_ring;
226 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
227
228 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
229 sds_ring = &recv_ctx->sds_rings[ring];
230 napi_enable(&sds_ring->napi);
231 netxen_nic_enable_int(sds_ring);
232 }
233}
234
235static void
236netxen_napi_disable(struct netxen_adapter *adapter)
237{
238 int ring;
239 struct nx_host_sds_ring *sds_ring;
240 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
241
242 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
243 sds_ring = &recv_ctx->sds_rings[ring];
244 netxen_nic_disable_int(sds_ring);
245 napi_synchronize(&sds_ring->napi);
246 napi_disable(&sds_ring->napi);
247 }
248}
249
250static int nx_set_dma_mask(struct netxen_adapter *adapter)
251{
252 struct pci_dev *pdev = adapter->pdev;
253 uint64_t mask, cmask;
254
255 adapter->pci_using_dac = 0;
256
257 mask = DMA_BIT_MASK(32);
258 cmask = DMA_BIT_MASK(32);
259
260 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
261#ifndef CONFIG_IA64
262 mask = DMA_BIT_MASK(35);
263#endif
264 } else {
265 mask = DMA_BIT_MASK(39);
266 cmask = mask;
267 }
268
269 if (pci_set_dma_mask(pdev, mask) == 0 &&
270 pci_set_consistent_dma_mask(pdev, cmask) == 0) {
271 adapter->pci_using_dac = 1;
272 return 0;
273 }
274
275 return -EIO;
276}
277
278/* Update addressable range if firmware supports it */
279static int
280nx_update_dma_mask(struct netxen_adapter *adapter)
281{
282 int change, shift, err;
283 uint64_t mask, old_mask, old_cmask;
284 struct pci_dev *pdev = adapter->pdev;
285
286 change = 0;
287
288 shift = NXRD32(adapter, CRB_DMA_SHIFT);
289 if (shift > 32)
290 return 0;
291
292 if (NX_IS_REVISION_P3(adapter->ahw.revision_id) && (shift > 9))
293 change = 1;
294 else if ((adapter->ahw.revision_id == NX_P2_C1) && (shift <= 4))
295 change = 1;
296
297 if (change) {
298 old_mask = pdev->dma_mask;
299 old_cmask = pdev->dev.coherent_dma_mask;
300
301 mask = DMA_BIT_MASK(32+shift);
302
303 err = pci_set_dma_mask(pdev, mask);
304 if (err)
305 goto err_out;
306
307 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
308
309 err = pci_set_consistent_dma_mask(pdev, mask);
310 if (err)
311 goto err_out;
312 }
313 dev_info(&pdev->dev, "using %d-bit dma mask\n", 32+shift);
314 }
315
316 return 0;
317
318err_out:
319 pci_set_dma_mask(pdev, old_mask);
320 pci_set_consistent_dma_mask(pdev, old_cmask);
321 return err;
322}
323
324static int
325netxen_check_hw_init(struct netxen_adapter *adapter, int first_boot)
326{
327 u32 val, timeout;
328
329 if (first_boot == 0x55555555) {
330 /* This is the first boot after power up */
331 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
332
333 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
334 return 0;
335
336 /* PCI bus master workaround */
337 first_boot = NXRD32(adapter, NETXEN_PCIE_REG(0x4));
338 if (!(first_boot & 0x4)) {
339 first_boot |= 0x4;
340 NXWR32(adapter, NETXEN_PCIE_REG(0x4), first_boot);
341 NXRD32(adapter, NETXEN_PCIE_REG(0x4));
342 }
343
344 /* This is the first boot after power up */
345 first_boot = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
346 if (first_boot != 0x80000f) {
347 /* clear the register for future unloads/loads */
348 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), 0);
349 return -EIO;
350 }
351
352 /* Start P2 boot loader */
353 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
354 NXWR32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1);
355 timeout = 0;
356 do {
357 msleep(1);
358 val = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc));
359
360 if (++timeout > 5000)
361 return -EIO;
362
363 } while (val == NETXEN_BDINFO_MAGIC);
364 }
365 return 0;
366}
367
368static void netxen_set_port_mode(struct netxen_adapter *adapter)
369{
370 u32 val, data;
371
372 val = adapter->ahw.board_type;
373 if ((val == NETXEN_BRDTYPE_P3_HMEZ) ||
374 (val == NETXEN_BRDTYPE_P3_XG_LOM)) {
375 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
376 data = NETXEN_PORT_MODE_802_3_AP;
377 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
378 } else if (port_mode == NETXEN_PORT_MODE_XG) {
379 data = NETXEN_PORT_MODE_XG;
380 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
381 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_1G) {
382 data = NETXEN_PORT_MODE_AUTO_NEG_1G;
383 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
384 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_XG) {
385 data = NETXEN_PORT_MODE_AUTO_NEG_XG;
386 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
387 } else {
388 data = NETXEN_PORT_MODE_AUTO_NEG;
389 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
390 }
391
392 if ((wol_port_mode != NETXEN_PORT_MODE_802_3_AP) &&
393 (wol_port_mode != NETXEN_PORT_MODE_XG) &&
394 (wol_port_mode != NETXEN_PORT_MODE_AUTO_NEG_1G) &&
395 (wol_port_mode != NETXEN_PORT_MODE_AUTO_NEG_XG)) {
396 wol_port_mode = NETXEN_PORT_MODE_AUTO_NEG;
397 }
398 NXWR32(adapter, NETXEN_WOL_PORT_MODE, wol_port_mode);
399 }
400}
401
402static void netxen_set_msix_bit(struct pci_dev *pdev, int enable)
403{
404 u32 control;
405 int pos;
406
407 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
408 if (pos) {
409 pci_read_config_dword(pdev, pos, &control);
410 if (enable)
411 control |= PCI_MSIX_FLAGS_ENABLE;
412 else
413 control = 0;
414 pci_write_config_dword(pdev, pos, control);
415 }
416}
417
418static void netxen_init_msix_entries(struct netxen_adapter *adapter, int count)
419{
420 int i;
421
422 for (i = 0; i < count; i++)
423 adapter->msix_entries[i].entry = i;
424}
425
426static int
427netxen_read_mac_addr(struct netxen_adapter *adapter)
428{
429 int i;
430 unsigned char *p;
431 u64 mac_addr;
432 struct net_device *netdev = adapter->netdev;
433 struct pci_dev *pdev = adapter->pdev;
434
435 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
436 if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0)
437 return -EIO;
438 } else {
439 if (netxen_get_flash_mac_addr(adapter, &mac_addr) != 0)
440 return -EIO;
441 }
442
443 p = (unsigned char *)&mac_addr;
444 for (i = 0; i < 6; i++)
445 netdev->dev_addr[i] = *(p + 5 - i);
446
447 memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
448 memcpy(adapter->mac_addr, netdev->dev_addr, netdev->addr_len);
449
450 /* set station address */
451
452 if (!is_valid_ether_addr(netdev->perm_addr))
453 dev_warn(&pdev->dev, "Bad MAC address %pM.\n", netdev->dev_addr);
454
455 return 0;
456}
457
458static int netxen_nic_set_mac(struct net_device *netdev, void *p)
459{
460 struct netxen_adapter *adapter = netdev_priv(netdev);
461 struct sockaddr *addr = p;
462
463 if (!is_valid_ether_addr(addr->sa_data))
464 return -EINVAL;
465
466 if (netif_running(netdev)) {
467 netif_device_detach(netdev);
468 netxen_napi_disable(adapter);
469 }
470
471 memcpy(adapter->mac_addr, addr->sa_data, netdev->addr_len);
472 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
473 adapter->macaddr_set(adapter, addr->sa_data);
474
475 if (netif_running(netdev)) {
476 netif_device_attach(netdev);
477 netxen_napi_enable(adapter);
478 }
479 return 0;
480}
481
482static void netxen_set_multicast_list(struct net_device *dev)
483{
484 struct netxen_adapter *adapter = netdev_priv(dev);
485
486 adapter->set_multi(dev);
487}
488
489static u32 netxen_fix_features(struct net_device *dev, u32 features)
490{
491 if (!(features & NETIF_F_RXCSUM)) {
492 netdev_info(dev, "disabling LRO as RXCSUM is off\n");
493
494 features &= ~NETIF_F_LRO;
495 }
496
497 return features;
498}
499
500static int netxen_set_features(struct net_device *dev, u32 features)
501{
502 struct netxen_adapter *adapter = netdev_priv(dev);
503 int hw_lro;
504
505 if (!((dev->features ^ features) & NETIF_F_LRO))
506 return 0;
507
508 hw_lro = (features & NETIF_F_LRO) ? NETXEN_NIC_LRO_ENABLED
509 : NETXEN_NIC_LRO_DISABLED;
510
511 if (netxen_config_hw_lro(adapter, hw_lro))
512 return -EIO;
513
514 if (!(features & NETIF_F_LRO) && netxen_send_lro_cleanup(adapter))
515 return -EIO;
516
517 return 0;
518}
519
520static const struct net_device_ops netxen_netdev_ops = {
521 .ndo_open = netxen_nic_open,
522 .ndo_stop = netxen_nic_close,
523 .ndo_start_xmit = netxen_nic_xmit_frame,
524 .ndo_get_stats64 = netxen_nic_get_stats,
525 .ndo_validate_addr = eth_validate_addr,
526 .ndo_set_multicast_list = netxen_set_multicast_list,
527 .ndo_set_mac_address = netxen_nic_set_mac,
528 .ndo_change_mtu = netxen_nic_change_mtu,
529 .ndo_tx_timeout = netxen_tx_timeout,
530 .ndo_fix_features = netxen_fix_features,
531 .ndo_set_features = netxen_set_features,
532#ifdef CONFIG_NET_POLL_CONTROLLER
533 .ndo_poll_controller = netxen_nic_poll_controller,
534#endif
535};
536
537static void
538netxen_setup_intr(struct netxen_adapter *adapter)
539{
540 struct netxen_legacy_intr_set *legacy_intrp;
541 struct pci_dev *pdev = adapter->pdev;
542 int err, num_msix;
543
544 if (adapter->rss_supported) {
545 num_msix = (num_online_cpus() >= MSIX_ENTRIES_PER_ADAPTER) ?
546 MSIX_ENTRIES_PER_ADAPTER : 2;
547 } else
548 num_msix = 1;
549
550 adapter->max_sds_rings = 1;
551
552 adapter->flags &= ~(NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED);
553
554 if (adapter->ahw.revision_id >= NX_P3_B0)
555 legacy_intrp = &legacy_intr[adapter->ahw.pci_func];
556 else
557 legacy_intrp = &legacy_intr[0];
558
559 adapter->int_vec_bit = legacy_intrp->int_vec_bit;
560 adapter->tgt_status_reg = netxen_get_ioaddr(adapter,
561 legacy_intrp->tgt_status_reg);
562 adapter->tgt_mask_reg = netxen_get_ioaddr(adapter,
563 legacy_intrp->tgt_mask_reg);
564 adapter->pci_int_reg = netxen_get_ioaddr(adapter,
565 legacy_intrp->pci_int_reg);
566 adapter->isr_int_vec = netxen_get_ioaddr(adapter, ISR_INT_VECTOR);
567
568 if (adapter->ahw.revision_id >= NX_P3_B1)
569 adapter->crb_int_state_reg = netxen_get_ioaddr(adapter,
570 ISR_INT_STATE_REG);
571 else
572 adapter->crb_int_state_reg = netxen_get_ioaddr(adapter,
573 CRB_INT_VECTOR);
574
575 netxen_set_msix_bit(pdev, 0);
576
577 if (adapter->msix_supported) {
578
579 netxen_init_msix_entries(adapter, num_msix);
580 err = pci_enable_msix(pdev, adapter->msix_entries, num_msix);
581 if (err == 0) {
582 adapter->flags |= NETXEN_NIC_MSIX_ENABLED;
583 netxen_set_msix_bit(pdev, 1);
584
585 if (adapter->rss_supported)
586 adapter->max_sds_rings = num_msix;
587
588 dev_info(&pdev->dev, "using msi-x interrupts\n");
589 return;
590 }
591
592 if (err > 0)
593 pci_disable_msix(pdev);
594
595 /* fall through for msi */
596 }
597
598 if (use_msi && !pci_enable_msi(pdev)) {
599 adapter->flags |= NETXEN_NIC_MSI_ENABLED;
600 adapter->tgt_status_reg = netxen_get_ioaddr(adapter,
601 msi_tgt_status[adapter->ahw.pci_func]);
602 dev_info(&pdev->dev, "using msi interrupts\n");
603 adapter->msix_entries[0].vector = pdev->irq;
604 return;
605 }
606
607 dev_info(&pdev->dev, "using legacy interrupts\n");
608 adapter->msix_entries[0].vector = pdev->irq;
609}
610
611static void
612netxen_teardown_intr(struct netxen_adapter *adapter)
613{
614 if (adapter->flags & NETXEN_NIC_MSIX_ENABLED)
615 pci_disable_msix(adapter->pdev);
616 if (adapter->flags & NETXEN_NIC_MSI_ENABLED)
617 pci_disable_msi(adapter->pdev);
618}
619
620static void
621netxen_cleanup_pci_map(struct netxen_adapter *adapter)
622{
623 if (adapter->ahw.db_base != NULL)
624 iounmap(adapter->ahw.db_base);
625 if (adapter->ahw.pci_base0 != NULL)
626 iounmap(adapter->ahw.pci_base0);
627 if (adapter->ahw.pci_base1 != NULL)
628 iounmap(adapter->ahw.pci_base1);
629 if (adapter->ahw.pci_base2 != NULL)
630 iounmap(adapter->ahw.pci_base2);
631}
632
633static int
634netxen_setup_pci_map(struct netxen_adapter *adapter)
635{
636 void __iomem *db_ptr = NULL;
637
638 resource_size_t mem_base, db_base;
639 unsigned long mem_len, db_len = 0;
640
641 struct pci_dev *pdev = adapter->pdev;
642 int pci_func = adapter->ahw.pci_func;
643 struct netxen_hardware_context *ahw = &adapter->ahw;
644
645 int err = 0;
646
647 /*
648 * Set the CRB window to invalid. If any register in window 0 is
649 * accessed it should set the window to 0 and then reset it to 1.
650 */
651 adapter->ahw.crb_win = -1;
652 adapter->ahw.ocm_win = -1;
653
654 /* remap phys address */
655 mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */
656 mem_len = pci_resource_len(pdev, 0);
657
658 /* 128 Meg of memory */
659 if (mem_len == NETXEN_PCI_128MB_SIZE) {
660
661 ahw->pci_base0 = ioremap(mem_base, FIRST_PAGE_GROUP_SIZE);
662 ahw->pci_base1 = ioremap(mem_base + SECOND_PAGE_GROUP_START,
663 SECOND_PAGE_GROUP_SIZE);
664 ahw->pci_base2 = ioremap(mem_base + THIRD_PAGE_GROUP_START,
665 THIRD_PAGE_GROUP_SIZE);
666 if (ahw->pci_base0 == NULL || ahw->pci_base1 == NULL ||
667 ahw->pci_base2 == NULL) {
668 dev_err(&pdev->dev, "failed to map PCI bar 0\n");
669 err = -EIO;
670 goto err_out;
671 }
672
673 ahw->pci_len0 = FIRST_PAGE_GROUP_SIZE;
674
675 } else if (mem_len == NETXEN_PCI_32MB_SIZE) {
676
677 ahw->pci_base1 = ioremap(mem_base, SECOND_PAGE_GROUP_SIZE);
678 ahw->pci_base2 = ioremap(mem_base + THIRD_PAGE_GROUP_START -
679 SECOND_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE);
680 if (ahw->pci_base1 == NULL || ahw->pci_base2 == NULL) {
681 dev_err(&pdev->dev, "failed to map PCI bar 0\n");
682 err = -EIO;
683 goto err_out;
684 }
685
686 } else if (mem_len == NETXEN_PCI_2MB_SIZE) {
687
688 ahw->pci_base0 = pci_ioremap_bar(pdev, 0);
689 if (ahw->pci_base0 == NULL) {
690 dev_err(&pdev->dev, "failed to map PCI bar 0\n");
691 return -EIO;
692 }
693 ahw->pci_len0 = mem_len;
694 } else {
695 return -EIO;
696 }
697
698 netxen_setup_hwops(adapter);
699
700 dev_info(&pdev->dev, "%dMB memory map\n", (int)(mem_len>>20));
701
702 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
703 adapter->ahw.ocm_win_crb = netxen_get_ioaddr(adapter,
704 NETXEN_PCIX_PS_REG(PCIX_OCM_WINDOW_REG(pci_func)));
705
706 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
707 adapter->ahw.ocm_win_crb = netxen_get_ioaddr(adapter,
708 NETXEN_PCIX_PS_REG(PCIE_MN_WINDOW_REG(pci_func)));
709 }
710
711 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
712 goto skip_doorbell;
713
714 db_base = pci_resource_start(pdev, 4); /* doorbell is on bar 4 */
715 db_len = pci_resource_len(pdev, 4);
716
717 if (db_len == 0) {
718 printk(KERN_ERR "%s: doorbell is disabled\n",
719 netxen_nic_driver_name);
720 err = -EIO;
721 goto err_out;
722 }
723
724 db_ptr = ioremap(db_base, NETXEN_DB_MAPSIZE_BYTES);
725 if (!db_ptr) {
726 printk(KERN_ERR "%s: Failed to allocate doorbell map.",
727 netxen_nic_driver_name);
728 err = -EIO;
729 goto err_out;
730 }
731
732skip_doorbell:
733 adapter->ahw.db_base = db_ptr;
734 adapter->ahw.db_len = db_len;
735 return 0;
736
737err_out:
738 netxen_cleanup_pci_map(adapter);
739 return err;
740}
741
742static void
743netxen_check_options(struct netxen_adapter *adapter)
744{
745 u32 fw_major, fw_minor, fw_build;
746 char brd_name[NETXEN_MAX_SHORT_NAME];
747 char serial_num[32];
748 int i, offset, val;
749 int *ptr32;
750 struct pci_dev *pdev = adapter->pdev;
751
752 adapter->driver_mismatch = 0;
753
754 ptr32 = (int *)&serial_num;
755 offset = NX_FW_SERIAL_NUM_OFFSET;
756 for (i = 0; i < 8; i++) {
757 if (netxen_rom_fast_read(adapter, offset, &val) == -1) {
758 dev_err(&pdev->dev, "error reading board info\n");
759 adapter->driver_mismatch = 1;
760 return;
761 }
762 ptr32[i] = cpu_to_le32(val);
763 offset += sizeof(u32);
764 }
765
766 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
767 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
768 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
769
770 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
771
772 if (adapter->portnum == 0) {
773 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
774
775 pr_info("%s: %s Board S/N %s Chip rev 0x%x\n",
776 module_name(THIS_MODULE),
777 brd_name, serial_num, adapter->ahw.revision_id);
778 }
779
780 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
781 adapter->driver_mismatch = 1;
782 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
783 fw_major, fw_minor, fw_build);
784 return;
785 }
786
787 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
788 i = NXRD32(adapter, NETXEN_SRE_MISC);
789 adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0;
790 }
791
792 dev_info(&pdev->dev, "firmware v%d.%d.%d [%s]\n",
793 fw_major, fw_minor, fw_build,
794 adapter->ahw.cut_through ? "cut-through" : "legacy");
795
796 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222))
797 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
798
799 if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
800 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
801 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
802 } else if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
803 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
804 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
805 }
806
807 adapter->msix_supported = 0;
808 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
809 adapter->msix_supported = !!use_msi_x;
810 adapter->rss_supported = !!use_msi_x;
811 } else {
812 u32 flashed_ver = 0;
813 netxen_rom_fast_read(adapter,
814 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
815 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
816
817 if (flashed_ver >= NETXEN_VERSION_CODE(3, 4, 336)) {
818 switch (adapter->ahw.board_type) {
819 case NETXEN_BRDTYPE_P2_SB31_10G:
820 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
821 adapter->msix_supported = !!use_msi_x;
822 adapter->rss_supported = !!use_msi_x;
823 break;
824 default:
825 break;
826 }
827 }
828 }
829
830 adapter->num_txd = MAX_CMD_DESCRIPTORS;
831
832 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
833 adapter->num_lro_rxd = MAX_LRO_RCV_DESCRIPTORS;
834 adapter->max_rds_rings = 3;
835 } else {
836 adapter->num_lro_rxd = 0;
837 adapter->max_rds_rings = 2;
838 }
839}
840
841static int
842netxen_start_firmware(struct netxen_adapter *adapter)
843{
844 int val, err, first_boot;
845 struct pci_dev *pdev = adapter->pdev;
846
847 /* required for NX2031 dummy dma */
848 err = nx_set_dma_mask(adapter);
849 if (err)
850 return err;
851
852 if (!netxen_can_start_firmware(adapter))
853 goto wait_init;
854
855 first_boot = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc));
856
857 err = netxen_check_hw_init(adapter, first_boot);
858 if (err) {
859 dev_err(&pdev->dev, "error in init HW init sequence\n");
860 return err;
861 }
862
863 netxen_request_firmware(adapter);
864
865 err = netxen_need_fw_reset(adapter);
866 if (err < 0)
867 goto err_out;
868 if (err == 0)
869 goto wait_init;
870
871 if (first_boot != 0x55555555) {
872 NXWR32(adapter, CRB_CMDPEG_STATE, 0);
873 netxen_pinit_from_rom(adapter);
874 msleep(1);
875 }
876
877 NXWR32(adapter, CRB_DMA_SHIFT, 0x55555555);
878 NXWR32(adapter, NETXEN_PEG_HALT_STATUS1, 0);
879 NXWR32(adapter, NETXEN_PEG_HALT_STATUS2, 0);
880
881 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
882 netxen_set_port_mode(adapter);
883
884 err = netxen_load_firmware(adapter);
885 if (err)
886 goto err_out;
887
888 netxen_release_firmware(adapter);
889
890 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
891
892 /* Initialize multicast addr pool owners */
893 val = 0x7654;
894 if (adapter->ahw.port_type == NETXEN_NIC_XGBE)
895 val |= 0x0f000000;
896 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
897
898 }
899
900 err = netxen_init_dummy_dma(adapter);
901 if (err)
902 goto err_out;
903
904 /*
905 * Tell the hardware our version number.
906 */
907 val = (_NETXEN_NIC_LINUX_MAJOR << 16)
908 | ((_NETXEN_NIC_LINUX_MINOR << 8))
909 | (_NETXEN_NIC_LINUX_SUBVERSION);
910 NXWR32(adapter, CRB_DRIVER_VERSION, val);
911
912wait_init:
913 /* Handshake with the card before we register the devices. */
914 err = netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
915 if (err) {
916 netxen_free_dummy_dma(adapter);
917 goto err_out;
918 }
919
920 NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_READY);
921
922 nx_update_dma_mask(adapter);
923
924 netxen_check_options(adapter);
925
926 adapter->need_fw_reset = 0;
927
928 /* fall through and release firmware */
929
930err_out:
931 netxen_release_firmware(adapter);
932 return err;
933}
934
935static int
936netxen_nic_request_irq(struct netxen_adapter *adapter)
937{
938 irq_handler_t handler;
939 struct nx_host_sds_ring *sds_ring;
940 int err, ring;
941
942 unsigned long flags = 0;
943 struct net_device *netdev = adapter->netdev;
944 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
945
946 if (adapter->flags & NETXEN_NIC_MSIX_ENABLED)
947 handler = netxen_msix_intr;
948 else if (adapter->flags & NETXEN_NIC_MSI_ENABLED)
949 handler = netxen_msi_intr;
950 else {
951 flags |= IRQF_SHARED;
952 handler = netxen_intr;
953 }
954 adapter->irq = netdev->irq;
955
956 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
957 sds_ring = &recv_ctx->sds_rings[ring];
958 sprintf(sds_ring->name, "%s[%d]", netdev->name, ring);
959 err = request_irq(sds_ring->irq, handler,
960 flags, sds_ring->name, sds_ring);
961 if (err)
962 return err;
963 }
964
965 return 0;
966}
967
968static void
969netxen_nic_free_irq(struct netxen_adapter *adapter)
970{
971 int ring;
972 struct nx_host_sds_ring *sds_ring;
973
974 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
975
976 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
977 sds_ring = &recv_ctx->sds_rings[ring];
978 free_irq(sds_ring->irq, sds_ring);
979 }
980}
981
982static void
983netxen_nic_init_coalesce_defaults(struct netxen_adapter *adapter)
984{
985 adapter->coal.flags = NETXEN_NIC_INTR_DEFAULT;
986 adapter->coal.normal.data.rx_time_us =
987 NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US;
988 adapter->coal.normal.data.rx_packets =
989 NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS;
990 adapter->coal.normal.data.tx_time_us =
991 NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US;
992 adapter->coal.normal.data.tx_packets =
993 NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS;
994}
995
996/* with rtnl_lock */
997static int
998__netxen_nic_up(struct netxen_adapter *adapter, struct net_device *netdev)
999{
1000 int err;
1001
1002 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
1003 return -EIO;
1004
1005 err = adapter->init_port(adapter, adapter->physical_port);
1006 if (err) {
1007 printk(KERN_ERR "%s: Failed to initialize port %d\n",
1008 netxen_nic_driver_name, adapter->portnum);
1009 return err;
1010 }
1011 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1012 adapter->macaddr_set(adapter, adapter->mac_addr);
1013
1014 adapter->set_multi(netdev);
1015 adapter->set_mtu(adapter, netdev->mtu);
1016
1017 adapter->ahw.linkup = 0;
1018
1019 if (adapter->max_sds_rings > 1)
1020 netxen_config_rss(adapter, 1);
1021
1022 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1023 netxen_config_intr_coalesce(adapter);
1024
1025 if (netdev->features & NETIF_F_LRO)
1026 netxen_config_hw_lro(adapter, NETXEN_NIC_LRO_ENABLED);
1027
1028 netxen_napi_enable(adapter);
1029
1030 if (adapter->capabilities & NX_FW_CAPABILITY_LINK_NOTIFICATION)
1031 netxen_linkevent_request(adapter, 1);
1032 else
1033 netxen_nic_set_link_parameters(adapter);
1034
1035 set_bit(__NX_DEV_UP, &adapter->state);
1036 return 0;
1037}
1038
1039/* Usage: During resume and firmware recovery module.*/
1040
1041static inline int
1042netxen_nic_up(struct netxen_adapter *adapter, struct net_device *netdev)
1043{
1044 int err = 0;
1045
1046 rtnl_lock();
1047 if (netif_running(netdev))
1048 err = __netxen_nic_up(adapter, netdev);
1049 rtnl_unlock();
1050
1051 return err;
1052}
1053
1054/* with rtnl_lock */
1055static void
1056__netxen_nic_down(struct netxen_adapter *adapter, struct net_device *netdev)
1057{
1058 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
1059 return;
1060
1061 if (!test_and_clear_bit(__NX_DEV_UP, &adapter->state))
1062 return;
1063
1064 smp_mb();
1065 spin_lock(&adapter->tx_clean_lock);
1066 netif_carrier_off(netdev);
1067 netif_tx_disable(netdev);
1068
1069 if (adapter->capabilities & NX_FW_CAPABILITY_LINK_NOTIFICATION)
1070 netxen_linkevent_request(adapter, 0);
1071
1072 if (adapter->stop_port)
1073 adapter->stop_port(adapter);
1074
1075 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1076 netxen_p3_free_mac_list(adapter);
1077
1078 adapter->set_promisc(adapter, NETXEN_NIU_NON_PROMISC_MODE);
1079
1080 netxen_napi_disable(adapter);
1081
1082 netxen_release_tx_buffers(adapter);
1083 spin_unlock(&adapter->tx_clean_lock);
1084}
1085
1086/* Usage: During suspend and firmware recovery module */
1087
1088static inline void
1089netxen_nic_down(struct netxen_adapter *adapter, struct net_device *netdev)
1090{
1091 rtnl_lock();
1092 if (netif_running(netdev))
1093 __netxen_nic_down(adapter, netdev);
1094 rtnl_unlock();
1095
1096}
1097
1098static int
1099netxen_nic_attach(struct netxen_adapter *adapter)
1100{
1101 struct net_device *netdev = adapter->netdev;
1102 struct pci_dev *pdev = adapter->pdev;
1103 int err, ring;
1104 struct nx_host_rds_ring *rds_ring;
1105 struct nx_host_tx_ring *tx_ring;
1106
1107 if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC)
1108 return 0;
1109
1110 err = netxen_init_firmware(adapter);
1111 if (err)
1112 return err;
1113
1114 err = netxen_napi_add(adapter, netdev);
1115 if (err)
1116 return err;
1117
1118 err = netxen_alloc_sw_resources(adapter);
1119 if (err) {
1120 printk(KERN_ERR "%s: Error in setting sw resources\n",
1121 netdev->name);
1122 return err;
1123 }
1124
1125 err = netxen_alloc_hw_resources(adapter);
1126 if (err) {
1127 printk(KERN_ERR "%s: Error in setting hw resources\n",
1128 netdev->name);
1129 goto err_out_free_sw;
1130 }
1131
1132 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1133 tx_ring = adapter->tx_ring;
1134 tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter,
1135 crb_cmd_producer[adapter->portnum]);
1136 tx_ring->crb_cmd_consumer = netxen_get_ioaddr(adapter,
1137 crb_cmd_consumer[adapter->portnum]);
1138
1139 tx_ring->producer = 0;
1140 tx_ring->sw_consumer = 0;
1141
1142 netxen_nic_update_cmd_producer(adapter, tx_ring);
1143 netxen_nic_update_cmd_consumer(adapter, tx_ring);
1144 }
1145
1146 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1147 rds_ring = &adapter->recv_ctx.rds_rings[ring];
1148 netxen_post_rx_buffers(adapter, ring, rds_ring);
1149 }
1150
1151 err = netxen_nic_request_irq(adapter);
1152 if (err) {
1153 dev_err(&pdev->dev, "%s: failed to setup interrupt\n",
1154 netdev->name);
1155 goto err_out_free_rxbuf;
1156 }
1157
1158 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1159 netxen_nic_init_coalesce_defaults(adapter);
1160
1161 netxen_create_sysfs_entries(adapter);
1162
1163 adapter->is_up = NETXEN_ADAPTER_UP_MAGIC;
1164 return 0;
1165
1166err_out_free_rxbuf:
1167 netxen_release_rx_buffers(adapter);
1168 netxen_free_hw_resources(adapter);
1169err_out_free_sw:
1170 netxen_free_sw_resources(adapter);
1171 return err;
1172}
1173
1174static void
1175netxen_nic_detach(struct netxen_adapter *adapter)
1176{
1177 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
1178 return;
1179
1180 netxen_remove_sysfs_entries(adapter);
1181
1182 netxen_free_hw_resources(adapter);
1183 netxen_release_rx_buffers(adapter);
1184 netxen_nic_free_irq(adapter);
1185 netxen_napi_del(adapter);
1186 netxen_free_sw_resources(adapter);
1187
1188 adapter->is_up = 0;
1189}
1190
1191int
1192netxen_nic_reset_context(struct netxen_adapter *adapter)
1193{
1194 int err = 0;
1195 struct net_device *netdev = adapter->netdev;
1196
1197 if (test_and_set_bit(__NX_RESETTING, &adapter->state))
1198 return -EBUSY;
1199
1200 if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) {
1201
1202 netif_device_detach(netdev);
1203
1204 if (netif_running(netdev))
1205 __netxen_nic_down(adapter, netdev);
1206
1207 netxen_nic_detach(adapter);
1208
1209 if (netif_running(netdev)) {
1210 err = netxen_nic_attach(adapter);
1211 if (!err)
1212 err = __netxen_nic_up(adapter, netdev);
1213
1214 if (err)
1215 goto done;
1216 }
1217
1218 netif_device_attach(netdev);
1219 }
1220
1221done:
1222 clear_bit(__NX_RESETTING, &adapter->state);
1223 return err;
1224}
1225
1226static int
1227netxen_setup_netdev(struct netxen_adapter *adapter,
1228 struct net_device *netdev)
1229{
1230 int err = 0;
1231 struct pci_dev *pdev = adapter->pdev;
1232
1233 adapter->mc_enabled = 0;
1234 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1235 adapter->max_mc_count = 38;
1236 else
1237 adapter->max_mc_count = 16;
1238
1239 netdev->netdev_ops = &netxen_netdev_ops;
1240 netdev->watchdog_timeo = 5*HZ;
1241
1242 netxen_nic_change_mtu(netdev, netdev->mtu);
1243
1244 SET_ETHTOOL_OPS(netdev, &netxen_nic_ethtool_ops);
1245
1246 netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1247 NETIF_F_RXCSUM;
1248
1249 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1250 netdev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
1251
1252 netdev->vlan_features |= netdev->hw_features;
1253
1254 if (adapter->pci_using_dac) {
1255 netdev->features |= NETIF_F_HIGHDMA;
1256 netdev->vlan_features |= NETIF_F_HIGHDMA;
1257 }
1258
1259 if (adapter->capabilities & NX_FW_CAPABILITY_FVLANTX)
1260 netdev->hw_features |= NETIF_F_HW_VLAN_TX;
1261
1262 if (adapter->capabilities & NX_FW_CAPABILITY_HW_LRO)
1263 netdev->hw_features |= NETIF_F_LRO;
1264
1265 netdev->features |= netdev->hw_features;
1266
1267 netdev->irq = adapter->msix_entries[0].vector;
1268
1269 INIT_WORK(&adapter->tx_timeout_task, netxen_tx_timeout_task);
1270
1271 if (netxen_read_mac_addr(adapter))
1272 dev_warn(&pdev->dev, "failed to read mac addr\n");
1273
1274 netif_carrier_off(netdev);
1275
1276 err = register_netdev(netdev);
1277 if (err) {
1278 dev_err(&pdev->dev, "failed to register net device\n");
1279 return err;
1280 }
1281
1282 return 0;
1283}
1284
1285#ifdef CONFIG_PCIEAER
1286static void netxen_mask_aer_correctable(struct netxen_adapter *adapter)
1287{
1288 struct pci_dev *pdev = adapter->pdev;
1289 struct pci_dev *root = pdev->bus->self;
1290 u32 aer_pos;
1291
1292 if (adapter->ahw.board_type != NETXEN_BRDTYPE_P3_4_GB_MM &&
1293 adapter->ahw.board_type != NETXEN_BRDTYPE_P3_10G_TP)
1294 return;
1295
1296 if (root->pcie_type != PCI_EXP_TYPE_ROOT_PORT)
1297 return;
1298
1299 aer_pos = pci_find_ext_capability(root, PCI_EXT_CAP_ID_ERR);
1300 if (!aer_pos)
1301 return;
1302
1303 pci_write_config_dword(root, aer_pos + PCI_ERR_COR_MASK, 0xffff);
1304}
1305#endif
1306
1307static int __devinit
1308netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1309{
1310 struct net_device *netdev = NULL;
1311 struct netxen_adapter *adapter = NULL;
1312 int i = 0, err;
1313 int pci_func_id = PCI_FUNC(pdev->devfn);
1314 uint8_t revision_id;
1315 u32 val;
1316
1317 if (pdev->revision >= NX_P3_A0 && pdev->revision <= NX_P3_B1) {
1318 pr_warning("%s: chip revisions between 0x%x-0x%x "
1319 "will not be enabled.\n",
1320 module_name(THIS_MODULE), NX_P3_A0, NX_P3_B1);
1321 return -ENODEV;
1322 }
1323
1324 if ((err = pci_enable_device(pdev)))
1325 return err;
1326
1327 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1328 err = -ENODEV;
1329 goto err_out_disable_pdev;
1330 }
1331
1332 if ((err = pci_request_regions(pdev, netxen_nic_driver_name)))
1333 goto err_out_disable_pdev;
1334
1335 if (NX_IS_REVISION_P3(pdev->revision))
1336 pci_enable_pcie_error_reporting(pdev);
1337
1338 pci_set_master(pdev);
1339
1340 netdev = alloc_etherdev(sizeof(struct netxen_adapter));
1341 if(!netdev) {
1342 dev_err(&pdev->dev, "failed to allocate net_device\n");
1343 err = -ENOMEM;
1344 goto err_out_free_res;
1345 }
1346
1347 SET_NETDEV_DEV(netdev, &pdev->dev);
1348
1349 adapter = netdev_priv(netdev);
1350 adapter->netdev = netdev;
1351 adapter->pdev = pdev;
1352 adapter->ahw.pci_func = pci_func_id;
1353
1354 revision_id = pdev->revision;
1355 adapter->ahw.revision_id = revision_id;
1356
1357 rwlock_init(&adapter->ahw.crb_lock);
1358 spin_lock_init(&adapter->ahw.mem_lock);
1359
1360 spin_lock_init(&adapter->tx_clean_lock);
1361 INIT_LIST_HEAD(&adapter->mac_list);
1362
1363 err = netxen_setup_pci_map(adapter);
1364 if (err)
1365 goto err_out_free_netdev;
1366
1367 /* This will be reset for mezz cards */
1368 adapter->portnum = pci_func_id;
1369
1370 err = netxen_nic_get_board_info(adapter);
1371 if (err) {
1372 dev_err(&pdev->dev, "Error getting board config info.\n");
1373 goto err_out_iounmap;
1374 }
1375
1376#ifdef CONFIG_PCIEAER
1377 netxen_mask_aer_correctable(adapter);
1378#endif
1379
1380 /* Mezz cards have PCI function 0,2,3 enabled */
1381 switch (adapter->ahw.board_type) {
1382 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1383 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1384 if (pci_func_id >= 2)
1385 adapter->portnum = pci_func_id - 2;
1386 break;
1387 default:
1388 break;
1389 }
1390
1391 err = netxen_check_flash_fw_compatibility(adapter);
1392 if (err)
1393 goto err_out_iounmap;
1394
1395 if (adapter->portnum == 0) {
1396 val = NXRD32(adapter, NX_CRB_DEV_REF_COUNT);
1397 if (val != 0xffffffff && val != 0) {
1398 NXWR32(adapter, NX_CRB_DEV_REF_COUNT, 0);
1399 adapter->need_fw_reset = 1;
1400 }
1401 }
1402
1403 err = netxen_start_firmware(adapter);
1404 if (err)
1405 goto err_out_decr_ref;
1406
1407 /*
1408 * See if the firmware gave us a virtual-physical port mapping.
1409 */
1410 adapter->physical_port = adapter->portnum;
1411 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1412 i = NXRD32(adapter, CRB_V2P(adapter->portnum));
1413 if (i != 0x55555555)
1414 adapter->physical_port = i;
1415 }
1416
1417 netxen_nic_clear_stats(adapter);
1418
1419 netxen_setup_intr(adapter);
1420
1421 err = netxen_setup_netdev(adapter, netdev);
1422 if (err)
1423 goto err_out_disable_msi;
1424
1425 pci_set_drvdata(pdev, adapter);
1426
1427 netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY);
1428
1429 switch (adapter->ahw.port_type) {
1430 case NETXEN_NIC_GBE:
1431 dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n",
1432 adapter->netdev->name);
1433 break;
1434 case NETXEN_NIC_XGBE:
1435 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
1436 adapter->netdev->name);
1437 break;
1438 }
1439
1440 netxen_create_diag_entries(adapter);
1441
1442 return 0;
1443
1444err_out_disable_msi:
1445 netxen_teardown_intr(adapter);
1446
1447 netxen_free_dummy_dma(adapter);
1448
1449err_out_decr_ref:
1450 nx_decr_dev_ref_cnt(adapter);
1451
1452err_out_iounmap:
1453 netxen_cleanup_pci_map(adapter);
1454
1455err_out_free_netdev:
1456 free_netdev(netdev);
1457
1458err_out_free_res:
1459 pci_release_regions(pdev);
1460
1461err_out_disable_pdev:
1462 pci_set_drvdata(pdev, NULL);
1463 pci_disable_device(pdev);
1464 return err;
1465}
1466
1467static void __devexit netxen_nic_remove(struct pci_dev *pdev)
1468{
1469 struct netxen_adapter *adapter;
1470 struct net_device *netdev;
1471
1472 adapter = pci_get_drvdata(pdev);
1473 if (adapter == NULL)
1474 return;
1475
1476 netdev = adapter->netdev;
1477
1478 netxen_cancel_fw_work(adapter);
1479
1480 unregister_netdev(netdev);
1481
1482 cancel_work_sync(&adapter->tx_timeout_task);
1483
1484 netxen_nic_detach(adapter);
1485
1486 nx_decr_dev_ref_cnt(adapter);
1487
1488 if (adapter->portnum == 0)
1489 netxen_free_dummy_dma(adapter);
1490
1491 clear_bit(__NX_RESETTING, &adapter->state);
1492
1493 netxen_teardown_intr(adapter);
1494
1495 netxen_remove_diag_entries(adapter);
1496
1497 netxen_cleanup_pci_map(adapter);
1498
1499 netxen_release_firmware(adapter);
1500
1501 if (NX_IS_REVISION_P3(pdev->revision))
1502 pci_disable_pcie_error_reporting(pdev);
1503
1504 pci_release_regions(pdev);
1505 pci_disable_device(pdev);
1506 pci_set_drvdata(pdev, NULL);
1507
1508 free_netdev(netdev);
1509}
1510
1511static void netxen_nic_detach_func(struct netxen_adapter *adapter)
1512{
1513 struct net_device *netdev = adapter->netdev;
1514
1515 netif_device_detach(netdev);
1516
1517 netxen_cancel_fw_work(adapter);
1518
1519 if (netif_running(netdev))
1520 netxen_nic_down(adapter, netdev);
1521
1522 cancel_work_sync(&adapter->tx_timeout_task);
1523
1524 netxen_nic_detach(adapter);
1525
1526 if (adapter->portnum == 0)
1527 netxen_free_dummy_dma(adapter);
1528
1529 nx_decr_dev_ref_cnt(adapter);
1530
1531 clear_bit(__NX_RESETTING, &adapter->state);
1532}
1533
1534static int netxen_nic_attach_func(struct pci_dev *pdev)
1535{
1536 struct netxen_adapter *adapter = pci_get_drvdata(pdev);
1537 struct net_device *netdev = adapter->netdev;
1538 int err;
1539
1540 err = pci_enable_device(pdev);
1541 if (err)
1542 return err;
1543
1544 pci_set_power_state(pdev, PCI_D0);
1545 pci_set_master(pdev);
1546 pci_restore_state(pdev);
1547
1548 adapter->ahw.crb_win = -1;
1549 adapter->ahw.ocm_win = -1;
1550
1551 err = netxen_start_firmware(adapter);
1552 if (err) {
1553 dev_err(&pdev->dev, "failed to start firmware\n");
1554 return err;
1555 }
1556
1557 if (netif_running(netdev)) {
1558 err = netxen_nic_attach(adapter);
1559 if (err)
1560 goto err_out;
1561
1562 err = netxen_nic_up(adapter, netdev);
1563 if (err)
1564 goto err_out_detach;
1565
1566 netxen_config_indev_addr(netdev, NETDEV_UP);
1567 }
1568
1569 netif_device_attach(netdev);
1570 netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY);
1571 return 0;
1572
1573err_out_detach:
1574 netxen_nic_detach(adapter);
1575err_out:
1576 nx_decr_dev_ref_cnt(adapter);
1577 return err;
1578}
1579
1580static pci_ers_result_t netxen_io_error_detected(struct pci_dev *pdev,
1581 pci_channel_state_t state)
1582{
1583 struct netxen_adapter *adapter = pci_get_drvdata(pdev);
1584
1585 if (state == pci_channel_io_perm_failure)
1586 return PCI_ERS_RESULT_DISCONNECT;
1587
1588 if (nx_dev_request_aer(adapter))
1589 return PCI_ERS_RESULT_RECOVERED;
1590
1591 netxen_nic_detach_func(adapter);
1592
1593 pci_disable_device(pdev);
1594
1595 return PCI_ERS_RESULT_NEED_RESET;
1596}
1597
1598static pci_ers_result_t netxen_io_slot_reset(struct pci_dev *pdev)
1599{
1600 int err = 0;
1601
1602 err = netxen_nic_attach_func(pdev);
1603
1604 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1605}
1606
1607static void netxen_io_resume(struct pci_dev *pdev)
1608{
1609 pci_cleanup_aer_uncorrect_error_status(pdev);
1610}
1611
1612static void netxen_nic_shutdown(struct pci_dev *pdev)
1613{
1614 struct netxen_adapter *adapter = pci_get_drvdata(pdev);
1615
1616 netxen_nic_detach_func(adapter);
1617
1618 if (pci_save_state(pdev))
1619 return;
1620
1621 if (netxen_nic_wol_supported(adapter)) {
1622 pci_enable_wake(pdev, PCI_D3cold, 1);
1623 pci_enable_wake(pdev, PCI_D3hot, 1);
1624 }
1625
1626 pci_disable_device(pdev);
1627}
1628
1629#ifdef CONFIG_PM
1630static int
1631netxen_nic_suspend(struct pci_dev *pdev, pm_message_t state)
1632{
1633 struct netxen_adapter *adapter = pci_get_drvdata(pdev);
1634 int retval;
1635
1636 netxen_nic_detach_func(adapter);
1637
1638 retval = pci_save_state(pdev);
1639 if (retval)
1640 return retval;
1641
1642 if (netxen_nic_wol_supported(adapter)) {
1643 pci_enable_wake(pdev, PCI_D3cold, 1);
1644 pci_enable_wake(pdev, PCI_D3hot, 1);
1645 }
1646
1647 pci_disable_device(pdev);
1648 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1649
1650 return 0;
1651}
1652
1653static int
1654netxen_nic_resume(struct pci_dev *pdev)
1655{
1656 return netxen_nic_attach_func(pdev);
1657}
1658#endif
1659
1660static int netxen_nic_open(struct net_device *netdev)
1661{
1662 struct netxen_adapter *adapter = netdev_priv(netdev);
1663 int err = 0;
1664
1665 if (adapter->driver_mismatch)
1666 return -EIO;
1667
1668 err = netxen_nic_attach(adapter);
1669 if (err)
1670 return err;
1671
1672 err = __netxen_nic_up(adapter, netdev);
1673 if (err)
1674 goto err_out;
1675
1676 netif_start_queue(netdev);
1677
1678 return 0;
1679
1680err_out:
1681 netxen_nic_detach(adapter);
1682 return err;
1683}
1684
1685/*
1686 * netxen_nic_close - Disables a network interface entry point
1687 */
1688static int netxen_nic_close(struct net_device *netdev)
1689{
1690 struct netxen_adapter *adapter = netdev_priv(netdev);
1691
1692 __netxen_nic_down(adapter, netdev);
1693 return 0;
1694}
1695
1696static void
1697netxen_tso_check(struct net_device *netdev,
1698 struct nx_host_tx_ring *tx_ring,
1699 struct cmd_desc_type0 *first_desc,
1700 struct sk_buff *skb)
1701{
1702 u8 opcode = TX_ETHER_PKT;
1703 __be16 protocol = skb->protocol;
1704 u16 flags = 0, vid = 0;
1705 u32 producer;
1706 int copied, offset, copy_len, hdr_len = 0, tso = 0, vlan_oob = 0;
1707 struct cmd_desc_type0 *hwdesc;
1708 struct vlan_ethhdr *vh;
1709
1710 if (protocol == cpu_to_be16(ETH_P_8021Q)) {
1711
1712 vh = (struct vlan_ethhdr *)skb->data;
1713 protocol = vh->h_vlan_encapsulated_proto;
1714 flags = FLAGS_VLAN_TAGGED;
1715
1716 } else if (vlan_tx_tag_present(skb)) {
1717
1718 flags = FLAGS_VLAN_OOB;
1719 vid = vlan_tx_tag_get(skb);
1720 netxen_set_tx_vlan_tci(first_desc, vid);
1721 vlan_oob = 1;
1722 }
1723
1724 if ((netdev->features & (NETIF_F_TSO | NETIF_F_TSO6)) &&
1725 skb_shinfo(skb)->gso_size > 0) {
1726
1727 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1728
1729 first_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1730 first_desc->total_hdr_length = hdr_len;
1731 if (vlan_oob) {
1732 first_desc->total_hdr_length += VLAN_HLEN;
1733 first_desc->tcp_hdr_offset = VLAN_HLEN;
1734 first_desc->ip_hdr_offset = VLAN_HLEN;
1735 /* Only in case of TSO on vlan device */
1736 flags |= FLAGS_VLAN_TAGGED;
1737 }
1738
1739 opcode = (protocol == cpu_to_be16(ETH_P_IPV6)) ?
1740 TX_TCP_LSO6 : TX_TCP_LSO;
1741 tso = 1;
1742
1743 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1744 u8 l4proto;
1745
1746 if (protocol == cpu_to_be16(ETH_P_IP)) {
1747 l4proto = ip_hdr(skb)->protocol;
1748
1749 if (l4proto == IPPROTO_TCP)
1750 opcode = TX_TCP_PKT;
1751 else if(l4proto == IPPROTO_UDP)
1752 opcode = TX_UDP_PKT;
1753 } else if (protocol == cpu_to_be16(ETH_P_IPV6)) {
1754 l4proto = ipv6_hdr(skb)->nexthdr;
1755
1756 if (l4proto == IPPROTO_TCP)
1757 opcode = TX_TCPV6_PKT;
1758 else if(l4proto == IPPROTO_UDP)
1759 opcode = TX_UDPV6_PKT;
1760 }
1761 }
1762
1763 first_desc->tcp_hdr_offset += skb_transport_offset(skb);
1764 first_desc->ip_hdr_offset += skb_network_offset(skb);
1765 netxen_set_tx_flags_opcode(first_desc, flags, opcode);
1766
1767 if (!tso)
1768 return;
1769
1770 /* For LSO, we need to copy the MAC/IP/TCP headers into
1771 * the descriptor ring
1772 */
1773 producer = tx_ring->producer;
1774 copied = 0;
1775 offset = 2;
1776
1777 if (vlan_oob) {
1778 /* Create a TSO vlan header template for firmware */
1779
1780 hwdesc = &tx_ring->desc_head[producer];
1781 tx_ring->cmd_buf_arr[producer].skb = NULL;
1782
1783 copy_len = min((int)sizeof(struct cmd_desc_type0) - offset,
1784 hdr_len + VLAN_HLEN);
1785
1786 vh = (struct vlan_ethhdr *)((char *)hwdesc + 2);
1787 skb_copy_from_linear_data(skb, vh, 12);
1788 vh->h_vlan_proto = htons(ETH_P_8021Q);
1789 vh->h_vlan_TCI = htons(vid);
1790 skb_copy_from_linear_data_offset(skb, 12,
1791 (char *)vh + 16, copy_len - 16);
1792
1793 copied = copy_len - VLAN_HLEN;
1794 offset = 0;
1795
1796 producer = get_next_index(producer, tx_ring->num_desc);
1797 }
1798
1799 while (copied < hdr_len) {
1800
1801 copy_len = min((int)sizeof(struct cmd_desc_type0) - offset,
1802 (hdr_len - copied));
1803
1804 hwdesc = &tx_ring->desc_head[producer];
1805 tx_ring->cmd_buf_arr[producer].skb = NULL;
1806
1807 skb_copy_from_linear_data_offset(skb, copied,
1808 (char *)hwdesc + offset, copy_len);
1809
1810 copied += copy_len;
1811 offset = 0;
1812
1813 producer = get_next_index(producer, tx_ring->num_desc);
1814 }
1815
1816 tx_ring->producer = producer;
1817 barrier();
1818}
1819
1820static int
1821netxen_map_tx_skb(struct pci_dev *pdev,
1822 struct sk_buff *skb, struct netxen_cmd_buffer *pbuf)
1823{
1824 struct netxen_skb_frag *nf;
1825 struct skb_frag_struct *frag;
1826 int i, nr_frags;
1827 dma_addr_t map;
1828
1829 nr_frags = skb_shinfo(skb)->nr_frags;
1830 nf = &pbuf->frag_array[0];
1831
1832 map = pci_map_single(pdev, skb->data,
1833 skb_headlen(skb), PCI_DMA_TODEVICE);
1834 if (pci_dma_mapping_error(pdev, map))
1835 goto out_err;
1836
1837 nf->dma = map;
1838 nf->length = skb_headlen(skb);
1839
1840 for (i = 0; i < nr_frags; i++) {
1841 frag = &skb_shinfo(skb)->frags[i];
1842 nf = &pbuf->frag_array[i+1];
1843
1844 map = pci_map_page(pdev, frag->page, frag->page_offset,
1845 frag->size, PCI_DMA_TODEVICE);
1846 if (pci_dma_mapping_error(pdev, map))
1847 goto unwind;
1848
1849 nf->dma = map;
1850 nf->length = frag->size;
1851 }
1852
1853 return 0;
1854
1855unwind:
1856 while (--i >= 0) {
1857 nf = &pbuf->frag_array[i+1];
1858 pci_unmap_page(pdev, nf->dma, nf->length, PCI_DMA_TODEVICE);
1859 }
1860
1861 nf = &pbuf->frag_array[0];
1862 pci_unmap_single(pdev, nf->dma, skb_headlen(skb), PCI_DMA_TODEVICE);
1863
1864out_err:
1865 return -ENOMEM;
1866}
1867
1868static inline void
1869netxen_clear_cmddesc(u64 *desc)
1870{
1871 desc[0] = 0ULL;
1872 desc[2] = 0ULL;
1873}
1874
1875static netdev_tx_t
1876netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1877{
1878 struct netxen_adapter *adapter = netdev_priv(netdev);
1879 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
1880 struct netxen_cmd_buffer *pbuf;
1881 struct netxen_skb_frag *buffrag;
1882 struct cmd_desc_type0 *hwdesc, *first_desc;
1883 struct pci_dev *pdev;
1884 int i, k;
1885 int delta = 0;
1886 struct skb_frag_struct *frag;
1887
1888 u32 producer;
1889 int frag_count, no_of_desc;
1890 u32 num_txd = tx_ring->num_desc;
1891
1892 frag_count = skb_shinfo(skb)->nr_frags + 1;
1893
1894 /* 14 frags supported for normal packet and
1895 * 32 frags supported for TSO packet
1896 */
1897 if (!skb_is_gso(skb) && frag_count > NETXEN_MAX_FRAGS_PER_TX) {
1898
1899 for (i = 0; i < (frag_count - NETXEN_MAX_FRAGS_PER_TX); i++) {
1900 frag = &skb_shinfo(skb)->frags[i];
1901 delta += frag->size;
1902 }
1903
1904 if (!__pskb_pull_tail(skb, delta))
1905 goto drop_packet;
1906
1907 frag_count = 1 + skb_shinfo(skb)->nr_frags;
1908 }
1909 /* 4 fragments per cmd des */
1910 no_of_desc = (frag_count + 3) >> 2;
1911
1912 if (unlikely(netxen_tx_avail(tx_ring) <= TX_STOP_THRESH)) {
1913 netif_stop_queue(netdev);
1914 smp_mb();
1915 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
1916 netif_start_queue(netdev);
1917 else
1918 return NETDEV_TX_BUSY;
1919 }
1920
1921 producer = tx_ring->producer;
1922 pbuf = &tx_ring->cmd_buf_arr[producer];
1923
1924 pdev = adapter->pdev;
1925
1926 if (netxen_map_tx_skb(pdev, skb, pbuf))
1927 goto drop_packet;
1928
1929 pbuf->skb = skb;
1930 pbuf->frag_count = frag_count;
1931
1932 first_desc = hwdesc = &tx_ring->desc_head[producer];
1933 netxen_clear_cmddesc((u64 *)hwdesc);
1934
1935 netxen_set_tx_frags_len(first_desc, frag_count, skb->len);
1936 netxen_set_tx_port(first_desc, adapter->portnum);
1937
1938 for (i = 0; i < frag_count; i++) {
1939
1940 k = i % 4;
1941
1942 if ((k == 0) && (i > 0)) {
1943 /* move to next desc.*/
1944 producer = get_next_index(producer, num_txd);
1945 hwdesc = &tx_ring->desc_head[producer];
1946 netxen_clear_cmddesc((u64 *)hwdesc);
1947 tx_ring->cmd_buf_arr[producer].skb = NULL;
1948 }
1949
1950 buffrag = &pbuf->frag_array[i];
1951
1952 hwdesc->buffer_length[k] = cpu_to_le16(buffrag->length);
1953 switch (k) {
1954 case 0:
1955 hwdesc->addr_buffer1 = cpu_to_le64(buffrag->dma);
1956 break;
1957 case 1:
1958 hwdesc->addr_buffer2 = cpu_to_le64(buffrag->dma);
1959 break;
1960 case 2:
1961 hwdesc->addr_buffer3 = cpu_to_le64(buffrag->dma);
1962 break;
1963 case 3:
1964 hwdesc->addr_buffer4 = cpu_to_le64(buffrag->dma);
1965 break;
1966 }
1967 }
1968
1969 tx_ring->producer = get_next_index(producer, num_txd);
1970
1971 netxen_tso_check(netdev, tx_ring, first_desc, skb);
1972
1973 adapter->stats.txbytes += skb->len;
1974 adapter->stats.xmitcalled++;
1975
1976 netxen_nic_update_cmd_producer(adapter, tx_ring);
1977
1978 return NETDEV_TX_OK;
1979
1980drop_packet:
1981 adapter->stats.txdropped++;
1982 dev_kfree_skb_any(skb);
1983 return NETDEV_TX_OK;
1984}
1985
1986static int netxen_nic_check_temp(struct netxen_adapter *adapter)
1987{
1988 struct net_device *netdev = adapter->netdev;
1989 uint32_t temp, temp_state, temp_val;
1990 int rv = 0;
1991
1992 temp = NXRD32(adapter, CRB_TEMP_STATE);
1993
1994 temp_state = nx_get_temp_state(temp);
1995 temp_val = nx_get_temp_val(temp);
1996
1997 if (temp_state == NX_TEMP_PANIC) {
1998 printk(KERN_ALERT
1999 "%s: Device temperature %d degrees C exceeds"
2000 " maximum allowed. Hardware has been shut down.\n",
2001 netdev->name, temp_val);
2002 rv = 1;
2003 } else if (temp_state == NX_TEMP_WARN) {
2004 if (adapter->temp == NX_TEMP_NORMAL) {
2005 printk(KERN_ALERT
2006 "%s: Device temperature %d degrees C "
2007 "exceeds operating range."
2008 " Immediate action needed.\n",
2009 netdev->name, temp_val);
2010 }
2011 } else {
2012 if (adapter->temp == NX_TEMP_WARN) {
2013 printk(KERN_INFO
2014 "%s: Device temperature is now %d degrees C"
2015 " in normal range.\n", netdev->name,
2016 temp_val);
2017 }
2018 }
2019 adapter->temp = temp_state;
2020 return rv;
2021}
2022
2023void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup)
2024{
2025 struct net_device *netdev = adapter->netdev;
2026
2027 if (adapter->ahw.linkup && !linkup) {
2028 printk(KERN_INFO "%s: %s NIC Link is down\n",
2029 netxen_nic_driver_name, netdev->name);
2030 adapter->ahw.linkup = 0;
2031 if (netif_running(netdev)) {
2032 netif_carrier_off(netdev);
2033 netif_stop_queue(netdev);
2034 }
2035 adapter->link_changed = !adapter->has_link_events;
2036 } else if (!adapter->ahw.linkup && linkup) {
2037 printk(KERN_INFO "%s: %s NIC Link is up\n",
2038 netxen_nic_driver_name, netdev->name);
2039 adapter->ahw.linkup = 1;
2040 if (netif_running(netdev)) {
2041 netif_carrier_on(netdev);
2042 netif_wake_queue(netdev);
2043 }
2044 adapter->link_changed = !adapter->has_link_events;
2045 }
2046}
2047
2048static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter)
2049{
2050 u32 val, port, linkup;
2051
2052 port = adapter->physical_port;
2053
2054 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2055 val = NXRD32(adapter, CRB_XG_STATE_P3);
2056 val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val);
2057 linkup = (val == XG_LINK_UP_P3);
2058 } else {
2059 val = NXRD32(adapter, CRB_XG_STATE);
2060 val = (val >> port*8) & 0xff;
2061 linkup = (val == XG_LINK_UP);
2062 }
2063
2064 netxen_advert_link_change(adapter, linkup);
2065}
2066
2067static void netxen_tx_timeout(struct net_device *netdev)
2068{
2069 struct netxen_adapter *adapter = netdev_priv(netdev);
2070
2071 if (test_bit(__NX_RESETTING, &adapter->state))
2072 return;
2073
2074 dev_err(&netdev->dev, "transmit timeout, resetting.\n");
2075 schedule_work(&adapter->tx_timeout_task);
2076}
2077
2078static void netxen_tx_timeout_task(struct work_struct *work)
2079{
2080 struct netxen_adapter *adapter =
2081 container_of(work, struct netxen_adapter, tx_timeout_task);
2082
2083 if (!netif_running(adapter->netdev))
2084 return;
2085
2086 if (test_and_set_bit(__NX_RESETTING, &adapter->state))
2087 return;
2088
2089 if (++adapter->tx_timeo_cnt >= NX_MAX_TX_TIMEOUTS)
2090 goto request_reset;
2091
2092 rtnl_lock();
2093 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
2094 /* try to scrub interrupt */
2095 netxen_napi_disable(adapter);
2096
2097 netxen_napi_enable(adapter);
2098
2099 netif_wake_queue(adapter->netdev);
2100
2101 clear_bit(__NX_RESETTING, &adapter->state);
2102 } else {
2103 clear_bit(__NX_RESETTING, &adapter->state);
2104 if (netxen_nic_reset_context(adapter)) {
2105 rtnl_unlock();
2106 goto request_reset;
2107 }
2108 }
2109 adapter->netdev->trans_start = jiffies;
2110 rtnl_unlock();
2111 return;
2112
2113request_reset:
2114 adapter->need_fw_reset = 1;
2115 clear_bit(__NX_RESETTING, &adapter->state);
2116}
2117
2118static struct rtnl_link_stats64 *netxen_nic_get_stats(struct net_device *netdev,
2119 struct rtnl_link_stats64 *stats)
2120{
2121 struct netxen_adapter *adapter = netdev_priv(netdev);
2122
2123 stats->rx_packets = adapter->stats.rx_pkts + adapter->stats.lro_pkts;
2124 stats->tx_packets = adapter->stats.xmitfinished;
2125 stats->rx_bytes = adapter->stats.rxbytes;
2126 stats->tx_bytes = adapter->stats.txbytes;
2127 stats->rx_dropped = adapter->stats.rxdropped;
2128 stats->tx_dropped = adapter->stats.txdropped;
2129
2130 return stats;
2131}
2132
2133static irqreturn_t netxen_intr(int irq, void *data)
2134{
2135 struct nx_host_sds_ring *sds_ring = data;
2136 struct netxen_adapter *adapter = sds_ring->adapter;
2137 u32 status = 0;
2138
2139 status = readl(adapter->isr_int_vec);
2140
2141 if (!(status & adapter->int_vec_bit))
2142 return IRQ_NONE;
2143
2144 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2145 /* check interrupt state machine, to be sure */
2146 status = readl(adapter->crb_int_state_reg);
2147 if (!ISR_LEGACY_INT_TRIGGERED(status))
2148 return IRQ_NONE;
2149
2150 } else {
2151 unsigned long our_int = 0;
2152
2153 our_int = readl(adapter->crb_int_state_reg);
2154
2155 /* not our interrupt */
2156 if (!test_and_clear_bit((7 + adapter->portnum), &our_int))
2157 return IRQ_NONE;
2158
2159 /* claim interrupt */
2160 writel((our_int & 0xffffffff), adapter->crb_int_state_reg);
2161
2162 /* clear interrupt */
2163 netxen_nic_disable_int(sds_ring);
2164 }
2165
2166 writel(0xffffffff, adapter->tgt_status_reg);
2167 /* read twice to ensure write is flushed */
2168 readl(adapter->isr_int_vec);
2169 readl(adapter->isr_int_vec);
2170
2171 napi_schedule(&sds_ring->napi);
2172
2173 return IRQ_HANDLED;
2174}
2175
2176static irqreturn_t netxen_msi_intr(int irq, void *data)
2177{
2178 struct nx_host_sds_ring *sds_ring = data;
2179 struct netxen_adapter *adapter = sds_ring->adapter;
2180
2181 /* clear interrupt */
2182 writel(0xffffffff, adapter->tgt_status_reg);
2183
2184 napi_schedule(&sds_ring->napi);
2185 return IRQ_HANDLED;
2186}
2187
2188static irqreturn_t netxen_msix_intr(int irq, void *data)
2189{
2190 struct nx_host_sds_ring *sds_ring = data;
2191
2192 napi_schedule(&sds_ring->napi);
2193 return IRQ_HANDLED;
2194}
2195
2196static int netxen_nic_poll(struct napi_struct *napi, int budget)
2197{
2198 struct nx_host_sds_ring *sds_ring =
2199 container_of(napi, struct nx_host_sds_ring, napi);
2200
2201 struct netxen_adapter *adapter = sds_ring->adapter;
2202
2203 int tx_complete;
2204 int work_done;
2205
2206 tx_complete = netxen_process_cmd_ring(adapter);
2207
2208 work_done = netxen_process_rcv_ring(sds_ring, budget);
2209
2210 if ((work_done < budget) && tx_complete) {
2211 napi_complete(&sds_ring->napi);
2212 if (test_bit(__NX_DEV_UP, &adapter->state))
2213 netxen_nic_enable_int(sds_ring);
2214 }
2215
2216 return work_done;
2217}
2218
2219#ifdef CONFIG_NET_POLL_CONTROLLER
2220static void netxen_nic_poll_controller(struct net_device *netdev)
2221{
2222 int ring;
2223 struct nx_host_sds_ring *sds_ring;
2224 struct netxen_adapter *adapter = netdev_priv(netdev);
2225 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
2226
2227 disable_irq(adapter->irq);
2228 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
2229 sds_ring = &recv_ctx->sds_rings[ring];
2230 netxen_intr(adapter->irq, sds_ring);
2231 }
2232 enable_irq(adapter->irq);
2233}
2234#endif
2235
2236static int
2237nx_incr_dev_ref_cnt(struct netxen_adapter *adapter)
2238{
2239 int count;
2240 if (netxen_api_lock(adapter))
2241 return -EIO;
2242
2243 count = NXRD32(adapter, NX_CRB_DEV_REF_COUNT);
2244
2245 NXWR32(adapter, NX_CRB_DEV_REF_COUNT, ++count);
2246
2247 netxen_api_unlock(adapter);
2248 return count;
2249}
2250
2251static int
2252nx_decr_dev_ref_cnt(struct netxen_adapter *adapter)
2253{
2254 int count;
2255 if (netxen_api_lock(adapter))
2256 return -EIO;
2257
2258 count = NXRD32(adapter, NX_CRB_DEV_REF_COUNT);
2259 WARN_ON(count == 0);
2260
2261 NXWR32(adapter, NX_CRB_DEV_REF_COUNT, --count);
2262
2263 if (count == 0)
2264 NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_COLD);
2265
2266 netxen_api_unlock(adapter);
2267 return count;
2268}
2269
2270static int
2271nx_dev_request_aer(struct netxen_adapter *adapter)
2272{
2273 u32 state;
2274 int ret = -EINVAL;
2275
2276 if (netxen_api_lock(adapter))
2277 return ret;
2278
2279 state = NXRD32(adapter, NX_CRB_DEV_STATE);
2280
2281 if (state == NX_DEV_NEED_AER)
2282 ret = 0;
2283 else if (state == NX_DEV_READY) {
2284 NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_NEED_AER);
2285 ret = 0;
2286 }
2287
2288 netxen_api_unlock(adapter);
2289 return ret;
2290}
2291
2292static int
2293nx_dev_request_reset(struct netxen_adapter *adapter)
2294{
2295 u32 state;
2296 int ret = -EINVAL;
2297
2298 if (netxen_api_lock(adapter))
2299 return ret;
2300
2301 state = NXRD32(adapter, NX_CRB_DEV_STATE);
2302
2303 if (state == NX_DEV_NEED_RESET)
2304 ret = 0;
2305 else if (state != NX_DEV_INITALIZING && state != NX_DEV_NEED_AER) {
2306 NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_NEED_RESET);
2307 ret = 0;
2308 }
2309
2310 netxen_api_unlock(adapter);
2311
2312 return ret;
2313}
2314
2315static int
2316netxen_can_start_firmware(struct netxen_adapter *adapter)
2317{
2318 int count;
2319 int can_start = 0;
2320
2321 if (netxen_api_lock(adapter))
2322 return 0;
2323
2324 count = NXRD32(adapter, NX_CRB_DEV_REF_COUNT);
2325
2326 if ((count < 0) || (count >= NX_MAX_PCI_FUNC))
2327 count = 0;
2328
2329 if (count == 0) {
2330 can_start = 1;
2331 NXWR32(adapter, NX_CRB_DEV_STATE, NX_DEV_INITALIZING);
2332 }
2333
2334 NXWR32(adapter, NX_CRB_DEV_REF_COUNT, ++count);
2335
2336 netxen_api_unlock(adapter);
2337
2338 return can_start;
2339}
2340
2341static void
2342netxen_schedule_work(struct netxen_adapter *adapter,
2343 work_func_t func, int delay)
2344{
2345 INIT_DELAYED_WORK(&adapter->fw_work, func);
2346 schedule_delayed_work(&adapter->fw_work, delay);
2347}
2348
2349static void
2350netxen_cancel_fw_work(struct netxen_adapter *adapter)
2351{
2352 while (test_and_set_bit(__NX_RESETTING, &adapter->state))
2353 msleep(10);
2354
2355 cancel_delayed_work_sync(&adapter->fw_work);
2356}
2357
2358static void
2359netxen_attach_work(struct work_struct *work)
2360{
2361 struct netxen_adapter *adapter = container_of(work,
2362 struct netxen_adapter, fw_work.work);
2363 struct net_device *netdev = adapter->netdev;
2364 int err = 0;
2365
2366 if (netif_running(netdev)) {
2367 err = netxen_nic_attach(adapter);
2368 if (err)
2369 goto done;
2370
2371 err = netxen_nic_up(adapter, netdev);
2372 if (err) {
2373 netxen_nic_detach(adapter);
2374 goto done;
2375 }
2376
2377 netxen_config_indev_addr(netdev, NETDEV_UP);
2378 }
2379
2380 netif_device_attach(netdev);
2381
2382done:
2383 adapter->fw_fail_cnt = 0;
2384 clear_bit(__NX_RESETTING, &adapter->state);
2385 netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY);
2386}
2387
2388static void
2389netxen_fwinit_work(struct work_struct *work)
2390{
2391 struct netxen_adapter *adapter = container_of(work,
2392 struct netxen_adapter, fw_work.work);
2393 int dev_state;
2394
2395 dev_state = NXRD32(adapter, NX_CRB_DEV_STATE);
2396
2397 switch (dev_state) {
2398 case NX_DEV_COLD:
2399 case NX_DEV_READY:
2400 if (!netxen_start_firmware(adapter)) {
2401 netxen_schedule_work(adapter, netxen_attach_work, 0);
2402 return;
2403 }
2404 break;
2405
2406 case NX_DEV_NEED_RESET:
2407 case NX_DEV_INITALIZING:
2408 if (++adapter->fw_wait_cnt < FW_POLL_THRESH) {
2409 netxen_schedule_work(adapter,
2410 netxen_fwinit_work, 2 * FW_POLL_DELAY);
2411 return;
2412 }
2413
2414 case NX_DEV_FAILED:
2415 default:
2416 nx_incr_dev_ref_cnt(adapter);
2417 break;
2418 }
2419
2420 clear_bit(__NX_RESETTING, &adapter->state);
2421}
2422
2423static void
2424netxen_detach_work(struct work_struct *work)
2425{
2426 struct netxen_adapter *adapter = container_of(work,
2427 struct netxen_adapter, fw_work.work);
2428 struct net_device *netdev = adapter->netdev;
2429 int ref_cnt, delay;
2430 u32 status;
2431
2432 netif_device_detach(netdev);
2433
2434 netxen_nic_down(adapter, netdev);
2435
2436 rtnl_lock();
2437 netxen_nic_detach(adapter);
2438 rtnl_unlock();
2439
2440 status = NXRD32(adapter, NETXEN_PEG_HALT_STATUS1);
2441
2442 if (status & NX_RCODE_FATAL_ERROR)
2443 goto err_ret;
2444
2445 if (adapter->temp == NX_TEMP_PANIC)
2446 goto err_ret;
2447
2448 ref_cnt = nx_decr_dev_ref_cnt(adapter);
2449
2450 if (ref_cnt == -EIO)
2451 goto err_ret;
2452
2453 delay = (ref_cnt == 0) ? 0 : (2 * FW_POLL_DELAY);
2454
2455 adapter->fw_wait_cnt = 0;
2456 netxen_schedule_work(adapter, netxen_fwinit_work, delay);
2457
2458 return;
2459
2460err_ret:
2461 clear_bit(__NX_RESETTING, &adapter->state);
2462}
2463
2464static int
2465netxen_check_health(struct netxen_adapter *adapter)
2466{
2467 u32 state, heartbit;
2468 struct net_device *netdev = adapter->netdev;
2469
2470 state = NXRD32(adapter, NX_CRB_DEV_STATE);
2471 if (state == NX_DEV_NEED_AER)
2472 return 0;
2473
2474 if (netxen_nic_check_temp(adapter))
2475 goto detach;
2476
2477 if (adapter->need_fw_reset) {
2478 if (nx_dev_request_reset(adapter))
2479 return 0;
2480 goto detach;
2481 }
2482
2483 /* NX_DEV_NEED_RESET, this state can be marked in two cases
2484 * 1. Tx timeout 2. Fw hang
2485 * Send request to destroy context in case of tx timeout only
2486 * and doesn't required in case of Fw hang
2487 */
2488 if (state == NX_DEV_NEED_RESET) {
2489 adapter->need_fw_reset = 1;
2490 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2491 goto detach;
2492 }
2493
2494 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2495 return 0;
2496
2497 heartbit = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
2498 if (heartbit != adapter->heartbit) {
2499 adapter->heartbit = heartbit;
2500 adapter->fw_fail_cnt = 0;
2501 if (adapter->need_fw_reset)
2502 goto detach;
2503 return 0;
2504 }
2505
2506 if (++adapter->fw_fail_cnt < FW_FAIL_THRESH)
2507 return 0;
2508
2509 if (nx_dev_request_reset(adapter))
2510 return 0;
2511
2512 clear_bit(__NX_FW_ATTACHED, &adapter->state);
2513
2514 dev_info(&netdev->dev, "firmware hang detected\n");
2515
2516detach:
2517 if ((auto_fw_reset == AUTO_FW_RESET_ENABLED) &&
2518 !test_and_set_bit(__NX_RESETTING, &adapter->state))
2519 netxen_schedule_work(adapter, netxen_detach_work, 0);
2520 return 1;
2521}
2522
2523static void
2524netxen_fw_poll_work(struct work_struct *work)
2525{
2526 struct netxen_adapter *adapter = container_of(work,
2527 struct netxen_adapter, fw_work.work);
2528
2529 if (test_bit(__NX_RESETTING, &adapter->state))
2530 goto reschedule;
2531
2532 if (test_bit(__NX_DEV_UP, &adapter->state)) {
2533 if (!adapter->has_link_events) {
2534
2535 netxen_nic_handle_phy_intr(adapter);
2536
2537 if (adapter->link_changed)
2538 netxen_nic_set_link_parameters(adapter);
2539 }
2540 }
2541
2542 if (netxen_check_health(adapter))
2543 return;
2544
2545reschedule:
2546 netxen_schedule_work(adapter, netxen_fw_poll_work, FW_POLL_DELAY);
2547}
2548
2549static ssize_t
2550netxen_store_bridged_mode(struct device *dev,
2551 struct device_attribute *attr, const char *buf, size_t len)
2552{
2553 struct net_device *net = to_net_dev(dev);
2554 struct netxen_adapter *adapter = netdev_priv(net);
2555 unsigned long new;
2556 int ret = -EINVAL;
2557
2558 if (!(adapter->capabilities & NX_FW_CAPABILITY_BDG))
2559 goto err_out;
2560
2561 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
2562 goto err_out;
2563
2564 if (strict_strtoul(buf, 2, &new))
2565 goto err_out;
2566
2567 if (!netxen_config_bridged_mode(adapter, !!new))
2568 ret = len;
2569
2570err_out:
2571 return ret;
2572}
2573
2574static ssize_t
2575netxen_show_bridged_mode(struct device *dev,
2576 struct device_attribute *attr, char *buf)
2577{
2578 struct net_device *net = to_net_dev(dev);
2579 struct netxen_adapter *adapter;
2580 int bridged_mode = 0;
2581
2582 adapter = netdev_priv(net);
2583
2584 if (adapter->capabilities & NX_FW_CAPABILITY_BDG)
2585 bridged_mode = !!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED);
2586
2587 return sprintf(buf, "%d\n", bridged_mode);
2588}
2589
2590static struct device_attribute dev_attr_bridged_mode = {
2591 .attr = {.name = "bridged_mode", .mode = (S_IRUGO | S_IWUSR)},
2592 .show = netxen_show_bridged_mode,
2593 .store = netxen_store_bridged_mode,
2594};
2595
2596static ssize_t
2597netxen_store_diag_mode(struct device *dev,
2598 struct device_attribute *attr, const char *buf, size_t len)
2599{
2600 struct netxen_adapter *adapter = dev_get_drvdata(dev);
2601 unsigned long new;
2602
2603 if (strict_strtoul(buf, 2, &new))
2604 return -EINVAL;
2605
2606 if (!!new != !!(adapter->flags & NETXEN_NIC_DIAG_ENABLED))
2607 adapter->flags ^= NETXEN_NIC_DIAG_ENABLED;
2608
2609 return len;
2610}
2611
2612static ssize_t
2613netxen_show_diag_mode(struct device *dev,
2614 struct device_attribute *attr, char *buf)
2615{
2616 struct netxen_adapter *adapter = dev_get_drvdata(dev);
2617
2618 return sprintf(buf, "%d\n",
2619 !!(adapter->flags & NETXEN_NIC_DIAG_ENABLED));
2620}
2621
2622static struct device_attribute dev_attr_diag_mode = {
2623 .attr = {.name = "diag_mode", .mode = (S_IRUGO | S_IWUSR)},
2624 .show = netxen_show_diag_mode,
2625 .store = netxen_store_diag_mode,
2626};
2627
2628static int
2629netxen_sysfs_validate_crb(struct netxen_adapter *adapter,
2630 loff_t offset, size_t size)
2631{
2632 size_t crb_size = 4;
2633
2634 if (!(adapter->flags & NETXEN_NIC_DIAG_ENABLED))
2635 return -EIO;
2636
2637 if (offset < NETXEN_PCI_CRBSPACE) {
2638 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2639 return -EINVAL;
2640
2641 if (ADDR_IN_RANGE(offset, NETXEN_PCI_CAMQM,
2642 NETXEN_PCI_CAMQM_2M_END))
2643 crb_size = 8;
2644 else
2645 return -EINVAL;
2646 }
2647
2648 if ((size != crb_size) || (offset & (crb_size-1)))
2649 return -EINVAL;
2650
2651 return 0;
2652}
2653
2654static ssize_t
2655netxen_sysfs_read_crb(struct file *filp, struct kobject *kobj,
2656 struct bin_attribute *attr,
2657 char *buf, loff_t offset, size_t size)
2658{
2659 struct device *dev = container_of(kobj, struct device, kobj);
2660 struct netxen_adapter *adapter = dev_get_drvdata(dev);
2661 u32 data;
2662 u64 qmdata;
2663 int ret;
2664
2665 ret = netxen_sysfs_validate_crb(adapter, offset, size);
2666 if (ret != 0)
2667 return ret;
2668
2669 if (NX_IS_REVISION_P3(adapter->ahw.revision_id) &&
2670 ADDR_IN_RANGE(offset, NETXEN_PCI_CAMQM,
2671 NETXEN_PCI_CAMQM_2M_END)) {
2672 netxen_pci_camqm_read_2M(adapter, offset, &qmdata);
2673 memcpy(buf, &qmdata, size);
2674 } else {
2675 data = NXRD32(adapter, offset);
2676 memcpy(buf, &data, size);
2677 }
2678
2679 return size;
2680}
2681
2682static ssize_t
2683netxen_sysfs_write_crb(struct file *filp, struct kobject *kobj,
2684 struct bin_attribute *attr,
2685 char *buf, loff_t offset, size_t size)
2686{
2687 struct device *dev = container_of(kobj, struct device, kobj);
2688 struct netxen_adapter *adapter = dev_get_drvdata(dev);
2689 u32 data;
2690 u64 qmdata;
2691 int ret;
2692
2693 ret = netxen_sysfs_validate_crb(adapter, offset, size);
2694 if (ret != 0)
2695 return ret;
2696
2697 if (NX_IS_REVISION_P3(adapter->ahw.revision_id) &&
2698 ADDR_IN_RANGE(offset, NETXEN_PCI_CAMQM,
2699 NETXEN_PCI_CAMQM_2M_END)) {
2700 memcpy(&qmdata, buf, size);
2701 netxen_pci_camqm_write_2M(adapter, offset, qmdata);
2702 } else {
2703 memcpy(&data, buf, size);
2704 NXWR32(adapter, offset, data);
2705 }
2706
2707 return size;
2708}
2709
2710static int
2711netxen_sysfs_validate_mem(struct netxen_adapter *adapter,
2712 loff_t offset, size_t size)
2713{
2714 if (!(adapter->flags & NETXEN_NIC_DIAG_ENABLED))
2715 return -EIO;
2716
2717 if ((size != 8) || (offset & 0x7))
2718 return -EIO;
2719
2720 return 0;
2721}
2722
2723static ssize_t
2724netxen_sysfs_read_mem(struct file *filp, struct kobject *kobj,
2725 struct bin_attribute *attr,
2726 char *buf, loff_t offset, size_t size)
2727{
2728 struct device *dev = container_of(kobj, struct device, kobj);
2729 struct netxen_adapter *adapter = dev_get_drvdata(dev);
2730 u64 data;
2731 int ret;
2732
2733 ret = netxen_sysfs_validate_mem(adapter, offset, size);
2734 if (ret != 0)
2735 return ret;
2736
2737 if (adapter->pci_mem_read(adapter, offset, &data))
2738 return -EIO;
2739
2740 memcpy(buf, &data, size);
2741
2742 return size;
2743}
2744
2745static ssize_t netxen_sysfs_write_mem(struct file *filp, struct kobject *kobj,
2746 struct bin_attribute *attr, char *buf,
2747 loff_t offset, size_t size)
2748{
2749 struct device *dev = container_of(kobj, struct device, kobj);
2750 struct netxen_adapter *adapter = dev_get_drvdata(dev);
2751 u64 data;
2752 int ret;
2753
2754 ret = netxen_sysfs_validate_mem(adapter, offset, size);
2755 if (ret != 0)
2756 return ret;
2757
2758 memcpy(&data, buf, size);
2759
2760 if (adapter->pci_mem_write(adapter, offset, data))
2761 return -EIO;
2762
2763 return size;
2764}
2765
2766
2767static struct bin_attribute bin_attr_crb = {
2768 .attr = {.name = "crb", .mode = (S_IRUGO | S_IWUSR)},
2769 .size = 0,
2770 .read = netxen_sysfs_read_crb,
2771 .write = netxen_sysfs_write_crb,
2772};
2773
2774static struct bin_attribute bin_attr_mem = {
2775 .attr = {.name = "mem", .mode = (S_IRUGO | S_IWUSR)},
2776 .size = 0,
2777 .read = netxen_sysfs_read_mem,
2778 .write = netxen_sysfs_write_mem,
2779};
2780
2781
2782static void
2783netxen_create_sysfs_entries(struct netxen_adapter *adapter)
2784{
2785 struct net_device *netdev = adapter->netdev;
2786 struct device *dev = &netdev->dev;
2787
2788 if (adapter->capabilities & NX_FW_CAPABILITY_BDG) {
2789 /* bridged_mode control */
2790 if (device_create_file(dev, &dev_attr_bridged_mode)) {
2791 dev_warn(&netdev->dev,
2792 "failed to create bridged_mode sysfs entry\n");
2793 }
2794 }
2795}
2796
2797static void
2798netxen_remove_sysfs_entries(struct netxen_adapter *adapter)
2799{
2800 struct net_device *netdev = adapter->netdev;
2801 struct device *dev = &netdev->dev;
2802
2803 if (adapter->capabilities & NX_FW_CAPABILITY_BDG)
2804 device_remove_file(dev, &dev_attr_bridged_mode);
2805}
2806
2807static void
2808netxen_create_diag_entries(struct netxen_adapter *adapter)
2809{
2810 struct pci_dev *pdev = adapter->pdev;
2811 struct device *dev;
2812
2813 dev = &pdev->dev;
2814 if (device_create_file(dev, &dev_attr_diag_mode))
2815 dev_info(dev, "failed to create diag_mode sysfs entry\n");
2816 if (device_create_bin_file(dev, &bin_attr_crb))
2817 dev_info(dev, "failed to create crb sysfs entry\n");
2818 if (device_create_bin_file(dev, &bin_attr_mem))
2819 dev_info(dev, "failed to create mem sysfs entry\n");
2820}
2821
2822
2823static void
2824netxen_remove_diag_entries(struct netxen_adapter *adapter)
2825{
2826 struct pci_dev *pdev = adapter->pdev;
2827 struct device *dev = &pdev->dev;
2828
2829 device_remove_file(dev, &dev_attr_diag_mode);
2830 device_remove_bin_file(dev, &bin_attr_crb);
2831 device_remove_bin_file(dev, &bin_attr_mem);
2832}
2833
2834#ifdef CONFIG_INET
2835
2836#define is_netxen_netdev(dev) (dev->netdev_ops == &netxen_netdev_ops)
2837
2838static int
2839netxen_destip_supported(struct netxen_adapter *adapter)
2840{
2841 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2842 return 0;
2843
2844 if (adapter->ahw.cut_through)
2845 return 0;
2846
2847 return 1;
2848}
2849
2850static void
2851netxen_config_indev_addr(struct net_device *dev, unsigned long event)
2852{
2853 struct in_device *indev;
2854 struct netxen_adapter *adapter = netdev_priv(dev);
2855
2856 if (!netxen_destip_supported(adapter))
2857 return;
2858
2859 indev = in_dev_get(dev);
2860 if (!indev)
2861 return;
2862
2863 for_ifa(indev) {
2864 switch (event) {
2865 case NETDEV_UP:
2866 netxen_config_ipaddr(adapter,
2867 ifa->ifa_address, NX_IP_UP);
2868 break;
2869 case NETDEV_DOWN:
2870 netxen_config_ipaddr(adapter,
2871 ifa->ifa_address, NX_IP_DOWN);
2872 break;
2873 default:
2874 break;
2875 }
2876 } endfor_ifa(indev);
2877
2878 in_dev_put(indev);
2879}
2880
2881static int netxen_netdev_event(struct notifier_block *this,
2882 unsigned long event, void *ptr)
2883{
2884 struct netxen_adapter *adapter;
2885 struct net_device *dev = (struct net_device *)ptr;
2886
2887recheck:
2888 if (dev == NULL)
2889 goto done;
2890
2891 if (dev->priv_flags & IFF_802_1Q_VLAN) {
2892 dev = vlan_dev_real_dev(dev);
2893 goto recheck;
2894 }
2895
2896 if (!is_netxen_netdev(dev))
2897 goto done;
2898
2899 adapter = netdev_priv(dev);
2900
2901 if (!adapter)
2902 goto done;
2903
2904 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
2905 goto done;
2906
2907 netxen_config_indev_addr(dev, event);
2908done:
2909 return NOTIFY_DONE;
2910}
2911
2912static int
2913netxen_inetaddr_event(struct notifier_block *this,
2914 unsigned long event, void *ptr)
2915{
2916 struct netxen_adapter *adapter;
2917 struct net_device *dev;
2918
2919 struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
2920
2921 dev = ifa->ifa_dev ? ifa->ifa_dev->dev : NULL;
2922
2923recheck:
2924 if (dev == NULL || !netif_running(dev))
2925 goto done;
2926
2927 if (dev->priv_flags & IFF_802_1Q_VLAN) {
2928 dev = vlan_dev_real_dev(dev);
2929 goto recheck;
2930 }
2931
2932 if (!is_netxen_netdev(dev))
2933 goto done;
2934
2935 adapter = netdev_priv(dev);
2936
2937 if (!adapter || !netxen_destip_supported(adapter))
2938 goto done;
2939
2940 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
2941 goto done;
2942
2943 switch (event) {
2944 case NETDEV_UP:
2945 netxen_config_ipaddr(adapter, ifa->ifa_address, NX_IP_UP);
2946 break;
2947 case NETDEV_DOWN:
2948 netxen_config_ipaddr(adapter, ifa->ifa_address, NX_IP_DOWN);
2949 break;
2950 default:
2951 break;
2952 }
2953
2954done:
2955 return NOTIFY_DONE;
2956}
2957
2958static struct notifier_block netxen_netdev_cb = {
2959 .notifier_call = netxen_netdev_event,
2960};
2961
2962static struct notifier_block netxen_inetaddr_cb = {
2963 .notifier_call = netxen_inetaddr_event,
2964};
2965#else
2966static void
2967netxen_config_indev_addr(struct net_device *dev, unsigned long event)
2968{ }
2969#endif
2970
2971static struct pci_error_handlers netxen_err_handler = {
2972 .error_detected = netxen_io_error_detected,
2973 .slot_reset = netxen_io_slot_reset,
2974 .resume = netxen_io_resume,
2975};
2976
2977static struct pci_driver netxen_driver = {
2978 .name = netxen_nic_driver_name,
2979 .id_table = netxen_pci_tbl,
2980 .probe = netxen_nic_probe,
2981 .remove = __devexit_p(netxen_nic_remove),
2982#ifdef CONFIG_PM
2983 .suspend = netxen_nic_suspend,
2984 .resume = netxen_nic_resume,
2985#endif
2986 .shutdown = netxen_nic_shutdown,
2987 .err_handler = &netxen_err_handler
2988};
2989
2990static int __init netxen_init_module(void)
2991{
2992 printk(KERN_INFO "%s\n", netxen_nic_driver_string);
2993
2994#ifdef CONFIG_INET
2995 register_netdevice_notifier(&netxen_netdev_cb);
2996 register_inetaddr_notifier(&netxen_inetaddr_cb);
2997#endif
2998 return pci_register_driver(&netxen_driver);
2999}
3000
3001module_init(netxen_init_module);
3002
3003static void __exit netxen_exit_module(void)
3004{
3005 pci_unregister_driver(&netxen_driver);
3006
3007#ifdef CONFIG_INET
3008 unregister_inetaddr_notifier(&netxen_inetaddr_cb);
3009 unregister_netdevice_notifier(&netxen_netdev_cb);
3010#endif
3011}
3012
3013module_exit(netxen_exit_module);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-13 12:21:36 -0500