diff options
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_type.h')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_type.h | 513 |
1 files changed, 335 insertions, 178 deletions
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index 7057aa3f393..c76e30b94d8 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h | |||
@@ -37,7 +37,6 @@ | |||
37 | /* Device IDs */ | 37 | /* Device IDs */ |
38 | #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 | 38 | #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 |
39 | #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 | 39 | #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 |
40 | #define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8 | ||
41 | #define IXGBE_DEV_ID_82598EB_CX4 0x10DD | 40 | #define IXGBE_DEV_ID_82598EB_CX4 0x10DD |
42 | #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC | 41 | #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC |
43 | #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 | 42 | #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 |
@@ -71,11 +70,11 @@ | |||
71 | #define IXGBE_EIMC 0x00888 | 70 | #define IXGBE_EIMC 0x00888 |
72 | #define IXGBE_EIAC 0x00810 | 71 | #define IXGBE_EIAC 0x00810 |
73 | #define IXGBE_EIAM 0x00890 | 72 | #define IXGBE_EIAM 0x00890 |
74 | #define IXGBE_EITR(_i) (0x00820 + ((_i) * 4)) /* 0x820-0x86c */ | 73 | #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4))) |
75 | #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ | 74 | #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ |
76 | #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ | 75 | #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ |
77 | #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ | 76 | #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ |
78 | #define IXGBE_PBACL 0x11068 | 77 | #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) |
79 | #define IXGBE_GPIE 0x00898 | 78 | #define IXGBE_GPIE 0x00898 |
80 | 79 | ||
81 | /* Flow Control Registers */ | 80 | /* Flow Control Registers */ |
@@ -87,20 +86,33 @@ | |||
87 | #define IXGBE_TFCS 0x0CE00 | 86 | #define IXGBE_TFCS 0x0CE00 |
88 | 87 | ||
89 | /* Receive DMA Registers */ | 88 | /* Receive DMA Registers */ |
90 | #define IXGBE_RDBAL(_i) (0x01000 + ((_i) * 0x40)) /* 64 of each (0-63)*/ | 89 | #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40))) |
91 | #define IXGBE_RDBAH(_i) (0x01004 + ((_i) * 0x40)) | 90 | #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40))) |
92 | #define IXGBE_RDLEN(_i) (0x01008 + ((_i) * 0x40)) | 91 | #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40))) |
93 | #define IXGBE_RDH(_i) (0x01010 + ((_i) * 0x40)) | 92 | #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40))) |
94 | #define IXGBE_RDT(_i) (0x01018 + ((_i) * 0x40)) | 93 | #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40))) |
95 | #define IXGBE_RXDCTL(_i) (0x01028 + ((_i) * 0x40)) | 94 | #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40))) |
96 | #define IXGBE_RSCCTL(_i) (0x0102C + ((_i) * 0x40)) | 95 | /* |
97 | #define IXGBE_SRRCTL(_i) (0x02100 + ((_i) * 4)) | 96 | * Split and Replication Receive Control Registers |
98 | /* array of 16 (0x02100-0x0213C) */ | 97 | * 00-15 : 0x02100 + n*4 |
99 | #define IXGBE_DCA_RXCTRL(_i) (0x02200 + ((_i) * 4)) | 98 | * 16-64 : 0x01014 + n*0x40 |
100 | /* array of 16 (0x02200-0x0223C) */ | 99 | * 64-127: 0x0D014 + (n-64)*0x40 |
101 | #define IXGBE_RDRXCTL 0x02F00 | 100 | */ |
101 | #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ | ||
102 | (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ | ||
103 | (0x0D014 + ((_i - 64) * 0x40)))) | ||
104 | /* | ||
105 | * Rx DCA Control Register: | ||
106 | * 00-15 : 0x02200 + n*4 | ||
107 | * 16-64 : 0x0100C + n*0x40 | ||
108 | * 64-127: 0x0D00C + (n-64)*0x40 | ||
109 | */ | ||
110 | #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ | ||
111 | (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ | ||
112 | (0x0D00C + ((_i - 64) * 0x40)))) | ||
113 | #define IXGBE_RDRXCTL 0x02F00 | ||
102 | #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) | 114 | #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) |
103 | /* 8 of these 0x03C00 - 0x03C1C */ | 115 | /* 8 of these 0x03C00 - 0x03C1C */ |
104 | #define IXGBE_RXCTRL 0x03000 | 116 | #define IXGBE_RXCTRL 0x03000 |
105 | #define IXGBE_DROPEN 0x03D04 | 117 | #define IXGBE_DROPEN 0x03D04 |
106 | #define IXGBE_RXPBSIZE_SHIFT 10 | 118 | #define IXGBE_RXPBSIZE_SHIFT 10 |
@@ -108,29 +120,32 @@ | |||
108 | /* Receive Registers */ | 120 | /* Receive Registers */ |
109 | #define IXGBE_RXCSUM 0x05000 | 121 | #define IXGBE_RXCSUM 0x05000 |
110 | #define IXGBE_RFCTL 0x05008 | 122 | #define IXGBE_RFCTL 0x05008 |
123 | #define IXGBE_DRECCCTL 0x02F08 | ||
124 | #define IXGBE_DRECCCTL_DISABLE 0 | ||
125 | /* Multicast Table Array - 128 entries */ | ||
111 | #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) | 126 | #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) |
112 | /* Multicast Table Array - 128 entries */ | 127 | #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8))) |
113 | #define IXGBE_RAL(_i) (0x05400 + ((_i) * 8)) /* 16 of these (0-15) */ | 128 | #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8))) |
114 | #define IXGBE_RAH(_i) (0x05404 + ((_i) * 8)) /* 16 of these (0-15) */ | 129 | /* Packet split receive type */ |
115 | #define IXGBE_PSRTYPE 0x05480 | 130 | #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4))) |
116 | /* 0x5480-0x54BC Packet split receive type */ | 131 | /* array of 4096 1-bit vlan filters */ |
117 | #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) | 132 | #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) |
118 | /* array of 4096 1-bit vlan filters */ | 133 | /*array of 4096 4-bit vlan vmdq indices */ |
119 | #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) | 134 | #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) |
120 | /*array of 4096 4-bit vlan vmdq indicies */ | ||
121 | #define IXGBE_FCTRL 0x05080 | 135 | #define IXGBE_FCTRL 0x05080 |
122 | #define IXGBE_VLNCTRL 0x05088 | 136 | #define IXGBE_VLNCTRL 0x05088 |
123 | #define IXGBE_MCSTCTRL 0x05090 | 137 | #define IXGBE_MCSTCTRL 0x05090 |
124 | #define IXGBE_MRQC 0x05818 | 138 | #define IXGBE_MRQC 0x05818 |
125 | #define IXGBE_VMD_CTL 0x0581C | ||
126 | #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ | 139 | #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ |
127 | #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ | 140 | #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ |
128 | #define IXGBE_IMIRVP 0x05AC0 | 141 | #define IXGBE_IMIRVP 0x05AC0 |
142 | #define IXGBE_VMD_CTL 0x0581C | ||
129 | #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ | 143 | #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ |
130 | #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ | 144 | #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ |
131 | 145 | ||
146 | |||
132 | /* Transmit DMA registers */ | 147 | /* Transmit DMA registers */ |
133 | #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))/* 32 of these (0-31)*/ | 148 | #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ |
134 | #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) | 149 | #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) |
135 | #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) | 150 | #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) |
136 | #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) | 151 | #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) |
@@ -139,11 +154,10 @@ | |||
139 | #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) | 154 | #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) |
140 | #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) | 155 | #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) |
141 | #define IXGBE_DTXCTL 0x07E00 | 156 | #define IXGBE_DTXCTL 0x07E00 |
142 | #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) | 157 | |
143 | /* there are 16 of these (0-15) */ | 158 | #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ |
144 | #define IXGBE_TIPG 0x0CB00 | 159 | #define IXGBE_TIPG 0x0CB00 |
145 | #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) | 160 | #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ |
146 | /* there are 8 of these */ | ||
147 | #define IXGBE_MNGTXMAP 0x0CD10 | 161 | #define IXGBE_MNGTXMAP 0x0CD10 |
148 | #define IXGBE_TIPG_FIBER_DEFAULT 3 | 162 | #define IXGBE_TIPG_FIBER_DEFAULT 3 |
149 | #define IXGBE_TXPBSIZE_SHIFT 10 | 163 | #define IXGBE_TXPBSIZE_SHIFT 10 |
@@ -155,6 +169,7 @@ | |||
155 | #define IXGBE_IPAV 0x05838 | 169 | #define IXGBE_IPAV 0x05838 |
156 | #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ | 170 | #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ |
157 | #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ | 171 | #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ |
172 | |||
158 | #define IXGBE_WUPL 0x05900 | 173 | #define IXGBE_WUPL 0x05900 |
159 | #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ | 174 | #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ |
160 | #define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ | 175 | #define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ |
@@ -171,6 +186,8 @@ | |||
171 | #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ | 186 | #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ |
172 | #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ | 187 | #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ |
173 | 188 | ||
189 | |||
190 | |||
174 | /* Stats registers */ | 191 | /* Stats registers */ |
175 | #define IXGBE_CRCERRS 0x04000 | 192 | #define IXGBE_CRCERRS 0x04000 |
176 | #define IXGBE_ILLERRC 0x04004 | 193 | #define IXGBE_ILLERRC 0x04004 |
@@ -225,7 +242,7 @@ | |||
225 | #define IXGBE_XEC 0x04120 | 242 | #define IXGBE_XEC 0x04120 |
226 | 243 | ||
227 | #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ | 244 | #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ |
228 | #define IXGBE_TQSMR(_i) (0x07300 + ((_i) * 4)) /* 8 of these */ | 245 | #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4))) |
229 | 246 | ||
230 | #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ | 247 | #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ |
231 | #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ | 248 | #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ |
@@ -276,17 +293,17 @@ | |||
276 | #define IXGBE_DCA_CTRL 0x11074 | 293 | #define IXGBE_DCA_CTRL 0x11074 |
277 | 294 | ||
278 | /* Diagnostic Registers */ | 295 | /* Diagnostic Registers */ |
279 | #define IXGBE_RDSTATCTL 0x02C20 | 296 | #define IXGBE_RDSTATCTL 0x02C20 |
280 | #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ | 297 | #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ |
281 | #define IXGBE_RDHMPN 0x02F08 | 298 | #define IXGBE_RDHMPN 0x02F08 |
282 | #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) | 299 | #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) |
283 | #define IXGBE_RDPROBE 0x02F20 | 300 | #define IXGBE_RDPROBE 0x02F20 |
284 | #define IXGBE_TDSTATCTL 0x07C20 | 301 | #define IXGBE_TDSTATCTL 0x07C20 |
285 | #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ | 302 | #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ |
286 | #define IXGBE_TDHMPN 0x07F08 | 303 | #define IXGBE_TDHMPN 0x07F08 |
287 | #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) | 304 | #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) |
288 | #define IXGBE_TDPROBE 0x07F20 | 305 | #define IXGBE_TDPROBE 0x07F20 |
289 | #define IXGBE_TXBUFCTRL 0x0C600 | 306 | #define IXGBE_TXBUFCTRL 0x0C600 |
290 | #define IXGBE_TXBUFDATA0 0x0C610 | 307 | #define IXGBE_TXBUFDATA0 0x0C610 |
291 | #define IXGBE_TXBUFDATA1 0x0C614 | 308 | #define IXGBE_TXBUFDATA1 0x0C614 |
292 | #define IXGBE_TXBUFDATA2 0x0C618 | 309 | #define IXGBE_TXBUFDATA2 0x0C618 |
@@ -387,7 +404,7 @@ | |||
387 | 404 | ||
388 | #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ | 405 | #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ |
389 | #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ | 406 | #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ |
390 | #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */ | 407 | #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ |
391 | #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ | 408 | #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ |
392 | 409 | ||
393 | /* MSCA Bit Masks */ | 410 | /* MSCA Bit Masks */ |
@@ -411,10 +428,10 @@ | |||
411 | #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ | 428 | #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ |
412 | 429 | ||
413 | /* MSRWD bit masks */ | 430 | /* MSRWD bit masks */ |
414 | #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF | 431 | #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF |
415 | #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 | 432 | #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 |
416 | #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 | 433 | #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 |
417 | #define IXGBE_MSRWD_READ_DATA_SHIFT 16 | 434 | #define IXGBE_MSRWD_READ_DATA_SHIFT 16 |
418 | 435 | ||
419 | /* Atlas registers */ | 436 | /* Atlas registers */ |
420 | #define IXGBE_ATLAS_PDN_LPBK 0x24 | 437 | #define IXGBE_ATLAS_PDN_LPBK 0x24 |
@@ -429,6 +446,7 @@ | |||
429 | #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 | 446 | #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 |
430 | #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 | 447 | #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 |
431 | 448 | ||
449 | |||
432 | /* Device Type definitions for new protocol MDIO commands */ | 450 | /* Device Type definitions for new protocol MDIO commands */ |
433 | #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 | 451 | #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 |
434 | #define IXGBE_MDIO_PCS_DEV_TYPE 0x3 | 452 | #define IXGBE_MDIO_PCS_DEV_TYPE 0x3 |
@@ -436,6 +454,8 @@ | |||
436 | #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 | 454 | #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 |
437 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ | 455 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ |
438 | 456 | ||
457 | #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ | ||
458 | |||
439 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ | 459 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ |
440 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ | 460 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ |
441 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ | 461 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ |
@@ -449,23 +469,39 @@ | |||
449 | #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ | 469 | #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ |
450 | #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ | 470 | #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ |
451 | #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ | 471 | #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ |
452 | #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Abilty Reg */ | 472 | #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ |
453 | #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ | 473 | #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ |
454 | #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ | 474 | #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ |
455 | 475 | ||
476 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Address Reg */ | ||
477 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ | ||
478 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ | ||
479 | |||
480 | /* MII clause 22/28 definitions */ | ||
481 | #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 | ||
482 | |||
483 | #define IXGBE_MII_SPEED_SELECTION_REG 0x10 | ||
484 | #define IXGBE_MII_RESTART 0x200 | ||
485 | #define IXGBE_MII_AUTONEG_COMPLETE 0x20 | ||
486 | #define IXGBE_MII_AUTONEG_REG 0x0 | ||
487 | |||
456 | #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 | 488 | #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 |
457 | #define IXGBE_MAX_PHY_ADDR 32 | 489 | #define IXGBE_MAX_PHY_ADDR 32 |
458 | 490 | ||
459 | /* PHY IDs*/ | 491 | /* PHY IDs*/ |
460 | #define TN1010_PHY_ID 0x00A19410 | ||
461 | #define QT2022_PHY_ID 0x0043A400 | 492 | #define QT2022_PHY_ID 0x0043A400 |
462 | 493 | ||
494 | /* PHY Types */ | ||
495 | #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 | ||
496 | |||
463 | /* General purpose Interrupt Enable */ | 497 | /* General purpose Interrupt Enable */ |
464 | #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ | 498 | #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ |
465 | #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ | 499 | #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ |
466 | #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ | 500 | #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ |
467 | #define IXGBE_GPIE_EIAME 0x40000000 | 501 | #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ |
468 | #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 | 502 | #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ |
503 | #define IXGBE_GPIE_EIAME 0x40000000 | ||
504 | #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 | ||
469 | 505 | ||
470 | /* Transmit Flow Control status */ | 506 | /* Transmit Flow Control status */ |
471 | #define IXGBE_TFCS_TXOFF 0x00000001 | 507 | #define IXGBE_TFCS_TXOFF 0x00000001 |
@@ -526,7 +562,7 @@ | |||
526 | #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ | 562 | #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ |
527 | 563 | ||
528 | /* RMCS Bit Masks */ | 564 | /* RMCS Bit Masks */ |
529 | #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recylce Mode enable */ | 565 | #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ |
530 | /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ | 566 | /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ |
531 | #define IXGBE_RMCS_RAC 0x00000004 | 567 | #define IXGBE_RMCS_RAC 0x00000004 |
532 | #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ | 568 | #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ |
@@ -534,12 +570,15 @@ | |||
534 | #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ | 570 | #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ |
535 | #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ | 571 | #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ |
536 | 572 | ||
573 | |||
537 | /* Interrupt register bitmasks */ | 574 | /* Interrupt register bitmasks */ |
538 | 575 | ||
539 | /* Extended Interrupt Cause Read */ | 576 | /* Extended Interrupt Cause Read */ |
540 | #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ | 577 | #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ |
541 | #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ | 578 | #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ |
542 | #define IXGBE_EICR_MNG 0x00400000 /* Managability Event Interrupt */ | 579 | #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ |
580 | #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ | ||
581 | #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ | ||
543 | #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ | 582 | #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ |
544 | #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ | 583 | #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ |
545 | #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ | 584 | #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ |
@@ -547,11 +586,12 @@ | |||
547 | 586 | ||
548 | /* Extended Interrupt Cause Set */ | 587 | /* Extended Interrupt Cause Set */ |
549 | #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ | 588 | #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ |
550 | #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ | 589 | #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ |
551 | #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ | 590 | #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ |
552 | #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ | 591 | #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ |
553 | #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ | 592 | #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ |
554 | #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ | 593 | #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ |
594 | #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ | ||
555 | #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ | 595 | #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
556 | #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ | 596 | #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ |
557 | 597 | ||
@@ -559,7 +599,9 @@ | |||
559 | #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ | 599 | #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ |
560 | #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ | 600 | #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ |
561 | #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ | 601 | #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ |
562 | #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ | 602 | #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ |
603 | #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ | ||
604 | #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ | ||
563 | #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ | 605 | #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ |
564 | #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ | 606 | #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
565 | #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ | 607 | #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ |
@@ -568,18 +610,20 @@ | |||
568 | #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ | 610 | #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ |
569 | #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ | 611 | #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ |
570 | #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ | 612 | #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ |
571 | #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ | 613 | #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ |
572 | #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */ | 614 | #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ |
615 | #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ | ||
616 | #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ | ||
573 | #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ | 617 | #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
574 | #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ | 618 | #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ |
575 | 619 | ||
576 | #define IXGBE_EIMS_ENABLE_MASK (\ | 620 | #define IXGBE_EIMS_ENABLE_MASK ( \ |
577 | IXGBE_EIMS_RTX_QUEUE | \ | 621 | IXGBE_EIMS_RTX_QUEUE | \ |
578 | IXGBE_EIMS_LSC | \ | 622 | IXGBE_EIMS_LSC | \ |
579 | IXGBE_EIMS_TCP_TIMER | \ | 623 | IXGBE_EIMS_TCP_TIMER | \ |
580 | IXGBE_EIMS_OTHER) | 624 | IXGBE_EIMS_OTHER) |
581 | 625 | ||
582 | /* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */ | 626 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ |
583 | #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ | 627 | #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ |
584 | #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ | 628 | #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ |
585 | #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ | 629 | #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ |
@@ -616,6 +660,7 @@ | |||
616 | #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ | 660 | #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ |
617 | #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ | 661 | #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ |
618 | 662 | ||
663 | |||
619 | #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ | 664 | #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ |
620 | 665 | ||
621 | /* STATUS Bit Masks */ | 666 | /* STATUS Bit Masks */ |
@@ -663,16 +708,16 @@ | |||
663 | #define IXGBE_AUTOC_AN_RESTART 0x00001000 | 708 | #define IXGBE_AUTOC_AN_RESTART 0x00001000 |
664 | #define IXGBE_AUTOC_FLU 0x00000001 | 709 | #define IXGBE_AUTOC_FLU 0x00000001 |
665 | #define IXGBE_AUTOC_LMS_SHIFT 13 | 710 | #define IXGBE_AUTOC_LMS_SHIFT 13 |
666 | #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) | 711 | #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) |
667 | #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) | 712 | #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) |
668 | #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) | 713 | #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) |
669 | #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) | 714 | #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) |
670 | #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) | 715 | #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) |
671 | #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) | 716 | #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) |
672 | #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) | 717 | #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) |
673 | 718 | ||
674 | #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 | 719 | #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 |
675 | #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 | 720 | #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 |
676 | #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 | 721 | #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 |
677 | #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 | 722 | #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 |
678 | #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) | 723 | #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) |
@@ -753,6 +798,11 @@ | |||
753 | #define IXGBE_PBANUM0_PTR 0x15 | 798 | #define IXGBE_PBANUM0_PTR 0x15 |
754 | #define IXGBE_PBANUM1_PTR 0x16 | 799 | #define IXGBE_PBANUM1_PTR 0x16 |
755 | 800 | ||
801 | /* Legacy EEPROM word offsets */ | ||
802 | #define IXGBE_ISCSI_BOOT_CAPS 0x0033 | ||
803 | #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 | ||
804 | #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 | ||
805 | |||
756 | /* EEPROM Commands - SPI */ | 806 | /* EEPROM Commands - SPI */ |
757 | #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ | 807 | #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ |
758 | #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 | 808 | #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 |
@@ -760,7 +810,7 @@ | |||
760 | #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ | 810 | #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ |
761 | #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ | 811 | #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ |
762 | #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ | 812 | #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ |
763 | /* EEPROM reset Write Enbale latch */ | 813 | /* EEPROM reset Write Enable latch */ |
764 | #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 | 814 | #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 |
765 | #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ | 815 | #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ |
766 | #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ | 816 | #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ |
@@ -799,22 +849,20 @@ | |||
799 | /* Number of 100 microseconds we wait for PCI Express master disable */ | 849 | /* Number of 100 microseconds we wait for PCI Express master disable */ |
800 | #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 | 850 | #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 |
801 | 851 | ||
802 | /* PHY Types */ | ||
803 | #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 | ||
804 | |||
805 | /* Check whether address is multicast. This is little-endian specific check.*/ | 852 | /* Check whether address is multicast. This is little-endian specific check.*/ |
806 | #define IXGBE_IS_MULTICAST(Address) \ | 853 | #define IXGBE_IS_MULTICAST(Address) \ |
807 | (bool)(((u8 *)(Address))[0] & ((u8)0x01)) | 854 | (bool)(((u8 *)(Address))[0] & ((u8)0x01)) |
808 | 855 | ||
809 | /* Check whether an address is broadcast. */ | 856 | /* Check whether an address is broadcast. */ |
810 | #define IXGBE_IS_BROADCAST(Address) \ | 857 | #define IXGBE_IS_BROADCAST(Address) \ |
811 | ((((u8 *)(Address))[0] == ((u8)0xff)) && \ | 858 | ((((u8 *)(Address))[0] == ((u8)0xff)) && \ |
812 | (((u8 *)(Address))[1] == ((u8)0xff))) | 859 | (((u8 *)(Address))[1] == ((u8)0xff))) |
813 | 860 | ||
814 | /* RAH */ | 861 | /* RAH */ |
815 | #define IXGBE_RAH_VIND_MASK 0x003C0000 | 862 | #define IXGBE_RAH_VIND_MASK 0x003C0000 |
816 | #define IXGBE_RAH_VIND_SHIFT 18 | 863 | #define IXGBE_RAH_VIND_SHIFT 18 |
817 | #define IXGBE_RAH_AV 0x80000000 | 864 | #define IXGBE_RAH_AV 0x80000000 |
865 | #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF | ||
818 | 866 | ||
819 | /* Header split receive */ | 867 | /* Header split receive */ |
820 | #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 | 868 | #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 |
@@ -843,7 +891,7 @@ | |||
843 | #define IXGBE_MAX_FRAME_SZ 0x40040000 | 891 | #define IXGBE_MAX_FRAME_SZ 0x40040000 |
844 | 892 | ||
845 | #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ | 893 | #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ |
846 | #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq. # write-back enable */ | 894 | #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ |
847 | 895 | ||
848 | /* Receive Config masks */ | 896 | /* Receive Config masks */ |
849 | #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ | 897 | #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ |
@@ -856,7 +904,7 @@ | |||
856 | #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ | 904 | #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ |
857 | #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ | 905 | #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ |
858 | #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ | 906 | #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ |
859 | /* Receive Priority Flow Control Enbale */ | 907 | /* Receive Priority Flow Control Enable */ |
860 | #define IXGBE_FCTRL_RPFCE 0x00004000 | 908 | #define IXGBE_FCTRL_RPFCE 0x00004000 |
861 | #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ | 909 | #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ |
862 | 910 | ||
@@ -886,9 +934,8 @@ | |||
886 | /* Receive Descriptor bit definitions */ | 934 | /* Receive Descriptor bit definitions */ |
887 | #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ | 935 | #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ |
888 | #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ | 936 | #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ |
889 | #define IXGBE_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | ||
890 | #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | 937 | #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
891 | #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | 938 | #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
892 | #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ | 939 | #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ |
893 | #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ | 940 | #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ |
894 | #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ | 941 | #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ |
@@ -904,7 +951,7 @@ | |||
904 | #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ | 951 | #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ |
905 | #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ | 952 | #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ |
906 | #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ | 953 | #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ |
907 | #define IXGBE_RXDADV_HBO 0x00800000 | 954 | #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ |
908 | #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ | 955 | #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ |
909 | #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ | 956 | #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ |
910 | #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ | 957 | #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ |
@@ -918,15 +965,17 @@ | |||
918 | #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ | 965 | #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ |
919 | #define IXGBE_RXD_CFI_SHIFT 12 | 966 | #define IXGBE_RXD_CFI_SHIFT 12 |
920 | 967 | ||
968 | |||
921 | /* SRRCTL bit definitions */ | 969 | /* SRRCTL bit definitions */ |
922 | #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ | 970 | #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ |
923 | #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F | 971 | #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F |
924 | #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 | 972 | #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 |
925 | #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 | 973 | #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 |
926 | #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 | 974 | #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 |
927 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 | 975 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 |
928 | #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 | 976 | #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 |
929 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 | 977 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 |
978 | #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 | ||
930 | 979 | ||
931 | #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 | 980 | #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 |
932 | #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF | 981 | #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF |
@@ -960,21 +1009,20 @@ | |||
960 | #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ | 1009 | #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ |
961 | #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ | 1010 | #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ |
962 | #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ | 1011 | #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ |
963 | |||
964 | /* Masks to determine if packets should be dropped due to frame errors */ | 1012 | /* Masks to determine if packets should be dropped due to frame errors */ |
965 | #define IXGBE_RXD_ERR_FRAME_ERR_MASK (\ | 1013 | #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ |
966 | IXGBE_RXD_ERR_CE | \ | 1014 | IXGBE_RXD_ERR_CE | \ |
967 | IXGBE_RXD_ERR_LE | \ | 1015 | IXGBE_RXD_ERR_LE | \ |
968 | IXGBE_RXD_ERR_PE | \ | 1016 | IXGBE_RXD_ERR_PE | \ |
969 | IXGBE_RXD_ERR_OSE | \ | 1017 | IXGBE_RXD_ERR_OSE | \ |
970 | IXGBE_RXD_ERR_USE) | 1018 | IXGBE_RXD_ERR_USE) |
971 | 1019 | ||
972 | #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK (\ | 1020 | #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ |
973 | IXGBE_RXDADV_ERR_CE | \ | 1021 | IXGBE_RXDADV_ERR_CE | \ |
974 | IXGBE_RXDADV_ERR_LE | \ | 1022 | IXGBE_RXDADV_ERR_LE | \ |
975 | IXGBE_RXDADV_ERR_PE | \ | 1023 | IXGBE_RXDADV_ERR_PE | \ |
976 | IXGBE_RXDADV_ERR_OSE | \ | 1024 | IXGBE_RXDADV_ERR_OSE | \ |
977 | IXGBE_RXDADV_ERR_USE) | 1025 | IXGBE_RXDADV_ERR_USE) |
978 | 1026 | ||
979 | /* Multicast bit mask */ | 1027 | /* Multicast bit mask */ |
980 | #define IXGBE_MCSTCTRL_MFE 0x4 | 1028 | #define IXGBE_MCSTCTRL_MFE 0x4 |
@@ -990,6 +1038,7 @@ | |||
990 | #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ | 1038 | #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ |
991 | #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT | 1039 | #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT |
992 | 1040 | ||
1041 | |||
993 | /* Transmit Descriptor - Legacy */ | 1042 | /* Transmit Descriptor - Legacy */ |
994 | struct ixgbe_legacy_tx_desc { | 1043 | struct ixgbe_legacy_tx_desc { |
995 | u64 buffer_addr; /* Address of the descriptor's data buffer */ | 1044 | u64 buffer_addr; /* Address of the descriptor's data buffer */ |
@@ -1004,8 +1053,8 @@ struct ixgbe_legacy_tx_desc { | |||
1004 | union { | 1053 | union { |
1005 | __le32 data; | 1054 | __le32 data; |
1006 | struct { | 1055 | struct { |
1007 | u8 status; /* Descriptor status */ | 1056 | u8 status; /* Descriptor status */ |
1008 | u8 css; /* Checksum start */ | 1057 | u8 css; /* Checksum start */ |
1009 | __le16 vlan; | 1058 | __le16 vlan; |
1010 | } fields; | 1059 | } fields; |
1011 | } upper; | 1060 | } upper; |
@@ -1014,7 +1063,7 @@ struct ixgbe_legacy_tx_desc { | |||
1014 | /* Transmit Descriptor - Advanced */ | 1063 | /* Transmit Descriptor - Advanced */ |
1015 | union ixgbe_adv_tx_desc { | 1064 | union ixgbe_adv_tx_desc { |
1016 | struct { | 1065 | struct { |
1017 | __le64 buffer_addr; /* Address of descriptor's data buf */ | 1066 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
1018 | __le32 cmd_type_len; | 1067 | __le32 cmd_type_len; |
1019 | __le32 olinfo_status; | 1068 | __le32 olinfo_status; |
1020 | } read; | 1069 | } read; |
@@ -1046,8 +1095,8 @@ union ixgbe_adv_rx_desc { | |||
1046 | union { | 1095 | union { |
1047 | __le32 data; | 1096 | __le32 data; |
1048 | struct { | 1097 | struct { |
1049 | __le16 pkt_info; /* RSS type, Packet type */ | 1098 | __le16 pkt_info; /* RSS, Pkt type */ |
1050 | __le16 hdr_info; /* Split Header, header len */ | 1099 | __le16 hdr_info; /* Splithdr, hdrlen */ |
1051 | } hs_rss; | 1100 | } hs_rss; |
1052 | } lo_dword; | 1101 | } lo_dword; |
1053 | union { | 1102 | union { |
@@ -1075,49 +1124,69 @@ struct ixgbe_adv_tx_context_desc { | |||
1075 | }; | 1124 | }; |
1076 | 1125 | ||
1077 | /* Adv Transmit Descriptor Config Masks */ | 1126 | /* Adv Transmit Descriptor Config Masks */ |
1078 | #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */ | 1127 | #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ |
1079 | #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ | 1128 | #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ |
1080 | #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ | 1129 | #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ |
1081 | #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ | 1130 | #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ |
1082 | #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ | 1131 | #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ |
1083 | #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ | 1132 | #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ |
1084 | #define IXGBE_ADVTXD_DCMD_RDMA 0x04000000 /* RDMA */ | ||
1085 | #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ | 1133 | #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ |
1086 | #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ | 1134 | #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ |
1087 | #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ | 1135 | #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ |
1088 | #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ | 1136 | #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ |
1089 | #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ | 1137 | #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ |
1090 | #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ | 1138 | #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ |
1091 | #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ | 1139 | #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ |
1092 | #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ | 1140 | #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ |
1093 | #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ | 1141 | #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ |
1142 | #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ | ||
1094 | #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ | 1143 | #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ |
1095 | #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ | 1144 | #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ |
1096 | IXGBE_ADVTXD_POPTS_SHIFT) | 1145 | IXGBE_ADVTXD_POPTS_SHIFT) |
1097 | #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ | 1146 | #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ |
1098 | IXGBE_ADVTXD_POPTS_SHIFT) | 1147 | IXGBE_ADVTXD_POPTS_SHIFT) |
1099 | #define IXGBE_ADVTXD_POPTS_EOM 0x00000400 /* Enable L bit-RDMA DDP hdr */ | 1148 | #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ |
1100 | #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ | 1149 | #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ |
1101 | #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ | 1150 | #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ |
1102 | #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ | 1151 | #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ |
1103 | #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/ | 1152 | #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ |
1104 | #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ | 1153 | #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ |
1105 | #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ | 1154 | #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ |
1106 | #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ | 1155 | #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ |
1107 | #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ | 1156 | #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ |
1108 | #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ | 1157 | #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ |
1109 | #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ | 1158 | #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ |
1110 | #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ | 1159 | #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ |
1111 | #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ | 1160 | #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ |
1112 | #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ | 1161 | #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ |
1113 | #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ | 1162 | #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ |
1114 | #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ | 1163 | #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ |
1115 | 1164 | ||
1165 | /* Autonegotiation advertised speeds */ | ||
1166 | typedef u32 ixgbe_autoneg_advertised; | ||
1116 | /* Link speed */ | 1167 | /* Link speed */ |
1168 | typedef u32 ixgbe_link_speed; | ||
1117 | #define IXGBE_LINK_SPEED_UNKNOWN 0 | 1169 | #define IXGBE_LINK_SPEED_UNKNOWN 0 |
1118 | #define IXGBE_LINK_SPEED_100_FULL 0x0008 | 1170 | #define IXGBE_LINK_SPEED_100_FULL 0x0008 |
1119 | #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 | 1171 | #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 |
1120 | #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 | 1172 | #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 |
1173 | #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ | ||
1174 | IXGBE_LINK_SPEED_10GB_FULL) | ||
1175 | |||
1176 | /* Physical layer type */ | ||
1177 | typedef u32 ixgbe_physical_layer; | ||
1178 | #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 | ||
1179 | #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 | ||
1180 | #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 | ||
1181 | #define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004 | ||
1182 | #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 | ||
1183 | #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 | ||
1184 | #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 | ||
1185 | #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 | ||
1186 | #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 | ||
1187 | #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 | ||
1188 | #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 | ||
1189 | #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 | ||
1121 | 1190 | ||
1122 | 1191 | ||
1123 | enum ixgbe_eeprom_type { | 1192 | enum ixgbe_eeprom_type { |
@@ -1134,16 +1203,38 @@ enum ixgbe_mac_type { | |||
1134 | 1203 | ||
1135 | enum ixgbe_phy_type { | 1204 | enum ixgbe_phy_type { |
1136 | ixgbe_phy_unknown = 0, | 1205 | ixgbe_phy_unknown = 0, |
1137 | ixgbe_phy_tn, | ||
1138 | ixgbe_phy_qt, | 1206 | ixgbe_phy_qt, |
1139 | ixgbe_phy_xaui | 1207 | ixgbe_phy_xaui, |
1208 | ixgbe_phy_tw_tyco, | ||
1209 | ixgbe_phy_tw_unknown, | ||
1210 | ixgbe_phy_sfp_avago, | ||
1211 | ixgbe_phy_sfp_ftl, | ||
1212 | ixgbe_phy_sfp_unknown, | ||
1213 | ixgbe_phy_generic | ||
1214 | }; | ||
1215 | |||
1216 | /* | ||
1217 | * SFP+ module type IDs: | ||
1218 | * | ||
1219 | * ID Module Type | ||
1220 | * ============= | ||
1221 | * 0 SFP_DA_CU | ||
1222 | * 1 SFP_SR | ||
1223 | * 2 SFP_LR | ||
1224 | */ | ||
1225 | enum ixgbe_sfp_type { | ||
1226 | ixgbe_sfp_type_da_cu = 0, | ||
1227 | ixgbe_sfp_type_sr = 1, | ||
1228 | ixgbe_sfp_type_lr = 2, | ||
1229 | ixgbe_sfp_type_unknown = 0xFFFF | ||
1140 | }; | 1230 | }; |
1141 | 1231 | ||
1142 | enum ixgbe_media_type { | 1232 | enum ixgbe_media_type { |
1143 | ixgbe_media_type_unknown = 0, | 1233 | ixgbe_media_type_unknown = 0, |
1144 | ixgbe_media_type_fiber, | 1234 | ixgbe_media_type_fiber, |
1145 | ixgbe_media_type_copper, | 1235 | ixgbe_media_type_copper, |
1146 | ixgbe_media_type_backplane | 1236 | ixgbe_media_type_backplane, |
1237 | ixgbe_media_type_virtual | ||
1147 | }; | 1238 | }; |
1148 | 1239 | ||
1149 | /* Flow Control Settings */ | 1240 | /* Flow Control Settings */ |
@@ -1241,59 +1332,114 @@ struct ixgbe_hw; | |||
1241 | typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, | 1332 | typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, |
1242 | u32 *vmdq); | 1333 | u32 *vmdq); |
1243 | 1334 | ||
1335 | /* Function pointer table */ | ||
1336 | struct ixgbe_eeprom_operations { | ||
1337 | s32 (*init_params)(struct ixgbe_hw *); | ||
1338 | s32 (*read)(struct ixgbe_hw *, u16, u16 *); | ||
1339 | s32 (*write)(struct ixgbe_hw *, u16, u16); | ||
1340 | s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); | ||
1341 | s32 (*update_checksum)(struct ixgbe_hw *); | ||
1342 | }; | ||
1343 | |||
1244 | struct ixgbe_mac_operations { | 1344 | struct ixgbe_mac_operations { |
1245 | s32 (*reset)(struct ixgbe_hw *); | 1345 | s32 (*init_hw)(struct ixgbe_hw *); |
1346 | s32 (*reset_hw)(struct ixgbe_hw *); | ||
1347 | s32 (*start_hw)(struct ixgbe_hw *); | ||
1348 | s32 (*clear_hw_cntrs)(struct ixgbe_hw *); | ||
1246 | enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); | 1349 | enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); |
1350 | s32 (*get_supported_physical_layer)(struct ixgbe_hw *); | ||
1351 | s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); | ||
1352 | s32 (*stop_adapter)(struct ixgbe_hw *); | ||
1353 | s32 (*get_bus_info)(struct ixgbe_hw *); | ||
1354 | s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); | ||
1355 | s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); | ||
1356 | |||
1357 | /* Link */ | ||
1247 | s32 (*setup_link)(struct ixgbe_hw *); | 1358 | s32 (*setup_link)(struct ixgbe_hw *); |
1248 | s32 (*check_link)(struct ixgbe_hw *, u32 *, bool *, bool); | 1359 | s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, |
1249 | s32 (*setup_link_speed)(struct ixgbe_hw *, u32, bool, bool); | 1360 | bool); |
1250 | s32 (*get_link_settings)(struct ixgbe_hw *, u32 *, bool *); | 1361 | s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); |
1362 | s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, | ||
1363 | bool *); | ||
1364 | |||
1365 | /* LED */ | ||
1366 | s32 (*led_on)(struct ixgbe_hw *, u32); | ||
1367 | s32 (*led_off)(struct ixgbe_hw *, u32); | ||
1368 | s32 (*blink_led_start)(struct ixgbe_hw *, u32); | ||
1369 | s32 (*blink_led_stop)(struct ixgbe_hw *, u32); | ||
1370 | |||
1371 | /* RAR, Multicast, VLAN */ | ||
1372 | s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); | ||
1373 | s32 (*clear_rar)(struct ixgbe_hw *, u32); | ||
1374 | s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); | ||
1375 | s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); | ||
1376 | s32 (*init_rx_addrs)(struct ixgbe_hw *); | ||
1377 | s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, | ||
1378 | ixgbe_mc_addr_itr); | ||
1379 | s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, | ||
1380 | ixgbe_mc_addr_itr); | ||
1381 | s32 (*enable_mc)(struct ixgbe_hw *); | ||
1382 | s32 (*disable_mc)(struct ixgbe_hw *); | ||
1383 | s32 (*clear_vfta)(struct ixgbe_hw *); | ||
1384 | s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); | ||
1385 | s32 (*init_uta_tables)(struct ixgbe_hw *); | ||
1386 | |||
1387 | /* Flow Control */ | ||
1388 | s32 (*setup_fc)(struct ixgbe_hw *, s32); | ||
1251 | }; | 1389 | }; |
1252 | 1390 | ||
1253 | struct ixgbe_phy_operations { | 1391 | struct ixgbe_phy_operations { |
1392 | s32 (*identify)(struct ixgbe_hw *); | ||
1393 | s32 (*identify_sfp)(struct ixgbe_hw *); | ||
1394 | s32 (*reset)(struct ixgbe_hw *); | ||
1395 | s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); | ||
1396 | s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); | ||
1254 | s32 (*setup_link)(struct ixgbe_hw *); | 1397 | s32 (*setup_link)(struct ixgbe_hw *); |
1255 | s32 (*check_link)(struct ixgbe_hw *, u32 *, bool *); | 1398 | s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, |
1256 | s32 (*setup_link_speed)(struct ixgbe_hw *, u32, bool, bool); | 1399 | bool); |
1257 | }; | 1400 | s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); |
1258 | 1401 | s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); | |
1259 | struct ixgbe_mac_info { | 1402 | s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); |
1260 | struct ixgbe_mac_operations ops; | 1403 | s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); |
1261 | enum ixgbe_mac_type type; | ||
1262 | u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; | ||
1263 | u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; | ||
1264 | s32 mc_filter_type; | ||
1265 | u32 mcft_size; | ||
1266 | u32 vft_size; | ||
1267 | u32 num_rar_entries; | ||
1268 | u32 num_rx_queues; | ||
1269 | u32 num_tx_queues; | ||
1270 | u32 link_attach_type; | ||
1271 | u32 link_mode_select; | ||
1272 | bool link_settings_loaded; | ||
1273 | }; | 1404 | }; |
1274 | 1405 | ||
1275 | struct ixgbe_eeprom_info { | 1406 | struct ixgbe_eeprom_info { |
1276 | enum ixgbe_eeprom_type type; | 1407 | struct ixgbe_eeprom_operations ops; |
1277 | u16 word_size; | 1408 | enum ixgbe_eeprom_type type; |
1278 | u16 address_bits; | 1409 | u32 semaphore_delay; |
1410 | u16 word_size; | ||
1411 | u16 address_bits; | ||
1279 | }; | 1412 | }; |
1280 | 1413 | ||
1281 | struct ixgbe_phy_info { | 1414 | struct ixgbe_mac_info { |
1282 | struct ixgbe_phy_operations ops; | 1415 | struct ixgbe_mac_operations ops; |
1283 | 1416 | enum ixgbe_mac_type type; | |
1284 | enum ixgbe_phy_type type; | 1417 | u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; |
1285 | u32 addr; | 1418 | u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; |
1286 | u32 id; | 1419 | s32 mc_filter_type; |
1287 | u32 revision; | 1420 | u32 mcft_size; |
1288 | enum ixgbe_media_type media_type; | 1421 | u32 vft_size; |
1289 | u32 autoneg_advertised; | 1422 | u32 num_rar_entries; |
1290 | bool autoneg_wait_to_complete; | 1423 | u32 max_tx_queues; |
1424 | u32 max_rx_queues; | ||
1425 | u32 link_attach_type; | ||
1426 | u32 link_mode_select; | ||
1427 | bool link_settings_loaded; | ||
1428 | bool autoneg; | ||
1429 | bool autoneg_failed; | ||
1291 | }; | 1430 | }; |
1292 | 1431 | ||
1293 | struct ixgbe_info { | 1432 | struct ixgbe_phy_info { |
1294 | enum ixgbe_mac_type mac; | 1433 | struct ixgbe_phy_operations ops; |
1295 | s32 (*get_invariants)(struct ixgbe_hw *); | 1434 | enum ixgbe_phy_type type; |
1296 | struct ixgbe_mac_operations *mac_ops; | 1435 | u32 addr; |
1436 | u32 id; | ||
1437 | enum ixgbe_sfp_type sfp_type; | ||
1438 | u32 revision; | ||
1439 | enum ixgbe_media_type media_type; | ||
1440 | bool reset_disable; | ||
1441 | ixgbe_autoneg_advertised autoneg_advertised; | ||
1442 | bool autoneg_wait_to_complete; | ||
1297 | }; | 1443 | }; |
1298 | 1444 | ||
1299 | struct ixgbe_hw { | 1445 | struct ixgbe_hw { |
@@ -1312,6 +1458,15 @@ struct ixgbe_hw { | |||
1312 | bool adapter_stopped; | 1458 | bool adapter_stopped; |
1313 | }; | 1459 | }; |
1314 | 1460 | ||
1461 | struct ixgbe_info { | ||
1462 | enum ixgbe_mac_type mac; | ||
1463 | s32 (*get_invariants)(struct ixgbe_hw *); | ||
1464 | struct ixgbe_mac_operations *mac_ops; | ||
1465 | struct ixgbe_eeprom_operations *eeprom_ops; | ||
1466 | struct ixgbe_phy_operations *phy_ops; | ||
1467 | }; | ||
1468 | |||
1469 | |||
1315 | /* Error Codes */ | 1470 | /* Error Codes */ |
1316 | #define IXGBE_ERR_EEPROM -1 | 1471 | #define IXGBE_ERR_EEPROM -1 |
1317 | #define IXGBE_ERR_EEPROM_CHECKSUM -2 | 1472 | #define IXGBE_ERR_EEPROM_CHECKSUM -2 |
@@ -1330,6 +1485,8 @@ struct ixgbe_hw { | |||
1330 | #define IXGBE_ERR_RESET_FAILED -15 | 1485 | #define IXGBE_ERR_RESET_FAILED -15 |
1331 | #define IXGBE_ERR_SWFW_SYNC -16 | 1486 | #define IXGBE_ERR_SWFW_SYNC -16 |
1332 | #define IXGBE_ERR_PHY_ADDR_INVALID -17 | 1487 | #define IXGBE_ERR_PHY_ADDR_INVALID -17 |
1488 | #define IXGBE_ERR_I2C -18 | ||
1489 | #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 | ||
1333 | #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF | 1490 | #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF |
1334 | 1491 | ||
1335 | #endif /* _IXGBE_TYPE_H_ */ | 1492 | #endif /* _IXGBE_TYPE_H_ */ |