diff options
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_phy.h')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_phy.h | 60 |
1 files changed, 46 insertions, 14 deletions
diff --git a/drivers/net/ixgbe/ixgbe_phy.h b/drivers/net/ixgbe/ixgbe_phy.h index aa3ea72e678..f88c9131a01 100644 --- a/drivers/net/ixgbe/ixgbe_phy.h +++ b/drivers/net/ixgbe/ixgbe_phy.h | |||
@@ -30,20 +30,52 @@ | |||
30 | #define _IXGBE_PHY_H_ | 30 | #define _IXGBE_PHY_H_ |
31 | 31 | ||
32 | #include "ixgbe_type.h" | 32 | #include "ixgbe_type.h" |
33 | #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 | ||
33 | 34 | ||
34 | s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw); | 35 | /* EEPROM byte offsets */ |
35 | s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, u32 *speed, bool *link_up); | 36 | #define IXGBE_SFF_IDENTIFIER 0x0 |
36 | s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, u32 speed, bool autoneg, | 37 | #define IXGBE_SFF_IDENTIFIER_SFP 0x3 |
37 | bool autoneg_wait_to_complete); | 38 | #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 |
38 | s32 ixgbe_identify_phy(struct ixgbe_hw *hw); | 39 | #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 |
39 | s32 ixgbe_reset_phy(struct ixgbe_hw *hw); | 40 | #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 |
40 | s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, | 41 | #define IXGBE_SFF_1GBE_COMP_CODES 0x6 |
41 | u32 device_type, u16 *phy_data); | 42 | #define IXGBE_SFF_10GBE_COMP_CODES 0x3 |
42 | 43 | #define IXGBE_SFF_TRANSMISSION_MEDIA 0x9 | |
43 | /* PHY specific */ | 44 | |
44 | s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw); | 45 | /* Bitmasks */ |
45 | s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw, u32 *speed, bool *link_up); | 46 | #define IXGBE_SFF_TWIN_AX_CAPABLE 0x80 |
46 | s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw, u32 speed, bool autoneg, | 47 | #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 |
47 | bool autoneg_wait_to_complete); | 48 | #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 |
49 | #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 | ||
50 | #define IXGBE_I2C_EEPROM_READ_MASK 0x100 | ||
51 | #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 | ||
52 | #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 | ||
53 | #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 | ||
54 | #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 | ||
55 | #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 | ||
56 | |||
57 | /* Bit-shift macros */ | ||
58 | #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12 | ||
59 | #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8 | ||
60 | #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4 | ||
61 | |||
62 | /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ | ||
63 | #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 | ||
64 | #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 | ||
65 | #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 | ||
66 | |||
67 | |||
68 | s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); | ||
69 | s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); | ||
70 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); | ||
71 | s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | ||
72 | u32 device_type, u16 *phy_data); | ||
73 | s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | ||
74 | u32 device_type, u16 phy_data); | ||
75 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); | ||
76 | s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, | ||
77 | ixgbe_link_speed speed, | ||
78 | bool autoneg, | ||
79 | bool autoneg_wait_to_complete); | ||
48 | 80 | ||
49 | #endif /* _IXGBE_PHY_H_ */ | 81 | #endif /* _IXGBE_PHY_H_ */ |