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path: root/drivers/net/chelsio/pm3393.c
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Diffstat (limited to 'drivers/net/chelsio/pm3393.c')
-rw-r--r--drivers/net/chelsio/pm3393.c69
1 files changed, 29 insertions, 40 deletions
diff --git a/drivers/net/chelsio/pm3393.c b/drivers/net/chelsio/pm3393.c
index b943f5ddd8f..a1d15eebe12 100644
--- a/drivers/net/chelsio/pm3393.c
+++ b/drivers/net/chelsio/pm3393.c
@@ -43,22 +43,6 @@
43#include "elmer0.h" 43#include "elmer0.h"
44#include "suni1x10gexp_regs.h" 44#include "suni1x10gexp_regs.h"
45 45
46/* 802.3ae 10Gb/s MDIO Manageable Device(MMD)
47 */
48enum {
49 MMD_RESERVED,
50 MMD_PMAPMD,
51 MMD_WIS,
52 MMD_PCS,
53 MMD_PHY_XGXS, /* XGMII Extender Sublayer */
54 MMD_DTE_XGXS,
55};
56
57enum {
58 PHY_XGXS_CTRL_1,
59 PHY_XGXS_STATUS_1
60};
61
62#define OFFSET(REG_ADDR) (REG_ADDR << 2) 46#define OFFSET(REG_ADDR) (REG_ADDR << 2)
63 47
64/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */ 48/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
@@ -128,12 +112,12 @@ static int pm3393_reset(struct cmac *cmac)
128 112
129/* 113/*
130 * Enable interrupts for the PM3393 114 * Enable interrupts for the PM3393
131 115 *
132 1. Enable PM3393 BLOCK interrupts. 116 * 1. Enable PM3393 BLOCK interrupts.
133 2. Enable PM3393 Master Interrupt bit(INTE) 117 * 2. Enable PM3393 Master Interrupt bit(INTE)
134 3. Enable ELMER's PM3393 bit. 118 * 3. Enable ELMER's PM3393 bit.
135 4. Enable Terminator external interrupt. 119 * 4. Enable Terminator external interrupt.
136*/ 120 */
137static int pm3393_interrupt_enable(struct cmac *cmac) 121static int pm3393_interrupt_enable(struct cmac *cmac)
138{ 122{
139 u32 pl_intr; 123 u32 pl_intr;
@@ -261,11 +245,7 @@ static int pm3393_interrupt_clear(struct cmac *cmac)
261static int pm3393_interrupt_handler(struct cmac *cmac) 245static int pm3393_interrupt_handler(struct cmac *cmac)
262{ 246{
263 u32 master_intr_status; 247 u32 master_intr_status;
264/* 248
265 1. Read master interrupt register.
266 2. Read BLOCK's interrupt status registers.
267 3. Handle BLOCK interrupts.
268*/
269 /* Read the master interrupt status register. */ 249 /* Read the master interrupt status register. */
270 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, 250 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
271 &master_intr_status); 251 &master_intr_status);
@@ -473,20 +453,29 @@ static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
473 return 0; 453 return 0;
474} 454}
475 455
456static void pm3393_rmon_update(struct adapter *adapter, u32 offs, u64 *val,
457 int over)
458{
459 u32 val0, val1, val2;
460
461 t1_tpi_read(adapter, offs, &val0);
462 t1_tpi_read(adapter, offs + 4, &val1);
463 t1_tpi_read(adapter, offs + 8, &val2);
464
465 *val &= ~0ull << 40;
466 *val |= val0 & 0xffff;
467 *val |= (val1 & 0xffff) << 16;
468 *val |= (u64)(val2 & 0xff) << 32;
469
470 if (over)
471 *val += 1ull << 40;
472}
473
476#define RMON_UPDATE(mac, name, stat_name) \ 474#define RMON_UPDATE(mac, name, stat_name) \
477 { \ 475 pm3393_rmon_update((mac)->adapter, OFFSET(name), \
478 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \ 476 &(mac)->stats.stat_name, \
479 t1_tpi_read((mac)->adapter, OFFSET(((name)+1)), &val1); \ 477 (ro &((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2)))
480 t1_tpi_read((mac)->adapter, OFFSET(((name)+2)), &val2); \ 478
481 (mac)->stats.stat_name = ((u64)val0 & 0xffff) | \
482 (((u64)val1 & 0xffff) << 16) | \
483 (((u64)val2 & 0xff) << 32) | \
484 ((mac)->stats.stat_name & \
485 (~(u64)0 << 40)); \
486 if (ro & \
487 ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2)) \
488 (mac)->stats.stat_name += ((u64)1 << 40); \
489 }
490 479
491static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac, 480static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
492 int flag) 481 int flag)