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path: root/drivers/net/bnx2x/bnx2x_link.c
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Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c345
1 files changed, 313 insertions, 32 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 57178589897..a07a3a6abd4 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -976,7 +976,6 @@ void bnx2x_link_status_update(struct link_params *params,
976 default: 976 default:
977 break; 977 break;
978 } 978 }
979
980 vars->flow_ctrl = 0; 979 vars->flow_ctrl = 0;
981 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 980 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
982 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 981 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
@@ -1561,7 +1560,6 @@ static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1561 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 1560 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
1562 if (pause_result & (1<<1)) 1561 if (pause_result & (1<<1))
1563 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 1562 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
1564
1565} 1563}
1566 1564
1567static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 1565static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
@@ -1755,6 +1753,7 @@ static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
1755 MDIO_REG_BANK_GP_STATUS, 1753 MDIO_REG_BANK_GP_STATUS,
1756 MDIO_GP_STATUS_TOP_AN_STATUS1, 1754 MDIO_GP_STATUS_TOP_AN_STATUS1,
1757 &gp_status); 1755 &gp_status);
1756
1758 if (phy->req_line_speed == SPEED_AUTO_NEG) 1757 if (phy->req_line_speed == SPEED_AUTO_NEG)
1759 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 1758 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1760 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 1759 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
@@ -1858,7 +1857,6 @@ static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
1858 1857
1859 vars->line_speed = new_line_speed; 1858 vars->line_speed = new_line_speed;
1860 1859
1861
1862 } else { /* link_down */ 1860 } else { /* link_down */
1863 DP(NETIF_MSG_LINK, "phy link down\n"); 1861 DP(NETIF_MSG_LINK, "phy link down\n");
1864 1862
@@ -1964,7 +1962,7 @@ static u8 bnx2x_emac_program(struct link_params *params,
1964 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 1962 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1965 mode); 1963 mode);
1966 1964
1967 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed); 1965 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
1968 return 0; 1966 return 0;
1969} 1967}
1970 1968
@@ -2187,7 +2185,7 @@ static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2187 2185
2188 /* For all latched-signal=up : Re-Arm Latch signals */ 2186 /* For all latched-signal=up : Re-Arm Latch signals */
2189 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 2187 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2190 (latch_status & 0xfffe) | (latch_status & 1)); 2188 (latch_status & 0xfffe) | (latch_status & 1));
2191 } 2189 }
2192 /* For all latched-signal=up,Write original_signal to status */ 2190 /* For all latched-signal=up,Write original_signal to status */
2193} 2191}
@@ -2496,18 +2494,29 @@ u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
2496 return 0; 2494 return 0;
2497} 2495}
2498 2496
2499u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed) 2497
2498u8 bnx2x_set_led(struct link_params *params,
2499 struct link_vars *vars, u8 mode, u32 speed)
2500{ 2500{
2501 u8 port = params->port; 2501 u8 port = params->port;
2502 u16 hw_led_mode = params->hw_led_mode; 2502 u16 hw_led_mode = params->hw_led_mode;
2503 u8 rc = 0; 2503 u8 rc = 0, phy_idx;
2504 u32 tmp; 2504 u32 tmp;
2505 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2505 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2506 struct bnx2x *bp = params->bp; 2506 struct bnx2x *bp = params->bp;
2507 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 2507 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
2508 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 2508 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
2509 speed, hw_led_mode); 2509 speed, hw_led_mode);
2510 /* In case */
2511 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
2512 if (params->phy[phy_idx].set_link_led) {
2513 params->phy[phy_idx].set_link_led(
2514 &params->phy[phy_idx], params, mode);
2515 }
2516 }
2517
2510 switch (mode) { 2518 switch (mode) {
2519 case LED_MODE_FRONT_PANEL_OFF:
2511 case LED_MODE_OFF: 2520 case LED_MODE_OFF:
2512 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 2521 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
2513 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 2522 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
@@ -2518,7 +2527,18 @@ u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
2518 break; 2527 break;
2519 2528
2520 case LED_MODE_OPER: 2529 case LED_MODE_OPER:
2530 /**
2531 * For all other phys, OPER mode is same as ON, so in case
2532 * link is down, do nothing
2533 **/
2534 if (!vars->link_up)
2535 break;
2536 case LED_MODE_ON:
2521 if (SINGLE_MEDIA_DIRECT(params)) { 2537 if (SINGLE_MEDIA_DIRECT(params)) {
2538 /**
2539 * This is a work-around for HW issue found when link
2540 * is up in CL73
2541 */
2522 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 2542 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
2523 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 2543 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
2524 } else { 2544 } else {
@@ -2718,7 +2738,7 @@ static u8 bnx2x_update_link_down(struct link_params *params,
2718 u8 port = params->port; 2738 u8 port = params->port;
2719 2739
2720 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 2740 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
2721 bnx2x_set_led(params, LED_MODE_OFF, 0); 2741 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
2722 2742
2723 /* indicate no mac active */ 2743 /* indicate no mac active */
2724 vars->mac_type = MAC_TYPE_NONE; 2744 vars->mac_type = MAC_TYPE_NONE;
@@ -2753,6 +2773,7 @@ static u8 bnx2x_update_link_up(struct link_params *params,
2753 u8 rc = 0; 2773 u8 rc = 0;
2754 2774
2755 vars->link_status |= LINK_STATUS_LINK_UP; 2775 vars->link_status |= LINK_STATUS_LINK_UP;
2776
2756 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 2777 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
2757 vars->link_status |= 2778 vars->link_status |=
2758 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 2779 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
@@ -2760,9 +2781,11 @@ static u8 bnx2x_update_link_up(struct link_params *params,
2760 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 2781 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
2761 vars->link_status |= 2782 vars->link_status |=
2762 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 2783 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
2784
2763 if (link_10g) { 2785 if (link_10g) {
2764 bnx2x_bmac_enable(params, vars, 0); 2786 bnx2x_bmac_enable(params, vars, 0);
2765 bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000); 2787 bnx2x_set_led(params, vars,
2788 LED_MODE_OPER, SPEED_10000);
2766 } else { 2789 } else {
2767 rc = bnx2x_emac_program(params, vars); 2790 rc = bnx2x_emac_program(params, vars);
2768 2791
@@ -4685,6 +4708,53 @@ static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
4685/******************************************************************/ 4708/******************************************************************/
4686/* BCM8727 PHY SECTION */ 4709/* BCM8727 PHY SECTION */
4687/******************************************************************/ 4710/******************************************************************/
4711
4712static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
4713 struct link_params *params, u8 mode)
4714{
4715 struct bnx2x *bp = params->bp;
4716 u16 led_mode_bitmask = 0;
4717 u16 gpio_pins_bitmask = 0;
4718 u16 val;
4719 /* Only NOC flavor requires to set the LED specifically */
4720 if (!(phy->flags & FLAGS_NOC))
4721 return;
4722 switch (mode) {
4723 case LED_MODE_FRONT_PANEL_OFF:
4724 case LED_MODE_OFF:
4725 led_mode_bitmask = 0;
4726 gpio_pins_bitmask = 0x03;
4727 break;
4728 case LED_MODE_ON:
4729 led_mode_bitmask = 0;
4730 gpio_pins_bitmask = 0x02;
4731 break;
4732 case LED_MODE_OPER:
4733 led_mode_bitmask = 0x60;
4734 gpio_pins_bitmask = 0x11;
4735 break;
4736 }
4737 bnx2x_cl45_read(bp, phy,
4738 MDIO_PMA_DEVAD,
4739 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4740 &val);
4741 val &= 0xff8f;
4742 val |= led_mode_bitmask;
4743 bnx2x_cl45_write(bp, phy,
4744 MDIO_PMA_DEVAD,
4745 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4746 val);
4747 bnx2x_cl45_read(bp, phy,
4748 MDIO_PMA_DEVAD,
4749 MDIO_PMA_REG_8727_GPIO_CTRL,
4750 &val);
4751 val &= 0xffe0;
4752 val |= gpio_pins_bitmask;
4753 bnx2x_cl45_write(bp, phy,
4754 MDIO_PMA_DEVAD,
4755 MDIO_PMA_REG_8727_GPIO_CTRL,
4756 val);
4757}
4688static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 4758static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
4689 struct link_params *params) { 4759 struct link_params *params) {
4690 u32 swap_val, swap_override; 4760 u32 swap_val, swap_override;
@@ -4732,7 +4802,9 @@ static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
4732 (bit 9). 4802 (bit 9).
4733 When the EDC is off it locks onto a reference clock and 4803 When the EDC is off it locks onto a reference clock and
4734 avoids becoming 'lost'.*/ 4804 avoids becoming 'lost'.*/
4735 mod_abs &= ~((1<<8) | (1<<9)); 4805 mod_abs &= ~(1<<8);
4806 if (!(phy->flags & FLAGS_NOC))
4807 mod_abs &= ~(1<<9);
4736 bnx2x_cl45_write(bp, phy, 4808 bnx2x_cl45_write(bp, phy,
4737 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 4809 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4738 4810
@@ -4741,15 +4813,15 @@ static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
4741 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 4813 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4742 &val); 4814 &val);
4743 val |= (1<<12); 4815 val |= (1<<12);
4744 bnx2x_cl45_write(bp, phy, 4816 if (phy->flags & FLAGS_NOC)
4745 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); 4817 val |= (3<<5);
4746 /* Set 8727 GPIOs to input to allow reading from the
4747 8727 GPIO0 status which reflect SFP+ module
4748 over-current */
4749 4818
4750 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 4819 /**
4751 &val); 4820 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
4752 val &= 0xff8f; /* Reset bits 4-6 */ 4821 * status which reflect SFP+ module over-current
4822 */
4823 if (!(phy->flags & FLAGS_NOC))
4824 val &= 0xff8f; /* Reset bits 4-6 */
4753 bnx2x_cl45_write(bp, phy, 4825 bnx2x_cl45_write(bp, phy,
4754 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); 4826 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
4755 4827
@@ -4863,7 +4935,9 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
4863 (bit 9). 4935 (bit 9).
4864 When the EDC is off it locks onto a reference clock and 4936 When the EDC is off it locks onto a reference clock and
4865 avoids becoming 'lost'.*/ 4937 avoids becoming 'lost'.*/
4866 mod_abs &= ~((1<<8)|(1<<9)); 4938 mod_abs &= ~(1<<8);
4939 if (!(phy->flags & FLAGS_NOC))
4940 mod_abs &= ~(1<<9);
4867 bnx2x_cl45_write(bp, phy, 4941 bnx2x_cl45_write(bp, phy,
4868 MDIO_PMA_DEVAD, 4942 MDIO_PMA_DEVAD,
4869 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 4943 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
@@ -4887,7 +4961,9 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
4887 2. Restore the default polarity of the OPRXLOS signal and 4961 2. Restore the default polarity of the OPRXLOS signal and
4888 this signal will then correctly indicate the presence or 4962 this signal will then correctly indicate the presence or
4889 absence of the Rx signal. (bit 9) */ 4963 absence of the Rx signal. (bit 9) */
4890 mod_abs |= ((1<<8)|(1<<9)); 4964 mod_abs |= (1<<8);
4965 if (!(phy->flags & FLAGS_NOC))
4966 mod_abs |= (1<<9);
4891 bnx2x_cl45_write(bp, phy, 4967 bnx2x_cl45_write(bp, phy,
4892 MDIO_PMA_DEVAD, 4968 MDIO_PMA_DEVAD,
4893 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 4969 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
@@ -5306,21 +5382,22 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
5306 struct link_vars *vars) 5382 struct link_vars *vars)
5307{ 5383{
5308 struct bnx2x *bp = params->bp; 5384 struct bnx2x *bp = params->bp;
5309 u8 initialize = 1; 5385 u8 port = params->port, initialize = 1;
5310 u16 val; 5386 u16 val;
5311 u16 temp; 5387 u16 temp;
5312 u32 actual_phy_selection; 5388 u32 actual_phy_selection;
5313 u8 rc = 0; 5389 u8 rc = 0;
5390
5391 /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
5392
5314 msleep(1); 5393 msleep(1);
5315 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 5394 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5316 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 5395 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
5317 params->port); 5396 port);
5318 msleep(200); /* 100 is not enough */ 5397 msleep(200); /* 100 is not enough */
5319 5398
5320 /** 5399 /* BCM84823 requires that XGXS links up first @ 10G for normal
5321 * BCM84823 requires that XGXS links up first @ 10G for normal 5400 behavior */
5322 * behavior
5323 */
5324 temp = vars->line_speed; 5401 temp = vars->line_speed;
5325 vars->line_speed = SPEED_10000; 5402 vars->line_speed = SPEED_10000;
5326 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0); 5403 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
@@ -5495,6 +5572,184 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
5495 port); 5572 port);
5496} 5573}
5497 5574
5575static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
5576 struct link_params *params, u8 mode)
5577{
5578 struct bnx2x *bp = params->bp;
5579 u16 val;
5580
5581 switch (mode) {
5582 case LED_MODE_OFF:
5583
5584 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
5585
5586 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5587 SHARED_HW_CFG_LED_EXTPHY1) {
5588
5589 /* Set LED masks */
5590 bnx2x_cl45_write(bp, phy,
5591 MDIO_PMA_DEVAD,
5592 MDIO_PMA_REG_8481_LED1_MASK,
5593 0x0);
5594
5595 bnx2x_cl45_write(bp, phy,
5596 MDIO_PMA_DEVAD,
5597 MDIO_PMA_REG_8481_LED2_MASK,
5598 0x0);
5599
5600 bnx2x_cl45_write(bp, phy,
5601 MDIO_PMA_DEVAD,
5602 MDIO_PMA_REG_8481_LED3_MASK,
5603 0x0);
5604
5605 bnx2x_cl45_write(bp, phy,
5606 MDIO_PMA_DEVAD,
5607 MDIO_PMA_REG_8481_LED5_MASK,
5608 0x0);
5609
5610 } else {
5611 bnx2x_cl45_write(bp, phy,
5612 MDIO_PMA_DEVAD,
5613 MDIO_PMA_REG_8481_LED1_MASK,
5614 0x0);
5615 }
5616 break;
5617 case LED_MODE_FRONT_PANEL_OFF:
5618
5619 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
5620 params->port);
5621
5622 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5623 SHARED_HW_CFG_LED_EXTPHY1) {
5624
5625 /* Set LED masks */
5626 bnx2x_cl45_write(bp, phy,
5627 MDIO_PMA_DEVAD,
5628 MDIO_PMA_REG_8481_LED1_MASK,
5629 0x0);
5630
5631 bnx2x_cl45_write(bp, phy,
5632 MDIO_PMA_DEVAD,
5633 MDIO_PMA_REG_8481_LED2_MASK,
5634 0x0);
5635
5636 bnx2x_cl45_write(bp, phy,
5637 MDIO_PMA_DEVAD,
5638 MDIO_PMA_REG_8481_LED3_MASK,
5639 0x0);
5640
5641 bnx2x_cl45_write(bp, phy,
5642 MDIO_PMA_DEVAD,
5643 MDIO_PMA_REG_8481_LED5_MASK,
5644 0x20);
5645
5646 } else {
5647 bnx2x_cl45_write(bp, phy,
5648 MDIO_PMA_DEVAD,
5649 MDIO_PMA_REG_8481_LED1_MASK,
5650 0x0);
5651 }
5652 break;
5653 case LED_MODE_ON:
5654
5655 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
5656
5657 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5658 SHARED_HW_CFG_LED_EXTPHY1) {
5659 /* Set control reg */
5660 bnx2x_cl45_read(bp, phy,
5661 MDIO_PMA_DEVAD,
5662 MDIO_PMA_REG_8481_LINK_SIGNAL,
5663 &val);
5664 val &= 0x8000;
5665 val |= 0x2492;
5666
5667 bnx2x_cl45_write(bp, phy,
5668 MDIO_PMA_DEVAD,
5669 MDIO_PMA_REG_8481_LINK_SIGNAL,
5670 val);
5671
5672 /* Set LED masks */
5673 bnx2x_cl45_write(bp, phy,
5674 MDIO_PMA_DEVAD,
5675 MDIO_PMA_REG_8481_LED1_MASK,
5676 0x0);
5677
5678 bnx2x_cl45_write(bp, phy,
5679 MDIO_PMA_DEVAD,
5680 MDIO_PMA_REG_8481_LED2_MASK,
5681 0x20);
5682
5683 bnx2x_cl45_write(bp, phy,
5684 MDIO_PMA_DEVAD,
5685 MDIO_PMA_REG_8481_LED3_MASK,
5686 0x20);
5687
5688 bnx2x_cl45_write(bp, phy,
5689 MDIO_PMA_DEVAD,
5690 MDIO_PMA_REG_8481_LED5_MASK,
5691 0x0);
5692 } else {
5693 bnx2x_cl45_write(bp, phy,
5694 MDIO_PMA_DEVAD,
5695 MDIO_PMA_REG_8481_LED1_MASK,
5696 0x20);
5697 }
5698 break;
5699
5700 case LED_MODE_OPER:
5701
5702 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
5703
5704 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5705 SHARED_HW_CFG_LED_EXTPHY1) {
5706
5707 /* Set control reg */
5708 bnx2x_cl45_read(bp, phy,
5709 MDIO_PMA_DEVAD,
5710 MDIO_PMA_REG_8481_LINK_SIGNAL,
5711 &val);
5712
5713 if (!((val &
5714 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
5715 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){
5716 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n");
5717 bnx2x_cl45_write(bp, phy,
5718 MDIO_PMA_DEVAD,
5719 MDIO_PMA_REG_8481_LINK_SIGNAL,
5720 0xa492);
5721 }
5722
5723 /* Set LED masks */
5724 bnx2x_cl45_write(bp, phy,
5725 MDIO_PMA_DEVAD,
5726 MDIO_PMA_REG_8481_LED1_MASK,
5727 0x10);
5728
5729 bnx2x_cl45_write(bp, phy,
5730 MDIO_PMA_DEVAD,
5731 MDIO_PMA_REG_8481_LED2_MASK,
5732 0x80);
5733
5734 bnx2x_cl45_write(bp, phy,
5735 MDIO_PMA_DEVAD,
5736 MDIO_PMA_REG_8481_LED3_MASK,
5737 0x98);
5738
5739 bnx2x_cl45_write(bp, phy,
5740 MDIO_PMA_DEVAD,
5741 MDIO_PMA_REG_8481_LED5_MASK,
5742 0x40);
5743
5744 } else {
5745 bnx2x_cl45_write(bp, phy,
5746 MDIO_PMA_DEVAD,
5747 MDIO_PMA_REG_8481_LED1_MASK,
5748 0x80);
5749 }
5750 break;
5751 }
5752}
5498/******************************************************************/ 5753/******************************************************************/
5499/* SFX7101 PHY SECTION */ 5754/* SFX7101 PHY SECTION */
5500/******************************************************************/ 5755/******************************************************************/
@@ -5632,6 +5887,29 @@ static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
5632 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 5887 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
5633} 5888}
5634 5889
5890static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
5891 struct link_params *params, u8 mode)
5892{
5893 u16 val = 0;
5894 struct bnx2x *bp = params->bp;
5895 switch (mode) {
5896 case LED_MODE_FRONT_PANEL_OFF:
5897 case LED_MODE_OFF:
5898 val = 2;
5899 break;
5900 case LED_MODE_ON:
5901 val = 1;
5902 break;
5903 case LED_MODE_OPER:
5904 val = 0;
5905 break;
5906 }
5907 bnx2x_cl45_write(bp, phy,
5908 MDIO_PMA_DEVAD,
5909 MDIO_PMA_REG_7107_LINK_LED_CNTL,
5910 val);
5911}
5912
5635/******************************************************************/ 5913/******************************************************************/
5636/* STATIC PHY DECLARATION */ 5914/* STATIC PHY DECLARATION */
5637/******************************************************************/ 5915/******************************************************************/
@@ -5763,7 +6041,7 @@ static struct bnx2x_phy phy_7101 = {
5763 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 6041 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
5764 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 6042 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
5765 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 6043 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
5766 .set_link_led = (set_link_led_t)NULL, 6044 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
5767 .phy_specific_func = (phy_specific_func_t)NULL 6045 .phy_specific_func = (phy_specific_func_t)NULL
5768}; 6046};
5769static struct bnx2x_phy phy_8073 = { 6047static struct bnx2x_phy phy_8073 = {
@@ -5918,7 +6196,7 @@ static struct bnx2x_phy phy_8727 = {
5918 .config_loopback = (config_loopback_t)NULL, 6196 .config_loopback = (config_loopback_t)NULL,
5919 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 6197 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
5920 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 6198 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
5921 .set_link_led = (set_link_led_t)NULL, 6199 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
5922 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 6200 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
5923}; 6201};
5924static struct bnx2x_phy phy_8481 = { 6202static struct bnx2x_phy phy_8481 = {
@@ -5954,7 +6232,7 @@ static struct bnx2x_phy phy_8481 = {
5954 .config_loopback = (config_loopback_t)NULL, 6232 .config_loopback = (config_loopback_t)NULL,
5955 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 6233 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
5956 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 6234 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
5957 .set_link_led = (set_link_led_t)NULL, 6235 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
5958 .phy_specific_func = (phy_specific_func_t)NULL 6236 .phy_specific_func = (phy_specific_func_t)NULL
5959}; 6237};
5960 6238
@@ -5991,7 +6269,7 @@ static struct bnx2x_phy phy_84823 = {
5991 .config_loopback = (config_loopback_t)NULL, 6269 .config_loopback = (config_loopback_t)NULL,
5992 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 6270 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
5993 .hw_reset = (hw_reset_t)NULL, 6271 .hw_reset = (hw_reset_t)NULL,
5994 .set_link_led = (set_link_led_t)NULL, 6272 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
5995 .phy_specific_func = (phy_specific_func_t)NULL 6273 .phy_specific_func = (phy_specific_func_t)NULL
5996}; 6274};
5997 6275
@@ -6573,7 +6851,8 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6573 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + 6851 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6574 params->port*4, 0); 6852 params->port*4, 0);
6575 6853
6576 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed); 6854 bnx2x_set_led(params, vars,
6855 LED_MODE_OPER, vars->line_speed);
6577 } else 6856 } else
6578 /* No loopback */ 6857 /* No loopback */
6579 { 6858 {
@@ -6581,6 +6860,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6581 bnx2x_xgxs_deassert(params); 6860 bnx2x_xgxs_deassert(params);
6582 else 6861 else
6583 bnx2x_serdes_deassert(bp, params->port); 6862 bnx2x_serdes_deassert(bp, params->port);
6863
6584 bnx2x_link_initialize(params, vars); 6864 bnx2x_link_initialize(params, vars);
6585 msleep(30); 6865 msleep(30);
6586 bnx2x_link_int_enable(params); 6866 bnx2x_link_int_enable(params);
@@ -6620,7 +6900,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6620 * Hold it as vars low 6900 * Hold it as vars low
6621 */ 6901 */
6622 /* clear link led */ 6902 /* clear link led */
6623 bnx2x_set_led(params, LED_MODE_OFF, 0); 6903 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6904
6624 if (reset_ext_phy) { 6905 if (reset_ext_phy) {
6625 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6906 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6626 phy_index++) { 6907 phy_index++) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 14:34:21 -0400