1 files changed, 15 insertions, 15 deletions

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index efe246961b6..dbc7e55a424 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -3,7 +3,7 @@
  *
  *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
  *
- * $Id: nand_ids.c,v 1.14 2005/06/23 09:38:50 gleixner Exp $
+ * $Id: nand_ids.c,v 1.16 2005/11/07 11:14:31 gleixner Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,14 +14,14 @@
 #include <linux/mtd/nand.h>
 /*
 *       Chip ID list
-*       
+*
 *       Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
 *       options
-* 
+*
 *       Pagesize; 0, 256, 512
 *       0       get this information from the extended chip ID
 +       256     256 Byte page size
-*       512     512 Byte page size      
+*       512     512 Byte page size
 */
 struct nand_flash_dev nand_flash_ids[] = {
         {"NAND 1MiB 5V 8-bit",          0x6e, 256, 1, 0x1000, 0},
@@ -34,27 +34,27 @@ struct nand_flash_dev nand_flash_ids[] = {
         {"NAND 4MiB 3,3V 8-bit",        0xe3, 512, 4, 0x2000, 0},
         {"NAND 4MiB 3,3V 8-bit",        0xe5, 512, 4, 0x2000, 0},
         {"NAND 8MiB 3,3V 8-bit",        0xd6, 512, 8, 0x2000, 0},
-        
+
         {"NAND 8MiB 1,8V 8-bit",        0x39, 512, 8, 0x2000, 0},
         {"NAND 8MiB 3,3V 8-bit",        0xe6, 512, 8, 0x2000, 0},
         {"NAND 8MiB 1,8V 16-bit",       0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
         {"NAND 8MiB 3,3V 16-bit",       0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-        
+
         {"NAND 16MiB 1,8V 8-bit",       0x33, 512, 16, 0x4000, 0},
         {"NAND 16MiB 3,3V 8-bit",       0x73, 512, 16, 0x4000, 0},
         {"NAND 16MiB 1,8V 16-bit",      0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
         {"NAND 16MiB 3,3V 16-bit",      0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-        
+
         {"NAND 32MiB 1,8V 8-bit",       0x35, 512, 32, 0x4000, 0},
         {"NAND 32MiB 3,3V 8-bit",       0x75, 512, 32, 0x4000, 0},
         {"NAND 32MiB 1,8V 16-bit",      0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
         {"NAND 32MiB 3,3V 16-bit",      0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-        
+
         {"NAND 64MiB 1,8V 8-bit",       0x36, 512, 64, 0x4000, 0},
         {"NAND 64MiB 3,3V 8-bit",       0x76, 512, 64, 0x4000, 0},
         {"NAND 64MiB 1,8V 16-bit",      0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
         {"NAND 64MiB 3,3V 16-bit",      0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-        
+
         {"NAND 128MiB 1,8V 8-bit",      0x78, 512, 128, 0x4000, 0},
         {"NAND 128MiB 1,8V 8-bit",      0x39, 512, 128, 0x4000, 0},
         {"NAND 128MiB 3,3V 8-bit",      0x79, 512, 128, 0x4000, 0},
@@ -62,7 +62,7 @@ struct nand_flash_dev nand_flash_ids[] = {
         {"NAND 128MiB 1,8V 16-bit",     0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
         {"NAND 128MiB 3,3V 16-bit",     0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
         {"NAND 128MiB 3,3V 16-bit",     0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-        
+
         {"NAND 256MiB 3,3V 8-bit",      0x71, 512, 256, 0x4000, 0},
 
         /* These are the new chips with large page size. The pagesize
@@ -73,7 +73,7 @@ struct nand_flash_dev nand_flash_ids[] = {
         {"NAND 64MiB 3,3V 8-bit",       0xF2, 0,  64, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
         {"NAND 64MiB 1,8V 16-bit",      0xB2, 0,  64, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
         {"NAND 64MiB 3,3V 16-bit",      0xC2, 0,  64, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-        
+
         /* 1 Gigabit */
         {"NAND 128MiB 1,8V 8-bit",      0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
         {"NAND 128MiB 3,3V 8-bit",      0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
@@ -85,13 +85,13 @@ struct nand_flash_dev nand_flash_ids[] = {
         {"NAND 256MiB 3,3V 8-bit",      0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
         {"NAND 256MiB 1,8V 16-bit",     0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
         {"NAND 256MiB 3,3V 16-bit",     0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-        
+
         /* 4 Gigabit */
         {"NAND 512MiB 1,8V 8-bit",      0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
         {"NAND 512MiB 3,3V 8-bit",      0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
         {"NAND 512MiB 1,8V 16-bit",     0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
         {"NAND 512MiB 3,3V 16-bit",     0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-        
+
         /* 8 Gigabit */
         {"NAND 1GiB 1,8V 8-bit",        0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
         {"NAND 1GiB 3,3V 8-bit",        0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
@@ -104,11 +104,11 @@ struct nand_flash_dev nand_flash_ids[] = {
         {"NAND 2GiB 1,8V 16-bit",       0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
         {"NAND 2GiB 3,3V 16-bit",       0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
 
-        /* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout ! 
+        /* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout !
          * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes
          * 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7
          * Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go
-         * There are more speed improvements for reads and writes possible, but not implemented now 
+         * There are more speed improvements for reads and writes possible, but not implemented now
          */
         {"AND 128MiB 3,3V 8-bit",       0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH},