diff options
Diffstat (limited to 'drivers/mtd/nand/nand_bcm_umi.h')
-rw-r--r-- | drivers/mtd/nand/nand_bcm_umi.h | 73 |
1 files changed, 36 insertions, 37 deletions
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h index 198b304d6f7..d90186684db 100644 --- a/drivers/mtd/nand/nand_bcm_umi.h +++ b/drivers/mtd/nand/nand_bcm_umi.h | |||
@@ -17,7 +17,7 @@ | |||
17 | /* ---- Include Files ---------------------------------------------------- */ | 17 | /* ---- Include Files ---------------------------------------------------- */ |
18 | #include <mach/reg_umi.h> | 18 | #include <mach/reg_umi.h> |
19 | #include <mach/reg_nand.h> | 19 | #include <mach/reg_nand.h> |
20 | #include <cfg_global.h> | 20 | #include <mach/cfg_global.h> |
21 | 21 | ||
22 | /* ---- Constants and Types ---------------------------------------------- */ | 22 | /* ---- Constants and Types ---------------------------------------------- */ |
23 | #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) | 23 | #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) |
@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData, | |||
48 | /* Check in device is ready */ | 48 | /* Check in device is ready */ |
49 | static inline int nand_bcm_umi_dev_ready(void) | 49 | static inline int nand_bcm_umi_dev_ready(void) |
50 | { | 50 | { |
51 | return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; | 51 | return readl(®_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY; |
52 | } | 52 | } |
53 | 53 | ||
54 | /* Wait until device is ready */ | 54 | /* Wait until device is ready */ |
@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void) | |||
62 | static inline void nand_bcm_umi_hamming_enable_hwecc(void) | 62 | static inline void nand_bcm_umi_hamming_enable_hwecc(void) |
63 | { | 63 | { |
64 | /* disable and reset ECC, 512 byte page */ | 64 | /* disable and reset ECC, 512 byte page */ |
65 | REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | | 65 | writel(readl(®_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | |
66 | REG_UMI_NAND_ECC_CSR_256BYTE); | 66 | REG_UMI_NAND_ECC_CSR_256BYTE), ®_UMI_NAND_ECC_CSR); |
67 | /* enable ECC */ | 67 | /* enable ECC */ |
68 | REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; | 68 | writel(readl(®_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE, |
69 | ®_UMI_NAND_ECC_CSR); | ||
69 | } | 70 | } |
70 | 71 | ||
71 | #if NAND_ECC_BCH | 72 | #if NAND_ECC_BCH |
@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void) | |||
76 | static inline void nand_bcm_umi_bch_enable_read_hwecc(void) | 77 | static inline void nand_bcm_umi_bch_enable_read_hwecc(void) |
77 | { | 78 | { |
78 | /* disable and reset ECC */ | 79 | /* disable and reset ECC */ |
79 | REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; | 80 | writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); |
80 | /* Turn on ECC */ | 81 | /* Turn on ECC */ |
81 | REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; | 82 | writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); |
82 | } | 83 | } |
83 | 84 | ||
84 | /* Enable BCH Write ECC */ | 85 | /* Enable BCH Write ECC */ |
85 | static inline void nand_bcm_umi_bch_enable_write_hwecc(void) | 86 | static inline void nand_bcm_umi_bch_enable_write_hwecc(void) |
86 | { | 87 | { |
87 | /* disable and reset ECC */ | 88 | /* disable and reset ECC */ |
88 | REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; | 89 | writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); |
89 | /* Turn on ECC */ | 90 | /* Turn on ECC */ |
90 | REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; | 91 | writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, ®_UMI_BCH_CTRL_STATUS); |
91 | } | 92 | } |
92 | 93 | ||
93 | /* Config number of BCH ECC bytes */ | 94 | /* Config number of BCH ECC bytes */ |
@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) | |||
99 | uint32_t numBits = numEccBytes * 8; | 100 | uint32_t numBits = numEccBytes * 8; |
100 | 101 | ||
101 | /* disable and reset ECC */ | 102 | /* disable and reset ECC */ |
102 | REG_UMI_BCH_CTRL_STATUS = | 103 | writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | |
103 | REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | | 104 | REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, |
104 | REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; | 105 | ®_UMI_BCH_CTRL_STATUS); |
105 | 106 | ||
106 | /* Every correctible bit requires 13 ECC bits */ | 107 | /* Every correctible bit requires 13 ECC bits */ |
107 | tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); | 108 | tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); |
@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) | |||
113 | kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); | 114 | kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); |
114 | 115 | ||
115 | /* Write the settings */ | 116 | /* Write the settings */ |
116 | REG_UMI_BCH_N = nValue; | 117 | writel(nValue, ®_UMI_BCH_N); |
117 | REG_UMI_BCH_T = tValue; | 118 | writel(tValue, ®_UMI_BCH_T); |
118 | REG_UMI_BCH_K = kValue; | 119 | writel(kValue, ®_UMI_BCH_K); |
119 | } | 120 | } |
120 | 121 | ||
121 | /* Pause during ECC read calculation to skip bytes in OOB */ | 122 | /* Pause during ECC read calculation to skip bytes in OOB */ |
122 | static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) | 123 | static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) |
123 | { | 124 | { |
124 | REG_UMI_BCH_CTRL_STATUS = | 125 | writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, ®_UMI_BCH_CTRL_STATUS); |
125 | REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | | ||
126 | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC; | ||
127 | } | 126 | } |
128 | 127 | ||
129 | /* Resume during ECC read calculation after skipping bytes in OOB */ | 128 | /* Resume during ECC read calculation after skipping bytes in OOB */ |
130 | static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) | 129 | static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) |
131 | { | 130 | { |
132 | REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; | 131 | writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); |
133 | } | 132 | } |
134 | 133 | ||
135 | /* Poll read ECC calc to check when hardware completes */ | 134 | /* Poll read ECC calc to check when hardware completes */ |
@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) | |||
139 | 138 | ||
140 | do { | 139 | do { |
141 | /* wait for ECC to be valid */ | 140 | /* wait for ECC to be valid */ |
142 | regVal = REG_UMI_BCH_CTRL_STATUS; | 141 | regVal = readl(®_UMI_BCH_CTRL_STATUS); |
143 | } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); | 142 | } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); |
144 | 143 | ||
145 | return regVal; | 144 | return regVal; |
@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) | |||
149 | static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) | 148 | static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) |
150 | { | 149 | { |
151 | /* wait for ECC to be valid */ | 150 | /* wait for ECC to be valid */ |
152 | while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) | 151 | while ((readl(®_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) |
153 | == 0) | 152 | == 0) |
154 | ; | 153 | ; |
155 | } | 154 | } |
@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, | |||
170 | if (pageSize != NAND_DATA_ACCESS_SIZE) { | 169 | if (pageSize != NAND_DATA_ACCESS_SIZE) { |
171 | /* skip BI */ | 170 | /* skip BI */ |
172 | #if defined(__KERNEL__) && !defined(STANDALONE) | 171 | #if defined(__KERNEL__) && !defined(STANDALONE) |
173 | *oobp++ = REG_NAND_DATA8; | 172 | *oobp++ = readb(®_NAND_DATA8); |
174 | #else | 173 | #else |
175 | REG_NAND_DATA8; | 174 | readb(®_NAND_DATA8); |
176 | #endif | 175 | #endif |
177 | numToRead--; | 176 | numToRead--; |
178 | } | 177 | } |
@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, | |||
180 | while (numToRead > numEccBytes) { | 179 | while (numToRead > numEccBytes) { |
181 | /* skip free oob region */ | 180 | /* skip free oob region */ |
182 | #if defined(__KERNEL__) && !defined(STANDALONE) | 181 | #if defined(__KERNEL__) && !defined(STANDALONE) |
183 | *oobp++ = REG_NAND_DATA8; | 182 | *oobp++ = readb(®_NAND_DATA8); |
184 | #else | 183 | #else |
185 | REG_NAND_DATA8; | 184 | readb(®_NAND_DATA8); |
186 | #endif | 185 | #endif |
187 | numToRead--; | 186 | numToRead--; |
188 | } | 187 | } |
@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, | |||
193 | 192 | ||
194 | while (numToRead > 11) { | 193 | while (numToRead > 11) { |
195 | #if defined(__KERNEL__) && !defined(STANDALONE) | 194 | #if defined(__KERNEL__) && !defined(STANDALONE) |
196 | *oobp = REG_NAND_DATA8; | 195 | *oobp = readb(®_NAND_DATA8); |
197 | eccCalc[eccPos++] = *oobp; | 196 | eccCalc[eccPos++] = *oobp; |
198 | oobp++; | 197 | oobp++; |
199 | #else | 198 | #else |
200 | eccCalc[eccPos++] = REG_NAND_DATA8; | 199 | eccCalc[eccPos++] = readb(®_NAND_DATA8); |
201 | #endif | 200 | #endif |
202 | numToRead--; | 201 | numToRead--; |
203 | } | 202 | } |
@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, | |||
207 | if (numToRead == 11) { | 206 | if (numToRead == 11) { |
208 | /* read BI */ | 207 | /* read BI */ |
209 | #if defined(__KERNEL__) && !defined(STANDALONE) | 208 | #if defined(__KERNEL__) && !defined(STANDALONE) |
210 | *oobp++ = REG_NAND_DATA8; | 209 | *oobp++ = readb(®_NAND_DATA8); |
211 | #else | 210 | #else |
212 | REG_NAND_DATA8; | 211 | readb(®_NAND_DATA8); |
213 | #endif | 212 | #endif |
214 | numToRead--; | 213 | numToRead--; |
215 | } | 214 | } |
@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, | |||
219 | nand_bcm_umi_bch_resume_read_ecc_calc(); | 218 | nand_bcm_umi_bch_resume_read_ecc_calc(); |
220 | while (numToRead) { | 219 | while (numToRead) { |
221 | #if defined(__KERNEL__) && !defined(STANDALONE) | 220 | #if defined(__KERNEL__) && !defined(STANDALONE) |
222 | *oobp = REG_NAND_DATA8; | 221 | *oobp = readb(®_NAND_DATA8); |
223 | eccCalc[eccPos++] = *oobp; | 222 | eccCalc[eccPos++] = *oobp; |
224 | oobp++; | 223 | oobp++; |
225 | #else | 224 | #else |
226 | eccCalc[eccPos++] = REG_NAND_DATA8; | 225 | eccCalc[eccPos++] = readb(®_NAND_DATA8); |
227 | #endif | 226 | #endif |
228 | numToRead--; | 227 | numToRead--; |
229 | } | 228 | } |
@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, | |||
255 | if (pageSize == NAND_DATA_ACCESS_SIZE) { | 254 | if (pageSize == NAND_DATA_ACCESS_SIZE) { |
256 | /* Now fill in the ECC bytes */ | 255 | /* Now fill in the ECC bytes */ |
257 | if (numEccBytes >= 13) | 256 | if (numEccBytes >= 13) |
258 | eccVal = REG_UMI_BCH_WR_ECC_3; | 257 | eccVal = readl(®_UMI_BCH_WR_ECC_3); |
259 | 258 | ||
260 | /* Usually we skip CM in oob[0,1] */ | 259 | /* Usually we skip CM in oob[0,1] */ |
261 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], | 260 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], |
@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, | |||
268 | eccVal & 0xff); /* ECC 12 */ | 267 | eccVal & 0xff); /* ECC 12 */ |
269 | 268 | ||
270 | if (numEccBytes >= 9) | 269 | if (numEccBytes >= 9) |
271 | eccVal = REG_UMI_BCH_WR_ECC_2; | 270 | eccVal = readl(®_UMI_BCH_WR_ECC_2); |
272 | 271 | ||
273 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], | 272 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], |
274 | (eccVal >> 24) & 0xff); /* ECC11 */ | 273 | (eccVal >> 24) & 0xff); /* ECC11 */ |
@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, | |||
281 | 280 | ||
282 | /* Now fill in the ECC bytes */ | 281 | /* Now fill in the ECC bytes */ |
283 | if (numEccBytes >= 13) | 282 | if (numEccBytes >= 13) |
284 | eccVal = REG_UMI_BCH_WR_ECC_3; | 283 | eccVal = readl(®_UMI_BCH_WR_ECC_3); |
285 | 284 | ||
286 | /* Usually skip CM in oob[1,2] */ | 285 | /* Usually skip CM in oob[1,2] */ |
287 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], | 286 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], |
@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, | |||
294 | eccVal & 0xff); /* ECC12 */ | 293 | eccVal & 0xff); /* ECC12 */ |
295 | 294 | ||
296 | if (numEccBytes >= 9) | 295 | if (numEccBytes >= 9) |
297 | eccVal = REG_UMI_BCH_WR_ECC_2; | 296 | eccVal = readl(®_UMI_BCH_WR_ECC_2); |
298 | 297 | ||
299 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], | 298 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], |
300 | (eccVal >> 24) & 0xff); /* ECC11 */ | 299 | (eccVal >> 24) & 0xff); /* ECC11 */ |
@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, | |||
309 | eccVal & 0xff); /* ECC8 */ | 308 | eccVal & 0xff); /* ECC8 */ |
310 | 309 | ||
311 | if (numEccBytes >= 5) | 310 | if (numEccBytes >= 5) |
312 | eccVal = REG_UMI_BCH_WR_ECC_1; | 311 | eccVal = readl(®_UMI_BCH_WR_ECC_1); |
313 | 312 | ||
314 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], | 313 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], |
315 | (eccVal >> 24) & 0xff); /* ECC7 */ | 314 | (eccVal >> 24) & 0xff); /* ECC7 */ |
@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, | |||
321 | eccVal & 0xff); /* ECC4 */ | 320 | eccVal & 0xff); /* ECC4 */ |
322 | 321 | ||
323 | if (numEccBytes >= 1) | 322 | if (numEccBytes >= 1) |
324 | eccVal = REG_UMI_BCH_WR_ECC_0; | 323 | eccVal = readl(®_UMI_BCH_WR_ECC_0); |
325 | 324 | ||
326 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], | 325 | NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], |
327 | (eccVal >> 24) & 0xff); /* ECC3 */ | 326 | (eccVal >> 24) & 0xff); /* ECC3 */ |