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-rw-r--r--drivers/mtd/nand/autcpu12.c239
-rw-r--r--drivers/mtd/nand/bcm_umi_bch.c213
-rw-r--r--drivers/mtd/nand/bcm_umi_nand.c579
-rw-r--r--drivers/mtd/nand/edb7312.c203
-rw-r--r--drivers/mtd/nand/nand_bcm_umi.c149
-rw-r--r--drivers/mtd/nand/nand_bcm_umi.h337
-rw-r--r--drivers/mtd/nand/nomadik_nand.c246
-rw-r--r--drivers/mtd/nand/spia.c176
8 files changed, 2142 insertions, 0 deletions
diff --git a/drivers/mtd/nand/autcpu12.c b/drivers/mtd/nand/autcpu12.c
new file mode 100644
index 00000000000..eddc9a22498
--- /dev/null
+++ b/drivers/mtd/nand/autcpu12.c
@@ -0,0 +1,239 @@
1/*
2 * drivers/mtd/autcpu12.c
3 *
4 * Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
5 *
6 * Derived from drivers/mtd/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Overview:
14 * This is a device driver for the NAND flash device found on the
15 * autronix autcpu12 board, which is a SmartMediaCard. It supports
16 * 16MiB, 32MiB and 64MiB cards.
17 *
18 *
19 * 02-12-2002 TG Cleanup of module params
20 *
21 * 02-20-2002 TG adjusted for different rd/wr address support
22 * added support for read device ready/busy line
23 * added page_cache
24 *
25 * 10-06-2002 TG 128K card support added
26 */
27
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/partitions.h>
34#include <asm/io.h>
35#include <mach/hardware.h>
36#include <asm/sizes.h>
37#include <mach/autcpu12.h>
38
39/*
40 * MTD structure for AUTCPU12 board
41 */
42static struct mtd_info *autcpu12_mtd = NULL;
43static void __iomem *autcpu12_fio_base;
44
45/*
46 * Define partitions for flash devices
47 */
48static struct mtd_partition partition_info16k[] = {
49 { .name = "AUTCPU12 flash partition 1",
50 .offset = 0,
51 .size = 8 * SZ_1M },
52 { .name = "AUTCPU12 flash partition 2",
53 .offset = 8 * SZ_1M,
54 .size = 8 * SZ_1M },
55};
56
57static struct mtd_partition partition_info32k[] = {
58 { .name = "AUTCPU12 flash partition 1",
59 .offset = 0,
60 .size = 8 * SZ_1M },
61 { .name = "AUTCPU12 flash partition 2",
62 .offset = 8 * SZ_1M,
63 .size = 24 * SZ_1M },
64};
65
66static struct mtd_partition partition_info64k[] = {
67 { .name = "AUTCPU12 flash partition 1",
68 .offset = 0,
69 .size = 16 * SZ_1M },
70 { .name = "AUTCPU12 flash partition 2",
71 .offset = 16 * SZ_1M,
72 .size = 48 * SZ_1M },
73};
74
75static struct mtd_partition partition_info128k[] = {
76 { .name = "AUTCPU12 flash partition 1",
77 .offset = 0,
78 .size = 16 * SZ_1M },
79 { .name = "AUTCPU12 flash partition 2",
80 .offset = 16 * SZ_1M,
81 .size = 112 * SZ_1M },
82};
83
84#define NUM_PARTITIONS16K 2
85#define NUM_PARTITIONS32K 2
86#define NUM_PARTITIONS64K 2
87#define NUM_PARTITIONS128K 2
88/*
89 * hardware specific access to control-lines
90 *
91 * ALE bit 4 autcpu12_pedr
92 * CLE bit 5 autcpu12_pedr
93 * NCE bit 0 fio_ctrl
94 *
95 */
96static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd,
97 unsigned int ctrl)
98{
99 struct nand_chip *chip = mtd->priv;
100
101 if (ctrl & NAND_CTRL_CHANGE) {
102 void __iomem *addr;
103 unsigned char bits;
104
105 addr = CS89712_VIRT_BASE + AUTCPU12_SMC_PORT_OFFSET;
106 bits = (ctrl & NAND_CLE) << 4;
107 bits |= (ctrl & NAND_ALE) << 2;
108 writeb((readb(addr) & ~0x30) | bits, addr);
109
110 addr = autcpu12_fio_base + AUTCPU12_SMC_SELECT_OFFSET;
111 writeb((readb(addr) & ~0x1) | (ctrl & NAND_NCE), addr);
112 }
113
114 if (cmd != NAND_CMD_NONE)
115 writeb(cmd, chip->IO_ADDR_W);
116}
117
118/*
119 * read device ready pin
120 */
121int autcpu12_device_ready(struct mtd_info *mtd)
122{
123 void __iomem *addr = CS89712_VIRT_BASE + AUTCPU12_SMC_PORT_OFFSET;
124
125 return readb(addr) & AUTCPU12_SMC_RDY;
126}
127
128/*
129 * Main initialization routine
130 */
131static int __init autcpu12_init(void)
132{
133 struct nand_chip *this;
134 int err = 0;
135
136 /* Allocate memory for MTD device structure and private data */
137 autcpu12_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
138 GFP_KERNEL);
139 if (!autcpu12_mtd) {
140 printk("Unable to allocate AUTCPU12 NAND MTD device structure.\n");
141 err = -ENOMEM;
142 goto out;
143 }
144
145 /* map physical address */
146 autcpu12_fio_base = ioremap(AUTCPU12_PHYS_SMC, SZ_1K);
147 if (!autcpu12_fio_base) {
148 printk("Ioremap autcpu12 SmartMedia Card failed\n");
149 err = -EIO;
150 goto out_mtd;
151 }
152
153 /* Get pointer to private data */
154 this = (struct nand_chip *)(&autcpu12_mtd[1]);
155
156 /* Initialize structures */
157 memset(autcpu12_mtd, 0, sizeof(struct mtd_info));
158 memset(this, 0, sizeof(struct nand_chip));
159
160 /* Link the private data with the MTD structure */
161 autcpu12_mtd->priv = this;
162 autcpu12_mtd->owner = THIS_MODULE;
163
164 /* Set address of NAND IO lines */
165 this->IO_ADDR_R = autcpu12_fio_base;
166 this->IO_ADDR_W = autcpu12_fio_base;
167 this->cmd_ctrl = autcpu12_hwcontrol;
168 this->dev_ready = autcpu12_device_ready;
169 /* 20 us command delay time */
170 this->chip_delay = 20;
171 this->ecc.mode = NAND_ECC_SOFT;
172
173 /* Enable the following for a flash based bad block table */
174 /*
175 this->options = NAND_USE_FLASH_BBT;
176 */
177 this->options = NAND_USE_FLASH_BBT;
178
179 /* Scan to find existence of the device */
180 if (nand_scan(autcpu12_mtd, 1)) {
181 err = -ENXIO;
182 goto out_ior;
183 }
184
185 /* Register the partitions */
186 switch (autcpu12_mtd->size) {
187 case SZ_16M:
188 mtd_device_register(autcpu12_mtd, partition_info16k,
189 NUM_PARTITIONS16K);
190 break;
191 case SZ_32M:
192 mtd_device_register(autcpu12_mtd, partition_info32k,
193 NUM_PARTITIONS32K);
194 break;
195 case SZ_64M:
196 mtd_device_register(autcpu12_mtd, partition_info64k,
197 NUM_PARTITIONS64K);
198 break;
199 case SZ_128M:
200 mtd_device_register(autcpu12_mtd, partition_info128k,
201 NUM_PARTITIONS128K);
202 break;
203 default:
204 printk("Unsupported SmartMedia device\n");
205 err = -ENXIO;
206 goto out_ior;
207 }
208 goto out;
209
210 out_ior:
211 iounmap(autcpu12_fio_base);
212 out_mtd:
213 kfree(autcpu12_mtd);
214 out:
215 return err;
216}
217
218module_init(autcpu12_init);
219
220/*
221 * Clean up routine
222 */
223static void __exit autcpu12_cleanup(void)
224{
225 /* Release resources, unregister device */
226 nand_release(autcpu12_mtd);
227
228 /* unmap physical address */
229 iounmap(autcpu12_fio_base);
230
231 /* Free the MTD device structure */
232 kfree(autcpu12_mtd);
233}
234
235module_exit(autcpu12_cleanup);
236
237MODULE_LICENSE("GPL");
238MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
239MODULE_DESCRIPTION("Glue layer for SmartMediaCard on autronix autcpu12");
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
new file mode 100644
index 00000000000..a930666d068
--- /dev/null
+++ b/drivers/mtd/nand/bcm_umi_bch.c
@@ -0,0 +1,213 @@
1/*****************************************************************************
2* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include "nand_bcm_umi.h"
17
18/* ---- External Variable Declarations ----------------------------------- */
19/* ---- External Function Prototypes ------------------------------------- */
20/* ---- Public Variables ------------------------------------------------- */
21/* ---- Private Constants and Types -------------------------------------- */
22
23/* ---- Private Function Prototypes -------------------------------------- */
24static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
25 struct nand_chip *chip, uint8_t *buf, int page);
26static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
27 struct nand_chip *chip, const uint8_t *buf);
28
29/* ---- Private Variables ------------------------------------------------ */
30
31/*
32** nand_hw_eccoob
33** New oob placement block for use with hardware ecc generation.
34*/
35static struct nand_ecclayout nand_hw_eccoob_512 = {
36 /* Reserve 5 for BI indicator */
37 .oobfree = {
38#if (NAND_ECC_NUM_BYTES > 3)
39 {.offset = 0, .length = 2}
40#else
41 {.offset = 0, .length = 5},
42 {.offset = 6, .length = 7}
43#endif
44 }
45};
46
47/*
48** We treat the OOB for a 2K page as if it were 4 512 byte oobs,
49** except the BI is at byte 0.
50*/
51static struct nand_ecclayout nand_hw_eccoob_2048 = {
52 /* Reserve 0 as BI indicator */
53 .oobfree = {
54#if (NAND_ECC_NUM_BYTES > 10)
55 {.offset = 1, .length = 2},
56#elif (NAND_ECC_NUM_BYTES > 7)
57 {.offset = 1, .length = 5},
58 {.offset = 16, .length = 6},
59 {.offset = 32, .length = 6},
60 {.offset = 48, .length = 6}
61#else
62 {.offset = 1, .length = 8},
63 {.offset = 16, .length = 9},
64 {.offset = 32, .length = 9},
65 {.offset = 48, .length = 9}
66#endif
67 }
68};
69
70/* We treat the OOB for a 4K page as if it were 8 512 byte oobs,
71 * except the BI is at byte 0. */
72static struct nand_ecclayout nand_hw_eccoob_4096 = {
73 /* Reserve 0 as BI indicator */
74 .oobfree = {
75#if (NAND_ECC_NUM_BYTES > 10)
76 {.offset = 1, .length = 2},
77 {.offset = 16, .length = 3},
78 {.offset = 32, .length = 3},
79 {.offset = 48, .length = 3},
80 {.offset = 64, .length = 3},
81 {.offset = 80, .length = 3},
82 {.offset = 96, .length = 3},
83 {.offset = 112, .length = 3}
84#else
85 {.offset = 1, .length = 5},
86 {.offset = 16, .length = 6},
87 {.offset = 32, .length = 6},
88 {.offset = 48, .length = 6},
89 {.offset = 64, .length = 6},
90 {.offset = 80, .length = 6},
91 {.offset = 96, .length = 6},
92 {.offset = 112, .length = 6}
93#endif
94 }
95};
96
97/* ---- Private Functions ------------------------------------------------ */
98/* ==== Public Functions ================================================= */
99
100/****************************************************************************
101*
102* bcm_umi_bch_read_page_hwecc - hardware ecc based page read function
103* @mtd: mtd info structure
104* @chip: nand chip info structure
105* @buf: buffer to store read data
106*
107***************************************************************************/
108static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
109 struct nand_chip *chip, uint8_t * buf,
110 int page)
111{
112 int sectorIdx = 0;
113 int eccsize = chip->ecc.size;
114 int eccsteps = chip->ecc.steps;
115 uint8_t *datap = buf;
116 uint8_t eccCalc[NAND_ECC_NUM_BYTES];
117 int sectorOobSize = mtd->oobsize / eccsteps;
118 int stat;
119
120 for (sectorIdx = 0; sectorIdx < eccsteps;
121 sectorIdx++, datap += eccsize) {
122 if (sectorIdx > 0) {
123 /* Seek to page location within sector */
124 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize,
125 -1);
126 }
127
128 /* Enable hardware ECC before reading the buf */
129 nand_bcm_umi_bch_enable_read_hwecc();
130
131 /* Read in data */
132 bcm_umi_nand_read_buf(mtd, datap, eccsize);
133
134 /* Pause hardware ECC after reading the buf */
135 nand_bcm_umi_bch_pause_read_ecc_calc();
136
137 /* Read the OOB ECC */
138 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
139 mtd->writesize + sectorIdx * sectorOobSize, -1);
140 nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc,
141 NAND_ECC_NUM_BYTES,
142 chip->oob_poi +
143 sectorIdx * sectorOobSize);
144
145 /* Correct any ECC detected errors */
146 stat =
147 nand_bcm_umi_bch_correct_page(datap, eccCalc,
148 NAND_ECC_NUM_BYTES);
149
150 /* Update Stats */
151 if (stat < 0) {
152#if defined(NAND_BCM_UMI_DEBUG)
153 printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
154 __func__, sectorIdx);
155 printk(KERN_WARNING
156 "%s data %02x %02x %02x %02x "
157 "%02x %02x %02x %02x\n",
158 __func__, datap[0], datap[1], datap[2], datap[3],
159 datap[4], datap[5], datap[6], datap[7]);
160 printk(KERN_WARNING
161 "%s ecc %02x %02x %02x %02x "
162 "%02x %02x %02x %02x %02x %02x "
163 "%02x %02x %02x\n",
164 __func__, eccCalc[0], eccCalc[1], eccCalc[2],
165 eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
166 eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
167 eccCalc[11], eccCalc[12]);
168 BUG();
169#endif
170 mtd->ecc_stats.failed++;
171 } else {
172#if defined(NAND_BCM_UMI_DEBUG)
173 if (stat > 0) {
174 printk(KERN_INFO
175 "%s %d correctable_errors detected\n",
176 __func__, stat);
177 }
178#endif
179 mtd->ecc_stats.corrected += stat;
180 }
181 }
182 return 0;
183}
184
185/****************************************************************************
186*
187* bcm_umi_bch_write_page_hwecc - hardware ecc based page write function
188* @mtd: mtd info structure
189* @chip: nand chip info structure
190* @buf: data buffer
191*
192***************************************************************************/
193static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
194 struct nand_chip *chip, const uint8_t *buf)
195{
196 int sectorIdx = 0;
197 int eccsize = chip->ecc.size;
198 int eccsteps = chip->ecc.steps;
199 const uint8_t *datap = buf;
200 uint8_t *oobp = chip->oob_poi;
201 int sectorOobSize = mtd->oobsize / eccsteps;
202
203 for (sectorIdx = 0; sectorIdx < eccsteps;
204 sectorIdx++, datap += eccsize, oobp += sectorOobSize) {
205 /* Enable hardware ECC before writing the buf */
206 nand_bcm_umi_bch_enable_write_hwecc();
207 bcm_umi_nand_write_buf(mtd, datap, eccsize);
208 nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp,
209 NAND_ECC_NUM_BYTES);
210 }
211
212 bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
213}
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
new file mode 100644
index 00000000000..8c569e454dc
--- /dev/null
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -0,0 +1,579 @@
1/*****************************************************************************
2* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/slab.h>
21#include <linux/string.h>
22#include <linux/ioport.h>
23#include <linux/device.h>
24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/platform_device.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/nand_ecc.h>
31#include <linux/mtd/partitions.h>
32
33#include <asm/mach-types.h>
34#include <asm/system.h>
35
36#include <mach/reg_nand.h>
37#include <mach/reg_umi.h>
38
39#include "nand_bcm_umi.h"
40
41#include <mach/memory_settings.h>
42
43#define USE_DMA 1
44#include <mach/dma.h>
45#include <linux/dma-mapping.h>
46#include <linux/completion.h>
47
48/* ---- External Variable Declarations ----------------------------------- */
49/* ---- External Function Prototypes ------------------------------------- */
50/* ---- Public Variables ------------------------------------------------- */
51/* ---- Private Constants and Types -------------------------------------- */
52static const __devinitconst char gBanner[] = KERN_INFO \
53 "BCM UMI MTD NAND Driver: 1.00\n";
54
55const char *part_probes[] = { "cmdlinepart", NULL };
56
57#if NAND_ECC_BCH
58static uint8_t scan_ff_pattern[] = { 0xff };
59
60static struct nand_bbt_descr largepage_bbt = {
61 .options = 0,
62 .offs = 0,
63 .len = 1,
64 .pattern = scan_ff_pattern
65};
66#endif
67
68/*
69** Preallocate a buffer to avoid having to do this every dma operation.
70** This is the size of the preallocated coherent DMA buffer.
71*/
72#if USE_DMA
73#define DMA_MIN_BUFLEN 512
74#define DMA_MAX_BUFLEN PAGE_SIZE
75#define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) || \
76 ((len) > DMA_MAX_BUFLEN))
77
78/*
79 * The current NAND data space goes from 0x80001900 to 0x80001FFF,
80 * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
81 * size NAND flash. Need to break the DMA down to multiple 1Ks.
82 *
83 * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
84 */
85#define DMA_MAX_LEN 1024
86
87#else /* !USE_DMA */
88#define DMA_MIN_BUFLEN 0
89#define DMA_MAX_BUFLEN 0
90#define USE_DIRECT_IO(len) 1
91#endif
92/* ---- Private Function Prototypes -------------------------------------- */
93static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
94static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
95 int len);
96
97/* ---- Private Variables ------------------------------------------------ */
98static struct mtd_info *board_mtd;
99static void __iomem *bcm_umi_io_base;
100static void *virtPtr;
101static dma_addr_t physPtr;
102static struct completion nand_comp;
103
104/* ---- Private Functions ------------------------------------------------ */
105#if NAND_ECC_BCH
106#include "bcm_umi_bch.c"
107#else
108#include "bcm_umi_hamming.c"
109#endif
110
111#if USE_DMA
112
113/* Handler called when the DMA finishes. */
114static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
115{
116 complete(&nand_comp);
117}
118
119static int nand_dma_init(void)
120{
121 int rc;
122
123 rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
124 nand_dma_handler, NULL);
125 if (rc != 0) {
126 printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
127 return rc;
128 }
129
130 virtPtr =
131 dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
132 if (virtPtr == NULL) {
133 printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
134 return -ENOMEM;
135 }
136
137 return 0;
138}
139
140static void nand_dma_term(void)
141{
142 if (virtPtr != NULL)
143 dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
144}
145
146static void nand_dma_read(void *buf, int len)
147{
148 int offset = 0;
149 int tmp_len = 0;
150 int len_left = len;
151 DMA_Handle_t hndl;
152
153 if (virtPtr == NULL)
154 panic("nand_dma_read: virtPtr == NULL\n");
155
156 if ((void *)physPtr == NULL)
157 panic("nand_dma_read: physPtr == NULL\n");
158
159 hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
160 if (hndl < 0) {
161 printk(KERN_ERR
162 "nand_dma_read: unable to allocate dma channel: %d\n",
163 (int)hndl);
164 panic("\n");
165 }
166
167 while (len_left > 0) {
168 if (len_left > DMA_MAX_LEN) {
169 tmp_len = DMA_MAX_LEN;
170 len_left -= DMA_MAX_LEN;
171 } else {
172 tmp_len = len_left;
173 len_left = 0;
174 }
175
176 init_completion(&nand_comp);
177 dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
178 physPtr + offset, tmp_len);
179 wait_for_completion(&nand_comp);
180
181 offset += tmp_len;
182 }
183
184 dma_free_channel(hndl);
185
186 if (buf != NULL)
187 memcpy(buf, virtPtr, len);
188}
189
190static void nand_dma_write(const void *buf, int len)
191{
192 int offset = 0;
193 int tmp_len = 0;
194 int len_left = len;
195 DMA_Handle_t hndl;
196
197 if (buf == NULL)
198 panic("nand_dma_write: buf == NULL\n");
199
200 if (virtPtr == NULL)
201 panic("nand_dma_write: virtPtr == NULL\n");
202
203 if ((void *)physPtr == NULL)
204 panic("nand_dma_write: physPtr == NULL\n");
205
206 memcpy(virtPtr, buf, len);
207
208
209 hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
210 if (hndl < 0) {
211 printk(KERN_ERR
212 "nand_dma_write: unable to allocate dma channel: %d\n",
213 (int)hndl);
214 panic("\n");
215 }
216
217 while (len_left > 0) {
218 if (len_left > DMA_MAX_LEN) {
219 tmp_len = DMA_MAX_LEN;
220 len_left -= DMA_MAX_LEN;
221 } else {
222 tmp_len = len_left;
223 len_left = 0;
224 }
225
226 init_completion(&nand_comp);
227 dma_transfer_mem_to_mem(hndl, physPtr + offset,
228 REG_NAND_DATA_PADDR, tmp_len);
229 wait_for_completion(&nand_comp);
230
231 offset += tmp_len;
232 }
233
234 dma_free_channel(hndl);
235}
236
237#endif
238
239static int nand_dev_ready(struct mtd_info *mtd)
240{
241 return nand_bcm_umi_dev_ready();
242}
243
244/****************************************************************************
245*
246* bcm_umi_nand_inithw
247*
248* This routine does the necessary hardware (board-specific)
249* initializations. This includes setting up the timings, etc.
250*
251***************************************************************************/
252int bcm_umi_nand_inithw(void)
253{
254 /* Configure nand timing parameters */
255 REG_UMI_NAND_TCR &= ~0x7ffff;
256 REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
257
258#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
259 /* enable software control of CS */
260 REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
261#endif
262
263 /* keep NAND chip select asserted */
264 REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
265
266 REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
267 /* enable writes to flash */
268 REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
269
270 writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
271 nand_bcm_umi_wait_till_ready();
272
273#if NAND_ECC_BCH
274 nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
275#endif
276
277 return 0;
278}
279
280/* Used to turn latch the proper register for access. */
281static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
282 unsigned int ctrl)
283{
284 /* send command to hardware */
285 struct nand_chip *chip = mtd->priv;
286 if (ctrl & NAND_CTRL_CHANGE) {
287 if (ctrl & NAND_CLE) {
288 chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
289 goto CMD;
290 }
291 if (ctrl & NAND_ALE) {
292 chip->IO_ADDR_W =
293 bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
294 goto CMD;
295 }
296 chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
297 }
298
299CMD:
300 /* Send command to chip directly */
301 if (cmd != NAND_CMD_NONE)
302 writeb(cmd, chip->IO_ADDR_W);
303}
304
305static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
306 int len)
307{
308 if (USE_DIRECT_IO(len)) {
309 /* Do it the old way if the buffer is small or too large.
310 * Probably quicker than starting and checking dma. */
311 int i;
312 struct nand_chip *this = mtd->priv;
313
314 for (i = 0; i < len; i++)
315 writeb(buf[i], this->IO_ADDR_W);
316 }
317#if USE_DMA
318 else
319 nand_dma_write(buf, len);
320#endif
321}
322
323static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
324{
325 if (USE_DIRECT_IO(len)) {
326 int i;
327 struct nand_chip *this = mtd->priv;
328
329 for (i = 0; i < len; i++)
330 buf[i] = readb(this->IO_ADDR_R);
331 }
332#if USE_DMA
333 else
334 nand_dma_read(buf, len);
335#endif
336}
337
338static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
339static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
340 int len)
341{
342 /*
343 * Try to readback page with ECC correction. This is necessary
344 * for MLC parts which may have permanently stuck bits.
345 */
346 struct nand_chip *chip = mtd->priv;
347 int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0);
348 if (ret < 0)
349 return -EFAULT;
350 else {
351 if (memcmp(readbackbuf, buf, len) == 0)
352 return 0;
353
354 return -EFAULT;
355 }
356 return 0;
357}
358
359static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
360{
361 struct nand_chip *this;
362 struct resource *r;
363 int err = 0;
364
365 printk(gBanner);
366
367 /* Allocate memory for MTD device structure and private data */
368 board_mtd =
369 kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
370 GFP_KERNEL);
371 if (!board_mtd) {
372 printk(KERN_WARNING
373 "Unable to allocate NAND MTD device structure.\n");
374 return -ENOMEM;
375 }
376
377 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
378
379 if (!r)
380 return -ENXIO;
381
382 /* map physical address */
383 bcm_umi_io_base = ioremap(r->start, resource_size(r));
384
385 if (!bcm_umi_io_base) {
386 printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
387 kfree(board_mtd);
388 return -EIO;
389 }
390
391 /* Get pointer to private data */
392 this = (struct nand_chip *)(&board_mtd[1]);
393
394 /* Initialize structures */
395 memset((char *)board_mtd, 0, sizeof(struct mtd_info));
396 memset((char *)this, 0, sizeof(struct nand_chip));
397
398 /* Link the private data with the MTD structure */
399 board_mtd->priv = this;
400
401 /* Initialize the NAND hardware. */
402 if (bcm_umi_nand_inithw() < 0) {
403 printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
404 iounmap(bcm_umi_io_base);
405 kfree(board_mtd);
406 return -EIO;
407 }
408
409 /* Set address of NAND IO lines */
410 this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
411 this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
412
413 /* Set command delay time, see datasheet for correct value */
414 this->chip_delay = 0;
415 /* Assign the device ready function, if available */
416 this->dev_ready = nand_dev_ready;
417 this->options = 0;
418
419 this->write_buf = bcm_umi_nand_write_buf;
420 this->read_buf = bcm_umi_nand_read_buf;
421 this->verify_buf = bcm_umi_nand_verify_buf;
422
423 this->cmd_ctrl = bcm_umi_nand_hwcontrol;
424 this->ecc.mode = NAND_ECC_HW;
425 this->ecc.size = 512;
426 this->ecc.bytes = NAND_ECC_NUM_BYTES;
427#if NAND_ECC_BCH
428 this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
429 this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
430#else
431 this->ecc.correct = nand_correct_data512;
432 this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
433 this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
434#endif
435
436#if USE_DMA
437 err = nand_dma_init();
438 if (err != 0)
439 return err;
440#endif
441
442 /* Figure out the size of the device that we have.
443 * We need to do this to figure out which ECC
444 * layout we'll be using.
445 */
446
447 err = nand_scan_ident(board_mtd, 1, NULL);
448 if (err) {
449 printk(KERN_ERR "nand_scan failed: %d\n", err);
450 iounmap(bcm_umi_io_base);
451 kfree(board_mtd);
452 return err;
453 }
454
455 /* Now that we know the nand size, we can setup the ECC layout */
456
457 switch (board_mtd->writesize) { /* writesize is the pagesize */
458 case 4096:
459 this->ecc.layout = &nand_hw_eccoob_4096;
460 break;
461 case 2048:
462 this->ecc.layout = &nand_hw_eccoob_2048;
463 break;
464 case 512:
465 this->ecc.layout = &nand_hw_eccoob_512;
466 break;
467 default:
468 {
469 printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
470 board_mtd->writesize);
471 return -EINVAL;
472 }
473 }
474
475#if NAND_ECC_BCH
476 if (board_mtd->writesize > 512) {
477 if (this->options & NAND_USE_FLASH_BBT)
478 largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
479 this->badblock_pattern = &largepage_bbt;
480 }
481#endif
482
483 /* Now finish off the scan, now that ecc.layout has been initialized. */
484
485 err = nand_scan_tail(board_mtd);
486 if (err) {
487 printk(KERN_ERR "nand_scan failed: %d\n", err);
488 iounmap(bcm_umi_io_base);
489 kfree(board_mtd);
490 return err;
491 }
492
493 /* Register the partitions */
494 {
495 int nr_partitions;
496 struct mtd_partition *partition_info;
497
498 board_mtd->name = "bcm_umi-nand";
499 nr_partitions =
500 parse_mtd_partitions(board_mtd, part_probes,
501 &partition_info, 0);
502
503 if (nr_partitions <= 0) {
504 printk(KERN_ERR "BCM UMI NAND: Too few partitions - %d\n",
505 nr_partitions);
506 iounmap(bcm_umi_io_base);
507 kfree(board_mtd);
508 return -EIO;
509 }
510 mtd_device_register(board_mtd, partition_info, nr_partitions);
511 }
512
513 /* Return happy */
514 return 0;
515}
516
517static int bcm_umi_nand_remove(struct platform_device *pdev)
518{
519#if USE_DMA
520 nand_dma_term();
521#endif
522
523 /* Release resources, unregister device */
524 nand_release(board_mtd);
525
526 /* unmap physical address */
527 iounmap(bcm_umi_io_base);
528
529 /* Free the MTD device structure */
530 kfree(board_mtd);
531
532 return 0;
533}
534
535#ifdef CONFIG_PM
536static int bcm_umi_nand_suspend(struct platform_device *pdev,
537 pm_message_t state)
538{
539 printk(KERN_ERR "MTD NAND suspend is being called\n");
540 return 0;
541}
542
543static int bcm_umi_nand_resume(struct platform_device *pdev)
544{
545 printk(KERN_ERR "MTD NAND resume is being called\n");
546 return 0;
547}
548#else
549#define bcm_umi_nand_suspend NULL
550#define bcm_umi_nand_resume NULL
551#endif
552
553static struct platform_driver nand_driver = {
554 .driver = {
555 .name = "bcm-nand",
556 .owner = THIS_MODULE,
557 },
558 .probe = bcm_umi_nand_probe,
559 .remove = bcm_umi_nand_remove,
560 .suspend = bcm_umi_nand_suspend,
561 .resume = bcm_umi_nand_resume,
562};
563
564static int __init nand_init(void)
565{
566 return platform_driver_register(&nand_driver);
567}
568
569static void __exit nand_exit(void)
570{
571 platform_driver_unregister(&nand_driver);
572}
573
574module_init(nand_init);
575module_exit(nand_exit);
576
577MODULE_LICENSE("GPL");
578MODULE_AUTHOR("Broadcom");
579MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
diff --git a/drivers/mtd/nand/edb7312.c b/drivers/mtd/nand/edb7312.c
new file mode 100644
index 00000000000..8400d0f6dad
--- /dev/null
+++ b/drivers/mtd/nand/edb7312.c
@@ -0,0 +1,203 @@
1/*
2 * drivers/mtd/nand/edb7312.c
3 *
4 * Copyright (C) 2002 Marius Gröger (mag@sysgo.de)
5 *
6 * Derived from drivers/mtd/nand/autcpu12.c
7 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Overview:
14 * This is a device driver for the NAND flash device found on the
15 * CLEP7312 board which utilizes the Toshiba TC58V64AFT part. This is
16 * a 64Mibit (8MiB x 8 bits) NAND flash device.
17 */
18
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/nand.h>
24#include <linux/mtd/partitions.h>
25#include <asm/io.h>
26#include <mach/hardware.h> /* for CLPS7111_VIRT_BASE */
27#include <asm/sizes.h>
28#include <asm/hardware/clps7111.h>
29
30/*
31 * MTD structure for EDB7312 board
32 */
33static struct mtd_info *ep7312_mtd = NULL;
34
35/*
36 * Values specific to the EDB7312 board (used with EP7312 processor)
37 */
38#define EP7312_FIO_PBASE 0x10000000 /* Phys address of flash */
39#define EP7312_PXDR 0x0001 /*
40 * IO offset to Port B data register
41 * where the CLE, ALE and NCE pins
42 * are wired to.
43 */
44#define EP7312_PXDDR 0x0041 /*
45 * IO offset to Port B data direction
46 * register so we can control the IO
47 * lines.
48 */
49
50/*
51 * Module stuff
52 */
53
54static unsigned long ep7312_fio_pbase = EP7312_FIO_PBASE;
55static void __iomem *ep7312_pxdr = (void __iomem *)EP7312_PXDR;
56static void __iomem *ep7312_pxddr = (void __iomem *)EP7312_PXDDR;
57
58/*
59 * Define static partitions for flash device
60 */
61static struct mtd_partition partition_info[] = {
62 {.name = "EP7312 Nand Flash",
63 .offset = 0,
64 .size = 8 * 1024 * 1024}
65};
66
67#define NUM_PARTITIONS 1
68
69/*
70 * hardware specific access to control-lines
71 *
72 * NAND_NCE: bit 0 -> bit 6 (bit 7 = 1)
73 * NAND_CLE: bit 1 -> bit 4
74 * NAND_ALE: bit 2 -> bit 5
75 */
76static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
77{
78 struct nand_chip *chip = mtd->priv;
79
80 if (ctrl & NAND_CTRL_CHANGE) {
81 unsigned char bits = 0x80;
82
83 bits |= (ctrl & (NAND_CLE | NAND_ALE)) << 3;
84 bits |= (ctrl & NAND_NCE) ? 0x00 : 0x40;
85
86 clps_writeb((clps_readb(ep7312_pxdr) & 0xF0) | bits,
87 ep7312_pxdr);
88 }
89 if (cmd != NAND_CMD_NONE)
90 writeb(cmd, chip->IO_ADDR_W);
91}
92
93/*
94 * read device ready pin
95 */
96static int ep7312_device_ready(struct mtd_info *mtd)
97{
98 return 1;
99}
100
101const char *part_probes[] = { "cmdlinepart", NULL };
102
103/*
104 * Main initialization routine
105 */
106static int __init ep7312_init(void)
107{
108 struct nand_chip *this;
109 const char *part_type = 0;
110 int mtd_parts_nb = 0;
111 struct mtd_partition *mtd_parts = 0;
112 void __iomem *ep7312_fio_base;
113
114 /* Allocate memory for MTD device structure and private data */
115 ep7312_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
116 if (!ep7312_mtd) {
117 printk("Unable to allocate EDB7312 NAND MTD device structure.\n");
118 return -ENOMEM;
119 }
120
121 /* map physical address */
122 ep7312_fio_base = ioremap(ep7312_fio_pbase, SZ_1K);
123 if (!ep7312_fio_base) {
124 printk("ioremap EDB7312 NAND flash failed\n");
125 kfree(ep7312_mtd);
126 return -EIO;
127 }
128
129 /* Get pointer to private data */
130 this = (struct nand_chip *)(&ep7312_mtd[1]);
131
132 /* Initialize structures */
133 memset(ep7312_mtd, 0, sizeof(struct mtd_info));
134 memset(this, 0, sizeof(struct nand_chip));
135
136 /* Link the private data with the MTD structure */
137 ep7312_mtd->priv = this;
138 ep7312_mtd->owner = THIS_MODULE;
139
140 /*
141 * Set GPIO Port B control register so that the pins are configured
142 * to be outputs for controlling the NAND flash.
143 */
144 clps_writeb(0xf0, ep7312_pxddr);
145
146 /* insert callbacks */
147 this->IO_ADDR_R = ep7312_fio_base;
148 this->IO_ADDR_W = ep7312_fio_base;
149 this->cmd_ctrl = ep7312_hwcontrol;
150 this->dev_ready = ep7312_device_ready;
151 /* 15 us command delay time */
152 this->chip_delay = 15;
153
154 /* Scan to find existence of the device */
155 if (nand_scan(ep7312_mtd, 1)) {
156 iounmap((void *)ep7312_fio_base);
157 kfree(ep7312_mtd);
158 return -ENXIO;
159 }
160 ep7312_mtd->name = "edb7312-nand";
161 mtd_parts_nb = parse_mtd_partitions(ep7312_mtd, part_probes, &mtd_parts, 0);
162 if (mtd_parts_nb > 0)
163 part_type = "command line";
164 else
165 mtd_parts_nb = 0;
166 if (mtd_parts_nb == 0) {
167 mtd_parts = partition_info;
168 mtd_parts_nb = NUM_PARTITIONS;
169 part_type = "static";
170 }
171
172 /* Register the partitions */
173 printk(KERN_NOTICE "Using %s partition definition\n", part_type);
174 mtd_device_register(ep7312_mtd, mtd_parts, mtd_parts_nb);
175
176 /* Return happy */
177 return 0;
178}
179
180module_init(ep7312_init);
181
182/*
183 * Clean up routine
184 */
185static void __exit ep7312_cleanup(void)
186{
187 struct nand_chip *this = (struct nand_chip *)&ep7312_mtd[1];
188
189 /* Release resources, unregister device */
190 nand_release(ap7312_mtd);
191
192 /* Release io resource */
193 iounmap(this->IO_ADDR_R);
194
195 /* Free the MTD device structure */
196 kfree(ep7312_mtd);
197}
198
199module_exit(ep7312_cleanup);
200
201MODULE_LICENSE("GPL");
202MODULE_AUTHOR("Marius Groeger <mag@sysgo.de>");
203MODULE_DESCRIPTION("MTD map driver for Cogent EDB7312 board");
diff --git a/drivers/mtd/nand/nand_bcm_umi.c b/drivers/mtd/nand/nand_bcm_umi.c
new file mode 100644
index 00000000000..46a6bc9c4b7
--- /dev/null
+++ b/drivers/mtd/nand/nand_bcm_umi.c
@@ -0,0 +1,149 @@
1/*****************************************************************************
2* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include <mach/reg_umi.h>
17#include "nand_bcm_umi.h"
18#ifdef BOOT0_BUILD
19#include <uart.h>
20#endif
21
22/* ---- External Variable Declarations ----------------------------------- */
23/* ---- External Function Prototypes ------------------------------------- */
24/* ---- Public Variables ------------------------------------------------- */
25/* ---- Private Constants and Types -------------------------------------- */
26/* ---- Private Function Prototypes -------------------------------------- */
27/* ---- Private Variables ------------------------------------------------ */
28/* ---- Private Functions ------------------------------------------------ */
29
30#if NAND_ECC_BCH
31/****************************************************************************
32* nand_bch_ecc_flip_bit - Routine to flip an errored bit
33*
34* PURPOSE:
35* This is a helper routine that flips the bit (0 -> 1 or 1 -> 0) of the
36* errored bit specified
37*
38* PARAMETERS:
39* datap - Container that holds the 512 byte data
40* errorLocation - Location of the bit that needs to be flipped
41*
42* RETURNS:
43* None
44****************************************************************************/
45static void nand_bcm_umi_bch_ecc_flip_bit(uint8_t *datap, int errorLocation)
46{
47 int locWithinAByte = (errorLocation & REG_UMI_BCH_ERR_LOC_BYTE) >> 0;
48 int locWithinAWord = (errorLocation & REG_UMI_BCH_ERR_LOC_WORD) >> 3;
49 int locWithinAPage = (errorLocation & REG_UMI_BCH_ERR_LOC_PAGE) >> 5;
50
51 uint8_t errorByte = 0;
52 uint8_t byteMask = 1 << locWithinAByte;
53
54 /* BCH uses big endian, need to change the location
55 * bits to little endian */
56 locWithinAWord = 3 - locWithinAWord;
57
58 errorByte = datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord];
59
60#ifdef BOOT0_BUILD
61 puthexs("\nECC Correct Offset: ",
62 locWithinAPage * sizeof(uint32_t) + locWithinAWord);
63 puthexs(" errorByte:", errorByte);
64 puthex8(" Bit: ", locWithinAByte);
65#endif
66
67 if (errorByte & byteMask) {
68 /* bit needs to be cleared */
69 errorByte &= ~byteMask;
70 } else {
71 /* bit needs to be set */
72 errorByte |= byteMask;
73 }
74
75 /* write back the value with the fixed bit */
76 datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord] = errorByte;
77}
78
79/****************************************************************************
80* nand_correct_page_bch - Routine to correct bit errors when reading NAND
81*
82* PURPOSE:
83* This routine reads the BCH registers to determine if there are any bit
84* errors during the read of the last 512 bytes of data + ECC bytes. If
85* errors exists, the routine fixes it.
86*
87* PARAMETERS:
88* datap - Container that holds the 512 byte data
89*
90* RETURNS:
91* 0 or greater = Number of errors corrected
92* (No errors are found or errors have been fixed)
93* -1 = Error(s) cannot be fixed
94****************************************************************************/
95int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
96 int numEccBytes)
97{
98 int numErrors;
99 int errorLocation;
100 int idx;
101 uint32_t regValue;
102
103 /* wait for read ECC to be valid */
104 regValue = nand_bcm_umi_bch_poll_read_ecc_calc();
105
106 /*
107 * read the control status register to determine if there
108 * are error'ed bits
109 * see if errors are correctible
110 */
111 if ((regValue & REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR) > 0) {
112 int i;
113
114 for (i = 0; i < numEccBytes; i++) {
115 if (readEccData[i] != 0xff) {
116 /* errors cannot be fixed, return -1 */
117 return -1;
118 }
119 }
120 /* If ECC is unprogrammed then we can't correct,
121 * assume everything OK */
122 return 0;
123 }
124
125 if ((regValue & REG_UMI_BCH_CTRL_STATUS_CORR_ERR) == 0) {
126 /* no errors */
127 return 0;
128 }
129
130 /*
131 * Fix errored bits by doing the following:
132 * 1. Read the number of errors in the control and status register
133 * 2. Read the error location registers that corresponds to the number
134 * of errors reported
135 * 3. Invert the bit in the data
136 */
137 numErrors = (regValue & REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR) >> 20;
138
139 for (idx = 0; idx < numErrors; idx++) {
140 errorLocation =
141 REG_UMI_BCH_ERR_LOC_ADDR(idx) & REG_UMI_BCH_ERR_LOC_MASK;
142
143 /* Flip bit */
144 nand_bcm_umi_bch_ecc_flip_bit(datap, errorLocation);
145 }
146 /* Errors corrected */
147 return numErrors;
148}
149#endif
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
new file mode 100644
index 00000000000..198b304d6f7
--- /dev/null
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -0,0 +1,337 @@
1/*****************************************************************************
2* Copyright 2003 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14#ifndef NAND_BCM_UMI_H
15#define NAND_BCM_UMI_H
16
17/* ---- Include Files ---------------------------------------------------- */
18#include <mach/reg_umi.h>
19#include <mach/reg_nand.h>
20#include <cfg_global.h>
21
22/* ---- Constants and Types ---------------------------------------------- */
23#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
24#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0)
25#else
26#define NAND_ECC_BCH 0
27#endif
28
29#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES 13
30
31#if NAND_ECC_BCH
32#ifdef BOOT0_BUILD
33#define NAND_ECC_NUM_BYTES 13
34#else
35#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES
36#endif
37#else
38#define NAND_ECC_NUM_BYTES 3
39#endif
40
41#define NAND_DATA_ACCESS_SIZE 512
42
43/* ---- Variable Externs ------------------------------------------ */
44/* ---- Function Prototypes --------------------------------------- */
45int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
46 int numEccBytes);
47
48/* Check in device is ready */
49static inline int nand_bcm_umi_dev_ready(void)
50{
51 return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
52}
53
54/* Wait until device is ready */
55static inline void nand_bcm_umi_wait_till_ready(void)
56{
57 while (nand_bcm_umi_dev_ready() == 0)
58 ;
59}
60
61/* Enable Hamming ECC */
62static inline void nand_bcm_umi_hamming_enable_hwecc(void)
63{
64 /* disable and reset ECC, 512 byte page */
65 REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
66 REG_UMI_NAND_ECC_CSR_256BYTE);
67 /* enable ECC */
68 REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
69}
70
71#if NAND_ECC_BCH
72/* BCH ECC specifics */
73#define ECC_BITS_PER_CORRECTABLE_BIT 13
74
75/* Enable BCH Read ECC */
76static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
77{
78 /* disable and reset ECC */
79 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
80 /* Turn on ECC */
81 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
82}
83
84/* Enable BCH Write ECC */
85static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
86{
87 /* disable and reset ECC */
88 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
89 /* Turn on ECC */
90 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
91}
92
93/* Config number of BCH ECC bytes */
94static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
95{
96 uint32_t nValue;
97 uint32_t tValue;
98 uint32_t kValue;
99 uint32_t numBits = numEccBytes * 8;
100
101 /* disable and reset ECC */
102 REG_UMI_BCH_CTRL_STATUS =
103 REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
104 REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
105
106 /* Every correctible bit requires 13 ECC bits */
107 tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
108
109 /* Total data in number of bits for generating and computing BCH ECC */
110 nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8;
111
112 /* K parameter is used internally. K = N - (T * 13) */
113 kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
114
115 /* Write the settings */
116 REG_UMI_BCH_N = nValue;
117 REG_UMI_BCH_T = tValue;
118 REG_UMI_BCH_K = kValue;
119}
120
121/* Pause during ECC read calculation to skip bytes in OOB */
122static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
123{
124 REG_UMI_BCH_CTRL_STATUS =
125 REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
126 REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
127}
128
129/* Resume during ECC read calculation after skipping bytes in OOB */
130static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
131{
132 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
133}
134
135/* Poll read ECC calc to check when hardware completes */
136static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
137{
138 uint32_t regVal;
139
140 do {
141 /* wait for ECC to be valid */
142 regVal = REG_UMI_BCH_CTRL_STATUS;
143 } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
144
145 return regVal;
146}
147
148/* Poll write ECC calc to check when hardware completes */
149static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
150{
151 /* wait for ECC to be valid */
152 while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
153 == 0)
154 ;
155}
156
157/* Read the OOB and ECC, for kernel write OOB to a buffer */
158#if defined(__KERNEL__) && !defined(STANDALONE)
159static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
160 uint8_t *eccCalc, int numEccBytes, uint8_t *oobp)
161#else
162static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
163 uint8_t *eccCalc, int numEccBytes)
164#endif
165{
166 int eccPos = 0;
167 int numToRead = 16; /* There are 16 bytes per sector in the OOB */
168
169 /* ECC is already paused when this function is called */
170 if (pageSize != NAND_DATA_ACCESS_SIZE) {
171 /* skip BI */
172#if defined(__KERNEL__) && !defined(STANDALONE)
173 *oobp++ = REG_NAND_DATA8;
174#else
175 REG_NAND_DATA8;
176#endif
177 numToRead--;
178 }
179
180 while (numToRead > numEccBytes) {
181 /* skip free oob region */
182#if defined(__KERNEL__) && !defined(STANDALONE)
183 *oobp++ = REG_NAND_DATA8;
184#else
185 REG_NAND_DATA8;
186#endif
187 numToRead--;
188 }
189
190 if (pageSize == NAND_DATA_ACCESS_SIZE) {
191 /* read ECC bytes before BI */
192 nand_bcm_umi_bch_resume_read_ecc_calc();
193
194 while (numToRead > 11) {
195#if defined(__KERNEL__) && !defined(STANDALONE)
196 *oobp = REG_NAND_DATA8;
197 eccCalc[eccPos++] = *oobp;
198 oobp++;
199#else
200 eccCalc[eccPos++] = REG_NAND_DATA8;
201#endif
202 numToRead--;
203 }
204
205 nand_bcm_umi_bch_pause_read_ecc_calc();
206
207 if (numToRead == 11) {
208 /* read BI */
209#if defined(__KERNEL__) && !defined(STANDALONE)
210 *oobp++ = REG_NAND_DATA8;
211#else
212 REG_NAND_DATA8;
213#endif
214 numToRead--;
215 }
216
217 }
218 /* read ECC bytes */
219 nand_bcm_umi_bch_resume_read_ecc_calc();
220 while (numToRead) {
221#if defined(__KERNEL__) && !defined(STANDALONE)
222 *oobp = REG_NAND_DATA8;
223 eccCalc[eccPos++] = *oobp;
224 oobp++;
225#else
226 eccCalc[eccPos++] = REG_NAND_DATA8;
227#endif
228 numToRead--;
229 }
230}
231
232/* Helper function to write ECC */
233static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos,
234 uint8_t *oobp, uint8_t eccVal)
235{
236 if (eccBytePos <= numEccBytes)
237 *oobp = eccVal;
238}
239
240/* Write OOB with ECC */
241static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
242 uint8_t *oobp, int numEccBytes)
243{
244 uint32_t eccVal = 0xffffffff;
245
246 /* wait for write ECC to be valid */
247 nand_bcm_umi_bch_poll_write_ecc_calc();
248
249 /*
250 ** Get the hardware ecc from the 32-bit result registers.
251 ** Read after 512 byte accesses. Format B3B2B1B0
252 ** where B3 = ecc3, etc.
253 */
254
255 if (pageSize == NAND_DATA_ACCESS_SIZE) {
256 /* Now fill in the ECC bytes */
257 if (numEccBytes >= 13)
258 eccVal = REG_UMI_BCH_WR_ECC_3;
259
260 /* Usually we skip CM in oob[0,1] */
261 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
262 (eccVal >> 16) & 0xff);
263 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1],
264 (eccVal >> 8) & 0xff);
265
266 /* Write ECC in oob[2,3,4] */
267 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2],
268 eccVal & 0xff); /* ECC 12 */
269
270 if (numEccBytes >= 9)
271 eccVal = REG_UMI_BCH_WR_ECC_2;
272
273 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
274 (eccVal >> 24) & 0xff); /* ECC11 */
275 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4],
276 (eccVal >> 16) & 0xff); /* ECC10 */
277
278 /* Always Skip BI in oob[5] */
279 } else {
280 /* Always Skip BI in oob[0] */
281
282 /* Now fill in the ECC bytes */
283 if (numEccBytes >= 13)
284 eccVal = REG_UMI_BCH_WR_ECC_3;
285
286 /* Usually skip CM in oob[1,2] */
287 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
288 (eccVal >> 16) & 0xff);
289 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2],
290 (eccVal >> 8) & 0xff);
291
292 /* Write ECC in oob[3-15] */
293 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3],
294 eccVal & 0xff); /* ECC12 */
295
296 if (numEccBytes >= 9)
297 eccVal = REG_UMI_BCH_WR_ECC_2;
298
299 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
300 (eccVal >> 24) & 0xff); /* ECC11 */
301 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5],
302 (eccVal >> 16) & 0xff); /* ECC10 */
303 }
304
305 /* Fill in the remainder of ECC locations */
306 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6],
307 (eccVal >> 8) & 0xff); /* ECC9 */
308 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7],
309 eccVal & 0xff); /* ECC8 */
310
311 if (numEccBytes >= 5)
312 eccVal = REG_UMI_BCH_WR_ECC_1;
313
314 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
315 (eccVal >> 24) & 0xff); /* ECC7 */
316 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9],
317 (eccVal >> 16) & 0xff); /* ECC6 */
318 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10],
319 (eccVal >> 8) & 0xff); /* ECC5 */
320 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11],
321 eccVal & 0xff); /* ECC4 */
322
323 if (numEccBytes >= 1)
324 eccVal = REG_UMI_BCH_WR_ECC_0;
325
326 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
327 (eccVal >> 24) & 0xff); /* ECC3 */
328 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13],
329 (eccVal >> 16) & 0xff); /* ECC2 */
330 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14],
331 (eccVal >> 8) & 0xff); /* ECC1 */
332 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15],
333 eccVal & 0xff); /* ECC0 */
334}
335#endif
336
337#endif /* NAND_BCM_UMI_H */
diff --git a/drivers/mtd/nand/nomadik_nand.c b/drivers/mtd/nand/nomadik_nand.c
new file mode 100644
index 00000000000..b6a5c86ab31
--- /dev/null
+++ b/drivers/mtd/nand/nomadik_nand.c
@@ -0,0 +1,246 @@
1/*
2 * drivers/mtd/nand/nomadik_nand.c
3 *
4 * Overview:
5 * Driver for on-board NAND flash on Nomadik Platforms
6 *
7 * Copyright © 2007 STMicroelectronics Pvt. Ltd.
8 * Author: Sachin Verma <sachin.verma@st.com>
9 *
10 * Copyright © 2009 Alessandro Rubini
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 */
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/types.h>
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/nand.h>
29#include <linux/mtd/nand_ecc.h>
30#include <linux/platform_device.h>
31#include <linux/mtd/partitions.h>
32#include <linux/io.h>
33#include <linux/slab.h>
34#include <mach/nand.h>
35#include <mach/fsmc.h>
36
37#include <mtd/mtd-abi.h>
38
39struct nomadik_nand_host {
40 struct mtd_info mtd;
41 struct nand_chip nand;
42 void __iomem *data_va;
43 void __iomem *cmd_va;
44 void __iomem *addr_va;
45 struct nand_bbt_descr *bbt_desc;
46};
47
48static struct nand_ecclayout nomadik_ecc_layout = {
49 .eccbytes = 3 * 4,
50 .eccpos = { /* each subpage has 16 bytes: pos 2,3,4 hosts ECC */
51 0x02, 0x03, 0x04,
52 0x12, 0x13, 0x14,
53 0x22, 0x23, 0x24,
54 0x32, 0x33, 0x34},
55 /* let's keep bytes 5,6,7 for us, just in case we change ECC algo */
56 .oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} },
57};
58
59static void nomadik_ecc_control(struct mtd_info *mtd, int mode)
60{
61 /* No need to enable hw ecc, it's on by default */
62}
63
64static void nomadik_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
65{
66 struct nand_chip *nand = mtd->priv;
67 struct nomadik_nand_host *host = nand->priv;
68
69 if (cmd == NAND_CMD_NONE)
70 return;
71
72 if (ctrl & NAND_CLE)
73 writeb(cmd, host->cmd_va);
74 else
75 writeb(cmd, host->addr_va);
76}
77
78static int nomadik_nand_probe(struct platform_device *pdev)
79{
80 struct nomadik_nand_platform_data *pdata = pdev->dev.platform_data;
81 struct nomadik_nand_host *host;
82 struct mtd_info *mtd;
83 struct nand_chip *nand;
84 struct resource *res;
85 int ret = 0;
86
87 /* Allocate memory for the device structure (and zero it) */
88 host = kzalloc(sizeof(struct nomadik_nand_host), GFP_KERNEL);
89 if (!host) {
90 dev_err(&pdev->dev, "Failed to allocate device structure.\n");
91 return -ENOMEM;
92 }
93
94 /* Call the client's init function, if any */
95 if (pdata->init)
96 ret = pdata->init();
97 if (ret < 0) {
98 dev_err(&pdev->dev, "Init function failed\n");
99 goto err;
100 }
101
102 /* ioremap three regions */
103 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
104 if (!res) {
105 ret = -EIO;
106 goto err_unmap;
107 }
108 host->addr_va = ioremap(res->start, resource_size(res));
109
110 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
111 if (!res) {
112 ret = -EIO;
113 goto err_unmap;
114 }
115 host->data_va = ioremap(res->start, resource_size(res));
116
117 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
118 if (!res) {
119 ret = -EIO;
120 goto err_unmap;
121 }
122 host->cmd_va = ioremap(res->start, resource_size(res));
123
124 if (!host->addr_va || !host->data_va || !host->cmd_va) {
125 ret = -ENOMEM;
126 goto err_unmap;
127 }
128
129 /* Link all private pointers */
130 mtd = &host->mtd;
131 nand = &host->nand;
132 mtd->priv = nand;
133 nand->priv = host;
134
135 host->mtd.owner = THIS_MODULE;
136 nand->IO_ADDR_R = host->data_va;
137 nand->IO_ADDR_W = host->data_va;
138 nand->cmd_ctrl = nomadik_cmd_ctrl;
139
140 /*
141 * This stanza declares ECC_HW but uses soft routines. It's because
142 * HW claims to make the calculation but not the correction. However,
143 * I haven't managed to get the desired data out of it until now.
144 */
145 nand->ecc.mode = NAND_ECC_SOFT;
146 nand->ecc.layout = &nomadik_ecc_layout;
147 nand->ecc.hwctl = nomadik_ecc_control;
148 nand->ecc.size = 512;
149 nand->ecc.bytes = 3;
150
151 nand->options = pdata->options;
152
153 /*
154 * Scan to find existence of the device
155 */
156 if (nand_scan(&host->mtd, 1)) {
157 ret = -ENXIO;
158 goto err_unmap;
159 }
160
161 mtd_device_register(&host->mtd, pdata->parts, pdata->nparts);
162
163 platform_set_drvdata(pdev, host);
164 return 0;
165
166 err_unmap:
167 if (host->cmd_va)
168 iounmap(host->cmd_va);
169 if (host->data_va)
170 iounmap(host->data_va);
171 if (host->addr_va)
172 iounmap(host->addr_va);
173 err:
174 kfree(host);
175 return ret;
176}
177
178/*
179 * Clean up routine
180 */
181static int nomadik_nand_remove(struct platform_device *pdev)
182{
183 struct nomadik_nand_host *host = platform_get_drvdata(pdev);
184 struct nomadik_nand_platform_data *pdata = pdev->dev.platform_data;
185
186 if (pdata->exit)
187 pdata->exit();
188
189 if (host) {
190 iounmap(host->cmd_va);
191 iounmap(host->data_va);
192 iounmap(host->addr_va);
193 kfree(host);
194 }
195 return 0;
196}
197
198static int nomadik_nand_suspend(struct device *dev)
199{
200 struct nomadik_nand_host *host = dev_get_drvdata(dev);
201 int ret = 0;
202 if (host)
203 ret = host->mtd.suspend(&host->mtd);
204 return ret;
205}
206
207static int nomadik_nand_resume(struct device *dev)
208{
209 struct nomadik_nand_host *host = dev_get_drvdata(dev);
210 if (host)
211 host->mtd.resume(&host->mtd);
212 return 0;
213}
214
215static const struct dev_pm_ops nomadik_nand_pm_ops = {
216 .suspend = nomadik_nand_suspend,
217 .resume = nomadik_nand_resume,
218};
219
220static struct platform_driver nomadik_nand_driver = {
221 .probe = nomadik_nand_probe,
222 .remove = nomadik_nand_remove,
223 .driver = {
224 .owner = THIS_MODULE,
225 .name = "nomadik_nand",
226 .pm = &nomadik_nand_pm_ops,
227 },
228};
229
230static int __init nand_nomadik_init(void)
231{
232 pr_info("Nomadik NAND driver\n");
233 return platform_driver_register(&nomadik_nand_driver);
234}
235
236static void __exit nand_nomadik_exit(void)
237{
238 platform_driver_unregister(&nomadik_nand_driver);
239}
240
241module_init(nand_nomadik_init);
242module_exit(nand_nomadik_exit);
243
244MODULE_LICENSE("GPL");
245MODULE_AUTHOR("ST Microelectronics (sachin.verma@st.com)");
246MODULE_DESCRIPTION("NAND driver for Nomadik Platform");
diff --git a/drivers/mtd/nand/spia.c b/drivers/mtd/nand/spia.c
new file mode 100644
index 00000000000..bef76cd7c24
--- /dev/null
+++ b/drivers/mtd/nand/spia.c
@@ -0,0 +1,176 @@
1/*
2 * drivers/mtd/nand/spia.c
3 *
4 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
5 *
6 *
7 * 10-29-2001 TG change to support hardwarespecific access
8 * to controllines (due to change in nand.c)
9 * page_cache added
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Overview:
16 * This is a device driver for the NAND flash device found on the
17 * SPIA board which utilizes the Toshiba TC58V64AFT part. This is
18 * a 64Mibit (8MiB x 8 bits) NAND flash device.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/slab.h>
24#include <linux/module.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h>
28#include <asm/io.h>
29
30/*
31 * MTD structure for SPIA board
32 */
33static struct mtd_info *spia_mtd = NULL;
34
35/*
36 * Values specific to the SPIA board (used with EP7212 processor)
37 */
38#define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */
39#define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */
40#define SPIA_PEDR 0x0080 /*
41 * IO offset to Port E data register
42 * where the CLE, ALE and NCE pins
43 * are wired to.
44 */
45#define SPIA_PEDDR 0x00c0 /*
46 * IO offset to Port E data direction
47 * register so we can control the IO
48 * lines.
49 */
50
51/*
52 * Module stuff
53 */
54
55static int spia_io_base = SPIA_IO_BASE;
56static int spia_fio_base = SPIA_FIO_BASE;
57static int spia_pedr = SPIA_PEDR;
58static int spia_peddr = SPIA_PEDDR;
59
60module_param(spia_io_base, int, 0);
61module_param(spia_fio_base, int, 0);
62module_param(spia_pedr, int, 0);
63module_param(spia_peddr, int, 0);
64
65/*
66 * Define partitions for flash device
67 */
68static const struct mtd_partition partition_info[] = {
69 {
70 .name = "SPIA flash partition 1",
71 .offset = 0,
72 .size = 2 * 1024 * 1024},
73 {
74 .name = "SPIA flash partition 2",
75 .offset = 2 * 1024 * 1024,
76 .size = 6 * 1024 * 1024}
77};
78
79#define NUM_PARTITIONS 2
80
81/*
82 * hardware specific access to control-lines
83 *
84 * ctrl:
85 * NAND_CNE: bit 0 -> bit 2
86 * NAND_CLE: bit 1 -> bit 0
87 * NAND_ALE: bit 2 -> bit 1
88 */
89static void spia_hwcontrol(struct mtd_info *mtd, int cmd)
90{
91 struct nand_chip *chip = mtd->priv;
92
93 if (ctrl & NAND_CTRL_CHANGE) {
94 void __iomem *addr = spia_io_base + spia_pedr;
95 unsigned char bits;
96
97 bits = (ctrl & NAND_CNE) << 2;
98 bits |= (ctrl & NAND_CLE | NAND_ALE) >> 1;
99 writeb((readb(addr) & ~0x7) | bits, addr);
100 }
101
102 if (cmd != NAND_CMD_NONE)
103 writeb(cmd, chip->IO_ADDR_W);
104}
105
106/*
107 * Main initialization routine
108 */
109static int __init spia_init(void)
110{
111 struct nand_chip *this;
112
113 /* Allocate memory for MTD device structure and private data */
114 spia_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
115 if (!spia_mtd) {
116 printk("Unable to allocate SPIA NAND MTD device structure.\n");
117 return -ENOMEM;
118 }
119
120 /* Get pointer to private data */
121 this = (struct nand_chip *)(&spia_mtd[1]);
122
123 /* Initialize structures */
124 memset(spia_mtd, 0, sizeof(struct mtd_info));
125 memset(this, 0, sizeof(struct nand_chip));
126
127 /* Link the private data with the MTD structure */
128 spia_mtd->priv = this;
129 spia_mtd->owner = THIS_MODULE;
130
131 /*
132 * Set GPIO Port E control register so that the pins are configured
133 * to be outputs for controlling the NAND flash.
134 */
135 (*(volatile unsigned char *)(spia_io_base + spia_peddr)) = 0x07;
136
137 /* Set address of NAND IO lines */
138 this->IO_ADDR_R = (void __iomem *)spia_fio_base;
139 this->IO_ADDR_W = (void __iomem *)spia_fio_base;
140 /* Set address of hardware control function */
141 this->cmd_ctrl = spia_hwcontrol;
142 /* 15 us command delay time */
143 this->chip_delay = 15;
144
145 /* Scan to find existence of the device */
146 if (nand_scan(spia_mtd, 1)) {
147 kfree(spia_mtd);
148 return -ENXIO;
149 }
150
151 /* Register the partitions */
152 mtd_device_register(spia_mtd, partition_info, NUM_PARTITIONS);
153
154 /* Return happy */
155 return 0;
156}
157
158module_init(spia_init);
159
160/*
161 * Clean up routine
162 */
163static void __exit spia_cleanup(void)
164{
165 /* Release resources, unregister device */
166 nand_release(spia_mtd);
167
168 /* Free the MTD device structure */
169 kfree(spia_mtd);
170}
171
172module_exit(spia_cleanup);
173
174MODULE_LICENSE("GPL");
175MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com");
176MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on SPIA board");
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