1 files changed, 51 insertions, 51 deletions
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c
index c901fa50fea..0dd84e99081 100644
--- a/drivers/mfd/sec-irq.c
+++ b/drivers/mfd/sec-irq.c
@@ -24,67 +24,67 @@
 static struct regmap_irq s2mps11_irqs[] = {
        [S2MPS11_IRQ_PWRONF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_PWRONF_MASK,
        },
        [S2MPS11_IRQ_PWRONR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_PWRONR_MASK,
        },
        [S2MPS11_IRQ_JIGONBF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_JIGONBF_MASK,
        },
        [S2MPS11_IRQ_JIGONBR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_JIGONBR_MASK,
        },
        [S2MPS11_IRQ_ACOKBF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_ACOKBF_MASK,
        },
        [S2MPS11_IRQ_ACOKBR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_ACOKBR_MASK,
        },
        [S2MPS11_IRQ_PWRON1S] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_PWRON1S_MASK,
        },
        [S2MPS11_IRQ_MRB] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S2MPS11_IRQ_MRB_MASK,
        },
        [S2MPS11_IRQ_RTC60S] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S2MPS11_IRQ_RTC60S_MASK,
        },
        [S2MPS11_IRQ_RTCA1] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S2MPS11_IRQ_RTCA1_MASK,
        },
        [S2MPS11_IRQ_RTCA2] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S2MPS11_IRQ_RTCA2_MASK,
        },
        [S2MPS11_IRQ_SMPL] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S2MPS11_IRQ_SMPL_MASK,
        },
        [S2MPS11_IRQ_RTC1S] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S2MPS11_IRQ_RTC1S_MASK,
        },
        [S2MPS11_IRQ_WTSR] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S2MPS11_IRQ_WTSR_MASK,
        },
        [S2MPS11_IRQ_INT120C] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S2MPS11_IRQ_INT120C_MASK,
        },
        [S2MPS11_IRQ_INT140C] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S2MPS11_IRQ_INT140C_MASK,
        },
 };
@@ -92,146 +92,146 @@ static struct regmap_irq s2mps11_irqs[] = {
 static struct regmap_irq s5m8767_irqs[] = {
        [S5M8767_IRQ_PWRR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8767_IRQ_PWRR_MASK,
        },
        [S5M8767_IRQ_PWRF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8767_IRQ_PWRF_MASK,
        },
        [S5M8767_IRQ_PWR1S] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8767_IRQ_PWR1S_MASK,
        },
        [S5M8767_IRQ_JIGR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8767_IRQ_JIGR_MASK,
        },
        [S5M8767_IRQ_JIGF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8767_IRQ_JIGF_MASK,
        },
        [S5M8767_IRQ_LOWBAT2] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8767_IRQ_LOWBAT2_MASK,
        },
        [S5M8767_IRQ_LOWBAT1] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8767_IRQ_LOWBAT1_MASK,
        },
        [S5M8767_IRQ_MRB] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8767_IRQ_MRB_MASK,
        },
        [S5M8767_IRQ_DVSOK2] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8767_IRQ_DVSOK2_MASK,
        },
        [S5M8767_IRQ_DVSOK3] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8767_IRQ_DVSOK3_MASK,
        },
        [S5M8767_IRQ_DVSOK4] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8767_IRQ_DVSOK4_MASK,
        },
        [S5M8767_IRQ_RTC60S] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8767_IRQ_RTC60S_MASK,
        },
        [S5M8767_IRQ_RTCA1] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8767_IRQ_RTCA1_MASK,
        },
        [S5M8767_IRQ_RTCA2] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8767_IRQ_RTCA2_MASK,
        },
        [S5M8767_IRQ_SMPL] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8767_IRQ_SMPL_MASK,
        },
        [S5M8767_IRQ_RTC1S] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8767_IRQ_RTC1S_MASK,
        },
        [S5M8767_IRQ_WTSR] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8767_IRQ_WTSR_MASK,
        },
 };
 static struct regmap_irq s5m8763_irqs[] = {
        [S5M8763_IRQ_DCINF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8763_IRQ_DCINF_MASK,
        },
        [S5M8763_IRQ_DCINR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8763_IRQ_DCINR_MASK,
        },
        [S5M8763_IRQ_JIGF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8763_IRQ_JIGF_MASK,
        },
        [S5M8763_IRQ_JIGR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8763_IRQ_JIGR_MASK,
        },
        [S5M8763_IRQ_PWRONF] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8763_IRQ_PWRONF_MASK,
        },
        [S5M8763_IRQ_PWRONR] = {
-                .reg_offset = 1,
+                .reg_offset = 0,
                .mask = S5M8763_IRQ_PWRONR_MASK,
        },
        [S5M8763_IRQ_WTSREVNT] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8763_IRQ_WTSREVNT_MASK,
        },
        [S5M8763_IRQ_SMPLEVNT] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8763_IRQ_SMPLEVNT_MASK,
        },
        [S5M8763_IRQ_ALARM1] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8763_IRQ_ALARM1_MASK,
        },
        [S5M8763_IRQ_ALARM0] = {
-                .reg_offset = 2,
+                .reg_offset = 1,
                .mask = S5M8763_IRQ_ALARM0_MASK,
        },
        [S5M8763_IRQ_ONKEY1S] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8763_IRQ_ONKEY1S_MASK,
        },
        [S5M8763_IRQ_TOPOFFR] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8763_IRQ_TOPOFFR_MASK,
        },
        [S5M8763_IRQ_DCINOVPR] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8763_IRQ_DCINOVPR_MASK,
        },
        [S5M8763_IRQ_CHGRSTF] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8763_IRQ_CHGRSTF_MASK,
        },
        [S5M8763_IRQ_DONER] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8763_IRQ_DONER_MASK,
        },
        [S5M8763_IRQ_CHGFAULT] = {
-                .reg_offset = 3,
+                .reg_offset = 2,
                .mask = S5M8763_IRQ_CHGFAULT_MASK,
        },
        [S5M8763_IRQ_LOBAT1] = {
-                .reg_offset = 4,
+                .reg_offset = 3,
                .mask = S5M8763_IRQ_LOBAT1_MASK,
        },
        [S5M8763_IRQ_LOBAT2] = {
-                .reg_offset = 4,
+                .reg_offset = 3,
                .mask = S5M8763_IRQ_LOBAT2_MASK,
        },
 };

diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index c901fa50fea..0dd84e99081 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c
@@ -24,67 +24,67 @@
24		24
25	static struct regmap_irq s2mps11_irqs[] = {	25	static struct regmap_irq s2mps11_irqs[] = {
26	[S2MPS11_IRQ_PWRONF] = {	26	[S2MPS11_IRQ_PWRONF] = {
27	.reg_offset = 1,	27	.reg_offset = 0,
28	.mask = S2MPS11_IRQ_PWRONF_MASK,	28	.mask = S2MPS11_IRQ_PWRONF_MASK,
29	},	29	},
30	[S2MPS11_IRQ_PWRONR] = {	30	[S2MPS11_IRQ_PWRONR] = {
31	.reg_offset = 1,	31	.reg_offset = 0,
32	.mask = S2MPS11_IRQ_PWRONR_MASK,	32	.mask = S2MPS11_IRQ_PWRONR_MASK,
33	},	33	},
34	[S2MPS11_IRQ_JIGONBF] = {	34	[S2MPS11_IRQ_JIGONBF] = {
35	.reg_offset = 1,	35	.reg_offset = 0,
36	.mask = S2MPS11_IRQ_JIGONBF_MASK,	36	.mask = S2MPS11_IRQ_JIGONBF_MASK,
37	},	37	},
38	[S2MPS11_IRQ_JIGONBR] = {	38	[S2MPS11_IRQ_JIGONBR] = {
39	.reg_offset = 1,	39	.reg_offset = 0,
40	.mask = S2MPS11_IRQ_JIGONBR_MASK,	40	.mask = S2MPS11_IRQ_JIGONBR_MASK,
41	},	41	},
42	[S2MPS11_IRQ_ACOKBF] = {	42	[S2MPS11_IRQ_ACOKBF] = {
43	.reg_offset = 1,	43	.reg_offset = 0,
44	.mask = S2MPS11_IRQ_ACOKBF_MASK,	44	.mask = S2MPS11_IRQ_ACOKBF_MASK,
45	},	45	},
46	[S2MPS11_IRQ_ACOKBR] = {	46	[S2MPS11_IRQ_ACOKBR] = {
47	.reg_offset = 1,	47	.reg_offset = 0,
48	.mask = S2MPS11_IRQ_ACOKBR_MASK,	48	.mask = S2MPS11_IRQ_ACOKBR_MASK,
49	},	49	},
50	[S2MPS11_IRQ_PWRON1S] = {	50	[S2MPS11_IRQ_PWRON1S] = {
51	.reg_offset = 1,	51	.reg_offset = 0,
52	.mask = S2MPS11_IRQ_PWRON1S_MASK,	52	.mask = S2MPS11_IRQ_PWRON1S_MASK,
53	},	53	},
54	[S2MPS11_IRQ_MRB] = {	54	[S2MPS11_IRQ_MRB] = {
55	.reg_offset = 1,	55	.reg_offset = 0,
56	.mask = S2MPS11_IRQ_MRB_MASK,	56	.mask = S2MPS11_IRQ_MRB_MASK,
57	},	57	},
58	[S2MPS11_IRQ_RTC60S] = {	58	[S2MPS11_IRQ_RTC60S] = {
59	.reg_offset = 2,	59	.reg_offset = 1,
60	.mask = S2MPS11_IRQ_RTC60S_MASK,	60	.mask = S2MPS11_IRQ_RTC60S_MASK,
61	},	61	},
62	[S2MPS11_IRQ_RTCA1] = {	62	[S2MPS11_IRQ_RTCA1] = {
63	.reg_offset = 2,	63	.reg_offset = 1,
64	.mask = S2MPS11_IRQ_RTCA1_MASK,	64	.mask = S2MPS11_IRQ_RTCA1_MASK,
65	},	65	},
66	[S2MPS11_IRQ_RTCA2] = {	66	[S2MPS11_IRQ_RTCA2] = {
67	.reg_offset = 2,	67	.reg_offset = 1,
68	.mask = S2MPS11_IRQ_RTCA2_MASK,	68	.mask = S2MPS11_IRQ_RTCA2_MASK,
69	},	69	},
70	[S2MPS11_IRQ_SMPL] = {	70	[S2MPS11_IRQ_SMPL] = {
71	.reg_offset = 2,	71	.reg_offset = 1,
72	.mask = S2MPS11_IRQ_SMPL_MASK,	72	.mask = S2MPS11_IRQ_SMPL_MASK,
73	},	73	},
74	[S2MPS11_IRQ_RTC1S] = {	74	[S2MPS11_IRQ_RTC1S] = {
75	.reg_offset = 2,	75	.reg_offset = 1,
76	.mask = S2MPS11_IRQ_RTC1S_MASK,	76	.mask = S2MPS11_IRQ_RTC1S_MASK,
77	},	77	},
78	[S2MPS11_IRQ_WTSR] = {	78	[S2MPS11_IRQ_WTSR] = {
79	.reg_offset = 2,	79	.reg_offset = 1,
80	.mask = S2MPS11_IRQ_WTSR_MASK,	80	.mask = S2MPS11_IRQ_WTSR_MASK,
81	},	81	},
82	[S2MPS11_IRQ_INT120C] = {	82	[S2MPS11_IRQ_INT120C] = {
83	.reg_offset = 3,	83	.reg_offset = 2,
84	.mask = S2MPS11_IRQ_INT120C_MASK,	84	.mask = S2MPS11_IRQ_INT120C_MASK,
85	},	85	},
86	[S2MPS11_IRQ_INT140C] = {	86	[S2MPS11_IRQ_INT140C] = {
87	.reg_offset = 3,	87	.reg_offset = 2,
88	.mask = S2MPS11_IRQ_INT140C_MASK,	88	.mask = S2MPS11_IRQ_INT140C_MASK,
89	},	89	},
90	};	90	};
@@ -92,146 +92,146 @@ static struct regmap_irq s2mps11_irqs[] = {
92		92
93	static struct regmap_irq s5m8767_irqs[] = {	93	static struct regmap_irq s5m8767_irqs[] = {
94	[S5M8767_IRQ_PWRR] = {	94	[S5M8767_IRQ_PWRR] = {
95	.reg_offset = 1,	95	.reg_offset = 0,
96	.mask = S5M8767_IRQ_PWRR_MASK,	96	.mask = S5M8767_IRQ_PWRR_MASK,
97	},	97	},
98	[S5M8767_IRQ_PWRF] = {	98	[S5M8767_IRQ_PWRF] = {
99	.reg_offset = 1,	99	.reg_offset = 0,
100	.mask = S5M8767_IRQ_PWRF_MASK,	100	.mask = S5M8767_IRQ_PWRF_MASK,
101	},	101	},
102	[S5M8767_IRQ_PWR1S] = {	102	[S5M8767_IRQ_PWR1S] = {
103	.reg_offset = 1,	103	.reg_offset = 0,
104	.mask = S5M8767_IRQ_PWR1S_MASK,	104	.mask = S5M8767_IRQ_PWR1S_MASK,
105	},	105	},
106	[S5M8767_IRQ_JIGR] = {	106	[S5M8767_IRQ_JIGR] = {
107	.reg_offset = 1,	107	.reg_offset = 0,
108	.mask = S5M8767_IRQ_JIGR_MASK,	108	.mask = S5M8767_IRQ_JIGR_MASK,
109	},	109	},
110	[S5M8767_IRQ_JIGF] = {	110	[S5M8767_IRQ_JIGF] = {
111	.reg_offset = 1,	111	.reg_offset = 0,
112	.mask = S5M8767_IRQ_JIGF_MASK,	112	.mask = S5M8767_IRQ_JIGF_MASK,
113	},	113	},
114	[S5M8767_IRQ_LOWBAT2] = {	114	[S5M8767_IRQ_LOWBAT2] = {
115	.reg_offset = 1,	115	.reg_offset = 0,
116	.mask = S5M8767_IRQ_LOWBAT2_MASK,	116	.mask = S5M8767_IRQ_LOWBAT2_MASK,
117	},	117	},
118	[S5M8767_IRQ_LOWBAT1] = {	118	[S5M8767_IRQ_LOWBAT1] = {
119	.reg_offset = 1,	119	.reg_offset = 0,
120	.mask = S5M8767_IRQ_LOWBAT1_MASK,	120	.mask = S5M8767_IRQ_LOWBAT1_MASK,
121	},	121	},
122	[S5M8767_IRQ_MRB] = {	122	[S5M8767_IRQ_MRB] = {
123	.reg_offset = 2,	123	.reg_offset = 1,
124	.mask = S5M8767_IRQ_MRB_MASK,	124	.mask = S5M8767_IRQ_MRB_MASK,
125	},	125	},
126	[S5M8767_IRQ_DVSOK2] = {	126	[S5M8767_IRQ_DVSOK2] = {
127	.reg_offset = 2,	127	.reg_offset = 1,
128	.mask = S5M8767_IRQ_DVSOK2_MASK,	128	.mask = S5M8767_IRQ_DVSOK2_MASK,
129	},	129	},
130	[S5M8767_IRQ_DVSOK3] = {	130	[S5M8767_IRQ_DVSOK3] = {
131	.reg_offset = 2,	131	.reg_offset = 1,
132	.mask = S5M8767_IRQ_DVSOK3_MASK,	132	.mask = S5M8767_IRQ_DVSOK3_MASK,
133	},	133	},
134	[S5M8767_IRQ_DVSOK4] = {	134	[S5M8767_IRQ_DVSOK4] = {
135	.reg_offset = 2,	135	.reg_offset = 1,
136	.mask = S5M8767_IRQ_DVSOK4_MASK,	136	.mask = S5M8767_IRQ_DVSOK4_MASK,
137	},	137	},
138	[S5M8767_IRQ_RTC60S] = {	138	[S5M8767_IRQ_RTC60S] = {
139	.reg_offset = 3,	139	.reg_offset = 2,
140	.mask = S5M8767_IRQ_RTC60S_MASK,	140	.mask = S5M8767_IRQ_RTC60S_MASK,
141	},	141	},
142	[S5M8767_IRQ_RTCA1] = {	142	[S5M8767_IRQ_RTCA1] = {
143	.reg_offset = 3,	143	.reg_offset = 2,
144	.mask = S5M8767_IRQ_RTCA1_MASK,	144	.mask = S5M8767_IRQ_RTCA1_MASK,
145	},	145	},
146	[S5M8767_IRQ_RTCA2] = {	146	[S5M8767_IRQ_RTCA2] = {
147	.reg_offset = 3,	147	.reg_offset = 2,
148	.mask = S5M8767_IRQ_RTCA2_MASK,	148	.mask = S5M8767_IRQ_RTCA2_MASK,
149	},	149	},
150	[S5M8767_IRQ_SMPL] = {	150	[S5M8767_IRQ_SMPL] = {
151	.reg_offset = 3,	151	.reg_offset = 2,
152	.mask = S5M8767_IRQ_SMPL_MASK,	152	.mask = S5M8767_IRQ_SMPL_MASK,
153	},	153	},
154	[S5M8767_IRQ_RTC1S] = {	154	[S5M8767_IRQ_RTC1S] = {
155	.reg_offset = 3,	155	.reg_offset = 2,
156	.mask = S5M8767_IRQ_RTC1S_MASK,	156	.mask = S5M8767_IRQ_RTC1S_MASK,
157	},	157	},
158	[S5M8767_IRQ_WTSR] = {	158	[S5M8767_IRQ_WTSR] = {
159	.reg_offset = 3,	159	.reg_offset = 2,
160	.mask = S5M8767_IRQ_WTSR_MASK,	160	.mask = S5M8767_IRQ_WTSR_MASK,
161	},	161	},
162	};	162	};
163		163
164	static struct regmap_irq s5m8763_irqs[] = {	164	static struct regmap_irq s5m8763_irqs[] = {
165	[S5M8763_IRQ_DCINF] = {	165	[S5M8763_IRQ_DCINF] = {
166	.reg_offset = 1,	166	.reg_offset = 0,
167	.mask = S5M8763_IRQ_DCINF_MASK,	167	.mask = S5M8763_IRQ_DCINF_MASK,
168	},	168	},
169	[S5M8763_IRQ_DCINR] = {	169	[S5M8763_IRQ_DCINR] = {
170	.reg_offset = 1,	170	.reg_offset = 0,
171	.mask = S5M8763_IRQ_DCINR_MASK,	171	.mask = S5M8763_IRQ_DCINR_MASK,
172	},	172	},
173	[S5M8763_IRQ_JIGF] = {	173	[S5M8763_IRQ_JIGF] = {
174	.reg_offset = 1,	174	.reg_offset = 0,
175	.mask = S5M8763_IRQ_JIGF_MASK,	175	.mask = S5M8763_IRQ_JIGF_MASK,
176	},	176	},
177	[S5M8763_IRQ_JIGR] = {	177	[S5M8763_IRQ_JIGR] = {
178	.reg_offset = 1,	178	.reg_offset = 0,
179	.mask = S5M8763_IRQ_JIGR_MASK,	179	.mask = S5M8763_IRQ_JIGR_MASK,
180	},	180	},
181	[S5M8763_IRQ_PWRONF] = {	181	[S5M8763_IRQ_PWRONF] = {
182	.reg_offset = 1,	182	.reg_offset = 0,
183	.mask = S5M8763_IRQ_PWRONF_MASK,	183	.mask = S5M8763_IRQ_PWRONF_MASK,
184	},	184	},
185	[S5M8763_IRQ_PWRONR] = {	185	[S5M8763_IRQ_PWRONR] = {
186	.reg_offset = 1,	186	.reg_offset = 0,
187	.mask = S5M8763_IRQ_PWRONR_MASK,	187	.mask = S5M8763_IRQ_PWRONR_MASK,
188	},	188	},
189	[S5M8763_IRQ_WTSREVNT] = {	189	[S5M8763_IRQ_WTSREVNT] = {
190	.reg_offset = 2,	190	.reg_offset = 1,
191	.mask = S5M8763_IRQ_WTSREVNT_MASK,	191	.mask = S5M8763_IRQ_WTSREVNT_MASK,
192	},	192	},
193	[S5M8763_IRQ_SMPLEVNT] = {	193	[S5M8763_IRQ_SMPLEVNT] = {
194	.reg_offset = 2,	194	.reg_offset = 1,
195	.mask = S5M8763_IRQ_SMPLEVNT_MASK,	195	.mask = S5M8763_IRQ_SMPLEVNT_MASK,
196	},	196	},
197	[S5M8763_IRQ_ALARM1] = {	197	[S5M8763_IRQ_ALARM1] = {
198	.reg_offset = 2,	198	.reg_offset = 1,
199	.mask = S5M8763_IRQ_ALARM1_MASK,	199	.mask = S5M8763_IRQ_ALARM1_MASK,
200	},	200	},
201	[S5M8763_IRQ_ALARM0] = {	201	[S5M8763_IRQ_ALARM0] = {
202	.reg_offset = 2,	202	.reg_offset = 1,
203	.mask = S5M8763_IRQ_ALARM0_MASK,	203	.mask = S5M8763_IRQ_ALARM0_MASK,
204	},	204	},
205	[S5M8763_IRQ_ONKEY1S] = {	205	[S5M8763_IRQ_ONKEY1S] = {
206	.reg_offset = 3,	206	.reg_offset = 2,
207	.mask = S5M8763_IRQ_ONKEY1S_MASK,	207	.mask = S5M8763_IRQ_ONKEY1S_MASK,
208	},	208	},
209	[S5M8763_IRQ_TOPOFFR] = {	209	[S5M8763_IRQ_TOPOFFR] = {
210	.reg_offset = 3,	210	.reg_offset = 2,
211	.mask = S5M8763_IRQ_TOPOFFR_MASK,	211	.mask = S5M8763_IRQ_TOPOFFR_MASK,
212	},	212	},
213	[S5M8763_IRQ_DCINOVPR] = {	213	[S5M8763_IRQ_DCINOVPR] = {
214	.reg_offset = 3,	214	.reg_offset = 2,
215	.mask = S5M8763_IRQ_DCINOVPR_MASK,	215	.mask = S5M8763_IRQ_DCINOVPR_MASK,
216	},	216	},
217	[S5M8763_IRQ_CHGRSTF] = {	217	[S5M8763_IRQ_CHGRSTF] = {
218	.reg_offset = 3,	218	.reg_offset = 2,
219	.mask = S5M8763_IRQ_CHGRSTF_MASK,	219	.mask = S5M8763_IRQ_CHGRSTF_MASK,
220	},	220	},
221	[S5M8763_IRQ_DONER] = {	221	[S5M8763_IRQ_DONER] = {
222	.reg_offset = 3,	222	.reg_offset = 2,
223	.mask = S5M8763_IRQ_DONER_MASK,	223	.mask = S5M8763_IRQ_DONER_MASK,
224	},	224	},
225	[S5M8763_IRQ_CHGFAULT] = {	225	[S5M8763_IRQ_CHGFAULT] = {
226	.reg_offset = 3,	226	.reg_offset = 2,
227	.mask = S5M8763_IRQ_CHGFAULT_MASK,	227	.mask = S5M8763_IRQ_CHGFAULT_MASK,
228	},	228	},
229	[S5M8763_IRQ_LOBAT1] = {	229	[S5M8763_IRQ_LOBAT1] = {
230	.reg_offset = 4,	230	.reg_offset = 3,
231	.mask = S5M8763_IRQ_LOBAT1_MASK,	231	.mask = S5M8763_IRQ_LOBAT1_MASK,
232	},	232	},
233	[S5M8763_IRQ_LOBAT2] = {	233	[S5M8763_IRQ_LOBAT2] = {
234	.reg_offset = 4,	234	.reg_offset = 3,
235	.mask = S5M8763_IRQ_LOBAT2_MASK,	235	.mask = S5M8763_IRQ_LOBAT2_MASK,
236	},	236	},
237	};	237	};