diff options
Diffstat (limited to 'drivers/mfd/dbx500-prcmu-regs.h')
| -rw-r--r-- | drivers/mfd/dbx500-prcmu-regs.h | 130 |
1 files changed, 88 insertions, 42 deletions
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index ec22e9f15d3..3a0bf91d778 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h | |||
| @@ -17,41 +17,41 @@ | |||
| 17 | 17 | ||
| 18 | #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) | 18 | #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) |
| 19 | 19 | ||
| 20 | #define PRCM_SVACLK_MGT_OFF 0x008 | 20 | #define PRCM_CLK_MGT(_offset) (void __iomem *)(IO_ADDRESS(U8500_PRCMU_BASE) \ |
| 21 | #define PRCM_SIACLK_MGT_OFF 0x00C | 21 | + _offset) |
| 22 | #define PRCM_SGACLK_MGT_OFF 0x014 | 22 | #define PRCM_ACLK_MGT PRCM_CLK_MGT(0x004) |
| 23 | #define PRCM_UARTCLK_MGT_OFF 0x018 | 23 | #define PRCM_SVACLK_MGT PRCM_CLK_MGT(0x008) |
| 24 | #define PRCM_MSP02CLK_MGT_OFF 0x01C | 24 | #define PRCM_SIACLK_MGT PRCM_CLK_MGT(0x00C) |
| 25 | #define PRCM_I2CCLK_MGT_OFF 0x020 | 25 | #define PRCM_SGACLK_MGT PRCM_CLK_MGT(0x014) |
| 26 | #define PRCM_SDMMCCLK_MGT_OFF 0x024 | 26 | #define PRCM_UARTCLK_MGT PRCM_CLK_MGT(0x018) |
| 27 | #define PRCM_SLIMCLK_MGT_OFF 0x028 | 27 | #define PRCM_MSP02CLK_MGT PRCM_CLK_MGT(0x01C) |
| 28 | #define PRCM_PER1CLK_MGT_OFF 0x02C | 28 | #define PRCM_I2CCLK_MGT PRCM_CLK_MGT(0x020) |
| 29 | #define PRCM_PER2CLK_MGT_OFF 0x030 | 29 | #define PRCM_SDMMCCLK_MGT PRCM_CLK_MGT(0x024) |
| 30 | #define PRCM_PER3CLK_MGT_OFF 0x034 | 30 | #define PRCM_SLIMCLK_MGT PRCM_CLK_MGT(0x028) |
| 31 | #define PRCM_PER5CLK_MGT_OFF 0x038 | 31 | #define PRCM_PER1CLK_MGT PRCM_CLK_MGT(0x02C) |
| 32 | #define PRCM_PER6CLK_MGT_OFF 0x03C | 32 | #define PRCM_PER2CLK_MGT PRCM_CLK_MGT(0x030) |
| 33 | #define PRCM_PER7CLK_MGT_OFF 0x040 | 33 | #define PRCM_PER3CLK_MGT PRCM_CLK_MGT(0x034) |
| 34 | #define PRCM_PWMCLK_MGT_OFF 0x044 /* for DB5500 */ | 34 | #define PRCM_PER5CLK_MGT PRCM_CLK_MGT(0x038) |
| 35 | #define PRCM_IRDACLK_MGT_OFF 0x048 /* for DB5500 */ | 35 | #define PRCM_PER6CLK_MGT PRCM_CLK_MGT(0x03C) |
| 36 | #define PRCM_IRRCCLK_MGT_OFF 0x04C /* for DB5500 */ | 36 | #define PRCM_PER7CLK_MGT PRCM_CLK_MGT(0x040) |
| 37 | #define PRCM_LCDCLK_MGT_OFF 0x044 | 37 | #define PRCM_LCDCLK_MGT PRCM_CLK_MGT(0x044) |
| 38 | #define PRCM_BMLCLK_MGT_OFF 0x04C | 38 | #define PRCM_BMLCLK_MGT PRCM_CLK_MGT(0x04C) |
| 39 | #define PRCM_HSITXCLK_MGT_OFF 0x050 | 39 | #define PRCM_HSITXCLK_MGT PRCM_CLK_MGT(0x050) |
| 40 | #define PRCM_HSIRXCLK_MGT_OFF 0x054 | 40 | #define PRCM_HSIRXCLK_MGT PRCM_CLK_MGT(0x054) |
| 41 | #define PRCM_HDMICLK_MGT_OFF 0x058 | 41 | #define PRCM_HDMICLK_MGT PRCM_CLK_MGT(0x058) |
| 42 | #define PRCM_APEATCLK_MGT_OFF 0x05C | 42 | #define PRCM_APEATCLK_MGT PRCM_CLK_MGT(0x05C) |
| 43 | #define PRCM_APETRACECLK_MGT_OFF 0x060 | 43 | #define PRCM_APETRACECLK_MGT PRCM_CLK_MGT(0x060) |
| 44 | #define PRCM_MCDECLK_MGT_OFF 0x064 | 44 | #define PRCM_MCDECLK_MGT PRCM_CLK_MGT(0x064) |
| 45 | #define PRCM_IPI2CCLK_MGT_OFF 0x068 | 45 | #define PRCM_IPI2CCLK_MGT PRCM_CLK_MGT(0x068) |
| 46 | #define PRCM_DSIALTCLK_MGT_OFF 0x06C | 46 | #define PRCM_DSIALTCLK_MGT PRCM_CLK_MGT(0x06C) |
| 47 | #define PRCM_DMACLK_MGT_OFF 0x074 | 47 | #define PRCM_DMACLK_MGT PRCM_CLK_MGT(0x074) |
| 48 | #define PRCM_B2R2CLK_MGT_OFF 0x078 | 48 | #define PRCM_B2R2CLK_MGT PRCM_CLK_MGT(0x078) |
| 49 | #define PRCM_TVCLK_MGT_OFF 0x07C | 49 | #define PRCM_TVCLK_MGT PRCM_CLK_MGT(0x07C) |
| 50 | #define PRCM_UNIPROCLK_MGT_OFF 0x278 | 50 | #define PRCM_UNIPROCLK_MGT PRCM_CLK_MGT(0x278) |
| 51 | #define PRCM_SSPCLK_MGT_OFF 0x280 | 51 | #define PRCM_SSPCLK_MGT PRCM_CLK_MGT(0x280) |
| 52 | #define PRCM_RNGCLK_MGT_OFF 0x284 | 52 | #define PRCM_RNGCLK_MGT PRCM_CLK_MGT(0x284) |
| 53 | #define PRCM_UICCCLK_MGT_OFF 0x27C | 53 | #define PRCM_UICCCLK_MGT PRCM_CLK_MGT(0x27C) |
| 54 | #define PRCM_MSP1CLK_MGT_OFF 0x288 | 54 | #define PRCM_MSP1CLK_MGT PRCM_CLK_MGT(0x288) |
| 55 | 55 | ||
| 56 | #define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) | 56 | #define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) |
| 57 | #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f | 57 | #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f |
| @@ -79,6 +79,8 @@ | |||
| 79 | 79 | ||
| 80 | /* ARM WFI Standby signal register */ | 80 | /* ARM WFI Standby signal register */ |
| 81 | #define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130) | 81 | #define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130) |
| 82 | #define PRCM_ARM_WFI_STANDBY_WFI0 0x08 | ||
| 83 | #define PRCM_ARM_WFI_STANDBY_WFI1 0x10 | ||
| 82 | #define PRCM_IOCR (_PRCMU_BASE + 0x310) | 84 | #define PRCM_IOCR (_PRCMU_BASE + 0x310) |
| 83 | #define PRCM_IOCR_IOFORCE 0x1 | 85 | #define PRCM_IOCR_IOFORCE 0x1 |
| 84 | 86 | ||
| @@ -131,20 +133,58 @@ | |||
| 131 | #define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) | 133 | #define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) |
| 132 | #define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) | 134 | #define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) |
| 133 | 135 | ||
| 136 | #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) | ||
| 137 | #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) | ||
| 138 | |||
| 134 | /* PRCMU clock/PLL/reset registers */ | 139 | /* PRCMU clock/PLL/reset registers */ |
| 140 | #define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080) | ||
| 141 | #define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084) | ||
| 142 | #define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C) | ||
| 143 | #define PRCM_PLL_FREQ_D_SHIFT 0 | ||
| 144 | #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) | ||
| 145 | #define PRCM_PLL_FREQ_N_SHIFT 8 | ||
| 146 | #define PRCM_PLL_FREQ_N_MASK BITS(8, 13) | ||
| 147 | #define PRCM_PLL_FREQ_R_SHIFT 16 | ||
| 148 | #define PRCM_PLL_FREQ_R_MASK BITS(16, 18) | ||
| 149 | #define PRCM_PLL_FREQ_SELDIV2 BIT(24) | ||
| 150 | #define PRCM_PLL_FREQ_DIV2EN BIT(25) | ||
| 151 | |||
| 135 | #define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) | 152 | #define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) |
| 136 | #define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) | 153 | #define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) |
| 137 | #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) | 154 | #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) |
| 138 | #define PRCM_LCDCLK_MGT (_PRCMU_BASE + PRCM_LCDCLK_MGT_OFF) | ||
| 139 | #define PRCM_MCDECLK_MGT (_PRCMU_BASE + PRCM_MCDECLK_MGT_OFF) | ||
| 140 | #define PRCM_HDMICLK_MGT (_PRCMU_BASE + PRCM_HDMICLK_MGT_OFF) | ||
| 141 | #define PRCM_TVCLK_MGT (_PRCMU_BASE + PRCM_TVCLK_MGT_OFF) | ||
| 142 | #define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) | 155 | #define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) |
| 143 | #define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) | 156 | #define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) |
| 144 | #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) | 157 | #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) |
| 145 | #define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) | 158 | #define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) |
| 146 | #define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) | 159 | #define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) |
| 147 | 160 | ||
| 161 | #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) | ||
| 162 | |||
| 163 | #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0) | ||
| 164 | #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1) | ||
| 165 | |||
| 166 | #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0 | ||
| 167 | #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2) | ||
| 168 | #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8 | ||
| 169 | #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10) | ||
| 170 | |||
| 171 | #define PRCM_DSI_PLLOUT_SEL_OFF 0 | ||
| 172 | #define PRCM_DSI_PLLOUT_SEL_PHI 1 | ||
| 173 | #define PRCM_DSI_PLLOUT_SEL_PHI_2 2 | ||
| 174 | #define PRCM_DSI_PLLOUT_SEL_PHI_4 3 | ||
| 175 | |||
| 176 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0 | ||
| 177 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7) | ||
| 178 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8 | ||
| 179 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15) | ||
| 180 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16 | ||
| 181 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23) | ||
| 182 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24) | ||
| 183 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25) | ||
| 184 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26) | ||
| 185 | |||
| 186 | #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) | ||
| 187 | |||
| 148 | #define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC) | 188 | #define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC) |
| 149 | #define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) | 189 | #define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) |
| 150 | #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) | 190 | #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) |
| @@ -183,9 +223,15 @@ | |||
| 183 | #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) | 223 | #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) |
| 184 | #define PRCM_CLKOCR_CLK1TYPE BIT(28) | 224 | #define PRCM_CLKOCR_CLK1TYPE BIT(28) |
| 185 | 225 | ||
| 186 | #define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) | 226 | #define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) |
| 187 | #define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) | 227 | #define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) |
| 188 | #define PRCM_CLK_MGT_CLKEN BIT(8) | 228 | #define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) |
| 229 | #define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) | ||
| 230 | #define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) | ||
| 231 | #define PRCM_CLK_MGT_CLKEN BIT(8) | ||
| 232 | #define PRCM_CLK_MGT_CLK38 BIT(9) | ||
| 233 | #define PRCM_CLK_MGT_CLK38DIV BIT(11) | ||
| 234 | #define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) | ||
| 189 | 235 | ||
| 190 | /* GPIOCR register */ | 236 | /* GPIOCR register */ |
| 191 | #define PRCM_GPIOCR_SPI2_SELECT BIT(23) | 237 | #define PRCM_GPIOCR_SPI2_SELECT BIT(23) |