diff options
Diffstat (limited to 'drivers/media/video/cx23885/cx23888-ir.c')
-rw-r--r-- | drivers/media/video/cx23885/cx23888-ir.c | 1269 |
1 files changed, 1269 insertions, 0 deletions
diff --git a/drivers/media/video/cx23885/cx23888-ir.c b/drivers/media/video/cx23885/cx23888-ir.c new file mode 100644 index 00000000000..e37be6fcf67 --- /dev/null +++ b/drivers/media/video/cx23885/cx23888-ir.c | |||
@@ -0,0 +1,1269 @@ | |||
1 | /* | ||
2 | * Driver for the Conexant CX23885/7/8 PCIe bridge | ||
3 | * | ||
4 | * CX23888 Integrated Consumer Infrared Controller | ||
5 | * | ||
6 | * Copyright (C) 2009 Andy Walls <awalls@md.metrocast.net> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License | ||
10 | * as published by the Free Software Foundation; either version 2 | ||
11 | * of the License, or (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
21 | * 02110-1301, USA. | ||
22 | */ | ||
23 | |||
24 | #include <linux/kfifo.h> | ||
25 | #include <linux/slab.h> | ||
26 | |||
27 | #include <media/v4l2-device.h> | ||
28 | #include <media/v4l2-chip-ident.h> | ||
29 | #include <media/rc-core.h> | ||
30 | |||
31 | #include "cx23885.h" | ||
32 | |||
33 | static unsigned int ir_888_debug; | ||
34 | module_param(ir_888_debug, int, 0644); | ||
35 | MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]"); | ||
36 | |||
37 | #define CX23888_IR_REG_BASE 0x170000 | ||
38 | /* | ||
39 | * These CX23888 register offsets have a straightforward one to one mapping | ||
40 | * to the CX23885 register offsets of 0x200 through 0x218 | ||
41 | */ | ||
42 | #define CX23888_IR_CNTRL_REG 0x170000 | ||
43 | #define CNTRL_WIN_3_3 0x00000000 | ||
44 | #define CNTRL_WIN_4_3 0x00000001 | ||
45 | #define CNTRL_WIN_3_4 0x00000002 | ||
46 | #define CNTRL_WIN_4_4 0x00000003 | ||
47 | #define CNTRL_WIN 0x00000003 | ||
48 | #define CNTRL_EDG_NONE 0x00000000 | ||
49 | #define CNTRL_EDG_FALL 0x00000004 | ||
50 | #define CNTRL_EDG_RISE 0x00000008 | ||
51 | #define CNTRL_EDG_BOTH 0x0000000C | ||
52 | #define CNTRL_EDG 0x0000000C | ||
53 | #define CNTRL_DMD 0x00000010 | ||
54 | #define CNTRL_MOD 0x00000020 | ||
55 | #define CNTRL_RFE 0x00000040 | ||
56 | #define CNTRL_TFE 0x00000080 | ||
57 | #define CNTRL_RXE 0x00000100 | ||
58 | #define CNTRL_TXE 0x00000200 | ||
59 | #define CNTRL_RIC 0x00000400 | ||
60 | #define CNTRL_TIC 0x00000800 | ||
61 | #define CNTRL_CPL 0x00001000 | ||
62 | #define CNTRL_LBM 0x00002000 | ||
63 | #define CNTRL_R 0x00004000 | ||
64 | /* CX23888 specific control flag */ | ||
65 | #define CNTRL_IVO 0x00008000 | ||
66 | |||
67 | #define CX23888_IR_TXCLK_REG 0x170004 | ||
68 | #define TXCLK_TCD 0x0000FFFF | ||
69 | |||
70 | #define CX23888_IR_RXCLK_REG 0x170008 | ||
71 | #define RXCLK_RCD 0x0000FFFF | ||
72 | |||
73 | #define CX23888_IR_CDUTY_REG 0x17000C | ||
74 | #define CDUTY_CDC 0x0000000F | ||
75 | |||
76 | #define CX23888_IR_STATS_REG 0x170010 | ||
77 | #define STATS_RTO 0x00000001 | ||
78 | #define STATS_ROR 0x00000002 | ||
79 | #define STATS_RBY 0x00000004 | ||
80 | #define STATS_TBY 0x00000008 | ||
81 | #define STATS_RSR 0x00000010 | ||
82 | #define STATS_TSR 0x00000020 | ||
83 | |||
84 | #define CX23888_IR_IRQEN_REG 0x170014 | ||
85 | #define IRQEN_RTE 0x00000001 | ||
86 | #define IRQEN_ROE 0x00000002 | ||
87 | #define IRQEN_RSE 0x00000010 | ||
88 | #define IRQEN_TSE 0x00000020 | ||
89 | |||
90 | #define CX23888_IR_FILTR_REG 0x170018 | ||
91 | #define FILTR_LPF 0x0000FFFF | ||
92 | |||
93 | /* This register doesn't follow the pattern; it's 0x23C on a CX23885 */ | ||
94 | #define CX23888_IR_FIFO_REG 0x170040 | ||
95 | #define FIFO_RXTX 0x0000FFFF | ||
96 | #define FIFO_RXTX_LVL 0x00010000 | ||
97 | #define FIFO_RXTX_RTO 0x0001FFFF | ||
98 | #define FIFO_RX_NDV 0x00020000 | ||
99 | #define FIFO_RX_DEPTH 8 | ||
100 | #define FIFO_TX_DEPTH 8 | ||
101 | |||
102 | /* CX23888 unique registers */ | ||
103 | #define CX23888_IR_SEEDP_REG 0x17001C | ||
104 | #define CX23888_IR_TIMOL_REG 0x170020 | ||
105 | #define CX23888_IR_WAKE0_REG 0x170024 | ||
106 | #define CX23888_IR_WAKE1_REG 0x170028 | ||
107 | #define CX23888_IR_WAKE2_REG 0x17002C | ||
108 | #define CX23888_IR_MASK0_REG 0x170030 | ||
109 | #define CX23888_IR_MASK1_REG 0x170034 | ||
110 | #define CX23888_IR_MAKS2_REG 0x170038 | ||
111 | #define CX23888_IR_DPIPG_REG 0x17003C | ||
112 | #define CX23888_IR_LEARN_REG 0x170044 | ||
113 | |||
114 | #define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */ | ||
115 | #define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2) | ||
116 | |||
117 | /* | ||
118 | * We use this union internally for convenience, but callers to tx_write | ||
119 | * and rx_read will be expecting records of type struct ir_raw_event. | ||
120 | * Always ensure the size of this union is dictated by struct ir_raw_event. | ||
121 | */ | ||
122 | union cx23888_ir_fifo_rec { | ||
123 | u32 hw_fifo_data; | ||
124 | struct ir_raw_event ir_core_data; | ||
125 | }; | ||
126 | |||
127 | #define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) | ||
128 | #define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec)) | ||
129 | |||
130 | struct cx23888_ir_state { | ||
131 | struct v4l2_subdev sd; | ||
132 | struct cx23885_dev *dev; | ||
133 | u32 id; | ||
134 | u32 rev; | ||
135 | |||
136 | struct v4l2_subdev_ir_parameters rx_params; | ||
137 | struct mutex rx_params_lock; | ||
138 | atomic_t rxclk_divider; | ||
139 | atomic_t rx_invert; | ||
140 | |||
141 | struct kfifo rx_kfifo; | ||
142 | spinlock_t rx_kfifo_lock; | ||
143 | |||
144 | struct v4l2_subdev_ir_parameters tx_params; | ||
145 | struct mutex tx_params_lock; | ||
146 | atomic_t txclk_divider; | ||
147 | }; | ||
148 | |||
149 | static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd) | ||
150 | { | ||
151 | return v4l2_get_subdevdata(sd); | ||
152 | } | ||
153 | |||
154 | /* | ||
155 | * IR register block read and write functions | ||
156 | */ | ||
157 | static | ||
158 | inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value) | ||
159 | { | ||
160 | cx_write(addr, value); | ||
161 | return 0; | ||
162 | } | ||
163 | |||
164 | static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr) | ||
165 | { | ||
166 | return cx_read(addr); | ||
167 | } | ||
168 | |||
169 | static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr, | ||
170 | u32 and_mask, u32 or_value) | ||
171 | { | ||
172 | cx_andor(addr, ~and_mask, or_value); | ||
173 | return 0; | ||
174 | } | ||
175 | |||
176 | /* | ||
177 | * Rx and Tx Clock Divider register computations | ||
178 | * | ||
179 | * Note the largest clock divider value of 0xffff corresponds to: | ||
180 | * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns | ||
181 | * which fits in 21 bits, so we'll use unsigned int for time arguments. | ||
182 | */ | ||
183 | static inline u16 count_to_clock_divider(unsigned int d) | ||
184 | { | ||
185 | if (d > RXCLK_RCD + 1) | ||
186 | d = RXCLK_RCD; | ||
187 | else if (d < 2) | ||
188 | d = 1; | ||
189 | else | ||
190 | d--; | ||
191 | return (u16) d; | ||
192 | } | ||
193 | |||
194 | static inline u16 ns_to_clock_divider(unsigned int ns) | ||
195 | { | ||
196 | return count_to_clock_divider( | ||
197 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); | ||
198 | } | ||
199 | |||
200 | static inline unsigned int clock_divider_to_ns(unsigned int divider) | ||
201 | { | ||
202 | /* Period of the Rx or Tx clock in ns */ | ||
203 | return DIV_ROUND_CLOSEST((divider + 1) * 1000, | ||
204 | CX23888_IR_REFCLK_FREQ / 1000000); | ||
205 | } | ||
206 | |||
207 | static inline u16 carrier_freq_to_clock_divider(unsigned int freq) | ||
208 | { | ||
209 | return count_to_clock_divider( | ||
210 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16)); | ||
211 | } | ||
212 | |||
213 | static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) | ||
214 | { | ||
215 | return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); | ||
216 | } | ||
217 | |||
218 | static inline u16 freq_to_clock_divider(unsigned int freq, | ||
219 | unsigned int rollovers) | ||
220 | { | ||
221 | return count_to_clock_divider( | ||
222 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * rollovers)); | ||
223 | } | ||
224 | |||
225 | static inline unsigned int clock_divider_to_freq(unsigned int divider, | ||
226 | unsigned int rollovers) | ||
227 | { | ||
228 | return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, | ||
229 | (divider + 1) * rollovers); | ||
230 | } | ||
231 | |||
232 | /* | ||
233 | * Low Pass Filter register calculations | ||
234 | * | ||
235 | * Note the largest count value of 0xffff corresponds to: | ||
236 | * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns | ||
237 | * which fits in 21 bits, so we'll use unsigned int for time arguments. | ||
238 | */ | ||
239 | static inline u16 count_to_lpf_count(unsigned int d) | ||
240 | { | ||
241 | if (d > FILTR_LPF) | ||
242 | d = FILTR_LPF; | ||
243 | else if (d < 4) | ||
244 | d = 0; | ||
245 | return (u16) d; | ||
246 | } | ||
247 | |||
248 | static inline u16 ns_to_lpf_count(unsigned int ns) | ||
249 | { | ||
250 | return count_to_lpf_count( | ||
251 | DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000)); | ||
252 | } | ||
253 | |||
254 | static inline unsigned int lpf_count_to_ns(unsigned int count) | ||
255 | { | ||
256 | /* Duration of the Low Pass Filter rejection window in ns */ | ||
257 | return DIV_ROUND_CLOSEST(count * 1000, | ||
258 | CX23888_IR_REFCLK_FREQ / 1000000); | ||
259 | } | ||
260 | |||
261 | static inline unsigned int lpf_count_to_us(unsigned int count) | ||
262 | { | ||
263 | /* Duration of the Low Pass Filter rejection window in us */ | ||
264 | return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000); | ||
265 | } | ||
266 | |||
267 | /* | ||
268 | * FIFO register pulse width count compuations | ||
269 | */ | ||
270 | static u32 clock_divider_to_resolution(u16 divider) | ||
271 | { | ||
272 | /* | ||
273 | * Resolution is the duration of 1 tick of the readable portion of | ||
274 | * of the pulse width counter as read from the FIFO. The two lsb's are | ||
275 | * not readable, hence the << 2. This function returns ns. | ||
276 | */ | ||
277 | return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, | ||
278 | CX23888_IR_REFCLK_FREQ / 1000000); | ||
279 | } | ||
280 | |||
281 | static u64 pulse_width_count_to_ns(u16 count, u16 divider) | ||
282 | { | ||
283 | u64 n; | ||
284 | u32 rem; | ||
285 | |||
286 | /* | ||
287 | * The 2 lsb's of the pulse width timer count are not readable, hence | ||
288 | * the (count << 2) | 0x3 | ||
289 | */ | ||
290 | n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ | ||
291 | rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */ | ||
292 | if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) | ||
293 | n++; | ||
294 | return n; | ||
295 | } | ||
296 | |||
297 | static unsigned int pulse_width_count_to_us(u16 count, u16 divider) | ||
298 | { | ||
299 | u64 n; | ||
300 | u32 rem; | ||
301 | |||
302 | /* | ||
303 | * The 2 lsb's of the pulse width timer count are not readable, hence | ||
304 | * the (count << 2) | 0x3 | ||
305 | */ | ||
306 | n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ | ||
307 | rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */ | ||
308 | if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2) | ||
309 | n++; | ||
310 | return (unsigned int) n; | ||
311 | } | ||
312 | |||
313 | /* | ||
314 | * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts | ||
315 | * | ||
316 | * The total pulse clock count is an 18 bit pulse width timer count as the most | ||
317 | * significant part and (up to) 16 bit clock divider count as a modulus. | ||
318 | * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse | ||
319 | * width timer count's least significant bit. | ||
320 | */ | ||
321 | static u64 ns_to_pulse_clocks(u32 ns) | ||
322 | { | ||
323 | u64 clocks; | ||
324 | u32 rem; | ||
325 | clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ | ||
326 | rem = do_div(clocks, 1000); /* /1000 = cycles */ | ||
327 | if (rem >= 1000 / 2) | ||
328 | clocks++; | ||
329 | return clocks; | ||
330 | } | ||
331 | |||
332 | static u16 pulse_clocks_to_clock_divider(u64 count) | ||
333 | { | ||
334 | u32 rem; | ||
335 | |||
336 | rem = do_div(count, (FIFO_RXTX << 2) | 0x3); | ||
337 | |||
338 | /* net result needs to be rounded down and decremented by 1 */ | ||
339 | if (count > RXCLK_RCD + 1) | ||
340 | count = RXCLK_RCD; | ||
341 | else if (count < 2) | ||
342 | count = 1; | ||
343 | else | ||
344 | count--; | ||
345 | return (u16) count; | ||
346 | } | ||
347 | |||
348 | /* | ||
349 | * IR Control Register helpers | ||
350 | */ | ||
351 | enum tx_fifo_watermark { | ||
352 | TX_FIFO_HALF_EMPTY = 0, | ||
353 | TX_FIFO_EMPTY = CNTRL_TIC, | ||
354 | }; | ||
355 | |||
356 | enum rx_fifo_watermark { | ||
357 | RX_FIFO_HALF_FULL = 0, | ||
358 | RX_FIFO_NOT_EMPTY = CNTRL_RIC, | ||
359 | }; | ||
360 | |||
361 | static inline void control_tx_irq_watermark(struct cx23885_dev *dev, | ||
362 | enum tx_fifo_watermark level) | ||
363 | { | ||
364 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level); | ||
365 | } | ||
366 | |||
367 | static inline void control_rx_irq_watermark(struct cx23885_dev *dev, | ||
368 | enum rx_fifo_watermark level) | ||
369 | { | ||
370 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level); | ||
371 | } | ||
372 | |||
373 | static inline void control_tx_enable(struct cx23885_dev *dev, bool enable) | ||
374 | { | ||
375 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE), | ||
376 | enable ? (CNTRL_TXE | CNTRL_TFE) : 0); | ||
377 | } | ||
378 | |||
379 | static inline void control_rx_enable(struct cx23885_dev *dev, bool enable) | ||
380 | { | ||
381 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE), | ||
382 | enable ? (CNTRL_RXE | CNTRL_RFE) : 0); | ||
383 | } | ||
384 | |||
385 | static inline void control_tx_modulation_enable(struct cx23885_dev *dev, | ||
386 | bool enable) | ||
387 | { | ||
388 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD, | ||
389 | enable ? CNTRL_MOD : 0); | ||
390 | } | ||
391 | |||
392 | static inline void control_rx_demodulation_enable(struct cx23885_dev *dev, | ||
393 | bool enable) | ||
394 | { | ||
395 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD, | ||
396 | enable ? CNTRL_DMD : 0); | ||
397 | } | ||
398 | |||
399 | static inline void control_rx_s_edge_detection(struct cx23885_dev *dev, | ||
400 | u32 edge_types) | ||
401 | { | ||
402 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH, | ||
403 | edge_types & CNTRL_EDG_BOTH); | ||
404 | } | ||
405 | |||
406 | static void control_rx_s_carrier_window(struct cx23885_dev *dev, | ||
407 | unsigned int carrier, | ||
408 | unsigned int *carrier_range_low, | ||
409 | unsigned int *carrier_range_high) | ||
410 | { | ||
411 | u32 v; | ||
412 | unsigned int c16 = carrier * 16; | ||
413 | |||
414 | if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) { | ||
415 | v = CNTRL_WIN_3_4; | ||
416 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4); | ||
417 | } else { | ||
418 | v = CNTRL_WIN_3_3; | ||
419 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3); | ||
420 | } | ||
421 | |||
422 | if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) { | ||
423 | v |= CNTRL_WIN_4_3; | ||
424 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4); | ||
425 | } else { | ||
426 | v |= CNTRL_WIN_3_3; | ||
427 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3); | ||
428 | } | ||
429 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v); | ||
430 | } | ||
431 | |||
432 | static inline void control_tx_polarity_invert(struct cx23885_dev *dev, | ||
433 | bool invert) | ||
434 | { | ||
435 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL, | ||
436 | invert ? CNTRL_CPL : 0); | ||
437 | } | ||
438 | |||
439 | static inline void control_tx_level_invert(struct cx23885_dev *dev, | ||
440 | bool invert) | ||
441 | { | ||
442 | cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO, | ||
443 | invert ? CNTRL_IVO : 0); | ||
444 | } | ||
445 | |||
446 | /* | ||
447 | * IR Rx & Tx Clock Register helpers | ||
448 | */ | ||
449 | static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev, | ||
450 | unsigned int freq, | ||
451 | u16 *divider) | ||
452 | { | ||
453 | *divider = carrier_freq_to_clock_divider(freq); | ||
454 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); | ||
455 | return clock_divider_to_carrier_freq(*divider); | ||
456 | } | ||
457 | |||
458 | static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev, | ||
459 | unsigned int freq, | ||
460 | u16 *divider) | ||
461 | { | ||
462 | *divider = carrier_freq_to_clock_divider(freq); | ||
463 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); | ||
464 | return clock_divider_to_carrier_freq(*divider); | ||
465 | } | ||
466 | |||
467 | static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, | ||
468 | u16 *divider) | ||
469 | { | ||
470 | u64 pulse_clocks; | ||
471 | |||
472 | if (ns > IR_MAX_DURATION) | ||
473 | ns = IR_MAX_DURATION; | ||
474 | pulse_clocks = ns_to_pulse_clocks(ns); | ||
475 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); | ||
476 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider); | ||
477 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); | ||
478 | } | ||
479 | |||
480 | static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, | ||
481 | u16 *divider) | ||
482 | { | ||
483 | u64 pulse_clocks; | ||
484 | |||
485 | if (ns > IR_MAX_DURATION) | ||
486 | ns = IR_MAX_DURATION; | ||
487 | pulse_clocks = ns_to_pulse_clocks(ns); | ||
488 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); | ||
489 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider); | ||
490 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); | ||
491 | } | ||
492 | |||
493 | /* | ||
494 | * IR Tx Carrier Duty Cycle register helpers | ||
495 | */ | ||
496 | static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev, | ||
497 | unsigned int duty_cycle) | ||
498 | { | ||
499 | u32 n; | ||
500 | n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */ | ||
501 | if (n != 0) | ||
502 | n--; | ||
503 | if (n > 15) | ||
504 | n = 15; | ||
505 | cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n); | ||
506 | return DIV_ROUND_CLOSEST((n + 1) * 100, 16); | ||
507 | } | ||
508 | |||
509 | /* | ||
510 | * IR Filter Register helpers | ||
511 | */ | ||
512 | static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns) | ||
513 | { | ||
514 | u32 count = ns_to_lpf_count(min_width_ns); | ||
515 | cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count); | ||
516 | return lpf_count_to_ns(count); | ||
517 | } | ||
518 | |||
519 | /* | ||
520 | * IR IRQ Enable Register helpers | ||
521 | */ | ||
522 | static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask) | ||
523 | { | ||
524 | mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); | ||
525 | cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, | ||
526 | ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); | ||
527 | } | ||
528 | |||
529 | static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask) | ||
530 | { | ||
531 | mask &= IRQEN_TSE; | ||
532 | cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask); | ||
533 | } | ||
534 | |||
535 | /* | ||
536 | * V4L2 Subdevice IR Ops | ||
537 | */ | ||
538 | static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status, | ||
539 | bool *handled) | ||
540 | { | ||
541 | struct cx23888_ir_state *state = to_state(sd); | ||
542 | struct cx23885_dev *dev = state->dev; | ||
543 | unsigned long flags; | ||
544 | |||
545 | u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); | ||
546 | u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); | ||
547 | u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); | ||
548 | |||
549 | union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH]; | ||
550 | unsigned int i, j, k; | ||
551 | u32 events, v; | ||
552 | int tsr, rsr, rto, ror, tse, rse, rte, roe, kror; | ||
553 | |||
554 | tsr = stats & STATS_TSR; /* Tx FIFO Service Request */ | ||
555 | rsr = stats & STATS_RSR; /* Rx FIFO Service Request */ | ||
556 | rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */ | ||
557 | ror = stats & STATS_ROR; /* Rx FIFO Over Run */ | ||
558 | |||
559 | tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ | ||
560 | rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ | ||
561 | rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ | ||
562 | roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ | ||
563 | |||
564 | *handled = false; | ||
565 | v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n", | ||
566 | tsr ? "tsr" : " ", rsr ? "rsr" : " ", | ||
567 | rto ? "rto" : " ", ror ? "ror" : " ", | ||
568 | stats & STATS_TBY ? "tby" : " ", | ||
569 | stats & STATS_RBY ? "rby" : " "); | ||
570 | |||
571 | v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n", | ||
572 | tse ? "tse" : " ", rse ? "rse" : " ", | ||
573 | rte ? "rte" : " ", roe ? "roe" : " "); | ||
574 | |||
575 | /* | ||
576 | * Transmitter interrupt service | ||
577 | */ | ||
578 | if (tse && tsr) { | ||
579 | /* | ||
580 | * TODO: | ||
581 | * Check the watermark threshold setting | ||
582 | * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo | ||
583 | * Push the data to the hardware FIFO. | ||
584 | * If there was nothing more to send in the tx_kfifo, disable | ||
585 | * the TSR IRQ and notify the v4l2_device. | ||
586 | * If there was something in the tx_kfifo, check the tx_kfifo | ||
587 | * level and notify the v4l2_device, if it is low. | ||
588 | */ | ||
589 | /* For now, inhibit TSR interrupt until Tx is implemented */ | ||
590 | irqenable_tx(dev, 0); | ||
591 | events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ; | ||
592 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events); | ||
593 | *handled = true; | ||
594 | } | ||
595 | |||
596 | /* | ||
597 | * Receiver interrupt service | ||
598 | */ | ||
599 | kror = 0; | ||
600 | if ((rse && rsr) || (rte && rto)) { | ||
601 | /* | ||
602 | * Receive data on RSR to clear the STATS_RSR. | ||
603 | * Receive data on RTO, since we may not have yet hit the RSR | ||
604 | * watermark when we receive the RTO. | ||
605 | */ | ||
606 | for (i = 0, v = FIFO_RX_NDV; | ||
607 | (v & FIFO_RX_NDV) && !kror; i = 0) { | ||
608 | for (j = 0; | ||
609 | (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) { | ||
610 | v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG); | ||
611 | rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV; | ||
612 | i++; | ||
613 | } | ||
614 | if (i == 0) | ||
615 | break; | ||
616 | j = i * sizeof(union cx23888_ir_fifo_rec); | ||
617 | k = kfifo_in_locked(&state->rx_kfifo, | ||
618 | (unsigned char *) rx_data, j, | ||
619 | &state->rx_kfifo_lock); | ||
620 | if (k != j) | ||
621 | kror++; /* rx_kfifo over run */ | ||
622 | } | ||
623 | *handled = true; | ||
624 | } | ||
625 | |||
626 | events = 0; | ||
627 | v = 0; | ||
628 | if (kror) { | ||
629 | events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN; | ||
630 | v4l2_err(sd, "IR receiver software FIFO overrun\n"); | ||
631 | } | ||
632 | if (roe && ror) { | ||
633 | /* | ||
634 | * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear | ||
635 | * the Rx FIFO Over Run status (STATS_ROR) | ||
636 | */ | ||
637 | v |= CNTRL_RFE; | ||
638 | events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN; | ||
639 | v4l2_err(sd, "IR receiver hardware FIFO overrun\n"); | ||
640 | } | ||
641 | if (rte && rto) { | ||
642 | /* | ||
643 | * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear | ||
644 | * the Rx Pulse Width Timer Time Out (STATS_RTO) | ||
645 | */ | ||
646 | v |= CNTRL_RXE; | ||
647 | events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; | ||
648 | } | ||
649 | if (v) { | ||
650 | /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ | ||
651 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v); | ||
652 | cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl); | ||
653 | *handled = true; | ||
654 | } | ||
655 | |||
656 | spin_lock_irqsave(&state->rx_kfifo_lock, flags); | ||
657 | if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2) | ||
658 | events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; | ||
659 | spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); | ||
660 | |||
661 | if (events) | ||
662 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events); | ||
663 | return 0; | ||
664 | } | ||
665 | |||
666 | /* Receiver */ | ||
667 | static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count, | ||
668 | ssize_t *num) | ||
669 | { | ||
670 | struct cx23888_ir_state *state = to_state(sd); | ||
671 | bool invert = (bool) atomic_read(&state->rx_invert); | ||
672 | u16 divider = (u16) atomic_read(&state->rxclk_divider); | ||
673 | |||
674 | unsigned int i, n; | ||
675 | union cx23888_ir_fifo_rec *p; | ||
676 | unsigned u, v; | ||
677 | |||
678 | n = count / sizeof(union cx23888_ir_fifo_rec) | ||
679 | * sizeof(union cx23888_ir_fifo_rec); | ||
680 | if (n == 0) { | ||
681 | *num = 0; | ||
682 | return 0; | ||
683 | } | ||
684 | |||
685 | n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock); | ||
686 | |||
687 | n /= sizeof(union cx23888_ir_fifo_rec); | ||
688 | *num = n * sizeof(union cx23888_ir_fifo_rec); | ||
689 | |||
690 | for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) { | ||
691 | |||
692 | if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) { | ||
693 | /* Assume RTO was because of no IR light input */ | ||
694 | u = 0; | ||
695 | v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n"); | ||
696 | } else { | ||
697 | u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0; | ||
698 | if (invert) | ||
699 | u = u ? 0 : 1; | ||
700 | } | ||
701 | |||
702 | v = (unsigned) pulse_width_count_to_ns( | ||
703 | (u16) (p->hw_fifo_data & FIFO_RXTX), divider); | ||
704 | if (v > IR_MAX_DURATION) | ||
705 | v = IR_MAX_DURATION; | ||
706 | |||
707 | init_ir_raw_event(&p->ir_core_data); | ||
708 | p->ir_core_data.pulse = u; | ||
709 | p->ir_core_data.duration = v; | ||
710 | |||
711 | v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s\n", | ||
712 | v, u ? "mark" : "space"); | ||
713 | } | ||
714 | return 0; | ||
715 | } | ||
716 | |||
717 | static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd, | ||
718 | struct v4l2_subdev_ir_parameters *p) | ||
719 | { | ||
720 | struct cx23888_ir_state *state = to_state(sd); | ||
721 | mutex_lock(&state->rx_params_lock); | ||
722 | memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters)); | ||
723 | mutex_unlock(&state->rx_params_lock); | ||
724 | return 0; | ||
725 | } | ||
726 | |||
727 | static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd) | ||
728 | { | ||
729 | struct cx23888_ir_state *state = to_state(sd); | ||
730 | struct cx23885_dev *dev = state->dev; | ||
731 | |||
732 | mutex_lock(&state->rx_params_lock); | ||
733 | |||
734 | /* Disable or slow down all IR Rx circuits and counters */ | ||
735 | irqenable_rx(dev, 0); | ||
736 | control_rx_enable(dev, false); | ||
737 | control_rx_demodulation_enable(dev, false); | ||
738 | control_rx_s_edge_detection(dev, CNTRL_EDG_NONE); | ||
739 | filter_rx_s_min_width(dev, 0); | ||
740 | cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD); | ||
741 | |||
742 | state->rx_params.shutdown = true; | ||
743 | |||
744 | mutex_unlock(&state->rx_params_lock); | ||
745 | return 0; | ||
746 | } | ||
747 | |||
748 | static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd, | ||
749 | struct v4l2_subdev_ir_parameters *p) | ||
750 | { | ||
751 | struct cx23888_ir_state *state = to_state(sd); | ||
752 | struct cx23885_dev *dev = state->dev; | ||
753 | struct v4l2_subdev_ir_parameters *o = &state->rx_params; | ||
754 | u16 rxclk_divider; | ||
755 | |||
756 | if (p->shutdown) | ||
757 | return cx23888_ir_rx_shutdown(sd); | ||
758 | |||
759 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) | ||
760 | return -ENOSYS; | ||
761 | |||
762 | mutex_lock(&state->rx_params_lock); | ||
763 | |||
764 | o->shutdown = p->shutdown; | ||
765 | |||
766 | o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; | ||
767 | |||
768 | o->bytes_per_data_element = p->bytes_per_data_element | ||
769 | = sizeof(union cx23888_ir_fifo_rec); | ||
770 | |||
771 | /* Before we tweak the hardware, we have to disable the receiver */ | ||
772 | irqenable_rx(dev, 0); | ||
773 | control_rx_enable(dev, false); | ||
774 | |||
775 | control_rx_demodulation_enable(dev, p->modulation); | ||
776 | o->modulation = p->modulation; | ||
777 | |||
778 | if (p->modulation) { | ||
779 | p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq, | ||
780 | &rxclk_divider); | ||
781 | |||
782 | o->carrier_freq = p->carrier_freq; | ||
783 | |||
784 | o->duty_cycle = p->duty_cycle = 50; | ||
785 | |||
786 | control_rx_s_carrier_window(dev, p->carrier_freq, | ||
787 | &p->carrier_range_lower, | ||
788 | &p->carrier_range_upper); | ||
789 | o->carrier_range_lower = p->carrier_range_lower; | ||
790 | o->carrier_range_upper = p->carrier_range_upper; | ||
791 | |||
792 | p->max_pulse_width = | ||
793 | (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); | ||
794 | } else { | ||
795 | p->max_pulse_width = | ||
796 | rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width, | ||
797 | &rxclk_divider); | ||
798 | } | ||
799 | o->max_pulse_width = p->max_pulse_width; | ||
800 | atomic_set(&state->rxclk_divider, rxclk_divider); | ||
801 | |||
802 | p->noise_filter_min_width = | ||
803 | filter_rx_s_min_width(dev, p->noise_filter_min_width); | ||
804 | o->noise_filter_min_width = p->noise_filter_min_width; | ||
805 | |||
806 | p->resolution = clock_divider_to_resolution(rxclk_divider); | ||
807 | o->resolution = p->resolution; | ||
808 | |||
809 | /* FIXME - make this dependent on resolution for better performance */ | ||
810 | control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL); | ||
811 | |||
812 | control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH); | ||
813 | |||
814 | o->invert_level = p->invert_level; | ||
815 | atomic_set(&state->rx_invert, p->invert_level); | ||
816 | |||
817 | o->interrupt_enable = p->interrupt_enable; | ||
818 | o->enable = p->enable; | ||
819 | if (p->enable) { | ||
820 | unsigned long flags; | ||
821 | |||
822 | spin_lock_irqsave(&state->rx_kfifo_lock, flags); | ||
823 | kfifo_reset(&state->rx_kfifo); | ||
824 | /* reset tx_fifo too if there is one... */ | ||
825 | spin_unlock_irqrestore(&state->rx_kfifo_lock, flags); | ||
826 | if (p->interrupt_enable) | ||
827 | irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE); | ||
828 | control_rx_enable(dev, p->enable); | ||
829 | } | ||
830 | |||
831 | mutex_unlock(&state->rx_params_lock); | ||
832 | return 0; | ||
833 | } | ||
834 | |||
835 | /* Transmitter */ | ||
836 | static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count, | ||
837 | ssize_t *num) | ||
838 | { | ||
839 | struct cx23888_ir_state *state = to_state(sd); | ||
840 | struct cx23885_dev *dev = state->dev; | ||
841 | /* For now enable the Tx FIFO Service interrupt & pretend we did work */ | ||
842 | irqenable_tx(dev, IRQEN_TSE); | ||
843 | *num = count; | ||
844 | return 0; | ||
845 | } | ||
846 | |||
847 | static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd, | ||
848 | struct v4l2_subdev_ir_parameters *p) | ||
849 | { | ||
850 | struct cx23888_ir_state *state = to_state(sd); | ||
851 | mutex_lock(&state->tx_params_lock); | ||
852 | memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters)); | ||
853 | mutex_unlock(&state->tx_params_lock); | ||
854 | return 0; | ||
855 | } | ||
856 | |||
857 | static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd) | ||
858 | { | ||
859 | struct cx23888_ir_state *state = to_state(sd); | ||
860 | struct cx23885_dev *dev = state->dev; | ||
861 | |||
862 | mutex_lock(&state->tx_params_lock); | ||
863 | |||
864 | /* Disable or slow down all IR Tx circuits and counters */ | ||
865 | irqenable_tx(dev, 0); | ||
866 | control_tx_enable(dev, false); | ||
867 | control_tx_modulation_enable(dev, false); | ||
868 | cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD); | ||
869 | |||
870 | state->tx_params.shutdown = true; | ||
871 | |||
872 | mutex_unlock(&state->tx_params_lock); | ||
873 | return 0; | ||
874 | } | ||
875 | |||
876 | static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd, | ||
877 | struct v4l2_subdev_ir_parameters *p) | ||
878 | { | ||
879 | struct cx23888_ir_state *state = to_state(sd); | ||
880 | struct cx23885_dev *dev = state->dev; | ||
881 | struct v4l2_subdev_ir_parameters *o = &state->tx_params; | ||
882 | u16 txclk_divider; | ||
883 | |||
884 | if (p->shutdown) | ||
885 | return cx23888_ir_tx_shutdown(sd); | ||
886 | |||
887 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) | ||
888 | return -ENOSYS; | ||
889 | |||
890 | mutex_lock(&state->tx_params_lock); | ||
891 | |||
892 | o->shutdown = p->shutdown; | ||
893 | |||
894 | o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; | ||
895 | |||
896 | o->bytes_per_data_element = p->bytes_per_data_element | ||
897 | = sizeof(union cx23888_ir_fifo_rec); | ||
898 | |||
899 | /* Before we tweak the hardware, we have to disable the transmitter */ | ||
900 | irqenable_tx(dev, 0); | ||
901 | control_tx_enable(dev, false); | ||
902 | |||
903 | control_tx_modulation_enable(dev, p->modulation); | ||
904 | o->modulation = p->modulation; | ||
905 | |||
906 | if (p->modulation) { | ||
907 | p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq, | ||
908 | &txclk_divider); | ||
909 | o->carrier_freq = p->carrier_freq; | ||
910 | |||
911 | p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle); | ||
912 | o->duty_cycle = p->duty_cycle; | ||
913 | |||
914 | p->max_pulse_width = | ||
915 | (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); | ||
916 | } else { | ||
917 | p->max_pulse_width = | ||
918 | txclk_tx_s_max_pulse_width(dev, p->max_pulse_width, | ||
919 | &txclk_divider); | ||
920 | } | ||
921 | o->max_pulse_width = p->max_pulse_width; | ||
922 | atomic_set(&state->txclk_divider, txclk_divider); | ||
923 | |||
924 | p->resolution = clock_divider_to_resolution(txclk_divider); | ||
925 | o->resolution = p->resolution; | ||
926 | |||
927 | /* FIXME - make this dependent on resolution for better performance */ | ||
928 | control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY); | ||
929 | |||
930 | control_tx_polarity_invert(dev, p->invert_carrier_sense); | ||
931 | o->invert_carrier_sense = p->invert_carrier_sense; | ||
932 | |||
933 | control_tx_level_invert(dev, p->invert_level); | ||
934 | o->invert_level = p->invert_level; | ||
935 | |||
936 | o->interrupt_enable = p->interrupt_enable; | ||
937 | o->enable = p->enable; | ||
938 | if (p->enable) { | ||
939 | if (p->interrupt_enable) | ||
940 | irqenable_tx(dev, IRQEN_TSE); | ||
941 | control_tx_enable(dev, p->enable); | ||
942 | } | ||
943 | |||
944 | mutex_unlock(&state->tx_params_lock); | ||
945 | return 0; | ||
946 | } | ||
947 | |||
948 | |||
949 | /* | ||
950 | * V4L2 Subdevice Core Ops | ||
951 | */ | ||
952 | static int cx23888_ir_log_status(struct v4l2_subdev *sd) | ||
953 | { | ||
954 | struct cx23888_ir_state *state = to_state(sd); | ||
955 | struct cx23885_dev *dev = state->dev; | ||
956 | char *s; | ||
957 | int i, j; | ||
958 | |||
959 | u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG); | ||
960 | u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD; | ||
961 | u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD; | ||
962 | u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC; | ||
963 | u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG); | ||
964 | u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG); | ||
965 | u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF; | ||
966 | |||
967 | v4l2_info(sd, "IR Receiver:\n"); | ||
968 | v4l2_info(sd, "\tEnabled: %s\n", | ||
969 | cntrl & CNTRL_RXE ? "yes" : "no"); | ||
970 | v4l2_info(sd, "\tDemodulation from a carrier: %s\n", | ||
971 | cntrl & CNTRL_DMD ? "enabled" : "disabled"); | ||
972 | v4l2_info(sd, "\tFIFO: %s\n", | ||
973 | cntrl & CNTRL_RFE ? "enabled" : "disabled"); | ||
974 | switch (cntrl & CNTRL_EDG) { | ||
975 | case CNTRL_EDG_NONE: | ||
976 | s = "disabled"; | ||
977 | break; | ||
978 | case CNTRL_EDG_FALL: | ||
979 | s = "falling edge"; | ||
980 | break; | ||
981 | case CNTRL_EDG_RISE: | ||
982 | s = "rising edge"; | ||
983 | break; | ||
984 | case CNTRL_EDG_BOTH: | ||
985 | s = "rising & falling edges"; | ||
986 | break; | ||
987 | default: | ||
988 | s = "??? edge"; | ||
989 | break; | ||
990 | } | ||
991 | v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s); | ||
992 | v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n", | ||
993 | cntrl & CNTRL_R ? "not loaded" : "overflow marker"); | ||
994 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", | ||
995 | cntrl & CNTRL_RIC ? "not empty" : "half full or greater"); | ||
996 | v4l2_info(sd, "\tLoopback mode: %s\n", | ||
997 | cntrl & CNTRL_LBM ? "loopback active" : "normal receive"); | ||
998 | if (cntrl & CNTRL_DMD) { | ||
999 | v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", | ||
1000 | clock_divider_to_carrier_freq(rxclk)); | ||
1001 | switch (cntrl & CNTRL_WIN) { | ||
1002 | case CNTRL_WIN_3_3: | ||
1003 | i = 3; | ||
1004 | j = 3; | ||
1005 | break; | ||
1006 | case CNTRL_WIN_4_3: | ||
1007 | i = 4; | ||
1008 | j = 3; | ||
1009 | break; | ||
1010 | case CNTRL_WIN_3_4: | ||
1011 | i = 3; | ||
1012 | j = 4; | ||
1013 | break; | ||
1014 | case CNTRL_WIN_4_4: | ||
1015 | i = 4; | ||
1016 | j = 4; | ||
1017 | break; | ||
1018 | default: | ||
1019 | i = 0; | ||
1020 | j = 0; | ||
1021 | break; | ||
1022 | } | ||
1023 | v4l2_info(sd, "\tNext carrier edge window: 16 clocks " | ||
1024 | "-%1d/+%1d, %u to %u Hz\n", i, j, | ||
1025 | clock_divider_to_freq(rxclk, 16 + j), | ||
1026 | clock_divider_to_freq(rxclk, 16 - i)); | ||
1027 | } | ||
1028 | v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", | ||
1029 | pulse_width_count_to_us(FIFO_RXTX, rxclk), | ||
1030 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); | ||
1031 | v4l2_info(sd, "\tLow pass filter: %s\n", | ||
1032 | filtr ? "enabled" : "disabled"); | ||
1033 | if (filtr) | ||
1034 | v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, " | ||
1035 | "%u ns\n", | ||
1036 | lpf_count_to_us(filtr), | ||
1037 | lpf_count_to_ns(filtr)); | ||
1038 | v4l2_info(sd, "\tPulse width timer timed-out: %s\n", | ||
1039 | stats & STATS_RTO ? "yes" : "no"); | ||
1040 | v4l2_info(sd, "\tPulse width timer time-out intr: %s\n", | ||
1041 | irqen & IRQEN_RTE ? "enabled" : "disabled"); | ||
1042 | v4l2_info(sd, "\tFIFO overrun: %s\n", | ||
1043 | stats & STATS_ROR ? "yes" : "no"); | ||
1044 | v4l2_info(sd, "\tFIFO overrun interrupt: %s\n", | ||
1045 | irqen & IRQEN_ROE ? "enabled" : "disabled"); | ||
1046 | v4l2_info(sd, "\tBusy: %s\n", | ||
1047 | stats & STATS_RBY ? "yes" : "no"); | ||
1048 | v4l2_info(sd, "\tFIFO service requested: %s\n", | ||
1049 | stats & STATS_RSR ? "yes" : "no"); | ||
1050 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", | ||
1051 | irqen & IRQEN_RSE ? "enabled" : "disabled"); | ||
1052 | |||
1053 | v4l2_info(sd, "IR Transmitter:\n"); | ||
1054 | v4l2_info(sd, "\tEnabled: %s\n", | ||
1055 | cntrl & CNTRL_TXE ? "yes" : "no"); | ||
1056 | v4l2_info(sd, "\tModulation onto a carrier: %s\n", | ||
1057 | cntrl & CNTRL_MOD ? "enabled" : "disabled"); | ||
1058 | v4l2_info(sd, "\tFIFO: %s\n", | ||
1059 | cntrl & CNTRL_TFE ? "enabled" : "disabled"); | ||
1060 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", | ||
1061 | cntrl & CNTRL_TIC ? "not empty" : "half full or less"); | ||
1062 | v4l2_info(sd, "\tOutput pin level inversion %s\n", | ||
1063 | cntrl & CNTRL_IVO ? "yes" : "no"); | ||
1064 | v4l2_info(sd, "\tCarrier polarity: %s\n", | ||
1065 | cntrl & CNTRL_CPL ? "space:burst mark:noburst" | ||
1066 | : "space:noburst mark:burst"); | ||
1067 | if (cntrl & CNTRL_MOD) { | ||
1068 | v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n", | ||
1069 | clock_divider_to_carrier_freq(txclk)); | ||
1070 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", | ||
1071 | cduty + 1); | ||
1072 | } | ||
1073 | v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", | ||
1074 | pulse_width_count_to_us(FIFO_RXTX, txclk), | ||
1075 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); | ||
1076 | v4l2_info(sd, "\tBusy: %s\n", | ||
1077 | stats & STATS_TBY ? "yes" : "no"); | ||
1078 | v4l2_info(sd, "\tFIFO service requested: %s\n", | ||
1079 | stats & STATS_TSR ? "yes" : "no"); | ||
1080 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", | ||
1081 | irqen & IRQEN_TSE ? "enabled" : "disabled"); | ||
1082 | |||
1083 | return 0; | ||
1084 | } | ||
1085 | |||
1086 | static inline int cx23888_ir_dbg_match(const struct v4l2_dbg_match *match) | ||
1087 | { | ||
1088 | return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 2; | ||
1089 | } | ||
1090 | |||
1091 | static int cx23888_ir_g_chip_ident(struct v4l2_subdev *sd, | ||
1092 | struct v4l2_dbg_chip_ident *chip) | ||
1093 | { | ||
1094 | struct cx23888_ir_state *state = to_state(sd); | ||
1095 | |||
1096 | if (cx23888_ir_dbg_match(&chip->match)) { | ||
1097 | chip->ident = state->id; | ||
1098 | chip->revision = state->rev; | ||
1099 | } | ||
1100 | return 0; | ||
1101 | } | ||
1102 | |||
1103 | #ifdef CONFIG_VIDEO_ADV_DEBUG | ||
1104 | static int cx23888_ir_g_register(struct v4l2_subdev *sd, | ||
1105 | struct v4l2_dbg_register *reg) | ||
1106 | { | ||
1107 | struct cx23888_ir_state *state = to_state(sd); | ||
1108 | u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; | ||
1109 | |||
1110 | if (!cx23888_ir_dbg_match(®->match)) | ||
1111 | return -EINVAL; | ||
1112 | if ((addr & 0x3) != 0) | ||
1113 | return -EINVAL; | ||
1114 | if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) | ||
1115 | return -EINVAL; | ||
1116 | if (!capable(CAP_SYS_ADMIN)) | ||
1117 | return -EPERM; | ||
1118 | reg->size = 4; | ||
1119 | reg->val = cx23888_ir_read4(state->dev, addr); | ||
1120 | return 0; | ||
1121 | } | ||
1122 | |||
1123 | static int cx23888_ir_s_register(struct v4l2_subdev *sd, | ||
1124 | struct v4l2_dbg_register *reg) | ||
1125 | { | ||
1126 | struct cx23888_ir_state *state = to_state(sd); | ||
1127 | u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; | ||
1128 | |||
1129 | if (!cx23888_ir_dbg_match(®->match)) | ||
1130 | return -EINVAL; | ||
1131 | if ((addr & 0x3) != 0) | ||
1132 | return -EINVAL; | ||
1133 | if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG) | ||
1134 | return -EINVAL; | ||
1135 | if (!capable(CAP_SYS_ADMIN)) | ||
1136 | return -EPERM; | ||
1137 | cx23888_ir_write4(state->dev, addr, reg->val); | ||
1138 | return 0; | ||
1139 | } | ||
1140 | #endif | ||
1141 | |||
1142 | static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = { | ||
1143 | .g_chip_ident = cx23888_ir_g_chip_ident, | ||
1144 | .log_status = cx23888_ir_log_status, | ||
1145 | #ifdef CONFIG_VIDEO_ADV_DEBUG | ||
1146 | .g_register = cx23888_ir_g_register, | ||
1147 | .s_register = cx23888_ir_s_register, | ||
1148 | #endif | ||
1149 | .interrupt_service_routine = cx23888_ir_irq_handler, | ||
1150 | }; | ||
1151 | |||
1152 | static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = { | ||
1153 | .rx_read = cx23888_ir_rx_read, | ||
1154 | .rx_g_parameters = cx23888_ir_rx_g_parameters, | ||
1155 | .rx_s_parameters = cx23888_ir_rx_s_parameters, | ||
1156 | |||
1157 | .tx_write = cx23888_ir_tx_write, | ||
1158 | .tx_g_parameters = cx23888_ir_tx_g_parameters, | ||
1159 | .tx_s_parameters = cx23888_ir_tx_s_parameters, | ||
1160 | }; | ||
1161 | |||
1162 | static const struct v4l2_subdev_ops cx23888_ir_controller_ops = { | ||
1163 | .core = &cx23888_ir_core_ops, | ||
1164 | .ir = &cx23888_ir_ir_ops, | ||
1165 | }; | ||
1166 | |||
1167 | static const struct v4l2_subdev_ir_parameters default_rx_params = { | ||
1168 | .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), | ||
1169 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, | ||
1170 | |||
1171 | .enable = false, | ||
1172 | .interrupt_enable = false, | ||
1173 | .shutdown = true, | ||
1174 | |||
1175 | .modulation = true, | ||
1176 | .carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */ | ||
1177 | |||
1178 | /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */ | ||
1179 | /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */ | ||
1180 | .noise_filter_min_width = 333333, /* ns */ | ||
1181 | .carrier_range_lower = 35000, | ||
1182 | .carrier_range_upper = 37000, | ||
1183 | .invert_level = false, | ||
1184 | }; | ||
1185 | |||
1186 | static const struct v4l2_subdev_ir_parameters default_tx_params = { | ||
1187 | .bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec), | ||
1188 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, | ||
1189 | |||
1190 | .enable = false, | ||
1191 | .interrupt_enable = false, | ||
1192 | .shutdown = true, | ||
1193 | |||
1194 | .modulation = true, | ||
1195 | .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */ | ||
1196 | .duty_cycle = 25, /* 25 % - RC-5 carrier */ | ||
1197 | .invert_level = false, | ||
1198 | .invert_carrier_sense = false, | ||
1199 | }; | ||
1200 | |||
1201 | int cx23888_ir_probe(struct cx23885_dev *dev) | ||
1202 | { | ||
1203 | struct cx23888_ir_state *state; | ||
1204 | struct v4l2_subdev *sd; | ||
1205 | struct v4l2_subdev_ir_parameters default_params; | ||
1206 | int ret; | ||
1207 | |||
1208 | state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL); | ||
1209 | if (state == NULL) | ||
1210 | return -ENOMEM; | ||
1211 | |||
1212 | spin_lock_init(&state->rx_kfifo_lock); | ||
1213 | if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE, GFP_KERNEL)) | ||
1214 | return -ENOMEM; | ||
1215 | |||
1216 | state->dev = dev; | ||
1217 | state->id = V4L2_IDENT_CX23888_IR; | ||
1218 | state->rev = 0; | ||
1219 | sd = &state->sd; | ||
1220 | |||
1221 | v4l2_subdev_init(sd, &cx23888_ir_controller_ops); | ||
1222 | v4l2_set_subdevdata(sd, state); | ||
1223 | /* FIXME - fix the formatting of dev->v4l2_dev.name and use it */ | ||
1224 | snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name); | ||
1225 | sd->grp_id = CX23885_HW_888_IR; | ||
1226 | |||
1227 | ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd); | ||
1228 | if (ret == 0) { | ||
1229 | /* | ||
1230 | * Ensure no interrupts arrive from '888 specific conditions, | ||
1231 | * since we ignore them in this driver to have commonality with | ||
1232 | * similar IR controller cores. | ||
1233 | */ | ||
1234 | cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0); | ||
1235 | |||
1236 | mutex_init(&state->rx_params_lock); | ||
1237 | memcpy(&default_params, &default_rx_params, | ||
1238 | sizeof(struct v4l2_subdev_ir_parameters)); | ||
1239 | v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params); | ||
1240 | |||
1241 | mutex_init(&state->tx_params_lock); | ||
1242 | memcpy(&default_params, &default_tx_params, | ||
1243 | sizeof(struct v4l2_subdev_ir_parameters)); | ||
1244 | v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params); | ||
1245 | } else { | ||
1246 | kfifo_free(&state->rx_kfifo); | ||
1247 | } | ||
1248 | return ret; | ||
1249 | } | ||
1250 | |||
1251 | int cx23888_ir_remove(struct cx23885_dev *dev) | ||
1252 | { | ||
1253 | struct v4l2_subdev *sd; | ||
1254 | struct cx23888_ir_state *state; | ||
1255 | |||
1256 | sd = cx23885_find_hw(dev, CX23885_HW_888_IR); | ||
1257 | if (sd == NULL) | ||
1258 | return -ENODEV; | ||
1259 | |||
1260 | cx23888_ir_rx_shutdown(sd); | ||
1261 | cx23888_ir_tx_shutdown(sd); | ||
1262 | |||
1263 | state = to_state(sd); | ||
1264 | v4l2_device_unregister_subdev(sd); | ||
1265 | kfifo_free(&state->rx_kfifo); | ||
1266 | kfree(state); | ||
1267 | /* Nothing more to free() as state held the actual v4l2_subdev object */ | ||
1268 | return 0; | ||
1269 | } | ||