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-rw-r--r--drivers/media/dvb/ngene/Kconfig13
-rw-r--r--drivers/media/dvb/ngene/Makefile14
-rw-r--r--drivers/media/dvb/ngene/ngene-cards.c558
-rw-r--r--drivers/media/dvb/ngene/ngene-core.c1715
-rw-r--r--drivers/media/dvb/ngene/ngene-dvb.c261
-rw-r--r--drivers/media/dvb/ngene/ngene-i2c.c176
-rw-r--r--drivers/media/dvb/ngene/ngene.h921
7 files changed, 3658 insertions, 0 deletions
diff --git a/drivers/media/dvb/ngene/Kconfig b/drivers/media/dvb/ngene/Kconfig
new file mode 100644
index 00000000000..64c84702ba5
--- /dev/null
+++ b/drivers/media/dvb/ngene/Kconfig
@@ -0,0 +1,13 @@
1config DVB_NGENE
2 tristate "Micronas nGene support"
3 depends on DVB_CORE && PCI && I2C
4 select DVB_LNBP21 if !DVB_FE_CUSTOMISE
5 select DVB_STV6110x if !DVB_FE_CUSTOMISE
6 select DVB_STV090x if !DVB_FE_CUSTOMISE
7 select DVB_LGDT330X if !DVB_FE_CUSTOMISE
8 select DVB_DRXK if !DVB_FE_CUSTOMISE
9 select DVB_TDA18271C2DD if !DVB_FE_CUSTOMISE
10 select MEDIA_TUNER_MT2131 if !MEDIA_TUNER_CUSTOMISE
11 ---help---
12 Support for Micronas PCI express cards with nGene bridge.
13
diff --git a/drivers/media/dvb/ngene/Makefile b/drivers/media/dvb/ngene/Makefile
new file mode 100644
index 00000000000..2bc96874d04
--- /dev/null
+++ b/drivers/media/dvb/ngene/Makefile
@@ -0,0 +1,14 @@
1#
2# Makefile for the nGene device driver
3#
4
5ngene-objs := ngene-core.o ngene-i2c.o ngene-cards.o ngene-dvb.o
6
7obj-$(CONFIG_DVB_NGENE) += ngene.o
8
9EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/
10EXTRA_CFLAGS += -Idrivers/media/dvb/frontends/
11EXTRA_CFLAGS += -Idrivers/media/common/tuners/
12
13# For the staging CI driver cxd2099
14EXTRA_CFLAGS += -Idrivers/staging/cxd2099/
diff --git a/drivers/media/dvb/ngene/ngene-cards.c b/drivers/media/dvb/ngene/ngene-cards.c
new file mode 100644
index 00000000000..05641922836
--- /dev/null
+++ b/drivers/media/dvb/ngene/ngene-cards.c
@@ -0,0 +1,558 @@
1/*
2 * ngene-cards.c: nGene PCIe bridge driver - card specific info
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/pci.h>
33#include <linux/pci_ids.h>
34
35#include "ngene.h"
36
37/* demods/tuners */
38#include "stv6110x.h"
39#include "stv090x.h"
40#include "lnbh24.h"
41#include "lgdt330x.h"
42#include "mt2131.h"
43#include "tda18271c2dd.h"
44#include "drxk.h"
45
46
47/****************************************************************************/
48/* Demod/tuner attachment ***************************************************/
49/****************************************************************************/
50
51static int tuner_attach_stv6110(struct ngene_channel *chan)
52{
53 struct i2c_adapter *i2c;
54 struct stv090x_config *feconf = (struct stv090x_config *)
55 chan->dev->card_info->fe_config[chan->number];
56 struct stv6110x_config *tunerconf = (struct stv6110x_config *)
57 chan->dev->card_info->tuner_config[chan->number];
58 struct stv6110x_devctl *ctl;
59
60 /* tuner 1+2: i2c adapter #0, tuner 3+4: i2c adapter #1 */
61 if (chan->number < 2)
62 i2c = &chan->dev->channel[0].i2c_adapter;
63 else
64 i2c = &chan->dev->channel[1].i2c_adapter;
65
66 ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf, i2c);
67 if (ctl == NULL) {
68 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
69 return -ENODEV;
70 }
71
72 feconf->tuner_init = ctl->tuner_init;
73 feconf->tuner_sleep = ctl->tuner_sleep;
74 feconf->tuner_set_mode = ctl->tuner_set_mode;
75 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
76 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
77 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
78 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
79 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
80 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
81 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
82 feconf->tuner_get_status = ctl->tuner_get_status;
83
84 return 0;
85}
86
87
88static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
89{
90 struct ngene_channel *chan = fe->sec_priv;
91 int status;
92
93 if (enable) {
94 down(&chan->dev->pll_mutex);
95 status = chan->gate_ctrl(fe, 1);
96 } else {
97 status = chan->gate_ctrl(fe, 0);
98 up(&chan->dev->pll_mutex);
99 }
100 return status;
101}
102
103static int tuner_attach_tda18271(struct ngene_channel *chan)
104{
105 struct i2c_adapter *i2c;
106 struct dvb_frontend *fe;
107
108 i2c = &chan->dev->channel[0].i2c_adapter;
109 if (chan->fe->ops.i2c_gate_ctrl)
110 chan->fe->ops.i2c_gate_ctrl(chan->fe, 1);
111 fe = dvb_attach(tda18271c2dd_attach, chan->fe, i2c, 0x60);
112 if (chan->fe->ops.i2c_gate_ctrl)
113 chan->fe->ops.i2c_gate_ctrl(chan->fe, 0);
114 if (!fe) {
115 printk(KERN_ERR "No TDA18271 found!\n");
116 return -ENODEV;
117 }
118
119 return 0;
120}
121
122static int tuner_attach_probe(struct ngene_channel *chan)
123{
124 if (chan->demod_type == 0)
125 return tuner_attach_stv6110(chan);
126 if (chan->demod_type == 1)
127 return tuner_attach_tda18271(chan);
128 return -EINVAL;
129}
130
131static int demod_attach_stv0900(struct ngene_channel *chan)
132{
133 struct i2c_adapter *i2c;
134 struct stv090x_config *feconf = (struct stv090x_config *)
135 chan->dev->card_info->fe_config[chan->number];
136
137 /* tuner 1+2: i2c adapter #0, tuner 3+4: i2c adapter #1 */
138 /* Note: Both adapters share the same i2c bus, but the demod */
139 /* driver requires that each demod has its own i2c adapter */
140 if (chan->number < 2)
141 i2c = &chan->dev->channel[0].i2c_adapter;
142 else
143 i2c = &chan->dev->channel[1].i2c_adapter;
144
145 chan->fe = dvb_attach(stv090x_attach, feconf, i2c,
146 (chan->number & 1) == 0 ? STV090x_DEMODULATOR_0
147 : STV090x_DEMODULATOR_1);
148 if (chan->fe == NULL) {
149 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
150 return -ENODEV;
151 }
152
153 /* store channel info */
154 if (feconf->tuner_i2c_lock)
155 chan->fe->analog_demod_priv = chan;
156
157 if (!dvb_attach(lnbh24_attach, chan->fe, i2c, 0,
158 0, chan->dev->card_info->lnb[chan->number])) {
159 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
160 dvb_frontend_detach(chan->fe);
161 chan->fe = NULL;
162 return -ENODEV;
163 }
164
165 return 0;
166}
167
168static void cineS2_tuner_i2c_lock(struct dvb_frontend *fe, int lock)
169{
170 struct ngene_channel *chan = fe->analog_demod_priv;
171
172 if (lock)
173 down(&chan->dev->pll_mutex);
174 else
175 up(&chan->dev->pll_mutex);
176}
177
178static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
179{
180 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
181 .buf = val, .len = 1 } };
182 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
183}
184
185static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
186 u16 reg, u8 *val)
187{
188 u8 msg[2] = {reg>>8, reg&0xff};
189 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
190 .buf = msg, .len = 2},
191 {.addr = adr, .flags = I2C_M_RD,
192 .buf = val, .len = 1} };
193 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
194}
195
196static int port_has_stv0900(struct i2c_adapter *i2c, int port)
197{
198 u8 val;
199 if (i2c_read_reg16(i2c, 0x68+port/2, 0xf100, &val) < 0)
200 return 0;
201 return 1;
202}
203
204static int port_has_drxk(struct i2c_adapter *i2c, int port)
205{
206 u8 val;
207
208 if (i2c_read(i2c, 0x29+port, &val) < 0)
209 return 0;
210 return 1;
211}
212
213static int demod_attach_drxk(struct ngene_channel *chan,
214 struct i2c_adapter *i2c)
215{
216 struct drxk_config config;
217
218 memset(&config, 0, sizeof(config));
219 config.adr = 0x29 + (chan->number ^ 2);
220
221 chan->fe = dvb_attach(drxk_attach, &config, i2c, &chan->fe2);
222 if (!chan->fe) {
223 printk(KERN_ERR "No DRXK found!\n");
224 return -ENODEV;
225 }
226 chan->fe->sec_priv = chan;
227 chan->gate_ctrl = chan->fe->ops.i2c_gate_ctrl;
228 chan->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
229 return 0;
230}
231
232static int cineS2_probe(struct ngene_channel *chan)
233{
234 struct i2c_adapter *i2c;
235 struct stv090x_config *fe_conf;
236 u8 buf[3];
237 struct i2c_msg i2c_msg = { .flags = 0, .buf = buf };
238 int rc;
239
240 /* tuner 1+2: i2c adapter #0, tuner 3+4: i2c adapter #1 */
241 if (chan->number < 2)
242 i2c = &chan->dev->channel[0].i2c_adapter;
243 else
244 i2c = &chan->dev->channel[1].i2c_adapter;
245
246 if (port_has_stv0900(i2c, chan->number)) {
247 chan->demod_type = 0;
248 fe_conf = chan->dev->card_info->fe_config[chan->number];
249 /* demod found, attach it */
250 rc = demod_attach_stv0900(chan);
251 if (rc < 0 || chan->number < 2)
252 return rc;
253
254 /* demod #2: reprogram outputs DPN1 & DPN2 */
255 i2c_msg.addr = fe_conf->address;
256 i2c_msg.len = 3;
257 buf[0] = 0xf1;
258 switch (chan->number) {
259 case 2:
260 buf[1] = 0x5c;
261 buf[2] = 0xc2;
262 break;
263 case 3:
264 buf[1] = 0x61;
265 buf[2] = 0xcc;
266 break;
267 default:
268 return -ENODEV;
269 }
270 rc = i2c_transfer(i2c, &i2c_msg, 1);
271 if (rc != 1) {
272 printk(KERN_ERR DEVICE_NAME ": could not setup DPNx\n");
273 return -EIO;
274 }
275 } else if (port_has_drxk(i2c, chan->number^2)) {
276 chan->demod_type = 1;
277 demod_attach_drxk(chan, i2c);
278 } else {
279 printk(KERN_ERR "No demod found on chan %d\n", chan->number);
280 return -ENODEV;
281 }
282 return 0;
283}
284
285
286static struct lgdt330x_config aver_m780 = {
287 .demod_address = 0xb2 >> 1,
288 .demod_chip = LGDT3303,
289 .serial_mpeg = 0x00, /* PARALLEL */
290 .clock_polarity_flip = 1,
291};
292
293static struct mt2131_config m780_tunerconfig = {
294 0xc0 >> 1
295};
296
297/* A single func to attach the demo and tuner, rather than
298 * use two sep funcs like the current design mandates.
299 */
300static int demod_attach_lg330x(struct ngene_channel *chan)
301{
302 chan->fe = dvb_attach(lgdt330x_attach, &aver_m780, &chan->i2c_adapter);
303 if (chan->fe == NULL) {
304 printk(KERN_ERR DEVICE_NAME ": No LGDT330x found!\n");
305 return -ENODEV;
306 }
307
308 dvb_attach(mt2131_attach, chan->fe, &chan->i2c_adapter,
309 &m780_tunerconfig, 0);
310
311 return (chan->fe) ? 0 : -ENODEV;
312}
313
314/****************************************************************************/
315/* Switch control (I2C gates, etc.) *****************************************/
316/****************************************************************************/
317
318
319static struct stv090x_config fe_cineS2 = {
320 .device = STV0900,
321 .demod_mode = STV090x_DUAL,
322 .clk_mode = STV090x_CLK_EXT,
323
324 .xtal = 27000000,
325 .address = 0x68,
326
327 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
328 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
329
330 .repeater_level = STV090x_RPTLEVEL_16,
331
332 .adc1_range = STV090x_ADC_1Vpp,
333 .adc2_range = STV090x_ADC_1Vpp,
334
335 .diseqc_envelope_mode = true,
336
337 .tuner_i2c_lock = cineS2_tuner_i2c_lock,
338};
339
340static struct stv090x_config fe_cineS2_2 = {
341 .device = STV0900,
342 .demod_mode = STV090x_DUAL,
343 .clk_mode = STV090x_CLK_EXT,
344
345 .xtal = 27000000,
346 .address = 0x69,
347
348 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
349 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
350
351 .repeater_level = STV090x_RPTLEVEL_16,
352
353 .adc1_range = STV090x_ADC_1Vpp,
354 .adc2_range = STV090x_ADC_1Vpp,
355
356 .diseqc_envelope_mode = true,
357
358 .tuner_i2c_lock = cineS2_tuner_i2c_lock,
359};
360
361static struct stv6110x_config tuner_cineS2_0 = {
362 .addr = 0x60,
363 .refclk = 27000000,
364 .clk_div = 1,
365};
366
367static struct stv6110x_config tuner_cineS2_1 = {
368 .addr = 0x63,
369 .refclk = 27000000,
370 .clk_div = 1,
371};
372
373static struct ngene_info ngene_info_cineS2 = {
374 .type = NGENE_SIDEWINDER,
375 .name = "Linux4Media cineS2 DVB-S2 Twin Tuner",
376 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
377 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
378 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
379 .fe_config = {&fe_cineS2, &fe_cineS2},
380 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
381 .lnb = {0x0b, 0x08},
382 .tsf = {3, 3},
383 .fw_version = 18,
384 .msi_supported = true,
385};
386
387static struct ngene_info ngene_info_satixS2 = {
388 .type = NGENE_SIDEWINDER,
389 .name = "Mystique SaTiX-S2 Dual",
390 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
391 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
392 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
393 .fe_config = {&fe_cineS2, &fe_cineS2},
394 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
395 .lnb = {0x0b, 0x08},
396 .tsf = {3, 3},
397 .fw_version = 18,
398 .msi_supported = true,
399};
400
401static struct ngene_info ngene_info_satixS2v2 = {
402 .type = NGENE_SIDEWINDER,
403 .name = "Mystique SaTiX-S2 Dual (v2)",
404 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
405 NGENE_IO_TSOUT},
406 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900, cineS2_probe, cineS2_probe},
407 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_probe, tuner_attach_probe},
408 .fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
409 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
410 .lnb = {0x0a, 0x08, 0x0b, 0x09},
411 .tsf = {3, 3},
412 .fw_version = 18,
413 .msi_supported = true,
414};
415
416static struct ngene_info ngene_info_cineS2v5 = {
417 .type = NGENE_SIDEWINDER,
418 .name = "Linux4Media cineS2 DVB-S2 Twin Tuner (v5)",
419 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
420 NGENE_IO_TSOUT},
421 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900, cineS2_probe, cineS2_probe},
422 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_probe, tuner_attach_probe},
423 .fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
424 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
425 .lnb = {0x0a, 0x08, 0x0b, 0x09},
426 .tsf = {3, 3},
427 .fw_version = 18,
428 .msi_supported = true,
429};
430
431
432static struct ngene_info ngene_info_duoFlex = {
433 .type = NGENE_SIDEWINDER,
434 .name = "Digital Devices DuoFlex PCIe or miniPCIe",
435 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
436 NGENE_IO_TSOUT},
437 .demod_attach = {cineS2_probe, cineS2_probe, cineS2_probe, cineS2_probe},
438 .tuner_attach = {tuner_attach_probe, tuner_attach_probe, tuner_attach_probe, tuner_attach_probe},
439 .fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
440 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
441 .lnb = {0x0a, 0x08, 0x0b, 0x09},
442 .tsf = {3, 3},
443 .fw_version = 18,
444 .msi_supported = true,
445};
446
447static struct ngene_info ngene_info_m780 = {
448 .type = NGENE_APP,
449 .name = "Aver M780 ATSC/QAM-B",
450
451 /* Channel 0 is analog, which is currently unsupported */
452 .io_type = { NGENE_IO_NONE, NGENE_IO_TSIN },
453 .demod_attach = { NULL, demod_attach_lg330x },
454
455 /* Ensure these are NULL else the frame will call them (as funcs) */
456 .tuner_attach = { 0, 0, 0, 0 },
457 .fe_config = { NULL, &aver_m780 },
458 .avf = { 0 },
459
460 /* A custom electrical interface config for the demod to bridge */
461 .tsf = { 4, 4 },
462 .fw_version = 15,
463};
464
465/****************************************************************************/
466
467
468
469/****************************************************************************/
470/* PCI Subsystem ID *********************************************************/
471/****************************************************************************/
472
473#define NGENE_ID(_subvend, _subdev, _driverdata) { \
474 .vendor = NGENE_VID, .device = NGENE_PID, \
475 .subvendor = _subvend, .subdevice = _subdev, \
476 .driver_data = (unsigned long) &_driverdata }
477
478/****************************************************************************/
479
480static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
481 NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2),
482 NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2),
483 NGENE_ID(0x18c3, 0xdb01, ngene_info_satixS2),
484 NGENE_ID(0x18c3, 0xdb02, ngene_info_satixS2v2),
485 NGENE_ID(0x18c3, 0xdd00, ngene_info_cineS2v5),
486 NGENE_ID(0x18c3, 0xdd10, ngene_info_duoFlex),
487 NGENE_ID(0x18c3, 0xdd20, ngene_info_duoFlex),
488 NGENE_ID(0x1461, 0x062e, ngene_info_m780),
489 {0}
490};
491MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
492
493/****************************************************************************/
494/* Init/Exit ****************************************************************/
495/****************************************************************************/
496
497static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
498 enum pci_channel_state state)
499{
500 printk(KERN_ERR DEVICE_NAME ": PCI error\n");
501 if (state == pci_channel_io_perm_failure)
502 return PCI_ERS_RESULT_DISCONNECT;
503 if (state == pci_channel_io_frozen)
504 return PCI_ERS_RESULT_NEED_RESET;
505 return PCI_ERS_RESULT_CAN_RECOVER;
506}
507
508static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
509{
510 printk(KERN_INFO DEVICE_NAME ": link reset\n");
511 return 0;
512}
513
514static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
515{
516 printk(KERN_INFO DEVICE_NAME ": slot reset\n");
517 return 0;
518}
519
520static void ngene_resume(struct pci_dev *dev)
521{
522 printk(KERN_INFO DEVICE_NAME ": resume\n");
523}
524
525static struct pci_error_handlers ngene_errors = {
526 .error_detected = ngene_error_detected,
527 .link_reset = ngene_link_reset,
528 .slot_reset = ngene_slot_reset,
529 .resume = ngene_resume,
530};
531
532static struct pci_driver ngene_pci_driver = {
533 .name = "ngene",
534 .id_table = ngene_id_tbl,
535 .probe = ngene_probe,
536 .remove = __devexit_p(ngene_remove),
537 .err_handler = &ngene_errors,
538 .shutdown = ngene_shutdown,
539};
540
541static __init int module_init_ngene(void)
542{
543 printk(KERN_INFO
544 "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
545 return pci_register_driver(&ngene_pci_driver);
546}
547
548static __exit void module_exit_ngene(void)
549{
550 pci_unregister_driver(&ngene_pci_driver);
551}
552
553module_init(module_init_ngene);
554module_exit(module_exit_ngene);
555
556MODULE_DESCRIPTION("nGene");
557MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
558MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c
new file mode 100644
index 00000000000..f129a9303f8
--- /dev/null
+++ b/drivers/media/dvb/ngene/ngene-core.c
@@ -0,0 +1,1715 @@
1/*
2 * ngene.c: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/poll.h>
34#include <linux/io.h>
35#include <asm/div64.h>
36#include <linux/pci.h>
37#include <linux/timer.h>
38#include <linux/byteorder/generic.h>
39#include <linux/firmware.h>
40#include <linux/vmalloc.h>
41
42#include "ngene.h"
43
44static int one_adapter;
45module_param(one_adapter, int, 0444);
46MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
47
48static int shutdown_workaround;
49module_param(shutdown_workaround, int, 0644);
50MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
51
52static int debug;
53module_param(debug, int, 0444);
54MODULE_PARM_DESC(debug, "Print debugging information.");
55
56DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
57
58#define dprintk if (debug) printk
59
60#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
61#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
62#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
63#define ngreadl(adr) readl(dev->iomem + (adr))
64#define ngreadb(adr) readb(dev->iomem + (adr))
65#define ngcpyto(adr, src, count) memcpy_toio((char *) \
66 (dev->iomem + (adr)), (src), (count))
67#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
68 (dev->iomem + (adr)), (count))
69
70/****************************************************************************/
71/* nGene interrupt handler **************************************************/
72/****************************************************************************/
73
74static void event_tasklet(unsigned long data)
75{
76 struct ngene *dev = (struct ngene *)data;
77
78 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
79 struct EVENT_BUFFER Event =
80 dev->EventQueue[dev->EventQueueReadIndex];
81 dev->EventQueueReadIndex =
82 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
83
84 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
85 dev->TxEventNotify(dev, Event.TimeStamp);
86 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
87 dev->RxEventNotify(dev, Event.TimeStamp,
88 Event.RXCharacter);
89 }
90}
91
92static void demux_tasklet(unsigned long data)
93{
94 struct ngene_channel *chan = (struct ngene_channel *)data;
95 struct SBufferHeader *Cur = chan->nextBuffer;
96
97 spin_lock_irq(&chan->state_lock);
98
99 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
100 if (chan->mode & NGENE_IO_TSOUT) {
101 u32 Flags = chan->DataFormatFlags;
102 if (Cur->ngeneBuffer.SR.Flags & 0x20)
103 Flags |= BEF_OVERFLOW;
104 if (chan->pBufferExchange) {
105 if (!chan->pBufferExchange(chan,
106 Cur->Buffer1,
107 chan->Capture1Length,
108 Cur->ngeneBuffer.SR.
109 Clock, Flags)) {
110 /*
111 We didn't get data
112 Clear in service flag to make sure we
113 get called on next interrupt again.
114 leave fill/empty (0x80) flag alone
115 to avoid hardware running out of
116 buffers during startup, we hold only
117 in run state ( the source may be late
118 delivering data )
119 */
120
121 if (chan->HWState == HWSTATE_RUN) {
122 Cur->ngeneBuffer.SR.Flags &=
123 ~0x40;
124 break;
125 /* Stop processing stream */
126 }
127 } else {
128 /* We got a valid buffer,
129 so switch to run state */
130 chan->HWState = HWSTATE_RUN;
131 }
132 } else {
133 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
134 if (chan->HWState == HWSTATE_RUN) {
135 Cur->ngeneBuffer.SR.Flags &= ~0x40;
136 break; /* Stop processing stream */
137 }
138 }
139 if (chan->AudioDTOUpdated) {
140 printk(KERN_INFO DEVICE_NAME
141 ": Update AudioDTO = %d\n",
142 chan->AudioDTOValue);
143 Cur->ngeneBuffer.SR.DTOUpdate =
144 chan->AudioDTOValue;
145 chan->AudioDTOUpdated = 0;
146 }
147 } else {
148 if (chan->HWState == HWSTATE_RUN) {
149 u32 Flags = chan->DataFormatFlags;
150 IBufferExchange *exch1 = chan->pBufferExchange;
151 IBufferExchange *exch2 = chan->pBufferExchange2;
152 if (Cur->ngeneBuffer.SR.Flags & 0x01)
153 Flags |= BEF_EVEN_FIELD;
154 if (Cur->ngeneBuffer.SR.Flags & 0x20)
155 Flags |= BEF_OVERFLOW;
156 spin_unlock_irq(&chan->state_lock);
157 if (exch1)
158 exch1(chan, Cur->Buffer1,
159 chan->Capture1Length,
160 Cur->ngeneBuffer.SR.Clock,
161 Flags);
162 if (exch2)
163 exch2(chan, Cur->Buffer2,
164 chan->Capture2Length,
165 Cur->ngeneBuffer.SR.Clock,
166 Flags);
167 spin_lock_irq(&chan->state_lock);
168 } else if (chan->HWState != HWSTATE_STOP)
169 chan->HWState = HWSTATE_RUN;
170 }
171 Cur->ngeneBuffer.SR.Flags = 0x00;
172 Cur = Cur->Next;
173 }
174 chan->nextBuffer = Cur;
175
176 spin_unlock_irq(&chan->state_lock);
177}
178
179static irqreturn_t irq_handler(int irq, void *dev_id)
180{
181 struct ngene *dev = (struct ngene *)dev_id;
182 u32 icounts = 0;
183 irqreturn_t rc = IRQ_NONE;
184 u32 i = MAX_STREAM;
185 u8 *tmpCmdDoneByte;
186
187 if (dev->BootFirmware) {
188 icounts = ngreadl(NGENE_INT_COUNTS);
189 if (icounts != dev->icounts) {
190 ngwritel(0, FORCE_NMI);
191 dev->cmd_done = 1;
192 wake_up(&dev->cmd_wq);
193 dev->icounts = icounts;
194 rc = IRQ_HANDLED;
195 }
196 return rc;
197 }
198
199 ngwritel(0, FORCE_NMI);
200
201 spin_lock(&dev->cmd_lock);
202 tmpCmdDoneByte = dev->CmdDoneByte;
203 if (tmpCmdDoneByte &&
204 (*tmpCmdDoneByte ||
205 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
206 dev->CmdDoneByte = NULL;
207 dev->cmd_done = 1;
208 wake_up(&dev->cmd_wq);
209 rc = IRQ_HANDLED;
210 }
211 spin_unlock(&dev->cmd_lock);
212
213 if (dev->EventBuffer->EventStatus & 0x80) {
214 u8 nextWriteIndex =
215 (dev->EventQueueWriteIndex + 1) &
216 (EVENT_QUEUE_SIZE - 1);
217 if (nextWriteIndex != dev->EventQueueReadIndex) {
218 dev->EventQueue[dev->EventQueueWriteIndex] =
219 *(dev->EventBuffer);
220 dev->EventQueueWriteIndex = nextWriteIndex;
221 } else {
222 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
223 dev->EventQueueOverflowCount += 1;
224 dev->EventQueueOverflowFlag = 1;
225 }
226 dev->EventBuffer->EventStatus &= ~0x80;
227 tasklet_schedule(&dev->event_tasklet);
228 rc = IRQ_HANDLED;
229 }
230
231 while (i > 0) {
232 i--;
233 spin_lock(&dev->channel[i].state_lock);
234 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
235 if (dev->channel[i].nextBuffer) {
236 if ((dev->channel[i].nextBuffer->
237 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
238 dev->channel[i].nextBuffer->
239 ngeneBuffer.SR.Flags |= 0x40;
240 tasklet_schedule(
241 &dev->channel[i].demux_tasklet);
242 rc = IRQ_HANDLED;
243 }
244 }
245 spin_unlock(&dev->channel[i].state_lock);
246 }
247
248 /* Request might have been processed by a previous call. */
249 return IRQ_HANDLED;
250}
251
252/****************************************************************************/
253/* nGene command interface **************************************************/
254/****************************************************************************/
255
256static void dump_command_io(struct ngene *dev)
257{
258 u8 buf[8], *b;
259
260 ngcpyfrom(buf, HOST_TO_NGENE, 8);
261 printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
262 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
263 buf[4], buf[5], buf[6], buf[7]);
264
265 ngcpyfrom(buf, NGENE_TO_HOST, 8);
266 printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
267 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
268 buf[4], buf[5], buf[6], buf[7]);
269
270 b = dev->hosttongene;
271 printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
272 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
273
274 b = dev->ngenetohost;
275 printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
276 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
277}
278
279static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
280{
281 int ret;
282 u8 *tmpCmdDoneByte;
283
284 dev->cmd_done = 0;
285
286 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
287 dev->BootFirmware = 1;
288 dev->icounts = ngreadl(NGENE_INT_COUNTS);
289 ngwritel(0, NGENE_COMMAND);
290 ngwritel(0, NGENE_COMMAND_HI);
291 ngwritel(0, NGENE_STATUS);
292 ngwritel(0, NGENE_STATUS_HI);
293 ngwritel(0, NGENE_EVENT);
294 ngwritel(0, NGENE_EVENT_HI);
295 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
296 u64 fwio = dev->PAFWInterfaceBuffer;
297
298 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
299 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
300 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
301 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
302 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
303 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
304 }
305
306 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
307
308 if (dev->BootFirmware)
309 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
310
311 spin_lock_irq(&dev->cmd_lock);
312 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
313 if (!com->out_len)
314 tmpCmdDoneByte++;
315 *tmpCmdDoneByte = 0;
316 dev->ngenetohost[0] = 0;
317 dev->ngenetohost[1] = 0;
318 dev->CmdDoneByte = tmpCmdDoneByte;
319 spin_unlock_irq(&dev->cmd_lock);
320
321 /* Notify 8051. */
322 ngwritel(1, FORCE_INT);
323
324 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
325 if (!ret) {
326 /*ngwritel(0, FORCE_NMI);*/
327
328 printk(KERN_ERR DEVICE_NAME
329 ": Command timeout cmd=%02x prev=%02x\n",
330 com->cmd.hdr.Opcode, dev->prev_cmd);
331 dump_command_io(dev);
332 return -1;
333 }
334 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
335 dev->BootFirmware = 0;
336
337 dev->prev_cmd = com->cmd.hdr.Opcode;
338
339 if (!com->out_len)
340 return 0;
341
342 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
343
344 return 0;
345}
346
347int ngene_command(struct ngene *dev, struct ngene_command *com)
348{
349 int result;
350
351 down(&dev->cmd_mutex);
352 result = ngene_command_mutex(dev, com);
353 up(&dev->cmd_mutex);
354 return result;
355}
356
357
358static int ngene_command_load_firmware(struct ngene *dev,
359 u8 *ngene_fw, u32 size)
360{
361#define FIRSTCHUNK (1024)
362 u32 cleft;
363 struct ngene_command com;
364
365 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
366 com.cmd.hdr.Length = 0;
367 com.in_len = 0;
368 com.out_len = 0;
369
370 ngene_command(dev, &com);
371
372 cleft = (size + 3) & ~3;
373 if (cleft > FIRSTCHUNK) {
374 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
375 cleft - FIRSTCHUNK);
376 cleft = FIRSTCHUNK;
377 }
378 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
379
380 memset(&com, 0, sizeof(struct ngene_command));
381 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
382 com.cmd.hdr.Length = 4;
383 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
384 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
385 com.in_len = 4;
386 com.out_len = 0;
387
388 return ngene_command(dev, &com);
389}
390
391
392static int ngene_command_config_buf(struct ngene *dev, u8 config)
393{
394 struct ngene_command com;
395
396 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
397 com.cmd.hdr.Length = 1;
398 com.cmd.ConfigureBuffers.config = config;
399 com.in_len = 1;
400 com.out_len = 0;
401
402 if (ngene_command(dev, &com) < 0)
403 return -EIO;
404 return 0;
405}
406
407static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
408{
409 struct ngene_command com;
410
411 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
412 com.cmd.hdr.Length = 6;
413 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
414 com.in_len = 6;
415 com.out_len = 0;
416
417 if (ngene_command(dev, &com) < 0)
418 return -EIO;
419
420 return 0;
421}
422
423int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
424{
425 struct ngene_command com;
426
427 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
428 com.cmd.hdr.Length = 1;
429 com.cmd.SetGpioPin.select = select | (level << 7);
430 com.in_len = 1;
431 com.out_len = 0;
432
433 return ngene_command(dev, &com);
434}
435
436
437/*
438 02000640 is sample on rising edge.
439 02000740 is sample on falling edge.
440 02000040 is ignore "valid" signal
441
442 0: FD_CTL1 Bit 7,6 must be 0,1
443 7 disable(fw controlled)
444 6 0-AUX,1-TS
445 5 0-par,1-ser
446 4 0-lsb/1-msb
447 3,2 reserved
448 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
449 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
450 2: FD_STA is read-only. 0-sync
451 3: FD_INSYNC is number of 47s to trigger "in sync".
452 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
453 5: FD_MAXBYTE1 is low-order of bytes per packet.
454 6: FD_MAXBYTE2 is high-order of bytes per packet.
455 7: Top byte is unused.
456*/
457
458/****************************************************************************/
459
460static u8 TSFeatureDecoderSetup[8 * 5] = {
461 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
462 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
463 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
464 0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
465 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
466};
467
468/* Set NGENE I2S Config to 16 bit packed */
469static u8 I2SConfiguration[] = {
470 0x00, 0x10, 0x00, 0x00,
471 0x80, 0x10, 0x00, 0x00,
472};
473
474static u8 SPDIFConfiguration[10] = {
475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
476};
477
478/* Set NGENE I2S Config to transport stream compatible mode */
479
480static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
481
482static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
483
484static u8 ITUDecoderSetup[4][16] = {
485 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
486 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
487 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
488 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
489 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
490 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
491 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
492 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
493};
494
495/*
496 * 50 48 60 gleich
497 * 27p50 9f 00 22 80 42 69 18 ...
498 * 27p60 93 00 22 80 82 69 1c ...
499 */
500
501/* Maxbyte to 1144 (for raw data) */
502static u8 ITUFeatureDecoderSetup[8] = {
503 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
504};
505
506void FillTSBuffer(void *Buffer, int Length, u32 Flags)
507{
508 u32 *ptr = Buffer;
509
510 memset(Buffer, TS_FILLER, Length);
511 while (Length > 0) {
512 if (Flags & DF_SWAP32)
513 *ptr = 0x471FFF10;
514 else
515 *ptr = 0x10FF1F47;
516 ptr += (188 / 4);
517 Length -= 188;
518 }
519}
520
521
522static void flush_buffers(struct ngene_channel *chan)
523{
524 u8 val;
525
526 do {
527 msleep(1);
528 spin_lock_irq(&chan->state_lock);
529 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
530 spin_unlock_irq(&chan->state_lock);
531 } while (val);
532}
533
534static void clear_buffers(struct ngene_channel *chan)
535{
536 struct SBufferHeader *Cur = chan->nextBuffer;
537
538 do {
539 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
540 if (chan->mode & NGENE_IO_TSOUT)
541 FillTSBuffer(Cur->Buffer1,
542 chan->Capture1Length,
543 chan->DataFormatFlags);
544 Cur = Cur->Next;
545 } while (Cur != chan->nextBuffer);
546
547 if (chan->mode & NGENE_IO_TSOUT) {
548 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
549 chan->AudioDTOValue;
550 chan->AudioDTOUpdated = 0;
551
552 Cur = chan->TSIdleBuffer.Head;
553
554 do {
555 memset(&Cur->ngeneBuffer.SR, 0,
556 sizeof(Cur->ngeneBuffer.SR));
557 FillTSBuffer(Cur->Buffer1,
558 chan->Capture1Length,
559 chan->DataFormatFlags);
560 Cur = Cur->Next;
561 } while (Cur != chan->TSIdleBuffer.Head);
562 }
563}
564
565static int ngene_command_stream_control(struct ngene *dev, u8 stream,
566 u8 control, u8 mode, u8 flags)
567{
568 struct ngene_channel *chan = &dev->channel[stream];
569 struct ngene_command com;
570 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
571 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
572 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
573 u16 BsSDO = 0x9B00;
574
575 down(&dev->stream_mutex);
576 memset(&com, 0, sizeof(com));
577 com.cmd.hdr.Opcode = CMD_CONTROL;
578 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
579 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
580 if (chan->mode & NGENE_IO_TSOUT)
581 com.cmd.StreamControl.Stream |= 0x07;
582 com.cmd.StreamControl.Control = control |
583 (flags & SFLAG_ORDER_LUMA_CHROMA);
584 com.cmd.StreamControl.Mode = mode;
585 com.in_len = sizeof(struct FW_STREAM_CONTROL);
586 com.out_len = 0;
587
588 dprintk(KERN_INFO DEVICE_NAME
589 ": Stream=%02x, Control=%02x, Mode=%02x\n",
590 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
591 com.cmd.StreamControl.Mode);
592
593 chan->Mode = mode;
594
595 if (!(control & 0x80)) {
596 spin_lock_irq(&chan->state_lock);
597 if (chan->State == KSSTATE_RUN) {
598 chan->State = KSSTATE_ACQUIRE;
599 chan->HWState = HWSTATE_STOP;
600 spin_unlock_irq(&chan->state_lock);
601 if (ngene_command(dev, &com) < 0) {
602 up(&dev->stream_mutex);
603 return -1;
604 }
605 /* clear_buffers(chan); */
606 flush_buffers(chan);
607 up(&dev->stream_mutex);
608 return 0;
609 }
610 spin_unlock_irq(&chan->state_lock);
611 up(&dev->stream_mutex);
612 return 0;
613 }
614
615 if (mode & SMODE_AUDIO_CAPTURE) {
616 com.cmd.StreamControl.CaptureBlockCount =
617 chan->Capture1Length / AUDIO_BLOCK_SIZE;
618 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
619 } else if (mode & SMODE_TRANSPORT_STREAM) {
620 com.cmd.StreamControl.CaptureBlockCount =
621 chan->Capture1Length / TS_BLOCK_SIZE;
622 com.cmd.StreamControl.MaxLinesPerField =
623 chan->Capture1Length / TS_BLOCK_SIZE;
624 com.cmd.StreamControl.Buffer_Address =
625 chan->TSRingBuffer.PAHead;
626 if (chan->mode & NGENE_IO_TSOUT) {
627 com.cmd.StreamControl.BytesPerVBILine =
628 chan->Capture1Length / TS_BLOCK_SIZE;
629 com.cmd.StreamControl.Stream |= 0x07;
630 }
631 } else {
632 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
633 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
634 com.cmd.StreamControl.MinLinesPerField = 100;
635 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
636
637 if (mode & SMODE_VBI_CAPTURE) {
638 com.cmd.StreamControl.MaxVBILinesPerField =
639 chan->nVBILines;
640 com.cmd.StreamControl.MinVBILinesPerField = 0;
641 com.cmd.StreamControl.BytesPerVBILine =
642 chan->nBytesPerVBILine;
643 }
644 if (flags & SFLAG_COLORBAR)
645 com.cmd.StreamControl.Stream |= 0x04;
646 }
647
648 spin_lock_irq(&chan->state_lock);
649 if (mode & SMODE_AUDIO_CAPTURE) {
650 chan->nextBuffer = chan->RingBuffer.Head;
651 if (mode & SMODE_AUDIO_SPDIF) {
652 com.cmd.StreamControl.SetupDataLen =
653 sizeof(SPDIFConfiguration);
654 com.cmd.StreamControl.SetupDataAddr = BsSPI;
655 memcpy(com.cmd.StreamControl.SetupData,
656 SPDIFConfiguration, sizeof(SPDIFConfiguration));
657 } else {
658 com.cmd.StreamControl.SetupDataLen = 4;
659 com.cmd.StreamControl.SetupDataAddr = BsSDI;
660 memcpy(com.cmd.StreamControl.SetupData,
661 I2SConfiguration +
662 4 * dev->card_info->i2s[stream], 4);
663 }
664 } else if (mode & SMODE_TRANSPORT_STREAM) {
665 chan->nextBuffer = chan->TSRingBuffer.Head;
666 if (stream >= STREAM_AUDIOIN1) {
667 if (chan->mode & NGENE_IO_TSOUT) {
668 com.cmd.StreamControl.SetupDataLen =
669 sizeof(TS_I2SOutConfiguration);
670 com.cmd.StreamControl.SetupDataAddr = BsSDO;
671 memcpy(com.cmd.StreamControl.SetupData,
672 TS_I2SOutConfiguration,
673 sizeof(TS_I2SOutConfiguration));
674 } else {
675 com.cmd.StreamControl.SetupDataLen =
676 sizeof(TS_I2SConfiguration);
677 com.cmd.StreamControl.SetupDataAddr = BsSDI;
678 memcpy(com.cmd.StreamControl.SetupData,
679 TS_I2SConfiguration,
680 sizeof(TS_I2SConfiguration));
681 }
682 } else {
683 com.cmd.StreamControl.SetupDataLen = 8;
684 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
685 memcpy(com.cmd.StreamControl.SetupData,
686 TSFeatureDecoderSetup +
687 8 * dev->card_info->tsf[stream], 8);
688 }
689 } else {
690 chan->nextBuffer = chan->RingBuffer.Head;
691 com.cmd.StreamControl.SetupDataLen =
692 16 + sizeof(ITUFeatureDecoderSetup);
693 com.cmd.StreamControl.SetupDataAddr = BsUVI;
694 memcpy(com.cmd.StreamControl.SetupData,
695 ITUDecoderSetup[chan->itumode], 16);
696 memcpy(com.cmd.StreamControl.SetupData + 16,
697 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
698 }
699 clear_buffers(chan);
700 chan->State = KSSTATE_RUN;
701 if (mode & SMODE_TRANSPORT_STREAM)
702 chan->HWState = HWSTATE_RUN;
703 else
704 chan->HWState = HWSTATE_STARTUP;
705 spin_unlock_irq(&chan->state_lock);
706
707 if (ngene_command(dev, &com) < 0) {
708 up(&dev->stream_mutex);
709 return -1;
710 }
711 up(&dev->stream_mutex);
712 return 0;
713}
714
715void set_transfer(struct ngene_channel *chan, int state)
716{
717 u8 control = 0, mode = 0, flags = 0;
718 struct ngene *dev = chan->dev;
719 int ret;
720
721 /*
722 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
723 msleep(100);
724 */
725
726 if (state) {
727 if (chan->running) {
728 printk(KERN_INFO DEVICE_NAME ": already running\n");
729 return;
730 }
731 } else {
732 if (!chan->running) {
733 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
734 return;
735 }
736 }
737
738 if (dev->card_info->switch_ctrl)
739 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
740
741 if (state) {
742 spin_lock_irq(&chan->state_lock);
743
744 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
745 ngreadl(0x9310)); */
746 dvb_ringbuffer_flush(&dev->tsout_rbuf);
747 control = 0x80;
748 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
749 chan->Capture1Length = 512 * 188;
750 mode = SMODE_TRANSPORT_STREAM;
751 }
752 if (chan->mode & NGENE_IO_TSOUT) {
753 chan->pBufferExchange = tsout_exchange;
754 /* 0x66666666 = 50MHz *2^33 /250MHz */
755 chan->AudioDTOValue = 0x80000000;
756 chan->AudioDTOUpdated = 1;
757 }
758 if (chan->mode & NGENE_IO_TSIN)
759 chan->pBufferExchange = tsin_exchange;
760 spin_unlock_irq(&chan->state_lock);
761 } else
762 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
763 ngreadl(0x9310)); */
764
765 ret = ngene_command_stream_control(dev, chan->number,
766 control, mode, flags);
767 if (!ret)
768 chan->running = state;
769 else
770 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
771 state);
772 if (!state) {
773 spin_lock_irq(&chan->state_lock);
774 chan->pBufferExchange = NULL;
775 dvb_ringbuffer_flush(&dev->tsout_rbuf);
776 spin_unlock_irq(&chan->state_lock);
777 }
778}
779
780
781/****************************************************************************/
782/* nGene hardware init and release functions ********************************/
783/****************************************************************************/
784
785static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
786{
787 struct SBufferHeader *Cur = rb->Head;
788 u32 j;
789
790 if (!Cur)
791 return;
792
793 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
794 if (Cur->Buffer1)
795 pci_free_consistent(dev->pci_dev,
796 rb->Buffer1Length,
797 Cur->Buffer1,
798 Cur->scList1->Address);
799
800 if (Cur->Buffer2)
801 pci_free_consistent(dev->pci_dev,
802 rb->Buffer2Length,
803 Cur->Buffer2,
804 Cur->scList2->Address);
805 }
806
807 if (rb->SCListMem)
808 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
809 rb->SCListMem, rb->PASCListMem);
810
811 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
812}
813
814static void free_idlebuffer(struct ngene *dev,
815 struct SRingBufferDescriptor *rb,
816 struct SRingBufferDescriptor *tb)
817{
818 int j;
819 struct SBufferHeader *Cur = tb->Head;
820
821 if (!rb->Head)
822 return;
823 free_ringbuffer(dev, rb);
824 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
825 Cur->Buffer2 = NULL;
826 Cur->scList2 = NULL;
827 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
828 Cur->ngeneBuffer.Number_of_entries_2 = 0;
829 }
830}
831
832static void free_common_buffers(struct ngene *dev)
833{
834 u32 i;
835 struct ngene_channel *chan;
836
837 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
838 chan = &dev->channel[i];
839 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
840 free_ringbuffer(dev, &chan->RingBuffer);
841 free_ringbuffer(dev, &chan->TSRingBuffer);
842 }
843
844 if (dev->OverflowBuffer)
845 pci_free_consistent(dev->pci_dev,
846 OVERFLOW_BUFFER_SIZE,
847 dev->OverflowBuffer, dev->PAOverflowBuffer);
848
849 if (dev->FWInterfaceBuffer)
850 pci_free_consistent(dev->pci_dev,
851 4096,
852 dev->FWInterfaceBuffer,
853 dev->PAFWInterfaceBuffer);
854}
855
856/****************************************************************************/
857/* Ring buffer handling *****************************************************/
858/****************************************************************************/
859
860static int create_ring_buffer(struct pci_dev *pci_dev,
861 struct SRingBufferDescriptor *descr, u32 NumBuffers)
862{
863 dma_addr_t tmp;
864 struct SBufferHeader *Head;
865 u32 i;
866 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
867 u64 PARingBufferHead;
868 u64 PARingBufferCur;
869 u64 PARingBufferNext;
870 struct SBufferHeader *Cur, *Next;
871
872 descr->Head = NULL;
873 descr->MemSize = 0;
874 descr->PAHead = 0;
875 descr->NumBuffers = 0;
876
877 if (MemSize < 4096)
878 MemSize = 4096;
879
880 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
881 PARingBufferHead = tmp;
882
883 if (!Head)
884 return -ENOMEM;
885
886 memset(Head, 0, MemSize);
887
888 PARingBufferCur = PARingBufferHead;
889 Cur = Head;
890
891 for (i = 0; i < NumBuffers - 1; i++) {
892 Next = (struct SBufferHeader *)
893 (((u8 *) Cur) + SIZEOF_SBufferHeader);
894 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
895 Cur->Next = Next;
896 Cur->ngeneBuffer.Next = PARingBufferNext;
897 Cur = Next;
898 PARingBufferCur = PARingBufferNext;
899 }
900 /* Last Buffer points back to first one */
901 Cur->Next = Head;
902 Cur->ngeneBuffer.Next = PARingBufferHead;
903
904 descr->Head = Head;
905 descr->MemSize = MemSize;
906 descr->PAHead = PARingBufferHead;
907 descr->NumBuffers = NumBuffers;
908
909 return 0;
910}
911
912static int AllocateRingBuffers(struct pci_dev *pci_dev,
913 dma_addr_t of,
914 struct SRingBufferDescriptor *pRingBuffer,
915 u32 Buffer1Length, u32 Buffer2Length)
916{
917 dma_addr_t tmp;
918 u32 i, j;
919 int status = 0;
920 u32 SCListMemSize = pRingBuffer->NumBuffers
921 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
922 NUM_SCATTER_GATHER_ENTRIES)
923 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
924
925 u64 PASCListMem;
926 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
927 u64 PASCListEntry;
928 struct SBufferHeader *Cur;
929 void *SCListMem;
930
931 if (SCListMemSize < 4096)
932 SCListMemSize = 4096;
933
934 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
935
936 PASCListMem = tmp;
937 if (SCListMem == NULL)
938 return -ENOMEM;
939
940 memset(SCListMem, 0, SCListMemSize);
941
942 pRingBuffer->SCListMem = SCListMem;
943 pRingBuffer->PASCListMem = PASCListMem;
944 pRingBuffer->SCListMemSize = SCListMemSize;
945 pRingBuffer->Buffer1Length = Buffer1Length;
946 pRingBuffer->Buffer2Length = Buffer2Length;
947
948 SCListEntry = SCListMem;
949 PASCListEntry = PASCListMem;
950 Cur = pRingBuffer->Head;
951
952 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
953 u64 PABuffer;
954
955 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
956 &tmp);
957 PABuffer = tmp;
958
959 if (Buffer == NULL)
960 return -ENOMEM;
961
962 Cur->Buffer1 = Buffer;
963
964 SCListEntry->Address = PABuffer;
965 SCListEntry->Length = Buffer1Length;
966
967 Cur->scList1 = SCListEntry;
968 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
969 Cur->ngeneBuffer.Number_of_entries_1 =
970 NUM_SCATTER_GATHER_ENTRIES;
971
972 SCListEntry += 1;
973 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
974
975#if NUM_SCATTER_GATHER_ENTRIES > 1
976 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
977 SCListEntry->Address = of;
978 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
979 SCListEntry += 1;
980 PASCListEntry +=
981 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
982 }
983#endif
984
985 if (!Buffer2Length)
986 continue;
987
988 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
989 PABuffer = tmp;
990
991 if (Buffer == NULL)
992 return -ENOMEM;
993
994 Cur->Buffer2 = Buffer;
995
996 SCListEntry->Address = PABuffer;
997 SCListEntry->Length = Buffer2Length;
998
999 Cur->scList2 = SCListEntry;
1000 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1001 Cur->ngeneBuffer.Number_of_entries_2 =
1002 NUM_SCATTER_GATHER_ENTRIES;
1003
1004 SCListEntry += 1;
1005 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1006
1007#if NUM_SCATTER_GATHER_ENTRIES > 1
1008 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1009 SCListEntry->Address = of;
1010 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1011 SCListEntry += 1;
1012 PASCListEntry +=
1013 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1014 }
1015#endif
1016
1017 }
1018
1019 return status;
1020}
1021
1022static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1023 struct SRingBufferDescriptor *pRingBuffer)
1024{
1025 int status = 0;
1026
1027 /* Copy pointer to scatter gather list in TSRingbuffer
1028 structure for buffer 2
1029 Load number of buffer
1030 */
1031 u32 n = pRingBuffer->NumBuffers;
1032
1033 /* Point to first buffer entry */
1034 struct SBufferHeader *Cur = pRingBuffer->Head;
1035 int i;
1036 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1037 for (i = 0; i < n; i++) {
1038 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1039 Cur->scList2 = pIdleBuffer->Head->scList1;
1040 Cur->ngeneBuffer.Address_of_first_entry_2 =
1041 pIdleBuffer->Head->ngeneBuffer.
1042 Address_of_first_entry_1;
1043 Cur->ngeneBuffer.Number_of_entries_2 =
1044 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1045 Cur = Cur->Next;
1046 }
1047 return status;
1048}
1049
1050static u32 RingBufferSizes[MAX_STREAM] = {
1051 RING_SIZE_VIDEO,
1052 RING_SIZE_VIDEO,
1053 RING_SIZE_AUDIO,
1054 RING_SIZE_AUDIO,
1055 RING_SIZE_AUDIO,
1056};
1057
1058static u32 Buffer1Sizes[MAX_STREAM] = {
1059 MAX_VIDEO_BUFFER_SIZE,
1060 MAX_VIDEO_BUFFER_SIZE,
1061 MAX_AUDIO_BUFFER_SIZE,
1062 MAX_AUDIO_BUFFER_SIZE,
1063 MAX_AUDIO_BUFFER_SIZE
1064};
1065
1066static u32 Buffer2Sizes[MAX_STREAM] = {
1067 MAX_VBI_BUFFER_SIZE,
1068 MAX_VBI_BUFFER_SIZE,
1069 0,
1070 0,
1071 0
1072};
1073
1074
1075static int AllocCommonBuffers(struct ngene *dev)
1076{
1077 int status = 0, i;
1078
1079 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1080 &dev->PAFWInterfaceBuffer);
1081 if (!dev->FWInterfaceBuffer)
1082 return -ENOMEM;
1083 dev->hosttongene = dev->FWInterfaceBuffer;
1084 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1085 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1086
1087 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1088 OVERFLOW_BUFFER_SIZE,
1089 &dev->PAOverflowBuffer);
1090 if (!dev->OverflowBuffer)
1091 return -ENOMEM;
1092 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1093
1094 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1095 int type = dev->card_info->io_type[i];
1096
1097 dev->channel[i].State = KSSTATE_STOP;
1098
1099 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1100 status = create_ring_buffer(dev->pci_dev,
1101 &dev->channel[i].RingBuffer,
1102 RingBufferSizes[i]);
1103 if (status < 0)
1104 break;
1105
1106 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1107 status = AllocateRingBuffers(dev->pci_dev,
1108 dev->
1109 PAOverflowBuffer,
1110 &dev->channel[i].
1111 RingBuffer,
1112 Buffer1Sizes[i],
1113 Buffer2Sizes[i]);
1114 if (status < 0)
1115 break;
1116 } else if (type & NGENE_IO_HDTV) {
1117 status = AllocateRingBuffers(dev->pci_dev,
1118 dev->
1119 PAOverflowBuffer,
1120 &dev->channel[i].
1121 RingBuffer,
1122 MAX_HDTV_BUFFER_SIZE,
1123 0);
1124 if (status < 0)
1125 break;
1126 }
1127 }
1128
1129 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1130
1131 status = create_ring_buffer(dev->pci_dev,
1132 &dev->channel[i].
1133 TSRingBuffer, RING_SIZE_TS);
1134 if (status < 0)
1135 break;
1136
1137 status = AllocateRingBuffers(dev->pci_dev,
1138 dev->PAOverflowBuffer,
1139 &dev->channel[i].
1140 TSRingBuffer,
1141 MAX_TS_BUFFER_SIZE, 0);
1142 if (status)
1143 break;
1144 }
1145
1146 if (type & NGENE_IO_TSOUT) {
1147 status = create_ring_buffer(dev->pci_dev,
1148 &dev->channel[i].
1149 TSIdleBuffer, 1);
1150 if (status < 0)
1151 break;
1152 status = AllocateRingBuffers(dev->pci_dev,
1153 dev->PAOverflowBuffer,
1154 &dev->channel[i].
1155 TSIdleBuffer,
1156 MAX_TS_BUFFER_SIZE, 0);
1157 if (status)
1158 break;
1159 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1160 &dev->channel[i].TSRingBuffer);
1161 }
1162 }
1163 return status;
1164}
1165
1166static void ngene_release_buffers(struct ngene *dev)
1167{
1168 if (dev->iomem)
1169 iounmap(dev->iomem);
1170 free_common_buffers(dev);
1171 vfree(dev->tsout_buf);
1172 vfree(dev->tsin_buf);
1173 vfree(dev->ain_buf);
1174 vfree(dev->vin_buf);
1175 vfree(dev);
1176}
1177
1178static int ngene_get_buffers(struct ngene *dev)
1179{
1180 if (AllocCommonBuffers(dev))
1181 return -ENOMEM;
1182 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1183 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1184 if (!dev->tsout_buf)
1185 return -ENOMEM;
1186 dvb_ringbuffer_init(&dev->tsout_rbuf,
1187 dev->tsout_buf, TSOUT_BUF_SIZE);
1188 }
1189 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1190 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1191 if (!dev->tsin_buf)
1192 return -ENOMEM;
1193 dvb_ringbuffer_init(&dev->tsin_rbuf,
1194 dev->tsin_buf, TSIN_BUF_SIZE);
1195 }
1196 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1197 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1198 if (!dev->ain_buf)
1199 return -ENOMEM;
1200 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1201 }
1202 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1203 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1204 if (!dev->vin_buf)
1205 return -ENOMEM;
1206 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1207 }
1208 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1209 pci_resource_len(dev->pci_dev, 0));
1210 if (!dev->iomem)
1211 return -ENOMEM;
1212
1213 return 0;
1214}
1215
1216static void ngene_init(struct ngene *dev)
1217{
1218 int i;
1219
1220 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1221
1222 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1223 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1224
1225 for (i = 0; i < MAX_STREAM; i++) {
1226 dev->channel[i].dev = dev;
1227 dev->channel[i].number = i;
1228 }
1229
1230 dev->fw_interface_version = 0;
1231
1232 ngwritel(0, NGENE_INT_ENABLE);
1233
1234 dev->icounts = ngreadl(NGENE_INT_COUNTS);
1235
1236 dev->device_version = ngreadl(DEV_VER) & 0x0f;
1237 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1238 dev->device_version);
1239}
1240
1241static int ngene_load_firm(struct ngene *dev)
1242{
1243 u32 size;
1244 const struct firmware *fw = NULL;
1245 u8 *ngene_fw;
1246 char *fw_name;
1247 int err, version;
1248
1249 version = dev->card_info->fw_version;
1250
1251 switch (version) {
1252 default:
1253 case 15:
1254 version = 15;
1255 size = 23466;
1256 fw_name = "ngene_15.fw";
1257 dev->cmd_timeout_workaround = true;
1258 break;
1259 case 16:
1260 size = 23498;
1261 fw_name = "ngene_16.fw";
1262 dev->cmd_timeout_workaround = true;
1263 break;
1264 case 17:
1265 size = 24446;
1266 fw_name = "ngene_17.fw";
1267 dev->cmd_timeout_workaround = true;
1268 break;
1269 case 18:
1270 size = 0;
1271 fw_name = "ngene_18.fw";
1272 break;
1273 }
1274
1275 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1276 printk(KERN_ERR DEVICE_NAME
1277 ": Could not load firmware file %s.\n", fw_name);
1278 printk(KERN_INFO DEVICE_NAME
1279 ": Copy %s to your hotplug directory!\n", fw_name);
1280 return -1;
1281 }
1282 if (size == 0)
1283 size = fw->size;
1284 if (size != fw->size) {
1285 printk(KERN_ERR DEVICE_NAME
1286 ": Firmware %s has invalid size!", fw_name);
1287 err = -1;
1288 } else {
1289 printk(KERN_INFO DEVICE_NAME
1290 ": Loading firmware file %s.\n", fw_name);
1291 ngene_fw = (u8 *) fw->data;
1292 err = ngene_command_load_firmware(dev, ngene_fw, size);
1293 }
1294
1295 release_firmware(fw);
1296
1297 return err;
1298}
1299
1300static void ngene_stop(struct ngene *dev)
1301{
1302 down(&dev->cmd_mutex);
1303 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1304 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1305 ngwritel(0, NGENE_INT_ENABLE);
1306 ngwritel(0, NGENE_COMMAND);
1307 ngwritel(0, NGENE_COMMAND_HI);
1308 ngwritel(0, NGENE_STATUS);
1309 ngwritel(0, NGENE_STATUS_HI);
1310 ngwritel(0, NGENE_EVENT);
1311 ngwritel(0, NGENE_EVENT_HI);
1312 free_irq(dev->pci_dev->irq, dev);
1313#ifdef CONFIG_PCI_MSI
1314 if (dev->msi_enabled)
1315 pci_disable_msi(dev->pci_dev);
1316#endif
1317}
1318
1319static int ngene_buffer_config(struct ngene *dev)
1320{
1321 int stat;
1322
1323 if (dev->card_info->fw_version >= 17) {
1324 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1325 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1326 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1327 u8 *bconf = tsin12_config;
1328
1329 if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1330 dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1331 bconf = tsin1234_config;
1332 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1333 dev->ci.en)
1334 bconf = tsio1235_config;
1335 }
1336 stat = ngene_command_config_free_buf(dev, bconf);
1337 } else {
1338 int bconf = BUFFER_CONFIG_4422;
1339
1340 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1341 bconf = BUFFER_CONFIG_3333;
1342 stat = ngene_command_config_buf(dev, bconf);
1343 }
1344 return stat;
1345}
1346
1347
1348static int ngene_start(struct ngene *dev)
1349{
1350 int stat;
1351 int i;
1352
1353 pci_set_master(dev->pci_dev);
1354 ngene_init(dev);
1355
1356 stat = request_irq(dev->pci_dev->irq, irq_handler,
1357 IRQF_SHARED, "nGene",
1358 (void *)dev);
1359 if (stat < 0)
1360 return stat;
1361
1362 init_waitqueue_head(&dev->cmd_wq);
1363 init_waitqueue_head(&dev->tx_wq);
1364 init_waitqueue_head(&dev->rx_wq);
1365 sema_init(&dev->cmd_mutex, 1);
1366 sema_init(&dev->stream_mutex, 1);
1367 sema_init(&dev->pll_mutex, 1);
1368 sema_init(&dev->i2c_switch_mutex, 1);
1369 spin_lock_init(&dev->cmd_lock);
1370 for (i = 0; i < MAX_STREAM; i++)
1371 spin_lock_init(&dev->channel[i].state_lock);
1372 ngwritel(1, TIMESTAMPS);
1373
1374 ngwritel(1, NGENE_INT_ENABLE);
1375
1376 stat = ngene_load_firm(dev);
1377 if (stat < 0)
1378 goto fail;
1379
1380#ifdef CONFIG_PCI_MSI
1381 /* enable MSI if kernel and card support it */
1382 if (pci_msi_enabled() && dev->card_info->msi_supported) {
1383 unsigned long flags;
1384
1385 ngwritel(0, NGENE_INT_ENABLE);
1386 free_irq(dev->pci_dev->irq, dev);
1387 stat = pci_enable_msi(dev->pci_dev);
1388 if (stat) {
1389 printk(KERN_INFO DEVICE_NAME
1390 ": MSI not available\n");
1391 flags = IRQF_SHARED;
1392 } else {
1393 flags = 0;
1394 dev->msi_enabled = true;
1395 }
1396 stat = request_irq(dev->pci_dev->irq, irq_handler,
1397 flags, "nGene", dev);
1398 if (stat < 0)
1399 goto fail2;
1400 ngwritel(1, NGENE_INT_ENABLE);
1401 }
1402#endif
1403
1404 stat = ngene_i2c_init(dev, 0);
1405 if (stat < 0)
1406 goto fail;
1407
1408 stat = ngene_i2c_init(dev, 1);
1409 if (stat < 0)
1410 goto fail;
1411
1412 if (!stat)
1413 return stat;
1414
1415 /* otherwise error: fall through */
1416fail:
1417 ngwritel(0, NGENE_INT_ENABLE);
1418 free_irq(dev->pci_dev->irq, dev);
1419#ifdef CONFIG_PCI_MSI
1420fail2:
1421 if (dev->msi_enabled)
1422 pci_disable_msi(dev->pci_dev);
1423#endif
1424 return stat;
1425}
1426
1427/****************************************************************************/
1428/****************************************************************************/
1429/****************************************************************************/
1430
1431static void release_channel(struct ngene_channel *chan)
1432{
1433 struct dvb_demux *dvbdemux = &chan->demux;
1434 struct ngene *dev = chan->dev;
1435
1436 if (chan->running)
1437 set_transfer(chan, 0);
1438
1439 tasklet_kill(&chan->demux_tasklet);
1440
1441 if (chan->ci_dev) {
1442 dvb_unregister_device(chan->ci_dev);
1443 chan->ci_dev = NULL;
1444 }
1445
1446 if (chan->fe2)
1447 dvb_unregister_frontend(chan->fe2);
1448
1449 if (chan->fe) {
1450 dvb_unregister_frontend(chan->fe);
1451 dvb_frontend_detach(chan->fe);
1452 chan->fe = NULL;
1453 }
1454
1455 if (chan->has_demux) {
1456 dvb_net_release(&chan->dvbnet);
1457 dvbdemux->dmx.close(&dvbdemux->dmx);
1458 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1459 &chan->hw_frontend);
1460 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1461 &chan->mem_frontend);
1462 dvb_dmxdev_release(&chan->dmxdev);
1463 dvb_dmx_release(&chan->demux);
1464 chan->has_demux = false;
1465 }
1466
1467 if (chan->has_adapter) {
1468 dvb_unregister_adapter(&dev->adapter[chan->number]);
1469 chan->has_adapter = false;
1470 }
1471}
1472
1473static int init_channel(struct ngene_channel *chan)
1474{
1475 int ret = 0, nr = chan->number;
1476 struct dvb_adapter *adapter = NULL;
1477 struct dvb_demux *dvbdemux = &chan->demux;
1478 struct ngene *dev = chan->dev;
1479 struct ngene_info *ni = dev->card_info;
1480 int io = ni->io_type[nr];
1481
1482 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1483 chan->users = 0;
1484 chan->type = io;
1485 chan->mode = chan->type; /* for now only one mode */
1486
1487 if (io & NGENE_IO_TSIN) {
1488 chan->fe = NULL;
1489 if (ni->demod_attach[nr]) {
1490 ret = ni->demod_attach[nr](chan);
1491 if (ret < 0)
1492 goto err;
1493 }
1494 if (chan->fe && ni->tuner_attach[nr]) {
1495 ret = ni->tuner_attach[nr](chan);
1496 if (ret < 0)
1497 goto err;
1498 }
1499 }
1500
1501 if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1502 return 0;
1503
1504 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1505 if (nr >= STREAM_AUDIOIN1)
1506 chan->DataFormatFlags = DF_SWAP32;
1507
1508 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1509 adapter = &dev->adapter[nr];
1510 ret = dvb_register_adapter(adapter, "nGene",
1511 THIS_MODULE,
1512 &chan->dev->pci_dev->dev,
1513 adapter_nr);
1514 if (ret < 0)
1515 goto err;
1516 if (dev->first_adapter == NULL)
1517 dev->first_adapter = adapter;
1518 chan->has_adapter = true;
1519 } else
1520 adapter = dev->first_adapter;
1521 }
1522
1523 if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1524 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1525 set_transfer(chan, 1);
1526 chan->dev->channel[2].DataFormatFlags = DF_SWAP32;
1527 set_transfer(&chan->dev->channel[2], 1);
1528 dvb_register_device(adapter, &chan->ci_dev,
1529 &ngene_dvbdev_ci, (void *) chan,
1530 DVB_DEVICE_SEC);
1531 if (!chan->ci_dev)
1532 goto err;
1533 }
1534
1535 if (chan->fe) {
1536 if (dvb_register_frontend(adapter, chan->fe) < 0)
1537 goto err;
1538 chan->has_demux = true;
1539 }
1540 if (chan->fe2) {
1541 if (dvb_register_frontend(adapter, chan->fe2) < 0)
1542 goto err;
1543 chan->fe2->tuner_priv = chan->fe->tuner_priv;
1544 memcpy(&chan->fe2->ops.tuner_ops,
1545 &chan->fe->ops.tuner_ops,
1546 sizeof(struct dvb_tuner_ops));
1547 }
1548
1549 if (chan->has_demux) {
1550 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1551 ngene_start_feed,
1552 ngene_stop_feed, chan);
1553 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1554 &chan->hw_frontend,
1555 &chan->mem_frontend, adapter);
1556 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
1557 }
1558
1559 return ret;
1560
1561err:
1562 if (chan->fe) {
1563 dvb_frontend_detach(chan->fe);
1564 chan->fe = NULL;
1565 }
1566 release_channel(chan);
1567 return 0;
1568}
1569
1570static int init_channels(struct ngene *dev)
1571{
1572 int i, j;
1573
1574 for (i = 0; i < MAX_STREAM; i++) {
1575 dev->channel[i].number = i;
1576 if (init_channel(&dev->channel[i]) < 0) {
1577 for (j = i - 1; j >= 0; j--)
1578 release_channel(&dev->channel[j]);
1579 return -1;
1580 }
1581 }
1582 return 0;
1583}
1584
1585static struct cxd2099_cfg cxd_cfg = {
1586 .bitrate = 62000,
1587 .adr = 0x40,
1588 .polarity = 0,
1589 .clock_mode = 0,
1590};
1591
1592static void cxd_attach(struct ngene *dev)
1593{
1594 struct ngene_ci *ci = &dev->ci;
1595
1596 ci->en = cxd2099_attach(&cxd_cfg, dev, &dev->channel[0].i2c_adapter);
1597 ci->dev = dev;
1598 return;
1599}
1600
1601static void cxd_detach(struct ngene *dev)
1602{
1603 struct ngene_ci *ci = &dev->ci;
1604
1605 dvb_ca_en50221_release(ci->en);
1606 kfree(ci->en);
1607 ci->en = 0;
1608}
1609
1610/***********************************/
1611/* workaround for shutdown failure */
1612/***********************************/
1613
1614static void ngene_unlink(struct ngene *dev)
1615{
1616 struct ngene_command com;
1617
1618 com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1619 com.cmd.hdr.Length = 3;
1620 com.cmd.MemoryWrite.address = 0x910c;
1621 com.cmd.MemoryWrite.data = 0xff;
1622 com.in_len = 3;
1623 com.out_len = 1;
1624
1625 down(&dev->cmd_mutex);
1626 ngwritel(0, NGENE_INT_ENABLE);
1627 ngene_command_mutex(dev, &com);
1628 up(&dev->cmd_mutex);
1629}
1630
1631void ngene_shutdown(struct pci_dev *pdev)
1632{
1633 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1634
1635 if (!dev || !shutdown_workaround)
1636 return;
1637
1638 printk(KERN_INFO DEVICE_NAME ": shutdown workaround...\n");
1639 ngene_unlink(dev);
1640 pci_disable_device(pdev);
1641}
1642
1643/****************************************************************************/
1644/* device probe/remove calls ************************************************/
1645/****************************************************************************/
1646
1647void __devexit ngene_remove(struct pci_dev *pdev)
1648{
1649 struct ngene *dev = pci_get_drvdata(pdev);
1650 int i;
1651
1652 tasklet_kill(&dev->event_tasklet);
1653 for (i = MAX_STREAM - 1; i >= 0; i--)
1654 release_channel(&dev->channel[i]);
1655 if (dev->ci.en)
1656 cxd_detach(dev);
1657 ngene_stop(dev);
1658 ngene_release_buffers(dev);
1659 pci_set_drvdata(pdev, NULL);
1660 pci_disable_device(pdev);
1661}
1662
1663int __devinit ngene_probe(struct pci_dev *pci_dev,
1664 const struct pci_device_id *id)
1665{
1666 struct ngene *dev;
1667 int stat = 0;
1668
1669 if (pci_enable_device(pci_dev) < 0)
1670 return -ENODEV;
1671
1672 dev = vzalloc(sizeof(struct ngene));
1673 if (dev == NULL) {
1674 stat = -ENOMEM;
1675 goto fail0;
1676 }
1677
1678 dev->pci_dev = pci_dev;
1679 dev->card_info = (struct ngene_info *)id->driver_data;
1680 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1681
1682 pci_set_drvdata(pci_dev, dev);
1683
1684 /* Alloc buffers and start nGene */
1685 stat = ngene_get_buffers(dev);
1686 if (stat < 0)
1687 goto fail1;
1688 stat = ngene_start(dev);
1689 if (stat < 0)
1690 goto fail1;
1691
1692 cxd_attach(dev);
1693
1694 stat = ngene_buffer_config(dev);
1695 if (stat < 0)
1696 goto fail1;
1697
1698
1699 dev->i2c_current_bus = -1;
1700
1701 /* Register DVB adapters and devices for both channels */
1702 if (init_channels(dev) < 0)
1703 goto fail2;
1704
1705 return 0;
1706
1707fail2:
1708 ngene_stop(dev);
1709fail1:
1710 ngene_release_buffers(dev);
1711fail0:
1712 pci_disable_device(pci_dev);
1713 pci_set_drvdata(pci_dev, NULL);
1714 return stat;
1715}
diff --git a/drivers/media/dvb/ngene/ngene-dvb.c b/drivers/media/dvb/ngene/ngene-dvb.c
new file mode 100644
index 00000000000..fcb16a615aa
--- /dev/null
+++ b/drivers/media/dvb/ngene/ngene-dvb.c
@@ -0,0 +1,261 @@
1/*
2 * ngene-dvb.c: nGene PCIe bridge driver - DVB functions
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <linux/poll.h>
35#include <linux/io.h>
36#include <asm/div64.h>
37#include <linux/pci.h>
38#include <linux/timer.h>
39#include <linux/byteorder/generic.h>
40#include <linux/firmware.h>
41#include <linux/vmalloc.h>
42
43#include "ngene.h"
44
45
46/****************************************************************************/
47/* COMMAND API interface ****************************************************/
48/****************************************************************************/
49
50static ssize_t ts_write(struct file *file, const char *buf,
51 size_t count, loff_t *ppos)
52{
53 struct dvb_device *dvbdev = file->private_data;
54 struct ngene_channel *chan = dvbdev->priv;
55 struct ngene *dev = chan->dev;
56
57 if (wait_event_interruptible(dev->tsout_rbuf.queue,
58 dvb_ringbuffer_free
59 (&dev->tsout_rbuf) >= count) < 0)
60 return 0;
61
62 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count);
63
64 return count;
65}
66
67static ssize_t ts_read(struct file *file, char *buf,
68 size_t count, loff_t *ppos)
69{
70 struct dvb_device *dvbdev = file->private_data;
71 struct ngene_channel *chan = dvbdev->priv;
72 struct ngene *dev = chan->dev;
73 int left, avail;
74
75 left = count;
76 while (left) {
77 if (wait_event_interruptible(
78 dev->tsin_rbuf.queue,
79 dvb_ringbuffer_avail(&dev->tsin_rbuf) > 0) < 0)
80 return -EAGAIN;
81 avail = dvb_ringbuffer_avail(&dev->tsin_rbuf);
82 if (avail > left)
83 avail = left;
84 dvb_ringbuffer_read_user(&dev->tsin_rbuf, buf, avail);
85 left -= avail;
86 buf += avail;
87 }
88 return count;
89}
90
91static const struct file_operations ci_fops = {
92 .owner = THIS_MODULE,
93 .read = ts_read,
94 .write = ts_write,
95 .open = dvb_generic_open,
96 .release = dvb_generic_release,
97};
98
99struct dvb_device ngene_dvbdev_ci = {
100 .priv = 0,
101 .readers = -1,
102 .writers = -1,
103 .users = -1,
104 .fops = &ci_fops,
105};
106
107
108/****************************************************************************/
109/* DVB functions and API interface ******************************************/
110/****************************************************************************/
111
112static void swap_buffer(u32 *p, u32 len)
113{
114 while (len) {
115 *p = swab32(*p);
116 p++;
117 len -= 4;
118 }
119}
120
121/* start of filler packet */
122static u8 fill_ts[] = { 0x47, 0x1f, 0xff, 0x10, TS_FILLER };
123
124/* #define DEBUG_CI_XFER */
125#ifdef DEBUG_CI_XFER
126static u32 ok;
127static u32 overflow;
128static u32 stripped;
129#endif
130
131void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
132{
133 struct ngene_channel *chan = priv;
134 struct ngene *dev = chan->dev;
135
136
137 if (flags & DF_SWAP32)
138 swap_buffer(buf, len);
139
140 if (dev->ci.en && chan->number == 2) {
141 while (len >= 188) {
142 if (memcmp(buf, fill_ts, sizeof fill_ts) != 0) {
143 if (dvb_ringbuffer_free(&dev->tsin_rbuf) >= 188) {
144 dvb_ringbuffer_write(&dev->tsin_rbuf, buf, 188);
145 wake_up(&dev->tsin_rbuf.queue);
146#ifdef DEBUG_CI_XFER
147 ok++;
148#endif
149 }
150#ifdef DEBUG_CI_XFER
151 else
152 overflow++;
153#endif
154 }
155#ifdef DEBUG_CI_XFER
156 else
157 stripped++;
158
159 if (ok % 100 == 0 && overflow)
160 printk(KERN_WARNING "%s: ok %u overflow %u dropped %u\n", __func__, ok, overflow, stripped);
161#endif
162 buf += 188;
163 len -= 188;
164 }
165 return NULL;
166 }
167
168 if (chan->users > 0)
169 dvb_dmx_swfilter(&chan->demux, buf, len);
170
171 return NULL;
172}
173
174void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
175{
176 struct ngene_channel *chan = priv;
177 struct ngene *dev = chan->dev;
178 u32 alen;
179
180 alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
181 alen -= alen % 188;
182
183 if (alen < len)
184 FillTSBuffer(buf + alen, len - alen, flags);
185 else
186 alen = len;
187 dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
188 if (flags & DF_SWAP32)
189 swap_buffer((u32 *)buf, alen);
190 wake_up_interruptible(&dev->tsout_rbuf.queue);
191 return buf;
192}
193
194
195
196int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
197{
198 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
199 struct ngene_channel *chan = dvbdmx->priv;
200
201 if (chan->users == 0) {
202 if (!chan->dev->cmd_timeout_workaround || !chan->running)
203 set_transfer(chan, 1);
204 }
205
206 return ++chan->users;
207}
208
209int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
210{
211 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
212 struct ngene_channel *chan = dvbdmx->priv;
213
214 if (--chan->users)
215 return chan->users;
216
217 if (!chan->dev->cmd_timeout_workaround)
218 set_transfer(chan, 0);
219
220 return 0;
221}
222
223int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
224 int (*start_feed)(struct dvb_demux_feed *),
225 int (*stop_feed)(struct dvb_demux_feed *),
226 void *priv)
227{
228 dvbdemux->priv = priv;
229
230 dvbdemux->filternum = 256;
231 dvbdemux->feednum = 256;
232 dvbdemux->start_feed = start_feed;
233 dvbdemux->stop_feed = stop_feed;
234 dvbdemux->write_to_decoder = NULL;
235 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
236 DMX_SECTION_FILTERING |
237 DMX_MEMORY_BASED_FILTERING);
238 return dvb_dmx_init(dvbdemux);
239}
240
241int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
242 struct dvb_demux *dvbdemux,
243 struct dmx_frontend *hw_frontend,
244 struct dmx_frontend *mem_frontend,
245 struct dvb_adapter *dvb_adapter)
246{
247 int ret;
248
249 dmxdev->filternum = 256;
250 dmxdev->demux = &dvbdemux->dmx;
251 dmxdev->capabilities = 0;
252 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
253 if (ret < 0)
254 return ret;
255
256 hw_frontend->source = DMX_FRONTEND_0;
257 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
258 mem_frontend->source = DMX_MEMORY_FE;
259 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
260 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
261}
diff --git a/drivers/media/dvb/ngene/ngene-i2c.c b/drivers/media/dvb/ngene/ngene-i2c.c
new file mode 100644
index 00000000000..d28554f8ce9
--- /dev/null
+++ b/drivers/media/dvb/ngene/ngene-i2c.c
@@ -0,0 +1,176 @@
1/*
2 * ngene-i2c.c: nGene PCIe bridge driver i2c functions
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30/* FIXME - some of these can probably be removed */
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
35#include <linux/poll.h>
36#include <linux/io.h>
37#include <asm/div64.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/timer.h>
41#include <linux/byteorder/generic.h>
42#include <linux/firmware.h>
43#include <linux/vmalloc.h>
44
45#include "ngene.h"
46
47/* Firmware command for i2c operations */
48static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
49 u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
50{
51 struct ngene_command com;
52
53 com.cmd.hdr.Opcode = CMD_I2C_READ;
54 com.cmd.hdr.Length = outlen + 3;
55 com.cmd.I2CRead.Device = adr << 1;
56 memcpy(com.cmd.I2CRead.Data, out, outlen);
57 com.cmd.I2CRead.Data[outlen] = inlen;
58 com.cmd.I2CRead.Data[outlen + 1] = 0;
59 com.in_len = outlen + 3;
60 com.out_len = inlen + 1;
61
62 if (ngene_command(dev, &com) < 0)
63 return -EIO;
64
65 if ((com.cmd.raw8[0] >> 1) != adr)
66 return -EIO;
67
68 if (flag)
69 memcpy(in, com.cmd.raw8, inlen + 1);
70 else
71 memcpy(in, com.cmd.raw8 + 1, inlen);
72 return 0;
73}
74
75static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
76 u8 *out, u8 outlen)
77{
78 struct ngene_command com;
79
80
81 com.cmd.hdr.Opcode = CMD_I2C_WRITE;
82 com.cmd.hdr.Length = outlen + 1;
83 com.cmd.I2CRead.Device = adr << 1;
84 memcpy(com.cmd.I2CRead.Data, out, outlen);
85 com.in_len = outlen + 1;
86 com.out_len = 1;
87
88 if (ngene_command(dev, &com) < 0)
89 return -EIO;
90
91 if (com.cmd.raw8[0] == 1)
92 return -EIO;
93
94 return 0;
95}
96
97static void ngene_i2c_set_bus(struct ngene *dev, int bus)
98{
99 if (!(dev->card_info->i2c_access & 2))
100 return;
101 if (dev->i2c_current_bus == bus)
102 return;
103
104 switch (bus) {
105 case 0:
106 ngene_command_gpio_set(dev, 3, 0);
107 ngene_command_gpio_set(dev, 2, 1);
108 break;
109
110 case 1:
111 ngene_command_gpio_set(dev, 2, 0);
112 ngene_command_gpio_set(dev, 3, 1);
113 break;
114 }
115 dev->i2c_current_bus = bus;
116}
117
118static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
119 struct i2c_msg msg[], int num)
120{
121 struct ngene_channel *chan =
122 (struct ngene_channel *)i2c_get_adapdata(adapter);
123 struct ngene *dev = chan->dev;
124
125 down(&dev->i2c_switch_mutex);
126 ngene_i2c_set_bus(dev, chan->number);
127
128 if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
129 if (!ngene_command_i2c_read(dev, msg[0].addr,
130 msg[0].buf, msg[0].len,
131 msg[1].buf, msg[1].len, 0))
132 goto done;
133
134 if (num == 1 && !(msg[0].flags & I2C_M_RD))
135 if (!ngene_command_i2c_write(dev, msg[0].addr,
136 msg[0].buf, msg[0].len))
137 goto done;
138 if (num == 1 && (msg[0].flags & I2C_M_RD))
139 if (!ngene_command_i2c_read(dev, msg[0].addr, NULL, 0,
140 msg[0].buf, msg[0].len, 0))
141 goto done;
142
143 up(&dev->i2c_switch_mutex);
144 return -EIO;
145
146done:
147 up(&dev->i2c_switch_mutex);
148 return num;
149}
150
151
152static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
153{
154 return I2C_FUNC_SMBUS_EMUL;
155}
156
157static struct i2c_algorithm ngene_i2c_algo = {
158 .master_xfer = ngene_i2c_master_xfer,
159 .functionality = ngene_i2c_functionality,
160};
161
162int ngene_i2c_init(struct ngene *dev, int dev_nr)
163{
164 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
165
166 i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
167
168 strcpy(adap->name, "nGene");
169
170 adap->algo = &ngene_i2c_algo;
171 adap->algo_data = (void *)&(dev->channel[dev_nr]);
172 adap->dev.parent = &dev->pci_dev->dev;
173
174 return i2c_add_adapter(adap);
175}
176
diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h
new file mode 100644
index 00000000000..5443dc0caea
--- /dev/null
+++ b/drivers/media/dvb/ngene/ngene.h
@@ -0,0 +1,921 @@
1/*
2 * ngene.h: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef _NGENE_H_
25#define _NGENE_H_
26
27#include <linux/types.h>
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/i2c.h>
31#include <asm/dma.h>
32#include <linux/scatterlist.h>
33
34#include <linux/dvb/frontend.h>
35
36#include "dmxdev.h"
37#include "dvbdev.h"
38#include "dvb_demux.h"
39#include "dvb_ca_en50221.h"
40#include "dvb_frontend.h"
41#include "dvb_ringbuffer.h"
42#include "dvb_net.h"
43#include "cxd2099.h"
44
45#define DEVICE_NAME "ngene"
46
47#define NGENE_VID 0x18c3
48#define NGENE_PID 0x0720
49
50#ifndef VIDEO_CAP_VC1
51#define VIDEO_CAP_AVC 128
52#define VIDEO_CAP_H264 128
53#define VIDEO_CAP_VC1 256
54#define VIDEO_CAP_WMV9 256
55#define VIDEO_CAP_MPEG4 512
56#endif
57
58enum STREAM {
59 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
60 STREAM_VIDEOIN2,
61 STREAM_AUDIOIN1, /* I2S or SPI Input */
62 STREAM_AUDIOIN2,
63 STREAM_AUDIOOUT,
64 MAX_STREAM
65};
66
67enum SMODE_BITS {
68 SMODE_AUDIO_SPDIF = 0x20,
69 SMODE_AVSYNC = 0x10,
70 SMODE_TRANSPORT_STREAM = 0x08,
71 SMODE_AUDIO_CAPTURE = 0x04,
72 SMODE_VBI_CAPTURE = 0x02,
73 SMODE_VIDEO_CAPTURE = 0x01
74};
75
76enum STREAM_FLAG_BITS {
77 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
78 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
79 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
80 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
81 SFLAG_COLORBAR = 0x04, /* Select colorbar */
82};
83
84#define PROGRAM_ROM 0x0000
85#define PROGRAM_SRAM 0x1000
86#define PERIPHERALS0 0x8000
87#define PERIPHERALS1 0x9000
88#define SHARED_BUFFER 0xC000
89
90#define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
91#define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
92#define NGENE_COMMAND (SHARED_BUFFER+0x0200)
93#define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
94#define NGENE_STATUS (SHARED_BUFFER+0x0208)
95#define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
96#define NGENE_EVENT (SHARED_BUFFER+0x0210)
97#define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
98#define VARIABLES (SHARED_BUFFER+0x0210)
99
100#define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
101#define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
102#define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
103
104#define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
105#define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
106#define EEPROM_AREA (SHARED_BUFFER+0x0A00)
107
108#define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
109#define SG_VBI_1 (SHARED_BUFFER+0x0B00)
110#define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
111#define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
112#define SG_VBI_2 (SHARED_BUFFER+0x0C80)
113#define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
114#define SG_V_OUT (SHARED_BUFFER+0x0D80)
115#define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
116
117#define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
118#define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
119#define DATA_A_OUT (SHARED_BUFFER+0x0F80)
120#define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
121#define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
122#define DATA_V_OUT (SHARED_BUFFER+0x3000)
123
124#define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
125
126#define TIMESTAMPS 0xA000
127#define SCRATCHPAD 0xA080
128#define FORCE_INT 0xA088
129#define FORCE_NMI 0xA090
130#define INT_STATUS 0xA0A0
131
132#define DEV_VER 0x9004
133
134#define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
135
136struct SG_ADDR {
137 u64 start;
138 u64 curr;
139 u16 curr_ptr;
140 u16 elements;
141 u32 pad[3];
142} __attribute__ ((__packed__));
143
144struct SHARED_MEMORY {
145 /* C000 */
146 u32 HostToNgene[64];
147
148 /* C100 */
149 u32 NgeneToHost[64];
150
151 /* C200 */
152 u64 NgeneCommand;
153 u64 NgeneStatus;
154 u64 NgeneEvent;
155
156 /* C210 */
157 u8 pad1[0xc260 - 0xc218];
158
159 /* C260 */
160 u32 IntCounts;
161 u32 IntEnable;
162
163 /* C268 */
164 u8 pad2[0xd000 - 0xc268];
165
166} __attribute__ ((__packed__));
167
168struct BUFFER_STREAM_RESULTS {
169 u32 Clock; /* Stream time in 100ns units */
170 u16 RemainingLines; /* Remaining lines in this field.
171 0 for complete field */
172 u8 FieldCount; /* Video field number */
173 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
174 Bit 0 = FieldID */
175 u16 BlockCount; /* Audio block count (unused) */
176 u8 Reserved[2];
177 u32 DTOUpdate;
178} __attribute__ ((__packed__));
179
180struct HW_SCATTER_GATHER_ELEMENT {
181 u64 Address;
182 u32 Length;
183 u32 Reserved;
184} __attribute__ ((__packed__));
185
186struct BUFFER_HEADER {
187 u64 Next;
188 struct BUFFER_STREAM_RESULTS SR;
189
190 u32 Number_of_entries_1;
191 u32 Reserved5;
192 u64 Address_of_first_entry_1;
193
194 u32 Number_of_entries_2;
195 u32 Reserved7;
196 u64 Address_of_first_entry_2;
197} __attribute__ ((__packed__));
198
199struct EVENT_BUFFER {
200 u32 TimeStamp;
201 u8 GPIOStatus;
202 u8 UARTStatus;
203 u8 RXCharacter;
204 u8 EventStatus;
205 u32 Reserved[2];
206} __attribute__ ((__packed__));
207
208/* Firmware commands. */
209
210enum OPCODES {
211 CMD_NOP = 0,
212 CMD_FWLOAD_PREPARE = 0x01,
213 CMD_FWLOAD_FINISH = 0x02,
214 CMD_I2C_READ = 0x03,
215 CMD_I2C_WRITE = 0x04,
216
217 CMD_I2C_WRITE_NOSTOP = 0x05,
218 CMD_I2C_CONTINUE_WRITE = 0x06,
219 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
220
221 CMD_DEBUG_OUTPUT = 0x09,
222
223 CMD_CONTROL = 0x10,
224 CMD_CONFIGURE_BUFFER = 0x11,
225 CMD_CONFIGURE_FREE_BUFFER = 0x12,
226
227 CMD_SPI_READ = 0x13,
228 CMD_SPI_WRITE = 0x14,
229
230 CMD_MEM_READ = 0x20,
231 CMD_MEM_WRITE = 0x21,
232 CMD_SFR_READ = 0x22,
233 CMD_SFR_WRITE = 0x23,
234 CMD_IRAM_READ = 0x24,
235 CMD_IRAM_WRITE = 0x25,
236 CMD_SET_GPIO_PIN = 0x26,
237 CMD_SET_GPIO_INT = 0x27,
238 CMD_CONFIGURE_UART = 0x28,
239 CMD_WRITE_UART = 0x29,
240 MAX_CMD
241};
242
243enum RESPONSES {
244 OK = 0,
245 ERROR = 1
246};
247
248struct FW_HEADER {
249 u8 Opcode;
250 u8 Length;
251} __attribute__ ((__packed__));
252
253struct FW_I2C_WRITE {
254 struct FW_HEADER hdr;
255 u8 Device;
256 u8 Data[250];
257} __attribute__ ((__packed__));
258
259struct FW_I2C_CONTINUE_WRITE {
260 struct FW_HEADER hdr;
261 u8 Data[250];
262} __attribute__ ((__packed__));
263
264struct FW_I2C_READ {
265 struct FW_HEADER hdr;
266 u8 Device;
267 u8 Data[252]; /* followed by two bytes of read data count */
268} __attribute__ ((__packed__));
269
270struct FW_SPI_WRITE {
271 struct FW_HEADER hdr;
272 u8 ModeSelect;
273 u8 Data[250];
274} __attribute__ ((__packed__));
275
276struct FW_SPI_READ {
277 struct FW_HEADER hdr;
278 u8 ModeSelect;
279 u8 Data[252]; /* followed by two bytes of read data count */
280} __attribute__ ((__packed__));
281
282struct FW_FWLOAD_PREPARE {
283 struct FW_HEADER hdr;
284} __attribute__ ((__packed__));
285
286struct FW_FWLOAD_FINISH {
287 struct FW_HEADER hdr;
288 u16 Address; /* address of final block */
289 u16 Length;
290} __attribute__ ((__packed__));
291
292/*
293 * Meaning of FW_STREAM_CONTROL::Mode bits:
294 * Bit 7: Loopback PEXin to PEXout using TVOut channel
295 * Bit 6: AVLOOP
296 * Bit 5: Audio select; 0=I2S, 1=SPDIF
297 * Bit 4: AVSYNC
298 * Bit 3: Enable transport stream
299 * Bit 2: Enable audio capture
300 * Bit 1: Enable ITU-Video VBI capture
301 * Bit 0: Enable ITU-Video capture
302 *
303 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
304 * Bit 7: continuous capture
305 * Bit 6: capture one field
306 * Bit 5: capture one frame
307 * Bit 4: unused
308 * Bit 3: starting field; 0=odd, 1=even
309 * Bit 2: sample size; 0=8-bit, 1=10-bit
310 * Bit 1: data format; 0=UYVY, 1=YUY2
311 * Bit 0: resets buffer pointers
312*/
313
314enum FSC_MODE_BITS {
315 SMODE_LOOPBACK = 0x80,
316 SMODE_AVLOOP = 0x40,
317 _SMODE_AUDIO_SPDIF = 0x20,
318 _SMODE_AVSYNC = 0x10,
319 _SMODE_TRANSPORT_STREAM = 0x08,
320 _SMODE_AUDIO_CAPTURE = 0x04,
321 _SMODE_VBI_CAPTURE = 0x02,
322 _SMODE_VIDEO_CAPTURE = 0x01
323};
324
325
326/* Meaning of FW_STREAM_CONTROL::Stream bits:
327 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
328 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
329 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
330 */
331
332struct FW_STREAM_CONTROL {
333 struct FW_HEADER hdr;
334 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
335 u8 Control; /* Value written to UVI1_CTL */
336 u8 Mode; /* Controls clock source */
337 u8 SetupDataLen; /* Length of setup data, MSB=1 write
338 backwards */
339 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
340 for TS and Audio */
341 u64 Buffer_Address; /* Address of first buffer header */
342 u16 BytesPerVideoLine;
343 u16 MaxLinesPerField;
344 u16 MinLinesPerField;
345 u16 Reserved_1;
346 u16 BytesPerVBILine;
347 u16 MaxVBILinesPerField;
348 u16 MinVBILinesPerField;
349 u16 SetupDataAddr; /* ngene relative address of setup data */
350 u8 SetupData[32]; /* setup data */
351} __attribute__((__packed__));
352
353#define AUDIO_BLOCK_SIZE 256
354#define TS_BLOCK_SIZE 256
355
356struct FW_MEM_READ {
357 struct FW_HEADER hdr;
358 u16 address;
359} __attribute__ ((__packed__));
360
361struct FW_MEM_WRITE {
362 struct FW_HEADER hdr;
363 u16 address;
364 u8 data;
365} __attribute__ ((__packed__));
366
367struct FW_SFR_IRAM_READ {
368 struct FW_HEADER hdr;
369 u8 address;
370} __attribute__ ((__packed__));
371
372struct FW_SFR_IRAM_WRITE {
373 struct FW_HEADER hdr;
374 u8 address;
375 u8 data;
376} __attribute__ ((__packed__));
377
378struct FW_SET_GPIO_PIN {
379 struct FW_HEADER hdr;
380 u8 select;
381} __attribute__ ((__packed__));
382
383struct FW_SET_GPIO_INT {
384 struct FW_HEADER hdr;
385 u8 select;
386} __attribute__ ((__packed__));
387
388struct FW_SET_DEBUGMODE {
389 struct FW_HEADER hdr;
390 u8 debug_flags;
391} __attribute__ ((__packed__));
392
393struct FW_CONFIGURE_BUFFERS {
394 struct FW_HEADER hdr;
395 u8 config;
396} __attribute__ ((__packed__));
397
398enum _BUFFER_CONFIGS {
399 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
400 BUFFER_CONFIG_4422 = 0,
401 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
402 BUFFER_CONFIG_3333 = 1,
403 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
404 BUFFER_CONFIG_8022 = 2,
405 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
406};
407
408struct FW_CONFIGURE_FREE_BUFFERS {
409 struct FW_HEADER hdr;
410 u8 UVI1_BufferLength;
411 u8 UVI2_BufferLength;
412 u8 TVO_BufferLength;
413 u8 AUD1_BufferLength;
414 u8 AUD2_BufferLength;
415 u8 TVA_BufferLength;
416} __attribute__ ((__packed__));
417
418struct FW_CONFIGURE_UART {
419 struct FW_HEADER hdr;
420 u8 UartControl;
421} __attribute__ ((__packed__));
422
423enum _UART_CONFIG {
424 _UART_BAUDRATE_19200 = 0,
425 _UART_BAUDRATE_9600 = 1,
426 _UART_BAUDRATE_4800 = 2,
427 _UART_BAUDRATE_2400 = 3,
428 _UART_RX_ENABLE = 0x40,
429 _UART_TX_ENABLE = 0x80,
430};
431
432struct FW_WRITE_UART {
433 struct FW_HEADER hdr;
434 u8 Data[252];
435} __attribute__ ((__packed__));
436
437
438struct ngene_command {
439 u32 in_len;
440 u32 out_len;
441 union {
442 u32 raw[64];
443 u8 raw8[256];
444 struct FW_HEADER hdr;
445 struct FW_I2C_WRITE I2CWrite;
446 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
447 struct FW_I2C_READ I2CRead;
448 struct FW_STREAM_CONTROL StreamControl;
449 struct FW_FWLOAD_PREPARE FWLoadPrepare;
450 struct FW_FWLOAD_FINISH FWLoadFinish;
451 struct FW_MEM_READ MemoryRead;
452 struct FW_MEM_WRITE MemoryWrite;
453 struct FW_SFR_IRAM_READ SfrIramRead;
454 struct FW_SFR_IRAM_WRITE SfrIramWrite;
455 struct FW_SPI_WRITE SPIWrite;
456 struct FW_SPI_READ SPIRead;
457 struct FW_SET_GPIO_PIN SetGpioPin;
458 struct FW_SET_GPIO_INT SetGpioInt;
459 struct FW_SET_DEBUGMODE SetDebugMode;
460 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
461 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
462 struct FW_CONFIGURE_UART ConfigureUart;
463 struct FW_WRITE_UART WriteUart;
464 } cmd;
465} __attribute__ ((__packed__));
466
467#define NGENE_INTERFACE_VERSION 0x103
468#define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
469#define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
470#define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
471#define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
472#define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
473 Max: (1920x1080i60) */
474
475#define OVERFLOW_BUFFER_SIZE (8192)
476
477#define RING_SIZE_VIDEO 4
478#define RING_SIZE_AUDIO 8
479#define RING_SIZE_TS 8
480
481#define NUM_SCATTER_GATHER_ENTRIES 8
482
483#define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
484 RING_SIZE_VIDEO * 2) + \
485 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
486 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
487 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
488 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
489 (RING_SIZE_TS * PAGE_SIZE * 4) + \
490 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
491
492#define EVENT_QUEUE_SIZE 16
493
494/* Gathers the current state of a single channel. */
495
496struct SBufferHeader {
497 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
498 struct SBufferHeader *Next;
499 void *Buffer1;
500 struct HW_SCATTER_GATHER_ELEMENT *scList1;
501 void *Buffer2;
502 struct HW_SCATTER_GATHER_ELEMENT *scList2;
503};
504
505/* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
506#define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
507
508enum HWSTATE {
509 HWSTATE_STOP,
510 HWSTATE_STARTUP,
511 HWSTATE_RUN,
512 HWSTATE_PAUSE,
513};
514
515enum KSSTATE {
516 KSSTATE_STOP,
517 KSSTATE_ACQUIRE,
518 KSSTATE_PAUSE,
519 KSSTATE_RUN,
520};
521
522struct SRingBufferDescriptor {
523 struct SBufferHeader *Head; /* Points to first buffer in ring buffer
524 structure*/
525 u64 PAHead; /* Physical address of first buffer */
526 u32 MemSize; /* Memory size of allocated ring buffers
527 (needed for freeing) */
528 u32 NumBuffers; /* Number of buffers in the ring */
529 u32 Buffer1Length; /* Allocated length of Buffer 1 */
530 u32 Buffer2Length; /* Allocated length of Buffer 2 */
531 void *SCListMem; /* Memory to hold scatter gather lists for this
532 ring */
533 u64 PASCListMem; /* Physical address .. */
534 u32 SCListMemSize; /* Size of this memory */
535};
536
537enum STREAMMODEFLAGS {
538 StreamMode_NONE = 0, /* Stream not used */
539 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
540 StreamMode_TSIN = 2, /* Transport stream input (all) */
541 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
542 (only stream 0) */
543 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
544};
545
546
547enum BufferExchangeFlags {
548 BEF_EVEN_FIELD = 0x00000001,
549 BEF_CONTINUATION = 0x00000002,
550 BEF_MORE_DATA = 0x00000004,
551 BEF_OVERFLOW = 0x00000008,
552 DF_SWAP32 = 0x00010000,
553};
554
555typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
556
557struct MICI_STREAMINFO {
558 IBufferExchange *pExchange;
559 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
560 u8 Stream;
561 u8 Flags;
562 u8 Mode;
563 u8 Reserved;
564 u16 nLinesVideo;
565 u16 nBytesPerLineVideo;
566 u16 nLinesVBI;
567 u16 nBytesPerLineVBI;
568 u32 CaptureLength; /* Used for audio and transport stream */
569};
570
571/****************************************************************************/
572/* STRUCTS ******************************************************************/
573/****************************************************************************/
574
575/* sound hardware definition */
576#define MIXER_ADDR_TVTUNER 0
577#define MIXER_ADDR_LAST 0
578
579struct ngene_channel;
580
581/*struct sound chip*/
582
583struct mychip {
584 struct ngene_channel *chan;
585 struct snd_card *card;
586 struct pci_dev *pci;
587 struct snd_pcm_substream *substream;
588 struct snd_pcm *pcm;
589 unsigned long port;
590 int irq;
591 spinlock_t mixer_lock;
592 spinlock_t lock;
593 int mixer_volume[MIXER_ADDR_LAST + 1][2];
594 int capture_source[MIXER_ADDR_LAST + 1][2];
595};
596
597#ifdef NGENE_V4L
598struct ngene_overlay {
599 int tvnorm;
600 struct v4l2_rect w;
601 enum v4l2_field field;
602 struct v4l2_clip *clips;
603 int nclips;
604 int setup_ok;
605};
606
607struct ngene_tvnorm {
608 int v4l2_id;
609 char *name;
610 u16 swidth, sheight; /* scaled standard width, height */
611 int tuner_norm;
612 int soundstd;
613};
614
615struct ngene_vopen {
616 struct ngene_channel *ch;
617 enum v4l2_priority prio;
618 int width;
619 int height;
620 int depth;
621 struct videobuf_queue vbuf_q;
622 struct videobuf_queue vbi;
623 int fourcc;
624 int picxcount;
625 int resources;
626 enum v4l2_buf_type type;
627 const struct ngene_format *fmt;
628
629 const struct ngene_format *ovfmt;
630 struct ngene_overlay ov;
631};
632#endif
633
634struct ngene_channel {
635 struct device device;
636 struct i2c_adapter i2c_adapter;
637
638 struct ngene *dev;
639 int number;
640 int type;
641 int mode;
642 bool has_adapter;
643 bool has_demux;
644 int demod_type;
645 int (*gate_ctrl)(struct dvb_frontend *, int);
646
647 struct dvb_frontend *fe;
648 struct dvb_frontend *fe2;
649 struct dmxdev dmxdev;
650 struct dvb_demux demux;
651 struct dvb_net dvbnet;
652 struct dmx_frontend hw_frontend;
653 struct dmx_frontend mem_frontend;
654 int users;
655 struct video_device *v4l_dev;
656 struct dvb_device *ci_dev;
657 struct tasklet_struct demux_tasklet;
658
659 struct SBufferHeader *nextBuffer;
660 enum KSSTATE State;
661 enum HWSTATE HWState;
662 u8 Stream;
663 u8 Flags;
664 u8 Mode;
665 IBufferExchange *pBufferExchange;
666 IBufferExchange *pBufferExchange2;
667
668 spinlock_t state_lock;
669 u16 nLines;
670 u16 nBytesPerLine;
671 u16 nVBILines;
672 u16 nBytesPerVBILine;
673 u16 itumode;
674 u32 Capture1Length;
675 u32 Capture2Length;
676 struct SRingBufferDescriptor RingBuffer;
677 struct SRingBufferDescriptor TSRingBuffer;
678 struct SRingBufferDescriptor TSIdleBuffer;
679
680 u32 DataFormatFlags;
681
682 int AudioDTOUpdated;
683 u32 AudioDTOValue;
684
685 int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t);
686 u8 lnbh;
687
688 /* stuff from analog driver */
689
690 int minor;
691 struct mychip *mychip;
692 struct snd_card *soundcard;
693 u8 *evenbuffer;
694 u8 dma_on;
695 int soundstreamon;
696 int audiomute;
697 int soundbuffisallocated;
698 int sndbuffflag;
699 int tun_rdy;
700 int dec_rdy;
701 int tun_dec_rdy;
702 int lastbufferflag;
703
704 struct ngene_tvnorm *tvnorms;
705 int tvnorm_num;
706 int tvnorm;
707
708#ifdef NGENE_V4L
709 int videousers;
710 struct v4l2_prio_state prio;
711 struct ngene_vopen init;
712 int resources;
713 struct v4l2_framebuffer fbuf;
714 struct ngene_buffer *screen; /* overlay */
715 struct list_head capture; /* video capture queue */
716 spinlock_t s_lock;
717 struct semaphore reslock;
718#endif
719
720 int running;
721};
722
723
724struct ngene_ci {
725 struct device device;
726 struct i2c_adapter i2c_adapter;
727
728 struct ngene *dev;
729 struct dvb_ca_en50221 *en;
730};
731
732struct ngene;
733
734typedef void (rx_cb_t)(struct ngene *, u32, u8);
735typedef void (tx_cb_t)(struct ngene *, u32);
736
737struct ngene {
738 int nr;
739 struct pci_dev *pci_dev;
740 unsigned char *iomem;
741
742 /*struct i2c_adapter i2c_adapter;*/
743
744 u32 device_version;
745 u32 fw_interface_version;
746 u32 icounts;
747 bool msi_enabled;
748 bool cmd_timeout_workaround;
749
750 u8 *CmdDoneByte;
751 int BootFirmware;
752 void *OverflowBuffer;
753 dma_addr_t PAOverflowBuffer;
754 void *FWInterfaceBuffer;
755 dma_addr_t PAFWInterfaceBuffer;
756 u8 *ngenetohost;
757 u8 *hosttongene;
758
759 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
760 int EventQueueOverflowCount;
761 int EventQueueOverflowFlag;
762 struct tasklet_struct event_tasklet;
763 struct EVENT_BUFFER *EventBuffer;
764 int EventQueueWriteIndex;
765 int EventQueueReadIndex;
766
767 wait_queue_head_t cmd_wq;
768 int cmd_done;
769 struct semaphore cmd_mutex;
770 struct semaphore stream_mutex;
771 struct semaphore pll_mutex;
772 struct semaphore i2c_switch_mutex;
773 int i2c_current_channel;
774 int i2c_current_bus;
775 spinlock_t cmd_lock;
776
777 struct dvb_adapter adapter[MAX_STREAM];
778 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */
779 struct ngene_channel channel[MAX_STREAM];
780
781 struct ngene_info *card_info;
782
783 tx_cb_t *TxEventNotify;
784 rx_cb_t *RxEventNotify;
785 int tx_busy;
786 wait_queue_head_t tx_wq;
787 wait_queue_head_t rx_wq;
788#define UART_RBUF_LEN 4096
789 u8 uart_rbuf[UART_RBUF_LEN];
790 int uart_rp, uart_wp;
791
792#define TS_FILLER 0x6f
793
794 u8 *tsout_buf;
795#define TSOUT_BUF_SIZE (512*188*8)
796 struct dvb_ringbuffer tsout_rbuf;
797
798 u8 *tsin_buf;
799#define TSIN_BUF_SIZE (512*188*8)
800 struct dvb_ringbuffer tsin_rbuf;
801
802 u8 *ain_buf;
803#define AIN_BUF_SIZE (128*1024)
804 struct dvb_ringbuffer ain_rbuf;
805
806
807 u8 *vin_buf;
808#define VIN_BUF_SIZE (4*1920*1080)
809 struct dvb_ringbuffer vin_rbuf;
810
811 unsigned long exp_val;
812 int prev_cmd;
813
814 struct ngene_ci ci;
815};
816
817struct ngene_info {
818 int type;
819#define NGENE_APP 0
820#define NGENE_TERRATEC 1
821#define NGENE_SIDEWINDER 2
822#define NGENE_RACER 3
823#define NGENE_VIPER 4
824#define NGENE_PYTHON 5
825#define NGENE_VBOX_V1 6
826#define NGENE_VBOX_V2 7
827
828 int fw_version;
829 bool msi_supported;
830 char *name;
831
832 int io_type[MAX_STREAM];
833#define NGENE_IO_NONE 0
834#define NGENE_IO_TV 1
835#define NGENE_IO_HDTV 2
836#define NGENE_IO_TSIN 4
837#define NGENE_IO_TSOUT 8
838#define NGENE_IO_AIN 16
839
840 void *fe_config[4];
841 void *tuner_config[4];
842
843 int (*demod_attach[4])(struct ngene_channel *);
844 int (*tuner_attach[4])(struct ngene_channel *);
845
846 u8 avf[4];
847 u8 msp[4];
848 u8 demoda[4];
849 u8 lnb[4];
850 int i2c_access;
851 u8 ntsc;
852 u8 tsf[4];
853 u8 i2s[4];
854
855 int (*gate_ctrl)(struct dvb_frontend *, int);
856 int (*switch_ctrl)(struct ngene_channel *, int, int);
857};
858
859#ifdef NGENE_V4L
860struct ngene_format {
861 char *name;
862 int fourcc; /* video4linux 2 */
863 int btformat; /* BT848_COLOR_FMT_* */
864 int format;
865 int btswap; /* BT848_COLOR_CTL_* */
866 int depth; /* bit/pixel */
867 int flags;
868 int hshift, vshift; /* for planar modes */
869 int palette;
870};
871
872#define RESOURCE_OVERLAY 1
873#define RESOURCE_VIDEO 2
874#define RESOURCE_VBI 4
875
876struct ngene_buffer {
877 /* common v4l buffer stuff -- must be first */
878 struct videobuf_buffer vb;
879
880 /* ngene specific */
881 const struct ngene_format *fmt;
882 int tvnorm;
883 int btformat;
884 int btswap;
885};
886#endif
887
888
889/* Provided by ngene-core.c */
890int __devinit ngene_probe(struct pci_dev *pci_dev,
891 const struct pci_device_id *id);
892void __devexit ngene_remove(struct pci_dev *pdev);
893void ngene_shutdown(struct pci_dev *pdev);
894int ngene_command(struct ngene *dev, struct ngene_command *com);
895int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
896void set_transfer(struct ngene_channel *chan, int state);
897void FillTSBuffer(void *Buffer, int Length, u32 Flags);
898
899/* Provided by ngene-i2c.c */
900int ngene_i2c_init(struct ngene *dev, int dev_nr);
901
902/* Provided by ngene-dvb.c */
903extern struct dvb_device ngene_dvbdev_ci;
904void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
905void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
906int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
907int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
908int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
909 int (*start_feed)(struct dvb_demux_feed *),
910 int (*stop_feed)(struct dvb_demux_feed *),
911 void *priv);
912int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
913 struct dvb_demux *dvbdemux,
914 struct dmx_frontend *hw_frontend,
915 struct dmx_frontend *mem_frontend,
916 struct dvb_adapter *dvb_adapter);
917
918#endif
919
920/* LocalWords: Endif
921 */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-17 05:15:28 -0500