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Diffstat (limited to 'drivers/media/dvb/frontends/drxk_hard.c')
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.c6454
1 files changed, 6454 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c
new file mode 100644
index 00000000000..41b083820da
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxk_hard.c
@@ -0,0 +1,6454 @@
1/*
2 * drxk_hard: DRX-K DVB-C/T demodulator driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/firmware.h>
30#include <linux/i2c.h>
31#include <linux/version.h>
32#include <asm/div64.h>
33
34#include "dvb_frontend.h"
35#include "drxk.h"
36#include "drxk_hard.h"
37
38static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39static int PowerDownQAM(struct drxk_state *state);
40static int SetDVBTStandard(struct drxk_state *state,
41 enum OperationMode oMode);
42static int SetQAMStandard(struct drxk_state *state,
43 enum OperationMode oMode);
44static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
45 s32 tunerFreqOffset);
46static int SetDVBTStandard(struct drxk_state *state,
47 enum OperationMode oMode);
48static int DVBTStart(struct drxk_state *state);
49static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
50 s32 tunerFreqOffset);
51static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53static int SwitchAntennaToQAM(struct drxk_state *state);
54static int SwitchAntennaToDVBT(struct drxk_state *state);
55
56static bool IsDVBT(struct drxk_state *state)
57{
58 return state->m_OperationMode == OM_DVBT;
59}
60
61static bool IsQAM(struct drxk_state *state)
62{
63 return state->m_OperationMode == OM_QAM_ITU_A ||
64 state->m_OperationMode == OM_QAM_ITU_B ||
65 state->m_OperationMode == OM_QAM_ITU_C;
66}
67
68bool IsA1WithPatchCode(struct drxk_state *state)
69{
70 return state->m_DRXK_A1_PATCH_CODE;
71}
72
73bool IsA1WithRomCode(struct drxk_state *state)
74{
75 return state->m_DRXK_A1_ROM_CODE;
76}
77
78#define NOA1ROM 0
79
80#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
81#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
82
83#define DEFAULT_MER_83 165
84#define DEFAULT_MER_93 250
85
86#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
87#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
88#endif
89
90#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
91#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
92#endif
93
94#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
95#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
96#endif
97
98#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
99#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
100
101#ifndef DRXK_KI_RAGC_ATV
102#define DRXK_KI_RAGC_ATV 4
103#endif
104#ifndef DRXK_KI_IAGC_ATV
105#define DRXK_KI_IAGC_ATV 6
106#endif
107#ifndef DRXK_KI_DAGC_ATV
108#define DRXK_KI_DAGC_ATV 7
109#endif
110
111#ifndef DRXK_KI_RAGC_QAM
112#define DRXK_KI_RAGC_QAM 3
113#endif
114#ifndef DRXK_KI_IAGC_QAM
115#define DRXK_KI_IAGC_QAM 4
116#endif
117#ifndef DRXK_KI_DAGC_QAM
118#define DRXK_KI_DAGC_QAM 7
119#endif
120#ifndef DRXK_KI_RAGC_DVBT
121#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
122#endif
123#ifndef DRXK_KI_IAGC_DVBT
124#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
125#endif
126#ifndef DRXK_KI_DAGC_DVBT
127#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
128#endif
129
130#ifndef DRXK_AGC_DAC_OFFSET
131#define DRXK_AGC_DAC_OFFSET (0x800)
132#endif
133
134#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
135#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
136#endif
137
138#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
139#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
140#endif
141
142#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
143#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
144#endif
145
146#ifndef DRXK_QAM_SYMBOLRATE_MAX
147#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
148#endif
149
150#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
151#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
152#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
153#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
154#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
155#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
156#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
157#define DRXK_BL_ROM_OFFSET_UCODE 0
158
159#define DRXK_BLC_TIMEOUT 100
160
161#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
162#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
163
164#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
165
166#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
167#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
168#endif
169
170#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
171#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
172#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
173#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
174#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
175
176static unsigned int debug;
177module_param(debug, int, 0644);
178MODULE_PARM_DESC(debug, "enable debug messages");
179
180#define dprintk(level, fmt, arg...) do { \
181if (debug >= level) \
182 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
183} while (0)
184
185
186static inline u32 MulDiv32(u32 a, u32 b, u32 c)
187{
188 u64 tmp64;
189
190 tmp64 = (u64) a * (u64) b;
191 do_div(tmp64, c);
192
193 return (u32) tmp64;
194}
195
196inline u32 Frac28a(u32 a, u32 c)
197{
198 int i = 0;
199 u32 Q1 = 0;
200 u32 R0 = 0;
201
202 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
203 Q1 = a / c; /* integer part, only the 4 least significant bits
204 will be visible in the result */
205
206 /* division using radix 16, 7 nibbles in the result */
207 for (i = 0; i < 7; i++) {
208 Q1 = (Q1 << 4) | (R0 / c);
209 R0 = (R0 % c) << 4;
210 }
211 /* rounding */
212 if ((R0 >> 3) >= c)
213 Q1++;
214
215 return Q1;
216}
217
218static u32 Log10Times100(u32 x)
219{
220 static const u8 scale = 15;
221 static const u8 indexWidth = 5;
222 u8 i = 0;
223 u32 y = 0;
224 u32 d = 0;
225 u32 k = 0;
226 u32 r = 0;
227 /*
228 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
229 0 <= n < ((1<<INDEXWIDTH)+1)
230 */
231
232 static const u32 log2lut[] = {
233 0, /* 0.000000 */
234 290941, /* 290941.300628 */
235 573196, /* 573196.476418 */
236 847269, /* 847269.179851 */
237 1113620, /* 1113620.489452 */
238 1372674, /* 1372673.576986 */
239 1624818, /* 1624817.752104 */
240 1870412, /* 1870411.981536 */
241 2109788, /* 2109787.962654 */
242 2343253, /* 2343252.817465 */
243 2571091, /* 2571091.461923 */
244 2793569, /* 2793568.696416 */
245 3010931, /* 3010931.055901 */
246 3223408, /* 3223408.452106 */
247 3431216, /* 3431215.635215 */
248 3634553, /* 3634553.498355 */
249 3833610, /* 3833610.244726 */
250 4028562, /* 4028562.434393 */
251 4219576, /* 4219575.925308 */
252 4406807, /* 4406806.721144 */
253 4590402, /* 4590401.736809 */
254 4770499, /* 4770499.491025 */
255 4947231, /* 4947230.734179 */
256 5120719, /* 5120719.018555 */
257 5291081, /* 5291081.217197 */
258 5458428, /* 5458427.996830 */
259 5622864, /* 5622864.249668 */
260 5784489, /* 5784489.488298 */
261 5943398, /* 5943398.207380 */
262 6099680, /* 6099680.215452 */
263 6253421, /* 6253420.939751 */
264 6404702, /* 6404701.706649 */
265 6553600, /* 6553600.000000 */
266 };
267
268
269 if (x == 0)
270 return 0;
271
272 /* Scale x (normalize) */
273 /* computing y in log(x/y) = log(x) - log(y) */
274 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
275 for (k = scale; k > 0; k--) {
276 if (x & (((u32) 1) << scale))
277 break;
278 x <<= 1;
279 }
280 } else {
281 for (k = scale; k < 31; k++) {
282 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
283 break;
284 x >>= 1;
285 }
286 }
287 /*
288 Now x has binary point between bit[scale] and bit[scale-1]
289 and 1.0 <= x < 2.0 */
290
291 /* correction for divison: log(x) = log(x/y)+log(y) */
292 y = k * ((((u32) 1) << scale) * 200);
293
294 /* remove integer part */
295 x &= ((((u32) 1) << scale) - 1);
296 /* get index */
297 i = (u8) (x >> (scale - indexWidth));
298 /* compute delta (x - a) */
299 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
300 /* compute log, multiplication (d* (..)) must be within range ! */
301 y += log2lut[i] +
302 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
303 /* Conver to log10() */
304 y /= 108853; /* (log2(10) << scale) */
305 r = (y >> 1);
306 /* rounding */
307 if (y & ((u32) 1))
308 r++;
309 return r;
310}
311
312/****************************************************************************/
313/* I2C **********************************************************************/
314/****************************************************************************/
315
316static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
317{
318 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
319 .buf = val, .len = 1}
320 };
321
322 return i2c_transfer(adapter, msgs, 1);
323}
324
325static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
326{
327 int status;
328 struct i2c_msg msg = {
329 .addr = adr, .flags = 0, .buf = data, .len = len };
330
331 dprintk(3, ":");
332 if (debug > 2) {
333 int i;
334 for (i = 0; i < len; i++)
335 printk(KERN_CONT " %02x", data[i]);
336 printk(KERN_CONT "\n");
337 }
338 status = i2c_transfer(adap, &msg, 1);
339 if (status >= 0 && status != 1)
340 status = -EIO;
341
342 if (status < 0)
343 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
344
345 return status;
346}
347
348static int i2c_read(struct i2c_adapter *adap,
349 u8 adr, u8 *msg, int len, u8 *answ, int alen)
350{
351 int status;
352 struct i2c_msg msgs[2] = {
353 {.addr = adr, .flags = 0,
354 .buf = msg, .len = len},
355 {.addr = adr, .flags = I2C_M_RD,
356 .buf = answ, .len = alen}
357 };
358
359 status = i2c_transfer(adap, msgs, 2);
360 if (status != 2) {
361 if (debug > 2)
362 printk(KERN_CONT ": ERROR!\n");
363 if (status >= 0)
364 status = -EIO;
365
366 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
367 return status;
368 }
369 if (debug > 2) {
370 int i;
371 dprintk(2, ": read from ");
372 for (i = 0; i < len; i++)
373 printk(KERN_CONT " %02x", msg[i]);
374 printk(KERN_CONT "Value = ");
375 for (i = 0; i < alen; i++)
376 printk(KERN_CONT " %02x", answ[i]);
377 printk(KERN_CONT "\n");
378 }
379 return 0;
380}
381
382static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
383{
384 int status;
385 u8 adr = state->demod_address, mm1[4], mm2[2], len;
386
387 if (state->single_master)
388 flags |= 0xC0;
389
390 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
391 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
392 mm1[1] = ((reg >> 16) & 0xFF);
393 mm1[2] = ((reg >> 24) & 0xFF) | flags;
394 mm1[3] = ((reg >> 7) & 0xFF);
395 len = 4;
396 } else {
397 mm1[0] = ((reg << 1) & 0xFF);
398 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
399 len = 2;
400 }
401 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
402 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
403 if (status < 0)
404 return status;
405 if (data)
406 *data = mm2[0] | (mm2[1] << 8);
407
408 return 0;
409}
410
411static int read16(struct drxk_state *state, u32 reg, u16 *data)
412{
413 return read16_flags(state, reg, data, 0);
414}
415
416static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
417{
418 int status;
419 u8 adr = state->demod_address, mm1[4], mm2[4], len;
420
421 if (state->single_master)
422 flags |= 0xC0;
423
424 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
425 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
426 mm1[1] = ((reg >> 16) & 0xFF);
427 mm1[2] = ((reg >> 24) & 0xFF) | flags;
428 mm1[3] = ((reg >> 7) & 0xFF);
429 len = 4;
430 } else {
431 mm1[0] = ((reg << 1) & 0xFF);
432 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
433 len = 2;
434 }
435 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
436 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
437 if (status < 0)
438 return status;
439 if (data)
440 *data = mm2[0] | (mm2[1] << 8) |
441 (mm2[2] << 16) | (mm2[3] << 24);
442
443 return 0;
444}
445
446static int read32(struct drxk_state *state, u32 reg, u32 *data)
447{
448 return read32_flags(state, reg, data, 0);
449}
450
451static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
452{
453 u8 adr = state->demod_address, mm[6], len;
454
455 if (state->single_master)
456 flags |= 0xC0;
457 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
458 mm[0] = (((reg << 1) & 0xFF) | 0x01);
459 mm[1] = ((reg >> 16) & 0xFF);
460 mm[2] = ((reg >> 24) & 0xFF) | flags;
461 mm[3] = ((reg >> 7) & 0xFF);
462 len = 4;
463 } else {
464 mm[0] = ((reg << 1) & 0xFF);
465 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
466 len = 2;
467 }
468 mm[len] = data & 0xff;
469 mm[len + 1] = (data >> 8) & 0xff;
470
471 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
472 return i2c_write(state->i2c, adr, mm, len + 2);
473}
474
475static int write16(struct drxk_state *state, u32 reg, u16 data)
476{
477 return write16_flags(state, reg, data, 0);
478}
479
480static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
481{
482 u8 adr = state->demod_address, mm[8], len;
483
484 if (state->single_master)
485 flags |= 0xC0;
486 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
487 mm[0] = (((reg << 1) & 0xFF) | 0x01);
488 mm[1] = ((reg >> 16) & 0xFF);
489 mm[2] = ((reg >> 24) & 0xFF) | flags;
490 mm[3] = ((reg >> 7) & 0xFF);
491 len = 4;
492 } else {
493 mm[0] = ((reg << 1) & 0xFF);
494 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
495 len = 2;
496 }
497 mm[len] = data & 0xff;
498 mm[len + 1] = (data >> 8) & 0xff;
499 mm[len + 2] = (data >> 16) & 0xff;
500 mm[len + 3] = (data >> 24) & 0xff;
501 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
502
503 return i2c_write(state->i2c, adr, mm, len + 4);
504}
505
506static int write32(struct drxk_state *state, u32 reg, u32 data)
507{
508 return write32_flags(state, reg, data, 0);
509}
510
511static int write_block(struct drxk_state *state, u32 Address,
512 const int BlockSize, const u8 pBlock[])
513{
514 int status = 0, BlkSize = BlockSize;
515 u8 Flags = 0;
516
517 if (state->single_master)
518 Flags |= 0xC0;
519
520 while (BlkSize > 0) {
521 int Chunk = BlkSize > state->m_ChunkSize ?
522 state->m_ChunkSize : BlkSize;
523 u8 *AdrBuf = &state->Chunk[0];
524 u32 AdrLength = 0;
525
526 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
527 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
528 AdrBuf[1] = ((Address >> 16) & 0xFF);
529 AdrBuf[2] = ((Address >> 24) & 0xFF);
530 AdrBuf[3] = ((Address >> 7) & 0xFF);
531 AdrBuf[2] |= Flags;
532 AdrLength = 4;
533 if (Chunk == state->m_ChunkSize)
534 Chunk -= 2;
535 } else {
536 AdrBuf[0] = ((Address << 1) & 0xFF);
537 AdrBuf[1] = (((Address >> 16) & 0x0F) |
538 ((Address >> 18) & 0xF0));
539 AdrLength = 2;
540 }
541 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
542 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
543 if (debug > 1) {
544 int i;
545 if (pBlock)
546 for (i = 0; i < Chunk; i++)
547 printk(KERN_CONT " %02x", pBlock[i]);
548 printk(KERN_CONT "\n");
549 }
550 status = i2c_write(state->i2c, state->demod_address,
551 &state->Chunk[0], Chunk + AdrLength);
552 if (status < 0) {
553 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
554 __func__, Address);
555 break;
556 }
557 pBlock += Chunk;
558 Address += (Chunk >> 1);
559 BlkSize -= Chunk;
560 }
561 return status;
562}
563
564#ifndef DRXK_MAX_RETRIES_POWERUP
565#define DRXK_MAX_RETRIES_POWERUP 20
566#endif
567
568int PowerUpDevice(struct drxk_state *state)
569{
570 int status;
571 u8 data = 0;
572 u16 retryCount = 0;
573
574 dprintk(1, "\n");
575
576 status = i2c_read1(state->i2c, state->demod_address, &data);
577 if (status < 0) {
578 do {
579 data = 0;
580 status = i2c_write(state->i2c, state->demod_address,
581 &data, 1);
582 msleep(10);
583 retryCount++;
584 if (status < 0)
585 continue;
586 status = i2c_read1(state->i2c, state->demod_address,
587 &data);
588 } while (status < 0 &&
589 (retryCount < DRXK_MAX_RETRIES_POWERUP));
590 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
591 goto error;
592 }
593
594 /* Make sure all clk domains are active */
595 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
596 if (status < 0)
597 goto error;
598 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
599 if (status < 0)
600 goto error;
601 /* Enable pll lock tests */
602 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
603 if (status < 0)
604 goto error;
605
606 state->m_currentPowerMode = DRX_POWER_UP;
607
608error:
609 if (status < 0)
610 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
611
612 return status;
613}
614
615
616static int init_state(struct drxk_state *state)
617{
618 /*
619 * FIXME: most (all?) of the values bellow should be moved into
620 * struct drxk_config, as they are probably board-specific
621 */
622 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
623 u32 ulVSBIfAgcOutputLevel = 0;
624 u32 ulVSBIfAgcMinLevel = 0;
625 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
626 u32 ulVSBIfAgcSpeed = 3;
627
628 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
629 u32 ulVSBRfAgcOutputLevel = 0;
630 u32 ulVSBRfAgcMinLevel = 0;
631 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
632 u32 ulVSBRfAgcSpeed = 3;
633 u32 ulVSBRfAgcTop = 9500;
634 u32 ulVSBRfAgcCutOffCurrent = 4000;
635
636 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
637 u32 ulATVIfAgcOutputLevel = 0;
638 u32 ulATVIfAgcMinLevel = 0;
639 u32 ulATVIfAgcMaxLevel = 0;
640 u32 ulATVIfAgcSpeed = 3;
641
642 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
643 u32 ulATVRfAgcOutputLevel = 0;
644 u32 ulATVRfAgcMinLevel = 0;
645 u32 ulATVRfAgcMaxLevel = 0;
646 u32 ulATVRfAgcTop = 9500;
647 u32 ulATVRfAgcCutOffCurrent = 4000;
648 u32 ulATVRfAgcSpeed = 3;
649
650 u32 ulQual83 = DEFAULT_MER_83;
651 u32 ulQual93 = DEFAULT_MER_93;
652
653 u32 ulDVBTStaticTSClock = 1;
654 u32 ulDVBCStaticTSClock = 1;
655
656 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
657 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
658
659 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
660 /* io_pad_cfg_mode output mode is drive always */
661 /* io_pad_cfg_drive is set to power 2 (23 mA) */
662 u32 ulGPIOCfg = 0x0113;
663 u32 ulSerialMode = 1;
664 u32 ulInvertTSClock = 0;
665 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
666 u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
667 u32 ulDVBTBitrate = 50000000;
668 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
669
670 u32 ulInsertRSByte = 0;
671
672 u32 ulRfMirror = 1;
673 u32 ulPowerDown = 0;
674
675 dprintk(1, "\n");
676
677 state->m_hasLNA = false;
678 state->m_hasDVBT = false;
679 state->m_hasDVBC = false;
680 state->m_hasATV = false;
681 state->m_hasOOB = false;
682 state->m_hasAudio = false;
683
684 state->m_ChunkSize = 124;
685
686 state->m_oscClockFreq = 0;
687 state->m_smartAntInverted = false;
688 state->m_bPDownOpenBridge = false;
689
690 /* real system clock frequency in kHz */
691 state->m_sysClockFreq = 151875;
692 /* Timing div, 250ns/Psys */
693 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
694 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
695 HI_I2C_DELAY) / 1000;
696 /* Clipping */
697 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
698 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
699 state->m_HICfgWakeUpKey = (state->demod_address << 1);
700 /* port/bridge/power down ctrl */
701 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
702
703 state->m_bPowerDown = (ulPowerDown != 0);
704
705 state->m_DRXK_A1_PATCH_CODE = false;
706 state->m_DRXK_A1_ROM_CODE = false;
707 state->m_DRXK_A2_ROM_CODE = false;
708 state->m_DRXK_A3_ROM_CODE = false;
709 state->m_DRXK_A2_PATCH_CODE = false;
710 state->m_DRXK_A3_PATCH_CODE = false;
711
712 /* Init AGC and PGA parameters */
713 /* VSB IF */
714 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
715 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
716 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
717 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
718 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
719 state->m_vsbPgaCfg = 140;
720
721 /* VSB RF */
722 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
723 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
724 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
725 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
726 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
727 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
728 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
729 state->m_vsbPreSawCfg.reference = 0x07;
730 state->m_vsbPreSawCfg.usePreSaw = true;
731
732 state->m_Quality83percent = DEFAULT_MER_83;
733 state->m_Quality93percent = DEFAULT_MER_93;
734 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
735 state->m_Quality83percent = ulQual83;
736 state->m_Quality93percent = ulQual93;
737 }
738
739 /* ATV IF */
740 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
741 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
742 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
743 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
744 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
745
746 /* ATV RF */
747 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
748 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
749 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
750 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
751 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
752 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
753 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
754 state->m_atvPreSawCfg.reference = 0x04;
755 state->m_atvPreSawCfg.usePreSaw = true;
756
757
758 /* DVBT RF */
759 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
760 state->m_dvbtRfAgcCfg.outputLevel = 0;
761 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
762 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
763 state->m_dvbtRfAgcCfg.top = 0x2100;
764 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
765 state->m_dvbtRfAgcCfg.speed = 1;
766
767
768 /* DVBT IF */
769 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
770 state->m_dvbtIfAgcCfg.outputLevel = 0;
771 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
772 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
773 state->m_dvbtIfAgcCfg.top = 13424;
774 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
775 state->m_dvbtIfAgcCfg.speed = 3;
776 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
777 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
778 /* state->m_dvbtPgaCfg = 140; */
779
780 state->m_dvbtPreSawCfg.reference = 4;
781 state->m_dvbtPreSawCfg.usePreSaw = false;
782
783 /* QAM RF */
784 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
785 state->m_qamRfAgcCfg.outputLevel = 0;
786 state->m_qamRfAgcCfg.minOutputLevel = 6023;
787 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
788 state->m_qamRfAgcCfg.top = 0x2380;
789 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
790 state->m_qamRfAgcCfg.speed = 3;
791
792 /* QAM IF */
793 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
794 state->m_qamIfAgcCfg.outputLevel = 0;
795 state->m_qamIfAgcCfg.minOutputLevel = 0;
796 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
797 state->m_qamIfAgcCfg.top = 0x0511;
798 state->m_qamIfAgcCfg.cutOffCurrent = 0;
799 state->m_qamIfAgcCfg.speed = 3;
800 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
801 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
802
803 state->m_qamPgaCfg = 140;
804 state->m_qamPreSawCfg.reference = 4;
805 state->m_qamPreSawCfg.usePreSaw = false;
806
807 state->m_OperationMode = OM_NONE;
808 state->m_DrxkState = DRXK_UNINITIALIZED;
809
810 /* MPEG output configuration */
811 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
812 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
813 state->m_enableParallel = true; /* If TRUE;
814 parallel out otherwise serial */
815 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
816 state->m_invertERR = false; /* If TRUE; invert ERR signal */
817 state->m_invertSTR = false; /* If TRUE; invert STR signals */
818 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
819 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
820 state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
821 state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
822 /* If TRUE; static MPEG clockrate will be used;
823 otherwise clockrate will adapt to the bitrate of the TS */
824
825 state->m_DVBTBitrate = ulDVBTBitrate;
826 state->m_DVBCBitrate = ulDVBCBitrate;
827
828 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
829 state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
830
831 /* Maximum bitrate in b/s in case static clockrate is selected */
832 state->m_mpegTsStaticBitrate = 19392658;
833 state->m_disableTEIhandling = false;
834
835 if (ulInsertRSByte)
836 state->m_insertRSByte = true;
837
838 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
839 if (ulMpegLockTimeOut < 10000)
840 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
841 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
842 if (ulDemodLockTimeOut < 10000)
843 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
844
845 /* QAM defaults */
846 state->m_Constellation = DRX_CONSTELLATION_AUTO;
847 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
848 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
849 state->m_fecRsPrescale = 1;
850
851 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
852 state->m_agcFastClipCtrlDelay = 0;
853
854 state->m_GPIOCfg = (ulGPIOCfg);
855
856 state->m_bPowerDown = false;
857 state->m_currentPowerMode = DRX_POWER_DOWN;
858
859 state->m_enableParallel = (ulSerialMode == 0);
860
861 state->m_rfmirror = (ulRfMirror == 0);
862 state->m_IfAgcPol = false;
863 return 0;
864}
865
866static int DRXX_Open(struct drxk_state *state)
867{
868 int status = 0;
869 u32 jtag = 0;
870 u16 bid = 0;
871 u16 key = 0;
872
873 dprintk(1, "\n");
874 /* stop lock indicator process */
875 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
876 if (status < 0)
877 goto error;
878 /* Check device id */
879 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
880 if (status < 0)
881 goto error;
882 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
883 if (status < 0)
884 goto error;
885 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
886 if (status < 0)
887 goto error;
888 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
889 if (status < 0)
890 goto error;
891 status = write16(state, SIO_TOP_COMM_KEY__A, key);
892error:
893 if (status < 0)
894 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
895 return status;
896}
897
898static int GetDeviceCapabilities(struct drxk_state *state)
899{
900 u16 sioPdrOhwCfg = 0;
901 u32 sioTopJtagidLo = 0;
902 int status;
903 const char *spin = "";
904
905 dprintk(1, "\n");
906
907 /* driver 0.9.0 */
908 /* stop lock indicator process */
909 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
910 if (status < 0)
911 goto error;
912 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
913 if (status < 0)
914 goto error;
915 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
916 if (status < 0)
917 goto error;
918 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
919 if (status < 0)
920 goto error;
921
922 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
923 case 0:
924 /* ignore (bypass ?) */
925 break;
926 case 1:
927 /* 27 MHz */
928 state->m_oscClockFreq = 27000;
929 break;
930 case 2:
931 /* 20.25 MHz */
932 state->m_oscClockFreq = 20250;
933 break;
934 case 3:
935 /* 4 MHz */
936 state->m_oscClockFreq = 20250;
937 break;
938 default:
939 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
940 return -EINVAL;
941 }
942 /*
943 Determine device capabilities
944 Based on pinning v14
945 */
946 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
947 if (status < 0)
948 goto error;
949 /* driver 0.9.0 */
950 switch ((sioTopJtagidLo >> 29) & 0xF) {
951 case 0:
952 state->m_deviceSpin = DRXK_SPIN_A1;
953 spin = "A1";
954 break;
955 case 2:
956 state->m_deviceSpin = DRXK_SPIN_A2;
957 spin = "A2";
958 break;
959 case 3:
960 state->m_deviceSpin = DRXK_SPIN_A3;
961 spin = "A3";
962 break;
963 default:
964 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
965 status = -EINVAL;
966 printk(KERN_ERR "drxk: Spin unknown\n");
967 goto error2;
968 }
969 switch ((sioTopJtagidLo >> 12) & 0xFF) {
970 case 0x13:
971 /* typeId = DRX3913K_TYPE_ID */
972 state->m_hasLNA = false;
973 state->m_hasOOB = false;
974 state->m_hasATV = false;
975 state->m_hasAudio = false;
976 state->m_hasDVBT = true;
977 state->m_hasDVBC = true;
978 state->m_hasSAWSW = true;
979 state->m_hasGPIO2 = false;
980 state->m_hasGPIO1 = false;
981 state->m_hasIRQN = false;
982 break;
983 case 0x15:
984 /* typeId = DRX3915K_TYPE_ID */
985 state->m_hasLNA = false;
986 state->m_hasOOB = false;
987 state->m_hasATV = true;
988 state->m_hasAudio = false;
989 state->m_hasDVBT = true;
990 state->m_hasDVBC = false;
991 state->m_hasSAWSW = true;
992 state->m_hasGPIO2 = true;
993 state->m_hasGPIO1 = true;
994 state->m_hasIRQN = false;
995 break;
996 case 0x16:
997 /* typeId = DRX3916K_TYPE_ID */
998 state->m_hasLNA = false;
999 state->m_hasOOB = false;
1000 state->m_hasATV = true;
1001 state->m_hasAudio = false;
1002 state->m_hasDVBT = true;
1003 state->m_hasDVBC = false;
1004 state->m_hasSAWSW = true;
1005 state->m_hasGPIO2 = true;
1006 state->m_hasGPIO1 = true;
1007 state->m_hasIRQN = false;
1008 break;
1009 case 0x18:
1010 /* typeId = DRX3918K_TYPE_ID */
1011 state->m_hasLNA = false;
1012 state->m_hasOOB = false;
1013 state->m_hasATV = true;
1014 state->m_hasAudio = true;
1015 state->m_hasDVBT = true;
1016 state->m_hasDVBC = false;
1017 state->m_hasSAWSW = true;
1018 state->m_hasGPIO2 = true;
1019 state->m_hasGPIO1 = true;
1020 state->m_hasIRQN = false;
1021 break;
1022 case 0x21:
1023 /* typeId = DRX3921K_TYPE_ID */
1024 state->m_hasLNA = false;
1025 state->m_hasOOB = false;
1026 state->m_hasATV = true;
1027 state->m_hasAudio = true;
1028 state->m_hasDVBT = true;
1029 state->m_hasDVBC = true;
1030 state->m_hasSAWSW = true;
1031 state->m_hasGPIO2 = true;
1032 state->m_hasGPIO1 = true;
1033 state->m_hasIRQN = false;
1034 break;
1035 case 0x23:
1036 /* typeId = DRX3923K_TYPE_ID */
1037 state->m_hasLNA = false;
1038 state->m_hasOOB = false;
1039 state->m_hasATV = true;
1040 state->m_hasAudio = true;
1041 state->m_hasDVBT = true;
1042 state->m_hasDVBC = true;
1043 state->m_hasSAWSW = true;
1044 state->m_hasGPIO2 = true;
1045 state->m_hasGPIO1 = true;
1046 state->m_hasIRQN = false;
1047 break;
1048 case 0x25:
1049 /* typeId = DRX3925K_TYPE_ID */
1050 state->m_hasLNA = false;
1051 state->m_hasOOB = false;
1052 state->m_hasATV = true;
1053 state->m_hasAudio = true;
1054 state->m_hasDVBT = true;
1055 state->m_hasDVBC = true;
1056 state->m_hasSAWSW = true;
1057 state->m_hasGPIO2 = true;
1058 state->m_hasGPIO1 = true;
1059 state->m_hasIRQN = false;
1060 break;
1061 case 0x26:
1062 /* typeId = DRX3926K_TYPE_ID */
1063 state->m_hasLNA = false;
1064 state->m_hasOOB = false;
1065 state->m_hasATV = true;
1066 state->m_hasAudio = false;
1067 state->m_hasDVBT = true;
1068 state->m_hasDVBC = true;
1069 state->m_hasSAWSW = true;
1070 state->m_hasGPIO2 = true;
1071 state->m_hasGPIO1 = true;
1072 state->m_hasIRQN = false;
1073 break;
1074 default:
1075 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1076 ((sioTopJtagidLo >> 12) & 0xFF));
1077 status = -EINVAL;
1078 goto error2;
1079 }
1080
1081 printk(KERN_INFO
1082 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1083 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1084 state->m_oscClockFreq / 1000,
1085 state->m_oscClockFreq % 1000);
1086
1087error:
1088 if (status < 0)
1089 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1090
1091error2:
1092 return status;
1093}
1094
1095static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1096{
1097 int status;
1098 bool powerdown_cmd;
1099
1100 dprintk(1, "\n");
1101
1102 /* Write command */
1103 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1104 if (status < 0)
1105 goto error;
1106 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1107 msleep(1);
1108
1109 powerdown_cmd =
1110 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1111 ((state->m_HICfgCtrl) &
1112 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1113 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1114 if (powerdown_cmd == false) {
1115 /* Wait until command rdy */
1116 u32 retryCount = 0;
1117 u16 waitCmd;
1118
1119 do {
1120 msleep(1);
1121 retryCount += 1;
1122 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1123 &waitCmd);
1124 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1125 && (waitCmd != 0));
1126 if (status < 0)
1127 goto error;
1128 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1129 }
1130error:
1131 if (status < 0)
1132 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1133
1134 return status;
1135}
1136
1137static int HI_CfgCommand(struct drxk_state *state)
1138{
1139 int status;
1140
1141 dprintk(1, "\n");
1142
1143 mutex_lock(&state->mutex);
1144
1145 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1146 if (status < 0)
1147 goto error;
1148 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1149 if (status < 0)
1150 goto error;
1151 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1152 if (status < 0)
1153 goto error;
1154 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1155 if (status < 0)
1156 goto error;
1157 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1158 if (status < 0)
1159 goto error;
1160 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1161 if (status < 0)
1162 goto error;
1163 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1164 if (status < 0)
1165 goto error;
1166
1167 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1168error:
1169 mutex_unlock(&state->mutex);
1170 if (status < 0)
1171 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1172 return status;
1173}
1174
1175static int InitHI(struct drxk_state *state)
1176{
1177 dprintk(1, "\n");
1178
1179 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1180 state->m_HICfgTimeout = 0x96FF;
1181 /* port/bridge/power down ctrl */
1182 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1183
1184 return HI_CfgCommand(state);
1185}
1186
1187static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1188{
1189 int status = -1;
1190 u16 sioPdrMclkCfg = 0;
1191 u16 sioPdrMdxCfg = 0;
1192
1193 dprintk(1, "\n");
1194
1195 /* stop lock indicator process */
1196 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1197 if (status < 0)
1198 goto error;
1199
1200 /* MPEG TS pad configuration */
1201 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1202 if (status < 0)
1203 goto error;
1204
1205 if (mpegEnable == false) {
1206 /* Set MPEG TS pads to inputmode */
1207 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1208 if (status < 0)
1209 goto error;
1210 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1211 if (status < 0)
1212 goto error;
1213 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1214 if (status < 0)
1215 goto error;
1216 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1217 if (status < 0)
1218 goto error;
1219 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1220 if (status < 0)
1221 goto error;
1222 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1223 if (status < 0)
1224 goto error;
1225 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1226 if (status < 0)
1227 goto error;
1228 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1229 if (status < 0)
1230 goto error;
1231 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1232 if (status < 0)
1233 goto error;
1234 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1235 if (status < 0)
1236 goto error;
1237 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1238 if (status < 0)
1239 goto error;
1240 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1241 if (status < 0)
1242 goto error;
1243 } else {
1244 /* Enable MPEG output */
1245 sioPdrMdxCfg =
1246 ((state->m_TSDataStrength <<
1247 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1248 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1249 SIO_PDR_MCLK_CFG_DRIVE__B) |
1250 0x0003);
1251
1252 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1253 if (status < 0)
1254 goto error;
1255 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1256 if (status < 0)
1257 goto error;
1258 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1259 if (status < 0)
1260 goto error;
1261 if (state->m_enableParallel == true) {
1262 /* paralel -> enable MD1 to MD7 */
1263 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1264 if (status < 0)
1265 goto error;
1266 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1267 if (status < 0)
1268 goto error;
1269 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1270 if (status < 0)
1271 goto error;
1272 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1273 if (status < 0)
1274 goto error;
1275 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1276 if (status < 0)
1277 goto error;
1278 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1279 if (status < 0)
1280 goto error;
1281 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1282 if (status < 0)
1283 goto error;
1284 } else {
1285 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1286 SIO_PDR_MD0_CFG_DRIVE__B)
1287 | 0x0003);
1288 /* serial -> disable MD1 to MD7 */
1289 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1290 if (status < 0)
1291 goto error;
1292 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1293 if (status < 0)
1294 goto error;
1295 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1296 if (status < 0)
1297 goto error;
1298 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1299 if (status < 0)
1300 goto error;
1301 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1302 if (status < 0)
1303 goto error;
1304 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1305 if (status < 0)
1306 goto error;
1307 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1308 if (status < 0)
1309 goto error;
1310 }
1311 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1312 if (status < 0)
1313 goto error;
1314 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1315 if (status < 0)
1316 goto error;
1317 }
1318 /* Enable MB output over MPEG pads and ctl input */
1319 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1320 if (status < 0)
1321 goto error;
1322 /* Write nomagic word to enable pdr reg write */
1323 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1324error:
1325 if (status < 0)
1326 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1327 return status;
1328}
1329
1330static int MPEGTSDisable(struct drxk_state *state)
1331{
1332 dprintk(1, "\n");
1333
1334 return MPEGTSConfigurePins(state, false);
1335}
1336
1337static int BLChainCmd(struct drxk_state *state,
1338 u16 romOffset, u16 nrOfElements, u32 timeOut)
1339{
1340 u16 blStatus = 0;
1341 int status;
1342 unsigned long end;
1343
1344 dprintk(1, "\n");
1345 mutex_lock(&state->mutex);
1346 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1347 if (status < 0)
1348 goto error;
1349 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1350 if (status < 0)
1351 goto error;
1352 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1353 if (status < 0)
1354 goto error;
1355 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1356 if (status < 0)
1357 goto error;
1358
1359 end = jiffies + msecs_to_jiffies(timeOut);
1360 do {
1361 msleep(1);
1362 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1363 if (status < 0)
1364 goto error;
1365 } while ((blStatus == 0x1) &&
1366 ((time_is_after_jiffies(end))));
1367
1368 if (blStatus == 0x1) {
1369 printk(KERN_ERR "drxk: SIO not ready\n");
1370 status = -EINVAL;
1371 goto error2;
1372 }
1373error:
1374 if (status < 0)
1375 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1376error2:
1377 mutex_unlock(&state->mutex);
1378 return status;
1379}
1380
1381
1382static int DownloadMicrocode(struct drxk_state *state,
1383 const u8 pMCImage[], u32 Length)
1384{
1385 const u8 *pSrc = pMCImage;
1386 u16 Flags;
1387 u16 Drain;
1388 u32 Address;
1389 u16 nBlocks;
1390 u16 BlockSize;
1391 u16 BlockCRC;
1392 u32 offset = 0;
1393 u32 i;
1394 int status = 0;
1395
1396 dprintk(1, "\n");
1397
1398 /* down the drain (we don care about MAGIC_WORD) */
1399 Drain = (pSrc[0] << 8) | pSrc[1];
1400 pSrc += sizeof(u16);
1401 offset += sizeof(u16);
1402 nBlocks = (pSrc[0] << 8) | pSrc[1];
1403 pSrc += sizeof(u16);
1404 offset += sizeof(u16);
1405
1406 for (i = 0; i < nBlocks; i += 1) {
1407 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1408 (pSrc[2] << 8) | pSrc[3];
1409 pSrc += sizeof(u32);
1410 offset += sizeof(u32);
1411
1412 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1413 pSrc += sizeof(u16);
1414 offset += sizeof(u16);
1415
1416 Flags = (pSrc[0] << 8) | pSrc[1];
1417 pSrc += sizeof(u16);
1418 offset += sizeof(u16);
1419
1420 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1421 pSrc += sizeof(u16);
1422 offset += sizeof(u16);
1423
1424 if (offset + BlockSize > Length) {
1425 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1426 return -EINVAL;
1427 }
1428
1429 status = write_block(state, Address, BlockSize, pSrc);
1430 if (status < 0) {
1431 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1432 break;
1433 }
1434 pSrc += BlockSize;
1435 offset += BlockSize;
1436 }
1437 return status;
1438}
1439
1440static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1441{
1442 int status;
1443 u16 data = 0;
1444 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1445 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1446 unsigned long end;
1447
1448 dprintk(1, "\n");
1449
1450 if (enable == false) {
1451 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1452 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1453 }
1454
1455 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1456 if (status >= 0 && data == desiredStatus) {
1457 /* tokenring already has correct status */
1458 return status;
1459 }
1460 /* Disable/enable dvbt tokenring bridge */
1461 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1462
1463 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1464 do {
1465 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1466 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1467 break;
1468 msleep(1);
1469 } while (1);
1470 if (data != desiredStatus) {
1471 printk(KERN_ERR "drxk: SIO not ready\n");
1472 return -EINVAL;
1473 }
1474 return status;
1475}
1476
1477static int MPEGTSStop(struct drxk_state *state)
1478{
1479 int status = 0;
1480 u16 fecOcSncMode = 0;
1481 u16 fecOcIprMode = 0;
1482
1483 dprintk(1, "\n");
1484
1485 /* Gracefull shutdown (byte boundaries) */
1486 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1487 if (status < 0)
1488 goto error;
1489 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1490 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1491 if (status < 0)
1492 goto error;
1493
1494 /* Suppress MCLK during absence of data */
1495 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1496 if (status < 0)
1497 goto error;
1498 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1499 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1500
1501error:
1502 if (status < 0)
1503 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1504
1505 return status;
1506}
1507
1508static int scu_command(struct drxk_state *state,
1509 u16 cmd, u8 parameterLen,
1510 u16 *parameter, u8 resultLen, u16 *result)
1511{
1512#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1513#error DRXK register mapping no longer compatible with this routine!
1514#endif
1515 u16 curCmd = 0;
1516 int status = -EINVAL;
1517 unsigned long end;
1518 u8 buffer[34];
1519 int cnt = 0, ii;
1520 const char *p;
1521 char errname[30];
1522
1523 dprintk(1, "\n");
1524
1525 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1526 ((resultLen > 0) && (result == NULL)))
1527 goto error;
1528
1529 mutex_lock(&state->mutex);
1530
1531 /* assume that the command register is ready
1532 since it is checked afterwards */
1533 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1534 buffer[cnt++] = (parameter[ii] & 0xFF);
1535 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1536 }
1537 buffer[cnt++] = (cmd & 0xFF);
1538 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1539
1540 write_block(state, SCU_RAM_PARAM_0__A -
1541 (parameterLen - 1), cnt, buffer);
1542 /* Wait until SCU has processed command */
1543 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1544 do {
1545 msleep(1);
1546 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1547 if (status < 0)
1548 goto error;
1549 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1550 if (curCmd != DRX_SCU_READY) {
1551 printk(KERN_ERR "drxk: SCU not ready\n");
1552 status = -EIO;
1553 goto error2;
1554 }
1555 /* read results */
1556 if ((resultLen > 0) && (result != NULL)) {
1557 s16 err;
1558 int ii;
1559
1560 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1561 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1562 if (status < 0)
1563 goto error;
1564 }
1565
1566 /* Check if an error was reported by SCU */
1567 err = (s16)result[0];
1568 if (err >= 0)
1569 goto error;
1570
1571 /* check for the known error codes */
1572 switch (err) {
1573 case SCU_RESULT_UNKCMD:
1574 p = "SCU_RESULT_UNKCMD";
1575 break;
1576 case SCU_RESULT_UNKSTD:
1577 p = "SCU_RESULT_UNKSTD";
1578 break;
1579 case SCU_RESULT_SIZE:
1580 p = "SCU_RESULT_SIZE";
1581 break;
1582 case SCU_RESULT_INVPAR:
1583 p = "SCU_RESULT_INVPAR";
1584 break;
1585 default: /* Other negative values are errors */
1586 sprintf(errname, "ERROR: %d\n", err);
1587 p = errname;
1588 }
1589 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1590 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1591 status = -EINVAL;
1592 goto error2;
1593 }
1594
1595error:
1596 if (status < 0)
1597 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1598error2:
1599 mutex_unlock(&state->mutex);
1600 return status;
1601}
1602
1603static int SetIqmAf(struct drxk_state *state, bool active)
1604{
1605 u16 data = 0;
1606 int status;
1607
1608 dprintk(1, "\n");
1609
1610 /* Configure IQM */
1611 status = read16(state, IQM_AF_STDBY__A, &data);
1612 if (status < 0)
1613 goto error;
1614
1615 if (!active) {
1616 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1617 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1618 | IQM_AF_STDBY_STDBY_PD_STANDBY
1619 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1620 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1621 } else {
1622 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1623 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1624 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1625 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1626 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1627 );
1628 }
1629 status = write16(state, IQM_AF_STDBY__A, data);
1630
1631error:
1632 if (status < 0)
1633 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1634 return status;
1635}
1636
1637static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1638{
1639 int status = 0;
1640 u16 sioCcPwdMode = 0;
1641
1642 dprintk(1, "\n");
1643
1644 /* Check arguments */
1645 if (mode == NULL)
1646 return -EINVAL;
1647
1648 switch (*mode) {
1649 case DRX_POWER_UP:
1650 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1651 break;
1652 case DRXK_POWER_DOWN_OFDM:
1653 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1654 break;
1655 case DRXK_POWER_DOWN_CORE:
1656 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1657 break;
1658 case DRXK_POWER_DOWN_PLL:
1659 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1660 break;
1661 case DRX_POWER_DOWN:
1662 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1663 break;
1664 default:
1665 /* Unknow sleep mode */
1666 return -EINVAL;
1667 }
1668
1669 /* If already in requested power mode, do nothing */
1670 if (state->m_currentPowerMode == *mode)
1671 return 0;
1672
1673 /* For next steps make sure to start from DRX_POWER_UP mode */
1674 if (state->m_currentPowerMode != DRX_POWER_UP) {
1675 status = PowerUpDevice(state);
1676 if (status < 0)
1677 goto error;
1678 status = DVBTEnableOFDMTokenRing(state, true);
1679 if (status < 0)
1680 goto error;
1681 }
1682
1683 if (*mode == DRX_POWER_UP) {
1684 /* Restore analog & pin configuartion */
1685 } else {
1686 /* Power down to requested mode */
1687 /* Backup some register settings */
1688 /* Set pins with possible pull-ups connected
1689 to them in input mode */
1690 /* Analog power down */
1691 /* ADC power down */
1692 /* Power down device */
1693 /* stop all comm_exec */
1694 /* Stop and power down previous standard */
1695 switch (state->m_OperationMode) {
1696 case OM_DVBT:
1697 status = MPEGTSStop(state);
1698 if (status < 0)
1699 goto error;
1700 status = PowerDownDVBT(state, false);
1701 if (status < 0)
1702 goto error;
1703 break;
1704 case OM_QAM_ITU_A:
1705 case OM_QAM_ITU_C:
1706 status = MPEGTSStop(state);
1707 if (status < 0)
1708 goto error;
1709 status = PowerDownQAM(state);
1710 if (status < 0)
1711 goto error;
1712 break;
1713 default:
1714 break;
1715 }
1716 status = DVBTEnableOFDMTokenRing(state, false);
1717 if (status < 0)
1718 goto error;
1719 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1720 if (status < 0)
1721 goto error;
1722 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1723 if (status < 0)
1724 goto error;
1725
1726 if (*mode != DRXK_POWER_DOWN_OFDM) {
1727 state->m_HICfgCtrl |=
1728 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1729 status = HI_CfgCommand(state);
1730 if (status < 0)
1731 goto error;
1732 }
1733 }
1734 state->m_currentPowerMode = *mode;
1735
1736error:
1737 if (status < 0)
1738 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1739
1740 return status;
1741}
1742
1743static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1744{
1745 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1746 u16 cmdResult = 0;
1747 u16 data = 0;
1748 int status;
1749
1750 dprintk(1, "\n");
1751
1752 status = read16(state, SCU_COMM_EXEC__A, &data);
1753 if (status < 0)
1754 goto error;
1755 if (data == SCU_COMM_EXEC_ACTIVE) {
1756 /* Send OFDM stop command */
1757 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1758 if (status < 0)
1759 goto error;
1760 /* Send OFDM reset command */
1761 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1762 if (status < 0)
1763 goto error;
1764 }
1765
1766 /* Reset datapath for OFDM, processors first */
1767 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1768 if (status < 0)
1769 goto error;
1770 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1771 if (status < 0)
1772 goto error;
1773 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1774 if (status < 0)
1775 goto error;
1776
1777 /* powerdown AFE */
1778 status = SetIqmAf(state, false);
1779 if (status < 0)
1780 goto error;
1781
1782 /* powerdown to OFDM mode */
1783 if (setPowerMode) {
1784 status = CtrlPowerMode(state, &powerMode);
1785 if (status < 0)
1786 goto error;
1787 }
1788error:
1789 if (status < 0)
1790 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1791 return status;
1792}
1793
1794static int SetOperationMode(struct drxk_state *state,
1795 enum OperationMode oMode)
1796{
1797 int status = 0;
1798
1799 dprintk(1, "\n");
1800 /*
1801 Stop and power down previous standard
1802 TODO investigate total power down instead of partial
1803 power down depending on "previous" standard.
1804 */
1805
1806 /* disable HW lock indicator */
1807 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1808 if (status < 0)
1809 goto error;
1810
1811 /* Device is already at the required mode */
1812 if (state->m_OperationMode == oMode)
1813 return 0;
1814
1815 switch (state->m_OperationMode) {
1816 /* OM_NONE was added for start up */
1817 case OM_NONE:
1818 break;
1819 case OM_DVBT:
1820 status = MPEGTSStop(state);
1821 if (status < 0)
1822 goto error;
1823 status = PowerDownDVBT(state, true);
1824 if (status < 0)
1825 goto error;
1826 state->m_OperationMode = OM_NONE;
1827 break;
1828 case OM_QAM_ITU_A: /* fallthrough */
1829 case OM_QAM_ITU_C:
1830 status = MPEGTSStop(state);
1831 if (status < 0)
1832 goto error;
1833 status = PowerDownQAM(state);
1834 if (status < 0)
1835 goto error;
1836 state->m_OperationMode = OM_NONE;
1837 break;
1838 case OM_QAM_ITU_B:
1839 default:
1840 status = -EINVAL;
1841 goto error;
1842 }
1843
1844 /*
1845 Power up new standard
1846 */
1847 switch (oMode) {
1848 case OM_DVBT:
1849 state->m_OperationMode = oMode;
1850 status = SetDVBTStandard(state, oMode);
1851 if (status < 0)
1852 goto error;
1853 break;
1854 case OM_QAM_ITU_A: /* fallthrough */
1855 case OM_QAM_ITU_C:
1856 state->m_OperationMode = oMode;
1857 status = SetQAMStandard(state, oMode);
1858 if (status < 0)
1859 goto error;
1860 break;
1861 case OM_QAM_ITU_B:
1862 default:
1863 status = -EINVAL;
1864 }
1865error:
1866 if (status < 0)
1867 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1868 return status;
1869}
1870
1871static int Start(struct drxk_state *state, s32 offsetFreq,
1872 s32 IntermediateFrequency)
1873{
1874 int status = -EINVAL;
1875
1876 u16 IFreqkHz;
1877 s32 OffsetkHz = offsetFreq / 1000;
1878
1879 dprintk(1, "\n");
1880 if (state->m_DrxkState != DRXK_STOPPED &&
1881 state->m_DrxkState != DRXK_DTV_STARTED)
1882 goto error;
1883
1884 state->m_bMirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1885
1886 if (IntermediateFrequency < 0) {
1887 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1888 IntermediateFrequency = -IntermediateFrequency;
1889 }
1890
1891 switch (state->m_OperationMode) {
1892 case OM_QAM_ITU_A:
1893 case OM_QAM_ITU_C:
1894 IFreqkHz = (IntermediateFrequency / 1000);
1895 status = SetQAM(state, IFreqkHz, OffsetkHz);
1896 if (status < 0)
1897 goto error;
1898 state->m_DrxkState = DRXK_DTV_STARTED;
1899 break;
1900 case OM_DVBT:
1901 IFreqkHz = (IntermediateFrequency / 1000);
1902 status = MPEGTSStop(state);
1903 if (status < 0)
1904 goto error;
1905 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1906 if (status < 0)
1907 goto error;
1908 status = DVBTStart(state);
1909 if (status < 0)
1910 goto error;
1911 state->m_DrxkState = DRXK_DTV_STARTED;
1912 break;
1913 default:
1914 break;
1915 }
1916error:
1917 if (status < 0)
1918 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1919 return status;
1920}
1921
1922static int ShutDown(struct drxk_state *state)
1923{
1924 dprintk(1, "\n");
1925
1926 MPEGTSStop(state);
1927 return 0;
1928}
1929
1930static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1931 u32 Time)
1932{
1933 int status = -EINVAL;
1934
1935 dprintk(1, "\n");
1936
1937 if (pLockStatus == NULL)
1938 goto error;
1939
1940 *pLockStatus = NOT_LOCKED;
1941
1942 /* define the SCU command code */
1943 switch (state->m_OperationMode) {
1944 case OM_QAM_ITU_A:
1945 case OM_QAM_ITU_B:
1946 case OM_QAM_ITU_C:
1947 status = GetQAMLockStatus(state, pLockStatus);
1948 break;
1949 case OM_DVBT:
1950 status = GetDVBTLockStatus(state, pLockStatus);
1951 break;
1952 default:
1953 break;
1954 }
1955error:
1956 if (status < 0)
1957 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1958 return status;
1959}
1960
1961static int MPEGTSStart(struct drxk_state *state)
1962{
1963 int status;
1964
1965 u16 fecOcSncMode = 0;
1966
1967 /* Allow OC to sync again */
1968 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1969 if (status < 0)
1970 goto error;
1971 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1972 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1973 if (status < 0)
1974 goto error;
1975 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1976error:
1977 if (status < 0)
1978 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1979 return status;
1980}
1981
1982static int MPEGTSDtoInit(struct drxk_state *state)
1983{
1984 int status;
1985
1986 dprintk(1, "\n");
1987
1988 /* Rate integration settings */
1989 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1990 if (status < 0)
1991 goto error;
1992 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1993 if (status < 0)
1994 goto error;
1995 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1996 if (status < 0)
1997 goto error;
1998 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1999 if (status < 0)
2000 goto error;
2001 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2002 if (status < 0)
2003 goto error;
2004 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2005 if (status < 0)
2006 goto error;
2007 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2008 if (status < 0)
2009 goto error;
2010 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2011 if (status < 0)
2012 goto error;
2013
2014 /* Additional configuration */
2015 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2016 if (status < 0)
2017 goto error;
2018 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2019 if (status < 0)
2020 goto error;
2021 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2022error:
2023 if (status < 0)
2024 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2025
2026 return status;
2027}
2028
2029static int MPEGTSDtoSetup(struct drxk_state *state,
2030 enum OperationMode oMode)
2031{
2032 int status;
2033
2034 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2035 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2036 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2037 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2038 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2039 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2040 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2041 u16 fecOcTmdMode = 0;
2042 u16 fecOcTmdIntUpdRate = 0;
2043 u32 maxBitRate = 0;
2044 bool staticCLK = false;
2045
2046 dprintk(1, "\n");
2047
2048 /* Check insertion of the Reed-Solomon parity bytes */
2049 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2050 if (status < 0)
2051 goto error;
2052 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2053 if (status < 0)
2054 goto error;
2055 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2056 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2057 if (state->m_insertRSByte == true) {
2058 /* enable parity symbol forward */
2059 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2060 /* MVAL disable during parity bytes */
2061 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2062 /* TS burst length to 204 */
2063 fecOcDtoBurstLen = 204;
2064 }
2065
2066 /* Check serial or parrallel output */
2067 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2068 if (state->m_enableParallel == false) {
2069 /* MPEG data output is serial -> set ipr_mode[0] */
2070 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2071 }
2072
2073 switch (oMode) {
2074 case OM_DVBT:
2075 maxBitRate = state->m_DVBTBitrate;
2076 fecOcTmdMode = 3;
2077 fecOcRcnCtlRate = 0xC00000;
2078 staticCLK = state->m_DVBTStaticCLK;
2079 break;
2080 case OM_QAM_ITU_A: /* fallthrough */
2081 case OM_QAM_ITU_C:
2082 fecOcTmdMode = 0x0004;
2083 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2084 maxBitRate = state->m_DVBCBitrate;
2085 staticCLK = state->m_DVBCStaticCLK;
2086 break;
2087 default:
2088 status = -EINVAL;
2089 } /* switch (standard) */
2090 if (status < 0)
2091 goto error;
2092
2093 /* Configure DTO's */
2094 if (staticCLK) {
2095 u32 bitRate = 0;
2096
2097 /* Rational DTO for MCLK source (static MCLK rate),
2098 Dynamic DTO for optimal grouping
2099 (avoid intra-packet gaps),
2100 DTO offset enable to sync TS burst with MSTRT */
2101 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2102 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2103 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2104 FEC_OC_FCT_MODE_VIRT_ENA__M);
2105
2106 /* Check user defined bitrate */
2107 bitRate = maxBitRate;
2108 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2109 bitRate = 75900000UL;
2110 }
2111 /* Rational DTO period:
2112 dto_period = (Fsys / bitrate) - 2
2113
2114 Result should be floored,
2115 to make sure >= requested bitrate
2116 */
2117 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2118 * 1000) / bitRate);
2119 if (fecOcDtoPeriod <= 2)
2120 fecOcDtoPeriod = 0;
2121 else
2122 fecOcDtoPeriod -= 2;
2123 fecOcTmdIntUpdRate = 8;
2124 } else {
2125 /* (commonAttr->staticCLK == false) => dynamic mode */
2126 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2127 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2128 fecOcTmdIntUpdRate = 5;
2129 }
2130
2131 /* Write appropriate registers with requested configuration */
2132 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2133 if (status < 0)
2134 goto error;
2135 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2136 if (status < 0)
2137 goto error;
2138 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2139 if (status < 0)
2140 goto error;
2141 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2142 if (status < 0)
2143 goto error;
2144 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2145 if (status < 0)
2146 goto error;
2147 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2148 if (status < 0)
2149 goto error;
2150
2151 /* Rate integration settings */
2152 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2153 if (status < 0)
2154 goto error;
2155 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2156 if (status < 0)
2157 goto error;
2158 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2159error:
2160 if (status < 0)
2161 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2162 return status;
2163}
2164
2165static int MPEGTSConfigurePolarity(struct drxk_state *state)
2166{
2167 u16 fecOcRegIprInvert = 0;
2168
2169 /* Data mask for the output data byte */
2170 u16 InvertDataMask =
2171 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2172 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2173 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2174 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2175
2176 dprintk(1, "\n");
2177
2178 /* Control selective inversion of output bits */
2179 fecOcRegIprInvert &= (~(InvertDataMask));
2180 if (state->m_invertDATA == true)
2181 fecOcRegIprInvert |= InvertDataMask;
2182 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2183 if (state->m_invertERR == true)
2184 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2185 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2186 if (state->m_invertSTR == true)
2187 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2188 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2189 if (state->m_invertVAL == true)
2190 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2191 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2192 if (state->m_invertCLK == true)
2193 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2194
2195 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2196}
2197
2198#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2199
2200static int SetAgcRf(struct drxk_state *state,
2201 struct SCfgAgc *pAgcCfg, bool isDTV)
2202{
2203 int status = -EINVAL;
2204 u16 data = 0;
2205 struct SCfgAgc *pIfAgcSettings;
2206
2207 dprintk(1, "\n");
2208
2209 if (pAgcCfg == NULL)
2210 goto error;
2211
2212 switch (pAgcCfg->ctrlMode) {
2213 case DRXK_AGC_CTRL_AUTO:
2214 /* Enable RF AGC DAC */
2215 status = read16(state, IQM_AF_STDBY__A, &data);
2216 if (status < 0)
2217 goto error;
2218 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2219 status = write16(state, IQM_AF_STDBY__A, data);
2220 if (status < 0)
2221 goto error;
2222 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2223 if (status < 0)
2224 goto error;
2225
2226 /* Enable SCU RF AGC loop */
2227 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2228
2229 /* Polarity */
2230 if (state->m_RfAgcPol)
2231 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2232 else
2233 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2234 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2235 if (status < 0)
2236 goto error;
2237
2238 /* Set speed (using complementary reduction value) */
2239 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2240 if (status < 0)
2241 goto error;
2242
2243 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2244 data |= (~(pAgcCfg->speed <<
2245 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2246 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2247
2248 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2249 if (status < 0)
2250 goto error;
2251
2252 if (IsDVBT(state))
2253 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2254 else if (IsQAM(state))
2255 pIfAgcSettings = &state->m_qamIfAgcCfg;
2256 else
2257 pIfAgcSettings = &state->m_atvIfAgcCfg;
2258 if (pIfAgcSettings == NULL) {
2259 status = -EINVAL;
2260 goto error;
2261 }
2262
2263 /* Set TOP, only if IF-AGC is in AUTO mode */
2264 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2265 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2266 if (status < 0)
2267 goto error;
2268
2269 /* Cut-Off current */
2270 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2271 if (status < 0)
2272 goto error;
2273
2274 /* Max. output level */
2275 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2276 if (status < 0)
2277 goto error;
2278
2279 break;
2280
2281 case DRXK_AGC_CTRL_USER:
2282 /* Enable RF AGC DAC */
2283 status = read16(state, IQM_AF_STDBY__A, &data);
2284 if (status < 0)
2285 goto error;
2286 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2287 status = write16(state, IQM_AF_STDBY__A, data);
2288 if (status < 0)
2289 goto error;
2290
2291 /* Disable SCU RF AGC loop */
2292 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2293 if (status < 0)
2294 goto error;
2295 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2296 if (state->m_RfAgcPol)
2297 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2298 else
2299 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2300 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2301 if (status < 0)
2302 goto error;
2303
2304 /* SCU c.o.c. to 0, enabling full control range */
2305 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2306 if (status < 0)
2307 goto error;
2308
2309 /* Write value to output pin */
2310 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2311 if (status < 0)
2312 goto error;
2313 break;
2314
2315 case DRXK_AGC_CTRL_OFF:
2316 /* Disable RF AGC DAC */
2317 status = read16(state, IQM_AF_STDBY__A, &data);
2318 if (status < 0)
2319 goto error;
2320 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2321 status = write16(state, IQM_AF_STDBY__A, data);
2322 if (status < 0)
2323 goto error;
2324
2325 /* Disable SCU RF AGC loop */
2326 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2327 if (status < 0)
2328 goto error;
2329 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2330 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2331 if (status < 0)
2332 goto error;
2333 break;
2334
2335 default:
2336 status = -EINVAL;
2337
2338 }
2339error:
2340 if (status < 0)
2341 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2342 return status;
2343}
2344
2345#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2346
2347static int SetAgcIf(struct drxk_state *state,
2348 struct SCfgAgc *pAgcCfg, bool isDTV)
2349{
2350 u16 data = 0;
2351 int status = 0;
2352 struct SCfgAgc *pRfAgcSettings;
2353
2354 dprintk(1, "\n");
2355
2356 switch (pAgcCfg->ctrlMode) {
2357 case DRXK_AGC_CTRL_AUTO:
2358
2359 /* Enable IF AGC DAC */
2360 status = read16(state, IQM_AF_STDBY__A, &data);
2361 if (status < 0)
2362 goto error;
2363 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2364 status = write16(state, IQM_AF_STDBY__A, data);
2365 if (status < 0)
2366 goto error;
2367
2368 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2369 if (status < 0)
2370 goto error;
2371
2372 /* Enable SCU IF AGC loop */
2373 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2374
2375 /* Polarity */
2376 if (state->m_IfAgcPol)
2377 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2378 else
2379 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2380 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2381 if (status < 0)
2382 goto error;
2383
2384 /* Set speed (using complementary reduction value) */
2385 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2386 if (status < 0)
2387 goto error;
2388 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2389 data |= (~(pAgcCfg->speed <<
2390 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2391 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2392
2393 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2394 if (status < 0)
2395 goto error;
2396
2397 if (IsQAM(state))
2398 pRfAgcSettings = &state->m_qamRfAgcCfg;
2399 else
2400 pRfAgcSettings = &state->m_atvRfAgcCfg;
2401 if (pRfAgcSettings == NULL)
2402 return -1;
2403 /* Restore TOP */
2404 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2405 if (status < 0)
2406 goto error;
2407 break;
2408
2409 case DRXK_AGC_CTRL_USER:
2410
2411 /* Enable IF AGC DAC */
2412 status = read16(state, IQM_AF_STDBY__A, &data);
2413 if (status < 0)
2414 goto error;
2415 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2416 status = write16(state, IQM_AF_STDBY__A, data);
2417 if (status < 0)
2418 goto error;
2419
2420 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2421 if (status < 0)
2422 goto error;
2423
2424 /* Disable SCU IF AGC loop */
2425 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2426
2427 /* Polarity */
2428 if (state->m_IfAgcPol)
2429 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2430 else
2431 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2432 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2433 if (status < 0)
2434 goto error;
2435
2436 /* Write value to output pin */
2437 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2438 if (status < 0)
2439 goto error;
2440 break;
2441
2442 case DRXK_AGC_CTRL_OFF:
2443
2444 /* Disable If AGC DAC */
2445 status = read16(state, IQM_AF_STDBY__A, &data);
2446 if (status < 0)
2447 goto error;
2448 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2449 status = write16(state, IQM_AF_STDBY__A, data);
2450 if (status < 0)
2451 goto error;
2452
2453 /* Disable SCU IF AGC loop */
2454 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2455 if (status < 0)
2456 goto error;
2457 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2458 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2459 if (status < 0)
2460 goto error;
2461 break;
2462 } /* switch (agcSettingsIf->ctrlMode) */
2463
2464 /* always set the top to support
2465 configurations without if-loop */
2466 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2467error:
2468 if (status < 0)
2469 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2470 return status;
2471}
2472
2473static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2474{
2475 u16 agcDacLvl;
2476 int status;
2477 u16 Level = 0;
2478
2479 dprintk(1, "\n");
2480
2481 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2482 if (status < 0) {
2483 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2484 return status;
2485 }
2486
2487 *pValue = 0;
2488
2489 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2490 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2491 if (Level < 14000)
2492 *pValue = (14000 - Level) / 4;
2493 else
2494 *pValue = 0;
2495
2496 return status;
2497}
2498
2499static int GetQAMSignalToNoise(struct drxk_state *state,
2500 s32 *pSignalToNoise)
2501{
2502 int status = 0;
2503 u16 qamSlErrPower = 0; /* accum. error between
2504 raw and sliced symbols */
2505 u32 qamSlSigPower = 0; /* used for MER, depends of
2506 QAM constellation */
2507 u32 qamSlMer = 0; /* QAM MER */
2508
2509 dprintk(1, "\n");
2510
2511 /* MER calculation */
2512
2513 /* get the register value needed for MER */
2514 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2515 if (status < 0) {
2516 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2517 return -EINVAL;
2518 }
2519
2520 switch (state->param.u.qam.modulation) {
2521 case QAM_16:
2522 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2523 break;
2524 case QAM_32:
2525 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2526 break;
2527 case QAM_64:
2528 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2529 break;
2530 case QAM_128:
2531 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2532 break;
2533 default:
2534 case QAM_256:
2535 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2536 break;
2537 }
2538
2539 if (qamSlErrPower > 0) {
2540 qamSlMer = Log10Times100(qamSlSigPower) -
2541 Log10Times100((u32) qamSlErrPower);
2542 }
2543 *pSignalToNoise = qamSlMer;
2544
2545 return status;
2546}
2547
2548static int GetDVBTSignalToNoise(struct drxk_state *state,
2549 s32 *pSignalToNoise)
2550{
2551 int status;
2552 u16 regData = 0;
2553 u32 EqRegTdSqrErrI = 0;
2554 u32 EqRegTdSqrErrQ = 0;
2555 u16 EqRegTdSqrErrExp = 0;
2556 u16 EqRegTdTpsPwrOfs = 0;
2557 u16 EqRegTdReqSmbCnt = 0;
2558 u32 tpsCnt = 0;
2559 u32 SqrErrIQ = 0;
2560 u32 a = 0;
2561 u32 b = 0;
2562 u32 c = 0;
2563 u32 iMER = 0;
2564 u16 transmissionParams = 0;
2565
2566 dprintk(1, "\n");
2567
2568 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2569 if (status < 0)
2570 goto error;
2571 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2572 if (status < 0)
2573 goto error;
2574 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2575 if (status < 0)
2576 goto error;
2577 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2578 if (status < 0)
2579 goto error;
2580 /* Extend SQR_ERR_I operational range */
2581 EqRegTdSqrErrI = (u32) regData;
2582 if ((EqRegTdSqrErrExp > 11) &&
2583 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2584 EqRegTdSqrErrI += 0x00010000UL;
2585 }
2586 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2587 if (status < 0)
2588 goto error;
2589 /* Extend SQR_ERR_Q operational range */
2590 EqRegTdSqrErrQ = (u32) regData;
2591 if ((EqRegTdSqrErrExp > 11) &&
2592 (EqRegTdSqrErrQ < 0x00000FFFUL))
2593 EqRegTdSqrErrQ += 0x00010000UL;
2594
2595 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2596 if (status < 0)
2597 goto error;
2598
2599 /* Check input data for MER */
2600
2601 /* MER calculation (in 0.1 dB) without math.h */
2602 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2603 iMER = 0;
2604 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2605 /* No error at all, this must be the HW reset value
2606 * Apparently no first measurement yet
2607 * Set MER to 0.0 */
2608 iMER = 0;
2609 } else {
2610 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2611 EqRegTdSqrErrExp;
2612 if ((transmissionParams &
2613 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2614 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2615 tpsCnt = 17;
2616 else
2617 tpsCnt = 68;
2618
2619 /* IMER = 100 * log10 (x)
2620 where x = (EqRegTdTpsPwrOfs^2 *
2621 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2622
2623 => IMER = a + b -c
2624 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2625 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2626 c = 100 * log10 (SqrErrIQ)
2627 */
2628
2629 /* log(x) x = 9bits * 9bits->18 bits */
2630 a = Log10Times100(EqRegTdTpsPwrOfs *
2631 EqRegTdTpsPwrOfs);
2632 /* log(x) x = 16bits * 7bits->23 bits */
2633 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2634 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2635 c = Log10Times100(SqrErrIQ);
2636
2637 iMER = a + b;
2638 /* No negative MER, clip to zero */
2639 if (iMER > c)
2640 iMER -= c;
2641 else
2642 iMER = 0;
2643 }
2644 *pSignalToNoise = iMER;
2645
2646error:
2647 if (status < 0)
2648 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2649 return status;
2650}
2651
2652static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2653{
2654 dprintk(1, "\n");
2655
2656 *pSignalToNoise = 0;
2657 switch (state->m_OperationMode) {
2658 case OM_DVBT:
2659 return GetDVBTSignalToNoise(state, pSignalToNoise);
2660 case OM_QAM_ITU_A:
2661 case OM_QAM_ITU_C:
2662 return GetQAMSignalToNoise(state, pSignalToNoise);
2663 default:
2664 break;
2665 }
2666 return 0;
2667}
2668
2669#if 0
2670static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2671{
2672 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2673 int status = 0;
2674
2675 dprintk(1, "\n");
2676
2677 static s32 QE_SN[] = {
2678 51, /* QPSK 1/2 */
2679 69, /* QPSK 2/3 */
2680 79, /* QPSK 3/4 */
2681 89, /* QPSK 5/6 */
2682 97, /* QPSK 7/8 */
2683 108, /* 16-QAM 1/2 */
2684 131, /* 16-QAM 2/3 */
2685 146, /* 16-QAM 3/4 */
2686 156, /* 16-QAM 5/6 */
2687 160, /* 16-QAM 7/8 */
2688 165, /* 64-QAM 1/2 */
2689 187, /* 64-QAM 2/3 */
2690 202, /* 64-QAM 3/4 */
2691 216, /* 64-QAM 5/6 */
2692 225, /* 64-QAM 7/8 */
2693 };
2694
2695 *pQuality = 0;
2696
2697 do {
2698 s32 SignalToNoise = 0;
2699 u16 Constellation = 0;
2700 u16 CodeRate = 0;
2701 u32 SignalToNoiseRel;
2702 u32 BERQuality;
2703
2704 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2705 if (status < 0)
2706 break;
2707 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2708 if (status < 0)
2709 break;
2710 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2711
2712 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2713 if (status < 0)
2714 break;
2715 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2716
2717 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2718 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2719 break;
2720 SignalToNoiseRel = SignalToNoise -
2721 QE_SN[Constellation * 5 + CodeRate];
2722 BERQuality = 100;
2723
2724 if (SignalToNoiseRel < -70)
2725 *pQuality = 0;
2726 else if (SignalToNoiseRel < 30)
2727 *pQuality = ((SignalToNoiseRel + 70) *
2728 BERQuality) / 100;
2729 else
2730 *pQuality = BERQuality;
2731 } while (0);
2732 return 0;
2733};
2734
2735static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2736{
2737 int status = 0;
2738 *pQuality = 0;
2739
2740 dprintk(1, "\n");
2741
2742 do {
2743 u32 SignalToNoise = 0;
2744 u32 BERQuality = 100;
2745 u32 SignalToNoiseRel = 0;
2746
2747 status = GetQAMSignalToNoise(state, &SignalToNoise);
2748 if (status < 0)
2749 break;
2750
2751 switch (state->param.u.qam.modulation) {
2752 case QAM_16:
2753 SignalToNoiseRel = SignalToNoise - 200;
2754 break;
2755 case QAM_32:
2756 SignalToNoiseRel = SignalToNoise - 230;
2757 break; /* Not in NorDig */
2758 case QAM_64:
2759 SignalToNoiseRel = SignalToNoise - 260;
2760 break;
2761 case QAM_128:
2762 SignalToNoiseRel = SignalToNoise - 290;
2763 break;
2764 default:
2765 case QAM_256:
2766 SignalToNoiseRel = SignalToNoise - 320;
2767 break;
2768 }
2769
2770 if (SignalToNoiseRel < -70)
2771 *pQuality = 0;
2772 else if (SignalToNoiseRel < 30)
2773 *pQuality = ((SignalToNoiseRel + 70) *
2774 BERQuality) / 100;
2775 else
2776 *pQuality = BERQuality;
2777 } while (0);
2778
2779 return status;
2780}
2781
2782static int GetQuality(struct drxk_state *state, s32 *pQuality)
2783{
2784 dprintk(1, "\n");
2785
2786 switch (state->m_OperationMode) {
2787 case OM_DVBT:
2788 return GetDVBTQuality(state, pQuality);
2789 case OM_QAM_ITU_A:
2790 return GetDVBCQuality(state, pQuality);
2791 default:
2792 break;
2793 }
2794
2795 return 0;
2796}
2797#endif
2798
2799/* Free data ram in SIO HI */
2800#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2801#define SIO_HI_RA_RAM_USR_END__A 0x420060
2802
2803#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2804#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2805#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2806#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2807
2808#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2809#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2810#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2811
2812static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2813{
2814 int status = -EINVAL;
2815
2816 dprintk(1, "\n");
2817
2818 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2819 goto error;
2820 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2821 goto error;
2822
2823 if (state->no_i2c_bridge)
2824 return 0;
2825
2826 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2827 if (status < 0)
2828 goto error;
2829 if (bEnableBridge) {
2830 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2831 if (status < 0)
2832 goto error;
2833 } else {
2834 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2835 if (status < 0)
2836 goto error;
2837 }
2838
2839 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2840
2841error:
2842 if (status < 0)
2843 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2844 return status;
2845}
2846
2847static int SetPreSaw(struct drxk_state *state,
2848 struct SCfgPreSaw *pPreSawCfg)
2849{
2850 int status = -EINVAL;
2851
2852 dprintk(1, "\n");
2853
2854 if ((pPreSawCfg == NULL)
2855 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2856 goto error;
2857
2858 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2859error:
2860 if (status < 0)
2861 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2862 return status;
2863}
2864
2865static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2866 u16 romOffset, u16 nrOfElements, u32 timeOut)
2867{
2868 u16 blStatus = 0;
2869 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2870 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2871 int status;
2872 unsigned long end;
2873
2874 dprintk(1, "\n");
2875
2876 mutex_lock(&state->mutex);
2877 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2878 if (status < 0)
2879 goto error;
2880 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2881 if (status < 0)
2882 goto error;
2883 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2884 if (status < 0)
2885 goto error;
2886 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2887 if (status < 0)
2888 goto error;
2889 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2890 if (status < 0)
2891 goto error;
2892 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2893 if (status < 0)
2894 goto error;
2895
2896 end = jiffies + msecs_to_jiffies(timeOut);
2897 do {
2898 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2899 if (status < 0)
2900 goto error;
2901 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2902 if (blStatus == 0x1) {
2903 printk(KERN_ERR "drxk: SIO not ready\n");
2904 status = -EINVAL;
2905 goto error2;
2906 }
2907error:
2908 if (status < 0)
2909 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2910error2:
2911 mutex_unlock(&state->mutex);
2912 return status;
2913
2914}
2915
2916static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2917{
2918 u16 data = 0;
2919 int status;
2920
2921 dprintk(1, "\n");
2922
2923 /* Start measurement */
2924 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2925 if (status < 0)
2926 goto error;
2927 status = write16(state, IQM_AF_START_LOCK__A, 1);
2928 if (status < 0)
2929 goto error;
2930
2931 *count = 0;
2932 status = read16(state, IQM_AF_PHASE0__A, &data);
2933 if (status < 0)
2934 goto error;
2935 if (data == 127)
2936 *count = *count + 1;
2937 status = read16(state, IQM_AF_PHASE1__A, &data);
2938 if (status < 0)
2939 goto error;
2940 if (data == 127)
2941 *count = *count + 1;
2942 status = read16(state, IQM_AF_PHASE2__A, &data);
2943 if (status < 0)
2944 goto error;
2945 if (data == 127)
2946 *count = *count + 1;
2947
2948error:
2949 if (status < 0)
2950 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2951 return status;
2952}
2953
2954static int ADCSynchronization(struct drxk_state *state)
2955{
2956 u16 count = 0;
2957 int status;
2958
2959 dprintk(1, "\n");
2960
2961 status = ADCSyncMeasurement(state, &count);
2962 if (status < 0)
2963 goto error;
2964
2965 if (count == 1) {
2966 /* Try sampling on a diffrent edge */
2967 u16 clkNeg = 0;
2968
2969 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2970 if (status < 0)
2971 goto error;
2972 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2973 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2974 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2975 clkNeg |=
2976 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2977 } else {
2978 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2979 clkNeg |=
2980 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2981 }
2982 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2983 if (status < 0)
2984 goto error;
2985 status = ADCSyncMeasurement(state, &count);
2986 if (status < 0)
2987 goto error;
2988 }
2989
2990 if (count < 2)
2991 status = -EINVAL;
2992error:
2993 if (status < 0)
2994 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2995 return status;
2996}
2997
2998static int SetFrequencyShifter(struct drxk_state *state,
2999 u16 intermediateFreqkHz,
3000 s32 tunerFreqOffset, bool isDTV)
3001{
3002 bool selectPosImage = false;
3003 u32 rfFreqResidual = tunerFreqOffset;
3004 u32 fmFrequencyShift = 0;
3005 bool tunerMirror = !state->m_bMirrorFreqSpect;
3006 u32 adcFreq;
3007 bool adcFlip;
3008 int status;
3009 u32 ifFreqActual;
3010 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3011 u32 frequencyShift;
3012 bool imageToSelect;
3013
3014 dprintk(1, "\n");
3015
3016 /*
3017 Program frequency shifter
3018 No need to account for mirroring on RF
3019 */
3020 if (isDTV) {
3021 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3022 (state->m_OperationMode == OM_QAM_ITU_C) ||
3023 (state->m_OperationMode == OM_DVBT))
3024 selectPosImage = true;
3025 else
3026 selectPosImage = false;
3027 }
3028 if (tunerMirror)
3029 /* tuner doesn't mirror */
3030 ifFreqActual = intermediateFreqkHz +
3031 rfFreqResidual + fmFrequencyShift;
3032 else
3033 /* tuner mirrors */
3034 ifFreqActual = intermediateFreqkHz -
3035 rfFreqResidual - fmFrequencyShift;
3036 if (ifFreqActual > samplingFrequency / 2) {
3037 /* adc mirrors */
3038 adcFreq = samplingFrequency - ifFreqActual;
3039 adcFlip = true;
3040 } else {
3041 /* adc doesn't mirror */
3042 adcFreq = ifFreqActual;
3043 adcFlip = false;
3044 }
3045
3046 frequencyShift = adcFreq;
3047 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3048 adcFlip ^ selectPosImage;
3049 state->m_IqmFsRateOfs =
3050 Frac28a((frequencyShift), samplingFrequency);
3051
3052 if (imageToSelect)
3053 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3054
3055 /* Program frequency shifter with tuner offset compensation */
3056 /* frequencyShift += tunerFreqOffset; TODO */
3057 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3058 state->m_IqmFsRateOfs);
3059 if (status < 0)
3060 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3061 return status;
3062}
3063
3064static int InitAGC(struct drxk_state *state, bool isDTV)
3065{
3066 u16 ingainTgt = 0;
3067 u16 ingainTgtMin = 0;
3068 u16 ingainTgtMax = 0;
3069 u16 clpCyclen = 0;
3070 u16 clpSumMin = 0;
3071 u16 clpDirTo = 0;
3072 u16 snsSumMin = 0;
3073 u16 snsSumMax = 0;
3074 u16 clpSumMax = 0;
3075 u16 snsDirTo = 0;
3076 u16 kiInnergainMin = 0;
3077 u16 ifIaccuHiTgt = 0;
3078 u16 ifIaccuHiTgtMin = 0;
3079 u16 ifIaccuHiTgtMax = 0;
3080 u16 data = 0;
3081 u16 fastClpCtrlDelay = 0;
3082 u16 clpCtrlMode = 0;
3083 int status = 0;
3084
3085 dprintk(1, "\n");
3086
3087 /* Common settings */
3088 snsSumMax = 1023;
3089 ifIaccuHiTgtMin = 2047;
3090 clpCyclen = 500;
3091 clpSumMax = 1023;
3092
3093 /* AGCInit() not available for DVBT; init done in microcode */
3094 if (!IsQAM(state)) {
3095 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3096 return -EINVAL;
3097 }
3098
3099 /* FIXME: Analog TV AGC require different settings */
3100
3101 /* Standard specific settings */
3102 clpSumMin = 8;
3103 clpDirTo = (u16) -9;
3104 clpCtrlMode = 0;
3105 snsSumMin = 8;
3106 snsDirTo = (u16) -9;
3107 kiInnergainMin = (u16) -1030;
3108 ifIaccuHiTgtMax = 0x2380;
3109 ifIaccuHiTgt = 0x2380;
3110 ingainTgtMin = 0x0511;
3111 ingainTgt = 0x0511;
3112 ingainTgtMax = 5119;
3113 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3114
3115 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3116 if (status < 0)
3117 goto error;
3118
3119 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3120 if (status < 0)
3121 goto error;
3122 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3123 if (status < 0)
3124 goto error;
3125 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3126 if (status < 0)
3127 goto error;
3128 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3129 if (status < 0)
3130 goto error;
3131 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3132 if (status < 0)
3133 goto error;
3134 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3135 if (status < 0)
3136 goto error;
3137 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3138 if (status < 0)
3139 goto error;
3140 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3141 if (status < 0)
3142 goto error;
3143 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3144 if (status < 0)
3145 goto error;
3146 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3147 if (status < 0)
3148 goto error;
3149 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3150 if (status < 0)
3151 goto error;
3152 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3153 if (status < 0)
3154 goto error;
3155
3156 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3157 if (status < 0)
3158 goto error;
3159 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3160 if (status < 0)
3161 goto error;
3162 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3163 if (status < 0)
3164 goto error;
3165
3166 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3167 if (status < 0)
3168 goto error;
3169 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3170 if (status < 0)
3171 goto error;
3172 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3173 if (status < 0)
3174 goto error;
3175
3176 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3177 if (status < 0)
3178 goto error;
3179 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3180 if (status < 0)
3181 goto error;
3182 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3183 if (status < 0)
3184 goto error;
3185 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3186 if (status < 0)
3187 goto error;
3188 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3189 if (status < 0)
3190 goto error;
3191 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3192 if (status < 0)
3193 goto error;
3194 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3195 if (status < 0)
3196 goto error;
3197 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3198 if (status < 0)
3199 goto error;
3200 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3201 if (status < 0)
3202 goto error;
3203 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3204 if (status < 0)
3205 goto error;
3206 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3207 if (status < 0)
3208 goto error;
3209 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3210 if (status < 0)
3211 goto error;
3212 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3213 if (status < 0)
3214 goto error;
3215 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3216 if (status < 0)
3217 goto error;
3218 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3219 if (status < 0)
3220 goto error;
3221 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3222 if (status < 0)
3223 goto error;
3224 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3225 if (status < 0)
3226 goto error;
3227 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3228 if (status < 0)
3229 goto error;
3230 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3231 if (status < 0)
3232 goto error;
3233
3234 /* Initialize inner-loop KI gain factors */
3235 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3236 if (status < 0)
3237 goto error;
3238
3239 data = 0x0657;
3240 data &= ~SCU_RAM_AGC_KI_RF__M;
3241 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3242 data &= ~SCU_RAM_AGC_KI_IF__M;
3243 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3244
3245 status = write16(state, SCU_RAM_AGC_KI__A, data);
3246error:
3247 if (status < 0)
3248 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3249 return status;
3250}
3251
3252static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3253{
3254 int status;
3255
3256 dprintk(1, "\n");
3257 if (packetErr == NULL)
3258 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3259 else
3260 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3261 if (status < 0)
3262 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3263 return status;
3264}
3265
3266static int DVBTScCommand(struct drxk_state *state,
3267 u16 cmd, u16 subcmd,
3268 u16 param0, u16 param1, u16 param2,
3269 u16 param3, u16 param4)
3270{
3271 u16 curCmd = 0;
3272 u16 errCode = 0;
3273 u16 retryCnt = 0;
3274 u16 scExec = 0;
3275 int status;
3276
3277 dprintk(1, "\n");
3278 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3279 if (scExec != 1) {
3280 /* SC is not running */
3281 status = -EINVAL;
3282 }
3283 if (status < 0)
3284 goto error;
3285
3286 /* Wait until sc is ready to receive command */
3287 retryCnt = 0;
3288 do {
3289 msleep(1);
3290 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3291 retryCnt++;
3292 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3293 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3294 goto error;
3295
3296 /* Write sub-command */
3297 switch (cmd) {
3298 /* All commands using sub-cmd */
3299 case OFDM_SC_RA_RAM_CMD_PROC_START:
3300 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3301 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3302 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3303 if (status < 0)
3304 goto error;
3305 break;
3306 default:
3307 /* Do nothing */
3308 break;
3309 }
3310
3311 /* Write needed parameters and the command */
3312 switch (cmd) {
3313 /* All commands using 5 parameters */
3314 /* All commands using 4 parameters */
3315 /* All commands using 3 parameters */
3316 /* All commands using 2 parameters */
3317 case OFDM_SC_RA_RAM_CMD_PROC_START:
3318 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3319 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3320 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3321 /* All commands using 1 parameters */
3322 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3323 case OFDM_SC_RA_RAM_CMD_USER_IO:
3324 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3325 /* All commands using 0 parameters */
3326 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3327 case OFDM_SC_RA_RAM_CMD_NULL:
3328 /* Write command */
3329 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3330 break;
3331 default:
3332 /* Unknown command */
3333 status = -EINVAL;
3334 }
3335 if (status < 0)
3336 goto error;
3337
3338 /* Wait until sc is ready processing command */
3339 retryCnt = 0;
3340 do {
3341 msleep(1);
3342 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3343 retryCnt++;
3344 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3345 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3346 goto error;
3347
3348 /* Check for illegal cmd */
3349 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3350 if (errCode == 0xFFFF) {
3351 /* illegal command */
3352 status = -EINVAL;
3353 }
3354 if (status < 0)
3355 goto error;
3356
3357 /* Retreive results parameters from SC */
3358 switch (cmd) {
3359 /* All commands yielding 5 results */
3360 /* All commands yielding 4 results */
3361 /* All commands yielding 3 results */
3362 /* All commands yielding 2 results */
3363 /* All commands yielding 1 result */
3364 case OFDM_SC_RA_RAM_CMD_USER_IO:
3365 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3366 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3367 /* All commands yielding 0 results */
3368 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3369 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3370 case OFDM_SC_RA_RAM_CMD_PROC_START:
3371 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3372 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3373 case OFDM_SC_RA_RAM_CMD_NULL:
3374 break;
3375 default:
3376 /* Unknown command */
3377 status = -EINVAL;
3378 break;
3379 } /* switch (cmd->cmd) */
3380error:
3381 if (status < 0)
3382 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3383 return status;
3384}
3385
3386static int PowerUpDVBT(struct drxk_state *state)
3387{
3388 enum DRXPowerMode powerMode = DRX_POWER_UP;
3389 int status;
3390
3391 dprintk(1, "\n");
3392 status = CtrlPowerMode(state, &powerMode);
3393 if (status < 0)
3394 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3395 return status;
3396}
3397
3398static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3399{
3400 int status;
3401
3402 dprintk(1, "\n");
3403 if (*enabled == true)
3404 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3405 else
3406 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3407 if (status < 0)
3408 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3409 return status;
3410}
3411
3412#define DEFAULT_FR_THRES_8K 4000
3413static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3414{
3415
3416 int status;
3417
3418 dprintk(1, "\n");
3419 if (*enabled == true) {
3420 /* write mask to 1 */
3421 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3422 DEFAULT_FR_THRES_8K);
3423 } else {
3424 /* write mask to 0 */
3425 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3426 }
3427 if (status < 0)
3428 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3429
3430 return status;
3431}
3432
3433static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3434 struct DRXKCfgDvbtEchoThres_t *echoThres)
3435{
3436 u16 data = 0;
3437 int status;
3438
3439 dprintk(1, "\n");
3440 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3441 if (status < 0)
3442 goto error;
3443
3444 switch (echoThres->fftMode) {
3445 case DRX_FFTMODE_2K:
3446 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3447 data |= ((echoThres->threshold <<
3448 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3449 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3450 break;
3451 case DRX_FFTMODE_8K:
3452 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3453 data |= ((echoThres->threshold <<
3454 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3455 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3456 break;
3457 default:
3458 return -EINVAL;
3459 }
3460
3461 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3462error:
3463 if (status < 0)
3464 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3465 return status;
3466}
3467
3468static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3469 enum DRXKCfgDvbtSqiSpeed *speed)
3470{
3471 int status = -EINVAL;
3472
3473 dprintk(1, "\n");
3474
3475 switch (*speed) {
3476 case DRXK_DVBT_SQI_SPEED_FAST:
3477 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3478 case DRXK_DVBT_SQI_SPEED_SLOW:
3479 break;
3480 default:
3481 goto error;
3482 }
3483 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3484 (u16) *speed);
3485error:
3486 if (status < 0)
3487 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3488 return status;
3489}
3490
3491/*============================================================================*/
3492
3493/**
3494* \brief Activate DVBT specific presets
3495* \param demod instance of demodulator.
3496* \return DRXStatus_t.
3497*
3498* Called in DVBTSetStandard
3499*
3500*/
3501static int DVBTActivatePresets(struct drxk_state *state)
3502{
3503 int status;
3504 bool setincenable = false;
3505 bool setfrenable = true;
3506
3507 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3508 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3509
3510 dprintk(1, "\n");
3511 status = DVBTCtrlSetIncEnable(state, &setincenable);
3512 if (status < 0)
3513 goto error;
3514 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3515 if (status < 0)
3516 goto error;
3517 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3518 if (status < 0)
3519 goto error;
3520 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3521 if (status < 0)
3522 goto error;
3523 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3524error:
3525 if (status < 0)
3526 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3527 return status;
3528}
3529
3530/*============================================================================*/
3531
3532/**
3533* \brief Initialize channelswitch-independent settings for DVBT.
3534* \param demod instance of demodulator.
3535* \return DRXStatus_t.
3536*
3537* For ROM code channel filter taps are loaded from the bootloader. For microcode
3538* the DVB-T taps from the drxk_filters.h are used.
3539*/
3540static int SetDVBTStandard(struct drxk_state *state,
3541 enum OperationMode oMode)
3542{
3543 u16 cmdResult = 0;
3544 u16 data = 0;
3545 int status;
3546
3547 dprintk(1, "\n");
3548
3549 PowerUpDVBT(state);
3550 /* added antenna switch */
3551 SwitchAntennaToDVBT(state);
3552 /* send OFDM reset command */
3553 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3554 if (status < 0)
3555 goto error;
3556
3557 /* send OFDM setenv command */
3558 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3559 if (status < 0)
3560 goto error;
3561
3562 /* reset datapath for OFDM, processors first */
3563 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3564 if (status < 0)
3565 goto error;
3566 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3567 if (status < 0)
3568 goto error;
3569 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3570 if (status < 0)
3571 goto error;
3572
3573 /* IQM setup */
3574 /* synchronize on ofdstate->m_festart */
3575 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3576 if (status < 0)
3577 goto error;
3578 /* window size for clipping ADC detection */
3579 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3580 if (status < 0)
3581 goto error;
3582 /* window size for for sense pre-SAW detection */
3583 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3584 if (status < 0)
3585 goto error;
3586 /* sense threshold for sense pre-SAW detection */
3587 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3588 if (status < 0)
3589 goto error;
3590 status = SetIqmAf(state, true);
3591 if (status < 0)
3592 goto error;
3593
3594 status = write16(state, IQM_AF_AGC_RF__A, 0);
3595 if (status < 0)
3596 goto error;
3597
3598 /* Impulse noise cruncher setup */
3599 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3600 if (status < 0)
3601 goto error;
3602 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3603 if (status < 0)
3604 goto error;
3605 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3606 if (status < 0)
3607 goto error;
3608
3609 status = write16(state, IQM_RC_STRETCH__A, 16);
3610 if (status < 0)
3611 goto error;
3612 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3613 if (status < 0)
3614 goto error;
3615 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3616 if (status < 0)
3617 goto error;
3618 status = write16(state, IQM_CF_SCALE__A, 1600);
3619 if (status < 0)
3620 goto error;
3621 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3622 if (status < 0)
3623 goto error;
3624
3625 /* virtual clipping threshold for clipping ADC detection */
3626 status = write16(state, IQM_AF_CLP_TH__A, 448);
3627 if (status < 0)
3628 goto error;
3629 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3630 if (status < 0)
3631 goto error;
3632
3633 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3634 if (status < 0)
3635 goto error;
3636
3637 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3638 if (status < 0)
3639 goto error;
3640 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3641 if (status < 0)
3642 goto error;
3643 /* enable power measurement interrupt */
3644 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3645 if (status < 0)
3646 goto error;
3647 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3648 if (status < 0)
3649 goto error;
3650
3651 /* IQM will not be reset from here, sync ADC and update/init AGC */
3652 status = ADCSynchronization(state);
3653 if (status < 0)
3654 goto error;
3655 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3656 if (status < 0)
3657 goto error;
3658
3659 /* Halt SCU to enable safe non-atomic accesses */
3660 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3661 if (status < 0)
3662 goto error;
3663
3664 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3665 if (status < 0)
3666 goto error;
3667 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3668 if (status < 0)
3669 goto error;
3670
3671 /* Set Noise Estimation notch width and enable DC fix */
3672 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3673 if (status < 0)
3674 goto error;
3675 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3676 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3677 if (status < 0)
3678 goto error;
3679
3680 /* Activate SCU to enable SCU commands */
3681 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3682 if (status < 0)
3683 goto error;
3684
3685 if (!state->m_DRXK_A3_ROM_CODE) {
3686 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3687 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3688 if (status < 0)
3689 goto error;
3690 }
3691
3692 /* OFDM_SC setup */
3693#ifdef COMPILE_FOR_NONRT
3694 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3695 if (status < 0)
3696 goto error;
3697 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3698 if (status < 0)
3699 goto error;
3700#endif
3701
3702 /* FEC setup */
3703 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3704 if (status < 0)
3705 goto error;
3706
3707
3708#ifdef COMPILE_FOR_NONRT
3709 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3710 if (status < 0)
3711 goto error;
3712#else
3713 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3714 if (status < 0)
3715 goto error;
3716#endif
3717 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3718 if (status < 0)
3719 goto error;
3720
3721 /* Setup MPEG bus */
3722 status = MPEGTSDtoSetup(state, OM_DVBT);
3723 if (status < 0)
3724 goto error;
3725 /* Set DVBT Presets */
3726 status = DVBTActivatePresets(state);
3727 if (status < 0)
3728 goto error;
3729
3730error:
3731 if (status < 0)
3732 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3733 return status;
3734}
3735
3736/*============================================================================*/
3737/**
3738* \brief Start dvbt demodulating for channel.
3739* \param demod instance of demodulator.
3740* \return DRXStatus_t.
3741*/
3742static int DVBTStart(struct drxk_state *state)
3743{
3744 u16 param1;
3745 int status;
3746 /* DRXKOfdmScCmd_t scCmd; */
3747
3748 dprintk(1, "\n");
3749 /* Start correct processes to get in lock */
3750 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3751 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3752 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3753 if (status < 0)
3754 goto error;
3755 /* Start FEC OC */
3756 status = MPEGTSStart(state);
3757 if (status < 0)
3758 goto error;
3759 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3760 if (status < 0)
3761 goto error;
3762error:
3763 if (status < 0)
3764 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3765 return status;
3766}
3767
3768
3769/*============================================================================*/
3770
3771/**
3772* \brief Set up dvbt demodulator for channel.
3773* \param demod instance of demodulator.
3774* \return DRXStatus_t.
3775* // original DVBTSetChannel()
3776*/
3777static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3778 s32 tunerFreqOffset)
3779{
3780 u16 cmdResult = 0;
3781 u16 transmissionParams = 0;
3782 u16 operationMode = 0;
3783 u32 iqmRcRateOfs = 0;
3784 u32 bandwidth = 0;
3785 u16 param1;
3786 int status;
3787
3788 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3789
3790 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3791 if (status < 0)
3792 goto error;
3793
3794 /* Halt SCU to enable safe non-atomic accesses */
3795 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3796 if (status < 0)
3797 goto error;
3798
3799 /* Stop processors */
3800 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3801 if (status < 0)
3802 goto error;
3803 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3804 if (status < 0)
3805 goto error;
3806
3807 /* Mandatory fix, always stop CP, required to set spl offset back to
3808 hardware default (is set to 0 by ucode during pilot detection */
3809 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3810 if (status < 0)
3811 goto error;
3812
3813 /*== Write channel settings to device =====================================*/
3814
3815 /* mode */
3816 switch (state->param.u.ofdm.transmission_mode) {
3817 case TRANSMISSION_MODE_AUTO:
3818 default:
3819 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3820 /* fall through , try first guess DRX_FFTMODE_8K */
3821 case TRANSMISSION_MODE_8K:
3822 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3823 break;
3824 case TRANSMISSION_MODE_2K:
3825 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3826 break;
3827 }
3828
3829 /* guard */
3830 switch (state->param.u.ofdm.guard_interval) {
3831 default:
3832 case GUARD_INTERVAL_AUTO:
3833 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3834 /* fall through , try first guess DRX_GUARD_1DIV4 */
3835 case GUARD_INTERVAL_1_4:
3836 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3837 break;
3838 case GUARD_INTERVAL_1_32:
3839 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3840 break;
3841 case GUARD_INTERVAL_1_16:
3842 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3843 break;
3844 case GUARD_INTERVAL_1_8:
3845 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3846 break;
3847 }
3848
3849 /* hierarchy */
3850 switch (state->param.u.ofdm.hierarchy_information) {
3851 case HIERARCHY_AUTO:
3852 case HIERARCHY_NONE:
3853 default:
3854 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3855 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3856 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3857 /* break; */
3858 case HIERARCHY_1:
3859 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3860 break;
3861 case HIERARCHY_2:
3862 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3863 break;
3864 case HIERARCHY_4:
3865 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3866 break;
3867 }
3868
3869
3870 /* constellation */
3871 switch (state->param.u.ofdm.constellation) {
3872 case QAM_AUTO:
3873 default:
3874 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3875 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3876 case QAM_64:
3877 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3878 break;
3879 case QPSK:
3880 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3881 break;
3882 case QAM_16:
3883 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3884 break;
3885 }
3886#if 0
3887 /* No hierachical channels support in BDA */
3888 /* Priority (only for hierarchical channels) */
3889 switch (channel->priority) {
3890 case DRX_PRIORITY_LOW:
3891 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3892 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3893 OFDM_EC_SB_PRIOR_LO);
3894 break;
3895 case DRX_PRIORITY_HIGH:
3896 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3897 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3898 OFDM_EC_SB_PRIOR_HI));
3899 break;
3900 case DRX_PRIORITY_UNKNOWN: /* fall through */
3901 default:
3902 status = -EINVAL;
3903 goto error;
3904 }
3905#else
3906 /* Set Priorty high */
3907 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3908 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3909 if (status < 0)
3910 goto error;
3911#endif
3912
3913 /* coderate */
3914 switch (state->param.u.ofdm.code_rate_HP) {
3915 case FEC_AUTO:
3916 default:
3917 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3918 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3919 case FEC_2_3:
3920 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3921 break;
3922 case FEC_1_2:
3923 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3924 break;
3925 case FEC_3_4:
3926 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3927 break;
3928 case FEC_5_6:
3929 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3930 break;
3931 case FEC_7_8:
3932 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3933 break;
3934 }
3935
3936 /* SAW filter selection: normaly not necesarry, but if wanted
3937 the application can select a SAW filter via the driver by using UIOs */
3938 /* First determine real bandwidth (Hz) */
3939 /* Also set delay for impulse noise cruncher */
3940 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3941 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3942 functions */
3943 switch (state->param.u.ofdm.bandwidth) {
3944 case BANDWIDTH_AUTO:
3945 case BANDWIDTH_8_MHZ:
3946 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3947 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3948 if (status < 0)
3949 goto error;
3950 /* cochannel protection for PAL 8 MHz */
3951 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3952 if (status < 0)
3953 goto error;
3954 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3955 if (status < 0)
3956 goto error;
3957 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3958 if (status < 0)
3959 goto error;
3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3961 if (status < 0)
3962 goto error;
3963 break;
3964 case BANDWIDTH_7_MHZ:
3965 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3966 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3967 if (status < 0)
3968 goto error;
3969 /* cochannel protection for PAL 7 MHz */
3970 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3971 if (status < 0)
3972 goto error;
3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3974 if (status < 0)
3975 goto error;
3976 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3977 if (status < 0)
3978 goto error;
3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3980 if (status < 0)
3981 goto error;
3982 break;
3983 case BANDWIDTH_6_MHZ:
3984 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3985 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3986 if (status < 0)
3987 goto error;
3988 /* cochannel protection for NTSC 6 MHz */
3989 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3990 if (status < 0)
3991 goto error;
3992 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3993 if (status < 0)
3994 goto error;
3995 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3996 if (status < 0)
3997 goto error;
3998 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3999 if (status < 0)
4000 goto error;
4001 break;
4002 default:
4003 status = -EINVAL;
4004 goto error;
4005 }
4006
4007 if (iqmRcRateOfs == 0) {
4008 /* Now compute IQM_RC_RATE_OFS
4009 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4010 =>
4011 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4012 */
4013 /* (SysFreq / BandWidth) * (2^28) */
4014 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4015 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4016 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4017 iqmRcRateOfs = Frac28a((u32)
4018 ((state->m_sysClockFreq *
4019 1000) / 3), bandwidth);
4020 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4021 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4022 iqmRcRateOfs += 0x80L;
4023 iqmRcRateOfs = iqmRcRateOfs >> 7;
4024 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4025 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4026 }
4027
4028 iqmRcRateOfs &=
4029 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4030 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4031 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4032 if (status < 0)
4033 goto error;
4034
4035 /* Bandwidth setting done */
4036
4037#if 0
4038 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4039 if (status < 0)
4040 goto error;
4041#endif
4042 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4043 if (status < 0)
4044 goto error;
4045
4046 /*== Start SC, write channel settings to SC ===============================*/
4047
4048 /* Activate SCU to enable SCU commands */
4049 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4050 if (status < 0)
4051 goto error;
4052
4053 /* Enable SC after setting all other parameters */
4054 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4055 if (status < 0)
4056 goto error;
4057 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4058 if (status < 0)
4059 goto error;
4060
4061
4062 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4063 if (status < 0)
4064 goto error;
4065
4066 /* Write SC parameter registers, set all AUTO flags in operation mode */
4067 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4068 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4069 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4070 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4071 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4072 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4073 0, transmissionParams, param1, 0, 0, 0);
4074 if (status < 0)
4075 goto error;
4076
4077 if (!state->m_DRXK_A3_ROM_CODE)
4078 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4079error:
4080 if (status < 0)
4081 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4082
4083 return status;
4084}
4085
4086
4087/*============================================================================*/
4088
4089/**
4090* \brief Retreive lock status .
4091* \param demod Pointer to demodulator instance.
4092* \param lockStat Pointer to lock status structure.
4093* \return DRXStatus_t.
4094*
4095*/
4096static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4097{
4098 int status;
4099 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4100 OFDM_SC_RA_RAM_LOCK_FEC__M);
4101 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4102 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4103
4104 u16 ScRaRamLock = 0;
4105 u16 ScCommExec = 0;
4106
4107 dprintk(1, "\n");
4108
4109 *pLockStatus = NOT_LOCKED;
4110 /* driver 0.9.0 */
4111 /* Check if SC is running */
4112 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4113 if (status < 0)
4114 goto end;
4115 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4116 goto end;
4117
4118 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4119 if (status < 0)
4120 goto end;
4121
4122 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4123 *pLockStatus = MPEG_LOCK;
4124 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4125 *pLockStatus = FEC_LOCK;
4126 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4127 *pLockStatus = DEMOD_LOCK;
4128 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4129 *pLockStatus = NEVER_LOCK;
4130end:
4131 if (status < 0)
4132 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4133
4134 return status;
4135}
4136
4137static int PowerUpQAM(struct drxk_state *state)
4138{
4139 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4140 int status;
4141
4142 dprintk(1, "\n");
4143 status = CtrlPowerMode(state, &powerMode);
4144 if (status < 0)
4145 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4146
4147 return status;
4148}
4149
4150
4151/** Power Down QAM */
4152static int PowerDownQAM(struct drxk_state *state)
4153{
4154 u16 data = 0;
4155 u16 cmdResult;
4156 int status = 0;
4157
4158 dprintk(1, "\n");
4159 status = read16(state, SCU_COMM_EXEC__A, &data);
4160 if (status < 0)
4161 goto error;
4162 if (data == SCU_COMM_EXEC_ACTIVE) {
4163 /*
4164 STOP demodulator
4165 QAM and HW blocks
4166 */
4167 /* stop all comstate->m_exec */
4168 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4169 if (status < 0)
4170 goto error;
4171 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4172 if (status < 0)
4173 goto error;
4174 }
4175 /* powerdown AFE */
4176 status = SetIqmAf(state, false);
4177
4178error:
4179 if (status < 0)
4180 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4181
4182 return status;
4183}
4184
4185/*============================================================================*/
4186
4187/**
4188* \brief Setup of the QAM Measurement intervals for signal quality
4189* \param demod instance of demod.
4190* \param constellation current constellation.
4191* \return DRXStatus_t.
4192*
4193* NOTE:
4194* Take into account that for certain settings the errorcounters can overflow.
4195* The implementation does not check this.
4196*
4197*/
4198static int SetQAMMeasurement(struct drxk_state *state,
4199 enum EDrxkConstellation constellation,
4200 u32 symbolRate)
4201{
4202 u32 fecBitsDesired = 0; /* BER accounting period */
4203 u32 fecRsPeriodTotal = 0; /* Total period */
4204 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4205 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4206 int status = 0;
4207
4208 dprintk(1, "\n");
4209
4210 fecRsPrescale = 1;
4211 /* fecBitsDesired = symbolRate [kHz] *
4212 FrameLenght [ms] *
4213 (constellation + 1) *
4214 SyncLoss (== 1) *
4215 ViterbiLoss (==1)
4216 */
4217 switch (constellation) {
4218 case DRX_CONSTELLATION_QAM16:
4219 fecBitsDesired = 4 * symbolRate;
4220 break;
4221 case DRX_CONSTELLATION_QAM32:
4222 fecBitsDesired = 5 * symbolRate;
4223 break;
4224 case DRX_CONSTELLATION_QAM64:
4225 fecBitsDesired = 6 * symbolRate;
4226 break;
4227 case DRX_CONSTELLATION_QAM128:
4228 fecBitsDesired = 7 * symbolRate;
4229 break;
4230 case DRX_CONSTELLATION_QAM256:
4231 fecBitsDesired = 8 * symbolRate;
4232 break;
4233 default:
4234 status = -EINVAL;
4235 }
4236 if (status < 0)
4237 goto error;
4238
4239 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4240 fecBitsDesired *= 500; /* meas. period [ms] */
4241
4242 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4243 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4244 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4245
4246 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4247 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4248 if (fecRsPrescale == 0) {
4249 /* Divide by zero (though impossible) */
4250 status = -EINVAL;
4251 if (status < 0)
4252 goto error;
4253 }
4254 fecRsPeriod =
4255 ((u16) fecRsPeriodTotal +
4256 (fecRsPrescale >> 1)) / fecRsPrescale;
4257
4258 /* write corresponding registers */
4259 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4260 if (status < 0)
4261 goto error;
4262 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4263 if (status < 0)
4264 goto error;
4265 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4266error:
4267 if (status < 0)
4268 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4269 return status;
4270}
4271
4272static int SetQAM16(struct drxk_state *state)
4273{
4274 int status = 0;
4275
4276 dprintk(1, "\n");
4277 /* QAM Equalizer Setup */
4278 /* Equalizer */
4279 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4280 if (status < 0)
4281 goto error;
4282 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4283 if (status < 0)
4284 goto error;
4285 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4286 if (status < 0)
4287 goto error;
4288 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4289 if (status < 0)
4290 goto error;
4291 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4292 if (status < 0)
4293 goto error;
4294 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4295 if (status < 0)
4296 goto error;
4297 /* Decision Feedback Equalizer */
4298 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4299 if (status < 0)
4300 goto error;
4301 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4302 if (status < 0)
4303 goto error;
4304 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4305 if (status < 0)
4306 goto error;
4307 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4308 if (status < 0)
4309 goto error;
4310 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4311 if (status < 0)
4312 goto error;
4313 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4314 if (status < 0)
4315 goto error;
4316
4317 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4318 if (status < 0)
4319 goto error;
4320 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4321 if (status < 0)
4322 goto error;
4323 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4324 if (status < 0)
4325 goto error;
4326
4327 /* QAM Slicer Settings */
4328 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4329 if (status < 0)
4330 goto error;
4331
4332 /* QAM Loop Controller Coeficients */
4333 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4334 if (status < 0)
4335 goto error;
4336 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4337 if (status < 0)
4338 goto error;
4339 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4340 if (status < 0)
4341 goto error;
4342 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4343 if (status < 0)
4344 goto error;
4345 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4346 if (status < 0)
4347 goto error;
4348 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4349 if (status < 0)
4350 goto error;
4351 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4352 if (status < 0)
4353 goto error;
4354 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4355 if (status < 0)
4356 goto error;
4357
4358 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4359 if (status < 0)
4360 goto error;
4361 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4362 if (status < 0)
4363 goto error;
4364 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4365 if (status < 0)
4366 goto error;
4367 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4368 if (status < 0)
4369 goto error;
4370 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4371 if (status < 0)
4372 goto error;
4373 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4374 if (status < 0)
4375 goto error;
4376 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4377 if (status < 0)
4378 goto error;
4379 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4380 if (status < 0)
4381 goto error;
4382 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4383 if (status < 0)
4384 goto error;
4385 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4386 if (status < 0)
4387 goto error;
4388 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4389 if (status < 0)
4390 goto error;
4391 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4392 if (status < 0)
4393 goto error;
4394
4395
4396 /* QAM State Machine (FSM) Thresholds */
4397
4398 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4399 if (status < 0)
4400 goto error;
4401 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4402 if (status < 0)
4403 goto error;
4404 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4405 if (status < 0)
4406 goto error;
4407 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4408 if (status < 0)
4409 goto error;
4410 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4411 if (status < 0)
4412 goto error;
4413 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4414 if (status < 0)
4415 goto error;
4416
4417 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4418 if (status < 0)
4419 goto error;
4420 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4421 if (status < 0)
4422 goto error;
4423 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4424 if (status < 0)
4425 goto error;
4426
4427
4428 /* QAM FSM Tracking Parameters */
4429
4430 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4431 if (status < 0)
4432 goto error;
4433 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4434 if (status < 0)
4435 goto error;
4436 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4437 if (status < 0)
4438 goto error;
4439 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4440 if (status < 0)
4441 goto error;
4442 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4443 if (status < 0)
4444 goto error;
4445 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4446 if (status < 0)
4447 goto error;
4448 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4449 if (status < 0)
4450 goto error;
4451
4452error:
4453 if (status < 0)
4454 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4455 return status;
4456}
4457
4458/*============================================================================*/
4459
4460/**
4461* \brief QAM32 specific setup
4462* \param demod instance of demod.
4463* \return DRXStatus_t.
4464*/
4465static int SetQAM32(struct drxk_state *state)
4466{
4467 int status = 0;
4468
4469 dprintk(1, "\n");
4470
4471 /* QAM Equalizer Setup */
4472 /* Equalizer */
4473 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4474 if (status < 0)
4475 goto error;
4476 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4477 if (status < 0)
4478 goto error;
4479 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4480 if (status < 0)
4481 goto error;
4482 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4483 if (status < 0)
4484 goto error;
4485 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4486 if (status < 0)
4487 goto error;
4488 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4489 if (status < 0)
4490 goto error;
4491
4492 /* Decision Feedback Equalizer */
4493 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4494 if (status < 0)
4495 goto error;
4496 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4497 if (status < 0)
4498 goto error;
4499 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4500 if (status < 0)
4501 goto error;
4502 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4503 if (status < 0)
4504 goto error;
4505 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4506 if (status < 0)
4507 goto error;
4508 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4509 if (status < 0)
4510 goto error;
4511
4512 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4513 if (status < 0)
4514 goto error;
4515 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4516 if (status < 0)
4517 goto error;
4518 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4519 if (status < 0)
4520 goto error;
4521
4522 /* QAM Slicer Settings */
4523
4524 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4525 if (status < 0)
4526 goto error;
4527
4528
4529 /* QAM Loop Controller Coeficients */
4530
4531 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4532 if (status < 0)
4533 goto error;
4534 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4535 if (status < 0)
4536 goto error;
4537 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4538 if (status < 0)
4539 goto error;
4540 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4541 if (status < 0)
4542 goto error;
4543 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4544 if (status < 0)
4545 goto error;
4546 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4547 if (status < 0)
4548 goto error;
4549 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4550 if (status < 0)
4551 goto error;
4552 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4553 if (status < 0)
4554 goto error;
4555
4556 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4557 if (status < 0)
4558 goto error;
4559 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4560 if (status < 0)
4561 goto error;
4562 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4563 if (status < 0)
4564 goto error;
4565 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4566 if (status < 0)
4567 goto error;
4568 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4569 if (status < 0)
4570 goto error;
4571 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4572 if (status < 0)
4573 goto error;
4574 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4575 if (status < 0)
4576 goto error;
4577 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4578 if (status < 0)
4579 goto error;
4580 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4581 if (status < 0)
4582 goto error;
4583 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4584 if (status < 0)
4585 goto error;
4586 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4587 if (status < 0)
4588 goto error;
4589 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4590 if (status < 0)
4591 goto error;
4592
4593
4594 /* QAM State Machine (FSM) Thresholds */
4595
4596 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4597 if (status < 0)
4598 goto error;
4599 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4600 if (status < 0)
4601 goto error;
4602 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4603 if (status < 0)
4604 goto error;
4605 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4606 if (status < 0)
4607 goto error;
4608 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4609 if (status < 0)
4610 goto error;
4611 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4612 if (status < 0)
4613 goto error;
4614
4615 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4616 if (status < 0)
4617 goto error;
4618 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4619 if (status < 0)
4620 goto error;
4621 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4622 if (status < 0)
4623 goto error;
4624
4625
4626 /* QAM FSM Tracking Parameters */
4627
4628 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4629 if (status < 0)
4630 goto error;
4631 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4632 if (status < 0)
4633 goto error;
4634 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4635 if (status < 0)
4636 goto error;
4637 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4638 if (status < 0)
4639 goto error;
4640 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4641 if (status < 0)
4642 goto error;
4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4644 if (status < 0)
4645 goto error;
4646 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4647error:
4648 if (status < 0)
4649 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4650 return status;
4651}
4652
4653/*============================================================================*/
4654
4655/**
4656* \brief QAM64 specific setup
4657* \param demod instance of demod.
4658* \return DRXStatus_t.
4659*/
4660static int SetQAM64(struct drxk_state *state)
4661{
4662 int status = 0;
4663
4664 dprintk(1, "\n");
4665 /* QAM Equalizer Setup */
4666 /* Equalizer */
4667 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4668 if (status < 0)
4669 goto error;
4670 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4671 if (status < 0)
4672 goto error;
4673 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4674 if (status < 0)
4675 goto error;
4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4677 if (status < 0)
4678 goto error;
4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4680 if (status < 0)
4681 goto error;
4682 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4683 if (status < 0)
4684 goto error;
4685
4686 /* Decision Feedback Equalizer */
4687 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4688 if (status < 0)
4689 goto error;
4690 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4691 if (status < 0)
4692 goto error;
4693 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4694 if (status < 0)
4695 goto error;
4696 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4697 if (status < 0)
4698 goto error;
4699 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4700 if (status < 0)
4701 goto error;
4702 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4703 if (status < 0)
4704 goto error;
4705
4706 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4707 if (status < 0)
4708 goto error;
4709 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4710 if (status < 0)
4711 goto error;
4712 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4713 if (status < 0)
4714 goto error;
4715
4716 /* QAM Slicer Settings */
4717 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4718 if (status < 0)
4719 goto error;
4720
4721
4722 /* QAM Loop Controller Coeficients */
4723
4724 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4725 if (status < 0)
4726 goto error;
4727 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4728 if (status < 0)
4729 goto error;
4730 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4731 if (status < 0)
4732 goto error;
4733 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4734 if (status < 0)
4735 goto error;
4736 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4737 if (status < 0)
4738 goto error;
4739 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4740 if (status < 0)
4741 goto error;
4742 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4743 if (status < 0)
4744 goto error;
4745 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4746 if (status < 0)
4747 goto error;
4748
4749 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4750 if (status < 0)
4751 goto error;
4752 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4753 if (status < 0)
4754 goto error;
4755 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4756 if (status < 0)
4757 goto error;
4758 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4759 if (status < 0)
4760 goto error;
4761 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4762 if (status < 0)
4763 goto error;
4764 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4765 if (status < 0)
4766 goto error;
4767 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4768 if (status < 0)
4769 goto error;
4770 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4771 if (status < 0)
4772 goto error;
4773 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4774 if (status < 0)
4775 goto error;
4776 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4777 if (status < 0)
4778 goto error;
4779 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4780 if (status < 0)
4781 goto error;
4782 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4783 if (status < 0)
4784 goto error;
4785
4786
4787 /* QAM State Machine (FSM) Thresholds */
4788
4789 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4790 if (status < 0)
4791 goto error;
4792 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4793 if (status < 0)
4794 goto error;
4795 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4796 if (status < 0)
4797 goto error;
4798 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4799 if (status < 0)
4800 goto error;
4801 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4802 if (status < 0)
4803 goto error;
4804 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4805 if (status < 0)
4806 goto error;
4807
4808 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4809 if (status < 0)
4810 goto error;
4811 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4812 if (status < 0)
4813 goto error;
4814 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4815 if (status < 0)
4816 goto error;
4817
4818
4819 /* QAM FSM Tracking Parameters */
4820
4821 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4822 if (status < 0)
4823 goto error;
4824 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4825 if (status < 0)
4826 goto error;
4827 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4828 if (status < 0)
4829 goto error;
4830 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4831 if (status < 0)
4832 goto error;
4833 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4834 if (status < 0)
4835 goto error;
4836 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4837 if (status < 0)
4838 goto error;
4839 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4840error:
4841 if (status < 0)
4842 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4843
4844 return status;
4845}
4846
4847/*============================================================================*/
4848
4849/**
4850* \brief QAM128 specific setup
4851* \param demod: instance of demod.
4852* \return DRXStatus_t.
4853*/
4854static int SetQAM128(struct drxk_state *state)
4855{
4856 int status = 0;
4857
4858 dprintk(1, "\n");
4859 /* QAM Equalizer Setup */
4860 /* Equalizer */
4861 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4862 if (status < 0)
4863 goto error;
4864 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4865 if (status < 0)
4866 goto error;
4867 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4868 if (status < 0)
4869 goto error;
4870 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4871 if (status < 0)
4872 goto error;
4873 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4874 if (status < 0)
4875 goto error;
4876 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4877 if (status < 0)
4878 goto error;
4879
4880 /* Decision Feedback Equalizer */
4881 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4882 if (status < 0)
4883 goto error;
4884 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4885 if (status < 0)
4886 goto error;
4887 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4888 if (status < 0)
4889 goto error;
4890 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4891 if (status < 0)
4892 goto error;
4893 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4894 if (status < 0)
4895 goto error;
4896 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4897 if (status < 0)
4898 goto error;
4899
4900 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4901 if (status < 0)
4902 goto error;
4903 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4904 if (status < 0)
4905 goto error;
4906 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4907 if (status < 0)
4908 goto error;
4909
4910
4911 /* QAM Slicer Settings */
4912
4913 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4914 if (status < 0)
4915 goto error;
4916
4917
4918 /* QAM Loop Controller Coeficients */
4919
4920 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4921 if (status < 0)
4922 goto error;
4923 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4924 if (status < 0)
4925 goto error;
4926 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4927 if (status < 0)
4928 goto error;
4929 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4930 if (status < 0)
4931 goto error;
4932 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4933 if (status < 0)
4934 goto error;
4935 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4936 if (status < 0)
4937 goto error;
4938 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4939 if (status < 0)
4940 goto error;
4941 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4942 if (status < 0)
4943 goto error;
4944
4945 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4946 if (status < 0)
4947 goto error;
4948 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4949 if (status < 0)
4950 goto error;
4951 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4952 if (status < 0)
4953 goto error;
4954 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4955 if (status < 0)
4956 goto error;
4957 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4958 if (status < 0)
4959 goto error;
4960 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4961 if (status < 0)
4962 goto error;
4963 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4964 if (status < 0)
4965 goto error;
4966 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4967 if (status < 0)
4968 goto error;
4969 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4970 if (status < 0)
4971 goto error;
4972 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4973 if (status < 0)
4974 goto error;
4975 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4976 if (status < 0)
4977 goto error;
4978 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4979 if (status < 0)
4980 goto error;
4981
4982
4983 /* QAM State Machine (FSM) Thresholds */
4984
4985 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4986 if (status < 0)
4987 goto error;
4988 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4989 if (status < 0)
4990 goto error;
4991 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4992 if (status < 0)
4993 goto error;
4994 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4995 if (status < 0)
4996 goto error;
4997 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4998 if (status < 0)
4999 goto error;
5000 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5001 if (status < 0)
5002 goto error;
5003
5004 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5005 if (status < 0)
5006 goto error;
5007 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5008 if (status < 0)
5009 goto error;
5010
5011 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5012 if (status < 0)
5013 goto error;
5014
5015 /* QAM FSM Tracking Parameters */
5016
5017 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5018 if (status < 0)
5019 goto error;
5020 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5021 if (status < 0)
5022 goto error;
5023 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5024 if (status < 0)
5025 goto error;
5026 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5027 if (status < 0)
5028 goto error;
5029 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5030 if (status < 0)
5031 goto error;
5032 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5033 if (status < 0)
5034 goto error;
5035 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5036error:
5037 if (status < 0)
5038 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5039
5040 return status;
5041}
5042
5043/*============================================================================*/
5044
5045/**
5046* \brief QAM256 specific setup
5047* \param demod: instance of demod.
5048* \return DRXStatus_t.
5049*/
5050static int SetQAM256(struct drxk_state *state)
5051{
5052 int status = 0;
5053
5054 dprintk(1, "\n");
5055 /* QAM Equalizer Setup */
5056 /* Equalizer */
5057 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5058 if (status < 0)
5059 goto error;
5060 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5061 if (status < 0)
5062 goto error;
5063 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5064 if (status < 0)
5065 goto error;
5066 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5067 if (status < 0)
5068 goto error;
5069 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5070 if (status < 0)
5071 goto error;
5072 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5073 if (status < 0)
5074 goto error;
5075
5076 /* Decision Feedback Equalizer */
5077 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5078 if (status < 0)
5079 goto error;
5080 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5081 if (status < 0)
5082 goto error;
5083 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5084 if (status < 0)
5085 goto error;
5086 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5087 if (status < 0)
5088 goto error;
5089 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5090 if (status < 0)
5091 goto error;
5092 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5093 if (status < 0)
5094 goto error;
5095
5096 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5097 if (status < 0)
5098 goto error;
5099 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5100 if (status < 0)
5101 goto error;
5102 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5103 if (status < 0)
5104 goto error;
5105
5106 /* QAM Slicer Settings */
5107
5108 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5109 if (status < 0)
5110 goto error;
5111
5112
5113 /* QAM Loop Controller Coeficients */
5114
5115 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5116 if (status < 0)
5117 goto error;
5118 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5119 if (status < 0)
5120 goto error;
5121 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5122 if (status < 0)
5123 goto error;
5124 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5125 if (status < 0)
5126 goto error;
5127 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5128 if (status < 0)
5129 goto error;
5130 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5131 if (status < 0)
5132 goto error;
5133 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5134 if (status < 0)
5135 goto error;
5136 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5137 if (status < 0)
5138 goto error;
5139
5140 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5141 if (status < 0)
5142 goto error;
5143 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5144 if (status < 0)
5145 goto error;
5146 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5147 if (status < 0)
5148 goto error;
5149 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5150 if (status < 0)
5151 goto error;
5152 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5153 if (status < 0)
5154 goto error;
5155 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5156 if (status < 0)
5157 goto error;
5158 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5159 if (status < 0)
5160 goto error;
5161 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5162 if (status < 0)
5163 goto error;
5164 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5165 if (status < 0)
5166 goto error;
5167 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5168 if (status < 0)
5169 goto error;
5170 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5171 if (status < 0)
5172 goto error;
5173 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5174 if (status < 0)
5175 goto error;
5176
5177
5178 /* QAM State Machine (FSM) Thresholds */
5179
5180 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5181 if (status < 0)
5182 goto error;
5183 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5184 if (status < 0)
5185 goto error;
5186 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5187 if (status < 0)
5188 goto error;
5189 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5190 if (status < 0)
5191 goto error;
5192 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5193 if (status < 0)
5194 goto error;
5195 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5196 if (status < 0)
5197 goto error;
5198
5199 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5200 if (status < 0)
5201 goto error;
5202 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5203 if (status < 0)
5204 goto error;
5205 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5206 if (status < 0)
5207 goto error;
5208
5209
5210 /* QAM FSM Tracking Parameters */
5211
5212 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5213 if (status < 0)
5214 goto error;
5215 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5216 if (status < 0)
5217 goto error;
5218 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5219 if (status < 0)
5220 goto error;
5221 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5222 if (status < 0)
5223 goto error;
5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5225 if (status < 0)
5226 goto error;
5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5228 if (status < 0)
5229 goto error;
5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5231error:
5232 if (status < 0)
5233 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5234 return status;
5235}
5236
5237
5238/*============================================================================*/
5239/**
5240* \brief Reset QAM block.
5241* \param demod: instance of demod.
5242* \param channel: pointer to channel data.
5243* \return DRXStatus_t.
5244*/
5245static int QAMResetQAM(struct drxk_state *state)
5246{
5247 int status;
5248 u16 cmdResult;
5249
5250 dprintk(1, "\n");
5251 /* Stop QAM comstate->m_exec */
5252 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5253 if (status < 0)
5254 goto error;
5255
5256 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5257error:
5258 if (status < 0)
5259 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5260 return status;
5261}
5262
5263/*============================================================================*/
5264
5265/**
5266* \brief Set QAM symbolrate.
5267* \param demod: instance of demod.
5268* \param channel: pointer to channel data.
5269* \return DRXStatus_t.
5270*/
5271static int QAMSetSymbolrate(struct drxk_state *state)
5272{
5273 u32 adcFrequency = 0;
5274 u32 symbFreq = 0;
5275 u32 iqmRcRate = 0;
5276 u16 ratesel = 0;
5277 u32 lcSymbRate = 0;
5278 int status;
5279
5280 dprintk(1, "\n");
5281 /* Select & calculate correct IQM rate */
5282 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5283 ratesel = 0;
5284 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */
5285 if (state->param.u.qam.symbol_rate <= 1188750)
5286 ratesel = 3;
5287 else if (state->param.u.qam.symbol_rate <= 2377500)
5288 ratesel = 2;
5289 else if (state->param.u.qam.symbol_rate <= 4755000)
5290 ratesel = 1;
5291 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5292 if (status < 0)
5293 goto error;
5294
5295 /*
5296 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5297 */
5298 symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel);
5299 if (symbFreq == 0) {
5300 /* Divide by zero */
5301 status = -EINVAL;
5302 goto error;
5303 }
5304 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5305 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5306 (1 << 23);
5307 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5308 if (status < 0)
5309 goto error;
5310 state->m_iqmRcRate = iqmRcRate;
5311 /*
5312 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5313 */
5314 symbFreq = state->param.u.qam.symbol_rate;
5315 if (adcFrequency == 0) {
5316 /* Divide by zero */
5317 status = -EINVAL;
5318 goto error;
5319 }
5320 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5321 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5322 16);
5323 if (lcSymbRate > 511)
5324 lcSymbRate = 511;
5325 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5326
5327error:
5328 if (status < 0)
5329 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5330 return status;
5331}
5332
5333/*============================================================================*/
5334
5335/**
5336* \brief Get QAM lock status.
5337* \param demod: instance of demod.
5338* \param channel: pointer to channel data.
5339* \return DRXStatus_t.
5340*/
5341
5342static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5343{
5344 int status;
5345 u16 Result[2] = { 0, 0 };
5346
5347 dprintk(1, "\n");
5348 *pLockStatus = NOT_LOCKED;
5349 status = scu_command(state,
5350 SCU_RAM_COMMAND_STANDARD_QAM |
5351 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5352 Result);
5353 if (status < 0)
5354 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5355
5356 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5357 /* 0x0000 NOT LOCKED */
5358 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5359 /* 0x4000 DEMOD LOCKED */
5360 *pLockStatus = DEMOD_LOCK;
5361 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5362 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5363 *pLockStatus = MPEG_LOCK;
5364 } else {
5365 /* 0xC000 NEVER LOCKED */
5366 /* (system will never be able to lock to the signal) */
5367 /* TODO: check this, intermediate & standard specific lock states are not
5368 taken into account here */
5369 *pLockStatus = NEVER_LOCK;
5370 }
5371 return status;
5372}
5373
5374#define QAM_MIRROR__M 0x03
5375#define QAM_MIRROR_NORMAL 0x00
5376#define QAM_MIRRORED 0x01
5377#define QAM_MIRROR_AUTO_ON 0x02
5378#define QAM_LOCKRANGE__M 0x10
5379#define QAM_LOCKRANGE_NORMAL 0x10
5380
5381static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5382 s32 tunerFreqOffset)
5383{
5384 int status;
5385 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5386 u16 cmdResult;
5387
5388 dprintk(1, "\n");
5389 /*
5390 * STEP 1: reset demodulator
5391 * resets FEC DI and FEC RS
5392 * resets QAM block
5393 * resets SCU variables
5394 */
5395 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5396 if (status < 0)
5397 goto error;
5398 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5399 if (status < 0)
5400 goto error;
5401 status = QAMResetQAM(state);
5402 if (status < 0)
5403 goto error;
5404
5405 /*
5406 * STEP 2: configure demodulator
5407 * -set params; resets IQM,QAM,FEC HW; initializes some
5408 * SCU variables
5409 */
5410 status = QAMSetSymbolrate(state);
5411 if (status < 0)
5412 goto error;
5413
5414 /* Set params */
5415 switch (state->param.u.qam.modulation) {
5416 case QAM_256:
5417 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5418 break;
5419 case QAM_AUTO:
5420 case QAM_64:
5421 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5422 break;
5423 case QAM_16:
5424 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5425 break;
5426 case QAM_32:
5427 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5428 break;
5429 case QAM_128:
5430 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5431 break;
5432 default:
5433 status = -EINVAL;
5434 break;
5435 }
5436 if (status < 0)
5437 goto error;
5438 setParamParameters[0] = state->m_Constellation; /* constellation */
5439 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5440 if (state->m_OperationMode == OM_QAM_ITU_C)
5441 setParamParameters[2] = QAM_TOP_ANNEX_C;
5442 else
5443 setParamParameters[2] = QAM_TOP_ANNEX_A;
5444 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5445 /* Env parameters */
5446 /* check for LOCKRANGE Extented */
5447 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5448
5449 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5450 if (status < 0) {
5451 /* Fall-back to the simpler call */
5452 if (state->m_OperationMode == OM_QAM_ITU_C)
5453 setParamParameters[0] = QAM_TOP_ANNEX_C;
5454 else
5455 setParamParameters[0] = QAM_TOP_ANNEX_A;
5456 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5457 if (status < 0)
5458 goto error;
5459
5460 setParamParameters[0] = state->m_Constellation; /* constellation */
5461 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5462 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5463 }
5464 if (status < 0)
5465 goto error;
5466
5467 /*
5468 * STEP 3: enable the system in a mode where the ADC provides valid
5469 * signal setup constellation independent registers
5470 */
5471#if 0
5472 status = SetFrequency(channel, tunerFreqOffset));
5473 if (status < 0)
5474 goto error;
5475#endif
5476 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5477 if (status < 0)
5478 goto error;
5479
5480 /* Setup BER measurement */
5481 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate);
5482 if (status < 0)
5483 goto error;
5484
5485 /* Reset default values */
5486 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5487 if (status < 0)
5488 goto error;
5489 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5490 if (status < 0)
5491 goto error;
5492
5493 /* Reset default LC values */
5494 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5495 if (status < 0)
5496 goto error;
5497 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5498 if (status < 0)
5499 goto error;
5500 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5501 if (status < 0)
5502 goto error;
5503 status = write16(state, QAM_LC_MODE__A, 7);
5504 if (status < 0)
5505 goto error;
5506
5507 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5508 if (status < 0)
5509 goto error;
5510 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5511 if (status < 0)
5512 goto error;
5513 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5514 if (status < 0)
5515 goto error;
5516 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5517 if (status < 0)
5518 goto error;
5519 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5520 if (status < 0)
5521 goto error;
5522 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5523 if (status < 0)
5524 goto error;
5525 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5526 if (status < 0)
5527 goto error;
5528 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5529 if (status < 0)
5530 goto error;
5531 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5532 if (status < 0)
5533 goto error;
5534 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5535 if (status < 0)
5536 goto error;
5537 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5538 if (status < 0)
5539 goto error;
5540 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5541 if (status < 0)
5542 goto error;
5543 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5544 if (status < 0)
5545 goto error;
5546 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5547 if (status < 0)
5548 goto error;
5549 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5550 if (status < 0)
5551 goto error;
5552
5553 /* Mirroring, QAM-block starting point not inverted */
5554 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5555 if (status < 0)
5556 goto error;
5557
5558 /* Halt SCU to enable safe non-atomic accesses */
5559 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5560 if (status < 0)
5561 goto error;
5562
5563 /* STEP 4: constellation specific setup */
5564 switch (state->param.u.qam.modulation) {
5565 case QAM_16:
5566 status = SetQAM16(state);
5567 break;
5568 case QAM_32:
5569 status = SetQAM32(state);
5570 break;
5571 case QAM_AUTO:
5572 case QAM_64:
5573 status = SetQAM64(state);
5574 break;
5575 case QAM_128:
5576 status = SetQAM128(state);
5577 break;
5578 case QAM_256:
5579 status = SetQAM256(state);
5580 break;
5581 default:
5582 status = -EINVAL;
5583 break;
5584 }
5585 if (status < 0)
5586 goto error;
5587
5588 /* Activate SCU to enable SCU commands */
5589 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5590 if (status < 0)
5591 goto error;
5592
5593 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5594 /* extAttr->currentChannel.constellation = channel->constellation; */
5595 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5596 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5597 if (status < 0)
5598 goto error;
5599
5600 /* Start processes */
5601 status = MPEGTSStart(state);
5602 if (status < 0)
5603 goto error;
5604 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5605 if (status < 0)
5606 goto error;
5607 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5608 if (status < 0)
5609 goto error;
5610 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5611 if (status < 0)
5612 goto error;
5613
5614 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5615 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5616 if (status < 0)
5617 goto error;
5618
5619 /* update global DRXK data container */
5620/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5621
5622error:
5623 if (status < 0)
5624 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5625 return status;
5626}
5627
5628static int SetQAMStandard(struct drxk_state *state,
5629 enum OperationMode oMode)
5630{
5631 int status;
5632#ifdef DRXK_QAM_TAPS
5633#define DRXK_QAMA_TAPS_SELECT
5634#include "drxk_filters.h"
5635#undef DRXK_QAMA_TAPS_SELECT
5636#endif
5637
5638 dprintk(1, "\n");
5639
5640 /* added antenna switch */
5641 SwitchAntennaToQAM(state);
5642
5643 /* Ensure correct power-up mode */
5644 status = PowerUpQAM(state);
5645 if (status < 0)
5646 goto error;
5647 /* Reset QAM block */
5648 status = QAMResetQAM(state);
5649 if (status < 0)
5650 goto error;
5651
5652 /* Setup IQM */
5653
5654 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5655 if (status < 0)
5656 goto error;
5657 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5658 if (status < 0)
5659 goto error;
5660
5661 /* Upload IQM Channel Filter settings by
5662 boot loader from ROM table */
5663 switch (oMode) {
5664 case OM_QAM_ITU_A:
5665 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5666 break;
5667 case OM_QAM_ITU_C:
5668 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5669 if (status < 0)
5670 goto error;
5671 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5672 break;
5673 default:
5674 status = -EINVAL;
5675 }
5676 if (status < 0)
5677 goto error;
5678
5679 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5680 if (status < 0)
5681 goto error;
5682 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5683 if (status < 0)
5684 goto error;
5685 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5686 if (status < 0)
5687 goto error;
5688
5689 status = write16(state, IQM_RC_STRETCH__A, 21);
5690 if (status < 0)
5691 goto error;
5692 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5693 if (status < 0)
5694 goto error;
5695 status = write16(state, IQM_AF_CLP_TH__A, 448);
5696 if (status < 0)
5697 goto error;
5698 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5699 if (status < 0)
5700 goto error;
5701 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5702 if (status < 0)
5703 goto error;
5704
5705 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5706 if (status < 0)
5707 goto error;
5708 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5709 if (status < 0)
5710 goto error;
5711 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5712 if (status < 0)
5713 goto error;
5714 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5715 if (status < 0)
5716 goto error;
5717
5718 /* IQM Impulse Noise Processing Unit */
5719 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5720 if (status < 0)
5721 goto error;
5722 status = write16(state, IQM_CF_DATATH__A, 1000);
5723 if (status < 0)
5724 goto error;
5725 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5726 if (status < 0)
5727 goto error;
5728 status = write16(state, IQM_CF_DET_LCT__A, 0);
5729 if (status < 0)
5730 goto error;
5731 status = write16(state, IQM_CF_WND_LEN__A, 1);
5732 if (status < 0)
5733 goto error;
5734 status = write16(state, IQM_CF_PKDTH__A, 1);
5735 if (status < 0)
5736 goto error;
5737 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5738 if (status < 0)
5739 goto error;
5740
5741 /* turn on IQMAF. Must be done before setAgc**() */
5742 status = SetIqmAf(state, true);
5743 if (status < 0)
5744 goto error;
5745 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5746 if (status < 0)
5747 goto error;
5748
5749 /* IQM will not be reset from here, sync ADC and update/init AGC */
5750 status = ADCSynchronization(state);
5751 if (status < 0)
5752 goto error;
5753
5754 /* Set the FSM step period */
5755 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5756 if (status < 0)
5757 goto error;
5758
5759 /* Halt SCU to enable safe non-atomic accesses */
5760 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5761 if (status < 0)
5762 goto error;
5763
5764 /* No more resets of the IQM, current standard correctly set =>
5765 now AGCs can be configured. */
5766
5767 status = InitAGC(state, true);
5768 if (status < 0)
5769 goto error;
5770 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5771 if (status < 0)
5772 goto error;
5773
5774 /* Configure AGC's */
5775 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5776 if (status < 0)
5777 goto error;
5778 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5779 if (status < 0)
5780 goto error;
5781
5782 /* Activate SCU to enable SCU commands */
5783 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5784error:
5785 if (status < 0)
5786 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5787 return status;
5788}
5789
5790static int WriteGPIO(struct drxk_state *state)
5791{
5792 int status;
5793 u16 value = 0;
5794
5795 dprintk(1, "\n");
5796 /* stop lock indicator process */
5797 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5798 if (status < 0)
5799 goto error;
5800
5801 /* Write magic word to enable pdr reg write */
5802 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5803 if (status < 0)
5804 goto error;
5805
5806 if (state->m_hasSAWSW) {
5807 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5808 /* write to io pad configuration register - output mode */
5809 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5810 if (status < 0)
5811 goto error;
5812
5813 /* use corresponding bit in io data output registar */
5814 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5815 if (status < 0)
5816 goto error;
5817 if ((state->m_GPIO & 0x0001) == 0)
5818 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5819 else
5820 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5821 /* write back to io data output register */
5822 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5823 if (status < 0)
5824 goto error;
5825 }
5826 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5827 /* write to io pad configuration register - output mode */
5828 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5829 if (status < 0)
5830 goto error;
5831
5832 /* use corresponding bit in io data output registar */
5833 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5834 if (status < 0)
5835 goto error;
5836 if ((state->m_GPIO & 0x0002) == 0)
5837 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5838 else
5839 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5840 /* write back to io data output register */
5841 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5842 if (status < 0)
5843 goto error;
5844 }
5845 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5846 /* write to io pad configuration register - output mode */
5847 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5848 if (status < 0)
5849 goto error;
5850
5851 /* use corresponding bit in io data output registar */
5852 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5853 if (status < 0)
5854 goto error;
5855 if ((state->m_GPIO & 0x0004) == 0)
5856 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5857 else
5858 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5859 /* write back to io data output register */
5860 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5861 if (status < 0)
5862 goto error;
5863 }
5864 }
5865 /* Write magic word to disable pdr reg write */
5866 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5867error:
5868 if (status < 0)
5869 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5870 return status;
5871}
5872
5873static int SwitchAntennaToQAM(struct drxk_state *state)
5874{
5875 int status = 0;
5876 bool gpio_state;
5877
5878 dprintk(1, "\n");
5879
5880 if (!state->antenna_gpio)
5881 return 0;
5882
5883 gpio_state = state->m_GPIO & state->antenna_gpio;
5884
5885 if (state->antenna_dvbt ^ gpio_state) {
5886 /* Antenna is on DVB-T mode. Switch */
5887 if (state->antenna_dvbt)
5888 state->m_GPIO &= ~state->antenna_gpio;
5889 else
5890 state->m_GPIO |= state->antenna_gpio;
5891 status = WriteGPIO(state);
5892 }
5893 if (status < 0)
5894 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5895 return status;
5896}
5897
5898static int SwitchAntennaToDVBT(struct drxk_state *state)
5899{
5900 int status = 0;
5901 bool gpio_state;
5902
5903 dprintk(1, "\n");
5904
5905 if (!state->antenna_gpio)
5906 return 0;
5907
5908 gpio_state = state->m_GPIO & state->antenna_gpio;
5909
5910 if (!(state->antenna_dvbt ^ gpio_state)) {
5911 /* Antenna is on DVB-C mode. Switch */
5912 if (state->antenna_dvbt)
5913 state->m_GPIO |= state->antenna_gpio;
5914 else
5915 state->m_GPIO &= ~state->antenna_gpio;
5916 status = WriteGPIO(state);
5917 }
5918 if (status < 0)
5919 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5920 return status;
5921}
5922
5923
5924static int PowerDownDevice(struct drxk_state *state)
5925{
5926 /* Power down to requested mode */
5927 /* Backup some register settings */
5928 /* Set pins with possible pull-ups connected to them in input mode */
5929 /* Analog power down */
5930 /* ADC power down */
5931 /* Power down device */
5932 int status;
5933
5934 dprintk(1, "\n");
5935 if (state->m_bPDownOpenBridge) {
5936 /* Open I2C bridge before power down of DRXK */
5937 status = ConfigureI2CBridge(state, true);
5938 if (status < 0)
5939 goto error;
5940 }
5941 /* driver 0.9.0 */
5942 status = DVBTEnableOFDMTokenRing(state, false);
5943 if (status < 0)
5944 goto error;
5945
5946 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5947 if (status < 0)
5948 goto error;
5949 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5950 if (status < 0)
5951 goto error;
5952 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5953 status = HI_CfgCommand(state);
5954error:
5955 if (status < 0)
5956 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5957
5958 return status;
5959}
5960
5961static int load_microcode(struct drxk_state *state, const char *mc_name)
5962{
5963 const struct firmware *fw = NULL;
5964 int err = 0;
5965
5966 dprintk(1, "\n");
5967
5968 err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5969 if (err < 0) {
5970 printk(KERN_ERR
5971 "drxk: Could not load firmware file %s.\n", mc_name);
5972 printk(KERN_INFO
5973 "drxk: Copy %s to your hotplug directory!\n", mc_name);
5974 return err;
5975 }
5976 err = DownloadMicrocode(state, fw->data, fw->size);
5977 release_firmware(fw);
5978 return err;
5979}
5980
5981static int init_drxk(struct drxk_state *state)
5982{
5983 int status = 0;
5984 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5985 u16 driverVersion;
5986
5987 dprintk(1, "\n");
5988 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5989 status = PowerUpDevice(state);
5990 if (status < 0)
5991 goto error;
5992 status = DRXX_Open(state);
5993 if (status < 0)
5994 goto error;
5995 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5996 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5997 if (status < 0)
5998 goto error;
5999 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6000 if (status < 0)
6001 goto error;
6002 /* TODO is this needed, if yes how much delay in worst case scenario */
6003 msleep(1);
6004 state->m_DRXK_A3_PATCH_CODE = true;
6005 status = GetDeviceCapabilities(state);
6006 if (status < 0)
6007 goto error;
6008
6009 /* Bridge delay, uses oscilator clock */
6010 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6011 /* SDA brdige delay */
6012 state->m_HICfgBridgeDelay =
6013 (u16) ((state->m_oscClockFreq / 1000) *
6014 HI_I2C_BRIDGE_DELAY) / 1000;
6015 /* Clipping */
6016 if (state->m_HICfgBridgeDelay >
6017 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6018 state->m_HICfgBridgeDelay =
6019 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6020 }
6021 /* SCL bridge delay, same as SDA for now */
6022 state->m_HICfgBridgeDelay +=
6023 state->m_HICfgBridgeDelay <<
6024 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6025
6026 status = InitHI(state);
6027 if (status < 0)
6028 goto error;
6029 /* disable various processes */
6030#if NOA1ROM
6031 if (!(state->m_DRXK_A1_ROM_CODE)
6032 && !(state->m_DRXK_A2_ROM_CODE))
6033#endif
6034 {
6035 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6036 if (status < 0)
6037 goto error;
6038 }
6039
6040 /* disable MPEG port */
6041 status = MPEGTSDisable(state);
6042 if (status < 0)
6043 goto error;
6044
6045 /* Stop AUD and SCU */
6046 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6047 if (status < 0)
6048 goto error;
6049 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6050 if (status < 0)
6051 goto error;
6052
6053 /* enable token-ring bus through OFDM block for possible ucode upload */
6054 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6055 if (status < 0)
6056 goto error;
6057
6058 /* include boot loader section */
6059 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6060 if (status < 0)
6061 goto error;
6062 status = BLChainCmd(state, 0, 6, 100);
6063 if (status < 0)
6064 goto error;
6065
6066 if (!state->microcode_name)
6067 load_microcode(state, "drxk_a3.mc");
6068 else
6069 load_microcode(state, state->microcode_name);
6070
6071 /* disable token-ring bus through OFDM block for possible ucode upload */
6072 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6073 if (status < 0)
6074 goto error;
6075
6076 /* Run SCU for a little while to initialize microcode version numbers */
6077 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6078 if (status < 0)
6079 goto error;
6080 status = DRXX_Open(state);
6081 if (status < 0)
6082 goto error;
6083 /* added for test */
6084 msleep(30);
6085
6086 powerMode = DRXK_POWER_DOWN_OFDM;
6087 status = CtrlPowerMode(state, &powerMode);
6088 if (status < 0)
6089 goto error;
6090
6091 /* Stamp driver version number in SCU data RAM in BCD code
6092 Done to enable field application engineers to retreive drxdriver version
6093 via I2C from SCU RAM.
6094 Not using SCU command interface for SCU register access since no
6095 microcode may be present.
6096 */
6097 driverVersion =
6098 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6099 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6100 ((DRXK_VERSION_MAJOR % 10) << 4) +
6101 (DRXK_VERSION_MINOR % 10);
6102 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6103 if (status < 0)
6104 goto error;
6105 driverVersion =
6106 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6107 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6108 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6109 (DRXK_VERSION_PATCH % 10);
6110 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6111 if (status < 0)
6112 goto error;
6113
6114 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6115 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6116 DRXK_VERSION_PATCH);
6117
6118 /* Dirty fix of default values for ROM/PATCH microcode
6119 Dirty because this fix makes it impossible to setup suitable values
6120 before calling DRX_Open. This solution requires changes to RF AGC speed
6121 to be done via the CTRL function after calling DRX_Open */
6122
6123 /* m_dvbtRfAgcCfg.speed = 3; */
6124
6125 /* Reset driver debug flags to 0 */
6126 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6127 if (status < 0)
6128 goto error;
6129 /* driver 0.9.0 */
6130 /* Setup FEC OC:
6131 NOTE: No more full FEC resets allowed afterwards!! */
6132 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6133 if (status < 0)
6134 goto error;
6135 /* MPEGTS functions are still the same */
6136 status = MPEGTSDtoInit(state);
6137 if (status < 0)
6138 goto error;
6139 status = MPEGTSStop(state);
6140 if (status < 0)
6141 goto error;
6142 status = MPEGTSConfigurePolarity(state);
6143 if (status < 0)
6144 goto error;
6145 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6146 if (status < 0)
6147 goto error;
6148 /* added: configure GPIO */
6149 status = WriteGPIO(state);
6150 if (status < 0)
6151 goto error;
6152
6153 state->m_DrxkState = DRXK_STOPPED;
6154
6155 if (state->m_bPowerDown) {
6156 status = PowerDownDevice(state);
6157 if (status < 0)
6158 goto error;
6159 state->m_DrxkState = DRXK_POWERED_DOWN;
6160 } else
6161 state->m_DrxkState = DRXK_STOPPED;
6162 }
6163error:
6164 if (status < 0)
6165 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6166
6167 return status;
6168}
6169
6170static void drxk_c_release(struct dvb_frontend *fe)
6171{
6172 struct drxk_state *state = fe->demodulator_priv;
6173
6174 dprintk(1, "\n");
6175 kfree(state);
6176}
6177
6178static int drxk_c_init(struct dvb_frontend *fe)
6179{
6180 struct drxk_state *state = fe->demodulator_priv;
6181
6182 dprintk(1, "\n");
6183 if (mutex_trylock(&state->ctlock) == 0)
6184 return -EBUSY;
6185 SetOperationMode(state, OM_QAM_ITU_A);
6186 return 0;
6187}
6188
6189static int drxk_c_sleep(struct dvb_frontend *fe)
6190{
6191 struct drxk_state *state = fe->demodulator_priv;
6192
6193 dprintk(1, "\n");
6194 ShutDown(state);
6195 mutex_unlock(&state->ctlock);
6196 return 0;
6197}
6198
6199static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6200{
6201 struct drxk_state *state = fe->demodulator_priv;
6202
6203 dprintk(1, "%s\n", enable ? "enable" : "disable");
6204 return ConfigureI2CBridge(state, enable ? true : false);
6205}
6206
6207static int drxk_set_parameters(struct dvb_frontend *fe,
6208 struct dvb_frontend_parameters *p)
6209{
6210 struct drxk_state *state = fe->demodulator_priv;
6211 u32 IF;
6212
6213 dprintk(1, "\n");
6214 if (fe->ops.i2c_gate_ctrl)
6215 fe->ops.i2c_gate_ctrl(fe, 1);
6216 if (fe->ops.tuner_ops.set_params)
6217 fe->ops.tuner_ops.set_params(fe, p);
6218 if (fe->ops.i2c_gate_ctrl)
6219 fe->ops.i2c_gate_ctrl(fe, 0);
6220 state->param = *p;
6221 fe->ops.tuner_ops.get_frequency(fe, &IF);
6222 Start(state, 0, IF);
6223
6224 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6225
6226 return 0;
6227}
6228
6229static int drxk_c_get_frontend(struct dvb_frontend *fe,
6230 struct dvb_frontend_parameters *p)
6231{
6232 dprintk(1, "\n");
6233 return 0;
6234}
6235
6236static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6237{
6238 struct drxk_state *state = fe->demodulator_priv;
6239 u32 stat;
6240
6241 dprintk(1, "\n");
6242 *status = 0;
6243 GetLockStatus(state, &stat, 0);
6244 if (stat == MPEG_LOCK)
6245 *status |= 0x1f;
6246 if (stat == FEC_LOCK)
6247 *status |= 0x0f;
6248 if (stat == DEMOD_LOCK)
6249 *status |= 0x07;
6250 return 0;
6251}
6252
6253static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6254{
6255 dprintk(1, "\n");
6256
6257 *ber = 0;
6258 return 0;
6259}
6260
6261static int drxk_read_signal_strength(struct dvb_frontend *fe,
6262 u16 *strength)
6263{
6264 struct drxk_state *state = fe->demodulator_priv;
6265 u32 val = 0;
6266
6267 dprintk(1, "\n");
6268 ReadIFAgc(state, &val);
6269 *strength = val & 0xffff;
6270 return 0;
6271}
6272
6273static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6274{
6275 struct drxk_state *state = fe->demodulator_priv;
6276 s32 snr2;
6277
6278 dprintk(1, "\n");
6279 GetSignalToNoise(state, &snr2);
6280 *snr = snr2 & 0xffff;
6281 return 0;
6282}
6283
6284static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6285{
6286 struct drxk_state *state = fe->demodulator_priv;
6287 u16 err;
6288
6289 dprintk(1, "\n");
6290 DVBTQAMGetAccPktErr(state, &err);
6291 *ucblocks = (u32) err;
6292 return 0;
6293}
6294
6295static int drxk_c_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6296 *sets)
6297{
6298 dprintk(1, "\n");
6299 sets->min_delay_ms = 3000;
6300 sets->max_drift = 0;
6301 sets->step_size = 0;
6302 return 0;
6303}
6304
6305static void drxk_t_release(struct dvb_frontend *fe)
6306{
6307 /*
6308 * There's nothing to release here, as the state struct
6309 * is already freed by drxk_c_release.
6310 */
6311}
6312
6313static int drxk_t_init(struct dvb_frontend *fe)
6314{
6315 struct drxk_state *state = fe->demodulator_priv;
6316
6317 dprintk(1, "\n");
6318 if (mutex_trylock(&state->ctlock) == 0)
6319 return -EBUSY;
6320 SetOperationMode(state, OM_DVBT);
6321 return 0;
6322}
6323
6324static int drxk_t_sleep(struct dvb_frontend *fe)
6325{
6326 struct drxk_state *state = fe->demodulator_priv;
6327
6328 dprintk(1, "\n");
6329 mutex_unlock(&state->ctlock);
6330 return 0;
6331}
6332
6333static int drxk_t_get_frontend(struct dvb_frontend *fe,
6334 struct dvb_frontend_parameters *p)
6335{
6336 dprintk(1, "\n");
6337
6338 return 0;
6339}
6340
6341static struct dvb_frontend_ops drxk_c_ops = {
6342 .info = {
6343 .name = "DRXK DVB-C",
6344 .type = FE_QAM,
6345 .frequency_stepsize = 62500,
6346 .frequency_min = 47000000,
6347 .frequency_max = 862000000,
6348 .symbol_rate_min = 870000,
6349 .symbol_rate_max = 11700000,
6350 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6351 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
6352 .release = drxk_c_release,
6353 .init = drxk_c_init,
6354 .sleep = drxk_c_sleep,
6355 .i2c_gate_ctrl = drxk_gate_ctrl,
6356
6357 .set_frontend = drxk_set_parameters,
6358 .get_frontend = drxk_c_get_frontend,
6359 .get_tune_settings = drxk_c_get_tune_settings,
6360
6361 .read_status = drxk_read_status,
6362 .read_ber = drxk_read_ber,
6363 .read_signal_strength = drxk_read_signal_strength,
6364 .read_snr = drxk_read_snr,
6365 .read_ucblocks = drxk_read_ucblocks,
6366};
6367
6368static struct dvb_frontend_ops drxk_t_ops = {
6369 .info = {
6370 .name = "DRXK DVB-T",
6371 .type = FE_OFDM,
6372 .frequency_min = 47125000,
6373 .frequency_max = 865000000,
6374 .frequency_stepsize = 166667,
6375 .frequency_tolerance = 0,
6376 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
6377 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
6378 FE_CAN_FEC_AUTO |
6379 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
6380 FE_CAN_QAM_AUTO |
6381 FE_CAN_TRANSMISSION_MODE_AUTO |
6382 FE_CAN_GUARD_INTERVAL_AUTO |
6383 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
6384 .release = drxk_t_release,
6385 .init = drxk_t_init,
6386 .sleep = drxk_t_sleep,
6387 .i2c_gate_ctrl = drxk_gate_ctrl,
6388
6389 .set_frontend = drxk_set_parameters,
6390 .get_frontend = drxk_t_get_frontend,
6391
6392 .read_status = drxk_read_status,
6393 .read_ber = drxk_read_ber,
6394 .read_signal_strength = drxk_read_signal_strength,
6395 .read_snr = drxk_read_snr,
6396 .read_ucblocks = drxk_read_ucblocks,
6397};
6398
6399struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6400 struct i2c_adapter *i2c,
6401 struct dvb_frontend **fe_t)
6402{
6403 struct drxk_state *state = NULL;
6404 u8 adr = config->adr;
6405
6406 dprintk(1, "\n");
6407 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6408 if (!state)
6409 return NULL;
6410
6411 state->i2c = i2c;
6412 state->demod_address = adr;
6413 state->single_master = config->single_master;
6414 state->microcode_name = config->microcode_name;
6415 state->no_i2c_bridge = config->no_i2c_bridge;
6416 state->antenna_gpio = config->antenna_gpio;
6417 state->antenna_dvbt = config->antenna_dvbt;
6418
6419 /* NOTE: as more UIO bits will be used, add them to the mask */
6420 state->UIO_mask = config->antenna_gpio;
6421
6422 /* Default gpio to DVB-C */
6423 if (!state->antenna_dvbt && state->antenna_gpio)
6424 state->m_GPIO |= state->antenna_gpio;
6425 else
6426 state->m_GPIO &= ~state->antenna_gpio;
6427
6428 mutex_init(&state->mutex);
6429 mutex_init(&state->ctlock);
6430
6431 memcpy(&state->c_frontend.ops, &drxk_c_ops,
6432 sizeof(struct dvb_frontend_ops));
6433 memcpy(&state->t_frontend.ops, &drxk_t_ops,
6434 sizeof(struct dvb_frontend_ops));
6435 state->c_frontend.demodulator_priv = state;
6436 state->t_frontend.demodulator_priv = state;
6437
6438 init_state(state);
6439 if (init_drxk(state) < 0)
6440 goto error;
6441 *fe_t = &state->t_frontend;
6442
6443 return &state->c_frontend;
6444
6445error:
6446 printk(KERN_ERR "drxk: not found\n");
6447 kfree(state);
6448 return NULL;
6449}
6450EXPORT_SYMBOL(drxk_attach);
6451
6452MODULE_DESCRIPTION("DRX-K driver");
6453MODULE_AUTHOR("Ralph Metzler");
6454MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 10:31:41 -0400