diff options
Diffstat (limited to 'drivers/media/dvb/frontends/dib8000.c')
-rw-r--r-- | drivers/media/dvb/frontends/dib8000.c | 163 |
1 files changed, 84 insertions, 79 deletions
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c index 625e4210d2d..3961fed9da6 100644 --- a/drivers/media/dvb/frontends/dib8000.c +++ b/drivers/media/dvb/frontends/dib8000.c | |||
@@ -261,7 +261,8 @@ static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode) | |||
261 | fifo_threshold = 1792; | 261 | fifo_threshold = 1792; |
262 | smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); | 262 | smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); |
263 | 263 | ||
264 | dprintk("-I- Setting output mode for demod %p to %d", &state->fe[0], mode); | 264 | dprintk("-I- Setting output mode for demod %p to %d", |
265 | &state->fe[0], mode); | ||
265 | 266 | ||
266 | switch (mode) { | 267 | switch (mode) { |
267 | case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock | 268 | case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock |
@@ -295,7 +296,8 @@ static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode) | |||
295 | break; | 296 | break; |
296 | 297 | ||
297 | default: | 298 | default: |
298 | dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]); | 299 | dprintk("Unhandled output_mode passed to be set for demod %p", |
300 | &state->fe[0]); | ||
299 | return -EINVAL; | 301 | return -EINVAL; |
300 | } | 302 | } |
301 | 303 | ||
@@ -345,7 +347,8 @@ static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_pow | |||
345 | { | 347 | { |
346 | /* by default everything is going to be powered off */ | 348 | /* by default everything is going to be powered off */ |
347 | u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff, | 349 | u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff, |
348 | reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; | 350 | reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, |
351 | reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; | ||
349 | 352 | ||
350 | /* now, depending on the requested mode, we power on */ | 353 | /* now, depending on the requested mode, we power on */ |
351 | switch (mode) { | 354 | switch (mode) { |
@@ -482,7 +485,8 @@ static void dib8000_reset_pll(struct dib8000_state *state) | |||
482 | 485 | ||
483 | // clk_cfg1 | 486 | // clk_cfg1 |
484 | clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | | 487 | clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | |
485 | (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | (pll->pll_range << 1) | (pll->pll_reset << 0); | 488 | (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | |
489 | (pll->pll_range << 1) | (pll->pll_reset << 0); | ||
486 | 490 | ||
487 | dib8000_write_word(state, 902, clk_cfg1); | 491 | dib8000_write_word(state, 902, clk_cfg1); |
488 | clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); | 492 | clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); |
@@ -492,11 +496,12 @@ static void dib8000_reset_pll(struct dib8000_state *state) | |||
492 | 496 | ||
493 | /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */ | 497 | /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */ |
494 | if (state->cfg.pll->ADClkSrc == 0) | 498 | if (state->cfg.pll->ADClkSrc == 0) |
495 | dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); | 499 | dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | |
500 | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); | ||
496 | else if (state->cfg.refclksel != 0) | 501 | else if (state->cfg.refclksel != 0) |
497 | dib8000_write_word(state, 904, | 502 | dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | |
498 | (0 << 15) | (1 << 12) | ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | (pll-> | 503 | ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | |
499 | ADClkSrc << 7) | (0 << 1)); | 504 | (pll->ADClkSrc << 7) | (0 << 1)); |
500 | else | 505 | else |
501 | dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); | 506 | dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); |
502 | 507 | ||
@@ -627,14 +632,14 @@ static const u16 dib8000_defaults[] = { | |||
627 | 1, 285, | 632 | 1, 285, |
628 | 0x0020, //p_fec_ | 633 | 0x0020, //p_fec_ |
629 | 1, 299, | 634 | 1, 299, |
630 | 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard | 635 | 0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */ |
631 | 636 | ||
632 | 1, 338, | 637 | 1, 338, |
633 | (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1 | 638 | (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1 |
634 | (1 << 10) | // P_ctrl_pre_freq_mode_sat=1 | 639 | (1 << 10) | |
635 | (0 << 9) | // P_ctrl_pre_freq_inh=0 | 640 | (0 << 9) | /* P_ctrl_pre_freq_inh=0 */ |
636 | (3 << 5) | // P_ctrl_pre_freq_step=3 | 641 | (3 << 5) | /* P_ctrl_pre_freq_step=3 */ |
637 | (1 << 0), // P_pre_freq_win_len=1 | 642 | (1 << 0), /* P_pre_freq_win_len=1 */ |
638 | 643 | ||
639 | 1, 903, | 644 | 1, 903, |
640 | (0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW) | 645 | (0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW) |
@@ -782,7 +787,7 @@ static int dib8000_update_lna(struct dib8000_state *state) | |||
782 | // read dyn_gain here (because it is demod-dependent and not tuner) | 787 | // read dyn_gain here (because it is demod-dependent and not tuner) |
783 | dyn_gain = dib8000_read_word(state, 390); | 788 | dyn_gain = dib8000_read_word(state, 390); |
784 | 789 | ||
785 | if (state->cfg.update_lna(state->fe[0], dyn_gain)) { // LNA has changed | 790 | if (state->cfg.update_lna(state->fe[0], dyn_gain)) { |
786 | dib8000_restart_agc(state); | 791 | dib8000_restart_agc(state); |
787 | return 1; | 792 | return 1; |
788 | } | 793 | } |
@@ -869,7 +874,8 @@ static int dib8000_agc_soft_split(struct dib8000_state *state) | |||
869 | split_offset = state->current_agc->split.max; | 874 | split_offset = state->current_agc->split.max; |
870 | else | 875 | else |
871 | split_offset = state->current_agc->split.max * | 876 | split_offset = state->current_agc->split.max * |
872 | (agc - state->current_agc->split.min_thres) / (state->current_agc->split.max_thres - state->current_agc->split.min_thres); | 877 | (agc - state->current_agc->split.min_thres) / |
878 | (state->current_agc->split.max_thres - state->current_agc->split.min_thres); | ||
873 | 879 | ||
874 | dprintk("AGC split_offset: %d", split_offset); | 880 | dprintk("AGC split_offset: %d", split_offset); |
875 | 881 | ||
@@ -952,14 +958,13 @@ s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode) | |||
952 | s32 val; | 958 | s32 val; |
953 | 959 | ||
954 | val = dib8000_read32(state, 384); | 960 | val = dib8000_read32(state, 384); |
955 | /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */ | ||
956 | if (mode) { | 961 | if (mode) { |
957 | tmp_val = val; | 962 | tmp_val = val; |
958 | while (tmp_val >>= 1) | 963 | while (tmp_val >>= 1) |
959 | exp++; | 964 | exp++; |
960 | mant = (val * 1000 / (1<<exp)); | 965 | mant = (val * 1000 / (1<<exp)); |
961 | ix = (u8)((mant-1000)/100); /* index of the LUT */ | 966 | ix = (u8)((mant-1000)/100); /* index of the LUT */ |
962 | val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */ | 967 | val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); |
963 | val = (val*256)/1000; | 968 | val = (val*256)/1000; |
964 | } | 969 | } |
965 | return val; | 970 | return val; |
@@ -1006,18 +1011,19 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1006 | dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); | 1011 | dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); |
1007 | 1012 | ||
1008 | i = dib8000_read_word(state, 26) & 1; // P_dds_invspec | 1013 | i = dib8000_read_word(state, 26) & 1; // P_dds_invspec |
1009 | dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion ^ i); | 1014 | dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i); |
1010 | 1015 | ||
1011 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) { | 1016 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) { |
1012 | //compute new dds_freq for the seg and adjust prbs | 1017 | //compute new dds_freq for the seg and adjust prbs |
1013 | int seg_offset = | 1018 | int seg_offset = |
1014 | state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx - (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) - | 1019 | state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx - |
1020 | (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) - | ||
1015 | (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2); | 1021 | (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2); |
1016 | int clk = state->cfg.pll->internal; | 1022 | int clk = state->cfg.pll->internal; |
1017 | u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26) | 1023 | u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26) |
1018 | int dds_offset = seg_offset * segtodds; | 1024 | int dds_offset = seg_offset * segtodds; |
1019 | int new_dds, sub_channel; | 1025 | int new_dds, sub_channel; |
1020 | if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) // if even | 1026 | if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) |
1021 | dds_offset -= (int)(segtodds / 2); | 1027 | dds_offset -= (int)(segtodds / 2); |
1022 | 1028 | ||
1023 | if (state->cfg.pll->ifreq == 0) { | 1029 | if (state->cfg.pll->ifreq == 0) { |
@@ -1031,7 +1037,8 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1031 | // - the segment of center frequency with an odd total number of segments | 1037 | // - the segment of center frequency with an odd total number of segments |
1032 | // - the segment to the left of center frequency with an even total number of segments | 1038 | // - the segment to the left of center frequency with an even total number of segments |
1033 | // - the segment to the right of center frequency with an even total number of segments | 1039 | // - the segment to the right of center frequency with an even total number of segments |
1034 | if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT) && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) | 1040 | if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT) |
1041 | && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) | ||
1035 | && (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) | 1042 | && (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) |
1036 | && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == | 1043 | && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == |
1037 | ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) | 1044 | ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) |
@@ -1051,9 +1058,9 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1051 | } | 1058 | } |
1052 | dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff)); | 1059 | dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff)); |
1053 | dib8000_write_word(state, 28, (u16) (new_dds & 0xffff)); | 1060 | dib8000_write_word(state, 28, (u16) (new_dds & 0xffff)); |
1054 | if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) // if odd | 1061 | if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) |
1055 | sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3; | 1062 | sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3; |
1056 | else // if even | 1063 | else |
1057 | sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3; | 1064 | sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3; |
1058 | sub_channel -= 6; | 1065 | sub_channel -= 6; |
1059 | 1066 | ||
@@ -1212,7 +1219,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1212 | } | 1219 | } |
1213 | break; | 1220 | break; |
1214 | } | 1221 | } |
1215 | } else { // if not state->fe[0]->dtv_property_cache.isdbt_sb_mode | 1222 | } else { |
1216 | dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff)); | 1223 | dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff)); |
1217 | dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff)); | 1224 | dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff)); |
1218 | dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003)); | 1225 | dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003)); |
@@ -1332,8 +1339,8 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1332 | state->differential_constellation = (seg_diff_mask != 0); | 1339 | state->differential_constellation = (seg_diff_mask != 0); |
1333 | dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); | 1340 | dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); |
1334 | 1341 | ||
1335 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb | 1342 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1336 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1) // 3-segments | 1343 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1) |
1337 | seg_mask13 = 0x00E0; | 1344 | seg_mask13 = 0x00E0; |
1338 | else // 1-segment | 1345 | else // 1-segment |
1339 | seg_mask13 = 0x0040; | 1346 | seg_mask13 = 0x0040; |
@@ -1355,25 +1362,24 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1355 | dib8000_write_word(state, 353, seg_mask13); // ADDR 353 | 1362 | dib8000_write_word(state, 353, seg_mask13); // ADDR 353 |
1356 | 1363 | ||
1357 | /* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */ | 1364 | /* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */ |
1358 | // dib8000_write_word(state, 351, (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5 ); | ||
1359 | 1365 | ||
1360 | // ---- SMALL ---- | 1366 | // ---- SMALL ---- |
1361 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { | 1367 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1362 | switch (state->fe[0]->dtv_property_cache.transmission_mode) { | 1368 | switch (state->fe[0]->dtv_property_cache.transmission_mode) { |
1363 | case TRANSMISSION_MODE_2K: | 1369 | case TRANSMISSION_MODE_2K: |
1364 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg | 1370 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { |
1365 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK | 1371 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) |
1366 | ncoeff = coeff_2k_sb_1seg_dqpsk; | 1372 | ncoeff = coeff_2k_sb_1seg_dqpsk; |
1367 | else // QPSK or QAM | 1373 | else // QPSK or QAM |
1368 | ncoeff = coeff_2k_sb_1seg; | 1374 | ncoeff = coeff_2k_sb_1seg; |
1369 | } else { // 3-segments | 1375 | } else { // 3-segments |
1370 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment | 1376 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { |
1371 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments | 1377 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) |
1372 | ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk; | 1378 | ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk; |
1373 | else // QPSK or QAM on external segments | 1379 | else // QPSK or QAM on external segments |
1374 | ncoeff = coeff_2k_sb_3seg_0dqpsk; | 1380 | ncoeff = coeff_2k_sb_3seg_0dqpsk; |
1375 | } else { // QPSK or QAM on central segment | 1381 | } else { // QPSK or QAM on central segment |
1376 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments | 1382 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) |
1377 | ncoeff = coeff_2k_sb_3seg_1dqpsk; | 1383 | ncoeff = coeff_2k_sb_3seg_1dqpsk; |
1378 | else // QPSK or QAM on external segments | 1384 | else // QPSK or QAM on external segments |
1379 | ncoeff = coeff_2k_sb_3seg; | 1385 | ncoeff = coeff_2k_sb_3seg; |
@@ -1382,20 +1388,20 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1382 | break; | 1388 | break; |
1383 | 1389 | ||
1384 | case TRANSMISSION_MODE_4K: | 1390 | case TRANSMISSION_MODE_4K: |
1385 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg | 1391 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { |
1386 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK | 1392 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) |
1387 | ncoeff = coeff_4k_sb_1seg_dqpsk; | 1393 | ncoeff = coeff_4k_sb_1seg_dqpsk; |
1388 | else // QPSK or QAM | 1394 | else // QPSK or QAM |
1389 | ncoeff = coeff_4k_sb_1seg; | 1395 | ncoeff = coeff_4k_sb_1seg; |
1390 | } else { // 3-segments | 1396 | } else { // 3-segments |
1391 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment | 1397 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { |
1392 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments | 1398 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { |
1393 | ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk; | 1399 | ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk; |
1394 | } else { // QPSK or QAM on external segments | 1400 | } else { // QPSK or QAM on external segments |
1395 | ncoeff = coeff_4k_sb_3seg_0dqpsk; | 1401 | ncoeff = coeff_4k_sb_3seg_0dqpsk; |
1396 | } | 1402 | } |
1397 | } else { // QPSK or QAM on central segment | 1403 | } else { // QPSK or QAM on central segment |
1398 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments | 1404 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { |
1399 | ncoeff = coeff_4k_sb_3seg_1dqpsk; | 1405 | ncoeff = coeff_4k_sb_3seg_1dqpsk; |
1400 | } else // QPSK or QAM on external segments | 1406 | } else // QPSK or QAM on external segments |
1401 | ncoeff = coeff_4k_sb_3seg; | 1407 | ncoeff = coeff_4k_sb_3seg; |
@@ -1406,20 +1412,20 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1406 | case TRANSMISSION_MODE_AUTO: | 1412 | case TRANSMISSION_MODE_AUTO: |
1407 | case TRANSMISSION_MODE_8K: | 1413 | case TRANSMISSION_MODE_8K: |
1408 | default: | 1414 | default: |
1409 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg | 1415 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { |
1410 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK | 1416 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) |
1411 | ncoeff = coeff_8k_sb_1seg_dqpsk; | 1417 | ncoeff = coeff_8k_sb_1seg_dqpsk; |
1412 | else // QPSK or QAM | 1418 | else // QPSK or QAM |
1413 | ncoeff = coeff_8k_sb_1seg; | 1419 | ncoeff = coeff_8k_sb_1seg; |
1414 | } else { // 3-segments | 1420 | } else { // 3-segments |
1415 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment | 1421 | if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { |
1416 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments | 1422 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { |
1417 | ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk; | 1423 | ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk; |
1418 | } else { // QPSK or QAM on external segments | 1424 | } else { // QPSK or QAM on external segments |
1419 | ncoeff = coeff_8k_sb_3seg_0dqpsk; | 1425 | ncoeff = coeff_8k_sb_3seg_0dqpsk; |
1420 | } | 1426 | } |
1421 | } else { // QPSK or QAM on central segment | 1427 | } else { // QPSK or QAM on central segment |
1422 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments | 1428 | if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { |
1423 | ncoeff = coeff_8k_sb_3seg_1dqpsk; | 1429 | ncoeff = coeff_8k_sb_3seg_1dqpsk; |
1424 | } else // QPSK or QAM on external segments | 1430 | } else // QPSK or QAM on external segments |
1425 | ncoeff = coeff_8k_sb_3seg; | 1431 | ncoeff = coeff_8k_sb_3seg; |
@@ -1437,7 +1443,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1437 | 1443 | ||
1438 | // ---- COFF ---- | 1444 | // ---- COFF ---- |
1439 | // Carloff, the most robust | 1445 | // Carloff, the most robust |
1440 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { // Sound Broadcasting mode - use both TMCC and AC pilots | 1446 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1441 | 1447 | ||
1442 | // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64 | 1448 | // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64 |
1443 | // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 | 1449 | // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 |
@@ -1448,7 +1454,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1448 | /* // P_small_coef_ext_enable = 1 */ | 1454 | /* // P_small_coef_ext_enable = 1 */ |
1449 | /* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */ | 1455 | /* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */ |
1450 | 1456 | ||
1451 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg | 1457 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { |
1452 | 1458 | ||
1453 | // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1) | 1459 | // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1) |
1454 | if (mode == 3) | 1460 | if (mode == 3) |
@@ -1512,7 +1518,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1512 | dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); | 1518 | dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); |
1513 | } | 1519 | } |
1514 | // ---- FFT ---- | 1520 | // ---- FFT ---- |
1515 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) // 1-seg | 1521 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) |
1516 | dib8000_write_word(state, 178, 64); // P_fft_powrange=64 | 1522 | dib8000_write_word(state, 178, 64); // P_fft_powrange=64 |
1517 | else | 1523 | else |
1518 | dib8000_write_word(state, 178, 32); // P_fft_powrange=32 | 1524 | dib8000_write_word(state, 178, 32); // P_fft_powrange=32 |
@@ -1542,7 +1548,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1542 | 1548 | ||
1543 | /* offset loop parameters */ | 1549 | /* offset loop parameters */ |
1544 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { | 1550 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1545 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg | 1551 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) |
1546 | /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */ | 1552 | /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */ |
1547 | dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40); | 1553 | dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40); |
1548 | 1554 | ||
@@ -1555,7 +1561,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1555 | dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80); | 1561 | dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80); |
1556 | 1562 | ||
1557 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { | 1563 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1558 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg | 1564 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) |
1559 | /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */ | 1565 | /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */ |
1560 | dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode)); | 1566 | dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode)); |
1561 | 1567 | ||
@@ -1628,7 +1634,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1628 | 1634 | ||
1629 | // ---- ANA_FE ---- | 1635 | // ---- ANA_FE ---- |
1630 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) { | 1636 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) { |
1631 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1) // 3-segments | 1637 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1) |
1632 | ana_fe = ana_fe_coeff_3seg; | 1638 | ana_fe = ana_fe_coeff_3seg; |
1633 | else // 1-segment | 1639 | else // 1-segment |
1634 | ana_fe = ana_fe_coeff_1seg; | 1640 | ana_fe = ana_fe_coeff_1seg; |
@@ -1651,10 +1657,10 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear | |||
1651 | // "P_cspu_left_edge" not used => do not care | 1657 | // "P_cspu_left_edge" not used => do not care |
1652 | // "P_cspu_right_edge" not used => do not care | 1658 | // "P_cspu_right_edge" not used => do not care |
1653 | 1659 | ||
1654 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb | 1660 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1655 | dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1 | 1661 | dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1 |
1656 | dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0 | 1662 | dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0 |
1657 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0 // 1-segment | 1663 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0 |
1658 | && state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) { | 1664 | && state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) { |
1659 | //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0 | 1665 | //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0 |
1660 | dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15 | 1666 | dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15 |
@@ -1803,7 +1809,7 @@ static int dib8000_tune(struct dvb_frontend *fe) | |||
1803 | // never achieved a lock before - wait for timfreq to update | 1809 | // never achieved a lock before - wait for timfreq to update |
1804 | if (state->timf == 0) { | 1810 | if (state->timf == 0) { |
1805 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { | 1811 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1806 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg | 1812 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) |
1807 | msleep(300); | 1813 | msleep(300); |
1808 | else // Sound Broadcasting mode 3 seg | 1814 | else // Sound Broadcasting mode 3 seg |
1809 | msleep(500); | 1815 | msleep(500); |
@@ -1811,7 +1817,7 @@ static int dib8000_tune(struct dvb_frontend *fe) | |||
1811 | msleep(200); | 1817 | msleep(200); |
1812 | } | 1818 | } |
1813 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { | 1819 | if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { |
1814 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg | 1820 | if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { |
1815 | 1821 | ||
1816 | /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */ | 1822 | /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */ |
1817 | dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40); | 1823 | dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40); |
@@ -1864,9 +1870,9 @@ static int dib8000_wakeup(struct dvb_frontend *fe) | |||
1864 | if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) | 1870 | if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) |
1865 | dprintk("could not start Slow ADC"); | 1871 | dprintk("could not start Slow ADC"); |
1866 | 1872 | ||
1867 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 1873 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
1868 | ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); | 1874 | ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); |
1869 | if (ret<0) | 1875 | if (ret < 0) |
1870 | return ret; | 1876 | return ret; |
1871 | } | 1877 | } |
1872 | 1878 | ||
@@ -1879,7 +1885,7 @@ static int dib8000_sleep(struct dvb_frontend *fe) | |||
1879 | u8 index_frontend; | 1885 | u8 index_frontend; |
1880 | int ret; | 1886 | int ret; |
1881 | 1887 | ||
1882 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 1888 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
1883 | ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); | 1889 | ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); |
1884 | if (ret < 0) | 1890 | if (ret < 0) |
1885 | return ret; | 1891 | return ret; |
@@ -1914,13 +1920,13 @@ static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
1914 | 1920 | ||
1915 | fe->dtv_property_cache.bandwidth_hz = 6000000; | 1921 | fe->dtv_property_cache.bandwidth_hz = 6000000; |
1916 | 1922 | ||
1917 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 1923 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
1918 | state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); | 1924 | state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); |
1919 | if (stat&FE_HAS_SYNC) { | 1925 | if (stat&FE_HAS_SYNC) { |
1920 | dprintk("TMCC lock on the slave%i", index_frontend); | 1926 | dprintk("TMCC lock on the slave%i", index_frontend); |
1921 | /* synchronize the cache with the other frontends */ | 1927 | /* synchronize the cache with the other frontends */ |
1922 | state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep); | 1928 | state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep); |
1923 | for (sub_index_frontend=0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) { | 1929 | for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) { |
1924 | if (sub_index_frontend != index_frontend) { | 1930 | if (sub_index_frontend != index_frontend) { |
1925 | state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode; | 1931 | state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode; |
1926 | state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion; | 1932 | state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion; |
@@ -2032,7 +2038,7 @@ static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2032 | } | 2038 | } |
2033 | 2039 | ||
2034 | /* synchronize the cache with the other frontends */ | 2040 | /* synchronize the cache with the other frontends */ |
2035 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2041 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2036 | state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode; | 2042 | state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode; |
2037 | state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion; | 2043 | state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion; |
2038 | state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode; | 2044 | state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode; |
@@ -2066,7 +2072,7 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2066 | state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000; | 2072 | state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000; |
2067 | } | 2073 | } |
2068 | 2074 | ||
2069 | for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2075 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2070 | /* synchronization of the cache */ | 2076 | /* synchronization of the cache */ |
2071 | state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; | 2077 | state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; |
2072 | memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties)); | 2078 | memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties)); |
@@ -2081,7 +2087,7 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2081 | /* start up the AGC */ | 2087 | /* start up the AGC */ |
2082 | do { | 2088 | do { |
2083 | time = dib8000_agc_startup(state->fe[0]); | 2089 | time = dib8000_agc_startup(state->fe[0]); |
2084 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2090 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2085 | time_slave = dib8000_agc_startup(state->fe[index_frontend]); | 2091 | time_slave = dib8000_agc_startup(state->fe[index_frontend]); |
2086 | if (time == FE_CALLBACK_TIME_NEVER) | 2092 | if (time == FE_CALLBACK_TIME_NEVER) |
2087 | time = time_slave; | 2093 | time = time_slave; |
@@ -2093,7 +2099,7 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2093 | else | 2099 | else |
2094 | break; | 2100 | break; |
2095 | exit_condition = 1; | 2101 | exit_condition = 1; |
2096 | for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2102 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2097 | if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) { | 2103 | if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) { |
2098 | exit_condition = 0; | 2104 | exit_condition = 0; |
2099 | break; | 2105 | break; |
@@ -2101,7 +2107,7 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2101 | } | 2107 | } |
2102 | } while (exit_condition == 0); | 2108 | } while (exit_condition == 0); |
2103 | 2109 | ||
2104 | for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) | 2110 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) |
2105 | dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); | 2111 | dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); |
2106 | 2112 | ||
2107 | if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) || | 2113 | if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) || |
@@ -2132,31 +2138,30 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2132 | u8 found = 0; | 2138 | u8 found = 0; |
2133 | u8 tune_failed = 0; | 2139 | u8 tune_failed = 0; |
2134 | 2140 | ||
2135 | for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2141 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2136 | dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000); | 2142 | dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000); |
2137 | dib8000_autosearch_start(state->fe[index_frontend]); | 2143 | dib8000_autosearch_start(state->fe[index_frontend]); |
2138 | } | 2144 | } |
2139 | 2145 | ||
2140 | do { | 2146 | do { |
2141 | msleep(10); | 2147 | msleep(20); |
2142 | nbr_pending = 0; | 2148 | nbr_pending = 0; |
2143 | exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */ | 2149 | exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */ |
2144 | for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2150 | for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2145 | if (((tune_failed >> index_frontend) & 0x1) == 0) { | 2151 | if (((tune_failed >> index_frontend) & 0x1) == 0) { |
2146 | found = dib8000_autosearch_irq(state->fe[index_frontend]); | 2152 | found = dib8000_autosearch_irq(state->fe[index_frontend]); |
2147 | switch (found) { | 2153 | switch (found) { |
2148 | case 0: /* tune pending */ | 2154 | case 0: /* tune pending */ |
2149 | nbr_pending++; | 2155 | nbr_pending++; |
2150 | break; | 2156 | break; |
2151 | case 2: | 2157 | case 2: |
2152 | dprintk("autosearch succeed on the frontend%i", index_frontend); | 2158 | dprintk("autosearch succeed on the frontend%i", index_frontend); |
2153 | exit_condition = 2; | 2159 | exit_condition = 2; |
2154 | index_frontend_success = index_frontend; | 2160 | index_frontend_success = index_frontend; |
2155 | break; | 2161 | break; |
2156 | default: | 2162 | default: |
2157 | dprintk("unhandled autosearch result"); | 2163 | dprintk("unhandled autosearch result"); |
2158 | case 1: | 2164 | case 1: |
2159 | tune_failed |= (1 << index_frontend); | ||
2160 | dprintk("autosearch failed for the frontend%i", index_frontend); | 2165 | dprintk("autosearch failed for the frontend%i", index_frontend); |
2161 | break; | 2166 | break; |
2162 | } | 2167 | } |
@@ -2178,13 +2183,12 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2178 | dib8000_get_frontend(fe, fep); | 2183 | dib8000_get_frontend(fe, fep); |
2179 | } | 2184 | } |
2180 | 2185 | ||
2181 | for (index_frontend=0, ret=0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2186 | for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) |
2182 | ret = dib8000_tune(state->fe[index_frontend]); | 2187 | ret = dib8000_tune(state->fe[index_frontend]); |
2183 | } | ||
2184 | 2188 | ||
2185 | /* set output mode and diversity input */ | 2189 | /* set output mode and diversity input */ |
2186 | dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); | 2190 | dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); |
2187 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2191 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2188 | dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY); | 2192 | dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY); |
2189 | dib8000_set_diversity_in(state->fe[index_frontend-1], 1); | 2193 | dib8000_set_diversity_in(state->fe[index_frontend-1], 1); |
2190 | } | 2194 | } |
@@ -2195,7 +2199,8 @@ static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par | |||
2195 | return ret; | 2199 | return ret; |
2196 | } | 2200 | } |
2197 | 2201 | ||
2198 | static u16 dib8000_read_lock(struct dvb_frontend *fe) { | 2202 | static u16 dib8000_read_lock(struct dvb_frontend *fe) |
2203 | { | ||
2199 | struct dib8000_state *state = fe->demodulator_priv; | 2204 | struct dib8000_state *state = fe->demodulator_priv; |
2200 | 2205 | ||
2201 | return dib8000_read_word(state, 568); | 2206 | return dib8000_read_word(state, 568); |
@@ -2207,7 +2212,7 @@ static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat) | |||
2207 | u16 lock_slave = 0, lock = dib8000_read_word(state, 568); | 2212 | u16 lock_slave = 0, lock = dib8000_read_word(state, 568); |
2208 | u8 index_frontend; | 2213 | u8 index_frontend; |
2209 | 2214 | ||
2210 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) | 2215 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) |
2211 | lock_slave |= dib8000_read_lock(state->fe[index_frontend]); | 2216 | lock_slave |= dib8000_read_lock(state->fe[index_frontend]); |
2212 | 2217 | ||
2213 | *stat = 0; | 2218 | *stat = 0; |
@@ -2262,7 +2267,7 @@ static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) | |||
2262 | u16 val; | 2267 | u16 val; |
2263 | 2268 | ||
2264 | *strength = 0; | 2269 | *strength = 0; |
2265 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { | 2270 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) { |
2266 | state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); | 2271 | state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); |
2267 | if (val > 65535 - *strength) | 2272 | if (val > 65535 - *strength) |
2268 | *strength = 65535; | 2273 | *strength = 65535; |
@@ -2312,7 +2317,7 @@ static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr) | |||
2312 | u32 snr_master; | 2317 | u32 snr_master; |
2313 | 2318 | ||
2314 | snr_master = dib8000_get_snr(fe); | 2319 | snr_master = dib8000_get_snr(fe); |
2315 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) | 2320 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) |
2316 | snr_master += dib8000_get_snr(state->fe[index_frontend]); | 2321 | snr_master += dib8000_get_snr(state->fe[index_frontend]); |
2317 | 2322 | ||
2318 | if (snr_master != 0) { | 2323 | if (snr_master != 0) { |
@@ -2361,7 +2366,7 @@ int dib8000_remove_slave_frontend(struct dvb_frontend *fe) | |||
2361 | } | 2366 | } |
2362 | EXPORT_SYMBOL(dib8000_remove_slave_frontend); | 2367 | EXPORT_SYMBOL(dib8000_remove_slave_frontend); |
2363 | 2368 | ||
2364 | struct dvb_frontend * dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index) | 2369 | struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index) |
2365 | { | 2370 | { |
2366 | struct dib8000_state *state = fe->demodulator_priv; | 2371 | struct dib8000_state *state = fe->demodulator_priv; |
2367 | 2372 | ||
@@ -2432,7 +2437,7 @@ static void dib8000_release(struct dvb_frontend *fe) | |||
2432 | struct dib8000_state *st = fe->demodulator_priv; | 2437 | struct dib8000_state *st = fe->demodulator_priv; |
2433 | u8 index_frontend; | 2438 | u8 index_frontend; |
2434 | 2439 | ||
2435 | for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++) | 2440 | for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++) |
2436 | dvb_frontend_detach(st->fe[index_frontend]); | 2441 | dvb_frontend_detach(st->fe[index_frontend]); |
2437 | 2442 | ||
2438 | dibx000_exit_i2c_master(&st->i2c_master); | 2443 | dibx000_exit_i2c_master(&st->i2c_master); |