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-rw-r--r--drivers/media/dvb/ddbridge/Kconfig18
-rw-r--r--drivers/media/dvb/ddbridge/Makefile14
-rw-r--r--drivers/media/dvb/ddbridge/ddbridge-core.c1719
-rw-r--r--drivers/media/dvb/ddbridge/ddbridge-regs.h151
-rw-r--r--drivers/media/dvb/ddbridge/ddbridge.h187
5 files changed, 2089 insertions, 0 deletions
diff --git a/drivers/media/dvb/ddbridge/Kconfig b/drivers/media/dvb/ddbridge/Kconfig
new file mode 100644
index 00000000000..d099e1a12c8
--- /dev/null
+++ b/drivers/media/dvb/ddbridge/Kconfig
@@ -0,0 +1,18 @@
1config DVB_DDBRIDGE
2 tristate "Digital Devices bridge support"
3 depends on DVB_CORE && PCI && I2C
4 select DVB_LNBP21 if !DVB_FE_CUSTOMISE
5 select DVB_STV6110x if !DVB_FE_CUSTOMISE
6 select DVB_STV090x if !DVB_FE_CUSTOMISE
7 select DVB_DRXK if !DVB_FE_CUSTOMISE
8 select DVB_TDA18271C2DD if !DVB_FE_CUSTOMISE
9 ---help---
10 Support for cards with the Digital Devices PCI express bridge:
11 - Octopus PCIe Bridge
12 - Octopus mini PCIe Bridge
13 - Octopus LE
14 - DuoFlex S2 Octopus
15 - DuoFlex CT Octopus
16 - cineS2(v6)
17
18 Say Y if you own such a card and want to use it.
diff --git a/drivers/media/dvb/ddbridge/Makefile b/drivers/media/dvb/ddbridge/Makefile
new file mode 100644
index 00000000000..de4fe193c3e
--- /dev/null
+++ b/drivers/media/dvb/ddbridge/Makefile
@@ -0,0 +1,14 @@
1#
2# Makefile for the ddbridge device driver
3#
4
5ddbridge-objs := ddbridge-core.o
6
7obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o
8
9EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/
10EXTRA_CFLAGS += -Idrivers/media/dvb/frontends/
11EXTRA_CFLAGS += -Idrivers/media/common/tuners/
12
13# For the staging CI driver cxd2099
14EXTRA_CFLAGS += -Idrivers/staging/cxd2099/
diff --git a/drivers/media/dvb/ddbridge/ddbridge-core.c b/drivers/media/dvb/ddbridge/ddbridge-core.c
new file mode 100644
index 00000000000..573d540f213
--- /dev/null
+++ b/drivers/media/dvb/ddbridge/ddbridge-core.c
@@ -0,0 +1,1719 @@
1/*
2 * ddbridge.c: Digital Devices PCIe bridge driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/poll.h>
30#include <linux/io.h>
31#include <linux/pci.h>
32#include <linux/pci_ids.h>
33#include <linux/timer.h>
34#include <linux/version.h>
35#include <linux/i2c.h>
36#include <linux/swab.h>
37#include <linux/vmalloc.h>
38#include "ddbridge.h"
39
40#include "ddbridge-regs.h"
41
42#include "tda18271c2dd.h"
43#include "stv6110x.h"
44#include "stv090x.h"
45#include "lnbh24.h"
46#include "drxk.h"
47
48DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
49
50/* MSI had problems with lost interrupts, fixed but needs testing */
51#undef CONFIG_PCI_MSI
52
53/******************************************************************************/
54
55static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
56{
57 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
58 .buf = val, .len = 1 } };
59 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
60}
61
62static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
63{
64 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
65 .buf = &reg, .len = 1 },
66 {.addr = adr, .flags = I2C_M_RD,
67 .buf = val, .len = 1 } };
68 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
69}
70
71static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
72 u16 reg, u8 *val)
73{
74 u8 msg[2] = {reg>>8, reg&0xff};
75 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
76 .buf = msg, .len = 2},
77 {.addr = adr, .flags = I2C_M_RD,
78 .buf = val, .len = 1} };
79 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
80}
81
82static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
83{
84 struct ddb *dev = i2c->dev;
85 int stat;
86 u32 val;
87
88 i2c->done = 0;
89 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
90 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
91 if (stat <= 0) {
92 printk(KERN_ERR "I2C timeout\n");
93 { /* MSI debugging*/
94 u32 istat = ddbreadl(INTERRUPT_STATUS);
95 printk(KERN_ERR "IRS %08x\n", istat);
96 ddbwritel(istat, INTERRUPT_ACK);
97 }
98 return -EIO;
99 }
100 val = ddbreadl(i2c->regs+I2C_COMMAND);
101 if (val & 0x70000)
102 return -EIO;
103 return 0;
104}
105
106static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
107 struct i2c_msg msg[], int num)
108{
109 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
110 struct ddb *dev = i2c->dev;
111 u8 addr = 0;
112
113 if (num)
114 addr = msg[0].addr;
115
116 if (num == 2 && msg[1].flags & I2C_M_RD &&
117 !(msg[0].flags & I2C_M_RD)) {
118 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
119 msg[0].buf, msg[0].len);
120 ddbwritel(msg[0].len|(msg[1].len << 16),
121 i2c->regs+I2C_TASKLENGTH);
122 if (!ddb_i2c_cmd(i2c, addr, 1)) {
123 memcpy_fromio(msg[1].buf,
124 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
125 msg[1].len);
126 return num;
127 }
128 }
129
130 if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
131 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
132 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
133 if (!ddb_i2c_cmd(i2c, addr, 2))
134 return num;
135 }
136 if (num == 1 && (msg[0].flags & I2C_M_RD)) {
137 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
138 if (!ddb_i2c_cmd(i2c, addr, 3)) {
139 ddbcpyfrom(msg[0].buf,
140 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
141 return num;
142 }
143 }
144 return -EIO;
145}
146
147
148static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
149{
150 return I2C_FUNC_SMBUS_EMUL;
151}
152
153struct i2c_algorithm ddb_i2c_algo = {
154 .master_xfer = ddb_i2c_master_xfer,
155 .functionality = ddb_i2c_functionality,
156};
157
158static void ddb_i2c_release(struct ddb *dev)
159{
160 int i;
161 struct ddb_i2c *i2c;
162 struct i2c_adapter *adap;
163
164 for (i = 0; i < dev->info->port_num; i++) {
165 i2c = &dev->i2c[i];
166 adap = &i2c->adap;
167 i2c_del_adapter(adap);
168 }
169}
170
171static int ddb_i2c_init(struct ddb *dev)
172{
173 int i, j, stat = 0;
174 struct ddb_i2c *i2c;
175 struct i2c_adapter *adap;
176
177 for (i = 0; i < dev->info->port_num; i++) {
178 i2c = &dev->i2c[i];
179 i2c->dev = dev;
180 i2c->nr = i;
181 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
182 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
183 i2c->regs = 0x80 + i * 0x20;
184 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
185 ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
186 i2c->regs + I2C_TASKADDRESS);
187 init_waitqueue_head(&i2c->wq);
188
189 adap = &i2c->adap;
190 i2c_set_adapdata(adap, i2c);
191#ifdef I2C_ADAP_CLASS_TV_DIGITAL
192 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
193#else
194#ifdef I2C_CLASS_TV_ANALOG
195 adap->class = I2C_CLASS_TV_ANALOG;
196#endif
197#endif
198 strcpy(adap->name, "ddbridge");
199 adap->algo = &ddb_i2c_algo;
200 adap->algo_data = (void *)i2c;
201 adap->dev.parent = &dev->pdev->dev;
202 stat = i2c_add_adapter(adap);
203 if (stat)
204 break;
205 }
206 if (stat)
207 for (j = 0; j < i; j++) {
208 i2c = &dev->i2c[j];
209 adap = &i2c->adap;
210 i2c_del_adapter(adap);
211 }
212 return stat;
213}
214
215
216/******************************************************************************/
217/******************************************************************************/
218/******************************************************************************/
219
220#if 0
221static void set_table(struct ddb *dev, u32 off,
222 dma_addr_t *pbuf, u32 num)
223{
224 u32 i, base;
225 u64 mem;
226
227 base = DMA_BASE_ADDRESS_TABLE + off;
228 for (i = 0; i < num; i++) {
229 mem = pbuf[i];
230 ddbwritel(mem & 0xffffffff, base + i * 8);
231 ddbwritel(mem >> 32, base + i * 8 + 4);
232 }
233}
234#endif
235
236static void ddb_address_table(struct ddb *dev)
237{
238 u32 i, j, base;
239 u64 mem;
240 dma_addr_t *pbuf;
241
242 for (i = 0; i < dev->info->port_num * 2; i++) {
243 base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
244 pbuf = dev->input[i].pbuf;
245 for (j = 0; j < dev->input[i].dma_buf_num; j++) {
246 mem = pbuf[j];
247 ddbwritel(mem & 0xffffffff, base + j * 8);
248 ddbwritel(mem >> 32, base + j * 8 + 4);
249 }
250 }
251 for (i = 0; i < dev->info->port_num; i++) {
252 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
253 pbuf = dev->output[i].pbuf;
254 for (j = 0; j < dev->output[i].dma_buf_num; j++) {
255 mem = pbuf[j];
256 ddbwritel(mem & 0xffffffff, base + j * 8);
257 ddbwritel(mem >> 32, base + j * 8 + 4);
258 }
259 }
260}
261
262static void io_free(struct pci_dev *pdev, u8 **vbuf,
263 dma_addr_t *pbuf, u32 size, int num)
264{
265 int i;
266
267 for (i = 0; i < num; i++) {
268 if (vbuf[i]) {
269 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
270 vbuf[i] = 0;
271 }
272 }
273}
274
275static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
276 dma_addr_t *pbuf, u32 size, int num)
277{
278 int i;
279
280 for (i = 0; i < num; i++) {
281 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
282 if (!vbuf[i])
283 return -ENOMEM;
284 }
285 return 0;
286}
287
288static int ddb_buffers_alloc(struct ddb *dev)
289{
290 int i;
291 struct ddb_port *port;
292
293 for (i = 0; i < dev->info->port_num; i++) {
294 port = &dev->port[i];
295 switch (port->class) {
296 case DDB_PORT_TUNER:
297 if (io_alloc(dev->pdev, port->input[0]->vbuf,
298 port->input[0]->pbuf,
299 port->input[0]->dma_buf_size,
300 port->input[0]->dma_buf_num) < 0)
301 return -1;
302 if (io_alloc(dev->pdev, port->input[1]->vbuf,
303 port->input[1]->pbuf,
304 port->input[1]->dma_buf_size,
305 port->input[1]->dma_buf_num) < 0)
306 return -1;
307 break;
308 case DDB_PORT_CI:
309 if (io_alloc(dev->pdev, port->input[0]->vbuf,
310 port->input[0]->pbuf,
311 port->input[0]->dma_buf_size,
312 port->input[0]->dma_buf_num) < 0)
313 return -1;
314 if (io_alloc(dev->pdev, port->output->vbuf,
315 port->output->pbuf,
316 port->output->dma_buf_size,
317 port->output->dma_buf_num) < 0)
318 return -1;
319 break;
320 default:
321 break;
322 }
323 }
324 ddb_address_table(dev);
325 return 0;
326}
327
328static void ddb_buffers_free(struct ddb *dev)
329{
330 int i;
331 struct ddb_port *port;
332
333 for (i = 0; i < dev->info->port_num; i++) {
334 port = &dev->port[i];
335 io_free(dev->pdev, port->input[0]->vbuf,
336 port->input[0]->pbuf,
337 port->input[0]->dma_buf_size,
338 port->input[0]->dma_buf_num);
339 io_free(dev->pdev, port->input[1]->vbuf,
340 port->input[1]->pbuf,
341 port->input[1]->dma_buf_size,
342 port->input[1]->dma_buf_num);
343 io_free(dev->pdev, port->output->vbuf,
344 port->output->pbuf,
345 port->output->dma_buf_size,
346 port->output->dma_buf_num);
347 }
348}
349
350static void ddb_input_start(struct ddb_input *input)
351{
352 struct ddb *dev = input->port->dev;
353
354 spin_lock_irq(&input->lock);
355 input->cbuf = 0;
356 input->coff = 0;
357
358 /* reset */
359 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
360 ddbwritel(2, TS_INPUT_CONTROL(input->nr));
361 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
362
363 ddbwritel((1 << 16) |
364 (input->dma_buf_num << 11) |
365 (input->dma_buf_size >> 7),
366 DMA_BUFFER_SIZE(input->nr));
367 ddbwritel(0, DMA_BUFFER_ACK(input->nr));
368
369 ddbwritel(1, DMA_BASE_WRITE);
370 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
371 ddbwritel(9, TS_INPUT_CONTROL(input->nr));
372 input->running = 1;
373 spin_unlock_irq(&input->lock);
374}
375
376static void ddb_input_stop(struct ddb_input *input)
377{
378 struct ddb *dev = input->port->dev;
379
380 spin_lock_irq(&input->lock);
381 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
382 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
383 input->running = 0;
384 spin_unlock_irq(&input->lock);
385}
386
387static void ddb_output_start(struct ddb_output *output)
388{
389 struct ddb *dev = output->port->dev;
390
391 spin_lock_irq(&output->lock);
392 output->cbuf = 0;
393 output->coff = 0;
394 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
395 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
396 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
397 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
398 ddbwritel((1 << 16) |
399 (output->dma_buf_num << 11) |
400 (output->dma_buf_size >> 7),
401 DMA_BUFFER_SIZE(output->nr + 8));
402 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
403
404 ddbwritel(1, DMA_BASE_READ);
405 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
406 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
407 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
408 output->running = 1;
409 spin_unlock_irq(&output->lock);
410}
411
412static void ddb_output_stop(struct ddb_output *output)
413{
414 struct ddb *dev = output->port->dev;
415
416 spin_lock_irq(&output->lock);
417 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
418 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
419 output->running = 0;
420 spin_unlock_irq(&output->lock);
421}
422
423static u32 ddb_output_free(struct ddb_output *output)
424{
425 u32 idx, off, stat = output->stat;
426 s32 diff;
427
428 idx = (stat >> 11) & 0x1f;
429 off = (stat & 0x7ff) << 7;
430
431 if (output->cbuf != idx) {
432 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
433 (output->dma_buf_size - output->coff <= 188))
434 return 0;
435 return 188;
436 }
437 diff = off - output->coff;
438 if (diff <= 0 || diff > 188)
439 return 188;
440 return 0;
441}
442
443static ssize_t ddb_output_write(struct ddb_output *output,
444 const u8 *buf, size_t count)
445{
446 struct ddb *dev = output->port->dev;
447 u32 idx, off, stat = output->stat;
448 u32 left = count, len;
449
450 idx = (stat >> 11) & 0x1f;
451 off = (stat & 0x7ff) << 7;
452
453 while (left) {
454 len = output->dma_buf_size - output->coff;
455 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
456 (off == 0)) {
457 if (len <= 188)
458 break;
459 len -= 188;
460 }
461 if (output->cbuf == idx) {
462 if (off > output->coff) {
463#if 1
464 len = off - output->coff;
465 len -= (len % 188);
466 if (len <= 188)
467
468#endif
469 break;
470 len -= 188;
471 }
472 }
473 if (len > left)
474 len = left;
475 if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
476 buf, len))
477 return -EIO;
478 left -= len;
479 buf += len;
480 output->coff += len;
481 if (output->coff == output->dma_buf_size) {
482 output->coff = 0;
483 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
484 }
485 ddbwritel((output->cbuf << 11) | (output->coff >> 7),
486 DMA_BUFFER_ACK(output->nr + 8));
487 }
488 return count - left;
489}
490
491static u32 ddb_input_avail(struct ddb_input *input)
492{
493 struct ddb *dev = input->port->dev;
494 u32 idx, off, stat = input->stat;
495 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
496
497 idx = (stat >> 11) & 0x1f;
498 off = (stat & 0x7ff) << 7;
499
500 if (ctrl & 4) {
501 printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
502 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
503 return 0;
504 }
505 if (input->cbuf != idx)
506 return 188;
507 return 0;
508}
509
510static size_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count)
511{
512 struct ddb *dev = input->port->dev;
513 u32 left = count;
514 u32 idx, off, free, stat = input->stat;
515 int ret;
516
517 idx = (stat >> 11) & 0x1f;
518 off = (stat & 0x7ff) << 7;
519
520 while (left) {
521 if (input->cbuf == idx)
522 return count - left;
523 free = input->dma_buf_size - input->coff;
524 if (free > left)
525 free = left;
526 ret = copy_to_user(buf, input->vbuf[input->cbuf] +
527 input->coff, free);
528 input->coff += free;
529 if (input->coff == input->dma_buf_size) {
530 input->coff = 0;
531 input->cbuf = (input->cbuf+1) % input->dma_buf_num;
532 }
533 left -= free;
534 ddbwritel((input->cbuf << 11) | (input->coff >> 7),
535 DMA_BUFFER_ACK(input->nr));
536 }
537 return count;
538}
539
540/******************************************************************************/
541/******************************************************************************/
542/******************************************************************************/
543
544#if 0
545static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
546{
547 int i;
548
549 for (i = 0; i < dev->info->port_num * 2; i++) {
550 if (dev->input[i].fe == fe)
551 return &dev->input[i];
552 }
553 return NULL;
554}
555#endif
556
557static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
558{
559 struct ddb_input *input = fe->sec_priv;
560 struct ddb_port *port = input->port;
561 int status;
562
563 if (enable) {
564 mutex_lock(&port->i2c_gate_lock);
565 status = input->gate_ctrl(fe, 1);
566 } else {
567 status = input->gate_ctrl(fe, 0);
568 mutex_unlock(&port->i2c_gate_lock);
569 }
570 return status;
571}
572
573static int demod_attach_drxk(struct ddb_input *input)
574{
575 struct i2c_adapter *i2c = &input->port->i2c->adap;
576 struct dvb_frontend *fe;
577 struct drxk_config config;
578
579 memset(&config, 0, sizeof(config));
580 config.adr = 0x29 + (input->nr & 1);
581
582 fe = input->fe = dvb_attach(drxk_attach, &config, i2c, &input->fe2);
583 if (!input->fe) {
584 printk(KERN_ERR "No DRXK found!\n");
585 return -ENODEV;
586 }
587 fe->sec_priv = input;
588 input->gate_ctrl = fe->ops.i2c_gate_ctrl;
589 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
590 return 0;
591}
592
593static int tuner_attach_tda18271(struct ddb_input *input)
594{
595 struct i2c_adapter *i2c = &input->port->i2c->adap;
596 struct dvb_frontend *fe;
597
598 if (input->fe->ops.i2c_gate_ctrl)
599 input->fe->ops.i2c_gate_ctrl(input->fe, 1);
600 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
601 if (!fe) {
602 printk(KERN_ERR "No TDA18271 found!\n");
603 return -ENODEV;
604 }
605 if (input->fe->ops.i2c_gate_ctrl)
606 input->fe->ops.i2c_gate_ctrl(input->fe, 0);
607 return 0;
608}
609
610/******************************************************************************/
611/******************************************************************************/
612/******************************************************************************/
613
614static struct stv090x_config stv0900 = {
615 .device = STV0900,
616 .demod_mode = STV090x_DUAL,
617 .clk_mode = STV090x_CLK_EXT,
618
619 .xtal = 27000000,
620 .address = 0x69,
621
622 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
623 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
624
625 .repeater_level = STV090x_RPTLEVEL_16,
626
627 .adc1_range = STV090x_ADC_1Vpp,
628 .adc2_range = STV090x_ADC_1Vpp,
629
630 .diseqc_envelope_mode = true,
631};
632
633static struct stv090x_config stv0900_aa = {
634 .device = STV0900,
635 .demod_mode = STV090x_DUAL,
636 .clk_mode = STV090x_CLK_EXT,
637
638 .xtal = 27000000,
639 .address = 0x68,
640
641 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
642 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
643
644 .repeater_level = STV090x_RPTLEVEL_16,
645
646 .adc1_range = STV090x_ADC_1Vpp,
647 .adc2_range = STV090x_ADC_1Vpp,
648
649 .diseqc_envelope_mode = true,
650};
651
652static struct stv6110x_config stv6110a = {
653 .addr = 0x60,
654 .refclk = 27000000,
655 .clk_div = 1,
656};
657
658static struct stv6110x_config stv6110b = {
659 .addr = 0x63,
660 .refclk = 27000000,
661 .clk_div = 1,
662};
663
664static int demod_attach_stv0900(struct ddb_input *input, int type)
665{
666 struct i2c_adapter *i2c = &input->port->i2c->adap;
667 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
668
669 input->fe = dvb_attach(stv090x_attach, feconf, i2c,
670 (input->nr & 1) ? STV090x_DEMODULATOR_1
671 : STV090x_DEMODULATOR_0);
672 if (!input->fe) {
673 printk(KERN_ERR "No STV0900 found!\n");
674 return -ENODEV;
675 }
676 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
677 0, (input->nr & 1) ?
678 (0x09 - type) : (0x0b - type))) {
679 printk(KERN_ERR "No LNBH24 found!\n");
680 return -ENODEV;
681 }
682 return 0;
683}
684
685static int tuner_attach_stv6110(struct ddb_input *input, int type)
686{
687 struct i2c_adapter *i2c = &input->port->i2c->adap;
688 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
689 struct stv6110x_config *tunerconf = (input->nr & 1) ?
690 &stv6110b : &stv6110a;
691 struct stv6110x_devctl *ctl;
692
693 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
694 if (!ctl) {
695 printk(KERN_ERR "No STV6110X found!\n");
696 return -ENODEV;
697 }
698 printk(KERN_INFO "attach tuner input %d adr %02x\n",
699 input->nr, tunerconf->addr);
700
701 feconf->tuner_init = ctl->tuner_init;
702 feconf->tuner_sleep = ctl->tuner_sleep;
703 feconf->tuner_set_mode = ctl->tuner_set_mode;
704 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
705 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
706 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
707 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
708 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
709 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
710 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
711 feconf->tuner_get_status = ctl->tuner_get_status;
712
713 return 0;
714}
715
716static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
717 int (*start_feed)(struct dvb_demux_feed *),
718 int (*stop_feed)(struct dvb_demux_feed *),
719 void *priv)
720{
721 dvbdemux->priv = priv;
722
723 dvbdemux->filternum = 256;
724 dvbdemux->feednum = 256;
725 dvbdemux->start_feed = start_feed;
726 dvbdemux->stop_feed = stop_feed;
727 dvbdemux->write_to_decoder = NULL;
728 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
729 DMX_SECTION_FILTERING |
730 DMX_MEMORY_BASED_FILTERING);
731 return dvb_dmx_init(dvbdemux);
732}
733
734static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
735 struct dvb_demux *dvbdemux,
736 struct dmx_frontend *hw_frontend,
737 struct dmx_frontend *mem_frontend,
738 struct dvb_adapter *dvb_adapter)
739{
740 int ret;
741
742 dmxdev->filternum = 256;
743 dmxdev->demux = &dvbdemux->dmx;
744 dmxdev->capabilities = 0;
745 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
746 if (ret < 0)
747 return ret;
748
749 hw_frontend->source = DMX_FRONTEND_0;
750 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
751 mem_frontend->source = DMX_MEMORY_FE;
752 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
753 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
754}
755
756static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
757{
758 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
759 struct ddb_input *input = dvbdmx->priv;
760
761 if (!input->users)
762 ddb_input_start(input);
763
764 return ++input->users;
765}
766
767static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
768{
769 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
770 struct ddb_input *input = dvbdmx->priv;
771
772 if (--input->users)
773 return input->users;
774
775 ddb_input_stop(input);
776 return 0;
777}
778
779
780static void dvb_input_detach(struct ddb_input *input)
781{
782 struct dvb_adapter *adap = &input->adap;
783 struct dvb_demux *dvbdemux = &input->demux;
784
785 switch (input->attached) {
786 case 5:
787 if (input->fe2)
788 dvb_unregister_frontend(input->fe2);
789 if (input->fe) {
790 dvb_unregister_frontend(input->fe);
791 dvb_frontend_detach(input->fe);
792 input->fe = NULL;
793 }
794 case 4:
795 dvb_net_release(&input->dvbnet);
796
797 case 3:
798 dvbdemux->dmx.close(&dvbdemux->dmx);
799 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
800 &input->hw_frontend);
801 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
802 &input->mem_frontend);
803 dvb_dmxdev_release(&input->dmxdev);
804
805 case 2:
806 dvb_dmx_release(&input->demux);
807
808 case 1:
809 dvb_unregister_adapter(adap);
810 }
811 input->attached = 0;
812}
813
814static int dvb_input_attach(struct ddb_input *input)
815{
816 int ret;
817 struct ddb_port *port = input->port;
818 struct dvb_adapter *adap = &input->adap;
819 struct dvb_demux *dvbdemux = &input->demux;
820
821 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
822 &input->port->dev->pdev->dev,
823 adapter_nr);
824 if (ret < 0) {
825 printk(KERN_ERR "ddbridge: Could not register adapter."
826 "Check if you enabled enough adapters in dvb-core!\n");
827 return ret;
828 }
829 input->attached = 1;
830
831 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
832 start_feed,
833 stop_feed, input);
834 if (ret < 0)
835 return ret;
836 input->attached = 2;
837
838 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
839 &input->hw_frontend,
840 &input->mem_frontend, adap);
841 if (ret < 0)
842 return ret;
843 input->attached = 3;
844
845 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
846 if (ret < 0)
847 return ret;
848 input->attached = 4;
849
850 input->fe = 0;
851 switch (port->type) {
852 case DDB_TUNER_DVBS_ST:
853 if (demod_attach_stv0900(input, 0) < 0)
854 return -ENODEV;
855 if (tuner_attach_stv6110(input, 0) < 0)
856 return -ENODEV;
857 if (input->fe) {
858 if (dvb_register_frontend(adap, input->fe) < 0)
859 return -ENODEV;
860 }
861 break;
862 case DDB_TUNER_DVBS_ST_AA:
863 if (demod_attach_stv0900(input, 1) < 0)
864 return -ENODEV;
865 if (tuner_attach_stv6110(input, 1) < 0)
866 return -ENODEV;
867 if (input->fe) {
868 if (dvb_register_frontend(adap, input->fe) < 0)
869 return -ENODEV;
870 }
871 break;
872 case DDB_TUNER_DVBCT_TR:
873 if (demod_attach_drxk(input) < 0)
874 return -ENODEV;
875 if (tuner_attach_tda18271(input) < 0)
876 return -ENODEV;
877 if (input->fe) {
878 if (dvb_register_frontend(adap, input->fe) < 0)
879 return -ENODEV;
880 }
881 if (input->fe2) {
882 if (dvb_register_frontend(adap, input->fe2) < 0)
883 return -ENODEV;
884 input->fe2->tuner_priv = input->fe->tuner_priv;
885 memcpy(&input->fe2->ops.tuner_ops,
886 &input->fe->ops.tuner_ops,
887 sizeof(struct dvb_tuner_ops));
888 }
889 break;
890 }
891 input->attached = 5;
892 return 0;
893}
894
895/****************************************************************************/
896/****************************************************************************/
897
898static ssize_t ts_write(struct file *file, const char *buf,
899 size_t count, loff_t *ppos)
900{
901 struct dvb_device *dvbdev = file->private_data;
902 struct ddb_output *output = dvbdev->priv;
903 size_t left = count;
904 int stat;
905
906 while (left) {
907 if (ddb_output_free(output) < 188) {
908 if (file->f_flags & O_NONBLOCK)
909 break;
910 if (wait_event_interruptible(
911 output->wq, ddb_output_free(output) >= 188) < 0)
912 break;
913 }
914 stat = ddb_output_write(output, buf, left);
915 if (stat < 0)
916 break;
917 buf += stat;
918 left -= stat;
919 }
920 return (left == count) ? -EAGAIN : (count - left);
921}
922
923static ssize_t ts_read(struct file *file, char *buf,
924 size_t count, loff_t *ppos)
925{
926 struct dvb_device *dvbdev = file->private_data;
927 struct ddb_output *output = dvbdev->priv;
928 struct ddb_input *input = output->port->input[0];
929 int left, read;
930
931 count -= count % 188;
932 left = count;
933 while (left) {
934 if (ddb_input_avail(input) < 188) {
935 if (file->f_flags & O_NONBLOCK)
936 break;
937 if (wait_event_interruptible(
938 input->wq, ddb_input_avail(input) >= 188) < 0)
939 break;
940 }
941 read = ddb_input_read(input, buf, left);
942 left -= read;
943 buf += read;
944 }
945 return (left == count) ? -EAGAIN : (count - left);
946}
947
948static unsigned int ts_poll(struct file *file, poll_table *wait)
949{
950 /*
951 struct dvb_device *dvbdev = file->private_data;
952 struct ddb_output *output = dvbdev->priv;
953 struct ddb_input *input = output->port->input[0];
954 */
955 unsigned int mask = 0;
956
957#if 0
958 if (data_avail_to_read)
959 mask |= POLLIN | POLLRDNORM;
960 if (data_avail_to_write)
961 mask |= POLLOUT | POLLWRNORM;
962
963 poll_wait(file, &read_queue, wait);
964 poll_wait(file, &write_queue, wait);
965#endif
966 return mask;
967}
968
969static const struct file_operations ci_fops = {
970 .owner = THIS_MODULE,
971 .read = ts_read,
972 .write = ts_write,
973 .open = dvb_generic_open,
974 .release = dvb_generic_release,
975 .poll = ts_poll,
976 .mmap = 0,
977};
978
979static struct dvb_device dvbdev_ci = {
980 .priv = 0,
981 .readers = -1,
982 .writers = -1,
983 .users = -1,
984 .fops = &ci_fops,
985};
986
987/****************************************************************************/
988/****************************************************************************/
989/****************************************************************************/
990
991static void input_tasklet(unsigned long data)
992{
993 struct ddb_input *input = (struct ddb_input *) data;
994 struct ddb *dev = input->port->dev;
995
996 spin_lock(&input->lock);
997 if (!input->running) {
998 spin_unlock(&input->lock);
999 return;
1000 }
1001 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1002
1003 if (input->port->class == DDB_PORT_TUNER) {
1004 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
1005 printk(KERN_ERR "Overflow input %d\n", input->nr);
1006 while (input->cbuf != ((input->stat >> 11) & 0x1f)
1007 || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
1008 dvb_dmx_swfilter_packets(&input->demux,
1009 input->vbuf[input->cbuf],
1010 input->dma_buf_size / 188);
1011
1012 input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
1013 ddbwritel((input->cbuf << 11),
1014 DMA_BUFFER_ACK(input->nr));
1015 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1016 }
1017 }
1018 if (input->port->class == DDB_PORT_CI)
1019 wake_up(&input->wq);
1020 spin_unlock(&input->lock);
1021}
1022
1023static void output_tasklet(unsigned long data)
1024{
1025 struct ddb_output *output = (struct ddb_output *) data;
1026 struct ddb *dev = output->port->dev;
1027
1028 spin_lock(&output->lock);
1029 if (!output->running) {
1030 spin_unlock(&output->lock);
1031 return;
1032 }
1033 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
1034 wake_up(&output->wq);
1035 spin_unlock(&output->lock);
1036}
1037
1038
1039struct cxd2099_cfg cxd_cfg = {
1040 .bitrate = 62000,
1041 .adr = 0x40,
1042 .polarity = 1,
1043 .clock_mode = 1,
1044};
1045
1046static int ddb_ci_attach(struct ddb_port *port)
1047{
1048 int ret;
1049
1050 ret = dvb_register_adapter(&port->output->adap,
1051 "DDBridge",
1052 THIS_MODULE,
1053 &port->dev->pdev->dev,
1054 adapter_nr);
1055 if (ret < 0)
1056 return ret;
1057 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
1058 if (!port->en) {
1059 dvb_unregister_adapter(&port->output->adap);
1060 return -ENODEV;
1061 }
1062 ddb_input_start(port->input[0]);
1063 ddb_output_start(port->output);
1064 dvb_ca_en50221_init(&port->output->adap,
1065 port->en, 0, 1);
1066 ret = dvb_register_device(&port->output->adap, &port->output->dev,
1067 &dvbdev_ci, (void *) port->output,
1068 DVB_DEVICE_SEC);
1069 return ret;
1070}
1071
1072static int ddb_port_attach(struct ddb_port *port)
1073{
1074 int ret = 0;
1075
1076 switch (port->class) {
1077 case DDB_PORT_TUNER:
1078 ret = dvb_input_attach(port->input[0]);
1079 if (ret < 0)
1080 break;
1081 ret = dvb_input_attach(port->input[1]);
1082 break;
1083 case DDB_PORT_CI:
1084 ret = ddb_ci_attach(port);
1085 break;
1086 default:
1087 break;
1088 }
1089 if (ret < 0)
1090 printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
1091 return ret;
1092}
1093
1094static int ddb_ports_attach(struct ddb *dev)
1095{
1096 int i, ret = 0;
1097 struct ddb_port *port;
1098
1099 for (i = 0; i < dev->info->port_num; i++) {
1100 port = &dev->port[i];
1101 ret = ddb_port_attach(port);
1102 if (ret < 0)
1103 break;
1104 }
1105 return ret;
1106}
1107
1108static void ddb_ports_detach(struct ddb *dev)
1109{
1110 int i;
1111 struct ddb_port *port;
1112
1113 for (i = 0; i < dev->info->port_num; i++) {
1114 port = &dev->port[i];
1115 switch (port->class) {
1116 case DDB_PORT_TUNER:
1117 dvb_input_detach(port->input[0]);
1118 dvb_input_detach(port->input[1]);
1119 break;
1120 case DDB_PORT_CI:
1121 if (port->output->dev)
1122 dvb_unregister_device(port->output->dev);
1123 if (port->en) {
1124 ddb_input_stop(port->input[0]);
1125 ddb_output_stop(port->output);
1126 dvb_ca_en50221_release(port->en);
1127 kfree(port->en);
1128 port->en = 0;
1129 dvb_unregister_adapter(&port->output->adap);
1130 }
1131 break;
1132 }
1133 }
1134}
1135
1136/****************************************************************************/
1137/****************************************************************************/
1138
1139static int port_has_ci(struct ddb_port *port)
1140{
1141 u8 val;
1142 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
1143}
1144
1145static int port_has_stv0900(struct ddb_port *port)
1146{
1147 u8 val;
1148 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
1149 return 0;
1150 return 1;
1151}
1152
1153static int port_has_stv0900_aa(struct ddb_port *port)
1154{
1155 u8 val;
1156 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
1157 return 0;
1158 return 1;
1159}
1160
1161static int port_has_drxks(struct ddb_port *port)
1162{
1163 u8 val;
1164 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
1165 return 0;
1166 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
1167 return 0;
1168 return 1;
1169}
1170
1171static void ddb_port_probe(struct ddb_port *port)
1172{
1173 struct ddb *dev = port->dev;
1174 char *modname = "NO MODULE";
1175
1176 port->class = DDB_PORT_NONE;
1177
1178 if (port_has_ci(port)) {
1179 modname = "CI";
1180 port->class = DDB_PORT_CI;
1181 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1182 } else if (port_has_stv0900(port)) {
1183 modname = "DUAL DVB-S2";
1184 port->class = DDB_PORT_TUNER;
1185 port->type = DDB_TUNER_DVBS_ST;
1186 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1187 } else if (port_has_stv0900_aa(port)) {
1188 modname = "DUAL DVB-S2";
1189 port->class = DDB_PORT_TUNER;
1190 port->type = DDB_TUNER_DVBS_ST_AA;
1191 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1192 } else if (port_has_drxks(port)) {
1193 modname = "DUAL DVB-C/T";
1194 port->class = DDB_PORT_TUNER;
1195 port->type = DDB_TUNER_DVBCT_TR;
1196 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1197 }
1198 printk(KERN_INFO "Port %d (TAB %d): %s\n",
1199 port->nr, port->nr+1, modname);
1200}
1201
1202static void ddb_input_init(struct ddb_port *port, int nr)
1203{
1204 struct ddb *dev = port->dev;
1205 struct ddb_input *input = &dev->input[nr];
1206
1207 input->nr = nr;
1208 input->port = port;
1209 input->dma_buf_num = INPUT_DMA_BUFS;
1210 input->dma_buf_size = INPUT_DMA_SIZE;
1211 ddbwritel(0, TS_INPUT_CONTROL(nr));
1212 ddbwritel(2, TS_INPUT_CONTROL(nr));
1213 ddbwritel(0, TS_INPUT_CONTROL(nr));
1214 ddbwritel(0, DMA_BUFFER_ACK(nr));
1215 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
1216 spin_lock_init(&input->lock);
1217 init_waitqueue_head(&input->wq);
1218}
1219
1220static void ddb_output_init(struct ddb_port *port, int nr)
1221{
1222 struct ddb *dev = port->dev;
1223 struct ddb_output *output = &dev->output[nr];
1224 output->nr = nr;
1225 output->port = port;
1226 output->dma_buf_num = OUTPUT_DMA_BUFS;
1227 output->dma_buf_size = OUTPUT_DMA_SIZE;
1228
1229 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1230 ddbwritel(2, TS_OUTPUT_CONTROL(nr));
1231 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1232 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
1233 init_waitqueue_head(&output->wq);
1234}
1235
1236static void ddb_ports_init(struct ddb *dev)
1237{
1238 int i;
1239 struct ddb_port *port;
1240
1241 for (i = 0; i < dev->info->port_num; i++) {
1242 port = &dev->port[i];
1243 port->dev = dev;
1244 port->nr = i;
1245 port->i2c = &dev->i2c[i];
1246 port->input[0] = &dev->input[2 * i];
1247 port->input[1] = &dev->input[2 * i + 1];
1248 port->output = &dev->output[i];
1249
1250 mutex_init(&port->i2c_gate_lock);
1251 ddb_port_probe(port);
1252 ddb_input_init(port, 2 * i);
1253 ddb_input_init(port, 2 * i + 1);
1254 ddb_output_init(port, i);
1255 }
1256}
1257
1258static void ddb_ports_release(struct ddb *dev)
1259{
1260 int i;
1261 struct ddb_port *port;
1262
1263 for (i = 0; i < dev->info->port_num; i++) {
1264 port = &dev->port[i];
1265 port->dev = dev;
1266 tasklet_kill(&port->input[0]->tasklet);
1267 tasklet_kill(&port->input[1]->tasklet);
1268 tasklet_kill(&port->output->tasklet);
1269 }
1270}
1271
1272/****************************************************************************/
1273/****************************************************************************/
1274/****************************************************************************/
1275
1276static void irq_handle_i2c(struct ddb *dev, int n)
1277{
1278 struct ddb_i2c *i2c = &dev->i2c[n];
1279
1280 i2c->done = 1;
1281 wake_up(&i2c->wq);
1282}
1283
1284static irqreturn_t irq_handler(int irq, void *dev_id)
1285{
1286 struct ddb *dev = (struct ddb *) dev_id;
1287 u32 s = ddbreadl(INTERRUPT_STATUS);
1288
1289 if (!s)
1290 return IRQ_NONE;
1291
1292 do {
1293 ddbwritel(s, INTERRUPT_ACK);
1294
1295 if (s & 0x00000001)
1296 irq_handle_i2c(dev, 0);
1297 if (s & 0x00000002)
1298 irq_handle_i2c(dev, 1);
1299 if (s & 0x00000004)
1300 irq_handle_i2c(dev, 2);
1301 if (s & 0x00000008)
1302 irq_handle_i2c(dev, 3);
1303
1304 if (s & 0x00000100)
1305 tasklet_schedule(&dev->input[0].tasklet);
1306 if (s & 0x00000200)
1307 tasklet_schedule(&dev->input[1].tasklet);
1308 if (s & 0x00000400)
1309 tasklet_schedule(&dev->input[2].tasklet);
1310 if (s & 0x00000800)
1311 tasklet_schedule(&dev->input[3].tasklet);
1312 if (s & 0x00001000)
1313 tasklet_schedule(&dev->input[4].tasklet);
1314 if (s & 0x00002000)
1315 tasklet_schedule(&dev->input[5].tasklet);
1316 if (s & 0x00004000)
1317 tasklet_schedule(&dev->input[6].tasklet);
1318 if (s & 0x00008000)
1319 tasklet_schedule(&dev->input[7].tasklet);
1320
1321 if (s & 0x00010000)
1322 tasklet_schedule(&dev->output[0].tasklet);
1323 if (s & 0x00020000)
1324 tasklet_schedule(&dev->output[1].tasklet);
1325 if (s & 0x00040000)
1326 tasklet_schedule(&dev->output[2].tasklet);
1327 if (s & 0x00080000)
1328 tasklet_schedule(&dev->output[3].tasklet);
1329
1330 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
1331 } while ((s = ddbreadl(INTERRUPT_STATUS)));
1332
1333 return IRQ_HANDLED;
1334}
1335
1336/******************************************************************************/
1337/******************************************************************************/
1338/******************************************************************************/
1339
1340static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
1341{
1342 u32 data, shift;
1343
1344 if (wlen > 4)
1345 ddbwritel(1, SPI_CONTROL);
1346 while (wlen > 4) {
1347 /* FIXME: check for big-endian */
1348 data = swab32(*(u32 *)wbuf);
1349 wbuf += 4;
1350 wlen -= 4;
1351 ddbwritel(data, SPI_DATA);
1352 while (ddbreadl(SPI_CONTROL) & 0x0004)
1353 ;
1354 }
1355
1356 if (rlen)
1357 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1358 else
1359 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1360
1361 data = 0;
1362 shift = ((4 - wlen) * 8);
1363 while (wlen) {
1364 data <<= 8;
1365 data |= *wbuf;
1366 wlen--;
1367 wbuf++;
1368 }
1369 if (shift)
1370 data <<= shift;
1371 ddbwritel(data, SPI_DATA);
1372 while (ddbreadl(SPI_CONTROL) & 0x0004)
1373 ;
1374
1375 if (!rlen) {
1376 ddbwritel(0, SPI_CONTROL);
1377 return 0;
1378 }
1379 if (rlen > 4)
1380 ddbwritel(1, SPI_CONTROL);
1381
1382 while (rlen > 4) {
1383 ddbwritel(0xffffffff, SPI_DATA);
1384 while (ddbreadl(SPI_CONTROL) & 0x0004)
1385 ;
1386 data = ddbreadl(SPI_DATA);
1387 *(u32 *) rbuf = swab32(data);
1388 rbuf += 4;
1389 rlen -= 4;
1390 }
1391 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
1392 ddbwritel(0xffffffff, SPI_DATA);
1393 while (ddbreadl(SPI_CONTROL) & 0x0004)
1394 ;
1395
1396 data = ddbreadl(SPI_DATA);
1397 ddbwritel(0, SPI_CONTROL);
1398
1399 if (rlen < 4)
1400 data <<= ((4 - rlen) * 8);
1401
1402 while (rlen > 0) {
1403 *rbuf = ((data >> 24) & 0xff);
1404 data <<= 8;
1405 rbuf++;
1406 rlen--;
1407 }
1408 return 0;
1409}
1410
1411#define DDB_MAGIC 'd'
1412
1413struct ddb_flashio {
1414 __u8 *write_buf;
1415 __u32 write_len;
1416 __u8 *read_buf;
1417 __u32 read_len;
1418};
1419
1420#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
1421
1422#define DDB_NAME "ddbridge"
1423
1424static u32 ddb_num;
1425static struct ddb *ddbs[32];
1426static struct class *ddb_class;
1427static int ddb_major;
1428
1429static int ddb_open(struct inode *inode, struct file *file)
1430{
1431 struct ddb *dev = ddbs[iminor(inode)];
1432
1433 file->private_data = dev;
1434 return 0;
1435}
1436
1437static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1438{
1439 struct ddb *dev = file->private_data;
1440 void *parg = (void *)arg;
1441 int res = -EFAULT;
1442
1443 switch (cmd) {
1444 case IOCTL_DDB_FLASHIO:
1445 {
1446 struct ddb_flashio fio;
1447 u8 *rbuf, *wbuf;
1448
1449 if (copy_from_user(&fio, parg, sizeof(fio)))
1450 break;
1451 if (fio.write_len + fio.read_len > 1028) {
1452 printk(KERN_ERR "IOBUF too small\n");
1453 return -ENOMEM;
1454 }
1455 wbuf = &dev->iobuf[0];
1456 if (!wbuf)
1457 return -ENOMEM;
1458 rbuf = wbuf + fio.write_len;
1459 if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) {
1460 vfree(wbuf);
1461 break;
1462 }
1463 res = flashio(dev, wbuf, fio.write_len,
1464 rbuf, fio.read_len);
1465 if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
1466 res = -EFAULT;
1467 break;
1468 }
1469 default:
1470 break;
1471 }
1472 return res;
1473}
1474
1475static const struct file_operations ddb_fops = {
1476 .unlocked_ioctl = ddb_ioctl,
1477 .open = ddb_open,
1478};
1479
1480static char *ddb_devnode(struct device *device, mode_t *mode)
1481{
1482 struct ddb *dev = dev_get_drvdata(device);
1483
1484 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
1485}
1486
1487static int ddb_class_create(void)
1488{
1489 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
1490 if (ddb_major < 0)
1491 return ddb_major;
1492
1493 ddb_class = class_create(THIS_MODULE, DDB_NAME);
1494 if (IS_ERR(ddb_class)) {
1495 unregister_chrdev(ddb_major, DDB_NAME);
1496 return -1;
1497 }
1498 ddb_class->devnode = ddb_devnode;
1499 return 0;
1500}
1501
1502static void ddb_class_destroy(void)
1503{
1504 class_destroy(ddb_class);
1505 unregister_chrdev(ddb_major, DDB_NAME);
1506}
1507
1508static int ddb_device_create(struct ddb *dev)
1509{
1510 dev->nr = ddb_num++;
1511 dev->ddb_dev = device_create(ddb_class, NULL,
1512 MKDEV(ddb_major, dev->nr),
1513 dev, "ddbridge%d", dev->nr);
1514 ddbs[dev->nr] = dev;
1515 if (IS_ERR(dev->ddb_dev))
1516 return -1;
1517 return 0;
1518}
1519
1520static void ddb_device_destroy(struct ddb *dev)
1521{
1522 ddb_num--;
1523 if (IS_ERR(dev->ddb_dev))
1524 return;
1525 device_destroy(ddb_class, MKDEV(ddb_major, 0));
1526}
1527
1528
1529/****************************************************************************/
1530/****************************************************************************/
1531/****************************************************************************/
1532
1533static void ddb_unmap(struct ddb *dev)
1534{
1535 if (dev->regs)
1536 iounmap(dev->regs);
1537 vfree(dev);
1538}
1539
1540
1541static void __devexit ddb_remove(struct pci_dev *pdev)
1542{
1543 struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev);
1544
1545 ddb_ports_detach(dev);
1546 ddb_i2c_release(dev);
1547
1548 ddbwritel(0, INTERRUPT_ENABLE);
1549 free_irq(dev->pdev->irq, dev);
1550#ifdef CONFIG_PCI_MSI
1551 if (dev->msi)
1552 pci_disable_msi(dev->pdev);
1553#endif
1554 ddb_ports_release(dev);
1555 ddb_buffers_free(dev);
1556 ddb_device_destroy(dev);
1557
1558 ddb_unmap(dev);
1559 pci_set_drvdata(pdev, 0);
1560 pci_disable_device(pdev);
1561}
1562
1563
1564static int __devinit ddb_probe(struct pci_dev *pdev,
1565 const struct pci_device_id *id)
1566{
1567 struct ddb *dev;
1568 int stat = 0;
1569 int irq_flag = IRQF_SHARED;
1570
1571 if (pci_enable_device(pdev) < 0)
1572 return -ENODEV;
1573
1574 dev = vmalloc(sizeof(struct ddb));
1575 if (dev == NULL)
1576 return -ENOMEM;
1577 memset(dev, 0, sizeof(struct ddb));
1578
1579 dev->pdev = pdev;
1580 pci_set_drvdata(pdev, dev);
1581 dev->info = (struct ddb_info *) id->driver_data;
1582 printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
1583
1584 dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
1585 pci_resource_len(dev->pdev, 0));
1586 if (!dev->regs) {
1587 stat = -ENOMEM;
1588 goto fail;
1589 }
1590 printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
1591
1592#ifdef CONFIG_PCI_MSI
1593 if (pci_msi_enabled())
1594 stat = pci_enable_msi(dev->pdev);
1595 if (stat) {
1596 printk(KERN_INFO ": MSI not available.\n");
1597 } else {
1598 irq_flag = 0;
1599 dev->msi = 1;
1600 }
1601#endif
1602 stat = request_irq(dev->pdev->irq, irq_handler,
1603 irq_flag, "DDBridge", (void *) dev);
1604 if (stat < 0)
1605 goto fail1;
1606 ddbwritel(0, DMA_BASE_WRITE);
1607 ddbwritel(0, DMA_BASE_READ);
1608 ddbwritel(0xffffffff, INTERRUPT_ACK);
1609 ddbwritel(0xfff0f, INTERRUPT_ENABLE);
1610 ddbwritel(0, MSI1_ENABLE);
1611
1612 if (ddb_i2c_init(dev) < 0)
1613 goto fail1;
1614 ddb_ports_init(dev);
1615 if (ddb_buffers_alloc(dev) < 0) {
1616 printk(KERN_INFO ": Could not allocate buffer memory\n");
1617 goto fail2;
1618 }
1619 if (ddb_ports_attach(dev) < 0)
1620 goto fail3;
1621 ddb_device_create(dev);
1622 return 0;
1623
1624fail3:
1625 ddb_ports_detach(dev);
1626 printk(KERN_ERR "fail3\n");
1627 ddb_ports_release(dev);
1628fail2:
1629 printk(KERN_ERR "fail2\n");
1630 ddb_buffers_free(dev);
1631fail1:
1632 printk(KERN_ERR "fail1\n");
1633 if (dev->msi)
1634 pci_disable_msi(dev->pdev);
1635 free_irq(dev->pdev->irq, dev);
1636fail:
1637 printk(KERN_ERR "fail\n");
1638 ddb_unmap(dev);
1639 pci_set_drvdata(pdev, 0);
1640 pci_disable_device(pdev);
1641 return -1;
1642}
1643
1644/******************************************************************************/
1645/******************************************************************************/
1646/******************************************************************************/
1647
1648static struct ddb_info ddb_none = {
1649 .type = DDB_NONE,
1650 .name = "Digital Devices PCIe bridge",
1651};
1652
1653static struct ddb_info ddb_octopus = {
1654 .type = DDB_OCTOPUS,
1655 .name = "Digital Devices Octopus DVB adapter",
1656 .port_num = 4,
1657};
1658
1659static struct ddb_info ddb_octopus_le = {
1660 .type = DDB_OCTOPUS,
1661 .name = "Digital Devices Octopus LE DVB adapter",
1662 .port_num = 2,
1663};
1664
1665static struct ddb_info ddb_v6 = {
1666 .type = DDB_OCTOPUS,
1667 .name = "Digital Devices Cine S2 V6 DVB adapter",
1668 .port_num = 3,
1669};
1670
1671#define DDVID 0xdd01 /* Digital Devices Vendor ID */
1672
1673#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
1674 .vendor = _vend, .device = _dev, \
1675 .subvendor = _subvend, .subdevice = _subdev, \
1676 .driver_data = (unsigned long)&_driverdata }
1677
1678static const struct pci_device_id ddb_id_tbl[] __devinitdata = {
1679 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
1680 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
1681 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
1682 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus),
1683 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
1684 /* in case sub-ids got deleted in flash */
1685 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
1686 {0}
1687};
1688MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
1689
1690
1691static struct pci_driver ddb_pci_driver = {
1692 .name = "DDBridge",
1693 .id_table = ddb_id_tbl,
1694 .probe = ddb_probe,
1695 .remove = ddb_remove,
1696};
1697
1698static __init int module_init_ddbridge(void)
1699{
1700 printk(KERN_INFO "Digital Devices PCIE bridge driver, "
1701 "Copyright (C) 2010-11 Digital Devices GmbH\n");
1702 if (ddb_class_create())
1703 return -1;
1704 return pci_register_driver(&ddb_pci_driver);
1705}
1706
1707static __exit void module_exit_ddbridge(void)
1708{
1709 pci_unregister_driver(&ddb_pci_driver);
1710 ddb_class_destroy();
1711}
1712
1713module_init(module_init_ddbridge);
1714module_exit(module_exit_ddbridge);
1715
1716MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
1717MODULE_AUTHOR("Ralph Metzler");
1718MODULE_LICENSE("GPL");
1719MODULE_VERSION("0.5");
diff --git a/drivers/media/dvb/ddbridge/ddbridge-regs.h b/drivers/media/dvb/ddbridge/ddbridge-regs.h
new file mode 100644
index 00000000000..a3ccb318b50
--- /dev/null
+++ b/drivers/media/dvb/ddbridge/ddbridge-regs.h
@@ -0,0 +1,151 @@
1/*
2 * ddbridge-regs.h: Digital Devices PCIe bridge driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24/* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */
25
26/* Register Definitions */
27
28#define CUR_REGISTERMAP_VERSION 0x10000
29
30#define HARDWARE_VERSION 0x00
31#define REGISTERMAP_VERSION 0x04
32
33/* ------------------------------------------------------------------------- */
34/* SPI Controller */
35
36#define SPI_CONTROL 0x10
37#define SPI_DATA 0x14
38
39/* ------------------------------------------------------------------------- */
40
41/* Interrupt controller */
42/* How many MSI's are available depends on HW (Min 2 max 8) */
43/* How many are usable also depends on Host platform */
44
45#define INTERRUPT_BASE (0x40)
46
47#define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
48#define MSI0_ENABLE (INTERRUPT_BASE + 0x00)
49#define MSI1_ENABLE (INTERRUPT_BASE + 0x04)
50#define MSI2_ENABLE (INTERRUPT_BASE + 0x08)
51#define MSI3_ENABLE (INTERRUPT_BASE + 0x0C)
52#define MSI4_ENABLE (INTERRUPT_BASE + 0x10)
53#define MSI5_ENABLE (INTERRUPT_BASE + 0x14)
54#define MSI6_ENABLE (INTERRUPT_BASE + 0x18)
55#define MSI7_ENABLE (INTERRUPT_BASE + 0x1C)
56
57#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
58#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20)
59
60#define INTMASK_I2C1 (0x00000001)
61#define INTMASK_I2C2 (0x00000002)
62#define INTMASK_I2C3 (0x00000004)
63#define INTMASK_I2C4 (0x00000008)
64
65#define INTMASK_CIRQ1 (0x00000010)
66#define INTMASK_CIRQ2 (0x00000020)
67#define INTMASK_CIRQ3 (0x00000040)
68#define INTMASK_CIRQ4 (0x00000080)
69
70#define INTMASK_TSINPUT1 (0x00000100)
71#define INTMASK_TSINPUT2 (0x00000200)
72#define INTMASK_TSINPUT3 (0x00000400)
73#define INTMASK_TSINPUT4 (0x00000800)
74#define INTMASK_TSINPUT5 (0x00001000)
75#define INTMASK_TSINPUT6 (0x00002000)
76#define INTMASK_TSINPUT7 (0x00004000)
77#define INTMASK_TSINPUT8 (0x00008000)
78
79#define INTMASK_TSOUTPUT1 (0x00010000)
80#define INTMASK_TSOUTPUT2 (0x00020000)
81#define INTMASK_TSOUTPUT3 (0x00040000)
82#define INTMASK_TSOUTPUT4 (0x00080000)
83
84/* ------------------------------------------------------------------------- */
85/* I2C Master Controller */
86
87#define I2C_BASE (0x80) /* Byte offset */
88
89#define I2C_COMMAND (0x00)
90#define I2C_TIMING (0x04)
91#define I2C_TASKLENGTH (0x08) /* High read, low write */
92#define I2C_TASKADDRESS (0x0C) /* High read, low write */
93
94#define I2C_MONITOR (0x1C)
95
96#define I2C_BASE_1 (I2C_BASE + 0x00)
97#define I2C_BASE_2 (I2C_BASE + 0x20)
98#define I2C_BASE_3 (I2C_BASE + 0x40)
99#define I2C_BASE_4 (I2C_BASE + 0x60)
100
101#define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20)
102
103#define I2C_TASKMEM_BASE (0x1000) /* Byte offset */
104#define I2C_TASKMEM_SIZE (0x1000)
105
106#define I2C_SPEED_400 (0x04030404)
107#define I2C_SPEED_200 (0x09080909)
108#define I2C_SPEED_154 (0x0C0B0C0C)
109#define I2C_SPEED_100 (0x13121313)
110#define I2C_SPEED_77 (0x19181919)
111#define I2C_SPEED_50 (0x27262727)
112
113
114/* ------------------------------------------------------------------------- */
115/* DMA Controller */
116
117#define DMA_BASE_WRITE (0x100)
118#define DMA_BASE_READ (0x140)
119
120#define DMA_CONTROL (0x00) /* 64 */
121#define DMA_ERROR (0x04) /* 65 ( only read instance ) */
122
123#define DMA_DIAG_CONTROL (0x1C) /* 71 */
124#define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */
125#define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */
126#define DMA_DIAG_TIMECOUNTER_LOW (0x28) /* 74 */
127#define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) /* 75 */
128#define DMA_DIAG_RECHECKCOUNTER (0x30) /* 76 ( Split completions on read ) */
129#define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */
130#define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */
131#define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */
132
133/* ------------------------------------------------------------------------- */
134/* DMA Buffer */
135
136#define TS_INPUT_BASE (0x200)
137#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00)
138
139#define TS_OUTPUT_BASE (0x280)
140#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 16 + 0x00)
141
142#define DMA_BUFFER_BASE (0x300)
143
144#define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 16 + 0x00)
145#define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 16 + 0x04)
146#define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 16 + 0x08)
147#define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 16 + 0x0c)
148
149#define DMA_BASE_ADDRESS_TABLE (0x2000)
150#define DMA_BASE_ADDRESS_TABLE_ENTRIES (512)
151
diff --git a/drivers/media/dvb/ddbridge/ddbridge.h b/drivers/media/dvb/ddbridge/ddbridge.h
new file mode 100644
index 00000000000..6d14893218f
--- /dev/null
+++ b/drivers/media/dvb/ddbridge/ddbridge.h
@@ -0,0 +1,187 @@
1/*
2 * ddbridge.h: Digital Devices PCIe bridge driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef _DDBRIDGE_H_
25#define _DDBRIDGE_H_
26
27#include <linux/types.h>
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/i2c.h>
31#include <linux/mutex.h>
32#include <asm/dma.h>
33#include <linux/dvb/frontend.h>
34#include <linux/dvb/ca.h>
35#include <linux/dvb/video.h>
36#include <linux/dvb/audio.h>
37#include <linux/socket.h>
38
39#include "dmxdev.h"
40#include "dvbdev.h"
41#include "dvb_demux.h"
42#include "dvb_frontend.h"
43#include "dvb_ringbuffer.h"
44#include "dvb_ca_en50221.h"
45#include "dvb_net.h"
46#include "cxd2099.h"
47
48#define DDB_MAX_I2C 4
49#define DDB_MAX_PORT 4
50#define DDB_MAX_INPUT 8
51#define DDB_MAX_OUTPUT 4
52
53struct ddb_info {
54 int type;
55#define DDB_NONE 0
56#define DDB_OCTOPUS 1
57 char *name;
58 int port_num;
59 u32 port_type[DDB_MAX_PORT];
60};
61
62/* DMA_SIZE MUST be divisible by 188 and 128 !!! */
63
64#define INPUT_DMA_MAX_BUFS 32 /* hardware table limit */
65#define INPUT_DMA_BUFS 8
66#define INPUT_DMA_SIZE (128*47*21)
67
68#define OUTPUT_DMA_MAX_BUFS 32
69#define OUTPUT_DMA_BUFS 8
70#define OUTPUT_DMA_SIZE (128*47*21)
71
72struct ddb;
73struct ddb_port;
74
75struct ddb_input {
76 struct ddb_port *port;
77 u32 nr;
78 int attached;
79
80 dma_addr_t pbuf[INPUT_DMA_MAX_BUFS];
81 u8 *vbuf[INPUT_DMA_MAX_BUFS];
82 u32 dma_buf_num;
83 u32 dma_buf_size;
84
85 struct tasklet_struct tasklet;
86 spinlock_t lock;
87 wait_queue_head_t wq;
88 int running;
89 u32 stat;
90 u32 cbuf;
91 u32 coff;
92
93 struct dvb_adapter adap;
94 struct dvb_device *dev;
95 struct dvb_frontend *fe;
96 struct dvb_frontend *fe2;
97 struct dmxdev dmxdev;
98 struct dvb_demux demux;
99 struct dvb_net dvbnet;
100 struct dmx_frontend hw_frontend;
101 struct dmx_frontend mem_frontend;
102 int users;
103 int (*gate_ctrl)(struct dvb_frontend *, int);
104};
105
106struct ddb_output {
107 struct ddb_port *port;
108 u32 nr;
109 dma_addr_t pbuf[OUTPUT_DMA_MAX_BUFS];
110 u8 *vbuf[OUTPUT_DMA_MAX_BUFS];
111 u32 dma_buf_num;
112 u32 dma_buf_size;
113 struct tasklet_struct tasklet;
114 spinlock_t lock;
115 wait_queue_head_t wq;
116 int running;
117 u32 stat;
118 u32 cbuf;
119 u32 coff;
120
121 struct dvb_adapter adap;
122 struct dvb_device *dev;
123};
124
125struct ddb_i2c {
126 struct ddb *dev;
127 u32 nr;
128 struct i2c_adapter adap;
129 struct i2c_adapter adap2;
130 u32 regs;
131 u32 rbuf;
132 u32 wbuf;
133 int done;
134 wait_queue_head_t wq;
135};
136
137struct ddb_port {
138 struct ddb *dev;
139 u32 nr;
140 struct ddb_i2c *i2c;
141 struct mutex i2c_gate_lock;
142 u32 class;
143#define DDB_PORT_NONE 0
144#define DDB_PORT_CI 1
145#define DDB_PORT_TUNER 2
146 u32 type;
147#define DDB_TUNER_NONE 0
148#define DDB_TUNER_DVBS_ST 1
149#define DDB_TUNER_DVBS_ST_AA 2
150#define DDB_TUNER_DVBCT_TR 16
151#define DDB_TUNER_DVBCT_ST 17
152 u32 adr;
153
154 struct ddb_input *input[2];
155 struct ddb_output *output;
156 struct dvb_ca_en50221 *en;
157};
158
159struct ddb {
160 struct pci_dev *pdev;
161 unsigned char *regs;
162 struct ddb_port port[DDB_MAX_PORT];
163 struct ddb_i2c i2c[DDB_MAX_I2C];
164 struct ddb_input input[DDB_MAX_INPUT];
165 struct ddb_output output[DDB_MAX_OUTPUT];
166
167 struct device *ddb_dev;
168 int nr;
169 u8 iobuf[1028];
170
171 struct ddb_info *info;
172 int msi;
173};
174
175/****************************************************************************/
176
177#define ddbwritel(_val, _adr) writel((_val), \
178 (char *) (dev->regs+(_adr)))
179#define ddbreadl(_adr) readl((char *) (dev->regs+(_adr)))
180#define ddbcpyto(_adr, _src, _count) memcpy_toio((char *) \
181 (dev->regs+(_adr)), (_src), (_count))
182#define ddbcpyfrom(_dst, _adr, _count) memcpy_fromio((_dst), (char *) \
183 (dev->regs+(_adr)), (_count))
184
185/****************************************************************************/
186
187#endif
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