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path: root/drivers/infiniband/hw/nes/nes_hw.c
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Diffstat (limited to 'drivers/infiniband/hw/nes/nes_hw.c')
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.c30
1 files changed, 18 insertions, 12 deletions
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index d6fc9ae4406..b832a7b814a 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -550,11 +550,8 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
550 msleep(1); 550 msleep(1);
551 } 551 }
552 if (int_cnt > 1) { 552 if (int_cnt > 1) {
553 u32 sds;
554 spin_lock_irqsave(&nesadapter->phy_lock, flags); 553 spin_lock_irqsave(&nesadapter->phy_lock, flags);
555 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); 554 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
556 sds |= 0x00000040;
557 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
558 mh_detected++; 555 mh_detected++;
559 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET); 556 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
560 reset_value |= 0x0000003d; 557 reset_value |= 0x0000003d;
@@ -579,7 +576,7 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
579 if (++ext_cnt > int_cnt) { 576 if (++ext_cnt > int_cnt) {
580 spin_lock_irqsave(&nesadapter->phy_lock, flags); 577 spin_lock_irqsave(&nesadapter->phy_lock, flags);
581 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 578 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1,
582 0x0000F0C8); 579 0x0000F088);
583 mh_detected++; 580 mh_detected++;
584 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET); 581 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
585 reset_value |= 0x0000003d; 582 reset_value |= 0x0000003d;
@@ -764,6 +761,9 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
764 return 0; 761 return 0;
765 762
766 /* init serdes 1 */ 763 /* init serdes 1 */
764 if (!(OneG_Mode && (nesadapter->phy_type[1] != NES_PHY_TYPE_PUMA_1G)))
765 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
766
767 switch (nesadapter->phy_type[1]) { 767 switch (nesadapter->phy_type[1]) {
768 case NES_PHY_TYPE_ARGUS: 768 case NES_PHY_TYPE_ARGUS:
769 case NES_PHY_TYPE_SFP_D: 769 case NES_PHY_TYPE_SFP_D:
@@ -771,21 +771,20 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
771 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000); 771 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
772 break; 772 break;
773 case NES_PHY_TYPE_CX4: 773 case NES_PHY_TYPE_CX4:
774 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
775 sds &= 0xFFFFFFBF;
776 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
777 if (wide_ppm_offset) 774 if (wide_ppm_offset)
778 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA); 775 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA);
779 else
780 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
781 break; 776 break;
782 case NES_PHY_TYPE_PUMA_1G: 777 case NES_PHY_TYPE_PUMA_1G:
783 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); 778 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
784 sds |= 0x000000100; 779 sds |= 0x000000100;
785 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds); 780 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
786 } 781 }
787 if (!OneG_Mode) 782 if (!OneG_Mode) {
788 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000); 783 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
784 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
785 sds &= 0xFFFFFFBF;
786 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
787 }
789 } else { 788 } else {
790 /* init serdes 0 */ 789 /* init serdes 0 */
791 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008); 790 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
@@ -913,6 +912,12 @@ static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_cou
913 u32temp &= 0x7fffffff; 912 u32temp &= 0x7fffffff;
914 u32temp |= 0x7fff0010; 913 u32temp |= 0x7fff0010;
915 nes_write_indexed(nesdev, 0x000021f8, u32temp); 914 nes_write_indexed(nesdev, 0x000021f8, u32temp);
915 if (port_count > 1) {
916 u32temp = nes_read_indexed(nesdev, 0x000023f8);
917 u32temp &= 0x7fffffff;
918 u32temp |= 0x7fff0010;
919 nes_write_indexed(nesdev, 0x000023f8, u32temp);
920 }
916 } 921 }
917} 922}
918 923
@@ -1366,13 +1371,14 @@ int nes_init_phy(struct nes_device *nesdev)
1366 if (phy_type == NES_PHY_TYPE_ARGUS) { 1371 if (phy_type == NES_PHY_TYPE_ARGUS) {
1367 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C); 1372 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1368 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008); 1373 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
1374 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1369 } else { 1375 } else {
1370 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004); 1376 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004);
1371 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038); 1377 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038);
1378 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1372 } 1379 }
1373 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098); 1380 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1374 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); 1381 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1375 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1376 1382
1377 /* setup LEDs */ 1383 /* setup LEDs */
1378 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007); 1384 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);