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path: root/drivers/i2c/busses/i2c-slave-tegra.c
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Diffstat (limited to 'drivers/i2c/busses/i2c-slave-tegra.c')
-rw-r--r--drivers/i2c/busses/i2c-slave-tegra.c1114
1 files changed, 1114 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-slave-tegra.c b/drivers/i2c/busses/i2c-slave-tegra.c
new file mode 100644
index 00000000000..f2468d85c1f
--- /dev/null
+++ b/drivers/i2c/busses/i2c-slave-tegra.c
@@ -0,0 +1,1114 @@
1/*
2 * drivers/i2c/busses/i2c-slave-tegra.c
3 * I2c slave driver for the Nvidia's tegra SOC.
4 *
5 * Copyright (c) 2009-2011, NVIDIA Corporation.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18/*#define DEBUG 1*/
19/*#define VERBOSE_DEBUG 1*/
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/clk.h>
25#include <linux/i2c.h>
26#include <linux/io.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/slab.h>
30#include <linux/spinlock.h>
31#include <linux/i2c-tegra.h>
32#include <linux/i2c-slave.h>
33#include <asm/unaligned.h>
34#include <mach/clk.h>
35#include <mach/pinmux.h>
36#include <linux/pm_runtime.h>
37#define BYTES_PER_FIFO_WORD 4
38#define to_jiffies(msecs) msecs_to_jiffies(msecs)
39
40#define I2C_CNFG 0x000
41#define I2C_CNFG_PACKET_MODE_EN (1<<10)
42#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
43#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
44#define I2C_CNFG_DEBOUNCE_CNT_MASK (0x7)
45
46#define I2C_STATUS 0x01C
47
48#define I2C_SLV_CNFG 0x020
49#define I2C_SLV_CNFG_NEWSL (1<<2)
50#define I2C_SLV_CNFG_ENABLE_SL (1<<3)
51#define I2C_SLV_CNFG_PKT_MODE_EN (1<<4)
52#define I2C_SLV_CNFG_FIFO_XFER_EN (1<<20)
53#define I2C_SLV_CNFG_ACK_LAST_BYTE (1<<6)
54#define I2C_SLV_CNFG_ACK_LAST_BYTE_VALID (1<<7)
55
56#define I2C_SLV_ADDR1 0x02c
57#define I2C_SLV_ADDR1_ADDR_SHIFT 0x0
58
59#define I2C_SLV_ADDR2 0x030
60#define I2C_SLV_ADDR2_ADDR0_HI_SHIFT 0x1
61#define I2C_SLV_ADDR2_ADDR0_MASK 0x7
62#define I2C_SLV_ADDR2_ADDR0_TEN_BIT_ADDR_MODE 0x1
63
64#define I2C_SLV_INT_MASK 0x040
65
66#define I2C_TX_FIFO 0x050
67#define I2C_RX_FIFO 0x054
68#define I2C_PACKET_TRANSFER_STATUS 0x058
69
70#define I2C_FIFO_CONTROL 0x05c
71#define I2C_FIFO_CONTROL_SLV_TX_FLUSH (1<<9)
72#define I2C_FIFO_CONTROL_SLV_RX_FLUSH (1<<8)
73#define I2C_FIFO_CONTROL_SLV_TX_TRIG_SHIFT 13
74#define I2C_FIFO_CONTROL_SLV_TX_TRIG_MASK (0x7 << 13)
75#define I2C_FIFO_CONTROL_SLV_RX_TRIG_SHIFT 10
76#define I2C_FIFO_CONTROL_SLV_RX_TRIG_MASK (1 << 10)
77
78#define I2C_FIFO_STATUS 0x060
79#define I2C_FIFO_STATUS_SLV_TX_MASK (0xF << 20)
80#define I2C_FIFO_STATUS_SLV_TX_SHIFT 20
81#define I2C_FIFO_STATUS_SLV_RX_MASK (0x0F << 16)
82#define I2C_FIFO_STATUS_SLV_RX_SHIFT 16
83
84#define I2C_INT_MASK 0x064
85#define I2C_INT_STATUS 0x068
86#define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
87#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
88#define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
89#define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
90#define I2C_INT_NO_ACK (1<<3)
91#define I2C_INT_ARBITRATION_LOST (1<<2)
92#define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
93#define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
94
95#define I2C_INT_SLV_PKT_XFER_ERR (1 << 25)
96#define I2C_INT_SLV_TX_BUFFER_REQ (1 << 24)
97#define I2C_INT_SLV_RX_BUFFER_FILLED (1 << 23)
98#define I2C_INT_SLV_PACKET_XFER_COMPLETE (1 << 22)
99#define I2C_INT_SLV_TFIFO_OVF_REQ (1 << 21)
100#define I2C_INT_SLV_RFIFO_UNF_REQ (1 << 20)
101#define I2C_INT_SLV_TFIFO_DATA_REQ (1 << 17)
102#define I2C_INT_SLV_RFIFO_DATA_REQ (1 << 16)
103
104#define I2C_SLV_TX_FIFO 0x078
105#define I2C_SLV_RX_FIFO 0x07c
106
107#define I2C_SLV_PACKET_STATUS 0x80
108#define I2C_SLV_PACKET_STATUS_BYTENUM_SHIFT 4
109#define I2C_SLV_PACKET_STATUS_BYTENUM_MASK 0xFFF0
110
111#define I2C_CLK_DIVISOR 0x06c
112
113#define DVC_CTRL_REG1 0x000
114#define DVC_CTRL_REG1_INTR_EN (1<<10)
115#define DVC_CTRL_REG2 0x004
116#define DVC_CTRL_REG3 0x008
117#define DVC_CTRL_REG3_SW_PROG (1<<26)
118#define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
119#define DVC_STATUS 0x00c
120#define DVC_STATUS_I2C_DONE_INTR (1<<30)
121
122#define I2C_ERR_NONE 0x00
123#define I2C_ERR_NO_ACK 0x01
124#define I2C_ERR_ARBITRATION_LOST 0x02
125#define I2C_ERR_UNKNOWN_INTERRUPT 0x04
126
127#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
128#define PACKET_HEADER0_PACKET_ID_SHIFT 16
129#define PACKET_HEADER0_CONT_ID_SHIFT 12
130#define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
131
132#define I2C_HEADER_HIGHSPEED_MODE (1<<22)
133#define I2C_HEADER_CONT_ON_NAK (1<<21)
134#define I2C_HEADER_SEND_START_BYTE (1<<20)
135#define I2C_HEADER_READ (1<<19)
136#define I2C_HEADER_10BIT_ADDR (1<<18)
137#define I2C_HEADER_IE_ENABLE (1<<17)
138#define I2C_HEADER_REPEAT_START (1<<16)
139#define I2C_HEADER_MASTER_ADDR_SHIFT 12
140#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
141
142#define I2C_FIFO_DEPTH 8
143/* Transfer state of the i2c slave */
144#define TRANSFER_STATE_NONE 0
145#define TRANSFER_STATE_READ 1
146#define TRANSFER_STATE_WRITE 2
147
148#define I2C_SLV_TRANS_PREMATURE_END I2C_INT_SLV_PKT_XFER_ERR
149
150#define I2C_SLV_TRANS_ALL_XFER_END I2C_INT_SLV_PACKET_XFER_COMPLETE
151
152#define I2C_SLV_TRANS_END \
153 (I2C_INT_SLV_PKT_XFER_ERR | I2C_INT_SLV_PACKET_XFER_COMPLETE)
154
155#define I2C_INT_STATUS_RX_BUFFER_FILLED I2C_INT_SLV_RX_BUFFER_FILLED
156
157#define I2C_INT_STATUS_RX_DATA_AVAILABLE \
158 (I2C_INT_SLV_RX_BUFFER_FILLED | I2C_INT_SLV_RFIFO_DATA_REQ)
159
160#define I2C_INT_STATUS_TX_BUFFER_REQUEST \
161 (I2C_INT_SLV_TX_BUFFER_REQ | I2C_INT_SLV_TFIFO_DATA_REQ)
162
163#define I2C_SLV_ERRORS_INT_MASK (I2C_INT_SLV_TFIFO_OVF_REQ | \
164 I2C_INT_SLV_RFIFO_UNF_REQ | I2C_INT_SLV_PKT_XFER_ERR)
165
166#define I2C_SLV_DEFAULT_INT_MASK (I2C_INT_SLV_TFIFO_OVF_REQ | \
167 I2C_INT_SLV_RFIFO_UNF_REQ | I2C_INT_SLV_PKT_XFER_ERR | \
168 I2C_INT_SLV_RX_BUFFER_FILLED | I2C_INT_SLV_TX_BUFFER_REQ)
169
170struct tegra_i2c_slave_dev;
171
172struct tegra_i2c_slave_bus {
173 struct tegra_i2c_slave_dev *dev;
174 const struct tegra_pingroup_config *pinmux;
175 int mux_len;
176 unsigned long bus_clk_rate;
177 struct i2c_slave_adapter slv_adap;
178};
179
180struct tegra_i2c_slave_dev {
181 struct device *dev;
182 struct clk *clk;
183 struct resource *iomem;
184 void __iomem *base;
185 int cont_id;
186 int irq;
187 spinlock_t lock;
188 struct completion rx_msg_complete;
189 struct completion tx_msg_complete;
190 bool is_rx_waiting;
191 bool is_tx_waiting;
192 u8 *rx_msg_buff;
193 int rx_msg_buf_size;
194 int rx_msg_head;
195 int rx_msg_tail;
196 u8 *tx_msg_buff;
197 int tx_msg_buf_size;
198 int tx_msg_head;
199 int tx_msg_tail;
200 bool is_slave_started;
201 int slave_add;
202 bool is_ten_bit_addr;
203 u32 dummy_word;
204 unsigned long rx_pack_hdr1;
205 unsigned long rx_pack_hdr2;
206 unsigned long rx_pack_hdr3;
207 int curr_transfer;
208 unsigned long int_mask;
209 int nack_packet_count;
210 bool is_first_byte_read_wait;
211 int curr_packet_bytes_read;
212 unsigned int cont_status;
213 bool is_dummy_char_cycle;
214 unsigned long curr_packet_tx_tail;
215 const struct tegra_pingroup_config *pin_mux;
216 int bus_clk;
217 struct tegra_i2c_slave_bus bus;
218};
219
220#define get_space_count(rInd, wInd, maxsize) \
221 (((wInd > rInd) ? (maxsize - wInd + rInd) : (rInd - wInd)) - 1)
222
223#define get_data_count(rInd, wInd, maxsize) \
224 ((wInd >= rInd) ? (wInd - rInd) : (maxsize - rInd + wInd - 1))
225
226static void set_tx_trigger_level(struct tegra_i2c_slave_dev *i2c_dev, int trig)
227{
228 unsigned long fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
229 if (trig) {
230 fifo_control &= ~I2C_FIFO_CONTROL_SLV_TX_TRIG_MASK;
231 fifo_control |= (trig-1) << I2C_FIFO_CONTROL_SLV_TX_TRIG_SHIFT;
232 writel(fifo_control, i2c_dev->base + I2C_FIFO_CONTROL);
233 }
234}
235
236static void set_rx_trigger_level(struct tegra_i2c_slave_dev *i2c_dev, int trig)
237{
238 unsigned long fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
239 if (trig) {
240 fifo_control &= ~I2C_FIFO_CONTROL_SLV_RX_TRIG_MASK;
241 fifo_control |= (trig-1) << I2C_FIFO_CONTROL_SLV_RX_TRIG_SHIFT;
242 writel(fifo_control, i2c_dev->base + I2C_FIFO_CONTROL);
243 }
244}
245
246static void reset_slave_tx_fifo(struct tegra_i2c_slave_dev *i2c_dev)
247{
248 unsigned long fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
249 unsigned long timeout_count = 1000;
250
251 writel(fifo_control | I2C_FIFO_CONTROL_SLV_TX_FLUSH,
252 i2c_dev->base + I2C_FIFO_CONTROL);
253 while (timeout_count--) {
254 fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
255 if (!(fifo_control & I2C_FIFO_CONTROL_SLV_TX_FLUSH))
256 break;
257 udelay(1);
258 }
259 if (!timeout_count) {
260 dev_err(i2c_dev->dev, "Not able to flush tx fifo\n");
261 BUG();
262 }
263}
264
265static void do_tx_fifo_empty(struct tegra_i2c_slave_dev *i2c_dev,
266 unsigned long *empty_count)
267{
268 unsigned long fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
269 unsigned long tx_fifo_empty_count;
270
271 tx_fifo_empty_count = (fifo_status & I2C_FIFO_STATUS_SLV_TX_MASK) >>
272 I2C_FIFO_STATUS_SLV_TX_SHIFT;
273 if (tx_fifo_empty_count < I2C_FIFO_DEPTH)
274 reset_slave_tx_fifo(i2c_dev);
275 if (empty_count)
276 *empty_count = tx_fifo_empty_count;
277}
278
279static void get_packet_headers(struct tegra_i2c_slave_dev *i2c_dev, u32 msg_len,
280 u32 flags, unsigned long *packet_header1,
281 unsigned long *packet_header2, unsigned long *packet_header3)
282{
283 unsigned long packet_header;
284 *packet_header1 = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
285 PACKET_HEADER0_PROTOCOL_I2C |
286 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
287 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
288 *packet_header2 = msg_len-1;
289 if (i2c_dev->is_ten_bit_addr)
290 packet_header = i2c_dev->slave_add | I2C_HEADER_10BIT_ADDR;
291 else
292 packet_header = i2c_dev->slave_add <<
293 I2C_HEADER_SLAVE_ADDR_SHIFT;
294
295 if (flags & I2C_M_RD)
296 packet_header |= I2C_HEADER_READ;
297
298 *packet_header3 = packet_header;
299}
300
301static void configure_i2c_slave_packet_mode(struct tegra_i2c_slave_dev *i2c_dev)
302{
303 unsigned long i2c_config;
304 i2c_config = I2C_CNFG_PACKET_MODE_EN | I2C_CNFG_NEW_MASTER_FSM;
305 i2c_config |= (2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
306 writel(i2c_config, i2c_dev->base + I2C_CNFG);
307}
308
309static void configure_i2c_slave_address(struct tegra_i2c_slave_dev *i2c_dev)
310{
311
312 unsigned long slave_add_reg;
313 unsigned long i2c_slv_config;
314 unsigned long slave_add;
315
316 if (i2c_dev->is_ten_bit_addr) {
317 slave_add = i2c_dev->slave_add & 0xFF;
318 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR1);
319 slave_add_reg &= ~(0xFF);
320 slave_add_reg |= slave_add << I2C_SLV_ADDR1_ADDR_SHIFT;
321 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR1);
322
323 slave_add = (i2c_dev->slave_add >> 8) & 0x3;
324 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR2);
325 slave_add_reg &= ~I2C_SLV_ADDR2_ADDR0_MASK;
326 slave_add_reg |= slave_add |
327 I2C_SLV_ADDR2_ADDR0_TEN_BIT_ADDR_MODE;
328 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR2);
329 } else {
330 slave_add = (i2c_dev->slave_add & 0x3FF);
331 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR1);
332 slave_add_reg &= ~(0x3FF);
333 slave_add_reg |= slave_add << I2C_SLV_ADDR1_ADDR_SHIFT;
334 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR1);
335
336 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR2);
337 slave_add_reg &= ~I2C_SLV_ADDR2_ADDR0_MASK;
338 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR2);
339 }
340
341 i2c_slv_config = I2C_SLV_CNFG_NEWSL;
342 if (i2c_dev->slave_add) {
343 i2c_slv_config = I2C_SLV_CNFG_ENABLE_SL |
344 I2C_SLV_CNFG_PKT_MODE_EN |
345 I2C_SLV_CNFG_FIFO_XFER_EN;
346 }
347 writel(i2c_slv_config, i2c_dev->base + I2C_SLV_CNFG);
348}
349
350static void copy_rx_data(struct tegra_i2c_slave_dev *i2c_dev, u8 rcv_char)
351{
352 if (get_space_count(i2c_dev->rx_msg_tail, i2c_dev->rx_msg_head,
353 i2c_dev->rx_msg_buf_size)){
354 i2c_dev->rx_msg_buff[i2c_dev->rx_msg_head++] = rcv_char;
355 if (i2c_dev->rx_msg_head == i2c_dev->rx_msg_buf_size)
356 i2c_dev->rx_msg_head = 0;
357 } else {
358 dev_warn(i2c_dev->dev, "The slave rx buffer is full, ignoring "
359 "new receive data\n");
360 }
361}
362
363static void handle_packet_first_byte_read(struct tegra_i2c_slave_dev *i2c_dev)
364{
365 unsigned long fifo_status;
366 int filled_slots;
367 unsigned long i2c_sl_config;
368 unsigned long recv_data;
369
370 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
371 filled_slots = (fifo_status & I2C_FIFO_STATUS_SLV_RX_MASK) >>
372 I2C_FIFO_STATUS_SLV_RX_SHIFT;
373
374 writel(I2C_INT_STATUS_RX_DATA_AVAILABLE,
375 i2c_dev->base + I2C_INT_STATUS);
376 if (unlikely(filled_slots != 1)) {
377 dev_err(i2c_dev->dev, "Unexpected number of filed slots %d",
378 filled_slots);
379 BUG();
380 }
381 recv_data = readl(i2c_dev->base + I2C_SLV_RX_FIFO);
382 copy_rx_data(i2c_dev, (u8)recv_data);
383
384 i2c_dev->is_first_byte_read_wait = false;
385 i2c_dev->curr_transfer = TRANSFER_STATE_READ;
386 i2c_dev->curr_packet_bytes_read = 0;
387
388 /* Write packet Header */
389 writel(i2c_dev->rx_pack_hdr1, i2c_dev->base + I2C_SLV_TX_FIFO);
390 writel(i2c_dev->rx_pack_hdr2, i2c_dev->base + I2C_SLV_TX_FIFO);
391 writel(i2c_dev->rx_pack_hdr3, i2c_dev->base + I2C_SLV_TX_FIFO);
392
393 set_rx_trigger_level(i2c_dev, 4);
394 i2c_dev->int_mask |= I2C_INT_SLV_RFIFO_DATA_REQ;
395 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
396
397 /* Ack the master */
398 i2c_sl_config = readl(i2c_dev->base + I2C_SLV_CNFG);
399 i2c_sl_config |= I2C_SLV_CNFG_ACK_LAST_BYTE |
400 I2C_SLV_CNFG_ACK_LAST_BYTE_VALID;
401 writel(i2c_sl_config, i2c_dev->base + I2C_SLV_CNFG);
402}
403
404static void handle_packet_byte_read(struct tegra_i2c_slave_dev *i2c_dev)
405{
406 unsigned long fifo_status;
407 int i, j;
408 int filled_slots;
409 unsigned long recv_data;
410 int curr_xfer_size;
411
412 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
413 filled_slots = (fifo_status & I2C_FIFO_STATUS_SLV_RX_MASK) >>
414 I2C_FIFO_STATUS_SLV_RX_SHIFT;
415
416 curr_xfer_size = BYTES_PER_FIFO_WORD * filled_slots;
417 if (i2c_dev->cont_status & I2C_SLV_TRANS_PREMATURE_END) {
418 curr_xfer_size = readl(i2c_dev->base + I2C_SLV_PACKET_STATUS);
419 curr_xfer_size =
420 (curr_xfer_size & I2C_SLV_PACKET_STATUS_BYTENUM_MASK) >>
421 I2C_SLV_PACKET_STATUS_BYTENUM_SHIFT;
422
423 BUG_ON(filled_slots != ((curr_xfer_size -
424 i2c_dev->curr_packet_bytes_read + 3) >> 2));
425 curr_xfer_size -= i2c_dev->curr_packet_bytes_read;
426 }
427
428 i2c_dev->curr_packet_bytes_read += curr_xfer_size;
429 for (i = 0; i < filled_slots; ++i) {
430 recv_data = readl(i2c_dev->base + I2C_SLV_RX_FIFO);
431 for (j = 0; j < BYTES_PER_FIFO_WORD; ++j) {
432 copy_rx_data(i2c_dev, (u8)(recv_data >> j*8));
433 curr_xfer_size--;
434 if (!curr_xfer_size)
435 break;
436 }
437 }
438 if (i2c_dev->cont_status & I2C_SLV_TRANS_PREMATURE_END) {
439 writel(I2C_SLV_TRANS_END | I2C_INT_STATUS_RX_BUFFER_FILLED,
440 i2c_dev->base + I2C_INT_STATUS);
441
442 i2c_dev->is_first_byte_read_wait = true;
443 i2c_dev->curr_transfer = TRANSFER_STATE_NONE;
444 i2c_dev->curr_packet_bytes_read = 0;
445 set_rx_trigger_level(i2c_dev, 1);
446 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
447 i2c_dev->int_mask = I2C_SLV_DEFAULT_INT_MASK;
448 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
449 }
450}
451
452static void handle_rx_interrupt(struct tegra_i2c_slave_dev *i2c_dev)
453{
454 if (i2c_dev->is_first_byte_read_wait)
455 handle_packet_first_byte_read(i2c_dev);
456 else
457 handle_packet_byte_read(i2c_dev);
458
459 if (i2c_dev->is_rx_waiting) {
460 complete(&i2c_dev->rx_msg_complete);
461 i2c_dev->is_rx_waiting = false;
462 }
463}
464
465static void handle_tx_transaction_end(struct tegra_i2c_slave_dev *i2c_dev)
466{
467 unsigned long curr_packet_size;
468
469 i2c_dev->curr_transfer = TRANSFER_STATE_NONE;
470 curr_packet_size = readl(i2c_dev->base + I2C_SLV_PACKET_STATUS);
471 curr_packet_size =
472 (curr_packet_size & I2C_SLV_PACKET_STATUS_BYTENUM_MASK) >>
473 I2C_SLV_PACKET_STATUS_BYTENUM_SHIFT;
474
475 /* Get transfer count from request size.*/
476 if ((curr_packet_size == 0) &&
477 (i2c_dev->cont_status & I2C_SLV_TRANS_ALL_XFER_END) &&
478 (!(i2c_dev->cont_status & I2C_SLV_TRANS_PREMATURE_END))) {
479 if (!i2c_dev->is_dummy_char_cycle)
480 i2c_dev->tx_msg_tail = i2c_dev->curr_packet_tx_tail;
481 } else {
482 if (!i2c_dev->is_dummy_char_cycle) {
483 i2c_dev->tx_msg_tail += curr_packet_size;
484 if (i2c_dev->tx_msg_tail >= i2c_dev->tx_msg_buf_size)
485 i2c_dev->tx_msg_tail -=
486 i2c_dev->tx_msg_buf_size;
487 }
488 }
489 writel(I2C_SLV_TRANS_END, i2c_dev->base + I2C_INT_STATUS);
490
491 i2c_dev->curr_transfer = TRANSFER_STATE_NONE;
492 set_tx_trigger_level(i2c_dev, 1);
493 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
494 i2c_dev->int_mask = I2C_SLV_DEFAULT_INT_MASK;
495 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
496 if (i2c_dev->is_tx_waiting) {
497 complete(&i2c_dev->tx_msg_complete);
498 i2c_dev->is_tx_waiting = false;
499 }
500}
501
502static void handle_tx_trigger_int(struct tegra_i2c_slave_dev *i2c_dev)
503{
504 unsigned long fifo_status;
505 int empty_slots;
506 int i, j;
507 int data_available;
508 unsigned long header1, header2, header3;
509 unsigned long tx_data;
510 int word_to_write;
511 int bytes_remain;
512 int bytes_in_curr_word;
513 int tx_tail;
514 int packet_len;
515
516 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
517 empty_slots = (fifo_status & I2C_FIFO_STATUS_SLV_TX_MASK) >>
518 I2C_FIFO_STATUS_SLV_TX_SHIFT;
519 BUG_ON(empty_slots <= 3);
520 if (i2c_dev->curr_transfer == TRANSFER_STATE_NONE) {
521 empty_slots -= 3;
522
523 /* Clear the tfifo request. */
524 writel(I2C_INT_STATUS_TX_BUFFER_REQUEST,
525 i2c_dev->base + I2C_INT_STATUS);
526
527 /* Get Number of bytes it can transfer in current */
528 data_available = get_data_count(i2c_dev->tx_msg_tail,
529 i2c_dev->tx_msg_head, i2c_dev->tx_msg_buf_size);
530 if (data_available)
531 packet_len = min(empty_slots*BYTES_PER_FIFO_WORD,
532 data_available);
533 else
534 packet_len = empty_slots*BYTES_PER_FIFO_WORD;
535
536 get_packet_headers(i2c_dev, packet_len, I2C_M_RD,
537 &header1, &header2, &header3);
538
539 /* Write packet Header */
540 writel(header1, i2c_dev->base + I2C_SLV_TX_FIFO);
541 writel(header2, i2c_dev->base + I2C_SLV_TX_FIFO);
542 writel(header3, i2c_dev->base + I2C_SLV_TX_FIFO);
543
544 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
545 if (data_available) {
546 word_to_write = (packet_len + 3) >> 2;
547 bytes_remain = packet_len;
548 tx_tail = i2c_dev->tx_msg_tail;
549 for (i = 0; i < word_to_write; i++) {
550 bytes_in_curr_word =
551 min(bytes_remain, BYTES_PER_FIFO_WORD);
552 tx_data = 0;
553 for (j = 0; j < bytes_in_curr_word; ++j) {
554 tx_data |= (i2c_dev->tx_msg_buff[
555 tx_tail++]<<(j*8));
556 if (tx_tail >= i2c_dev->tx_msg_buf_size)
557 tx_tail = 0;
558 }
559 writel(tx_data, i2c_dev->base +
560 I2C_SLV_TX_FIFO);
561 bytes_remain -= bytes_in_curr_word;
562 }
563 i2c_dev->curr_packet_tx_tail = tx_tail;
564 i2c_dev->is_dummy_char_cycle = false;
565 } else {
566 i2c_dev->curr_packet_tx_tail = i2c_dev->tx_msg_tail;
567 for (i = 0; i < empty_slots; i++)
568 writel(i2c_dev->dummy_word,
569 i2c_dev->base + I2C_SLV_TX_FIFO);
570 i2c_dev->is_dummy_char_cycle = true;
571 }
572
573 i2c_dev->curr_transfer = TRANSFER_STATE_WRITE;
574 i2c_dev->int_mask &= ~I2C_INT_SLV_TFIFO_DATA_REQ;
575 i2c_dev->int_mask |= I2C_SLV_TRANS_END;
576 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
577 } else {
578 dev_err(i2c_dev->dev, "I2cSlaveIsr(): Illegal transfer at "
579 "this point\n");
580 BUG();
581 }
582}
583
584static void handle_tx_interrupt(struct tegra_i2c_slave_dev *i2c_dev)
585{
586 if (i2c_dev->cont_status & I2C_SLV_TRANS_END)
587 handle_tx_transaction_end(i2c_dev);
588 else
589 handle_tx_trigger_int(i2c_dev);
590}
591
592static irqreturn_t tegra_i2c_slave_isr(int irq, void *dev_id)
593{
594 struct tegra_i2c_slave_dev *i2c_dev = dev_id;
595 unsigned long flags;
596
597 /* Read the Interrupt status register & PKT_STATUS */
598 i2c_dev->cont_status = readl(i2c_dev->base + I2C_INT_STATUS);
599
600 dev_dbg(i2c_dev->dev, "ISR ContStatus 0x%08x\n", i2c_dev->cont_status);
601 spin_lock_irqsave(&i2c_dev->lock, flags);
602
603 if ((i2c_dev->cont_status & I2C_INT_STATUS_RX_DATA_AVAILABLE) ||
604 (i2c_dev->curr_transfer == TRANSFER_STATE_READ)) {
605 handle_rx_interrupt(i2c_dev);
606 goto Done;
607 }
608
609 if ((i2c_dev->cont_status & I2C_INT_STATUS_TX_BUFFER_REQUEST) ||
610 (i2c_dev->curr_transfer == TRANSFER_STATE_WRITE)) {
611 handle_tx_interrupt(i2c_dev);
612 goto Done;
613 }
614
615 dev_err(i2c_dev->dev, "Tegra I2c Slave got unwanted interrupt "
616 "IntStatus 0x%08x\n", i2c_dev->cont_status);
617 BUG();
618
619Done:
620 spin_unlock_irqrestore(&i2c_dev->lock, flags);
621 return IRQ_HANDLED;
622}
623
624static int tegra_i2c_slave_start(struct i2c_slave_adapter *slv_adap, int addr,
625 int is_ten_bit_addr, unsigned char dummy_char)
626{
627 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
628 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
629 unsigned long flags;
630
631 spin_lock_irqsave(&i2c_dev->lock, flags);
632 if (i2c_dev->is_slave_started) {
633 spin_unlock_irqrestore(&i2c_dev->lock, flags);
634 return -EBUSY;
635 }
636
637 i2c_dev->rx_msg_buff = (u8 *)(i2c_dev+1);
638 i2c_dev->rx_msg_head = 0;
639 i2c_dev->rx_msg_tail = 0;
640 i2c_dev->is_rx_waiting = false;
641
642 i2c_dev->tx_msg_head = 0;
643 i2c_dev->tx_msg_tail = 0;
644 i2c_dev->is_tx_waiting = true;
645
646 i2c_dev->dummy_word = (dummy_char << 8) | dummy_char;
647 i2c_dev->dummy_word |= i2c_dev->dummy_word << 16;
648
649 i2c_dev->slave_add = addr;
650 i2c_dev->is_ten_bit_addr = is_ten_bit_addr;
651
652 get_packet_headers(i2c_dev, 4096, 0, &i2c_dev->rx_pack_hdr1,
653 &i2c_dev->rx_pack_hdr2, &i2c_dev->rx_pack_hdr3);
654
655 pm_runtime_get_sync(i2c_dev->dev);
656 configure_i2c_slave_packet_mode(i2c_dev);
657 configure_i2c_slave_address(i2c_dev);
658 do_tx_fifo_empty(i2c_dev, NULL);
659 set_rx_trigger_level(i2c_dev, 1);
660 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
661
662 if (i2c_bus->pinmux)
663 tegra_pinmux_config_tristate_table(i2c_bus->pinmux,
664 i2c_bus->mux_len, TEGRA_TRI_NORMAL);
665
666 i2c_dev->curr_transfer = 0;
667 i2c_dev->is_slave_started = true;
668 i2c_dev->int_mask = I2C_SLV_DEFAULT_INT_MASK;
669 i2c_dev->is_first_byte_read_wait = true;
670 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
671 spin_unlock_irqrestore(&i2c_dev->lock, flags);
672 return 0;
673}
674
675static void tegra_i2c_slave_stop(struct i2c_slave_adapter *slv_adap,
676 int is_buffer_clear)
677{
678 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
679 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
680 unsigned long flags;
681
682 spin_lock_irqsave(&i2c_dev->lock, flags);
683 if (!i2c_dev->is_slave_started) {
684 spin_unlock_irqrestore(&i2c_dev->lock, flags);
685 return;
686 }
687
688 i2c_dev->slave_add = 0;
689 i2c_dev->is_ten_bit_addr = false;
690 configure_i2c_slave_address(i2c_dev);
691 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
692 writel(0, i2c_dev->base + I2C_INT_MASK);
693 i2c_dev->curr_transfer = 0;
694 i2c_dev->is_slave_started = false;
695 pm_runtime_put_sync(i2c_dev->dev);
696 if (is_buffer_clear) {
697 i2c_dev->rx_msg_head = 0;
698 i2c_dev->rx_msg_tail = 0;
699 i2c_dev->is_rx_waiting = false;
700 i2c_dev->tx_msg_head = 0;
701 i2c_dev->tx_msg_tail = 0;
702 i2c_dev->is_tx_waiting = false;
703 }
704 if (i2c_bus->pinmux)
705 tegra_pinmux_config_tristate_table(i2c_bus->pinmux,
706 i2c_bus->mux_len, TEGRA_TRI_TRISTATE);
707 spin_unlock_irqrestore(&i2c_dev->lock, flags);
708}
709
710static int tegra_i2c_slave_send(struct i2c_slave_adapter *slv_adap,
711 const char *buf, int count)
712{
713 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
714 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
715 unsigned long flags;
716 unsigned long space_available;
717 int i;
718
719 spin_lock_irqsave(&i2c_dev->lock, flags);
720 if (!i2c_dev->is_slave_started) {
721 spin_unlock_irqrestore(&i2c_dev->lock, flags);
722 return -EPERM;
723 }
724
725 space_available = get_space_count(i2c_dev->tx_msg_tail,
726 i2c_dev->tx_msg_head, i2c_dev->tx_msg_buf_size);
727 if (space_available < count) {
728 spin_unlock_irqrestore(&i2c_dev->lock, flags);
729 return 0;
730 }
731
732 for (i = 0; i < count; ++i) {
733 i2c_dev->tx_msg_buff[i2c_dev->tx_msg_head++] = *buf++;
734 if (i2c_dev->tx_msg_head >= i2c_dev->tx_msg_buf_size)
735 i2c_dev->tx_msg_head = 0;
736 }
737 i2c_dev->is_tx_waiting = false;
738 spin_unlock_irqrestore(&i2c_dev->lock, flags);
739 return count;
740}
741
742static int tegra_i2c_slave_get_tx_status(struct i2c_slave_adapter *slv_adap,
743 int timeout_ms)
744{
745 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
746 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
747 unsigned long flags;
748 unsigned long data_available;
749
750 spin_lock_irqsave(&i2c_dev->lock, flags);
751 if (!i2c_dev->is_slave_started) {
752 spin_unlock_irqrestore(&i2c_dev->lock, flags);
753 return -EPERM;
754 }
755
756 data_available = get_data_count(i2c_dev->tx_msg_tail,
757 i2c_dev->tx_msg_head, i2c_dev->tx_msg_buf_size);
758 if (!data_available) {
759 spin_unlock_irqrestore(&i2c_dev->lock, flags);
760 return 0;
761 }
762
763 INIT_COMPLETION(i2c_dev->tx_msg_complete);
764 if (timeout_ms)
765 i2c_dev->is_tx_waiting = true;
766 spin_unlock_irqrestore(&i2c_dev->lock, flags);
767 if (timeout_ms) {
768 wait_for_completion_timeout(&i2c_dev->tx_msg_complete,
769 to_jiffies(timeout_ms));
770 spin_lock_irqsave(&i2c_dev->lock, flags);
771 i2c_dev->is_tx_waiting = false;
772 data_available = get_data_count(i2c_dev->tx_msg_tail,
773 i2c_dev->tx_msg_head,
774 i2c_dev->tx_msg_buf_size);
775 spin_unlock_irqrestore(&i2c_dev->lock, flags);
776 if (data_available)
777 return -ETIMEDOUT;
778 }
779 return data_available;
780}
781
782/*
783 * Timeoutms = 0, MinBytesRead = 0, read without waiting.
784 * Timeoutms = 0, MinBytesRead != 0, block till min bytes read.
785 * Timeoutms != 0, wait till timeout to read data..
786 * Timeoutms = INF, wait till all req bytes read.
787 */
788
789static int tegra_i2c_slave_recv(struct i2c_slave_adapter *slv_adap, char *buf,
790 int count, int min_count, int timeout_ms)
791{
792 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
793 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
794 unsigned long flags;
795 int data_available;
796 int bytes_copy;
797 int i;
798 int read_count = 0;
799 bool is_inf_wait = false;
800 int run_count = 0;
801
802 spin_lock_irqsave(&i2c_dev->lock, flags);
803 if (!i2c_dev->is_slave_started) {
804 spin_unlock_irqrestore(&i2c_dev->lock, flags);
805 return -EPERM;
806 }
807
808 do {
809 data_available = get_data_count(i2c_dev->rx_msg_tail,
810 i2c_dev->rx_msg_head, i2c_dev->rx_msg_buf_size);
811
812 bytes_copy = min(data_available, count);
813
814 if (!data_available) {
815 spin_unlock_irqrestore(&i2c_dev->lock, flags);
816 return 0;
817 }
818 for (i = 0; i < bytes_copy; ++i) {
819 *buf++ = i2c_dev->rx_msg_buff[i2c_dev->rx_msg_tail++];
820 if (i2c_dev->rx_msg_tail >= i2c_dev->rx_msg_buf_size)
821 i2c_dev->rx_msg_tail = 0;
822 read_count++;
823 }
824 if (!timeout_ms) {
825 if ((!min_count) || (read_count >= min_count))
826 break;
827 is_inf_wait = true;
828 } else {
829 if ((read_count == count) || run_count)
830 break;
831 }
832 i2c_dev->is_rx_waiting = true;
833 INIT_COMPLETION(i2c_dev->rx_msg_complete);
834 spin_unlock_irqrestore(&i2c_dev->lock, flags);
835 if (is_inf_wait)
836 wait_for_completion(&i2c_dev->rx_msg_complete);
837 else
838 wait_for_completion_timeout(&i2c_dev->rx_msg_complete,
839 to_jiffies(timeout_ms));
840
841 spin_lock_irqsave(&i2c_dev->lock, flags);
842 } while (1);
843 spin_unlock_irqrestore(&i2c_dev->lock, flags);
844 i2c_dev->is_rx_waiting = false;
845 return read_count;
846}
847
848static int tegra_i2c_slave_flush_buffer(struct i2c_slave_adapter *slv_adap,
849 int is_flush_tx_buffer, int is_flush_rx_buffer)
850{
851 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
852 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
853 unsigned long flags;
854
855 spin_lock_irqsave(&i2c_dev->lock, flags);
856 if (!i2c_dev->is_slave_started) {
857 spin_unlock_irqrestore(&i2c_dev->lock, flags);
858 return -EPERM;
859 }
860 if (is_flush_tx_buffer) {
861 i2c_dev->tx_msg_head = 0;
862 i2c_dev->tx_msg_tail = 0;
863 }
864 if (is_flush_rx_buffer) {
865 i2c_dev->rx_msg_head = 0;
866 i2c_dev->rx_msg_tail = 0;
867 }
868 spin_unlock_irqrestore(&i2c_dev->lock, flags);
869 return 0;
870}
871
872static int tegra_i2c_slave_get_nack_cycle(struct i2c_slave_adapter *slv_adap,
873 int is_cout_reset)
874{
875 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
876 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
877 unsigned long flags;
878 int retval;
879
880 spin_lock_irqsave(&i2c_dev->lock, flags);
881 if (!i2c_dev->is_slave_started) {
882 spin_unlock_irqrestore(&i2c_dev->lock, flags);
883 dev_dbg(i2c_dev->dev, "The slave bus is already started\n");
884 return -EPERM;
885 }
886
887 retval = i2c_dev->nack_packet_count;
888 if (is_cout_reset)
889 i2c_dev->nack_packet_count = 0;
890
891 spin_unlock_irqrestore(&i2c_dev->lock, flags);
892 return retval;
893}
894
895static const struct i2c_slave_algorithm tegra_i2c_slave_algo = {
896 .slave_start = tegra_i2c_slave_start,
897 .slave_stop = tegra_i2c_slave_stop,
898 .slave_send = tegra_i2c_slave_send,
899 .slave_get_tx_status = tegra_i2c_slave_get_tx_status,
900 .slave_recv = tegra_i2c_slave_recv,
901 .slave_flush_buffer = tegra_i2c_slave_flush_buffer,
902 .slave_get_nack_cycle = tegra_i2c_slave_get_nack_cycle,
903};
904
905static int tegra_i2c_slave_probe(struct platform_device *pdev)
906{
907 struct tegra_i2c_slave_dev *i2c_dev;
908 struct tegra_i2c_slave_bus *i2c_bus = NULL;
909 struct tegra_i2c_slave_platform_data *pdata = pdev->dev.platform_data;
910 struct resource *res;
911 struct resource *iomem;
912 struct clk *clk;
913 void *base;
914 int irq;
915 int ret = 0;
916 int rx_buffer_size;
917 int tx_buffer_size;
918
919 if (!pdata) {
920 dev_err(&pdev->dev, "no platform data?\n");
921 return -ENODEV;
922 }
923
924 if (pdata->adapter_nr < 0) {
925 dev_err(&pdev->dev, "invalid platform data?\n");
926 return -ENODEV;
927 }
928
929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
930 if (!res) {
931 dev_err(&pdev->dev, "no mem resource?\n");
932 return -ENODEV;
933 }
934 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
935 if (!iomem) {
936 dev_err(&pdev->dev, "I2C region already claimed\n");
937 return -EBUSY;
938 }
939
940 base = ioremap(iomem->start, resource_size(iomem));
941 if (!base) {
942 dev_err(&pdev->dev, "Can't ioremap I2C region\n");
943 return -ENOMEM;
944 }
945
946 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
947 if (!res) {
948 dev_err(&pdev->dev, "no irq resource?\n");
949 ret = -ENODEV;
950 goto err_iounmap;
951 }
952 irq = res->start;
953
954 clk = clk_get(&pdev->dev, NULL);
955 if (!clk) {
956 ret = -ENODEV;
957 goto err_release_region;
958 }
959
960 rx_buffer_size = (pdata->max_rx_buffer_size)?:4096;
961 tx_buffer_size = (pdata->max_tx_buffer_size)?:4096;
962 i2c_dev = kzalloc(sizeof(struct tegra_i2c_slave_dev) +
963 rx_buffer_size + tx_buffer_size, GFP_KERNEL);
964 if (!i2c_dev) {
965 ret = -ENOMEM;
966 goto err_clk_put;
967 }
968
969 i2c_dev->base = base;
970 i2c_dev->clk = clk;
971 i2c_dev->iomem = iomem;
972 i2c_dev->irq = irq;
973 i2c_dev->cont_id = pdev->id;
974 i2c_dev->dev = &pdev->dev;
975 i2c_dev->bus_clk = pdata->bus_clk_rate?: 100000;
976 i2c_dev->rx_msg_buff = (u8 *)(i2c_dev+1);
977 i2c_dev->rx_msg_buf_size = rx_buffer_size;
978 i2c_dev->rx_msg_head = 0;
979 i2c_dev->rx_msg_tail = 0;
980 i2c_dev->is_rx_waiting = 0;
981 i2c_dev->tx_msg_buff = i2c_dev->rx_msg_buff + rx_buffer_size;
982 i2c_dev->tx_msg_buf_size = tx_buffer_size;
983 i2c_dev->tx_msg_head = 0;
984 i2c_dev->tx_msg_tail = 0;
985 i2c_dev->is_tx_waiting = 0;
986
987 i2c_dev->is_slave_started = false;
988 spin_lock_init(&i2c_dev->lock);
989
990 init_completion(&i2c_dev->rx_msg_complete);
991 init_completion(&i2c_dev->tx_msg_complete);
992
993 platform_set_drvdata(pdev, i2c_dev);
994
995 ret = request_irq(i2c_dev->irq, tegra_i2c_slave_isr, IRQF_DISABLED,
996 pdev->name, i2c_dev);
997 if (ret) {
998 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
999 goto err_free;
1000 }
1001
1002 i2c_bus = &i2c_dev->bus;
1003 i2c_bus->dev = i2c_dev;
1004 i2c_bus->pinmux = pdata->pinmux;
1005 i2c_bus->mux_len = pdata->bus_mux_len;
1006 i2c_bus->bus_clk_rate = pdata->bus_clk_rate ?: 100000;
1007
1008 i2c_bus->slv_adap.slv_algo = &tegra_i2c_slave_algo;
1009 i2c_bus->slv_adap.owner = THIS_MODULE;
1010 i2c_bus->slv_adap.class = I2C_CLASS_HWMON;
1011 strlcpy(i2c_bus->slv_adap.name, "Tegra I2C SLAVE adapter",
1012 sizeof(i2c_bus->slv_adap.name));
1013 i2c_bus->slv_adap.parent_dev = &pdev->dev;
1014 i2c_bus->slv_adap.dev = NULL;
1015 i2c_bus->slv_adap.nr = pdata->adapter_nr;
1016 ret = i2c_add_slave_adapter(&i2c_bus->slv_adap, true);
1017 if (ret < 0) {
1018 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
1019 goto err_free_irq;
1020 }
1021 i2c_set_slave_adapdata(&i2c_bus->slv_adap, i2c_bus);
1022 dev_dbg(&pdev->dev, "%s() suucess\n", __func__);
1023 pm_runtime_enable(i2c_dev->dev);
1024 return 0;
1025
1026err_free_irq:
1027 free_irq(i2c_dev->irq, i2c_dev);
1028err_free:
1029 kfree(i2c_dev);
1030err_clk_put:
1031 clk_put(clk);
1032err_release_region:
1033 release_mem_region(iomem->start, resource_size(iomem));
1034err_iounmap:
1035 iounmap(base);
1036 dev_dbg(&pdev->dev, "%s() failed %d\n", __func__, ret);
1037 return ret;
1038}
1039
1040static int tegra_i2c_slave_remove(struct platform_device *pdev)
1041{
1042 struct tegra_i2c_slave_dev *i2c_dev = platform_get_drvdata(pdev);
1043
1044 i2c_del_slave_adapter(&i2c_dev->bus.slv_adap);
1045 pm_runtime_disable(i2c_dev->dev);
1046 free_irq(i2c_dev->irq, i2c_dev);
1047 clk_put(i2c_dev->clk);
1048 release_mem_region(i2c_dev->iomem->start,
1049 resource_size(i2c_dev->iomem));
1050 iounmap(i2c_dev->base);
1051 kfree(i2c_dev);
1052 return 0;
1053}
1054
1055#ifdef CONFIG_PM
1056static int tegra_i2c_slave_suspend(struct platform_device *pdev,
1057 pm_message_t state)
1058{
1059 return 0;
1060}
1061
1062static int tegra_i2c_slave_resume(struct platform_device *pdev)
1063{
1064 return 0;
1065}
1066#endif
1067#if defined(CONFIG_PM_RUNTIME)
1068static int tegra_i2c_slave_runtime_idle(struct device *dev)
1069{
1070 struct platform_device *pdev = to_platform_device(dev);
1071 struct tegra_i2c_slave_dev *i2c_dev = platform_get_drvdata(pdev);
1072 clk_disable(i2c_dev->clk);
1073 return 0;
1074}
1075static int tegra_i2c_slave_runtime_resume(struct device *dev)
1076{
1077 struct platform_device *pdev = to_platform_device(dev);
1078 struct tegra_i2c_slave_dev *i2c_dev = platform_get_drvdata(pdev);
1079 clk_enable(i2c_dev->clk);
1080 return 0;
1081}
1082static const struct dev_pm_ops tegra_i2c_slave_dev_pm_ops = {
1083 .runtime_idle = tegra_i2c_slave_runtime_idle,
1084 .runtime_resume = tegra_i2c_slave_runtime_resume,
1085};
1086#endif
1087
1088static struct platform_driver tegra_i2c_slave_driver = {
1089 .probe = tegra_i2c_slave_probe,
1090 .remove = tegra_i2c_slave_remove,
1091#ifdef CONFIG_PM
1092 .suspend = tegra_i2c_slave_suspend,
1093 .resume = tegra_i2c_slave_resume,
1094#endif
1095 .driver = {
1096 .name = "tegra-i2c-slave",
1097 .owner = THIS_MODULE,
1098#if defined(CONFIG_PM_RUNTIME)
1099 .pm = &tegra_i2c_slave_dev_pm_ops,
1100#endif
1101 },
1102};
1103
1104static int __init tegra_i2c_slave_init_driver(void)
1105{
1106 return platform_driver_register(&tegra_i2c_slave_driver);
1107}
1108
1109static void __exit tegra_i2c_slave_exit_driver(void)
1110{
1111 platform_driver_unregister(&tegra_i2c_slave_driver);
1112}
1113subsys_initcall(tegra_i2c_slave_init_driver);
1114module_exit(tegra_i2c_slave_exit_driver);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 16:07:11 -0400