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-rw-r--r--drivers/i2c/busses/i2c-designware.c847
-rw-r--r--drivers/i2c/busses/i2c-ixp2000.c168
-rw-r--r--drivers/i2c/busses/i2c-slave-tegra.c1114
-rw-r--r--drivers/i2c/busses/i2c-stub.c222
4 files changed, 2351 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c
new file mode 100644
index 00000000000..b7a51c43b18
--- /dev/null
+++ b/drivers/i2c/busses/i2c-designware.c
@@ -0,0 +1,847 @@
1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
26 *
27 */
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/delay.h>
31#include <linux/i2c.h>
32#include <linux/clk.h>
33#include <linux/errno.h>
34#include <linux/sched.h>
35#include <linux/err.h>
36#include <linux/interrupt.h>
37#include <linux/platform_device.h>
38#include <linux/io.h>
39#include <linux/slab.h>
40
41/*
42 * Registers offset
43 */
44#define DW_IC_CON 0x0
45#define DW_IC_TAR 0x4
46#define DW_IC_DATA_CMD 0x10
47#define DW_IC_SS_SCL_HCNT 0x14
48#define DW_IC_SS_SCL_LCNT 0x18
49#define DW_IC_FS_SCL_HCNT 0x1c
50#define DW_IC_FS_SCL_LCNT 0x20
51#define DW_IC_INTR_STAT 0x2c
52#define DW_IC_INTR_MASK 0x30
53#define DW_IC_RAW_INTR_STAT 0x34
54#define DW_IC_RX_TL 0x38
55#define DW_IC_TX_TL 0x3c
56#define DW_IC_CLR_INTR 0x40
57#define DW_IC_CLR_RX_UNDER 0x44
58#define DW_IC_CLR_RX_OVER 0x48
59#define DW_IC_CLR_TX_OVER 0x4c
60#define DW_IC_CLR_RD_REQ 0x50
61#define DW_IC_CLR_TX_ABRT 0x54
62#define DW_IC_CLR_RX_DONE 0x58
63#define DW_IC_CLR_ACTIVITY 0x5c
64#define DW_IC_CLR_STOP_DET 0x60
65#define DW_IC_CLR_START_DET 0x64
66#define DW_IC_CLR_GEN_CALL 0x68
67#define DW_IC_ENABLE 0x6c
68#define DW_IC_STATUS 0x70
69#define DW_IC_TXFLR 0x74
70#define DW_IC_RXFLR 0x78
71#define DW_IC_COMP_PARAM_1 0xf4
72#define DW_IC_TX_ABRT_SOURCE 0x80
73
74#define DW_IC_CON_MASTER 0x1
75#define DW_IC_CON_SPEED_STD 0x2
76#define DW_IC_CON_SPEED_FAST 0x4
77#define DW_IC_CON_10BITADDR_MASTER 0x10
78#define DW_IC_CON_RESTART_EN 0x20
79#define DW_IC_CON_SLAVE_DISABLE 0x40
80
81#define DW_IC_INTR_RX_UNDER 0x001
82#define DW_IC_INTR_RX_OVER 0x002
83#define DW_IC_INTR_RX_FULL 0x004
84#define DW_IC_INTR_TX_OVER 0x008
85#define DW_IC_INTR_TX_EMPTY 0x010
86#define DW_IC_INTR_RD_REQ 0x020
87#define DW_IC_INTR_TX_ABRT 0x040
88#define DW_IC_INTR_RX_DONE 0x080
89#define DW_IC_INTR_ACTIVITY 0x100
90#define DW_IC_INTR_STOP_DET 0x200
91#define DW_IC_INTR_START_DET 0x400
92#define DW_IC_INTR_GEN_CALL 0x800
93
94#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
95 DW_IC_INTR_TX_EMPTY | \
96 DW_IC_INTR_TX_ABRT | \
97 DW_IC_INTR_STOP_DET)
98
99#define DW_IC_STATUS_ACTIVITY 0x1
100
101#define DW_IC_ERR_TX_ABRT 0x1
102
103/*
104 * status codes
105 */
106#define STATUS_IDLE 0x0
107#define STATUS_WRITE_IN_PROGRESS 0x1
108#define STATUS_READ_IN_PROGRESS 0x2
109
110#define TIMEOUT 20 /* ms */
111
112/*
113 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
114 *
115 * only expected abort codes are listed here
116 * refer to the datasheet for the full list
117 */
118#define ABRT_7B_ADDR_NOACK 0
119#define ABRT_10ADDR1_NOACK 1
120#define ABRT_10ADDR2_NOACK 2
121#define ABRT_TXDATA_NOACK 3
122#define ABRT_GCALL_NOACK 4
123#define ABRT_GCALL_READ 5
124#define ABRT_SBYTE_ACKDET 7
125#define ABRT_SBYTE_NORSTRT 9
126#define ABRT_10B_RD_NORSTRT 10
127#define ABRT_MASTER_DIS 11
128#define ARB_LOST 12
129
130#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
131#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
132#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
133#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
134#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
135#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
136#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
137#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
138#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
139#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
140#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
141
142#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
143 DW_IC_TX_ABRT_10ADDR1_NOACK | \
144 DW_IC_TX_ABRT_10ADDR2_NOACK | \
145 DW_IC_TX_ABRT_TXDATA_NOACK | \
146 DW_IC_TX_ABRT_GCALL_NOACK)
147
148static char *abort_sources[] = {
149 [ABRT_7B_ADDR_NOACK] =
150 "slave address not acknowledged (7bit mode)",
151 [ABRT_10ADDR1_NOACK] =
152 "first address byte not acknowledged (10bit mode)",
153 [ABRT_10ADDR2_NOACK] =
154 "second address byte not acknowledged (10bit mode)",
155 [ABRT_TXDATA_NOACK] =
156 "data not acknowledged",
157 [ABRT_GCALL_NOACK] =
158 "no acknowledgement for a general call",
159 [ABRT_GCALL_READ] =
160 "read after general call",
161 [ABRT_SBYTE_ACKDET] =
162 "start byte acknowledged",
163 [ABRT_SBYTE_NORSTRT] =
164 "trying to send start byte when restart is disabled",
165 [ABRT_10B_RD_NORSTRT] =
166 "trying to read when restart is disabled (10bit mode)",
167 [ABRT_MASTER_DIS] =
168 "trying to use disabled adapter",
169 [ARB_LOST] =
170 "lost arbitration",
171};
172
173/**
174 * struct dw_i2c_dev - private i2c-designware data
175 * @dev: driver model device node
176 * @base: IO registers pointer
177 * @cmd_complete: tx completion indicator
178 * @lock: protect this struct and IO registers
179 * @clk: input reference clock
180 * @cmd_err: run time hadware error code
181 * @msgs: points to an array of messages currently being transferred
182 * @msgs_num: the number of elements in msgs
183 * @msg_write_idx: the element index of the current tx message in the msgs
184 * array
185 * @tx_buf_len: the length of the current tx buffer
186 * @tx_buf: the current tx buffer
187 * @msg_read_idx: the element index of the current rx message in the msgs
188 * array
189 * @rx_buf_len: the length of the current rx buffer
190 * @rx_buf: the current rx buffer
191 * @msg_err: error status of the current transfer
192 * @status: i2c master status, one of STATUS_*
193 * @abort_source: copy of the TX_ABRT_SOURCE register
194 * @irq: interrupt number for the i2c master
195 * @adapter: i2c subsystem adapter node
196 * @tx_fifo_depth: depth of the hardware tx fifo
197 * @rx_fifo_depth: depth of the hardware rx fifo
198 */
199struct dw_i2c_dev {
200 struct device *dev;
201 void __iomem *base;
202 struct completion cmd_complete;
203 struct mutex lock;
204 struct clk *clk;
205 int cmd_err;
206 struct i2c_msg *msgs;
207 int msgs_num;
208 int msg_write_idx;
209 u32 tx_buf_len;
210 u8 *tx_buf;
211 int msg_read_idx;
212 u32 rx_buf_len;
213 u8 *rx_buf;
214 int msg_err;
215 unsigned int status;
216 u32 abort_source;
217 int irq;
218 struct i2c_adapter adapter;
219 unsigned int tx_fifo_depth;
220 unsigned int rx_fifo_depth;
221};
222
223static u32
224i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
225{
226 /*
227 * DesignWare I2C core doesn't seem to have solid strategy to meet
228 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
229 * will result in violation of the tHD;STA spec.
230 */
231 if (cond)
232 /*
233 * Conditional expression:
234 *
235 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
236 *
237 * This is based on the DW manuals, and represents an ideal
238 * configuration. The resulting I2C bus speed will be
239 * faster than any of the others.
240 *
241 * If your hardware is free from tHD;STA issue, try this one.
242 */
243 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
244 else
245 /*
246 * Conditional expression:
247 *
248 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
249 *
250 * This is just experimental rule; the tHD;STA period turned
251 * out to be proportinal to (_HCNT + 3). With this setting,
252 * we could meet both tHIGH and tHD;STA timing specs.
253 *
254 * If unsure, you'd better to take this alternative.
255 *
256 * The reason why we need to take into account "tf" here,
257 * is the same as described in i2c_dw_scl_lcnt().
258 */
259 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
260}
261
262static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
263{
264 /*
265 * Conditional expression:
266 *
267 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
268 *
269 * DW I2C core starts counting the SCL CNTs for the LOW period
270 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
271 * In order to meet the tLOW timing spec, we need to take into
272 * account the fall time of SCL signal (tf). Default tf value
273 * should be 0.3 us, for safety.
274 */
275 return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
276}
277
278/**
279 * i2c_dw_init() - initialize the designware i2c master hardware
280 * @dev: device private data
281 *
282 * This functions configures and enables the I2C master.
283 * This function is called during I2C init function, and in case of timeout at
284 * run time.
285 */
286static void i2c_dw_init(struct dw_i2c_dev *dev)
287{
288 u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
289 u32 ic_con, hcnt, lcnt;
290
291 /* Disable the adapter */
292 writel(0, dev->base + DW_IC_ENABLE);
293
294 /* set standard and fast speed deviders for high/low periods */
295
296 /* Standard-mode */
297 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
298 40, /* tHD;STA = tHIGH = 4.0 us */
299 3, /* tf = 0.3 us */
300 0, /* 0: DW default, 1: Ideal */
301 0); /* No offset */
302 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
303 47, /* tLOW = 4.7 us */
304 3, /* tf = 0.3 us */
305 0); /* No offset */
306 writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT);
307 writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT);
308 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
309
310 /* Fast-mode */
311 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
312 6, /* tHD;STA = tHIGH = 0.6 us */
313 3, /* tf = 0.3 us */
314 0, /* 0: DW default, 1: Ideal */
315 0); /* No offset */
316 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
317 13, /* tLOW = 1.3 us */
318 3, /* tf = 0.3 us */
319 0); /* No offset */
320 writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT);
321 writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT);
322 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
323
324 /* Configure Tx/Rx FIFO threshold levels */
325 writel(dev->tx_fifo_depth - 1, dev->base + DW_IC_TX_TL);
326 writel(0, dev->base + DW_IC_RX_TL);
327
328 /* configure the i2c master */
329 ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
330 DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST;
331 writel(ic_con, dev->base + DW_IC_CON);
332}
333
334/*
335 * Waiting for bus not busy
336 */
337static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
338{
339 int timeout = TIMEOUT;
340
341 while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
342 if (timeout <= 0) {
343 dev_warn(dev->dev, "timeout waiting for bus ready\n");
344 return -ETIMEDOUT;
345 }
346 timeout--;
347 mdelay(1);
348 }
349
350 return 0;
351}
352
353static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
354{
355 struct i2c_msg *msgs = dev->msgs;
356 u32 ic_con;
357
358 /* Disable the adapter */
359 writel(0, dev->base + DW_IC_ENABLE);
360
361 /* set the slave (target) address */
362 writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
363
364 /* if the slave address is ten bit address, enable 10BITADDR */
365 ic_con = readl(dev->base + DW_IC_CON);
366 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
367 ic_con |= DW_IC_CON_10BITADDR_MASTER;
368 else
369 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
370 writel(ic_con, dev->base + DW_IC_CON);
371
372 /* Enable the adapter */
373 writel(1, dev->base + DW_IC_ENABLE);
374
375 /* Enable interrupts */
376 writel(DW_IC_INTR_DEFAULT_MASK, dev->base + DW_IC_INTR_MASK);
377}
378
379/*
380 * Initiate (and continue) low level master read/write transaction.
381 * This function is only called from i2c_dw_isr, and pumping i2c_msg
382 * messages into the tx buffer. Even if the size of i2c_msg data is
383 * longer than the size of the tx buffer, it handles everything.
384 */
385static void
386i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
387{
388 struct i2c_msg *msgs = dev->msgs;
389 u32 intr_mask;
390 int tx_limit, rx_limit;
391 u32 addr = msgs[dev->msg_write_idx].addr;
392 u32 buf_len = dev->tx_buf_len;
393 u8 *buf = dev->tx_buf;;
394
395 intr_mask = DW_IC_INTR_DEFAULT_MASK;
396
397 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
398 /*
399 * if target address has changed, we need to
400 * reprogram the target address in the i2c
401 * adapter when we are done with this transfer
402 */
403 if (msgs[dev->msg_write_idx].addr != addr) {
404 dev_err(dev->dev,
405 "%s: invalid target address\n", __func__);
406 dev->msg_err = -EINVAL;
407 break;
408 }
409
410 if (msgs[dev->msg_write_idx].len == 0) {
411 dev_err(dev->dev,
412 "%s: invalid message length\n", __func__);
413 dev->msg_err = -EINVAL;
414 break;
415 }
416
417 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
418 /* new i2c_msg */
419 buf = msgs[dev->msg_write_idx].buf;
420 buf_len = msgs[dev->msg_write_idx].len;
421 }
422
423 tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR);
424 rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR);
425
426 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
427 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
428 writel(0x100, dev->base + DW_IC_DATA_CMD);
429 rx_limit--;
430 } else
431 writel(*buf++, dev->base + DW_IC_DATA_CMD);
432 tx_limit--; buf_len--;
433 }
434
435 dev->tx_buf = buf;
436 dev->tx_buf_len = buf_len;
437
438 if (buf_len > 0) {
439 /* more bytes to be written */
440 dev->status |= STATUS_WRITE_IN_PROGRESS;
441 break;
442 } else
443 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
444 }
445
446 /*
447 * If i2c_msg index search is completed, we don't need TX_EMPTY
448 * interrupt any more.
449 */
450 if (dev->msg_write_idx == dev->msgs_num)
451 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
452
453 if (dev->msg_err)
454 intr_mask = 0;
455
456 writel(intr_mask, dev->base + DW_IC_INTR_MASK);
457}
458
459static void
460i2c_dw_read(struct dw_i2c_dev *dev)
461{
462 struct i2c_msg *msgs = dev->msgs;
463 int rx_valid;
464
465 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
466 u32 len;
467 u8 *buf;
468
469 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
470 continue;
471
472 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
473 len = msgs[dev->msg_read_idx].len;
474 buf = msgs[dev->msg_read_idx].buf;
475 } else {
476 len = dev->rx_buf_len;
477 buf = dev->rx_buf;
478 }
479
480 rx_valid = readl(dev->base + DW_IC_RXFLR);
481
482 for (; len > 0 && rx_valid > 0; len--, rx_valid--)
483 *buf++ = readl(dev->base + DW_IC_DATA_CMD);
484
485 if (len > 0) {
486 dev->status |= STATUS_READ_IN_PROGRESS;
487 dev->rx_buf_len = len;
488 dev->rx_buf = buf;
489 return;
490 } else
491 dev->status &= ~STATUS_READ_IN_PROGRESS;
492 }
493}
494
495static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
496{
497 unsigned long abort_source = dev->abort_source;
498 int i;
499
500 if (abort_source & DW_IC_TX_ABRT_NOACK) {
501 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
502 dev_dbg(dev->dev,
503 "%s: %s\n", __func__, abort_sources[i]);
504 return -EREMOTEIO;
505 }
506
507 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
508 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
509
510 if (abort_source & DW_IC_TX_ARB_LOST)
511 return -EAGAIN;
512 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
513 return -EINVAL; /* wrong msgs[] data */
514 else
515 return -EIO;
516}
517
518/*
519 * Prepare controller for a transaction and call i2c_dw_xfer_msg
520 */
521static int
522i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
523{
524 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
525 int ret;
526
527 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
528
529 mutex_lock(&dev->lock);
530
531 INIT_COMPLETION(dev->cmd_complete);
532 dev->msgs = msgs;
533 dev->msgs_num = num;
534 dev->cmd_err = 0;
535 dev->msg_write_idx = 0;
536 dev->msg_read_idx = 0;
537 dev->msg_err = 0;
538 dev->status = STATUS_IDLE;
539 dev->abort_source = 0;
540
541 ret = i2c_dw_wait_bus_not_busy(dev);
542 if (ret < 0)
543 goto done;
544
545 /* start the transfers */
546 i2c_dw_xfer_init(dev);
547
548 /* wait for tx to complete */
549 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
550 if (ret == 0) {
551 dev_err(dev->dev, "controller timed out\n");
552 i2c_dw_init(dev);
553 ret = -ETIMEDOUT;
554 goto done;
555 } else if (ret < 0)
556 goto done;
557
558 if (dev->msg_err) {
559 ret = dev->msg_err;
560 goto done;
561 }
562
563 /* no error */
564 if (likely(!dev->cmd_err)) {
565 /* Disable the adapter */
566 writel(0, dev->base + DW_IC_ENABLE);
567 ret = num;
568 goto done;
569 }
570
571 /* We have an error */
572 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
573 ret = i2c_dw_handle_tx_abort(dev);
574 goto done;
575 }
576 ret = -EIO;
577
578done:
579 mutex_unlock(&dev->lock);
580
581 return ret;
582}
583
584static u32 i2c_dw_func(struct i2c_adapter *adap)
585{
586 return I2C_FUNC_I2C |
587 I2C_FUNC_10BIT_ADDR |
588 I2C_FUNC_SMBUS_BYTE |
589 I2C_FUNC_SMBUS_BYTE_DATA |
590 I2C_FUNC_SMBUS_WORD_DATA |
591 I2C_FUNC_SMBUS_I2C_BLOCK;
592}
593
594static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
595{
596 u32 stat;
597
598 /*
599 * The IC_INTR_STAT register just indicates "enabled" interrupts.
600 * Ths unmasked raw version of interrupt status bits are available
601 * in the IC_RAW_INTR_STAT register.
602 *
603 * That is,
604 * stat = readl(IC_INTR_STAT);
605 * equals to,
606 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
607 *
608 * The raw version might be useful for debugging purposes.
609 */
610 stat = readl(dev->base + DW_IC_INTR_STAT);
611
612 /*
613 * Do not use the IC_CLR_INTR register to clear interrupts, or
614 * you'll miss some interrupts, triggered during the period from
615 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
616 *
617 * Instead, use the separately-prepared IC_CLR_* registers.
618 */
619 if (stat & DW_IC_INTR_RX_UNDER)
620 readl(dev->base + DW_IC_CLR_RX_UNDER);
621 if (stat & DW_IC_INTR_RX_OVER)
622 readl(dev->base + DW_IC_CLR_RX_OVER);
623 if (stat & DW_IC_INTR_TX_OVER)
624 readl(dev->base + DW_IC_CLR_TX_OVER);
625 if (stat & DW_IC_INTR_RD_REQ)
626 readl(dev->base + DW_IC_CLR_RD_REQ);
627 if (stat & DW_IC_INTR_TX_ABRT) {
628 /*
629 * The IC_TX_ABRT_SOURCE register is cleared whenever
630 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
631 */
632 dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE);
633 readl(dev->base + DW_IC_CLR_TX_ABRT);
634 }
635 if (stat & DW_IC_INTR_RX_DONE)
636 readl(dev->base + DW_IC_CLR_RX_DONE);
637 if (stat & DW_IC_INTR_ACTIVITY)
638 readl(dev->base + DW_IC_CLR_ACTIVITY);
639 if (stat & DW_IC_INTR_STOP_DET)
640 readl(dev->base + DW_IC_CLR_STOP_DET);
641 if (stat & DW_IC_INTR_START_DET)
642 readl(dev->base + DW_IC_CLR_START_DET);
643 if (stat & DW_IC_INTR_GEN_CALL)
644 readl(dev->base + DW_IC_CLR_GEN_CALL);
645
646 return stat;
647}
648
649/*
650 * Interrupt service routine. This gets called whenever an I2C interrupt
651 * occurs.
652 */
653static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
654{
655 struct dw_i2c_dev *dev = dev_id;
656 u32 stat;
657
658 stat = i2c_dw_read_clear_intrbits(dev);
659 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
660
661 if (stat & DW_IC_INTR_TX_ABRT) {
662 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
663 dev->status = STATUS_IDLE;
664
665 /*
666 * Anytime TX_ABRT is set, the contents of the tx/rx
667 * buffers are flushed. Make sure to skip them.
668 */
669 writel(0, dev->base + DW_IC_INTR_MASK);
670 goto tx_aborted;
671 }
672
673 if (stat & DW_IC_INTR_RX_FULL)
674 i2c_dw_read(dev);
675
676 if (stat & DW_IC_INTR_TX_EMPTY)
677 i2c_dw_xfer_msg(dev);
678
679 /*
680 * No need to modify or disable the interrupt mask here.
681 * i2c_dw_xfer_msg() will take care of it according to
682 * the current transmit status.
683 */
684
685tx_aborted:
686 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
687 complete(&dev->cmd_complete);
688
689 return IRQ_HANDLED;
690}
691
692static struct i2c_algorithm i2c_dw_algo = {
693 .master_xfer = i2c_dw_xfer,
694 .functionality = i2c_dw_func,
695};
696
697static int __devinit dw_i2c_probe(struct platform_device *pdev)
698{
699 struct dw_i2c_dev *dev;
700 struct i2c_adapter *adap;
701 struct resource *mem, *ioarea;
702 int irq, r;
703
704 /* NOTE: driver uses the static register mapping */
705 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
706 if (!mem) {
707 dev_err(&pdev->dev, "no mem resource?\n");
708 return -EINVAL;
709 }
710
711 irq = platform_get_irq(pdev, 0);
712 if (irq < 0) {
713 dev_err(&pdev->dev, "no irq resource?\n");
714 return irq; /* -ENXIO */
715 }
716
717 ioarea = request_mem_region(mem->start, resource_size(mem),
718 pdev->name);
719 if (!ioarea) {
720 dev_err(&pdev->dev, "I2C region already claimed\n");
721 return -EBUSY;
722 }
723
724 dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
725 if (!dev) {
726 r = -ENOMEM;
727 goto err_release_region;
728 }
729
730 init_completion(&dev->cmd_complete);
731 mutex_init(&dev->lock);
732 dev->dev = get_device(&pdev->dev);
733 dev->irq = irq;
734 platform_set_drvdata(pdev, dev);
735
736 dev->clk = clk_get(&pdev->dev, NULL);
737 if (IS_ERR(dev->clk)) {
738 r = -ENODEV;
739 goto err_free_mem;
740 }
741 clk_enable(dev->clk);
742
743 dev->base = ioremap(mem->start, resource_size(mem));
744 if (dev->base == NULL) {
745 dev_err(&pdev->dev, "failure mapping io resources\n");
746 r = -EBUSY;
747 goto err_unuse_clocks;
748 }
749 {
750 u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1);
751
752 dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1;
753 dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1;
754 }
755 i2c_dw_init(dev);
756
757 writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */
758 r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev);
759 if (r) {
760 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
761 goto err_iounmap;
762 }
763
764 adap = &dev->adapter;
765 i2c_set_adapdata(adap, dev);
766 adap->owner = THIS_MODULE;
767 adap->class = I2C_CLASS_HWMON;
768 strlcpy(adap->name, "Synopsys DesignWare I2C adapter",
769 sizeof(adap->name));
770 adap->algo = &i2c_dw_algo;
771 adap->dev.parent = &pdev->dev;
772
773 adap->nr = pdev->id;
774 r = i2c_add_numbered_adapter(adap);
775 if (r) {
776 dev_err(&pdev->dev, "failure adding adapter\n");
777 goto err_free_irq;
778 }
779
780 return 0;
781
782err_free_irq:
783 free_irq(dev->irq, dev);
784err_iounmap:
785 iounmap(dev->base);
786err_unuse_clocks:
787 clk_disable(dev->clk);
788 clk_put(dev->clk);
789 dev->clk = NULL;
790err_free_mem:
791 platform_set_drvdata(pdev, NULL);
792 put_device(&pdev->dev);
793 kfree(dev);
794err_release_region:
795 release_mem_region(mem->start, resource_size(mem));
796
797 return r;
798}
799
800static int __devexit dw_i2c_remove(struct platform_device *pdev)
801{
802 struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
803 struct resource *mem;
804
805 platform_set_drvdata(pdev, NULL);
806 i2c_del_adapter(&dev->adapter);
807 put_device(&pdev->dev);
808
809 clk_disable(dev->clk);
810 clk_put(dev->clk);
811 dev->clk = NULL;
812
813 writel(0, dev->base + DW_IC_ENABLE);
814 free_irq(dev->irq, dev);
815 kfree(dev);
816
817 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 release_mem_region(mem->start, resource_size(mem));
819 return 0;
820}
821
822/* work with hotplug and coldplug */
823MODULE_ALIAS("platform:i2c_designware");
824
825static struct platform_driver dw_i2c_driver = {
826 .remove = __devexit_p(dw_i2c_remove),
827 .driver = {
828 .name = "i2c_designware",
829 .owner = THIS_MODULE,
830 },
831};
832
833static int __init dw_i2c_init_driver(void)
834{
835 return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe);
836}
837module_init(dw_i2c_init_driver);
838
839static void __exit dw_i2c_exit_driver(void)
840{
841 platform_driver_unregister(&dw_i2c_driver);
842}
843module_exit(dw_i2c_exit_driver);
844
845MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
846MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
847MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-ixp2000.c b/drivers/i2c/busses/i2c-ixp2000.c
new file mode 100644
index 00000000000..5d8aed5ec21
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ixp2000.c
@@ -0,0 +1,168 @@
1/*
2 * drivers/i2c/busses/i2c-ixp2000.c
3 *
4 * I2C adapter for IXP2000 systems using GPIOs for I2C bus
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 * Based on IXDP2400 code by: Naeem M. Afzal <naeem.m.afzal@intel.com>
8 * Made generic by: Jeff Daly <jeffrey.daly@intel.com>
9 *
10 * Copyright (c) 2003-2004 MontaVista Software Inc.
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 *
16 * From Jeff Daly:
17 *
18 * I2C adapter driver for Intel IXDP2xxx platforms. This should work for any
19 * IXP2000 platform if it uses the HW GPIO in the same manner. Basically,
20 * SDA and SCL GPIOs have external pullups. Setting the respective GPIO to
21 * an input will make the signal a '1' via the pullup. Setting them to
22 * outputs will pull them down.
23 *
24 * The GPIOs are open drain signals and are used as configuration strap inputs
25 * during power-up so there's generally a buffer on the board that needs to be
26 * 'enabled' to drive the GPIOs.
27 */
28
29#include <linux/kernel.h>
30#include <linux/init.h>
31#include <linux/platform_device.h>
32#include <linux/module.h>
33#include <linux/i2c.h>
34#include <linux/i2c-algo-bit.h>
35#include <linux/slab.h>
36
37#include <mach/hardware.h> /* Pick up IXP2000-specific bits */
38#include <mach/gpio.h>
39
40static inline int ixp2000_scl_pin(void *data)
41{
42 return ((struct ixp2000_i2c_pins*)data)->scl_pin;
43}
44
45static inline int ixp2000_sda_pin(void *data)
46{
47 return ((struct ixp2000_i2c_pins*)data)->sda_pin;
48}
49
50
51static void ixp2000_bit_setscl(void *data, int val)
52{
53 int i = 5000;
54
55 if (val) {
56 gpio_line_config(ixp2000_scl_pin(data), GPIO_IN);
57 while(!gpio_line_get(ixp2000_scl_pin(data)) && i--);
58 } else {
59 gpio_line_config(ixp2000_scl_pin(data), GPIO_OUT);
60 }
61}
62
63static void ixp2000_bit_setsda(void *data, int val)
64{
65 if (val) {
66 gpio_line_config(ixp2000_sda_pin(data), GPIO_IN);
67 } else {
68 gpio_line_config(ixp2000_sda_pin(data), GPIO_OUT);
69 }
70}
71
72static int ixp2000_bit_getscl(void *data)
73{
74 return gpio_line_get(ixp2000_scl_pin(data));
75}
76
77static int ixp2000_bit_getsda(void *data)
78{
79 return gpio_line_get(ixp2000_sda_pin(data));
80}
81
82struct ixp2000_i2c_data {
83 struct ixp2000_i2c_pins *gpio_pins;
84 struct i2c_adapter adapter;
85 struct i2c_algo_bit_data algo_data;
86};
87
88static int ixp2000_i2c_remove(struct platform_device *plat_dev)
89{
90 struct ixp2000_i2c_data *drv_data = platform_get_drvdata(plat_dev);
91
92 platform_set_drvdata(plat_dev, NULL);
93
94 i2c_del_adapter(&drv_data->adapter);
95
96 kfree(drv_data);
97
98 return 0;
99}
100
101static int ixp2000_i2c_probe(struct platform_device *plat_dev)
102{
103 int err;
104 struct ixp2000_i2c_pins *gpio = plat_dev->dev.platform_data;
105 struct ixp2000_i2c_data *drv_data =
106 kzalloc(sizeof(struct ixp2000_i2c_data), GFP_KERNEL);
107
108 if (!drv_data)
109 return -ENOMEM;
110 drv_data->gpio_pins = gpio;
111
112 drv_data->algo_data.data = gpio;
113 drv_data->algo_data.setsda = ixp2000_bit_setsda;
114 drv_data->algo_data.setscl = ixp2000_bit_setscl;
115 drv_data->algo_data.getsda = ixp2000_bit_getsda;
116 drv_data->algo_data.getscl = ixp2000_bit_getscl;
117 drv_data->algo_data.udelay = 6;
118 drv_data->algo_data.timeout = HZ;
119
120 strlcpy(drv_data->adapter.name, plat_dev->dev.driver->name,
121 sizeof(drv_data->adapter.name));
122 drv_data->adapter.algo_data = &drv_data->algo_data,
123
124 drv_data->adapter.dev.parent = &plat_dev->dev;
125
126 gpio_line_config(gpio->sda_pin, GPIO_IN);
127 gpio_line_config(gpio->scl_pin, GPIO_IN);
128 gpio_line_set(gpio->scl_pin, 0);
129 gpio_line_set(gpio->sda_pin, 0);
130
131 if ((err = i2c_bit_add_bus(&drv_data->adapter)) != 0) {
132 dev_err(&plat_dev->dev, "Could not install, error %d\n", err);
133 kfree(drv_data);
134 return err;
135 }
136
137 platform_set_drvdata(plat_dev, drv_data);
138
139 return 0;
140}
141
142static struct platform_driver ixp2000_i2c_driver = {
143 .probe = ixp2000_i2c_probe,
144 .remove = ixp2000_i2c_remove,
145 .driver = {
146 .name = "IXP2000-I2C",
147 .owner = THIS_MODULE,
148 },
149};
150
151static int __init ixp2000_i2c_init(void)
152{
153 return platform_driver_register(&ixp2000_i2c_driver);
154}
155
156static void __exit ixp2000_i2c_exit(void)
157{
158 platform_driver_unregister(&ixp2000_i2c_driver);
159}
160
161module_init(ixp2000_i2c_init);
162module_exit(ixp2000_i2c_exit);
163
164MODULE_AUTHOR ("Deepak Saxena <dsaxena@plexity.net>");
165MODULE_DESCRIPTION("IXP2000 GPIO-based I2C bus driver");
166MODULE_LICENSE("GPL");
167MODULE_ALIAS("platform:IXP2000-I2C");
168
diff --git a/drivers/i2c/busses/i2c-slave-tegra.c b/drivers/i2c/busses/i2c-slave-tegra.c
new file mode 100644
index 00000000000..f2468d85c1f
--- /dev/null
+++ b/drivers/i2c/busses/i2c-slave-tegra.c
@@ -0,0 +1,1114 @@
1/*
2 * drivers/i2c/busses/i2c-slave-tegra.c
3 * I2c slave driver for the Nvidia's tegra SOC.
4 *
5 * Copyright (c) 2009-2011, NVIDIA Corporation.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18/*#define DEBUG 1*/
19/*#define VERBOSE_DEBUG 1*/
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/clk.h>
25#include <linux/i2c.h>
26#include <linux/io.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/slab.h>
30#include <linux/spinlock.h>
31#include <linux/i2c-tegra.h>
32#include <linux/i2c-slave.h>
33#include <asm/unaligned.h>
34#include <mach/clk.h>
35#include <mach/pinmux.h>
36#include <linux/pm_runtime.h>
37#define BYTES_PER_FIFO_WORD 4
38#define to_jiffies(msecs) msecs_to_jiffies(msecs)
39
40#define I2C_CNFG 0x000
41#define I2C_CNFG_PACKET_MODE_EN (1<<10)
42#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
43#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
44#define I2C_CNFG_DEBOUNCE_CNT_MASK (0x7)
45
46#define I2C_STATUS 0x01C
47
48#define I2C_SLV_CNFG 0x020
49#define I2C_SLV_CNFG_NEWSL (1<<2)
50#define I2C_SLV_CNFG_ENABLE_SL (1<<3)
51#define I2C_SLV_CNFG_PKT_MODE_EN (1<<4)
52#define I2C_SLV_CNFG_FIFO_XFER_EN (1<<20)
53#define I2C_SLV_CNFG_ACK_LAST_BYTE (1<<6)
54#define I2C_SLV_CNFG_ACK_LAST_BYTE_VALID (1<<7)
55
56#define I2C_SLV_ADDR1 0x02c
57#define I2C_SLV_ADDR1_ADDR_SHIFT 0x0
58
59#define I2C_SLV_ADDR2 0x030
60#define I2C_SLV_ADDR2_ADDR0_HI_SHIFT 0x1
61#define I2C_SLV_ADDR2_ADDR0_MASK 0x7
62#define I2C_SLV_ADDR2_ADDR0_TEN_BIT_ADDR_MODE 0x1
63
64#define I2C_SLV_INT_MASK 0x040
65
66#define I2C_TX_FIFO 0x050
67#define I2C_RX_FIFO 0x054
68#define I2C_PACKET_TRANSFER_STATUS 0x058
69
70#define I2C_FIFO_CONTROL 0x05c
71#define I2C_FIFO_CONTROL_SLV_TX_FLUSH (1<<9)
72#define I2C_FIFO_CONTROL_SLV_RX_FLUSH (1<<8)
73#define I2C_FIFO_CONTROL_SLV_TX_TRIG_SHIFT 13
74#define I2C_FIFO_CONTROL_SLV_TX_TRIG_MASK (0x7 << 13)
75#define I2C_FIFO_CONTROL_SLV_RX_TRIG_SHIFT 10
76#define I2C_FIFO_CONTROL_SLV_RX_TRIG_MASK (1 << 10)
77
78#define I2C_FIFO_STATUS 0x060
79#define I2C_FIFO_STATUS_SLV_TX_MASK (0xF << 20)
80#define I2C_FIFO_STATUS_SLV_TX_SHIFT 20
81#define I2C_FIFO_STATUS_SLV_RX_MASK (0x0F << 16)
82#define I2C_FIFO_STATUS_SLV_RX_SHIFT 16
83
84#define I2C_INT_MASK 0x064
85#define I2C_INT_STATUS 0x068
86#define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
87#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
88#define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
89#define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
90#define I2C_INT_NO_ACK (1<<3)
91#define I2C_INT_ARBITRATION_LOST (1<<2)
92#define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
93#define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
94
95#define I2C_INT_SLV_PKT_XFER_ERR (1 << 25)
96#define I2C_INT_SLV_TX_BUFFER_REQ (1 << 24)
97#define I2C_INT_SLV_RX_BUFFER_FILLED (1 << 23)
98#define I2C_INT_SLV_PACKET_XFER_COMPLETE (1 << 22)
99#define I2C_INT_SLV_TFIFO_OVF_REQ (1 << 21)
100#define I2C_INT_SLV_RFIFO_UNF_REQ (1 << 20)
101#define I2C_INT_SLV_TFIFO_DATA_REQ (1 << 17)
102#define I2C_INT_SLV_RFIFO_DATA_REQ (1 << 16)
103
104#define I2C_SLV_TX_FIFO 0x078
105#define I2C_SLV_RX_FIFO 0x07c
106
107#define I2C_SLV_PACKET_STATUS 0x80
108#define I2C_SLV_PACKET_STATUS_BYTENUM_SHIFT 4
109#define I2C_SLV_PACKET_STATUS_BYTENUM_MASK 0xFFF0
110
111#define I2C_CLK_DIVISOR 0x06c
112
113#define DVC_CTRL_REG1 0x000
114#define DVC_CTRL_REG1_INTR_EN (1<<10)
115#define DVC_CTRL_REG2 0x004
116#define DVC_CTRL_REG3 0x008
117#define DVC_CTRL_REG3_SW_PROG (1<<26)
118#define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
119#define DVC_STATUS 0x00c
120#define DVC_STATUS_I2C_DONE_INTR (1<<30)
121
122#define I2C_ERR_NONE 0x00
123#define I2C_ERR_NO_ACK 0x01
124#define I2C_ERR_ARBITRATION_LOST 0x02
125#define I2C_ERR_UNKNOWN_INTERRUPT 0x04
126
127#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
128#define PACKET_HEADER0_PACKET_ID_SHIFT 16
129#define PACKET_HEADER0_CONT_ID_SHIFT 12
130#define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
131
132#define I2C_HEADER_HIGHSPEED_MODE (1<<22)
133#define I2C_HEADER_CONT_ON_NAK (1<<21)
134#define I2C_HEADER_SEND_START_BYTE (1<<20)
135#define I2C_HEADER_READ (1<<19)
136#define I2C_HEADER_10BIT_ADDR (1<<18)
137#define I2C_HEADER_IE_ENABLE (1<<17)
138#define I2C_HEADER_REPEAT_START (1<<16)
139#define I2C_HEADER_MASTER_ADDR_SHIFT 12
140#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
141
142#define I2C_FIFO_DEPTH 8
143/* Transfer state of the i2c slave */
144#define TRANSFER_STATE_NONE 0
145#define TRANSFER_STATE_READ 1
146#define TRANSFER_STATE_WRITE 2
147
148#define I2C_SLV_TRANS_PREMATURE_END I2C_INT_SLV_PKT_XFER_ERR
149
150#define I2C_SLV_TRANS_ALL_XFER_END I2C_INT_SLV_PACKET_XFER_COMPLETE
151
152#define I2C_SLV_TRANS_END \
153 (I2C_INT_SLV_PKT_XFER_ERR | I2C_INT_SLV_PACKET_XFER_COMPLETE)
154
155#define I2C_INT_STATUS_RX_BUFFER_FILLED I2C_INT_SLV_RX_BUFFER_FILLED
156
157#define I2C_INT_STATUS_RX_DATA_AVAILABLE \
158 (I2C_INT_SLV_RX_BUFFER_FILLED | I2C_INT_SLV_RFIFO_DATA_REQ)
159
160#define I2C_INT_STATUS_TX_BUFFER_REQUEST \
161 (I2C_INT_SLV_TX_BUFFER_REQ | I2C_INT_SLV_TFIFO_DATA_REQ)
162
163#define I2C_SLV_ERRORS_INT_MASK (I2C_INT_SLV_TFIFO_OVF_REQ | \
164 I2C_INT_SLV_RFIFO_UNF_REQ | I2C_INT_SLV_PKT_XFER_ERR)
165
166#define I2C_SLV_DEFAULT_INT_MASK (I2C_INT_SLV_TFIFO_OVF_REQ | \
167 I2C_INT_SLV_RFIFO_UNF_REQ | I2C_INT_SLV_PKT_XFER_ERR | \
168 I2C_INT_SLV_RX_BUFFER_FILLED | I2C_INT_SLV_TX_BUFFER_REQ)
169
170struct tegra_i2c_slave_dev;
171
172struct tegra_i2c_slave_bus {
173 struct tegra_i2c_slave_dev *dev;
174 const struct tegra_pingroup_config *pinmux;
175 int mux_len;
176 unsigned long bus_clk_rate;
177 struct i2c_slave_adapter slv_adap;
178};
179
180struct tegra_i2c_slave_dev {
181 struct device *dev;
182 struct clk *clk;
183 struct resource *iomem;
184 void __iomem *base;
185 int cont_id;
186 int irq;
187 spinlock_t lock;
188 struct completion rx_msg_complete;
189 struct completion tx_msg_complete;
190 bool is_rx_waiting;
191 bool is_tx_waiting;
192 u8 *rx_msg_buff;
193 int rx_msg_buf_size;
194 int rx_msg_head;
195 int rx_msg_tail;
196 u8 *tx_msg_buff;
197 int tx_msg_buf_size;
198 int tx_msg_head;
199 int tx_msg_tail;
200 bool is_slave_started;
201 int slave_add;
202 bool is_ten_bit_addr;
203 u32 dummy_word;
204 unsigned long rx_pack_hdr1;
205 unsigned long rx_pack_hdr2;
206 unsigned long rx_pack_hdr3;
207 int curr_transfer;
208 unsigned long int_mask;
209 int nack_packet_count;
210 bool is_first_byte_read_wait;
211 int curr_packet_bytes_read;
212 unsigned int cont_status;
213 bool is_dummy_char_cycle;
214 unsigned long curr_packet_tx_tail;
215 const struct tegra_pingroup_config *pin_mux;
216 int bus_clk;
217 struct tegra_i2c_slave_bus bus;
218};
219
220#define get_space_count(rInd, wInd, maxsize) \
221 (((wInd > rInd) ? (maxsize - wInd + rInd) : (rInd - wInd)) - 1)
222
223#define get_data_count(rInd, wInd, maxsize) \
224 ((wInd >= rInd) ? (wInd - rInd) : (maxsize - rInd + wInd - 1))
225
226static void set_tx_trigger_level(struct tegra_i2c_slave_dev *i2c_dev, int trig)
227{
228 unsigned long fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
229 if (trig) {
230 fifo_control &= ~I2C_FIFO_CONTROL_SLV_TX_TRIG_MASK;
231 fifo_control |= (trig-1) << I2C_FIFO_CONTROL_SLV_TX_TRIG_SHIFT;
232 writel(fifo_control, i2c_dev->base + I2C_FIFO_CONTROL);
233 }
234}
235
236static void set_rx_trigger_level(struct tegra_i2c_slave_dev *i2c_dev, int trig)
237{
238 unsigned long fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
239 if (trig) {
240 fifo_control &= ~I2C_FIFO_CONTROL_SLV_RX_TRIG_MASK;
241 fifo_control |= (trig-1) << I2C_FIFO_CONTROL_SLV_RX_TRIG_SHIFT;
242 writel(fifo_control, i2c_dev->base + I2C_FIFO_CONTROL);
243 }
244}
245
246static void reset_slave_tx_fifo(struct tegra_i2c_slave_dev *i2c_dev)
247{
248 unsigned long fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
249 unsigned long timeout_count = 1000;
250
251 writel(fifo_control | I2C_FIFO_CONTROL_SLV_TX_FLUSH,
252 i2c_dev->base + I2C_FIFO_CONTROL);
253 while (timeout_count--) {
254 fifo_control = readl(i2c_dev->base + I2C_FIFO_CONTROL);
255 if (!(fifo_control & I2C_FIFO_CONTROL_SLV_TX_FLUSH))
256 break;
257 udelay(1);
258 }
259 if (!timeout_count) {
260 dev_err(i2c_dev->dev, "Not able to flush tx fifo\n");
261 BUG();
262 }
263}
264
265static void do_tx_fifo_empty(struct tegra_i2c_slave_dev *i2c_dev,
266 unsigned long *empty_count)
267{
268 unsigned long fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
269 unsigned long tx_fifo_empty_count;
270
271 tx_fifo_empty_count = (fifo_status & I2C_FIFO_STATUS_SLV_TX_MASK) >>
272 I2C_FIFO_STATUS_SLV_TX_SHIFT;
273 if (tx_fifo_empty_count < I2C_FIFO_DEPTH)
274 reset_slave_tx_fifo(i2c_dev);
275 if (empty_count)
276 *empty_count = tx_fifo_empty_count;
277}
278
279static void get_packet_headers(struct tegra_i2c_slave_dev *i2c_dev, u32 msg_len,
280 u32 flags, unsigned long *packet_header1,
281 unsigned long *packet_header2, unsigned long *packet_header3)
282{
283 unsigned long packet_header;
284 *packet_header1 = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
285 PACKET_HEADER0_PROTOCOL_I2C |
286 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
287 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
288 *packet_header2 = msg_len-1;
289 if (i2c_dev->is_ten_bit_addr)
290 packet_header = i2c_dev->slave_add | I2C_HEADER_10BIT_ADDR;
291 else
292 packet_header = i2c_dev->slave_add <<
293 I2C_HEADER_SLAVE_ADDR_SHIFT;
294
295 if (flags & I2C_M_RD)
296 packet_header |= I2C_HEADER_READ;
297
298 *packet_header3 = packet_header;
299}
300
301static void configure_i2c_slave_packet_mode(struct tegra_i2c_slave_dev *i2c_dev)
302{
303 unsigned long i2c_config;
304 i2c_config = I2C_CNFG_PACKET_MODE_EN | I2C_CNFG_NEW_MASTER_FSM;
305 i2c_config |= (2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
306 writel(i2c_config, i2c_dev->base + I2C_CNFG);
307}
308
309static void configure_i2c_slave_address(struct tegra_i2c_slave_dev *i2c_dev)
310{
311
312 unsigned long slave_add_reg;
313 unsigned long i2c_slv_config;
314 unsigned long slave_add;
315
316 if (i2c_dev->is_ten_bit_addr) {
317 slave_add = i2c_dev->slave_add & 0xFF;
318 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR1);
319 slave_add_reg &= ~(0xFF);
320 slave_add_reg |= slave_add << I2C_SLV_ADDR1_ADDR_SHIFT;
321 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR1);
322
323 slave_add = (i2c_dev->slave_add >> 8) & 0x3;
324 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR2);
325 slave_add_reg &= ~I2C_SLV_ADDR2_ADDR0_MASK;
326 slave_add_reg |= slave_add |
327 I2C_SLV_ADDR2_ADDR0_TEN_BIT_ADDR_MODE;
328 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR2);
329 } else {
330 slave_add = (i2c_dev->slave_add & 0x3FF);
331 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR1);
332 slave_add_reg &= ~(0x3FF);
333 slave_add_reg |= slave_add << I2C_SLV_ADDR1_ADDR_SHIFT;
334 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR1);
335
336 slave_add_reg = readl(i2c_dev->base + I2C_SLV_ADDR2);
337 slave_add_reg &= ~I2C_SLV_ADDR2_ADDR0_MASK;
338 writel(slave_add_reg, i2c_dev->base + I2C_SLV_ADDR2);
339 }
340
341 i2c_slv_config = I2C_SLV_CNFG_NEWSL;
342 if (i2c_dev->slave_add) {
343 i2c_slv_config = I2C_SLV_CNFG_ENABLE_SL |
344 I2C_SLV_CNFG_PKT_MODE_EN |
345 I2C_SLV_CNFG_FIFO_XFER_EN;
346 }
347 writel(i2c_slv_config, i2c_dev->base + I2C_SLV_CNFG);
348}
349
350static void copy_rx_data(struct tegra_i2c_slave_dev *i2c_dev, u8 rcv_char)
351{
352 if (get_space_count(i2c_dev->rx_msg_tail, i2c_dev->rx_msg_head,
353 i2c_dev->rx_msg_buf_size)){
354 i2c_dev->rx_msg_buff[i2c_dev->rx_msg_head++] = rcv_char;
355 if (i2c_dev->rx_msg_head == i2c_dev->rx_msg_buf_size)
356 i2c_dev->rx_msg_head = 0;
357 } else {
358 dev_warn(i2c_dev->dev, "The slave rx buffer is full, ignoring "
359 "new receive data\n");
360 }
361}
362
363static void handle_packet_first_byte_read(struct tegra_i2c_slave_dev *i2c_dev)
364{
365 unsigned long fifo_status;
366 int filled_slots;
367 unsigned long i2c_sl_config;
368 unsigned long recv_data;
369
370 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
371 filled_slots = (fifo_status & I2C_FIFO_STATUS_SLV_RX_MASK) >>
372 I2C_FIFO_STATUS_SLV_RX_SHIFT;
373
374 writel(I2C_INT_STATUS_RX_DATA_AVAILABLE,
375 i2c_dev->base + I2C_INT_STATUS);
376 if (unlikely(filled_slots != 1)) {
377 dev_err(i2c_dev->dev, "Unexpected number of filed slots %d",
378 filled_slots);
379 BUG();
380 }
381 recv_data = readl(i2c_dev->base + I2C_SLV_RX_FIFO);
382 copy_rx_data(i2c_dev, (u8)recv_data);
383
384 i2c_dev->is_first_byte_read_wait = false;
385 i2c_dev->curr_transfer = TRANSFER_STATE_READ;
386 i2c_dev->curr_packet_bytes_read = 0;
387
388 /* Write packet Header */
389 writel(i2c_dev->rx_pack_hdr1, i2c_dev->base + I2C_SLV_TX_FIFO);
390 writel(i2c_dev->rx_pack_hdr2, i2c_dev->base + I2C_SLV_TX_FIFO);
391 writel(i2c_dev->rx_pack_hdr3, i2c_dev->base + I2C_SLV_TX_FIFO);
392
393 set_rx_trigger_level(i2c_dev, 4);
394 i2c_dev->int_mask |= I2C_INT_SLV_RFIFO_DATA_REQ;
395 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
396
397 /* Ack the master */
398 i2c_sl_config = readl(i2c_dev->base + I2C_SLV_CNFG);
399 i2c_sl_config |= I2C_SLV_CNFG_ACK_LAST_BYTE |
400 I2C_SLV_CNFG_ACK_LAST_BYTE_VALID;
401 writel(i2c_sl_config, i2c_dev->base + I2C_SLV_CNFG);
402}
403
404static void handle_packet_byte_read(struct tegra_i2c_slave_dev *i2c_dev)
405{
406 unsigned long fifo_status;
407 int i, j;
408 int filled_slots;
409 unsigned long recv_data;
410 int curr_xfer_size;
411
412 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
413 filled_slots = (fifo_status & I2C_FIFO_STATUS_SLV_RX_MASK) >>
414 I2C_FIFO_STATUS_SLV_RX_SHIFT;
415
416 curr_xfer_size = BYTES_PER_FIFO_WORD * filled_slots;
417 if (i2c_dev->cont_status & I2C_SLV_TRANS_PREMATURE_END) {
418 curr_xfer_size = readl(i2c_dev->base + I2C_SLV_PACKET_STATUS);
419 curr_xfer_size =
420 (curr_xfer_size & I2C_SLV_PACKET_STATUS_BYTENUM_MASK) >>
421 I2C_SLV_PACKET_STATUS_BYTENUM_SHIFT;
422
423 BUG_ON(filled_slots != ((curr_xfer_size -
424 i2c_dev->curr_packet_bytes_read + 3) >> 2));
425 curr_xfer_size -= i2c_dev->curr_packet_bytes_read;
426 }
427
428 i2c_dev->curr_packet_bytes_read += curr_xfer_size;
429 for (i = 0; i < filled_slots; ++i) {
430 recv_data = readl(i2c_dev->base + I2C_SLV_RX_FIFO);
431 for (j = 0; j < BYTES_PER_FIFO_WORD; ++j) {
432 copy_rx_data(i2c_dev, (u8)(recv_data >> j*8));
433 curr_xfer_size--;
434 if (!curr_xfer_size)
435 break;
436 }
437 }
438 if (i2c_dev->cont_status & I2C_SLV_TRANS_PREMATURE_END) {
439 writel(I2C_SLV_TRANS_END | I2C_INT_STATUS_RX_BUFFER_FILLED,
440 i2c_dev->base + I2C_INT_STATUS);
441
442 i2c_dev->is_first_byte_read_wait = true;
443 i2c_dev->curr_transfer = TRANSFER_STATE_NONE;
444 i2c_dev->curr_packet_bytes_read = 0;
445 set_rx_trigger_level(i2c_dev, 1);
446 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
447 i2c_dev->int_mask = I2C_SLV_DEFAULT_INT_MASK;
448 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
449 }
450}
451
452static void handle_rx_interrupt(struct tegra_i2c_slave_dev *i2c_dev)
453{
454 if (i2c_dev->is_first_byte_read_wait)
455 handle_packet_first_byte_read(i2c_dev);
456 else
457 handle_packet_byte_read(i2c_dev);
458
459 if (i2c_dev->is_rx_waiting) {
460 complete(&i2c_dev->rx_msg_complete);
461 i2c_dev->is_rx_waiting = false;
462 }
463}
464
465static void handle_tx_transaction_end(struct tegra_i2c_slave_dev *i2c_dev)
466{
467 unsigned long curr_packet_size;
468
469 i2c_dev->curr_transfer = TRANSFER_STATE_NONE;
470 curr_packet_size = readl(i2c_dev->base + I2C_SLV_PACKET_STATUS);
471 curr_packet_size =
472 (curr_packet_size & I2C_SLV_PACKET_STATUS_BYTENUM_MASK) >>
473 I2C_SLV_PACKET_STATUS_BYTENUM_SHIFT;
474
475 /* Get transfer count from request size.*/
476 if ((curr_packet_size == 0) &&
477 (i2c_dev->cont_status & I2C_SLV_TRANS_ALL_XFER_END) &&
478 (!(i2c_dev->cont_status & I2C_SLV_TRANS_PREMATURE_END))) {
479 if (!i2c_dev->is_dummy_char_cycle)
480 i2c_dev->tx_msg_tail = i2c_dev->curr_packet_tx_tail;
481 } else {
482 if (!i2c_dev->is_dummy_char_cycle) {
483 i2c_dev->tx_msg_tail += curr_packet_size;
484 if (i2c_dev->tx_msg_tail >= i2c_dev->tx_msg_buf_size)
485 i2c_dev->tx_msg_tail -=
486 i2c_dev->tx_msg_buf_size;
487 }
488 }
489 writel(I2C_SLV_TRANS_END, i2c_dev->base + I2C_INT_STATUS);
490
491 i2c_dev->curr_transfer = TRANSFER_STATE_NONE;
492 set_tx_trigger_level(i2c_dev, 1);
493 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
494 i2c_dev->int_mask = I2C_SLV_DEFAULT_INT_MASK;
495 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
496 if (i2c_dev->is_tx_waiting) {
497 complete(&i2c_dev->tx_msg_complete);
498 i2c_dev->is_tx_waiting = false;
499 }
500}
501
502static void handle_tx_trigger_int(struct tegra_i2c_slave_dev *i2c_dev)
503{
504 unsigned long fifo_status;
505 int empty_slots;
506 int i, j;
507 int data_available;
508 unsigned long header1, header2, header3;
509 unsigned long tx_data;
510 int word_to_write;
511 int bytes_remain;
512 int bytes_in_curr_word;
513 int tx_tail;
514 int packet_len;
515
516 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
517 empty_slots = (fifo_status & I2C_FIFO_STATUS_SLV_TX_MASK) >>
518 I2C_FIFO_STATUS_SLV_TX_SHIFT;
519 BUG_ON(empty_slots <= 3);
520 if (i2c_dev->curr_transfer == TRANSFER_STATE_NONE) {
521 empty_slots -= 3;
522
523 /* Clear the tfifo request. */
524 writel(I2C_INT_STATUS_TX_BUFFER_REQUEST,
525 i2c_dev->base + I2C_INT_STATUS);
526
527 /* Get Number of bytes it can transfer in current */
528 data_available = get_data_count(i2c_dev->tx_msg_tail,
529 i2c_dev->tx_msg_head, i2c_dev->tx_msg_buf_size);
530 if (data_available)
531 packet_len = min(empty_slots*BYTES_PER_FIFO_WORD,
532 data_available);
533 else
534 packet_len = empty_slots*BYTES_PER_FIFO_WORD;
535
536 get_packet_headers(i2c_dev, packet_len, I2C_M_RD,
537 &header1, &header2, &header3);
538
539 /* Write packet Header */
540 writel(header1, i2c_dev->base + I2C_SLV_TX_FIFO);
541 writel(header2, i2c_dev->base + I2C_SLV_TX_FIFO);
542 writel(header3, i2c_dev->base + I2C_SLV_TX_FIFO);
543
544 fifo_status = readl(i2c_dev->base + I2C_FIFO_STATUS);
545 if (data_available) {
546 word_to_write = (packet_len + 3) >> 2;
547 bytes_remain = packet_len;
548 tx_tail = i2c_dev->tx_msg_tail;
549 for (i = 0; i < word_to_write; i++) {
550 bytes_in_curr_word =
551 min(bytes_remain, BYTES_PER_FIFO_WORD);
552 tx_data = 0;
553 for (j = 0; j < bytes_in_curr_word; ++j) {
554 tx_data |= (i2c_dev->tx_msg_buff[
555 tx_tail++]<<(j*8));
556 if (tx_tail >= i2c_dev->tx_msg_buf_size)
557 tx_tail = 0;
558 }
559 writel(tx_data, i2c_dev->base +
560 I2C_SLV_TX_FIFO);
561 bytes_remain -= bytes_in_curr_word;
562 }
563 i2c_dev->curr_packet_tx_tail = tx_tail;
564 i2c_dev->is_dummy_char_cycle = false;
565 } else {
566 i2c_dev->curr_packet_tx_tail = i2c_dev->tx_msg_tail;
567 for (i = 0; i < empty_slots; i++)
568 writel(i2c_dev->dummy_word,
569 i2c_dev->base + I2C_SLV_TX_FIFO);
570 i2c_dev->is_dummy_char_cycle = true;
571 }
572
573 i2c_dev->curr_transfer = TRANSFER_STATE_WRITE;
574 i2c_dev->int_mask &= ~I2C_INT_SLV_TFIFO_DATA_REQ;
575 i2c_dev->int_mask |= I2C_SLV_TRANS_END;
576 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
577 } else {
578 dev_err(i2c_dev->dev, "I2cSlaveIsr(): Illegal transfer at "
579 "this point\n");
580 BUG();
581 }
582}
583
584static void handle_tx_interrupt(struct tegra_i2c_slave_dev *i2c_dev)
585{
586 if (i2c_dev->cont_status & I2C_SLV_TRANS_END)
587 handle_tx_transaction_end(i2c_dev);
588 else
589 handle_tx_trigger_int(i2c_dev);
590}
591
592static irqreturn_t tegra_i2c_slave_isr(int irq, void *dev_id)
593{
594 struct tegra_i2c_slave_dev *i2c_dev = dev_id;
595 unsigned long flags;
596
597 /* Read the Interrupt status register & PKT_STATUS */
598 i2c_dev->cont_status = readl(i2c_dev->base + I2C_INT_STATUS);
599
600 dev_dbg(i2c_dev->dev, "ISR ContStatus 0x%08x\n", i2c_dev->cont_status);
601 spin_lock_irqsave(&i2c_dev->lock, flags);
602
603 if ((i2c_dev->cont_status & I2C_INT_STATUS_RX_DATA_AVAILABLE) ||
604 (i2c_dev->curr_transfer == TRANSFER_STATE_READ)) {
605 handle_rx_interrupt(i2c_dev);
606 goto Done;
607 }
608
609 if ((i2c_dev->cont_status & I2C_INT_STATUS_TX_BUFFER_REQUEST) ||
610 (i2c_dev->curr_transfer == TRANSFER_STATE_WRITE)) {
611 handle_tx_interrupt(i2c_dev);
612 goto Done;
613 }
614
615 dev_err(i2c_dev->dev, "Tegra I2c Slave got unwanted interrupt "
616 "IntStatus 0x%08x\n", i2c_dev->cont_status);
617 BUG();
618
619Done:
620 spin_unlock_irqrestore(&i2c_dev->lock, flags);
621 return IRQ_HANDLED;
622}
623
624static int tegra_i2c_slave_start(struct i2c_slave_adapter *slv_adap, int addr,
625 int is_ten_bit_addr, unsigned char dummy_char)
626{
627 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
628 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
629 unsigned long flags;
630
631 spin_lock_irqsave(&i2c_dev->lock, flags);
632 if (i2c_dev->is_slave_started) {
633 spin_unlock_irqrestore(&i2c_dev->lock, flags);
634 return -EBUSY;
635 }
636
637 i2c_dev->rx_msg_buff = (u8 *)(i2c_dev+1);
638 i2c_dev->rx_msg_head = 0;
639 i2c_dev->rx_msg_tail = 0;
640 i2c_dev->is_rx_waiting = false;
641
642 i2c_dev->tx_msg_head = 0;
643 i2c_dev->tx_msg_tail = 0;
644 i2c_dev->is_tx_waiting = true;
645
646 i2c_dev->dummy_word = (dummy_char << 8) | dummy_char;
647 i2c_dev->dummy_word |= i2c_dev->dummy_word << 16;
648
649 i2c_dev->slave_add = addr;
650 i2c_dev->is_ten_bit_addr = is_ten_bit_addr;
651
652 get_packet_headers(i2c_dev, 4096, 0, &i2c_dev->rx_pack_hdr1,
653 &i2c_dev->rx_pack_hdr2, &i2c_dev->rx_pack_hdr3);
654
655 pm_runtime_get_sync(i2c_dev->dev);
656 configure_i2c_slave_packet_mode(i2c_dev);
657 configure_i2c_slave_address(i2c_dev);
658 do_tx_fifo_empty(i2c_dev, NULL);
659 set_rx_trigger_level(i2c_dev, 1);
660 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
661
662 if (i2c_bus->pinmux)
663 tegra_pinmux_config_tristate_table(i2c_bus->pinmux,
664 i2c_bus->mux_len, TEGRA_TRI_NORMAL);
665
666 i2c_dev->curr_transfer = 0;
667 i2c_dev->is_slave_started = true;
668 i2c_dev->int_mask = I2C_SLV_DEFAULT_INT_MASK;
669 i2c_dev->is_first_byte_read_wait = true;
670 writel(i2c_dev->int_mask, i2c_dev->base + I2C_INT_MASK);
671 spin_unlock_irqrestore(&i2c_dev->lock, flags);
672 return 0;
673}
674
675static void tegra_i2c_slave_stop(struct i2c_slave_adapter *slv_adap,
676 int is_buffer_clear)
677{
678 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
679 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
680 unsigned long flags;
681
682 spin_lock_irqsave(&i2c_dev->lock, flags);
683 if (!i2c_dev->is_slave_started) {
684 spin_unlock_irqrestore(&i2c_dev->lock, flags);
685 return;
686 }
687
688 i2c_dev->slave_add = 0;
689 i2c_dev->is_ten_bit_addr = false;
690 configure_i2c_slave_address(i2c_dev);
691 writel(0, i2c_dev->base + I2C_SLV_INT_MASK);
692 writel(0, i2c_dev->base + I2C_INT_MASK);
693 i2c_dev->curr_transfer = 0;
694 i2c_dev->is_slave_started = false;
695 pm_runtime_put_sync(i2c_dev->dev);
696 if (is_buffer_clear) {
697 i2c_dev->rx_msg_head = 0;
698 i2c_dev->rx_msg_tail = 0;
699 i2c_dev->is_rx_waiting = false;
700 i2c_dev->tx_msg_head = 0;
701 i2c_dev->tx_msg_tail = 0;
702 i2c_dev->is_tx_waiting = false;
703 }
704 if (i2c_bus->pinmux)
705 tegra_pinmux_config_tristate_table(i2c_bus->pinmux,
706 i2c_bus->mux_len, TEGRA_TRI_TRISTATE);
707 spin_unlock_irqrestore(&i2c_dev->lock, flags);
708}
709
710static int tegra_i2c_slave_send(struct i2c_slave_adapter *slv_adap,
711 const char *buf, int count)
712{
713 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
714 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
715 unsigned long flags;
716 unsigned long space_available;
717 int i;
718
719 spin_lock_irqsave(&i2c_dev->lock, flags);
720 if (!i2c_dev->is_slave_started) {
721 spin_unlock_irqrestore(&i2c_dev->lock, flags);
722 return -EPERM;
723 }
724
725 space_available = get_space_count(i2c_dev->tx_msg_tail,
726 i2c_dev->tx_msg_head, i2c_dev->tx_msg_buf_size);
727 if (space_available < count) {
728 spin_unlock_irqrestore(&i2c_dev->lock, flags);
729 return 0;
730 }
731
732 for (i = 0; i < count; ++i) {
733 i2c_dev->tx_msg_buff[i2c_dev->tx_msg_head++] = *buf++;
734 if (i2c_dev->tx_msg_head >= i2c_dev->tx_msg_buf_size)
735 i2c_dev->tx_msg_head = 0;
736 }
737 i2c_dev->is_tx_waiting = false;
738 spin_unlock_irqrestore(&i2c_dev->lock, flags);
739 return count;
740}
741
742static int tegra_i2c_slave_get_tx_status(struct i2c_slave_adapter *slv_adap,
743 int timeout_ms)
744{
745 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
746 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
747 unsigned long flags;
748 unsigned long data_available;
749
750 spin_lock_irqsave(&i2c_dev->lock, flags);
751 if (!i2c_dev->is_slave_started) {
752 spin_unlock_irqrestore(&i2c_dev->lock, flags);
753 return -EPERM;
754 }
755
756 data_available = get_data_count(i2c_dev->tx_msg_tail,
757 i2c_dev->tx_msg_head, i2c_dev->tx_msg_buf_size);
758 if (!data_available) {
759 spin_unlock_irqrestore(&i2c_dev->lock, flags);
760 return 0;
761 }
762
763 INIT_COMPLETION(i2c_dev->tx_msg_complete);
764 if (timeout_ms)
765 i2c_dev->is_tx_waiting = true;
766 spin_unlock_irqrestore(&i2c_dev->lock, flags);
767 if (timeout_ms) {
768 wait_for_completion_timeout(&i2c_dev->tx_msg_complete,
769 to_jiffies(timeout_ms));
770 spin_lock_irqsave(&i2c_dev->lock, flags);
771 i2c_dev->is_tx_waiting = false;
772 data_available = get_data_count(i2c_dev->tx_msg_tail,
773 i2c_dev->tx_msg_head,
774 i2c_dev->tx_msg_buf_size);
775 spin_unlock_irqrestore(&i2c_dev->lock, flags);
776 if (data_available)
777 return -ETIMEDOUT;
778 }
779 return data_available;
780}
781
782/*
783 * Timeoutms = 0, MinBytesRead = 0, read without waiting.
784 * Timeoutms = 0, MinBytesRead != 0, block till min bytes read.
785 * Timeoutms != 0, wait till timeout to read data..
786 * Timeoutms = INF, wait till all req bytes read.
787 */
788
789static int tegra_i2c_slave_recv(struct i2c_slave_adapter *slv_adap, char *buf,
790 int count, int min_count, int timeout_ms)
791{
792 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
793 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
794 unsigned long flags;
795 int data_available;
796 int bytes_copy;
797 int i;
798 int read_count = 0;
799 bool is_inf_wait = false;
800 int run_count = 0;
801
802 spin_lock_irqsave(&i2c_dev->lock, flags);
803 if (!i2c_dev->is_slave_started) {
804 spin_unlock_irqrestore(&i2c_dev->lock, flags);
805 return -EPERM;
806 }
807
808 do {
809 data_available = get_data_count(i2c_dev->rx_msg_tail,
810 i2c_dev->rx_msg_head, i2c_dev->rx_msg_buf_size);
811
812 bytes_copy = min(data_available, count);
813
814 if (!data_available) {
815 spin_unlock_irqrestore(&i2c_dev->lock, flags);
816 return 0;
817 }
818 for (i = 0; i < bytes_copy; ++i) {
819 *buf++ = i2c_dev->rx_msg_buff[i2c_dev->rx_msg_tail++];
820 if (i2c_dev->rx_msg_tail >= i2c_dev->rx_msg_buf_size)
821 i2c_dev->rx_msg_tail = 0;
822 read_count++;
823 }
824 if (!timeout_ms) {
825 if ((!min_count) || (read_count >= min_count))
826 break;
827 is_inf_wait = true;
828 } else {
829 if ((read_count == count) || run_count)
830 break;
831 }
832 i2c_dev->is_rx_waiting = true;
833 INIT_COMPLETION(i2c_dev->rx_msg_complete);
834 spin_unlock_irqrestore(&i2c_dev->lock, flags);
835 if (is_inf_wait)
836 wait_for_completion(&i2c_dev->rx_msg_complete);
837 else
838 wait_for_completion_timeout(&i2c_dev->rx_msg_complete,
839 to_jiffies(timeout_ms));
840
841 spin_lock_irqsave(&i2c_dev->lock, flags);
842 } while (1);
843 spin_unlock_irqrestore(&i2c_dev->lock, flags);
844 i2c_dev->is_rx_waiting = false;
845 return read_count;
846}
847
848static int tegra_i2c_slave_flush_buffer(struct i2c_slave_adapter *slv_adap,
849 int is_flush_tx_buffer, int is_flush_rx_buffer)
850{
851 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
852 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
853 unsigned long flags;
854
855 spin_lock_irqsave(&i2c_dev->lock, flags);
856 if (!i2c_dev->is_slave_started) {
857 spin_unlock_irqrestore(&i2c_dev->lock, flags);
858 return -EPERM;
859 }
860 if (is_flush_tx_buffer) {
861 i2c_dev->tx_msg_head = 0;
862 i2c_dev->tx_msg_tail = 0;
863 }
864 if (is_flush_rx_buffer) {
865 i2c_dev->rx_msg_head = 0;
866 i2c_dev->rx_msg_tail = 0;
867 }
868 spin_unlock_irqrestore(&i2c_dev->lock, flags);
869 return 0;
870}
871
872static int tegra_i2c_slave_get_nack_cycle(struct i2c_slave_adapter *slv_adap,
873 int is_cout_reset)
874{
875 struct tegra_i2c_slave_bus *i2c_bus = i2c_get_slave_adapdata(slv_adap);
876 struct tegra_i2c_slave_dev *i2c_dev = i2c_bus->dev;
877 unsigned long flags;
878 int retval;
879
880 spin_lock_irqsave(&i2c_dev->lock, flags);
881 if (!i2c_dev->is_slave_started) {
882 spin_unlock_irqrestore(&i2c_dev->lock, flags);
883 dev_dbg(i2c_dev->dev, "The slave bus is already started\n");
884 return -EPERM;
885 }
886
887 retval = i2c_dev->nack_packet_count;
888 if (is_cout_reset)
889 i2c_dev->nack_packet_count = 0;
890
891 spin_unlock_irqrestore(&i2c_dev->lock, flags);
892 return retval;
893}
894
895static const struct i2c_slave_algorithm tegra_i2c_slave_algo = {
896 .slave_start = tegra_i2c_slave_start,
897 .slave_stop = tegra_i2c_slave_stop,
898 .slave_send = tegra_i2c_slave_send,
899 .slave_get_tx_status = tegra_i2c_slave_get_tx_status,
900 .slave_recv = tegra_i2c_slave_recv,
901 .slave_flush_buffer = tegra_i2c_slave_flush_buffer,
902 .slave_get_nack_cycle = tegra_i2c_slave_get_nack_cycle,
903};
904
905static int tegra_i2c_slave_probe(struct platform_device *pdev)
906{
907 struct tegra_i2c_slave_dev *i2c_dev;
908 struct tegra_i2c_slave_bus *i2c_bus = NULL;
909 struct tegra_i2c_slave_platform_data *pdata = pdev->dev.platform_data;
910 struct resource *res;
911 struct resource *iomem;
912 struct clk *clk;
913 void *base;
914 int irq;
915 int ret = 0;
916 int rx_buffer_size;
917 int tx_buffer_size;
918
919 if (!pdata) {
920 dev_err(&pdev->dev, "no platform data?\n");
921 return -ENODEV;
922 }
923
924 if (pdata->adapter_nr < 0) {
925 dev_err(&pdev->dev, "invalid platform data?\n");
926 return -ENODEV;
927 }
928
929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
930 if (!res) {
931 dev_err(&pdev->dev, "no mem resource?\n");
932 return -ENODEV;
933 }
934 iomem = request_mem_region(res->start, resource_size(res), pdev->name);
935 if (!iomem) {
936 dev_err(&pdev->dev, "I2C region already claimed\n");
937 return -EBUSY;
938 }
939
940 base = ioremap(iomem->start, resource_size(iomem));
941 if (!base) {
942 dev_err(&pdev->dev, "Can't ioremap I2C region\n");
943 return -ENOMEM;
944 }
945
946 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
947 if (!res) {
948 dev_err(&pdev->dev, "no irq resource?\n");
949 ret = -ENODEV;
950 goto err_iounmap;
951 }
952 irq = res->start;
953
954 clk = clk_get(&pdev->dev, NULL);
955 if (!clk) {
956 ret = -ENODEV;
957 goto err_release_region;
958 }
959
960 rx_buffer_size = (pdata->max_rx_buffer_size)?:4096;
961 tx_buffer_size = (pdata->max_tx_buffer_size)?:4096;
962 i2c_dev = kzalloc(sizeof(struct tegra_i2c_slave_dev) +
963 rx_buffer_size + tx_buffer_size, GFP_KERNEL);
964 if (!i2c_dev) {
965 ret = -ENOMEM;
966 goto err_clk_put;
967 }
968
969 i2c_dev->base = base;
970 i2c_dev->clk = clk;
971 i2c_dev->iomem = iomem;
972 i2c_dev->irq = irq;
973 i2c_dev->cont_id = pdev->id;
974 i2c_dev->dev = &pdev->dev;
975 i2c_dev->bus_clk = pdata->bus_clk_rate?: 100000;
976 i2c_dev->rx_msg_buff = (u8 *)(i2c_dev+1);
977 i2c_dev->rx_msg_buf_size = rx_buffer_size;
978 i2c_dev->rx_msg_head = 0;
979 i2c_dev->rx_msg_tail = 0;
980 i2c_dev->is_rx_waiting = 0;
981 i2c_dev->tx_msg_buff = i2c_dev->rx_msg_buff + rx_buffer_size;
982 i2c_dev->tx_msg_buf_size = tx_buffer_size;
983 i2c_dev->tx_msg_head = 0;
984 i2c_dev->tx_msg_tail = 0;
985 i2c_dev->is_tx_waiting = 0;
986
987 i2c_dev->is_slave_started = false;
988 spin_lock_init(&i2c_dev->lock);
989
990 init_completion(&i2c_dev->rx_msg_complete);
991 init_completion(&i2c_dev->tx_msg_complete);
992
993 platform_set_drvdata(pdev, i2c_dev);
994
995 ret = request_irq(i2c_dev->irq, tegra_i2c_slave_isr, IRQF_DISABLED,
996 pdev->name, i2c_dev);
997 if (ret) {
998 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
999 goto err_free;
1000 }
1001
1002 i2c_bus = &i2c_dev->bus;
1003 i2c_bus->dev = i2c_dev;
1004 i2c_bus->pinmux = pdata->pinmux;
1005 i2c_bus->mux_len = pdata->bus_mux_len;
1006 i2c_bus->bus_clk_rate = pdata->bus_clk_rate ?: 100000;
1007
1008 i2c_bus->slv_adap.slv_algo = &tegra_i2c_slave_algo;
1009 i2c_bus->slv_adap.owner = THIS_MODULE;
1010 i2c_bus->slv_adap.class = I2C_CLASS_HWMON;
1011 strlcpy(i2c_bus->slv_adap.name, "Tegra I2C SLAVE adapter",
1012 sizeof(i2c_bus->slv_adap.name));
1013 i2c_bus->slv_adap.parent_dev = &pdev->dev;
1014 i2c_bus->slv_adap.dev = NULL;
1015 i2c_bus->slv_adap.nr = pdata->adapter_nr;
1016 ret = i2c_add_slave_adapter(&i2c_bus->slv_adap, true);
1017 if (ret < 0) {
1018 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
1019 goto err_free_irq;
1020 }
1021 i2c_set_slave_adapdata(&i2c_bus->slv_adap, i2c_bus);
1022 dev_dbg(&pdev->dev, "%s() suucess\n", __func__);
1023 pm_runtime_enable(i2c_dev->dev);
1024 return 0;
1025
1026err_free_irq:
1027 free_irq(i2c_dev->irq, i2c_dev);
1028err_free:
1029 kfree(i2c_dev);
1030err_clk_put:
1031 clk_put(clk);
1032err_release_region:
1033 release_mem_region(iomem->start, resource_size(iomem));
1034err_iounmap:
1035 iounmap(base);
1036 dev_dbg(&pdev->dev, "%s() failed %d\n", __func__, ret);
1037 return ret;
1038}
1039
1040static int tegra_i2c_slave_remove(struct platform_device *pdev)
1041{
1042 struct tegra_i2c_slave_dev *i2c_dev = platform_get_drvdata(pdev);
1043
1044 i2c_del_slave_adapter(&i2c_dev->bus.slv_adap);
1045 pm_runtime_disable(i2c_dev->dev);
1046 free_irq(i2c_dev->irq, i2c_dev);
1047 clk_put(i2c_dev->clk);
1048 release_mem_region(i2c_dev->iomem->start,
1049 resource_size(i2c_dev->iomem));
1050 iounmap(i2c_dev->base);
1051 kfree(i2c_dev);
1052 return 0;
1053}
1054
1055#ifdef CONFIG_PM
1056static int tegra_i2c_slave_suspend(struct platform_device *pdev,
1057 pm_message_t state)
1058{
1059 return 0;
1060}
1061
1062static int tegra_i2c_slave_resume(struct platform_device *pdev)
1063{
1064 return 0;
1065}
1066#endif
1067#if defined(CONFIG_PM_RUNTIME)
1068static int tegra_i2c_slave_runtime_idle(struct device *dev)
1069{
1070 struct platform_device *pdev = to_platform_device(dev);
1071 struct tegra_i2c_slave_dev *i2c_dev = platform_get_drvdata(pdev);
1072 clk_disable(i2c_dev->clk);
1073 return 0;
1074}
1075static int tegra_i2c_slave_runtime_resume(struct device *dev)
1076{
1077 struct platform_device *pdev = to_platform_device(dev);
1078 struct tegra_i2c_slave_dev *i2c_dev = platform_get_drvdata(pdev);
1079 clk_enable(i2c_dev->clk);
1080 return 0;
1081}
1082static const struct dev_pm_ops tegra_i2c_slave_dev_pm_ops = {
1083 .runtime_idle = tegra_i2c_slave_runtime_idle,
1084 .runtime_resume = tegra_i2c_slave_runtime_resume,
1085};
1086#endif
1087
1088static struct platform_driver tegra_i2c_slave_driver = {
1089 .probe = tegra_i2c_slave_probe,
1090 .remove = tegra_i2c_slave_remove,
1091#ifdef CONFIG_PM
1092 .suspend = tegra_i2c_slave_suspend,
1093 .resume = tegra_i2c_slave_resume,
1094#endif
1095 .driver = {
1096 .name = "tegra-i2c-slave",
1097 .owner = THIS_MODULE,
1098#if defined(CONFIG_PM_RUNTIME)
1099 .pm = &tegra_i2c_slave_dev_pm_ops,
1100#endif
1101 },
1102};
1103
1104static int __init tegra_i2c_slave_init_driver(void)
1105{
1106 return platform_driver_register(&tegra_i2c_slave_driver);
1107}
1108
1109static void __exit tegra_i2c_slave_exit_driver(void)
1110{
1111 platform_driver_unregister(&tegra_i2c_slave_driver);
1112}
1113subsys_initcall(tegra_i2c_slave_init_driver);
1114module_exit(tegra_i2c_slave_exit_driver);
diff --git a/drivers/i2c/busses/i2c-stub.c b/drivers/i2c/busses/i2c-stub.c
new file mode 100644
index 00000000000..b1b3447942c
--- /dev/null
+++ b/drivers/i2c/busses/i2c-stub.c
@@ -0,0 +1,222 @@
1/*
2 i2c-stub.c - I2C/SMBus chip emulator
3
4 Copyright (c) 2004 Mark M. Hoffman <mhoffman@lightlink.com>
5 Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#define DEBUG 1
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/errno.h>
29#include <linux/i2c.h>
30
31#define MAX_CHIPS 10
32#define STUB_FUNC (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | \
33 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | \
34 I2C_FUNC_SMBUS_I2C_BLOCK)
35
36static unsigned short chip_addr[MAX_CHIPS];
37module_param_array(chip_addr, ushort, NULL, S_IRUGO);
38MODULE_PARM_DESC(chip_addr,
39 "Chip addresses (up to 10, between 0x03 and 0x77)");
40
41static unsigned long functionality = STUB_FUNC;
42module_param(functionality, ulong, S_IRUGO | S_IWUSR);
43MODULE_PARM_DESC(functionality, "Override functionality bitfield");
44
45struct stub_chip {
46 u8 pointer;
47 u16 words[256]; /* Byte operations use the LSB as per SMBus
48 specification */
49};
50
51static struct stub_chip *stub_chips;
52
53/* Return negative errno on error. */
54static s32 stub_xfer(struct i2c_adapter * adap, u16 addr, unsigned short flags,
55 char read_write, u8 command, int size, union i2c_smbus_data * data)
56{
57 s32 ret;
58 int i, len;
59 struct stub_chip *chip = NULL;
60
61 /* Search for the right chip */
62 for (i = 0; i < MAX_CHIPS && chip_addr[i]; i++) {
63 if (addr == chip_addr[i]) {
64 chip = stub_chips + i;
65 break;
66 }
67 }
68 if (!chip)
69 return -ENODEV;
70
71 switch (size) {
72
73 case I2C_SMBUS_QUICK:
74 dev_dbg(&adap->dev, "smbus quick - addr 0x%02x\n", addr);
75 ret = 0;
76 break;
77
78 case I2C_SMBUS_BYTE:
79 if (read_write == I2C_SMBUS_WRITE) {
80 chip->pointer = command;
81 dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, "
82 "wrote 0x%02x.\n",
83 addr, command);
84 } else {
85 data->byte = chip->words[chip->pointer++] & 0xff;
86 dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, "
87 "read 0x%02x.\n",
88 addr, data->byte);
89 }
90
91 ret = 0;
92 break;
93
94 case I2C_SMBUS_BYTE_DATA:
95 if (read_write == I2C_SMBUS_WRITE) {
96 chip->words[command] &= 0xff00;
97 chip->words[command] |= data->byte;
98 dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, "
99 "wrote 0x%02x at 0x%02x.\n",
100 addr, data->byte, command);
101 } else {
102 data->byte = chip->words[command] & 0xff;
103 dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, "
104 "read 0x%02x at 0x%02x.\n",
105 addr, data->byte, command);
106 }
107 chip->pointer = command + 1;
108
109 ret = 0;
110 break;
111
112 case I2C_SMBUS_WORD_DATA:
113 if (read_write == I2C_SMBUS_WRITE) {
114 chip->words[command] = data->word;
115 dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, "
116 "wrote 0x%04x at 0x%02x.\n",
117 addr, data->word, command);
118 } else {
119 data->word = chip->words[command];
120 dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, "
121 "read 0x%04x at 0x%02x.\n",
122 addr, data->word, command);
123 }
124
125 ret = 0;
126 break;
127
128 case I2C_SMBUS_I2C_BLOCK_DATA:
129 len = data->block[0];
130 if (read_write == I2C_SMBUS_WRITE) {
131 for (i = 0; i < len; i++) {
132 chip->words[command + i] &= 0xff00;
133 chip->words[command + i] |= data->block[1 + i];
134 }
135 dev_dbg(&adap->dev, "i2c block data - addr 0x%02x, "
136 "wrote %d bytes at 0x%02x.\n",
137 addr, len, command);
138 } else {
139 for (i = 0; i < len; i++) {
140 data->block[1 + i] =
141 chip->words[command + i] & 0xff;
142 }
143 dev_dbg(&adap->dev, "i2c block data - addr 0x%02x, "
144 "read %d bytes at 0x%02x.\n",
145 addr, len, command);
146 }
147
148 ret = 0;
149 break;
150
151 default:
152 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command\n");
153 ret = -EOPNOTSUPP;
154 break;
155 } /* switch (size) */
156
157 return ret;
158}
159
160static u32 stub_func(struct i2c_adapter *adapter)
161{
162 return STUB_FUNC & functionality;
163}
164
165static const struct i2c_algorithm smbus_algorithm = {
166 .functionality = stub_func,
167 .smbus_xfer = stub_xfer,
168};
169
170static struct i2c_adapter stub_adapter = {
171 .owner = THIS_MODULE,
172 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
173 .algo = &smbus_algorithm,
174 .name = "SMBus stub driver",
175};
176
177static int __init i2c_stub_init(void)
178{
179 int i, ret;
180
181 if (!chip_addr[0]) {
182 printk(KERN_ERR "i2c-stub: Please specify a chip address\n");
183 return -ENODEV;
184 }
185
186 for (i = 0; i < MAX_CHIPS && chip_addr[i]; i++) {
187 if (chip_addr[i] < 0x03 || chip_addr[i] > 0x77) {
188 printk(KERN_ERR "i2c-stub: Invalid chip address "
189 "0x%02x\n", chip_addr[i]);
190 return -EINVAL;
191 }
192
193 printk(KERN_INFO "i2c-stub: Virtual chip at 0x%02x\n",
194 chip_addr[i]);
195 }
196
197 /* Allocate memory for all chips at once */
198 stub_chips = kzalloc(i * sizeof(struct stub_chip), GFP_KERNEL);
199 if (!stub_chips) {
200 printk(KERN_ERR "i2c-stub: Out of memory\n");
201 return -ENOMEM;
202 }
203
204 ret = i2c_add_adapter(&stub_adapter);
205 if (ret)
206 kfree(stub_chips);
207 return ret;
208}
209
210static void __exit i2c_stub_exit(void)
211{
212 i2c_del_adapter(&stub_adapter);
213 kfree(stub_chips);
214}
215
216MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
217MODULE_DESCRIPTION("I2C stub driver");
218MODULE_LICENSE("GPL");
219
220module_init(i2c_stub_init);
221module_exit(i2c_stub_exit);
222
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-16 20:33:32 -0500